IEMR3.cpp@ 104064

Last change on this file since 104064 was 104064, checked in by vboxsync, 14 months ago
VMM/IEM: Made the IEMTB::cUsage value the native recompilation is done at configurable. bugref:10370
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 72.2 KB

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1	/* $Id: IEMR3.cpp 104064 2024-03-26 14:53:59Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_EM
33	#define VMCPU_INCL_CPUM_GST_CTX
34	#include <VBox/vmm/iem.h>
35	#include <VBox/vmm/cpum.h>
36	#include <VBox/vmm/dbgf.h>
37	#include <VBox/vmm/mm.h>
38	#if defined(VBOX_VMM_TARGET_ARMV8)
39	# include "IEMInternal-armv8.h"
40	#else
41	# include "IEMInternal.h"
42	#endif
43	#include <VBox/vmm/vm.h>
44	#include <VBox/vmm/vmapi.h>
45	#include <VBox/err.h>
46	#ifdef VBOX_WITH_DEBUGGER
47	# include <VBox/dbg.h>
48	#endif
49
50	#include <iprt/assert.h>
51	#include <iprt/getopt.h>
52	#include <iprt/string.h>
53
54	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
55	# include "IEMN8veRecompiler.h"
56	# include "IEMThreadedFunctions.h"
57	# include "IEMInline.h"
58	#endif
59
60
61	/*********************************************************************************************************************************
62	* Internal Functions *
63	*********************************************************************************************************************************/
64	static FNDBGFINFOARGVINT iemR3InfoITlb;
65	static FNDBGFINFOARGVINT iemR3InfoDTlb;
66	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
67	static FNDBGFINFOARGVINT iemR3InfoTb;
68	#endif
69	#ifdef VBOX_WITH_DEBUGGER
70	static void iemR3RegisterDebuggerCommands(void);
71	#endif
72
73
74	#if !defined(VBOX_VMM_TARGET_ARMV8)
75	static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
76	{
77	switch (enmTargetCpu)
78	{
79	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
80	CASE_RET_STR(IEMTARGETCPU_8086);
81	CASE_RET_STR(IEMTARGETCPU_V20);
82	CASE_RET_STR(IEMTARGETCPU_186);
83	CASE_RET_STR(IEMTARGETCPU_286);
84	CASE_RET_STR(IEMTARGETCPU_386);
85	CASE_RET_STR(IEMTARGETCPU_486);
86	CASE_RET_STR(IEMTARGETCPU_PENTIUM);
87	CASE_RET_STR(IEMTARGETCPU_PPRO);
88	CASE_RET_STR(IEMTARGETCPU_CURRENT);
89	#undef CASE_RET_STR
90	default: return "Unknown";
91	}
92	}
93	#endif
94
95
96	/**
97	* Initializes the interpreted execution manager.
98	*
99	* This must be called after CPUM as we're quering information from CPUM about
100	* the guest and host CPUs.
101	*
102	* @returns VBox status code.
103	* @param pVM The cross context VM structure.
104	*/
105	VMMR3DECL(int) IEMR3Init(PVM pVM)
106	{
107	/*
108	* Read configuration.
109	*/
110	#if (!defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)) \|\| defined(VBOX_WITH_IEM_RECOMPILER)
111	PCFGMNODE const pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
112	int rc;
113	#endif
114
115	#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)
116	/** @cfgm{/IEM/CpuIdHostCall, boolean, false}
117	* Controls whether the custom VBox specific CPUID host call interface is
118	* enabled or not. */
119	# ifdef DEBUG_bird
120	rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
121	# else
122	rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
123	# endif
124	AssertLogRelRCReturn(rc, rc);
125	#endif
126
127	#ifdef VBOX_WITH_IEM_RECOMPILER
128	/** @cfgm{/IEM/MaxTbCount, uint32_t, 524288}
129	* Max number of TBs per EMT. */
130	uint32_t cMaxTbs = 0;
131	rc = CFGMR3QueryU32Def(pIem, "MaxTbCount", &cMaxTbs, _512K);
132	AssertLogRelRCReturn(rc, rc);
133	if (cMaxTbs < _16K \|\| cMaxTbs > _8M)
134	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
135	"MaxTbCount value %u (%#x) is out of range (min %u, max %u)", cMaxTbs, cMaxTbs, _16K, _8M);
136
137	/** @cfgm{/IEM/InitialTbCount, uint32_t, 32678}
138	* Initial (minimum) number of TBs per EMT in ring-3. */
139	uint32_t cInitialTbs = 0;
140	rc = CFGMR3QueryU32Def(pIem, "InitialTbCount", &cInitialTbs, RT_MIN(cMaxTbs, _32K));
141	AssertLogRelRCReturn(rc, rc);
142	if (cInitialTbs < _16K \|\| cInitialTbs > _8M)
143	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
144	"InitialTbCount value %u (%#x) is out of range (min %u, max %u)", cInitialTbs, cInitialTbs, _16K, _8M);
145
146	/* Check that the two values makes sense together. Expect user/api to do
147	the right thing or get lost. */
148	if (cInitialTbs > cMaxTbs)
149	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
150	"InitialTbCount value %u (%#x) is higher than the MaxTbCount value %u (%#x)",
151	cInitialTbs, cInitialTbs, cMaxTbs, cMaxTbs);
152
153	/** @cfgm{/IEM/MaxExecMem, uint64_t, 512 MiB}
154	* Max executable memory for recompiled code per EMT. */
155	uint64_t cbMaxExec = 0;
156	rc = CFGMR3QueryU64Def(pIem, "MaxExecMem", &cbMaxExec, _512M);
157	AssertLogRelRCReturn(rc, rc);
158	if (cbMaxExec < _1M \|\| cbMaxExec > 16*_1G64)
159	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
160	"MaxExecMem value %'RU64 (%#RX64) is out of range (min %'RU64, max %'RU64)",
161	cbMaxExec, cbMaxExec, (uint64_t)_1M, 16*_1G64);
162
163	/** @cfgm{/IEM/ExecChunkSize, uint32_t, 0 (auto)}
164	* The executable memory allocator chunk size. */
165	uint32_t cbChunkExec = 0;
166	rc = CFGMR3QueryU32Def(pIem, "ExecChunkSize", &cbChunkExec, 0);
167	AssertLogRelRCReturn(rc, rc);
168	if (cbChunkExec != 0 && cbChunkExec != UINT32_MAX && (cbChunkExec < _1M \|\| cbChunkExec > _256M))
169	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
170	"ExecChunkSize value %'RU32 (%#RX32) is out of range (min %'RU32, max %'RU32)",
171	cbChunkExec, cbChunkExec, _1M, _256M);
172
173	/** @cfgm{/IEM/InitialExecMemSize, uint64_t, 1}
174	* The initial executable memory allocator size (per EMT). The value is
175	* rounded up to the nearest chunk size, so 1 byte means one chunk. */
176	uint64_t cbInitialExec = 0;
177	rc = CFGMR3QueryU64Def(pIem, "InitialExecMemSize", &cbInitialExec, 0);
178	AssertLogRelRCReturn(rc, rc);
179	if (cbInitialExec > cbMaxExec)
180	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
181	"InitialExecMemSize value %'RU64 (%#RX64) is out of range (max %'RU64)",
182	cbInitialExec, cbInitialExec, cbMaxExec);
183
184	/** @cfgm{/IEM/NativeRecompileAtUsedCount, uint32_t, 16}
185	* The translation block use count value to do native recompilation at. */
186	uint32_t uTbNativeRecompileAtUsedCount = 16;
187	rc = CFGMR3QueryU32Def(pIem, "NativeRecompileAtUsedCount", &uTbNativeRecompileAtUsedCount, 16);
188	AssertLogRelRCReturn(rc, rc);
189
190	#endif /* VBOX_WITH_IEM_RECOMPILER*/
191
192	/*
193	* Initialize per-CPU data and register statistics.
194	*/
195	uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
196	uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
197
198	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
199	{
200	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
201	AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
202
203	pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
204	pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
205
206	/*
207	* Host and guest CPU information.
208	*/
209	if (idCpu == 0)
210	{
211	pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
212	pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
213	#if !defined(VBOX_VMM_TARGET_ARMV8)
214	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
215	\|\| pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /??/
216	? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
217	# if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
218	if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
219	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
220	else
221	# endif
222	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
223	#else
224	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
225	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
226	#endif
227
228	#if !defined(VBOX_VMM_TARGET_ARMV8) && (IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC)
229	switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
230	{
231	case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
232	case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
233	case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
234	case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
235	case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
236	case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
237	case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
238	case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
239	case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
240	default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
241	}
242	LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
243	iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
244	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
245	#else
246	LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
247	CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
248	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
249	#endif
250	}
251	else
252	{
253	pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
254	pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
255	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
256	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
257	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
258	pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
259	#endif
260	}
261
262	/*
263	* Mark all buffers free.
264	*/
265	uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
266	while (iMemMap-- > 0)
267	pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
268
269	#ifdef VBOX_WITH_IEM_RECOMPILER
270	/*
271	* Distribute recompiler configuration.
272	*/
273	pVCpu->iem.s.uTbNativeRecompileAtUsedCount = uTbNativeRecompileAtUsedCount;
274	#endif
275	}
276
277
278	#ifdef VBOX_WITH_IEM_RECOMPILER
279	/*
280	* Initialize the TB allocator and cache (/ hash table).
281	*
282	* This is done by each EMT to try get more optimal thread/numa locality of
283	* the allocations.
284	*/
285	rc = VMR3ReqCallWait(pVM, VMCPUID_ALL, (PFNRT)iemTbInit, 6,
286	pVM, cInitialTbs, cMaxTbs, cbInitialExec, cbMaxExec, cbChunkExec);
287	AssertLogRelRCReturn(rc, rc);
288	#endif
289
290	/*
291	* Register statistics.
292	*/
293	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
294	{
295	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) /* quick fix for stupid structure duplication non-sense */
296	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
297
298	STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
299	"Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
300	STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
301	"Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
302	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
303	"Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
304	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
305	"VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
306	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
307	"VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
308	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
309	"Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
310	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
311	"Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
312	STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
313	"Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
314	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
315	"Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
316	STAMR3RegisterF(pVM, &pVCpu->iem.s.cMisalignedAtomics, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
317	"Number of misaligned (for the host) atomic instructions", "/IEM/CPU%u/cMisalignedAtomics", idCpu);
318
319	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
320	"Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
321	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
322	"Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
323	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
324	"Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
325	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
326	"Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
327
328	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
329	"Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
330	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
331	"Data TLB safe read path", "/IEM/CPU%u/DataTlb-SafeReads", idCpu);
332	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeWritePath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
333	"Data TLB safe write path", "/IEM/CPU%u/DataTlb-SafeWrites", idCpu);
334	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
335	"Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
336	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
337	"Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
338
339	# ifdef VBOX_WITH_STATISTICS
340	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
341	"Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
342	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
343	"Data TLB hits", "/IEM/CPU%u/DataTlb-Hits-Other", idCpu);
344	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
345	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForStack, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
346	"Data TLB native stack access hits", "/IEM/CPU%u/DataTlb-Hits-Native-Stack", idCpu);
347	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForFetch, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
348	"Data TLB native data fetch hits", "/IEM/CPU%u/DataTlb-Hits-Native-Fetch", idCpu);
349	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForStore, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
350	"Data TLB native data store hits", "/IEM/CPU%u/DataTlb-Hits-Native-Store", idCpu);
351	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForMapped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
352	"Data TLB native mapped data hits", "/IEM/CPU%u/DataTlb-Hits-Native-Mapped", idCpu);
353	# endif
354	char szPat[128];
355	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/DataTlb-Hits-*", idCpu);
356	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat,
357	"Data TLB hits total", "/IEM/CPU%u/DataTlb-Hits", idCpu);
358
359	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/DataTlb-Safe*", idCpu);
360	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat,
361	"Data TLB actual misses", "/IEM/CPU%u/DataTlb-SafeTotal", idCpu);
362	char szVal[128];
363	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/DataTlb-SafeTotal", idCpu);
364	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/DataTlb-Hits-*", idCpu);
365	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PPM, szVal, true, szPat,
366	"Data TLB actual miss rate", "/IEM/CPU%u/DataTlb-SafeRate", idCpu);
367
368	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
369	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbMissesNewPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
370	"Code TLB native misses on new page", "/IEM/CPU%u/CodeTlb-Misses-New-Page", idCpu);
371	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbMissesNewPageWithOffset, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
372	"Code TLB native misses on new page w/ offset", "/IEM/CPU%u/CodeTlb-Misses-New-Page-With-Offset", idCpu);
373	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbHitsForNewPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
374	"Code TLB native hits on new page", "/IEM/CPU%u/CodeTlb-Hits-New-Page", idCpu);
375	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbHitsForNewPageWithOffset, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
376	"Code TLB native hits on new page /w offset", "/IEM/CPU%u/CodeTlb-Hits-New-Page-With-Offset", idCpu);
377	# endif
378	# endif
379
380	#ifdef VBOX_WITH_IEM_RECOMPILER
381	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecNative, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
382	"Executed native translation block", "/IEM/CPU%u/re/cTbExecNative", idCpu);
383	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecThreaded, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
384	"Executed threaded translation block", "/IEM/CPU%u/re/cTbExecThreaded", idCpu);
385	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbExecBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
386	"Times TB execution was interrupted/broken off", "/IEM/CPU%u/re/cTbExecBreaks", idCpu);
387
388	PIEMTBALLOCATOR const pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
389	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatAllocs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
390	"Translation block allocations", "/IEM/CPU%u/re/cTbAllocCalls", idCpu);
391	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatFrees, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
392	"Translation block frees", "/IEM/CPU%u/re/cTbFreeCalls", idCpu);
393	# ifdef VBOX_WITH_STATISTICS
394	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
395	"Time spent freeing up TBs when full at alloc", "/IEM/CPU%u/re/TbPruningAlloc", idCpu);
396	# endif
397	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPruneNative, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
398	"Time spent freeing up native TBs when out of executable memory", "/IEM/CPU%u/re/TbPruningNative", idCpu);
399	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cAllocatedChunks, STAMTYPE_U16, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
400	"Populated TB chunks", "/IEM/CPU%u/re/cTbChunks", idCpu);
401	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxChunks, STAMTYPE_U8, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
402	"Max number of TB chunks", "/IEM/CPU%u/re/cTbChunksMax", idCpu);
403	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cTotalTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
404	"Total number of TBs in the allocator", "/IEM/CPU%u/re/cTbTotal", idCpu);
405	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
406	"Max total number of TBs allowed", "/IEM/CPU%u/re/cTbTotalMax", idCpu);
407	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cInUseTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
408	"Number of currently allocated TBs", "/IEM/CPU%u/re/cTbAllocated", idCpu);
409	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cNativeTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
410	"Number of currently allocated native TBs", "/IEM/CPU%u/re/cTbAllocatedNative", idCpu);
411	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cThreadedTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
412	"Number of currently allocated threaded TBs", "/IEM/CPU%u/re/cTbAllocatedThreaded", idCpu);
413
414	PIEMTBCACHE const pTbCache = pVCpu->iem.s.pTbCacheR3;
415	STAMR3RegisterF(pVM, (void *)&pTbCache->cHash, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
416	"Translation block lookup table size", "/IEM/CPU%u/re/cTbHashTab", idCpu);
417
418	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupHits, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
419	"Translation block lookup hits", "/IEM/CPU%u/re/cTbLookupHits", idCpu);
420	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
421	"Translation block lookup misses", "/IEM/CPU%u/re/cTbLookupMisses", idCpu);
422	STAMR3RegisterF(pVM, (void *)&pTbCache->cCollisions, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
423	"Translation block hash table collisions", "/IEM/CPU%u/re/cTbCollisions", idCpu);
424	# ifdef VBOX_WITH_STATISTICS
425	STAMR3RegisterF(pVM, (void *)&pTbCache->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
426	"Time spent shortening collision lists", "/IEM/CPU%u/re/TbPruningCollisions", idCpu);
427	# endif
428
429	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedCalls, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
430	"Calls per threaded translation block", "/IEM/CPU%u/re/ThrdCallsPerTb", idCpu);
431	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedInstr, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
432	"Instruction per threaded translation block", "/IEM/CPU%u/re/ThrdInstrPerTb", idCpu);
433
434	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckIrqBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
435	"TB breaks by CheckIrq", "/IEM/CPU%u/re/CheckIrqBreaks", idCpu);
436	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckModeBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
437	"TB breaks by CheckMode", "/IEM/CPU%u/re/CheckModeBreaks", idCpu);
438	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
439	"Branch target misses", "/IEM/CPU%u/re/CheckTbJmpMisses", idCpu);
440	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
441	"Needing CS.LIM checking TB after branch or on page crossing", "/IEM/CPU%u/re/CheckTbNeedCsLimChecking", idCpu);
442
443	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCallsRecompiled, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
444	"Number of threaded calls per TB that have been properly recompiled to native code",
445	"/IEM/CPU%u/re/NativeCallsRecompiledPerTb", idCpu);
446	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCallsThreaded, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
447	"Number of threaded calls per TB that could not be recompiler to native code",
448	"/IEM/CPU%u/re/NativeCallsThreadedPerTb", idCpu);
449	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeFullyRecompiledTbs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
450	"Number of threaded calls that could not be recompiler to native code",
451	"/IEM/CPU%u/re/NativeFullyRecompiledTbs", idCpu);
452
453	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbNativeCode, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES_PER_TB,
454	"Size of native code per TB", "/IEM/CPU%u/re/NativeCodeSizePerTb", idCpu);
455	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeRecompilation, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
456	"Profiling iemNativeRecompile()", "/IEM/CPU%u/re/NativeRecompilation", idCpu);
457
458	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
459	# ifdef VBOX_WITH_STATISTICS
460	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFree, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
461	"Number of calls to iemNativeRegAllocFindFree.",
462	"/IEM/CPU%u/re/NativeRegFindFree", idCpu);
463	# endif
464	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
465	"Number of times iemNativeRegAllocFindFree needed to free a variable.",
466	"/IEM/CPU%u/re/NativeRegFindFreeVar", idCpu);
467	# ifdef VBOX_WITH_STATISTICS
468	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeNoVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
469	"Number of times iemNativeRegAllocFindFree did not needed to free any variables.",
470	"/IEM/CPU%u/re/NativeRegFindFreeNoVar", idCpu);
471	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeLivenessUnshadowed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
472	"Times liveness info freeed up shadowed guest registers in iemNativeRegAllocFindFree.",
473	"/IEM/CPU%u/re/NativeRegFindFreeLivenessUnshadowed", idCpu);
474	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeLivenessHelped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
475	"Times liveness info helped finding the return register in iemNativeRegAllocFindFree.",
476	"/IEM/CPU%u/re/NativeRegFindFreeLivenessHelped", idCpu);
477
478	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEflSkippedArithmetic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
479	"Skipped all status flag updating, arithmetic instructions",
480	"/IEM/CPU%u/re/NativeEFlagsSkippedArithmetic", idCpu);
481	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEflSkippedLogical, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
482	"Skipped all status flag updating, logical instructions",
483	"/IEM/CPU%u/re/NativeEFlagsSkippedLogical", idCpu);
484
485	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippable", idCpu);
486	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfSkippable", idCpu);
487	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfSkippable", idCpu);
488	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfSkippable", idCpu);
489	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfSkippable", idCpu);
490	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfSkippable", idCpu);
491
492	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfRequired", idCpu);
493	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfRequired", idCpu);
494	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfRequired", idCpu);
495	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfRequired", idCpu);
496	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfRequired", idCpu);
497	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfRequired", idCpu);
498
499	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
500	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfDelayable", idCpu);
501	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfDelayable", idCpu);
502	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfDelayable", idCpu);
503	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfDelayable", idCpu);
504	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfDelayable", idCpu);
505	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfDelayable", idCpu);
506	# endif
507
508	/* Sum up all status bits ('_' is a sorting hack). */
509	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fSkippable*", idCpu);
510	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total skippable EFLAGS status bit updating",
511	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippable", idCpu);
512
513	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fRequired*", idCpu);
514	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total required STATUS status bit updating",
515	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusRequired", idCpu);
516
517	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
518	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fDelayable*", idCpu);
519	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total potentially delayable STATUS status bit updating",
520	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayable", idCpu);
521	# endif
522
523	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?f*", idCpu);
524	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total STATUS status bit events of any kind",
525	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusTotal", idCpu);
526
527	/* Ratio of the status bit skippables. */
528	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusTotal", idCpu);
529	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippable", idCpu);
530	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
531	"Total skippable EFLAGS status bit updating percentage",
532	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippablePct", idCpu);
533
534	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
535	/* Ratio of the status bit skippables. */
536	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayable", idCpu);
537	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
538	"Total potentially delayable EFLAGS status bit updating percentage",
539	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayablePct", idCpu);
540	# endif
541
542	/* Ratios of individual bits. */
543	size_t const offFlagChar = RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlagsCf*", idCpu) - 3;
544	Assert(szPat[offFlagChar] == 'C');
545	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippable", idCpu);
546	Assert(szVal[offFlagChar] == 'C');
547	szPat[offFlagChar] = szVal[offFlagChar] = 'C'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.CF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippablePct", idCpu);
548	szPat[offFlagChar] = szVal[offFlagChar] = 'P'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.PF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsPfSkippablePct", idCpu);
549	szPat[offFlagChar] = szVal[offFlagChar] = 'A'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.AF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsAfSkippablePct", idCpu);
550	szPat[offFlagChar] = szVal[offFlagChar] = 'Z'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.ZF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsZfSkippablePct", idCpu);
551	szPat[offFlagChar] = szVal[offFlagChar] = 'S'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.SF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsSfSkippablePct", idCpu);
552	szPat[offFlagChar] = szVal[offFlagChar] = 'O'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.OF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsOfSkippablePct", idCpu);
553
554	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativePcUpdateTotal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Total RIP updates", "/IEM/CPU%u/re/NativePcUpdateTotal", idCpu);
555	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativePcUpdateDelayed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Delayed RIP updates", "/IEM/CPU%u/re/NativePcUpdateDelayed", idCpu);
556
557	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
558	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFree, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
559	"Number of calls to iemNativeSimdRegAllocFindFree.",
560	"/IEM/CPU%u/re/NativeSimdRegFindFree", idCpu);
561	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
562	"Number of times iemNativeSimdRegAllocFindFree needed to free a variable.",
563	"/IEM/CPU%u/re/NativeSimdRegFindFreeVar", idCpu);
564	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeNoVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
565	"Number of times iemNativeSimdRegAllocFindFree did not needed to free any variables.",
566	"/IEM/CPU%u/re/NativeSimdRegFindFreeNoVar", idCpu);
567	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeLivenessUnshadowed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
568	"Times liveness info freeed up shadowed guest registers in iemNativeSimdRegAllocFindFree.",
569	"/IEM/CPU%u/re/NativeSimdRegFindFreeLivenessUnshadowed", idCpu);
570	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeLivenessHelped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
571	"Times liveness info helped finding the return register in iemNativeSimdRegAllocFindFree.",
572	"/IEM/CPU%u/re/NativeSimdRegFindFreeLivenessHelped", idCpu);
573
574	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeDeviceNotAvailXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks", "/IEM/CPU%u/re/NativeMaybeDeviceNotAvailXcptCheckPotential", idCpu);
575	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeSseXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks", "/IEM/CPU%u/re/NativeMaybeSseXcptCheckPotential", idCpu);
576	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeAvxXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks", "/IEM/CPU%u/re/NativeMaybeAvxXcptCheckPotential", idCpu);
577
578	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeDeviceNotAvailXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted", "/IEM/CPU%u/re/NativeMaybeDeviceNotAvailXcptCheckOmitted", idCpu);
579	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeSseXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted", "/IEM/CPU%u/re/NativeMaybeSseXcptCheckOmitted", idCpu);
580	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeAvxXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted", "/IEM/CPU%u/re/NativeMaybeAvxXcptCheckOmitted", idCpu);
581	#endif
582
583	/* Ratio of the status bit skippables. */
584	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativePcUpdateTotal", idCpu);
585	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativePcUpdateDelayed", idCpu);
586	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
587	"Delayed RIP updating percentage",
588	"/IEM/CPU%u/re/NativePcUpdateDelayed_StatusDelayedPct", idCpu);
589
590	# endif /* VBOX_WITH_STATISTICS */
591	# endif /* VBOX_WITH_IEM_NATIVE_RECOMPILER */
592
593	#endif /* VBOX_WITH_IEM_RECOMPILER */
594
595	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
596	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
597	"", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
598	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
599	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
600	"", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
601
602	# if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
603	/* Instruction statistics: */
604	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
605	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
606	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
607	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
608	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
609	# include "IEMInstructionStatisticsTmpl.h"
610	# undef IEM_DO_INSTR_STAT
611	# endif
612
613	# if defined(VBOX_WITH_STATISTICS) && defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
614	/* Threaded function statistics: */
615	for (unsigned i = 1; i < (unsigned)kIemThreadedFunc_End; i++)
616	STAMR3RegisterF(pVM, &pVCpu->iem.s.acThreadedFuncStats[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED,
617	STAMUNIT_COUNT, NULL, "/IEM/CPU%u/ThrdFuncs/%s", idCpu, g_apszIemThreadedFunctionStats[i]);
618	# endif
619
620	#endif /* !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) - quick fix for stupid structure duplication non-sense */
621	}
622
623	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX)
624	/*
625	* Register the per-VM VMX APIC-access page handler type.
626	*/
627	if (pVM->cpum.ro.GuestFeatures.fVmx)
628	{
629	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
630	iemVmxApicAccessPageHandler,
631	"VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
632	AssertLogRelRCReturn(rc, rc);
633	}
634	#endif
635
636	DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
637	DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
638	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
639	DBGFR3InfoRegisterInternalArgv(pVM, "tb", "IEM translation block", iemR3InfoTb, DBGFINFO_FLAGS_RUN_ON_EMT);
640	#endif
641	#ifdef VBOX_WITH_DEBUGGER
642	iemR3RegisterDebuggerCommands();
643	#endif
644
645	return VINF_SUCCESS;
646	}
647
648
649	VMMR3DECL(int) IEMR3Term(PVM pVM)
650	{
651	NOREF(pVM);
652	return VINF_SUCCESS;
653	}
654
655
656	VMMR3DECL(void) IEMR3Relocate(PVM pVM)
657	{
658	RT_NOREF(pVM);
659	}
660
661
662	/**
663	* Gets the name of a generic IEM exit code.
664	*
665	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
666	* @param uExit The IEM exit to name.
667	*/
668	VMMR3DECL(const char *) IEMR3GetExitName(uint32_t uExit)
669	{
670	static const char * const s_apszNames[] =
671	{
672	/* external interrupts */
673	"ExtInt 00h", "ExtInt 01h", "ExtInt 02h", "ExtInt 03h", "ExtInt 04h", "ExtInt 05h", "ExtInt 06h", "ExtInt 07h",
674	"ExtInt 08h", "ExtInt 09h", "ExtInt 0ah", "ExtInt 0bh", "ExtInt 0ch", "ExtInt 0dh", "ExtInt 0eh", "ExtInt 0fh",
675	"ExtInt 10h", "ExtInt 11h", "ExtInt 12h", "ExtInt 13h", "ExtInt 14h", "ExtInt 15h", "ExtInt 16h", "ExtInt 17h",
676	"ExtInt 18h", "ExtInt 19h", "ExtInt 1ah", "ExtInt 1bh", "ExtInt 1ch", "ExtInt 1dh", "ExtInt 1eh", "ExtInt 1fh",
677	"ExtInt 20h", "ExtInt 21h", "ExtInt 22h", "ExtInt 23h", "ExtInt 24h", "ExtInt 25h", "ExtInt 26h", "ExtInt 27h",
678	"ExtInt 28h", "ExtInt 29h", "ExtInt 2ah", "ExtInt 2bh", "ExtInt 2ch", "ExtInt 2dh", "ExtInt 2eh", "ExtInt 2fh",
679	"ExtInt 30h", "ExtInt 31h", "ExtInt 32h", "ExtInt 33h", "ExtInt 34h", "ExtInt 35h", "ExtInt 36h", "ExtInt 37h",
680	"ExtInt 38h", "ExtInt 39h", "ExtInt 3ah", "ExtInt 3bh", "ExtInt 3ch", "ExtInt 3dh", "ExtInt 3eh", "ExtInt 3fh",
681	"ExtInt 40h", "ExtInt 41h", "ExtInt 42h", "ExtInt 43h", "ExtInt 44h", "ExtInt 45h", "ExtInt 46h", "ExtInt 47h",
682	"ExtInt 48h", "ExtInt 49h", "ExtInt 4ah", "ExtInt 4bh", "ExtInt 4ch", "ExtInt 4dh", "ExtInt 4eh", "ExtInt 4fh",
683	"ExtInt 50h", "ExtInt 51h", "ExtInt 52h", "ExtInt 53h", "ExtInt 54h", "ExtInt 55h", "ExtInt 56h", "ExtInt 57h",
684	"ExtInt 58h", "ExtInt 59h", "ExtInt 5ah", "ExtInt 5bh", "ExtInt 5ch", "ExtInt 5dh", "ExtInt 5eh", "ExtInt 5fh",
685	"ExtInt 60h", "ExtInt 61h", "ExtInt 62h", "ExtInt 63h", "ExtInt 64h", "ExtInt 65h", "ExtInt 66h", "ExtInt 67h",
686	"ExtInt 68h", "ExtInt 69h", "ExtInt 6ah", "ExtInt 6bh", "ExtInt 6ch", "ExtInt 6dh", "ExtInt 6eh", "ExtInt 6fh",
687	"ExtInt 70h", "ExtInt 71h", "ExtInt 72h", "ExtInt 73h", "ExtInt 74h", "ExtInt 75h", "ExtInt 76h", "ExtInt 77h",
688	"ExtInt 78h", "ExtInt 79h", "ExtInt 7ah", "ExtInt 7bh", "ExtInt 7ch", "ExtInt 7dh", "ExtInt 7eh", "ExtInt 7fh",
689	"ExtInt 80h", "ExtInt 81h", "ExtInt 82h", "ExtInt 83h", "ExtInt 84h", "ExtInt 85h", "ExtInt 86h", "ExtInt 87h",
690	"ExtInt 88h", "ExtInt 89h", "ExtInt 8ah", "ExtInt 8bh", "ExtInt 8ch", "ExtInt 8dh", "ExtInt 8eh", "ExtInt 8fh",
691	"ExtInt 90h", "ExtInt 91h", "ExtInt 92h", "ExtInt 93h", "ExtInt 94h", "ExtInt 95h", "ExtInt 96h", "ExtInt 97h",
692	"ExtInt 98h", "ExtInt 99h", "ExtInt 9ah", "ExtInt 9bh", "ExtInt 9ch", "ExtInt 9dh", "ExtInt 9eh", "ExtInt 9fh",
693	"ExtInt a0h", "ExtInt a1h", "ExtInt a2h", "ExtInt a3h", "ExtInt a4h", "ExtInt a5h", "ExtInt a6h", "ExtInt a7h",
694	"ExtInt a8h", "ExtInt a9h", "ExtInt aah", "ExtInt abh", "ExtInt ach", "ExtInt adh", "ExtInt aeh", "ExtInt afh",
695	"ExtInt b0h", "ExtInt b1h", "ExtInt b2h", "ExtInt b3h", "ExtInt b4h", "ExtInt b5h", "ExtInt b6h", "ExtInt b7h",
696	"ExtInt b8h", "ExtInt b9h", "ExtInt bah", "ExtInt bbh", "ExtInt bch", "ExtInt bdh", "ExtInt beh", "ExtInt bfh",
697	"ExtInt c0h", "ExtInt c1h", "ExtInt c2h", "ExtInt c3h", "ExtInt c4h", "ExtInt c5h", "ExtInt c6h", "ExtInt c7h",
698	"ExtInt c8h", "ExtInt c9h", "ExtInt cah", "ExtInt cbh", "ExtInt cch", "ExtInt cdh", "ExtInt ceh", "ExtInt cfh",
699	"ExtInt d0h", "ExtInt d1h", "ExtInt d2h", "ExtInt d3h", "ExtInt d4h", "ExtInt d5h", "ExtInt d6h", "ExtInt d7h",
700	"ExtInt d8h", "ExtInt d9h", "ExtInt dah", "ExtInt dbh", "ExtInt dch", "ExtInt ddh", "ExtInt deh", "ExtInt dfh",
701	"ExtInt e0h", "ExtInt e1h", "ExtInt e2h", "ExtInt e3h", "ExtInt e4h", "ExtInt e5h", "ExtInt e6h", "ExtInt e7h",
702	"ExtInt e8h", "ExtInt e9h", "ExtInt eah", "ExtInt ebh", "ExtInt ech", "ExtInt edh", "ExtInt eeh", "ExtInt efh",
703	"ExtInt f0h", "ExtInt f1h", "ExtInt f2h", "ExtInt f3h", "ExtInt f4h", "ExtInt f5h", "ExtInt f6h", "ExtInt f7h",
704	"ExtInt f8h", "ExtInt f9h", "ExtInt fah", "ExtInt fbh", "ExtInt fch", "ExtInt fdh", "ExtInt feh", "ExtInt ffh",
705	/* software interrups */
706	"SoftInt 00h", "SoftInt 01h", "SoftInt 02h", "SoftInt 03h", "SoftInt 04h", "SoftInt 05h", "SoftInt 06h", "SoftInt 07h",
707	"SoftInt 08h", "SoftInt 09h", "SoftInt 0ah", "SoftInt 0bh", "SoftInt 0ch", "SoftInt 0dh", "SoftInt 0eh", "SoftInt 0fh",
708	"SoftInt 10h", "SoftInt 11h", "SoftInt 12h", "SoftInt 13h", "SoftInt 14h", "SoftInt 15h", "SoftInt 16h", "SoftInt 17h",
709	"SoftInt 18h", "SoftInt 19h", "SoftInt 1ah", "SoftInt 1bh", "SoftInt 1ch", "SoftInt 1dh", "SoftInt 1eh", "SoftInt 1fh",
710	"SoftInt 20h", "SoftInt 21h", "SoftInt 22h", "SoftInt 23h", "SoftInt 24h", "SoftInt 25h", "SoftInt 26h", "SoftInt 27h",
711	"SoftInt 28h", "SoftInt 29h", "SoftInt 2ah", "SoftInt 2bh", "SoftInt 2ch", "SoftInt 2dh", "SoftInt 2eh", "SoftInt 2fh",
712	"SoftInt 30h", "SoftInt 31h", "SoftInt 32h", "SoftInt 33h", "SoftInt 34h", "SoftInt 35h", "SoftInt 36h", "SoftInt 37h",
713	"SoftInt 38h", "SoftInt 39h", "SoftInt 3ah", "SoftInt 3bh", "SoftInt 3ch", "SoftInt 3dh", "SoftInt 3eh", "SoftInt 3fh",
714	"SoftInt 40h", "SoftInt 41h", "SoftInt 42h", "SoftInt 43h", "SoftInt 44h", "SoftInt 45h", "SoftInt 46h", "SoftInt 47h",
715	"SoftInt 48h", "SoftInt 49h", "SoftInt 4ah", "SoftInt 4bh", "SoftInt 4ch", "SoftInt 4dh", "SoftInt 4eh", "SoftInt 4fh",
716	"SoftInt 50h", "SoftInt 51h", "SoftInt 52h", "SoftInt 53h", "SoftInt 54h", "SoftInt 55h", "SoftInt 56h", "SoftInt 57h",
717	"SoftInt 58h", "SoftInt 59h", "SoftInt 5ah", "SoftInt 5bh", "SoftInt 5ch", "SoftInt 5dh", "SoftInt 5eh", "SoftInt 5fh",
718	"SoftInt 60h", "SoftInt 61h", "SoftInt 62h", "SoftInt 63h", "SoftInt 64h", "SoftInt 65h", "SoftInt 66h", "SoftInt 67h",
719	"SoftInt 68h", "SoftInt 69h", "SoftInt 6ah", "SoftInt 6bh", "SoftInt 6ch", "SoftInt 6dh", "SoftInt 6eh", "SoftInt 6fh",
720	"SoftInt 70h", "SoftInt 71h", "SoftInt 72h", "SoftInt 73h", "SoftInt 74h", "SoftInt 75h", "SoftInt 76h", "SoftInt 77h",
721	"SoftInt 78h", "SoftInt 79h", "SoftInt 7ah", "SoftInt 7bh", "SoftInt 7ch", "SoftInt 7dh", "SoftInt 7eh", "SoftInt 7fh",
722	"SoftInt 80h", "SoftInt 81h", "SoftInt 82h", "SoftInt 83h", "SoftInt 84h", "SoftInt 85h", "SoftInt 86h", "SoftInt 87h",
723	"SoftInt 88h", "SoftInt 89h", "SoftInt 8ah", "SoftInt 8bh", "SoftInt 8ch", "SoftInt 8dh", "SoftInt 8eh", "SoftInt 8fh",
724	"SoftInt 90h", "SoftInt 91h", "SoftInt 92h", "SoftInt 93h", "SoftInt 94h", "SoftInt 95h", "SoftInt 96h", "SoftInt 97h",
725	"SoftInt 98h", "SoftInt 99h", "SoftInt 9ah", "SoftInt 9bh", "SoftInt 9ch", "SoftInt 9dh", "SoftInt 9eh", "SoftInt 9fh",
726	"SoftInt a0h", "SoftInt a1h", "SoftInt a2h", "SoftInt a3h", "SoftInt a4h", "SoftInt a5h", "SoftInt a6h", "SoftInt a7h",
727	"SoftInt a8h", "SoftInt a9h", "SoftInt aah", "SoftInt abh", "SoftInt ach", "SoftInt adh", "SoftInt aeh", "SoftInt afh",
728	"SoftInt b0h", "SoftInt b1h", "SoftInt b2h", "SoftInt b3h", "SoftInt b4h", "SoftInt b5h", "SoftInt b6h", "SoftInt b7h",
729	"SoftInt b8h", "SoftInt b9h", "SoftInt bah", "SoftInt bbh", "SoftInt bch", "SoftInt bdh", "SoftInt beh", "SoftInt bfh",
730	"SoftInt c0h", "SoftInt c1h", "SoftInt c2h", "SoftInt c3h", "SoftInt c4h", "SoftInt c5h", "SoftInt c6h", "SoftInt c7h",
731	"SoftInt c8h", "SoftInt c9h", "SoftInt cah", "SoftInt cbh", "SoftInt cch", "SoftInt cdh", "SoftInt ceh", "SoftInt cfh",
732	"SoftInt d0h", "SoftInt d1h", "SoftInt d2h", "SoftInt d3h", "SoftInt d4h", "SoftInt d5h", "SoftInt d6h", "SoftInt d7h",
733	"SoftInt d8h", "SoftInt d9h", "SoftInt dah", "SoftInt dbh", "SoftInt dch", "SoftInt ddh", "SoftInt deh", "SoftInt dfh",
734	"SoftInt e0h", "SoftInt e1h", "SoftInt e2h", "SoftInt e3h", "SoftInt e4h", "SoftInt e5h", "SoftInt e6h", "SoftInt e7h",
735	"SoftInt e8h", "SoftInt e9h", "SoftInt eah", "SoftInt ebh", "SoftInt ech", "SoftInt edh", "SoftInt eeh", "SoftInt efh",
736	"SoftInt f0h", "SoftInt f1h", "SoftInt f2h", "SoftInt f3h", "SoftInt f4h", "SoftInt f5h", "SoftInt f6h", "SoftInt f7h",
737	"SoftInt f8h", "SoftInt f9h", "SoftInt fah", "SoftInt fbh", "SoftInt fch", "SoftInt fdh", "SoftInt feh", "SoftInt ffh",
738	};
739	if (uExit < RT_ELEMENTS(s_apszNames))
740	return s_apszNames[uExit];
741	return NULL;
742	}
743
744
745	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
746	static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const pTlb, bool pfHeader)
747	{
748	if (*pfHeader)
749	return;
750	pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
751	*pfHeader = true;
752	}
753
754
755	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
756	static void iemR3InfoTlbPrintSlot(PCDBGFINFOHLP pHlp, IEMTLB const pTlb, IEMTLBENTRY const pTlbe, uint32_t uSlot)
757	{
758	pHlp->pfnPrintf(pHlp, "%02x: %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s/%s%s%s/%s %s\n",
759	uSlot,
760	(pTlbe->uTag & IEMTLB_REVISION_MASK) == pTlb->uTlbRevision ? "valid "
761	: (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
762	: "expired",
763	(pTlbe->uTag & ~IEMTLB_REVISION_MASK) << X86_PAGE_SHIFT,
764	pTlbe->GCPhys, pTlbe->pbMappingR3,
765	(uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
766	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "NX" : " X",
767	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "RO" : "RW",
768	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
769	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
770	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
771	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
772	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "U" : "-",
773	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "S" : "M",
774	(pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
775	: (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired");
776	}
777
778
779	/** Displays one or more TLB slots. */
780	static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
781	uint32_t uSlot, uint32_t cSlots, bool *pfHeader)
782	{
783	if (uSlot < RT_ELEMENTS(pTlb->aEntries))
784	{
785	if (cSlots > RT_ELEMENTS(pTlb->aEntries))
786	{
787	pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
788	cSlots, RT_ELEMENTS(pTlb->aEntries));
789	cSlots = RT_ELEMENTS(pTlb->aEntries);
790	}
791
792	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
793	while (cSlots-- > 0)
794	{
795	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
796	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
797	uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
798	}
799	}
800	else
801	pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
802	uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
803	}
804
805
806	/** Displays the TLB slot for the given address. */
807	static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
808	uint64_t uAddress, bool *pfHeader)
809	{
810	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
811
812	uint64_t const uTag = (uAddress << 16) >> (X86_PAGE_SHIFT + 16);
813	uint32_t const uSlot = (uint8_t)uTag;
814	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
815	pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
816	Tlbe.uTag == (uTag \| pTlb->uTlbRevision) ? "match"
817	: (Tlbe.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
818	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
819	}
820
821
822	/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
823	static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
824	{
825	/*
826	* This is entirely argument driven.
827	*/
828	static RTGETOPTDEF const s_aOptions[] =
829	{
830	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
831	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
832	{ "all", 'A', RTGETOPT_REQ_NOTHING },
833	{ "--all", 'A', RTGETOPT_REQ_NOTHING },
834	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
835	{ "--range", 'r', RTGETOPT_REQ_UINT32_PAIR \| RTGETOPT_FLAG_HEX },
836	{ "--slot", 's', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
837	};
838
839	char szDefault[] = "-A";
840	char *papszDefaults[2] = { szDefault, NULL };
841	if (cArgs == 0)
842	{
843	cArgs = 1;
844	papszArgs = papszDefaults;
845	}
846
847	RTGETOPTSTATE State;
848	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
849	AssertRCReturnVoid(rc);
850
851	bool fNeedHeader = true;
852	bool fAddressMode = true;
853	PVMCPU pVCpu = VMMGetCpu(pVM);
854	if (!pVCpu)
855	pVCpu = VMMGetCpuById(pVM, 0);
856
857	RTGETOPTUNION ValueUnion;
858	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
859	{
860	switch (rc)
861	{
862	case 'c':
863	if (ValueUnion.u32 >= pVM->cCpus)
864	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
865	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
866	{
867	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
868	fNeedHeader = true;
869	}
870	break;
871
872	case 'a':
873	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
874	ValueUnion.u64, &fNeedHeader);
875	fAddressMode = true;
876	break;
877
878	case 'A':
879	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
880	0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), &fNeedHeader);
881	break;
882
883	case 'r':
884	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
885	ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, &fNeedHeader);
886	fAddressMode = false;
887	break;
888
889	case 's':
890	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
891	ValueUnion.u32, 1, &fNeedHeader);
892	fAddressMode = false;
893	break;
894
895	case VINF_GETOPT_NOT_OPTION:
896	if (fAddressMode)
897	{
898	uint64_t uAddr;
899	rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
900	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
901	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
902	uAddr, &fNeedHeader);
903	else
904	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
905	}
906	else
907	{
908	uint32_t uSlot;
909	rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
910	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
911	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
912	uSlot, 1, &fNeedHeader);
913	else
914	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
915	}
916	break;
917
918	case 'h':
919	pHlp->pfnPrintf(pHlp,
920	"Usage: info %ctlb [options]\n"
921	"\n"
922	"Options:\n"
923	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
924	" Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
925	" -A, --all, all\n"
926	" Display all the TLB entries (default if no other args).\n"
927	" -a<virt>, --address=<virt>\n"
928	" Shows the TLB entry for the specified guest virtual address.\n"
929	" -r<slot:count>, --range=<slot:count>\n"
930	" Shows the TLB entries for the specified slot range.\n"
931	" -s<slot>,--slot=<slot>\n"
932	" Shows the given TLB slot.\n"
933	"\n"
934	"Non-options are interpreted according to the last -a, -r or -s option,\n"
935	"defaulting to addresses if not preceeded by any of those options.\n"
936	, fITlb ? 'i' : 'd');
937	return;
938
939	default:
940	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
941	return;
942	}
943	}
944	}
945
946
947	/**
948	* @callback_method_impl{FNDBGFINFOARGVINT, itlb}
949	*/
950	static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
951	{
952	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /fITlb/);
953	}
954
955
956	/**
957	* @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
958	*/
959	static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
960	{
961	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /fITlb/);
962	}
963
964	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
965	/**
966	* @callback_method_impl{FNDBGFINFOARGVINT, tb}
967	*/
968	static DECLCALLBACK(void) iemR3InfoTb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
969	{
970	/*
971	* Parse arguments.
972	*/
973	static RTGETOPTDEF const s_aOptions[] =
974	{
975	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
976	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
977	{ "--addr", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
978	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
979	{ "--phys", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
980	{ "--physical", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
981	{ "--phys-addr", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
982	{ "--phys-address", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
983	{ "--physical-address", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
984	{ "--flags", 'f', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
985	};
986
987	RTGETOPTSTATE State;
988	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
989	AssertRCReturnVoid(rc);
990
991	PVMCPU const pVCpuThis = VMMGetCpu(pVM);
992	PVMCPU pVCpu = pVCpuThis ? pVCpuThis : VMMGetCpuById(pVM, 0);
993	RTGCPHYS GCPhysPc = NIL_RTGCPHYS;
994	RTGCPHYS GCVirt = NIL_RTGCPTR;
995	uint32_t fFlags = UINT32_MAX;
996
997	RTGETOPTUNION ValueUnion;
998	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
999	{
1000	switch (rc)
1001	{
1002	case 'c':
1003	if (ValueUnion.u32 >= pVM->cCpus)
1004	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
1005	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
1006	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
1007	break;
1008
1009	case 'a':
1010	GCVirt = ValueUnion.u64;
1011	GCPhysPc = NIL_RTGCPHYS;
1012	break;
1013
1014	case 'p':
1015	GCVirt = NIL_RTGCPHYS;
1016	GCPhysPc = ValueUnion.u64;
1017	break;
1018
1019	case 'f':
1020	fFlags = ValueUnion.u32;
1021	break;
1022
1023	case 'h':
1024	pHlp->pfnPrintf(pHlp,
1025	"Usage: info %ctlb [options]\n"
1026	"\n"
1027	"Options:\n"
1028	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
1029	" Selects the CPU which TBs we're looking at. Default: Caller / 0\n"
1030	" -a<virt>, --address=<virt>\n"
1031	" Shows the TB for the specified guest virtual address.\n"
1032	" -p<phys>, --phys=<phys>, --phys-addr=<phys>\n"
1033	" Shows the TB for the specified guest physical address.\n"
1034	" -f<flags>,--flags=<flags>\n"
1035	" The TB flags value (hex) to use when looking up the TB.\n"
1036	"\n"
1037	"The default is to use CS:RIP and derive flags from the CPU mode.\n");
1038	return;
1039
1040	default:
1041	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1042	return;
1043	}
1044	}
1045
1046	/* Currently, only do work on the same EMT. */
1047	if (pVCpu != pVCpuThis)
1048	{
1049	pHlp->pfnPrintf(pHlp, "TODO: Cross EMT calling not supported yet: targeting %u, caller on %d\n",
1050	pVCpu->idCpu, pVCpuThis ? (int)pVCpuThis->idCpu : -1);
1051	return;
1052	}
1053
1054	/*
1055	* Defaults.
1056	*/
1057	if (GCPhysPc == NIL_RTGCPHYS)
1058	{
1059	if (GCVirt == NIL_RTGCPTR)
1060	GCVirt = CPUMGetGuestFlatPC(pVCpu);
1061	rc = PGMPhysGCPtr2GCPhys(pVCpu, GCVirt, &GCPhysPc);
1062	if (RT_FAILURE(rc))
1063	{
1064	pHlp->pfnPrintf(pHlp, "Failed to convert %%%RGv to an guest physical address: %Rrc\n", GCVirt, rc);
1065	return;
1066	}
1067	}
1068	if (fFlags == UINT32_MAX)
1069	{
1070	/* Note! This is duplicating code in IEMAllThrdRecompiler. */
1071	fFlags = iemCalcExecFlags(pVCpu);
1072	if (pVM->cCpus == 1)
1073	fFlags \|= IEM_F_X86_DISREGARD_LOCK;
1074	if (CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx))
1075	fFlags \|= IEMTB_F_INHIBIT_SHADOW;
1076	if (CPUMAreInterruptsInhibitedByNmiEx(&pVCpu->cpum.GstCtx))
1077	fFlags \|= IEMTB_F_INHIBIT_NMI;
1078	if ((IEM_F_MODE_CPUMODE_MASK & fFlags) != IEMMODE_64BIT)
1079	{
1080	int64_t const offFromLim = (int64_t)pVCpu->cpum.GstCtx.cs.u32Limit - (int64_t)pVCpu->cpum.GstCtx.eip;
1081	if (offFromLim < X86_PAGE_SIZE + 16 - (int32_t)(pVCpu->cpum.GstCtx.cs.u64Base & GUEST_PAGE_OFFSET_MASK))
1082	fFlags \|= IEMTB_F_CS_LIM_CHECKS;
1083	}
1084	}
1085
1086	/*
1087	* Do the lookup...
1088	*
1089	* Note! This is also duplicating code in IEMAllThrdRecompiler. We don't
1090	* have much choice since we don't want to increase use counters and
1091	* trigger native recompilation.
1092	*/
1093	fFlags &= IEMTB_F_KEY_MASK;
1094	IEMTBCACHE const * const pTbCache = pVCpu->iem.s.pTbCacheR3;
1095	uint32_t const idxHash = IEMTBCACHE_HASH_NO_KEY_MASK(pTbCache, fFlags, GCPhysPc);
1096	PCIEMTB pTb = IEMTBCACHE_PTR_GET_TB(pTbCache->apHash[idxHash]);
1097	while (pTb)
1098	{
1099	if (pTb->GCPhysPc == GCPhysPc)
1100	{
1101	if ((pTb->fFlags & IEMTB_F_KEY_MASK) == fFlags)
1102	{
1103	/// @todo if (pTb->x86.fAttr == (uint16_t)pVCpu->cpum.GstCtx.cs.Attr.u)
1104	break;
1105	}
1106	}
1107	pTb = pTb->pNext;
1108	}
1109	if (!pTb)
1110	pHlp->pfnPrintf(pHlp, "PC=%RGp fFlags=%#x - no TB found on #%u\n", GCPhysPc, fFlags, pVCpu->idCpu);
1111	else
1112	{
1113	/*
1114	* Disassemble according to type.
1115	*/
1116	switch (pTb->fFlags & IEMTB_F_TYPE_MASK)
1117	{
1118	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
1119	case IEMTB_F_TYPE_NATIVE:
1120	pHlp->pfnPrintf(pHlp, "PC=%RGp fFlags=%#x on #%u: %p - native\n", GCPhysPc, fFlags, pVCpu->idCpu, pTb);
1121	iemNativeDisassembleTb(pTb, pHlp);
1122	break;
1123	# endif
1124
1125	case IEMTB_F_TYPE_THREADED:
1126	pHlp->pfnPrintf(pHlp, "PC=%RGp fFlags=%#x on #%u: %p - threaded\n", GCPhysPc, fFlags, pVCpu->idCpu, pTb);
1127	iemThreadedDisassembleTb(pTb, pHlp);
1128	break;
1129
1130	default:
1131	pHlp->pfnPrintf(pHlp, "PC=%RGp fFlags=%#x on #%u: %p - ??? %#x\n",
1132	GCPhysPc, fFlags, pVCpu->idCpu, pTb, pTb->fFlags);
1133	break;
1134	}
1135	}
1136	}
1137	#endif /* VBOX_WITH_IEM_RECOMPILER && !VBOX_VMM_TARGET_ARMV8 */
1138
1139
1140	#ifdef VBOX_WITH_DEBUGGER
1141
1142	/** @callback_method_impl{FNDBGCCMD,
1143	* Implements the '.alliem' command. }
1144	*/
1145	static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
1146	{
1147	VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
1148	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
1149	if (pVCpu)
1150	{
1151	VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAll, 1, pVCpu);
1152	return VINF_SUCCESS;
1153	}
1154	RT_NOREF(paArgs, cArgs);
1155	return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
1156	}
1157
1158
1159	/**
1160	* Called by IEMR3Init to register debugger commands.
1161	*/
1162	static void iemR3RegisterDebuggerCommands(void)
1163	{
1164	/*
1165	* Register debugger commands.
1166	*/
1167	static DBGCCMD const s_aCmds[] =
1168	{
1169	{
1170	/* .pszCmd = */ "iemflushtlb",
1171	/* .cArgsMin = */ 0,
1172	/* .cArgsMax = */ 0,
1173	/* .paArgDescs = */ NULL,
1174	/* .cArgDescs = */ 0,
1175	/* .fFlags = */ 0,
1176	/* .pfnHandler = */ iemR3DbgFlushTlbs,
1177	/* .pszSyntax = */ "",
1178	/* .pszDescription = */ "Flushed the code and data TLBs"
1179	},
1180	};
1181
1182	int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
1183	AssertLogRelRC(rc);
1184	}
1185
1186	#endif /* VBOX_WITH_DEBUGGER */
1187

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source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 104064

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