[36788] | 1 | /* $Id: IEMR3.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
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| 2 | /** @file
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| 3 | * IEM - Interpreted Execution Manager.
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| 4 | */
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| 5 |
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| 6 | /*
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[82968] | 7 | * Copyright (C) 2011-2020 Oracle Corporation
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[36788] | 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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[57358] | 18 |
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| 19 | /*********************************************************************************************************************************
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| 20 | * Header Files *
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| 21 | *********************************************************************************************************************************/
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[36788] | 22 | #define LOG_GROUP LOG_GROUP_EM
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| 23 | #include <VBox/vmm/iem.h>
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[47307] | 24 | #include <VBox/vmm/cpum.h>
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[64545] | 25 | #include <VBox/vmm/mm.h>
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[36788] | 26 | #include "IEMInternal.h"
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| 27 | #include <VBox/vmm/vm.h>
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| 28 | #include <VBox/err.h>
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| 29 |
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[47307] | 30 | #include <iprt/asm-amd64-x86.h>
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[36788] | 31 | #include <iprt/assert.h>
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| 32 |
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[61307] | 33 | static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
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| 34 | {
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| 35 | switch (enmTargetCpu)
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| 36 | {
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| 37 | #define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
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| 38 | CASE_RET_STR(IEMTARGETCPU_8086);
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| 39 | CASE_RET_STR(IEMTARGETCPU_V20);
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| 40 | CASE_RET_STR(IEMTARGETCPU_186);
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| 41 | CASE_RET_STR(IEMTARGETCPU_286);
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| 42 | CASE_RET_STR(IEMTARGETCPU_386);
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| 43 | CASE_RET_STR(IEMTARGETCPU_486);
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| 44 | CASE_RET_STR(IEMTARGETCPU_PENTIUM);
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| 45 | CASE_RET_STR(IEMTARGETCPU_PPRO);
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| 46 | CASE_RET_STR(IEMTARGETCPU_CURRENT);
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| 47 | #undef CASE_RET_STR
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| 48 | default: return "Unknown";
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| 49 | }
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| 50 | }
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[36788] | 51 |
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[47307] | 52 | /**
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| 53 | * Initializes the interpreted execution manager.
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| 54 | *
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| 55 | * This must be called after CPUM as we're quering information from CPUM about
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| 56 | * the guest and host CPUs.
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| 57 | *
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| 58 | * @returns VBox status code.
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[58122] | 59 | * @param pVM The cross context VM structure.
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[47307] | 60 | */
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[36788] | 61 | VMMR3DECL(int) IEMR3Init(PVM pVM)
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| 62 | {
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[62302] | 63 | uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
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| 64 | uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
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| 65 |
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[36788] | 66 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
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| 67 | {
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[80191] | 68 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
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[42437] | 69 |
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[62302] | 70 | pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
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| 71 | pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
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| 72 |
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| 73 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 74 | "Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
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| 75 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
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| 76 | "Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
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| 77 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 78 | "Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
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| 79 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 80 | "VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
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| 81 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 82 | "VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
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| 83 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 84 | "Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
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| 85 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 86 | "Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
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| 87 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
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| 88 | "Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
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| 89 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
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[56628] | 90 | "Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
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[47307] | 91 |
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[62302] | 92 | #ifdef VBOX_WITH_STATISTICS
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| 93 | STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 94 | "Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
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| 95 | STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 96 | "Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
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| 97 | #endif
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| 98 | STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 99 | "Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
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| 100 | STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
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| 101 | "Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
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| 102 | STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
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| 103 | "Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
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| 104 | STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
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| 105 | "Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
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| 106 |
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| 107 | STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 108 | "Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
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| 109 | STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
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| 110 | "Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
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| 111 | STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
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| 112 | "Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
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| 113 |
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[64551] | 114 | #if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
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[64545] | 115 | /* Allocate instruction statistics and register them. */
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| 116 | pVCpu->iem.s.pStatsR3 = (PIEMINSTRSTATS)MMR3HeapAllocZ(pVM, MM_TAG_IEM, sizeof(IEMINSTRSTATS));
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| 117 | AssertLogRelReturn(pVCpu->iem.s.pStatsR3, VERR_NO_MEMORY);
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| 118 | int rc = MMHyperAlloc(pVM, sizeof(IEMINSTRSTATS), sizeof(uint64_t), MM_TAG_IEM, (void **)&pVCpu->iem.s.pStatsCCR3);
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| 119 | AssertLogRelRCReturn(rc, rc);
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| 120 | pVCpu->iem.s.pStatsR0 = MMHyperR3ToR0(pVM, pVCpu->iem.s.pStatsCCR3);
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| 121 | # define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
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| 122 | STAMR3RegisterF(pVM, &pVCpu->iem.s.pStatsCCR3->a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
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[66650] | 123 | STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
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[64545] | 124 | STAMR3RegisterF(pVM, &pVCpu->iem.s.pStatsR3->a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
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[66650] | 125 | STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
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[64545] | 126 | # include "IEMInstructionStatisticsTmpl.h"
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| 127 | # undef IEM_DO_INSTR_STAT
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| 128 | #endif
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[62302] | 129 |
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[47307] | 130 | /*
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| 131 | * Host and guest CPU information.
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| 132 | */
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| 133 | if (idCpu == 0)
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| 134 | {
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| 135 | pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
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| 136 | pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
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[60415] | 137 | #if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
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| 138 | switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
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| 139 | {
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| 140 | case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
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| 141 | case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
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| 142 | case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
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| 143 | case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
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| 144 | case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
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| 145 | case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
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| 146 | case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
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| 147 | case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
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| 148 | case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
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| 149 | default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
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| 150 | }
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[61307] | 151 | LogRel(("IEM: TargetCpu=%s, Microarch=%s\n", iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMR3MicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch)));
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[60415] | 152 | #endif
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[47307] | 153 | }
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| 154 | else
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| 155 | {
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[80191] | 156 | pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
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| 157 | pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
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[60415] | 158 | #if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
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[80191] | 159 | pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
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[60415] | 160 | #endif
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[47307] | 161 | }
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[47548] | 162 |
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| 163 | /*
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| 164 | * Mark all buffers free.
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| 165 | */
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| 166 | uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
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| 167 | while (iMemMap-- > 0)
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| 168 | pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
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[36788] | 169 | }
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[75611] | 170 |
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| 171 | #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
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| 172 | /*
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| 173 | * Register the per-VM VMX APIC-access page handler type.
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| 174 | */
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| 175 | if (pVM->cpum.ro.GuestFeatures.fVmx)
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| 176 | {
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[80191] | 177 | PVMCPU pVCpu0 = pVM->apCpusR3[0];
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[75611] | 178 | int rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, iemVmxApicAccessPageHandler,
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| 179 | NULL /* pszModR0 */,
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| 180 | "iemVmxApicAccessPageHandler", NULL /* pszPfHandlerR0 */,
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| 181 | NULL /* pszModRC */,
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| 182 | NULL /* pszHandlerRC */, NULL /* pszPfHandlerRC */,
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| 183 | "VMX APIC-access page", &pVCpu0->iem.s.hVmxApicAccessPage);
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| 184 | AssertLogRelRCReturn(rc, rc);
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| 185 | }
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| 186 | #endif
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| 187 |
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[36788] | 188 | return VINF_SUCCESS;
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| 189 | }
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| 190 |
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| 191 |
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| 192 | VMMR3DECL(int) IEMR3Term(PVM pVM)
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| 193 | {
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[39078] | 194 | NOREF(pVM);
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[65824] | 195 | #if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
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| 196 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
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| 197 | {
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[80191] | 198 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
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[65824] | 199 | MMR3HeapFree(pVCpu->iem.s.pStatsR3);
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| 200 | pVCpu->iem.s.pStatsR3 = NULL;
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| 201 | }
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| 202 | #endif
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[36788] | 203 | return VINF_SUCCESS;
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| 204 | }
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| 205 |
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| 206 |
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| 207 | VMMR3DECL(void) IEMR3Relocate(PVM pVM)
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| 208 | {
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[80089] | 209 | RT_NOREF(pVM);
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[36788] | 210 | }
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| 211 |
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