VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp

Last change on this file was 100758, checked in by vboxsync, 10 months ago

VMM/GICR3: Add some preliminary saved state handling, bugref:10404 [fix]
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1/* $Id: GICR3.cpp 100758 2023-07-31 14:32:33Z vboxsync $ */
2/** @file
3 * GIC - Generic Interrupt Controller Architecture (GICv3).
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_APIC
33#include <VBox/log.h>
34#include "GICInternal.h"
35#include <VBox/vmm/gic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/hm.h>
38#include <VBox/vmm/mm.h>
39#include <VBox/vmm/pdmdev.h>
40#include <VBox/vmm/ssm.h>
41#include <VBox/vmm/vm.h>
42
43#include <iprt/armv8.h>
44
45
46#ifndef VBOX_DEVICE_STRUCT_TESTCASE
47
48
49/*********************************************************************************************************************************
50* Defined Constants And Macros *
51*********************************************************************************************************************************/
52/** Some ancient version... */
53#define GIC_SAVED_STATE_VERSION 1
54
55# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
56 { (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicV3Icc, kCpumSysRegWrFn_GicV3Icc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
57
58
59/*********************************************************************************************************************************
60* Global Variables *
61*********************************************************************************************************************************/
62/**
63 * System register ranges for the GICv3.
64 */
65static CPUMSYSREGRANGE const g_aSysRegRanges_GICv3[] =
66{
67 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
68 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
69 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
70 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
71 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
72};
73
74
75/**
76 * Dumps basic APIC state.
77 *
78 * @param pVM The cross context VM structure.
79 * @param pHlp The info helpers.
80 * @param pszArgs Arguments, ignored.
81 */
82static DECLCALLBACK(void) gicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
83{
84 RT_NOREF(pVM, pHlp, pszArgs);
85}
86
87
88/**
89 * Dumps GIC Distributor information.
90 *
91 * @param pVM The cross context VM structure.
92 * @param pHlp The info helpers.
93 * @param pszArgs Arguments, ignored.
94 */
95static DECLCALLBACK(void) gicR3InfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
96{
97 RT_NOREF(pszArgs);
98
99 PGIC pGic = VM_TO_GIC(pVM);
100 PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
101 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
102
103 pHlp->pfnPrintf(pHlp, "GICv3 Distributor:\n");
104 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->u32RegIGrp0);
105 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->u32RegICfg0);
106 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->u32RegICfg1);
107 pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicDev->bmIntEnabled);
108 pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicDev->bmIntPending);
109 pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicDev->bmIntActive);
110 pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
111 for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->abIntPriority); i++)
112 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->abIntPriority[i]);
113
114 pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicDev->fIrqGrp0Enabled);
115 pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicDev->fIrqGrp1Enabled);
116}
117
118
119/**
120 * Dumps the GIC Redistributor information.
121 *
122 * @param pVM The cross context VM structure.
123 * @param pHlp The info helpers.
124 * @param pszArgs Arguments, ignored.
125 */
126static DECLCALLBACK(void) gicR3InfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
127{
128 NOREF(pszArgs);
129 PVMCPU pVCpu = VMMGetCpu(pVM);
130 if (!pVCpu)
131 pVCpu = pVM->apCpusR3[0];
132
133 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
134
135 pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
136 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicVCpu->u32RegIGrp0);
137 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicVCpu->u32RegICfg0);
138 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicVCpu->u32RegICfg1);
139 pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicVCpu->bmIntEnabled);
140 pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicVCpu->bmIntPending);
141 pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicVCpu->bmIntActive);
142 pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
143 for (uint32_t i = 0; i < RT_ELEMENTS(pGicVCpu->abIntPriority); i++)
144 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", i, pGicVCpu->abIntPriority[i]);
145
146 pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
147 pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicVCpu->fIrqGrp0Enabled);
148 pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicVCpu->fIrqGrp1Enabled);
149 pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicVCpu->bInterruptPriority);
150 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicVCpu->bBinaryPointGrp0);
151 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicVCpu->bBinaryPointGrp1);
152 pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicVCpu->idxRunningPriority);
153 pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicVCpu->abRunningPriorities[pGicVCpu->idxRunningPriority]);
154}
155
156
157/**
158 * Worker for saving per-VM GIC data.
159 *
160 * @returns VBox status code.
161 * @param pDevIns The device instance.
162 * @param pVM The cross context VM structure.
163 * @param pSSM The SSM handle.
164 */
165static int gicR3SaveVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
166{
167 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
168 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
169
170 pHlp->pfnSSMPutU32( pSSM, pVM->cCpus);
171 pHlp->pfnSSMPutU32( pSSM, GIC_SPI_MAX);
172 pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegIGrp0);
173 pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg0);
174 pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg1);
175 pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntEnabled);
176 pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntPending);
177 pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntActive);
178 pHlp->pfnSSMPutMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
179 pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp0Enabled);
180
181 return pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp1Enabled);
182}
183
184
185/**
186 * Worker for loading per-VM GIC data.
187 *
188 * @returns VBox status code.
189 * @param pDevIns The device instance.
190 * @param pVM The cross context VM structure.
191 * @param pSSM The SSM handle.
192 */
193static int gicR3LoadVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
194{
195 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
196 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
197
198 /* Load and verify number of CPUs. */
199 uint32_t cCpus;
200 int rc = pHlp->pfnSSMGetU32(pSSM, &cCpus);
201 AssertRCReturn(rc, rc);
202 if (cCpus != pVM->cCpus)
203 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
204
205 /* Load and verify maximum number of SPIs. */
206 uint32_t cSpisMax;
207 rc = pHlp->pfnSSMGetU32(pSSM, &cSpisMax);
208 AssertRCReturn(rc, rc);
209 if (cSpisMax != GIC_SPI_MAX)
210 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cSpisMax: saved=%u config=%u"),
211 cSpisMax, GIC_SPI_MAX);
212
213 /* Load the state. */
214 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegIGrp0);
215 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg0);
216 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg1);
217 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntEnabled);
218 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntPending);
219 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntActive);
220 pHlp->pfnSSMGetMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
221 pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp0Enabled);
222 pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp1Enabled);
223
224 return VINF_SUCCESS;
225}
226
227
228/**
229 * @copydoc FNSSMDEVSAVEEXEC
230 */
231static DECLCALLBACK(int) gicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
232{
233 PVM pVM = PDMDevHlpGetVM(pDevIns);
234 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
235
236 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
237
238 LogFlow(("GIC: gicR3SaveExec\n"));
239
240 /* Save per-VM data. */
241 int rc = gicR3SaveVMData(pDevIns, pVM, pSSM);
242 AssertRCReturn(rc, rc);
243
244 /* Save per-VCPU data.*/
245 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
246 {
247 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
248 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
249
250 /* Load the redistributor state. */
251 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegIGrp0);
252 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg0);
253 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg1);
254 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntEnabled);
255 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntPending);
256 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntActive);
257 pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
258
259 pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp0Enabled);
260 pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp1Enabled);
261 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bInterruptPriority);
262 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp0);
263 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp1);
264 pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
265 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->idxRunningPriority);
266 }
267
268 return rc;
269}
270
271
272/**
273 * @copydoc FNSSMDEVLOADEXEC
274 */
275static DECLCALLBACK(int) gicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
276{
277 PVM pVM = PDMDevHlpGetVM(pDevIns);
278 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
279
280 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
281 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
282
283 LogFlow(("GIC: gicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
284
285 /* Weed out invalid versions. */
286 if (uVersion != GIC_SAVED_STATE_VERSION)
287 {
288 LogRel(("GIC: gicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
289 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
290 }
291
292 int rc = gicR3LoadVMData(pDevIns, pVM, pSSM);
293 AssertRCReturn(rc, rc);
294
295 /*
296 * Restore per CPU state.
297 *
298 * Note! PDM will restore the VMCPU_FF_INTERRUPT_IRQ and VMCPU_FF_INTERRUPT_FIQ flags for us.
299 * This code doesn't touch it. No devices should make us touch
300 * it later during the restore either, only during the 'done' phase.
301 */
302 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
303 {
304 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
305 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
306
307 /* Load the redistributor state. */
308 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegIGrp0);
309 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg0);
310 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg1);
311 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntEnabled);
312 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntPending);
313 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntActive);
314 pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
315
316 pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp0Enabled);
317 pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp1Enabled);
318 pHlp->pfnSSMGetU8V( pSSM, &pGicVCpu->bInterruptPriority);
319 pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp0);
320 pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp1);
321 pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
322 rc = pHlp->pfnSSMGetU8V(pSSM, &pGicVCpu->idxRunningPriority);
323 if (RT_FAILURE(rc))
324 return rc;
325 }
326
327 return rc;
328}
329
330
331/**
332 * @interface_method_impl{PDMDEVREG,pfnReset}
333 */
334DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
335{
336 PVM pVM = PDMDevHlpGetVM(pDevIns);
337 VM_ASSERT_EMT0(pVM);
338 VM_ASSERT_IS_NOT_RUNNING(pVM);
339
340 LogFlow(("GIC: gicR3Reset\n"));
341
342 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
343 {
344 PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
345
346 gicResetCpu(pVCpuDest);
347 }
348}
349
350
351/**
352 * @interface_method_impl{PDMDEVREG,pfnRelocate}
353 */
354DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
355{
356 RT_NOREF(pDevIns, offDelta);
357}
358
359
360/**
361 * Initializes the GIC state.
362 *
363 * @returns VBox status code.
364 * @param pVM The cross context VM structure.
365 */
366static int gicR3InitState(PVM pVM)
367{
368 LogFlowFunc(("pVM=%p\n", pVM));
369
370 RT_NOREF(pVM);
371 return VINF_SUCCESS;
372}
373
374
375/**
376 * @interface_method_impl{PDMDEVREG,pfnDestruct}
377 */
378DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
379{
380 LogFlowFunc(("pDevIns=%p\n", pDevIns));
381 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
382
383 return VINF_SUCCESS;
384}
385
386
387/**
388 * @interface_method_impl{PDMDEVREG,pfnConstruct}
389 */
390DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
391{
392 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
393 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
394 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
395 PVM pVM = PDMDevHlpGetVM(pDevIns);
396 PGIC pGic = VM_TO_GIC(pVM);
397 Assert(iInstance == 0); NOREF(iInstance);
398
399 /*
400 * Init the data.
401 */
402 pGic->pDevInsR3 = pDevIns;
403
404 /*
405 * Validate GIC settings.
406 */
407 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase|RedistributorMmioBase", "");
408
409#if 0
410 /*
411 * Disable automatic PDM locking for this device.
412 */
413 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
414 AssertRCReturn(rc, rc);
415#else
416 int rc;
417#endif
418
419 /*
420 * Register the GIC with PDM.
421 */
422 rc = PDMDevHlpApicRegister(pDevIns);
423 AssertLogRelRCReturn(rc, rc);
424
425 /*
426 * Initialize the GIC state.
427 */
428 for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GICv3); i++)
429 {
430 rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GICv3[i]);
431 AssertLogRelRCReturn(rc, rc);
432 }
433
434 /* Finally, initialize the state. */
435 rc = gicR3InitState(pVM);
436 AssertRCReturn(rc, rc);
437
438 /*
439 * Register the MMIO ranges.
440 */
441 RTGCPHYS GCPhysMmioBase = 0;
442 rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
443 if (RT_FAILURE(rc))
444 return PDMDEV_SET_ERROR(pDevIns, rc,
445 N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
446
447 rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
448 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GICv3_Dist", &pGicDev->hMmioDist);
449 AssertRCReturn(rc, rc);
450
451 rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
452 if (RT_FAILURE(rc))
453 return PDMDEV_SET_ERROR(pDevIns, rc,
454 N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
455
456 RTGCPHYS cbRegion = pVM->cCpus * (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
457 rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
458 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GICv3_ReDist", &pGicDev->hMmioReDist);
459 AssertRCReturn(rc, rc);
460
461 /*
462 * Register saved state callbacks.
463 */
464 rc = PDMDevHlpSSMRegister(pDevIns, GIC_SAVED_STATE_VERSION, 0, gicR3SaveExec, gicR3LoadExec);
465 AssertRCReturn(rc, rc);
466
467 /*
468 * Register debugger info callbacks.
469 *
470 * We use separate callbacks rather than arguments so they can also be
471 * dumped in an automated fashion while collecting crash diagnostics and
472 * not just used during live debugging via the VM debugger.
473 */
474 DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
475 DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC Distributor information.", gicR3InfoDist, DBGFINFO_FLAGS_ALL_EMTS);
476 DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC Redistributor information.", gicR3InfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
477
478 /*
479 * Statistics.
480 */
481#define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
482 PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, \
483 STAMUNIT_OCCURENCES, a_pszDesc, a_pszNameFmt, idCpu)
484#define GIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
485 PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, \
486 STAMUNIT_TICKS_PER_CALL, a_pszDesc, a_pszNameFmt, idCpu)
487
488#ifdef VBOX_WITH_STATISTICS
489 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
490 {
491 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
492 PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
493
494# if 0 /* No R0 for now. */
495 GIC_REG_COUNTER(&pGicCpu->StatMmioReadRZ, "%u/RZ/MmioRead", "Number of APIC MMIO reads in RZ.");
496 GIC_REG_COUNTER(&pGicCpu->StatMmioWriteRZ, "%u/RZ/MmioWrite", "Number of APIC MMIO writes in RZ.");
497 GIC_REG_COUNTER(&pGicCpu->StatMsrReadRZ, "%u/RZ/MsrRead", "Number of APIC MSR reads in RZ.");
498 GIC_REG_COUNTER(&pGicCpu->StatMsrWriteRZ, "%u/RZ/MsrWrite", "Number of APIC MSR writes in RZ.");
499# endif
500
501 GIC_REG_COUNTER(&pGicCpu->StatMmioReadR3, "%u/R3/MmioRead", "Number of APIC MMIO reads in R3.");
502 GIC_REG_COUNTER(&pGicCpu->StatMmioWriteR3, "%u/R3/MmioWrite", "Number of APIC MMIO writes in R3.");
503 GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3, "%u/R3/SysRegRead", "Number of GIC system register reads in R3.");
504 GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/R3/SysRegWrite", "Number of GIC system register writes in R3.");
505 }
506#endif
507
508# undef GIC_PROF_COUNTER
509
510 gicR3Reset(pDevIns);
511 return VINF_SUCCESS;
512}
513
514#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
515
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