VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 80007

Last change on this file since 80007 was 80007, checked in by vboxsync, 5 years ago

VMM: Kicking out raw-mode (work in progress). bugref:9517
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 58.3 KB
Line 
1/* $Id: EMRaw.cpp 80007 2019-07-26 13:57:38Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager - software virtualization
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_EM
23#define VMCPU_INCL_CPUM_GST_CTX
24#include <VBox/vmm/em.h>
25#include <VBox/vmm/vmm.h>
26#include <VBox/vmm/selm.h>
27#include <VBox/vmm/trpm.h>
28#include <VBox/vmm/iem.h>
29#include <VBox/vmm/iom.h>
30#include <VBox/vmm/dbgf.h>
31#include <VBox/vmm/pgm.h>
32#ifdef VBOX_WITH_REM
33# include <VBox/vmm/rem.h>
34#endif
35#include <VBox/vmm/tm.h>
36#include <VBox/vmm/mm.h>
37#include <VBox/vmm/ssm.h>
38#include <VBox/vmm/pdmapi.h>
39#include <VBox/vmm/pdmcritsect.h>
40#include <VBox/vmm/pdmqueue.h>
41#include <VBox/vmm/patm.h>
42#include "EMInternal.h"
43#include <VBox/vmm/vm.h>
44#include <VBox/vmm/gim.h>
45#include <VBox/vmm/cpumdis.h>
46#include <VBox/dis.h>
47#include <VBox/disopcode.h>
48#include <VBox/vmm/dbgf.h>
49#include "VMMTracing.h"
50
51#include <VBox/err.h>
52#include <VBox/log.h>
53#include <iprt/asm.h>
54#include <iprt/string.h>
55#include <iprt/stream.h>
56
57
58
59/*********************************************************************************************************************************
60* Internal Functions *
61*********************************************************************************************************************************/
62static int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, int rc);
63static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu);
64DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
65static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
66static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, int gcret);
67static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
68static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
69static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
70static int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, int rc);
71
72#define EMHANDLERC_WITH_PATM
73#define emR3ExecuteInstruction emR3RawExecuteInstruction
74#define emR3ExecuteIOInstruction emR3RawExecuteIOInstruction
75#include "EMHandleRCTmpl.h"
76
77
78
79#ifdef VBOX_WITH_STATISTICS
80/**
81 * Just a braindead function to keep track of cli addresses.
82 * @param pVM The cross context VM structure.
83 * @param pVCpu The cross context virtual CPU structure.
84 * @param GCPtrInstr The EIP of the cli instruction.
85 */
86static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
87{
88 PCLISTAT pRec;
89
90 pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
91 if (!pRec)
92 {
93 /* New cli instruction; insert into the tree. */
94 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
95 Assert(pRec);
96 if (!pRec)
97 return;
98 pRec->Core.Key = GCPtrInstr;
99
100 char szCliStatName[32];
101 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
102 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
103
104 bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
105 Assert(fRc); NOREF(fRc);
106 }
107 STAM_COUNTER_INC(&pRec->Counter);
108 STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
109}
110#endif /* VBOX_WITH_STATISTICS */
111
112
113
114/**
115 * Resumes executing hypervisor after a debug event.
116 *
117 * This is kind of special since our current guest state is
118 * potentially out of sync.
119 *
120 * @returns VBox status code.
121 * @param pVM The cross context VM structure.
122 * @param pVCpu The cross context virtual CPU structure.
123 */
124int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
125{
126 int rc;
127 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
128 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags));
129
130 /*
131 * Resume execution.
132 */
133 CPUMRawEnter(pVCpu);
134 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
135 rc = VMMR3ResumeHyper(pVM, pVCpu);
136 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags, rc));
137 rc = CPUMRawLeave(pVCpu, rc);
138 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
139
140 /*
141 * Deal with the return code.
142 */
143 rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc));
144 rc = emR3RawHandleRC(pVM, pVCpu, rc);
145 rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
146 return rc;
147}
148
149
150/**
151 * Steps rawmode.
152 *
153 * @returns VBox status code.
154 * @param pVM The cross context VM structure.
155 * @param pVCpu The cross context virtual CPU structure.
156 */
157int emR3RawStep(PVM pVM, PVMCPU pVCpu)
158{
159 Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
160 || pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
161 || pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
162 int rc;
163 bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
164#ifndef DEBUG_sander
165 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
166 fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
167#endif
168 if (fGuest)
169 {
170 /*
171 * Check vital forced actions, but ignore pending interrupts and timers.
172 */
173 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
174 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
175 {
176 rc = emR3RawForcedActions(pVM, pVCpu);
177 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
178 if (rc != VINF_SUCCESS)
179 return rc;
180 }
181
182 /*
183 * Set flags for single stepping.
184 */
185 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
186 }
187 else
188 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
189
190 /*
191 * Single step.
192 * We do not start time or anything, if anything we should just do a few nanoseconds.
193 */
194 CPUMRawEnter(pVCpu);
195 do
196 {
197 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
198 rc = VMMR3ResumeHyper(pVM, pVCpu);
199 else
200 rc = VMMR3RawRunGC(pVM, pVCpu);
201#ifndef DEBUG_sander
202 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
203 fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
204#endif
205 } while ( rc == VINF_SUCCESS
206 || rc == VINF_EM_RAW_INTERRUPT);
207 rc = CPUMRawLeave(pVCpu, rc);
208 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
209
210 /*
211 * Make sure the trap flag is cleared.
212 * (Too bad if the guest is trying to single step too.)
213 */
214 if (fGuest)
215 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
216 else
217 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
218
219 /*
220 * Deal with the return codes.
221 */
222 rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc));
223 rc = emR3RawHandleRC(pVM, pVCpu, rc);
224 rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
225 return rc;
226}
227
228
229#ifdef DEBUG
230
231
232int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
233{
234 int rc = VINF_SUCCESS;
235 EMSTATE enmOldState = pVCpu->em.s.enmState;
236 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
237
238 Log(("Single step BEGIN:\n"));
239 for (uint32_t i = 0; i < cIterations; i++)
240 {
241 DBGFR3PrgStep(pVCpu);
242 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
243 rc = emR3RawStep(pVM, pVCpu);
244 if ( rc != VINF_SUCCESS
245 && rc != VINF_EM_DBG_STEPPED)
246 break;
247 }
248 Log(("Single step END: rc=%Rrc\n", rc));
249 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
250 pVCpu->em.s.enmState = enmOldState;
251 return rc;
252}
253
254#endif /* DEBUG */
255
256
257/**
258 * Executes one (or perhaps a few more) instruction(s).
259 *
260 * @returns VBox status code suitable for EM.
261 *
262 * @param pVM The cross context VM structure.
263 * @param pVCpu The cross context virtual CPU structure.
264 * @param rcGC GC return code
265 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
266 * instruction and prefix the log output with this text.
267 */
268#if defined(LOG_ENABLED) || defined(DOXYGEN_RUNNING)
269static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
270#else
271static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
272#endif
273{
274 int rc;
275
276#ifdef LOG_ENABLED
277 /*
278 * Disassemble the instruction if requested.
279 */
280 if (pszPrefix)
281 {
282 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", pszPrefix);
283 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
284 }
285#endif /* LOG_ENABLED */
286
287 /*
288 * PATM is making life more interesting.
289 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
290 * tell PATM there is a trap in this code and have it take the appropriate actions
291 * to allow us execute the code in REM.
292 */
293 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
294 {
295 Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pVCpu->cpum.GstCtx.eip));
296
297 RTGCPTR uNewEip;
298 rc = PATMR3HandleTrap(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip, &uNewEip);
299 switch (rc)
300 {
301 /*
302 * It's not very useful to emulate a single instruction and then go back to raw
303 * mode; just execute the whole block until IF is set again.
304 */
305 case VINF_SUCCESS:
306 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
307 uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
308 pVCpu->cpum.GstCtx.eip = uNewEip;
309 Assert(pVCpu->cpum.GstCtx.eip);
310
311 if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
312 {
313 /*
314 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
315 */
316 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
317 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
318 }
319 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
320 {
321 /* special case: iret, that sets IF, detected a pending irq/event */
322 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
323 }
324 return VINF_EM_RESCHEDULE_REM;
325
326 /*
327 * One instruction.
328 */
329 case VINF_PATCH_EMULATE_INSTR:
330 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
331 uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
332 pVCpu->cpum.GstCtx.eip = uNewEip;
333 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
334
335 /*
336 * The patch was disabled, hand it to the REM.
337 */
338 case VERR_PATCH_DISABLED:
339 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
340 uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
341 pVCpu->cpum.GstCtx.eip = uNewEip;
342 if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
343 {
344 /*
345 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
346 */
347 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
348 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
349 }
350 return VINF_EM_RESCHEDULE_REM;
351
352 /* Force continued patch exection; usually due to write monitored stack. */
353 case VINF_PATCH_CONTINUE:
354 return VINF_SUCCESS;
355
356 default:
357 AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
358 return VERR_IPE_UNEXPECTED_STATUS;
359 }
360 }
361
362
363 /*
364 * Use IEM and fallback on REM if the functionality is missing.
365 * Once IEM gets mature enough, nothing should ever fall back.
366 */
367#define VBOX_WITH_FIRST_IEM_STEP_B
368#if defined(VBOX_WITH_FIRST_IEM_STEP_B) || !defined(VBOX_WITH_REM)
369 Log(("EMINS: %04x:%RGv RSP=%RGv\n", pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, (RTGCPTR)pVCpu->cpum.GstCtx.rsp));
370 STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
371 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
372 STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
373 if (RT_SUCCESS(rc))
374 {
375 if (rc == VINF_SUCCESS || rc == VINF_EM_RESCHEDULE)
376 rc = VINF_EM_RESCHEDULE;
377 }
378 else if ( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
379 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED)
380#endif
381 {
382#ifdef VBOX_WITH_REM
383 STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, b);
384# ifndef VBOX_WITH_FIRST_IEM_STEP_B
385 Log(("EMINS[rem]: %04x:%RGv RSP=%RGv\n", pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, (RTGCPTR)pVCpu->cpum.GstCtx.rsp));
386//# elif defined(DEBUG_bird)
387// AssertFailed();
388# endif
389 EMRemLock(pVM);
390 /* Flush the recompiler TLB if the VCPU has changed. */
391 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
392 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
393 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
394
395 rc = REMR3EmulateInstruction(pVM, pVCpu);
396 EMRemUnlock(pVM);
397 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, b);
398#else /* !VBOX_WITH_REM */
399 NOREF(pVM);
400#endif /* !VBOX_WITH_REM */
401 }
402 return rc;
403}
404
405
406/**
407 * Executes one (or perhaps a few more) instruction(s).
408 * This is just a wrapper for discarding pszPrefix in non-logging builds.
409 *
410 * @returns VBox status code suitable for EM.
411 * @param pVM The cross context VM structure.
412 * @param pVCpu The cross context virtual CPU structure.
413 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
414 * instruction and prefix the log output with this text.
415 * @param rcGC GC return code
416 */
417DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
418{
419#ifdef LOG_ENABLED
420 return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
421#else
422 RT_NOREF_PV(pszPrefix);
423 return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
424#endif
425}
426
427/**
428 * Executes one (or perhaps a few more) IO instruction(s).
429 *
430 * @returns VBox status code suitable for EM.
431 * @param pVM The cross context VM structure.
432 * @param pVCpu The cross context virtual CPU structure.
433 */
434static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
435{
436 STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
437 RT_NOREF_PV(pVM);
438
439 /* Hand it over to the interpreter. */
440 VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
441 LogFlow(("emR3RawExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
442 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
443 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
444 return VBOXSTRICTRC_TODO(rcStrict);
445}
446
447
448/**
449 * Handle a guest context trap.
450 *
451 * @returns VBox status code suitable for EM.
452 * @param pVM The cross context VM structure.
453 * @param pVCpu The cross context virtual CPU structure.
454 */
455static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
456{
457 /*
458 * Get the trap info.
459 */
460 uint8_t u8TrapNo;
461 TRPMEVENT enmType;
462 RTGCUINT uErrorCode;
463 RTGCUINTPTR uCR2;
464 int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
465 if (RT_FAILURE(rc))
466 {
467 AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
468 return rc;
469 }
470
471
472#if 1 /* Experimental: Review, disable if it causes trouble. */
473 /*
474 * Handle traps in patch code first.
475 *
476 * We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
477 * but several traps isn't handled specially by TRPM in RC and we end up here
478 * instead. One example is #DE.
479 */
480 uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
481 if ( uCpl == 0
482 && PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
483 {
484 LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pVCpu->cpum.GstCtx.eip));
485 return emR3RawPatchTrap(pVM, pVCpu, rc);
486 }
487#endif
488
489 /*
490 * If the guest gate is marked unpatched, then we will check again if we can patch it.
491 * (This assumes that we've already tried and failed to dispatch the trap in
492 * RC for the gates that already has been patched. Which is true for most high
493 * volume traps, because these are handled specially, but not for odd ones like #DE.)
494 */
495 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
496 {
497 CSAMR3CheckGates(pVM, u8TrapNo, 1);
498 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
499
500 /* If it was successful, then we could go back to raw mode. */
501 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
502 {
503 /* Must check pending forced actions as our IDT or GDT might be out of sync. */
504 rc = EMR3CheckRawForcedActions(pVM, pVCpu);
505 AssertRCReturn(rc, rc);
506
507 TRPMERRORCODE enmError = uErrorCode != ~0U
508 ? TRPM_TRAP_HAS_ERRORCODE
509 : TRPM_TRAP_NO_ERRORCODE;
510 rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
511 if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
512 {
513 TRPMResetTrap(pVCpu);
514 return VINF_EM_RESCHEDULE_RAW;
515 }
516 AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
517 }
518 }
519
520 /*
521 * Scan kernel code that traps; we might not get another chance.
522 */
523 /** @todo move this up before the dispatching? */
524 if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) <= 1
525 && !pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
526 {
527 Assert(!PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip));
528 CSAMR3CheckCodeEx(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip);
529 }
530
531 /*
532 * Trap specific handling.
533 */
534 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
535 {
536 /*
537 * If MONITOR & MWAIT are supported, then interpret them here.
538 */
539 DISCPUSTATE cpu;
540 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &cpu, "Guest Trap (#UD): ");
541 if ( RT_SUCCESS(rc)
542 && (cpu.pCurInstr->uOpcode == OP_MONITOR || cpu.pCurInstr->uOpcode == OP_MWAIT))
543 {
544 uint32_t u32Dummy, u32Features, u32ExtFeatures;
545 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
546 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
547 {
548 rc = TRPMResetTrap(pVCpu);
549 AssertRC(rc);
550
551 rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &cpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx),
552 0, EMCODETYPE_SUPERVISOR));
553 if (RT_SUCCESS(rc))
554 return rc;
555 return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
556 }
557 }
558 }
559 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
560 {
561 /*
562 * Handle I/O bitmap?
563 */
564 /** @todo We're not supposed to be here with a false guest trap concerning
565 * I/O access. We can easily handle those in RC. */
566 DISCPUSTATE cpu;
567 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &cpu, "Guest Trap: ");
568 if ( RT_SUCCESS(rc)
569 && (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
570 {
571 /*
572 * We should really check the TSS for the IO bitmap, but it's not like this
573 * lazy approach really makes things worse.
574 */
575 rc = TRPMResetTrap(pVCpu);
576 AssertRC(rc);
577 return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
578 }
579 }
580
581#ifdef LOG_ENABLED
582 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "Guest trap");
583 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Guest trap");
584
585 /* Get guest page information. */
586 uint64_t fFlags = 0;
587 RTGCPHYS GCPhys = 0;
588 int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
589 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
590 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pVCpu->cpum.GstCtx.cr0,
591 (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
592 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
593 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
594#endif
595
596 /*
597 * #PG has CR2.
598 * (Because of stuff like above we must set CR2 in a delayed fashion.)
599 */
600 if (u8TrapNo == 14 /* #PG */)
601 pVCpu->cpum.GstCtx.cr2 = uCR2;
602
603 return VINF_EM_RESCHEDULE_REM;
604}
605
606
607/**
608 * Handle a ring switch trap.
609 * Need to do statistics and to install patches. The result is going to REM.
610 *
611 * @returns VBox status code suitable for EM.
612 * @param pVM The cross context VM structure.
613 * @param pVCpu The cross context virtual CPU structure.
614 */
615static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
616{
617 int rc;
618 DISCPUSTATE Cpu;
619
620 /*
621 * sysenter, syscall & callgate
622 */
623 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &Cpu, "RSWITCH: ");
624 if (RT_SUCCESS(rc))
625 {
626 if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
627 {
628 if (pVCpu->cpum.GstCtx.SysEnter.cs != 0)
629 {
630 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.eip),
631 CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
632 if (RT_SUCCESS(rc))
633 {
634 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched sysenter instruction");
635 return VINF_EM_RESCHEDULE_RAW;
636 }
637 }
638 }
639
640#ifdef VBOX_WITH_STATISTICS
641 switch (Cpu.pCurInstr->uOpcode)
642 {
643 case OP_SYSENTER:
644 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
645 break;
646 case OP_SYSEXIT:
647 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
648 break;
649 case OP_SYSCALL:
650 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
651 break;
652 case OP_SYSRET:
653 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
654 break;
655 }
656#endif
657 }
658 else
659 AssertRC(rc);
660
661 /* go to the REM to emulate a single instruction */
662 return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
663}
664
665
666/**
667 * Handle a trap (\#PF or \#GP) in patch code
668 *
669 * @returns VBox status code suitable for EM.
670 * @param pVM The cross context VM structure.
671 * @param pVCpu The cross context virtual CPU structure.
672 * @param gcret GC return code.
673 */
674static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, int gcret)
675{
676 uint8_t u8TrapNo;
677 int rc;
678 TRPMEVENT enmType;
679 RTGCUINT uErrorCode;
680 RTGCUINTPTR uCR2;
681
682 Assert(PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip));
683
684 if (gcret == VINF_PATM_PATCH_INT3)
685 {
686 u8TrapNo = 3;
687 uCR2 = 0;
688 uErrorCode = 0;
689 }
690 else if (gcret == VINF_PATM_PATCH_TRAP_GP)
691 {
692 /* No active trap in this case. Kind of ugly. */
693 u8TrapNo = X86_XCPT_GP;
694 uCR2 = 0;
695 uErrorCode = 0;
696 }
697 else
698 {
699 rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
700 if (RT_FAILURE(rc))
701 {
702 AssertReleaseMsgFailed(("emR3RawPatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
703 return rc;
704 }
705 /* Reset the trap as we'll execute the original instruction again. */
706 TRPMResetTrap(pVCpu);
707 }
708
709 /*
710 * Deal with traps inside patch code.
711 * (This code won't run outside GC.)
712 */
713 if (u8TrapNo != 1)
714 {
715#ifdef LOG_ENABLED
716 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "Trap in patch code");
717 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patch code");
718
719 DISCPUSTATE Cpu;
720 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip, &Cpu, "Patch code: ");
721 if ( RT_SUCCESS(rc)
722 && Cpu.pCurInstr->uOpcode == OP_IRET)
723 {
724 uint32_t eip, selCS, uEFlags;
725
726 /* Iret crashes are bad as we have already changed the flags on the stack */
727 rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pVCpu->cpum.GstCtx.esp, 4);
728 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pVCpu->cpum.GstCtx.esp+4, 4);
729 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pVCpu->cpum.GstCtx.esp+8, 4);
730 if (rc == VINF_SUCCESS)
731 {
732 if ( (uEFlags & X86_EFL_VM)
733 || (selCS & X86_SEL_RPL) == 3)
734 {
735 uint32_t selSS, esp;
736
737 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pVCpu->cpum.GstCtx.esp + 12, 4);
738 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pVCpu->cpum.GstCtx.esp + 16, 4);
739
740 if (uEFlags & X86_EFL_VM)
741 {
742 uint32_t selDS, selES, selFS, selGS;
743 rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pVCpu->cpum.GstCtx.esp + 20, 4);
744 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pVCpu->cpum.GstCtx.esp + 24, 4);
745 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pVCpu->cpum.GstCtx.esp + 28, 4);
746 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pVCpu->cpum.GstCtx.esp + 32, 4);
747 if (rc == VINF_SUCCESS)
748 {
749 Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
750 Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
751 }
752 }
753 else
754 Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
755 }
756 else
757 Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
758 }
759 }
760#endif /* LOG_ENABLED */
761 Log(("emR3RawPatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
762 pVCpu->cpum.GstCtx.eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pVCpu->cpum.GstCtx.cr0));
763
764 RTGCPTR uNewEip;
765 rc = PATMR3HandleTrap(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip, &uNewEip);
766 switch (rc)
767 {
768 /*
769 * Execute the faulting instruction.
770 */
771 case VINF_SUCCESS:
772 {
773 /** @todo execute a whole block */
774 Log(("emR3RawPatchTrap: Executing faulting instruction at new address %RGv\n", uNewEip));
775 if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
776 Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
777
778 pVCpu->cpum.GstCtx.eip = uNewEip;
779 AssertRelease(pVCpu->cpum.GstCtx.eip);
780
781 if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
782 {
783 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
784 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
785 */
786 if ( u8TrapNo == X86_XCPT_GP
787 && PATMIsInt3Patch(pVM, pVCpu->cpum.GstCtx.eip, NULL, NULL))
788 {
789 /** @todo move to PATMR3HandleTrap */
790 Log(("Possible Windows XP iret fault at %08RX32\n", pVCpu->cpum.GstCtx.eip));
791 PATMR3RemovePatch(pVM, pVCpu->cpum.GstCtx.eip);
792 }
793
794 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
795 /* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
796
797 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
798 /* Interrupts are enabled; just go back to the original instruction.
799 return VINF_SUCCESS; */
800 }
801 return VINF_EM_RESCHEDULE_REM;
802 }
803
804 /*
805 * One instruction.
806 */
807 case VINF_PATCH_EMULATE_INSTR:
808 Log(("emR3RawPatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
809 uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
810 pVCpu->cpum.GstCtx.eip = uNewEip;
811 AssertRelease(pVCpu->cpum.GstCtx.eip);
812 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
813
814 /*
815 * The patch was disabled, hand it to the REM.
816 */
817 case VERR_PATCH_DISABLED:
818 if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
819 Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
820 pVCpu->cpum.GstCtx.eip = uNewEip;
821 AssertRelease(pVCpu->cpum.GstCtx.eip);
822
823 if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
824 {
825 /*
826 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
827 */
828 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
829 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
830 }
831 return VINF_EM_RESCHEDULE_REM;
832
833 /* Force continued patch exection; usually due to write monitored stack. */
834 case VINF_PATCH_CONTINUE:
835 return VINF_SUCCESS;
836
837 /*
838 * Anything else is *fatal*.
839 */
840 default:
841 AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
842 return VERR_IPE_UNEXPECTED_STATUS;
843 }
844 }
845 return VINF_SUCCESS;
846}
847
848
849/**
850 * Handle a privileged instruction.
851 *
852 * @returns VBox status code suitable for EM.
853 * @param pVM The cross context VM structure.
854 * @param pVCpu The cross context virtual CPU structure.
855 */
856static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
857{
858 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
859
860 if (PATMIsEnabled(pVM))
861 {
862 /*
863 * Check if in patch code.
864 */
865 if (PATMR3IsInsidePatchJump(pVM, pVCpu->cpum.GstCtx.eip, NULL))
866 {
867#ifdef LOG_ENABLED
868 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
869#endif
870 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08x\n", pVCpu->cpum.GstCtx.eip));
871 return VERR_EM_RAW_PATCH_CONFLICT;
872 }
873 if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 0
874 && !pVCpu->cpum.GstCtx.eflags.Bits.u1VM
875 && !PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
876 {
877 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.eip),
878 CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
879 if (RT_SUCCESS(rc))
880 {
881#ifdef LOG_ENABLED
882 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
883#endif
884 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched privileged instruction");
885 return VINF_SUCCESS;
886 }
887 }
888 }
889
890#ifdef LOG_ENABLED
891 if (!PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
892 {
893 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
894 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
895 }
896#endif
897
898 /*
899 * Instruction statistics and logging.
900 */
901 DISCPUSTATE Cpu;
902 int rc;
903
904 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &Cpu, "PRIV: ");
905 if (RT_SUCCESS(rc))
906 {
907#ifdef VBOX_WITH_STATISTICS
908 PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
909 switch (Cpu.pCurInstr->uOpcode)
910 {
911 case OP_INVLPG:
912 STAM_COUNTER_INC(&pStats->StatInvlpg);
913 break;
914 case OP_IRET:
915 STAM_COUNTER_INC(&pStats->StatIret);
916 break;
917 case OP_CLI:
918 STAM_COUNTER_INC(&pStats->StatCli);
919 emR3RecordCli(pVM, pVCpu, pVCpu->cpum.GstCtx.rip);
920 break;
921 case OP_STI:
922 STAM_COUNTER_INC(&pStats->StatSti);
923 break;
924 case OP_INSB:
925 case OP_INSWD:
926 case OP_IN:
927 case OP_OUTSB:
928 case OP_OUTSWD:
929 case OP_OUT:
930 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
931 break;
932
933 case OP_MOV_CR:
934 if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
935 {
936 //read
937 Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
938 Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
939 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
940 }
941 else
942 {
943 //write
944 Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
945 Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
946 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
947 }
948 break;
949
950 case OP_MOV_DR:
951 STAM_COUNTER_INC(&pStats->StatMovDRx);
952 break;
953 case OP_LLDT:
954 STAM_COUNTER_INC(&pStats->StatMovLldt);
955 break;
956 case OP_LIDT:
957 STAM_COUNTER_INC(&pStats->StatMovLidt);
958 break;
959 case OP_LGDT:
960 STAM_COUNTER_INC(&pStats->StatMovLgdt);
961 break;
962 case OP_SYSENTER:
963 STAM_COUNTER_INC(&pStats->StatSysEnter);
964 break;
965 case OP_SYSEXIT:
966 STAM_COUNTER_INC(&pStats->StatSysExit);
967 break;
968 case OP_SYSCALL:
969 STAM_COUNTER_INC(&pStats->StatSysCall);
970 break;
971 case OP_SYSRET:
972 STAM_COUNTER_INC(&pStats->StatSysRet);
973 break;
974 case OP_HLT:
975 STAM_COUNTER_INC(&pStats->StatHlt);
976 break;
977 default:
978 STAM_COUNTER_INC(&pStats->StatMisc);
979 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
980 break;
981 }
982#endif /* VBOX_WITH_STATISTICS */
983 if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 0
984 && !pVCpu->cpum.GstCtx.eflags.Bits.u1VM
985 && CPUMGetGuestCodeBits(pVCpu) == 32)
986 {
987 STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
988 switch (Cpu.pCurInstr->uOpcode)
989 {
990 case OP_CLI:
991 pVCpu->cpum.GstCtx.eflags.u32 &= ~X86_EFL_IF;
992 Assert(Cpu.cbInstr == 1);
993 pVCpu->cpum.GstCtx.rip += Cpu.cbInstr;
994 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
995 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
996
997 case OP_STI:
998 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_IF;
999 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip + Cpu.cbInstr);
1000 Assert(Cpu.cbInstr == 1);
1001 pVCpu->cpum.GstCtx.rip += Cpu.cbInstr;
1002 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1003 return VINF_SUCCESS;
1004
1005 case OP_HLT:
1006 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1007 {
1008 PATMTRANSSTATE enmState;
1009 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pVCpu->cpum.GstCtx.eip, &enmState);
1010
1011 if (enmState == PATMTRANS_OVERWRITTEN)
1012 {
1013 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1014 Assert(rc == VERR_PATCH_DISABLED);
1015 /* Conflict detected, patch disabled */
1016 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pVCpu->cpum.GstCtx.eip));
1017
1018 enmState = PATMTRANS_SAFE;
1019 }
1020
1021 /* The translation had better be successful. Otherwise we can't recover. */
1022 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pVCpu->cpum.GstCtx.eip));
1023 if (enmState != PATMTRANS_OVERWRITTEN)
1024 pVCpu->cpum.GstCtx.eip = pOrgInstrGC;
1025 }
1026 /* no break; we could just return VINF_EM_HALT here */
1027 RT_FALL_THRU();
1028
1029 case OP_MOV_CR:
1030 case OP_MOV_DR:
1031#ifdef LOG_ENABLED
1032 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1033 {
1034 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
1035 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
1036 }
1037#endif
1038
1039 rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx),
1040 0, EMCODETYPE_SUPERVISOR));
1041 if (RT_SUCCESS(rc))
1042 {
1043 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1044
1045 if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR
1046 && Cpu.Param1.fUse == DISUSE_REG_CR /* write */
1047 )
1048 {
1049 /* Deal with CR0 updates inside patch code that force
1050 * us to go to the recompiler.
1051 */
1052 if ( PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.rip)
1053 && (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE)) != (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE))
1054 {
1055 PATMTRANSSTATE enmState;
1056 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pVCpu->cpum.GstCtx.rip, &enmState);
1057
1058 Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.rip, pOrgInstrGC, enmState));
1059 if (enmState == PATMTRANS_OVERWRITTEN)
1060 {
1061 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1062 Assert(rc == VERR_PATCH_DISABLED);
1063 /* Conflict detected, patch disabled */
1064 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pVCpu->cpum.GstCtx.rip));
1065 enmState = PATMTRANS_SAFE;
1066 }
1067 /* The translation had better be successful. Otherwise we can't recover. */
1068 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pVCpu->cpum.GstCtx.rip));
1069 if (enmState != PATMTRANS_OVERWRITTEN)
1070 pVCpu->cpum.GstCtx.rip = pOrgInstrGC;
1071 }
1072
1073 /* Reschedule is necessary as the execution/paging mode might have changed. */
1074 return VINF_EM_RESCHEDULE;
1075 }
1076 return rc; /* can return VINF_EM_HALT as well. */
1077 }
1078 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1079 break; /* fall back to the recompiler */
1080 }
1081 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1082 }
1083 }
1084
1085 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1086 return emR3RawPatchTrap(pVM, pVCpu, VINF_PATM_PATCH_TRAP_GP);
1087
1088 return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
1089}
1090
1091
1092/**
1093 * Update the forced rawmode execution modifier.
1094 *
1095 * This function is called when we're returning from the raw-mode loop(s). If we're
1096 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1097 * if not in patch code, the flag will be cleared.
1098 *
1099 * We should never interrupt patch code while it's being executed. Cli patches can
1100 * contain big code blocks, but they are always executed with IF=0. Other patches
1101 * replace single instructions and should be atomic.
1102 *
1103 * @returns Updated rc.
1104 *
1105 * @param pVM The cross context VM structure.
1106 * @param pVCpu The cross context virtual CPU structure.
1107 * @param rc The result code.
1108 */
1109static int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, int rc)
1110{
1111 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip)) /** @todo check cs selector base/type */
1112 {
1113 /* ignore reschedule attempts. */
1114 switch (rc)
1115 {
1116 case VINF_EM_RESCHEDULE:
1117 case VINF_EM_RESCHEDULE_REM:
1118 LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1119 rc = VINF_SUCCESS;
1120 break;
1121 }
1122 pVCpu->em.s.fForceRAW = true;
1123 }
1124 else
1125 pVCpu->em.s.fForceRAW = false;
1126 return rc;
1127}
1128
1129
1130/**
1131 * Check for pending raw actions
1132 *
1133 * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1134 * EM statuses.
1135 * @param pVM The cross context VM structure.
1136 * @param pVCpu The cross context virtual CPU structure.
1137 */
1138VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1139{
1140 int rc = emR3RawForcedActions(pVM, pVCpu);
1141 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1142 return rc;
1143}
1144
1145
1146/**
1147 * Process raw-mode specific forced actions.
1148 *
1149 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1150 *
1151 * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1152 * EM statuses.
1153 * @param pVM The cross context VM structure.
1154 * @param pVCpu The cross context virtual CPU structure.
1155 */
1156static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu)
1157{
1158 /*
1159 * Note that the order is *vitally* important!
1160 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1161 */
1162 VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1163
1164 /*
1165 * Sync selector tables.
1166 */
1167 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT))
1168 {
1169 VBOXSTRICTRC rcStrict = SELMR3UpdateFromCPUM(pVM, pVCpu);
1170 if (rcStrict != VINF_SUCCESS)
1171 return VBOXSTRICTRC_TODO(rcStrict);
1172 }
1173
1174 /*
1175 * Sync IDT.
1176 *
1177 * The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1178 * and PGMShwModifyPage, so we're in for trouble if for instance a
1179 * PGMSyncCR3+pgmR3PoolClearAll is pending.
1180 */
1181 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1182 {
1183 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1184 && EMIsRawRing0Enabled(pVM)
1185 && CSAMIsEnabled(pVM))
1186 {
1187 int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1188 if (RT_FAILURE(rc))
1189 return rc;
1190 }
1191
1192 int rc = TRPMR3SyncIDT(pVM, pVCpu);
1193 if (RT_FAILURE(rc))
1194 return rc;
1195 }
1196
1197 /*
1198 * Sync TSS.
1199 */
1200 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1201 {
1202 int rc = SELMR3SyncTSS(pVM, pVCpu);
1203 if (RT_FAILURE(rc))
1204 return rc;
1205 }
1206
1207 /*
1208 * Sync page directory.
1209 */
1210 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1211 {
1212 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1213 int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1214 if (RT_FAILURE(rc))
1215 return rc == VERR_PGM_NO_HYPERVISOR_ADDRESS ? VINF_EM_RESCHEDULE_REM : rc;
1216
1217 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
1218
1219 /* Prefetch pages for EIP and ESP. */
1220 /** @todo This is rather expensive. Should investigate if it really helps at all. */
1221 rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.rip));
1222 if (rc == VINF_SUCCESS)
1223 rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.rsp));
1224 if (rc != VINF_SUCCESS)
1225 {
1226 if (rc != VINF_PGM_SYNC_CR3)
1227 {
1228 AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1229 return rc;
1230 }
1231 rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1232 if (RT_FAILURE(rc))
1233 return rc;
1234 }
1235 /** @todo maybe prefetch the supervisor stack page as well */
1236 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
1237 }
1238
1239 /*
1240 * Allocate handy pages (just in case the above actions have consumed some pages).
1241 */
1242 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1243 {
1244 int rc = PGMR3PhysAllocateHandyPages(pVM);
1245 if (RT_FAILURE(rc))
1246 return rc;
1247 }
1248
1249 /*
1250 * Check whether we're out of memory now.
1251 *
1252 * This may stem from some of the above actions or operations that has been executed
1253 * since we ran FFs. The allocate handy pages must for instance always be followed by
1254 * this check.
1255 */
1256 if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
1257 return VINF_EM_NO_MEMORY;
1258
1259 return VINF_SUCCESS;
1260}
1261
1262
1263/**
1264 * Executes raw code.
1265 *
1266 * This function contains the raw-mode version of the inner
1267 * execution loop (the outer loop being in EMR3ExecuteVM()).
1268 *
1269 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1270 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1271 *
1272 * @param pVM The cross context VM structure.
1273 * @param pVCpu The cross context virtual CPU structure.
1274 * @param pfFFDone Where to store an indicator telling whether or not
1275 * FFs were done before returning.
1276 */
1277int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1278{
1279 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1280
1281 int rc = VERR_IPE_UNINITIALIZED_STATUS;
1282 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip));
1283 pVCpu->em.s.fForceRAW = false;
1284 *pfFFDone = false;
1285
1286
1287 /*
1288 *
1289 * Spin till we get a forced action or raw mode status code resulting in
1290 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1291 *
1292 */
1293 for (;;)
1294 {
1295 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1296
1297 /*
1298 * Check various preconditions.
1299 */
1300#ifdef VBOX_STRICT
1301 Assert(pVCpu->cpum.GstCtx.eflags.Bits.u1VM || (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 3 || (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 0
1302 || (EMIsRawRing1Enabled(pVM) && (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 1));
1303 AssertMsg( (pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_IF)
1304 || PATMShouldUseRawMode(pVM, (RTGCPTR)pVCpu->cpum.GstCtx.eip),
1305 ("Tried to execute code with IF at EIP=%08x!\n", pVCpu->cpum.GstCtx.eip));
1306 if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1307 && PGMMapHasConflicts(pVM))
1308 {
1309 PGMMapCheck(pVM);
1310 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1311 return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1312 }
1313#endif /* VBOX_STRICT */
1314
1315 /*
1316 * Process high priority pre-execution raw-mode FFs.
1317 */
1318 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1319 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1320 {
1321 rc = emR3RawForcedActions(pVM, pVCpu);
1322 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1323 if (rc != VINF_SUCCESS)
1324 break;
1325 }
1326
1327 /*
1328 * If we're going to execute ring-0 code, the guest state needs to
1329 * be modified a bit and some of the state components (IF, SS/CS RPL,
1330 * and perhaps EIP) needs to be stored with PATM.
1331 */
1332 rc = CPUMRawEnter(pVCpu);
1333 if (rc != VINF_SUCCESS)
1334 {
1335 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1336 break;
1337 }
1338
1339 /*
1340 * Scan code before executing it. Don't bother with user mode or V86 code
1341 */
1342 if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) <= 1
1343 && !pVCpu->cpum.GstCtx.eflags.Bits.u1VM
1344 && !PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1345 {
1346 STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1347 CSAMR3CheckCodeEx(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip);
1348 STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1349 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1350 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1351 {
1352 rc = emR3RawForcedActions(pVM, pVCpu);
1353 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1354 if (rc != VINF_SUCCESS)
1355 {
1356 rc = CPUMRawLeave(pVCpu, rc);
1357 break;
1358 }
1359 }
1360 }
1361
1362#ifdef LOG_ENABLED
1363 /*
1364 * Log important stuff before entering GC.
1365 */
1366 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1367 if (pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
1368 Log(("RV86: %04x:%08x IF=%d VMFlags=%x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags));
1369 else if ((pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 1)
1370 Log(("RR0: %x:%08x ESP=%x:%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n",
1371 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.esp, CPUMRawGetEFlags(pVCpu), !!(pGCState->uVMFlags & X86_EFL_IF), pVCpu->cpum.GstCtx.eflags.Bits.u1IF,
1372 pGCState->uVMFlags, pGCState->fPIF, (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL), CSAMIsPageScanned(pVM, (RTGCPTR)pVCpu->cpum.GstCtx.eip)));
1373# ifdef VBOX_WITH_RAW_RING1
1374 else if ((pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 2)
1375 Log(("RR1: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x CPL=%x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags, (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL)));
1376# endif
1377 else if ((pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 3)
1378 Log(("RR3: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags));
1379#endif /* LOG_ENABLED */
1380
1381
1382
1383 /*
1384 * Execute the code.
1385 */
1386 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1387 if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1388 {
1389 STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1390 VBOXVMM_EM_RAW_RUN_PRE(pVCpu, &pVCpu->cpum.GstCtx);
1391 rc = VMMR3RawRunGC(pVM, pVCpu);
1392 VBOXVMM_EM_RAW_RUN_RET(pVCpu, &pVCpu->cpum.GstCtx, rc);
1393 STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1394 }
1395 else
1396 {
1397 /* Give up this time slice; virtual time continues */
1398 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1399 RTThreadSleep(5);
1400 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1401 rc = VINF_SUCCESS;
1402 }
1403 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1404
1405 LogFlow(("RR%u-E: %08x ESP=%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d\n",
1406 (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL), pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.esp, CPUMRawGetEFlags(pVCpu),
1407 !!(pGCState->uVMFlags & X86_EFL_IF), pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF));
1408 LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1409
1410
1411
1412 /*
1413 * Restore the real CPU state and deal with high priority post
1414 * execution FFs before doing anything else.
1415 */
1416 rc = CPUMRawLeave(pVCpu, rc);
1417 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1418 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1419 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1420 rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc));
1421
1422#ifdef VBOX_STRICT
1423 /*
1424 * Assert TSS consistency & rc vs patch code.
1425 */
1426 if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1427 && EMIsRawRing0Enabled(pVM))
1428 SELMR3CheckTSS(pVM);
1429 switch (rc)
1430 {
1431 case VINF_SUCCESS:
1432 case VINF_EM_RAW_INTERRUPT:
1433 case VINF_PATM_PATCH_TRAP_PF:
1434 case VINF_PATM_PATCH_TRAP_GP:
1435 case VINF_PATM_PATCH_INT3:
1436 case VINF_PATM_CHECK_PATCH_PAGE:
1437 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1438 case VINF_EM_RAW_GUEST_TRAP:
1439 case VINF_EM_RESCHEDULE_RAW:
1440 break;
1441
1442 default:
1443 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip) && !(pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_TF))
1444 LogIt(0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1445 break;
1446 }
1447 /*
1448 * Let's go paranoid!
1449 */
1450 if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1451 && PGMMapHasConflicts(pVM))
1452 {
1453 PGMMapCheck(pVM);
1454 AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1455 return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1456 }
1457#endif /* VBOX_STRICT */
1458
1459 /*
1460 * Process the returned status code.
1461 */
1462 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1463 {
1464 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1465 break;
1466 }
1467 rc = emR3RawHandleRC(pVM, pVCpu, rc);
1468 if (rc != VINF_SUCCESS)
1469 {
1470 rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
1471 if (rc != VINF_SUCCESS)
1472 {
1473 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1474 break;
1475 }
1476 }
1477
1478 /*
1479 * Check and execute forced actions.
1480 */
1481#ifdef VBOX_HIGH_RES_TIMERS_HACK
1482 TMTimerPollVoid(pVM, pVCpu);
1483#endif
1484 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1485 if ( VM_FF_IS_ANY_SET(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK | VM_FF_PGM_NO_MEMORY)
1486 || VMCPU_FF_IS_ANY_SET(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1487 {
1488 Assert(pVCpu->cpum.GstCtx.eflags.Bits.u1VM || (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) != (EMIsRawRing1Enabled(pVM) ? 2U : 1U));
1489
1490 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1491 rc = emR3ForcedActions(pVM, pVCpu, rc);
1492 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1493 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1494 if ( rc != VINF_SUCCESS
1495 && rc != VINF_EM_RESCHEDULE_RAW)
1496 {
1497 rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
1498 if (rc != VINF_SUCCESS)
1499 {
1500 *pfFFDone = true;
1501 break;
1502 }
1503 }
1504 }
1505 }
1506
1507 /*
1508 * Return to outer loop.
1509 */
1510#if defined(LOG_ENABLED) && defined(DEBUG)
1511 RTLogFlush(NULL);
1512#endif
1513 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1514 return rc;
1515}
1516
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use