VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 74795

Last change on this file since 74795 was 74795, checked in by vboxsync, 6 years ago

vm.h,EM: Made the FF_SET and FF_CLEAR macros only take constants with _BIT variants. bugref:9180
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1/* $Id: EMRaw.cpp 74795 2018-10-12 11:24:11Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager - software virtualization
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_EM
23#define VMCPU_INCL_CPUM_GST_CTX
24#include <VBox/vmm/em.h>
25#include <VBox/vmm/vmm.h>
26#include <VBox/vmm/patm.h>
27#include <VBox/vmm/csam.h>
28#include <VBox/vmm/selm.h>
29#include <VBox/vmm/trpm.h>
30#include <VBox/vmm/iem.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/dbgf.h>
33#include <VBox/vmm/pgm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/tm.h>
38#include <VBox/vmm/mm.h>
39#include <VBox/vmm/ssm.h>
40#include <VBox/vmm/pdmapi.h>
41#include <VBox/vmm/pdmcritsect.h>
42#include <VBox/vmm/pdmqueue.h>
43#include <VBox/vmm/patm.h>
44#include "EMInternal.h"
45#include <VBox/vmm/vm.h>
46#include <VBox/vmm/gim.h>
47#include <VBox/vmm/cpumdis.h>
48#include <VBox/dis.h>
49#include <VBox/disopcode.h>
50#include <VBox/vmm/dbgf.h>
51#include "VMMTracing.h"
52
53#include <VBox/log.h>
54#include <iprt/asm.h>
55#include <iprt/string.h>
56#include <iprt/stream.h>
57
58
59
60/*********************************************************************************************************************************
61* Internal Functions *
62*********************************************************************************************************************************/
63static int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, int rc);
64static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu);
65DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
66static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
67static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, int gcret);
68static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
69static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
70static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
71static int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, int rc);
72
73#define EMHANDLERC_WITH_PATM
74#define emR3ExecuteInstruction emR3RawExecuteInstruction
75#define emR3ExecuteIOInstruction emR3RawExecuteIOInstruction
76#include "EMHandleRCTmpl.h"
77
78
79
80#ifdef VBOX_WITH_STATISTICS
81/**
82 * Just a braindead function to keep track of cli addresses.
83 * @param pVM The cross context VM structure.
84 * @param pVCpu The cross context virtual CPU structure.
85 * @param GCPtrInstr The EIP of the cli instruction.
86 */
87static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
88{
89 PCLISTAT pRec;
90
91 pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
92 if (!pRec)
93 {
94 /* New cli instruction; insert into the tree. */
95 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
96 Assert(pRec);
97 if (!pRec)
98 return;
99 pRec->Core.Key = GCPtrInstr;
100
101 char szCliStatName[32];
102 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
103 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
104
105 bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
106 Assert(fRc); NOREF(fRc);
107 }
108 STAM_COUNTER_INC(&pRec->Counter);
109 STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
110}
111#endif /* VBOX_WITH_STATISTICS */
112
113
114
115/**
116 * Resumes executing hypervisor after a debug event.
117 *
118 * This is kind of special since our current guest state is
119 * potentially out of sync.
120 *
121 * @returns VBox status code.
122 * @param pVM The cross context VM structure.
123 * @param pVCpu The cross context virtual CPU structure.
124 */
125int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
126{
127 int rc;
128 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
129 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags));
130
131 /*
132 * Resume execution.
133 */
134 CPUMRawEnter(pVCpu);
135 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
136 rc = VMMR3ResumeHyper(pVM, pVCpu);
137 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags, rc));
138 rc = CPUMRawLeave(pVCpu, rc);
139 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
140
141 /*
142 * Deal with the return code.
143 */
144 rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc));
145 rc = emR3RawHandleRC(pVM, pVCpu, rc);
146 rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
147 return rc;
148}
149
150
151/**
152 * Steps rawmode.
153 *
154 * @returns VBox status code.
155 * @param pVM The cross context VM structure.
156 * @param pVCpu The cross context virtual CPU structure.
157 */
158int emR3RawStep(PVM pVM, PVMCPU pVCpu)
159{
160 Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
161 || pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
162 || pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
163 int rc;
164 bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
165#ifndef DEBUG_sander
166 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
167 fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
168#endif
169 if (fGuest)
170 {
171 /*
172 * Check vital forced actions, but ignore pending interrupts and timers.
173 */
174 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
175 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
176 {
177 rc = emR3RawForcedActions(pVM, pVCpu);
178 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
179 if (rc != VINF_SUCCESS)
180 return rc;
181 }
182
183 /*
184 * Set flags for single stepping.
185 */
186 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
187 }
188 else
189 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
190
191 /*
192 * Single step.
193 * We do not start time or anything, if anything we should just do a few nanoseconds.
194 */
195 CPUMRawEnter(pVCpu);
196 do
197 {
198 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
199 rc = VMMR3ResumeHyper(pVM, pVCpu);
200 else
201 rc = VMMR3RawRunGC(pVM, pVCpu);
202#ifndef DEBUG_sander
203 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
204 fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
205#endif
206 } while ( rc == VINF_SUCCESS
207 || rc == VINF_EM_RAW_INTERRUPT);
208 rc = CPUMRawLeave(pVCpu, rc);
209 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
210
211 /*
212 * Make sure the trap flag is cleared.
213 * (Too bad if the guest is trying to single step too.)
214 */
215 if (fGuest)
216 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
217 else
218 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
219
220 /*
221 * Deal with the return codes.
222 */
223 rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc));
224 rc = emR3RawHandleRC(pVM, pVCpu, rc);
225 rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
226 return rc;
227}
228
229
230#ifdef DEBUG
231
232
233int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
234{
235 int rc = VINF_SUCCESS;
236 EMSTATE enmOldState = pVCpu->em.s.enmState;
237 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
238
239 Log(("Single step BEGIN:\n"));
240 for (uint32_t i = 0; i < cIterations; i++)
241 {
242 DBGFR3PrgStep(pVCpu);
243 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
244 rc = emR3RawStep(pVM, pVCpu);
245 if ( rc != VINF_SUCCESS
246 && rc != VINF_EM_DBG_STEPPED)
247 break;
248 }
249 Log(("Single step END: rc=%Rrc\n", rc));
250 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
251 pVCpu->em.s.enmState = enmOldState;
252 return rc;
253}
254
255#endif /* DEBUG */
256
257
258/**
259 * Executes one (or perhaps a few more) instruction(s).
260 *
261 * @returns VBox status code suitable for EM.
262 *
263 * @param pVM The cross context VM structure.
264 * @param pVCpu The cross context virtual CPU structure.
265 * @param rcGC GC return code
266 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
267 * instruction and prefix the log output with this text.
268 */
269#if defined(LOG_ENABLED) || defined(DOXYGEN_RUNNING)
270static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
271#else
272static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
273#endif
274{
275 int rc;
276
277#ifdef LOG_ENABLED
278 /*
279 * Disassemble the instruction if requested.
280 */
281 if (pszPrefix)
282 {
283 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", pszPrefix);
284 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
285 }
286#endif /* LOG_ENABLED */
287
288 /*
289 * PATM is making life more interesting.
290 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
291 * tell PATM there is a trap in this code and have it take the appropriate actions
292 * to allow us execute the code in REM.
293 */
294 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
295 {
296 Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pVCpu->cpum.GstCtx.eip));
297
298 RTGCPTR uNewEip;
299 rc = PATMR3HandleTrap(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip, &uNewEip);
300 switch (rc)
301 {
302 /*
303 * It's not very useful to emulate a single instruction and then go back to raw
304 * mode; just execute the whole block until IF is set again.
305 */
306 case VINF_SUCCESS:
307 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
308 uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
309 pVCpu->cpum.GstCtx.eip = uNewEip;
310 Assert(pVCpu->cpum.GstCtx.eip);
311
312 if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
313 {
314 /*
315 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
316 */
317 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
318 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
319 }
320 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
321 {
322 /* special case: iret, that sets IF, detected a pending irq/event */
323 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
324 }
325 return VINF_EM_RESCHEDULE_REM;
326
327 /*
328 * One instruction.
329 */
330 case VINF_PATCH_EMULATE_INSTR:
331 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
332 uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
333 pVCpu->cpum.GstCtx.eip = uNewEip;
334 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
335
336 /*
337 * The patch was disabled, hand it to the REM.
338 */
339 case VERR_PATCH_DISABLED:
340 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
341 uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
342 pVCpu->cpum.GstCtx.eip = uNewEip;
343 if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
344 {
345 /*
346 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
347 */
348 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
349 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
350 }
351 return VINF_EM_RESCHEDULE_REM;
352
353 /* Force continued patch exection; usually due to write monitored stack. */
354 case VINF_PATCH_CONTINUE:
355 return VINF_SUCCESS;
356
357 default:
358 AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
359 return VERR_IPE_UNEXPECTED_STATUS;
360 }
361 }
362
363
364 /*
365 * Use IEM and fallback on REM if the functionality is missing.
366 * Once IEM gets mature enough, nothing should ever fall back.
367 */
368#define VBOX_WITH_FIRST_IEM_STEP_B
369#if defined(VBOX_WITH_FIRST_IEM_STEP_B) || !defined(VBOX_WITH_REM)
370 Log(("EMINS: %04x:%RGv RSP=%RGv\n", pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, (RTGCPTR)pVCpu->cpum.GstCtx.rsp));
371 STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
372 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
373 STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
374 if (RT_SUCCESS(rc))
375 {
376 if (rc == VINF_SUCCESS || rc == VINF_EM_RESCHEDULE)
377 rc = VINF_EM_RESCHEDULE;
378 }
379 else if ( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
380 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED)
381#endif
382 {
383#ifdef VBOX_WITH_REM
384 STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, b);
385# ifndef VBOX_WITH_FIRST_IEM_STEP_B
386 Log(("EMINS[rem]: %04x:%RGv RSP=%RGv\n", pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, (RTGCPTR)pVCpu->cpum.GstCtx.rsp));
387//# elif defined(DEBUG_bird)
388// AssertFailed();
389# endif
390 EMRemLock(pVM);
391 /* Flush the recompiler TLB if the VCPU has changed. */
392 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
393 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
394 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
395
396 rc = REMR3EmulateInstruction(pVM, pVCpu);
397 EMRemUnlock(pVM);
398 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, b);
399#else /* !VBOX_WITH_REM */
400 NOREF(pVM);
401#endif /* !VBOX_WITH_REM */
402 }
403 return rc;
404}
405
406
407/**
408 * Executes one (or perhaps a few more) instruction(s).
409 * This is just a wrapper for discarding pszPrefix in non-logging builds.
410 *
411 * @returns VBox status code suitable for EM.
412 * @param pVM The cross context VM structure.
413 * @param pVCpu The cross context virtual CPU structure.
414 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
415 * instruction and prefix the log output with this text.
416 * @param rcGC GC return code
417 */
418DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
419{
420#ifdef LOG_ENABLED
421 return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
422#else
423 RT_NOREF_PV(pszPrefix);
424 return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
425#endif
426}
427
428/**
429 * Executes one (or perhaps a few more) IO instruction(s).
430 *
431 * @returns VBox status code suitable for EM.
432 * @param pVM The cross context VM structure.
433 * @param pVCpu The cross context virtual CPU structure.
434 */
435static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
436{
437 STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
438 RT_NOREF_PV(pVM);
439
440 /* Hand it over to the interpreter. */
441 VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
442 LogFlow(("emR3RawExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
443 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
444 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
445 return VBOXSTRICTRC_TODO(rcStrict);
446}
447
448
449/**
450 * Handle a guest context trap.
451 *
452 * @returns VBox status code suitable for EM.
453 * @param pVM The cross context VM structure.
454 * @param pVCpu The cross context virtual CPU structure.
455 */
456static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
457{
458 /*
459 * Get the trap info.
460 */
461 uint8_t u8TrapNo;
462 TRPMEVENT enmType;
463 RTGCUINT uErrorCode;
464 RTGCUINTPTR uCR2;
465 int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
466 if (RT_FAILURE(rc))
467 {
468 AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
469 return rc;
470 }
471
472
473#if 1 /* Experimental: Review, disable if it causes trouble. */
474 /*
475 * Handle traps in patch code first.
476 *
477 * We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
478 * but several traps isn't handled specially by TRPM in RC and we end up here
479 * instead. One example is #DE.
480 */
481 uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
482 if ( uCpl == 0
483 && PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
484 {
485 LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pVCpu->cpum.GstCtx.eip));
486 return emR3RawPatchTrap(pVM, pVCpu, rc);
487 }
488#endif
489
490 /*
491 * If the guest gate is marked unpatched, then we will check again if we can patch it.
492 * (This assumes that we've already tried and failed to dispatch the trap in
493 * RC for the gates that already has been patched. Which is true for most high
494 * volume traps, because these are handled specially, but not for odd ones like #DE.)
495 */
496 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
497 {
498 CSAMR3CheckGates(pVM, u8TrapNo, 1);
499 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
500
501 /* If it was successful, then we could go back to raw mode. */
502 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
503 {
504 /* Must check pending forced actions as our IDT or GDT might be out of sync. */
505 rc = EMR3CheckRawForcedActions(pVM, pVCpu);
506 AssertRCReturn(rc, rc);
507
508 TRPMERRORCODE enmError = uErrorCode != ~0U
509 ? TRPM_TRAP_HAS_ERRORCODE
510 : TRPM_TRAP_NO_ERRORCODE;
511 rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
512 if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
513 {
514 TRPMResetTrap(pVCpu);
515 return VINF_EM_RESCHEDULE_RAW;
516 }
517 AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
518 }
519 }
520
521 /*
522 * Scan kernel code that traps; we might not get another chance.
523 */
524 /** @todo move this up before the dispatching? */
525 if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) <= 1
526 && !pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
527 {
528 Assert(!PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip));
529 CSAMR3CheckCodeEx(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip);
530 }
531
532 /*
533 * Trap specific handling.
534 */
535 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
536 {
537 /*
538 * If MONITOR & MWAIT are supported, then interpret them here.
539 */
540 DISCPUSTATE cpu;
541 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &cpu, "Guest Trap (#UD): ");
542 if ( RT_SUCCESS(rc)
543 && (cpu.pCurInstr->uOpcode == OP_MONITOR || cpu.pCurInstr->uOpcode == OP_MWAIT))
544 {
545 uint32_t u32Dummy, u32Features, u32ExtFeatures;
546 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
547 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
548 {
549 rc = TRPMResetTrap(pVCpu);
550 AssertRC(rc);
551
552 rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &cpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx),
553 0, EMCODETYPE_SUPERVISOR));
554 if (RT_SUCCESS(rc))
555 return rc;
556 return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
557 }
558 }
559 }
560 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
561 {
562 /*
563 * Handle I/O bitmap?
564 */
565 /** @todo We're not supposed to be here with a false guest trap concerning
566 * I/O access. We can easily handle those in RC. */
567 DISCPUSTATE cpu;
568 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &cpu, "Guest Trap: ");
569 if ( RT_SUCCESS(rc)
570 && (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
571 {
572 /*
573 * We should really check the TSS for the IO bitmap, but it's not like this
574 * lazy approach really makes things worse.
575 */
576 rc = TRPMResetTrap(pVCpu);
577 AssertRC(rc);
578 return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
579 }
580 }
581
582#ifdef LOG_ENABLED
583 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "Guest trap");
584 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Guest trap");
585
586 /* Get guest page information. */
587 uint64_t fFlags = 0;
588 RTGCPHYS GCPhys = 0;
589 int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
590 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
591 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pVCpu->cpum.GstCtx.cr0,
592 (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
593 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
594 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
595#endif
596
597 /*
598 * #PG has CR2.
599 * (Because of stuff like above we must set CR2 in a delayed fashion.)
600 */
601 if (u8TrapNo == 14 /* #PG */)
602 pVCpu->cpum.GstCtx.cr2 = uCR2;
603
604 return VINF_EM_RESCHEDULE_REM;
605}
606
607
608/**
609 * Handle a ring switch trap.
610 * Need to do statistics and to install patches. The result is going to REM.
611 *
612 * @returns VBox status code suitable for EM.
613 * @param pVM The cross context VM structure.
614 * @param pVCpu The cross context virtual CPU structure.
615 */
616static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
617{
618 int rc;
619 DISCPUSTATE Cpu;
620
621 /*
622 * sysenter, syscall & callgate
623 */
624 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &Cpu, "RSWITCH: ");
625 if (RT_SUCCESS(rc))
626 {
627 if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
628 {
629 if (pVCpu->cpum.GstCtx.SysEnter.cs != 0)
630 {
631 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.eip),
632 CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
633 if (RT_SUCCESS(rc))
634 {
635 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched sysenter instruction");
636 return VINF_EM_RESCHEDULE_RAW;
637 }
638 }
639 }
640
641#ifdef VBOX_WITH_STATISTICS
642 switch (Cpu.pCurInstr->uOpcode)
643 {
644 case OP_SYSENTER:
645 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
646 break;
647 case OP_SYSEXIT:
648 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
649 break;
650 case OP_SYSCALL:
651 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
652 break;
653 case OP_SYSRET:
654 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
655 break;
656 }
657#endif
658 }
659 else
660 AssertRC(rc);
661
662 /* go to the REM to emulate a single instruction */
663 return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
664}
665
666
667/**
668 * Handle a trap (\#PF or \#GP) in patch code
669 *
670 * @returns VBox status code suitable for EM.
671 * @param pVM The cross context VM structure.
672 * @param pVCpu The cross context virtual CPU structure.
673 * @param gcret GC return code.
674 */
675static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, int gcret)
676{
677 uint8_t u8TrapNo;
678 int rc;
679 TRPMEVENT enmType;
680 RTGCUINT uErrorCode;
681 RTGCUINTPTR uCR2;
682
683 Assert(PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip));
684
685 if (gcret == VINF_PATM_PATCH_INT3)
686 {
687 u8TrapNo = 3;
688 uCR2 = 0;
689 uErrorCode = 0;
690 }
691 else if (gcret == VINF_PATM_PATCH_TRAP_GP)
692 {
693 /* No active trap in this case. Kind of ugly. */
694 u8TrapNo = X86_XCPT_GP;
695 uCR2 = 0;
696 uErrorCode = 0;
697 }
698 else
699 {
700 rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
701 if (RT_FAILURE(rc))
702 {
703 AssertReleaseMsgFailed(("emR3RawPatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
704 return rc;
705 }
706 /* Reset the trap as we'll execute the original instruction again. */
707 TRPMResetTrap(pVCpu);
708 }
709
710 /*
711 * Deal with traps inside patch code.
712 * (This code won't run outside GC.)
713 */
714 if (u8TrapNo != 1)
715 {
716#ifdef LOG_ENABLED
717 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "Trap in patch code");
718 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patch code");
719
720 DISCPUSTATE Cpu;
721 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip, &Cpu, "Patch code: ");
722 if ( RT_SUCCESS(rc)
723 && Cpu.pCurInstr->uOpcode == OP_IRET)
724 {
725 uint32_t eip, selCS, uEFlags;
726
727 /* Iret crashes are bad as we have already changed the flags on the stack */
728 rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pVCpu->cpum.GstCtx.esp, 4);
729 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pVCpu->cpum.GstCtx.esp+4, 4);
730 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pVCpu->cpum.GstCtx.esp+8, 4);
731 if (rc == VINF_SUCCESS)
732 {
733 if ( (uEFlags & X86_EFL_VM)
734 || (selCS & X86_SEL_RPL) == 3)
735 {
736 uint32_t selSS, esp;
737
738 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pVCpu->cpum.GstCtx.esp + 12, 4);
739 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pVCpu->cpum.GstCtx.esp + 16, 4);
740
741 if (uEFlags & X86_EFL_VM)
742 {
743 uint32_t selDS, selES, selFS, selGS;
744 rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pVCpu->cpum.GstCtx.esp + 20, 4);
745 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pVCpu->cpum.GstCtx.esp + 24, 4);
746 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pVCpu->cpum.GstCtx.esp + 28, 4);
747 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pVCpu->cpum.GstCtx.esp + 32, 4);
748 if (rc == VINF_SUCCESS)
749 {
750 Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
751 Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
752 }
753 }
754 else
755 Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
756 }
757 else
758 Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
759 }
760 }
761#endif /* LOG_ENABLED */
762 Log(("emR3RawPatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
763 pVCpu->cpum.GstCtx.eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pVCpu->cpum.GstCtx.cr0));
764
765 RTGCPTR uNewEip;
766 rc = PATMR3HandleTrap(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip, &uNewEip);
767 switch (rc)
768 {
769 /*
770 * Execute the faulting instruction.
771 */
772 case VINF_SUCCESS:
773 {
774 /** @todo execute a whole block */
775 Log(("emR3RawPatchTrap: Executing faulting instruction at new address %RGv\n", uNewEip));
776 if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
777 Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
778
779 pVCpu->cpum.GstCtx.eip = uNewEip;
780 AssertRelease(pVCpu->cpum.GstCtx.eip);
781
782 if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
783 {
784 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
785 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
786 */
787 if ( u8TrapNo == X86_XCPT_GP
788 && PATMIsInt3Patch(pVM, pVCpu->cpum.GstCtx.eip, NULL, NULL))
789 {
790 /** @todo move to PATMR3HandleTrap */
791 Log(("Possible Windows XP iret fault at %08RX32\n", pVCpu->cpum.GstCtx.eip));
792 PATMR3RemovePatch(pVM, pVCpu->cpum.GstCtx.eip);
793 }
794
795 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
796 /* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
797
798 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
799 /* Interrupts are enabled; just go back to the original instruction.
800 return VINF_SUCCESS; */
801 }
802 return VINF_EM_RESCHEDULE_REM;
803 }
804
805 /*
806 * One instruction.
807 */
808 case VINF_PATCH_EMULATE_INSTR:
809 Log(("emR3RawPatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
810 uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
811 pVCpu->cpum.GstCtx.eip = uNewEip;
812 AssertRelease(pVCpu->cpum.GstCtx.eip);
813 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
814
815 /*
816 * The patch was disabled, hand it to the REM.
817 */
818 case VERR_PATCH_DISABLED:
819 if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
820 Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
821 pVCpu->cpum.GstCtx.eip = uNewEip;
822 AssertRelease(pVCpu->cpum.GstCtx.eip);
823
824 if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
825 {
826 /*
827 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
828 */
829 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
830 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
831 }
832 return VINF_EM_RESCHEDULE_REM;
833
834 /* Force continued patch exection; usually due to write monitored stack. */
835 case VINF_PATCH_CONTINUE:
836 return VINF_SUCCESS;
837
838 /*
839 * Anything else is *fatal*.
840 */
841 default:
842 AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
843 return VERR_IPE_UNEXPECTED_STATUS;
844 }
845 }
846 return VINF_SUCCESS;
847}
848
849
850/**
851 * Handle a privileged instruction.
852 *
853 * @returns VBox status code suitable for EM.
854 * @param pVM The cross context VM structure.
855 * @param pVCpu The cross context virtual CPU structure.
856 */
857static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
858{
859 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
860
861 if (PATMIsEnabled(pVM))
862 {
863 /*
864 * Check if in patch code.
865 */
866 if (PATMR3IsInsidePatchJump(pVM, pVCpu->cpum.GstCtx.eip, NULL))
867 {
868#ifdef LOG_ENABLED
869 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
870#endif
871 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08x\n", pVCpu->cpum.GstCtx.eip));
872 return VERR_EM_RAW_PATCH_CONFLICT;
873 }
874 if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 0
875 && !pVCpu->cpum.GstCtx.eflags.Bits.u1VM
876 && !PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
877 {
878 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.eip),
879 CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
880 if (RT_SUCCESS(rc))
881 {
882#ifdef LOG_ENABLED
883 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
884#endif
885 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched privileged instruction");
886 return VINF_SUCCESS;
887 }
888 }
889 }
890
891#ifdef LOG_ENABLED
892 if (!PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
893 {
894 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
895 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
896 }
897#endif
898
899 /*
900 * Instruction statistics and logging.
901 */
902 DISCPUSTATE Cpu;
903 int rc;
904
905 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &Cpu, "PRIV: ");
906 if (RT_SUCCESS(rc))
907 {
908#ifdef VBOX_WITH_STATISTICS
909 PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
910 switch (Cpu.pCurInstr->uOpcode)
911 {
912 case OP_INVLPG:
913 STAM_COUNTER_INC(&pStats->StatInvlpg);
914 break;
915 case OP_IRET:
916 STAM_COUNTER_INC(&pStats->StatIret);
917 break;
918 case OP_CLI:
919 STAM_COUNTER_INC(&pStats->StatCli);
920 emR3RecordCli(pVM, pVCpu, pVCpu->cpum.GstCtx.rip);
921 break;
922 case OP_STI:
923 STAM_COUNTER_INC(&pStats->StatSti);
924 break;
925 case OP_INSB:
926 case OP_INSWD:
927 case OP_IN:
928 case OP_OUTSB:
929 case OP_OUTSWD:
930 case OP_OUT:
931 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
932 break;
933
934 case OP_MOV_CR:
935 if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
936 {
937 //read
938 Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
939 Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
940 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
941 }
942 else
943 {
944 //write
945 Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
946 Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
947 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
948 }
949 break;
950
951 case OP_MOV_DR:
952 STAM_COUNTER_INC(&pStats->StatMovDRx);
953 break;
954 case OP_LLDT:
955 STAM_COUNTER_INC(&pStats->StatMovLldt);
956 break;
957 case OP_LIDT:
958 STAM_COUNTER_INC(&pStats->StatMovLidt);
959 break;
960 case OP_LGDT:
961 STAM_COUNTER_INC(&pStats->StatMovLgdt);
962 break;
963 case OP_SYSENTER:
964 STAM_COUNTER_INC(&pStats->StatSysEnter);
965 break;
966 case OP_SYSEXIT:
967 STAM_COUNTER_INC(&pStats->StatSysExit);
968 break;
969 case OP_SYSCALL:
970 STAM_COUNTER_INC(&pStats->StatSysCall);
971 break;
972 case OP_SYSRET:
973 STAM_COUNTER_INC(&pStats->StatSysRet);
974 break;
975 case OP_HLT:
976 STAM_COUNTER_INC(&pStats->StatHlt);
977 break;
978 default:
979 STAM_COUNTER_INC(&pStats->StatMisc);
980 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
981 break;
982 }
983#endif /* VBOX_WITH_STATISTICS */
984 if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 0
985 && !pVCpu->cpum.GstCtx.eflags.Bits.u1VM
986 && CPUMGetGuestCodeBits(pVCpu) == 32)
987 {
988 STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
989 switch (Cpu.pCurInstr->uOpcode)
990 {
991 case OP_CLI:
992 pVCpu->cpum.GstCtx.eflags.u32 &= ~X86_EFL_IF;
993 Assert(Cpu.cbInstr == 1);
994 pVCpu->cpum.GstCtx.rip += Cpu.cbInstr;
995 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
996 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
997
998 case OP_STI:
999 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_IF;
1000 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip + Cpu.cbInstr);
1001 Assert(Cpu.cbInstr == 1);
1002 pVCpu->cpum.GstCtx.rip += Cpu.cbInstr;
1003 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1004 return VINF_SUCCESS;
1005
1006 case OP_HLT:
1007 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1008 {
1009 PATMTRANSSTATE enmState;
1010 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pVCpu->cpum.GstCtx.eip, &enmState);
1011
1012 if (enmState == PATMTRANS_OVERWRITTEN)
1013 {
1014 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1015 Assert(rc == VERR_PATCH_DISABLED);
1016 /* Conflict detected, patch disabled */
1017 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pVCpu->cpum.GstCtx.eip));
1018
1019 enmState = PATMTRANS_SAFE;
1020 }
1021
1022 /* The translation had better be successful. Otherwise we can't recover. */
1023 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pVCpu->cpum.GstCtx.eip));
1024 if (enmState != PATMTRANS_OVERWRITTEN)
1025 pVCpu->cpum.GstCtx.eip = pOrgInstrGC;
1026 }
1027 /* no break; we could just return VINF_EM_HALT here */
1028 RT_FALL_THRU();
1029
1030 case OP_MOV_CR:
1031 case OP_MOV_DR:
1032#ifdef LOG_ENABLED
1033 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1034 {
1035 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
1036 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
1037 }
1038#endif
1039
1040 rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx),
1041 0, EMCODETYPE_SUPERVISOR));
1042 if (RT_SUCCESS(rc))
1043 {
1044 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1045
1046 if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR
1047 && Cpu.Param1.fUse == DISUSE_REG_CR /* write */
1048 )
1049 {
1050 /* Deal with CR0 updates inside patch code that force
1051 * us to go to the recompiler.
1052 */
1053 if ( PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.rip)
1054 && (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE)) != (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE))
1055 {
1056 PATMTRANSSTATE enmState;
1057 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pVCpu->cpum.GstCtx.rip, &enmState);
1058
1059 Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.rip, pOrgInstrGC, enmState));
1060 if (enmState == PATMTRANS_OVERWRITTEN)
1061 {
1062 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1063 Assert(rc == VERR_PATCH_DISABLED);
1064 /* Conflict detected, patch disabled */
1065 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pVCpu->cpum.GstCtx.rip));
1066 enmState = PATMTRANS_SAFE;
1067 }
1068 /* The translation had better be successful. Otherwise we can't recover. */
1069 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pVCpu->cpum.GstCtx.rip));
1070 if (enmState != PATMTRANS_OVERWRITTEN)
1071 pVCpu->cpum.GstCtx.rip = pOrgInstrGC;
1072 }
1073
1074 /* Reschedule is necessary as the execution/paging mode might have changed. */
1075 return VINF_EM_RESCHEDULE;
1076 }
1077 return rc; /* can return VINF_EM_HALT as well. */
1078 }
1079 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1080 break; /* fall back to the recompiler */
1081 }
1082 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1083 }
1084 }
1085
1086 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1087 return emR3RawPatchTrap(pVM, pVCpu, VINF_PATM_PATCH_TRAP_GP);
1088
1089 return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
1090}
1091
1092
1093/**
1094 * Update the forced rawmode execution modifier.
1095 *
1096 * This function is called when we're returning from the raw-mode loop(s). If we're
1097 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1098 * if not in patch code, the flag will be cleared.
1099 *
1100 * We should never interrupt patch code while it's being executed. Cli patches can
1101 * contain big code blocks, but they are always executed with IF=0. Other patches
1102 * replace single instructions and should be atomic.
1103 *
1104 * @returns Updated rc.
1105 *
1106 * @param pVM The cross context VM structure.
1107 * @param pVCpu The cross context virtual CPU structure.
1108 * @param rc The result code.
1109 */
1110static int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, int rc)
1111{
1112 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip)) /** @todo check cs selector base/type */
1113 {
1114 /* ignore reschedule attempts. */
1115 switch (rc)
1116 {
1117 case VINF_EM_RESCHEDULE:
1118 case VINF_EM_RESCHEDULE_REM:
1119 LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1120 rc = VINF_SUCCESS;
1121 break;
1122 }
1123 pVCpu->em.s.fForceRAW = true;
1124 }
1125 else
1126 pVCpu->em.s.fForceRAW = false;
1127 return rc;
1128}
1129
1130
1131/**
1132 * Check for pending raw actions
1133 *
1134 * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1135 * EM statuses.
1136 * @param pVM The cross context VM structure.
1137 * @param pVCpu The cross context virtual CPU structure.
1138 */
1139VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1140{
1141 int rc = emR3RawForcedActions(pVM, pVCpu);
1142 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1143 return rc;
1144}
1145
1146
1147/**
1148 * Process raw-mode specific forced actions.
1149 *
1150 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1151 *
1152 * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1153 * EM statuses.
1154 * @param pVM The cross context VM structure.
1155 * @param pVCpu The cross context virtual CPU structure.
1156 */
1157static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu)
1158{
1159 /*
1160 * Note that the order is *vitally* important!
1161 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1162 */
1163 VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1164
1165 /*
1166 * Sync selector tables.
1167 */
1168 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT))
1169 {
1170 VBOXSTRICTRC rcStrict = SELMR3UpdateFromCPUM(pVM, pVCpu);
1171 if (rcStrict != VINF_SUCCESS)
1172 return VBOXSTRICTRC_TODO(rcStrict);
1173 }
1174
1175 /*
1176 * Sync IDT.
1177 *
1178 * The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1179 * and PGMShwModifyPage, so we're in for trouble if for instance a
1180 * PGMSyncCR3+pgmR3PoolClearAll is pending.
1181 */
1182 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1183 {
1184 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1185 && EMIsRawRing0Enabled(pVM)
1186 && CSAMIsEnabled(pVM))
1187 {
1188 int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1189 if (RT_FAILURE(rc))
1190 return rc;
1191 }
1192
1193 int rc = TRPMR3SyncIDT(pVM, pVCpu);
1194 if (RT_FAILURE(rc))
1195 return rc;
1196 }
1197
1198 /*
1199 * Sync TSS.
1200 */
1201 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1202 {
1203 int rc = SELMR3SyncTSS(pVM, pVCpu);
1204 if (RT_FAILURE(rc))
1205 return rc;
1206 }
1207
1208 /*
1209 * Sync page directory.
1210 */
1211 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1212 {
1213 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1214 int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1215 if (RT_FAILURE(rc))
1216 return rc == VERR_PGM_NO_HYPERVISOR_ADDRESS ? VINF_EM_RESCHEDULE_REM : rc;
1217
1218 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
1219
1220 /* Prefetch pages for EIP and ESP. */
1221 /** @todo This is rather expensive. Should investigate if it really helps at all. */
1222 rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.rip));
1223 if (rc == VINF_SUCCESS)
1224 rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.rsp));
1225 if (rc != VINF_SUCCESS)
1226 {
1227 if (rc != VINF_PGM_SYNC_CR3)
1228 {
1229 AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1230 return rc;
1231 }
1232 rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1233 if (RT_FAILURE(rc))
1234 return rc;
1235 }
1236 /** @todo maybe prefetch the supervisor stack page as well */
1237 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
1238 }
1239
1240 /*
1241 * Allocate handy pages (just in case the above actions have consumed some pages).
1242 */
1243 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1244 {
1245 int rc = PGMR3PhysAllocateHandyPages(pVM);
1246 if (RT_FAILURE(rc))
1247 return rc;
1248 }
1249
1250 /*
1251 * Check whether we're out of memory now.
1252 *
1253 * This may stem from some of the above actions or operations that has been executed
1254 * since we ran FFs. The allocate handy pages must for instance always be followed by
1255 * this check.
1256 */
1257 if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
1258 return VINF_EM_NO_MEMORY;
1259
1260 return VINF_SUCCESS;
1261}
1262
1263
1264/**
1265 * Executes raw code.
1266 *
1267 * This function contains the raw-mode version of the inner
1268 * execution loop (the outer loop being in EMR3ExecuteVM()).
1269 *
1270 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1271 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1272 *
1273 * @param pVM The cross context VM structure.
1274 * @param pVCpu The cross context virtual CPU structure.
1275 * @param pfFFDone Where to store an indicator telling whether or not
1276 * FFs were done before returning.
1277 */
1278int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1279{
1280 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1281
1282 int rc = VERR_IPE_UNINITIALIZED_STATUS;
1283 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip));
1284 pVCpu->em.s.fForceRAW = false;
1285 *pfFFDone = false;
1286
1287
1288 /*
1289 *
1290 * Spin till we get a forced action or raw mode status code resulting in
1291 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1292 *
1293 */
1294 for (;;)
1295 {
1296 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1297
1298 /*
1299 * Check various preconditions.
1300 */
1301#ifdef VBOX_STRICT
1302 Assert(pVCpu->cpum.GstCtx.eflags.Bits.u1VM || (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 3 || (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 0
1303 || (EMIsRawRing1Enabled(pVM) && (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 1));
1304 AssertMsg( (pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_IF)
1305 || PATMShouldUseRawMode(pVM, (RTGCPTR)pVCpu->cpum.GstCtx.eip),
1306 ("Tried to execute code with IF at EIP=%08x!\n", pVCpu->cpum.GstCtx.eip));
1307 if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1308 && PGMMapHasConflicts(pVM))
1309 {
1310 PGMMapCheck(pVM);
1311 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1312 return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1313 }
1314#endif /* VBOX_STRICT */
1315
1316 /*
1317 * Process high priority pre-execution raw-mode FFs.
1318 */
1319 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1320 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1321 {
1322 rc = emR3RawForcedActions(pVM, pVCpu);
1323 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1324 if (rc != VINF_SUCCESS)
1325 break;
1326 }
1327
1328 /*
1329 * If we're going to execute ring-0 code, the guest state needs to
1330 * be modified a bit and some of the state components (IF, SS/CS RPL,
1331 * and perhaps EIP) needs to be stored with PATM.
1332 */
1333 rc = CPUMRawEnter(pVCpu);
1334 if (rc != VINF_SUCCESS)
1335 {
1336 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1337 break;
1338 }
1339
1340 /*
1341 * Scan code before executing it. Don't bother with user mode or V86 code
1342 */
1343 if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) <= 1
1344 && !pVCpu->cpum.GstCtx.eflags.Bits.u1VM
1345 && !PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1346 {
1347 STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1348 CSAMR3CheckCodeEx(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip);
1349 STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1350 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1351 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1352 {
1353 rc = emR3RawForcedActions(pVM, pVCpu);
1354 VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1355 if (rc != VINF_SUCCESS)
1356 {
1357 rc = CPUMRawLeave(pVCpu, rc);
1358 break;
1359 }
1360 }
1361 }
1362
1363#ifdef LOG_ENABLED
1364 /*
1365 * Log important stuff before entering GC.
1366 */
1367 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1368 if (pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
1369 Log(("RV86: %04x:%08x IF=%d VMFlags=%x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags));
1370 else if ((pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 1)
1371 Log(("RR0: %x:%08x ESP=%x:%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n",
1372 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.esp, CPUMRawGetEFlags(pVCpu), !!(pGCState->uVMFlags & X86_EFL_IF), pVCpu->cpum.GstCtx.eflags.Bits.u1IF,
1373 pGCState->uVMFlags, pGCState->fPIF, (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL), CSAMIsPageScanned(pVM, (RTGCPTR)pVCpu->cpum.GstCtx.eip)));
1374# ifdef VBOX_WITH_RAW_RING1
1375 else if ((pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 2)
1376 Log(("RR1: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x CPL=%x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags, (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL)));
1377# endif
1378 else if ((pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 3)
1379 Log(("RR3: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags));
1380#endif /* LOG_ENABLED */
1381
1382
1383
1384 /*
1385 * Execute the code.
1386 */
1387 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1388 if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1389 {
1390 STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1391 VBOXVMM_EM_RAW_RUN_PRE(pVCpu, &pVCpu->cpum.GstCtx);
1392 rc = VMMR3RawRunGC(pVM, pVCpu);
1393 VBOXVMM_EM_RAW_RUN_RET(pVCpu, &pVCpu->cpum.GstCtx, rc);
1394 STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1395 }
1396 else
1397 {
1398 /* Give up this time slice; virtual time continues */
1399 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1400 RTThreadSleep(5);
1401 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1402 rc = VINF_SUCCESS;
1403 }
1404 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1405
1406 LogFlow(("RR%u-E: %08x ESP=%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d\n",
1407 (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL), pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.esp, CPUMRawGetEFlags(pVCpu),
1408 !!(pGCState->uVMFlags & X86_EFL_IF), pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF));
1409 LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1410
1411
1412
1413 /*
1414 * Restore the real CPU state and deal with high priority post
1415 * execution FFs before doing anything else.
1416 */
1417 rc = CPUMRawLeave(pVCpu, rc);
1418 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1419 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1420 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1421 rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc));
1422
1423#ifdef VBOX_STRICT
1424 /*
1425 * Assert TSS consistency & rc vs patch code.
1426 */
1427 if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1428 && EMIsRawRing0Enabled(pVM))
1429 SELMR3CheckTSS(pVM);
1430 switch (rc)
1431 {
1432 case VINF_SUCCESS:
1433 case VINF_EM_RAW_INTERRUPT:
1434 case VINF_PATM_PATCH_TRAP_PF:
1435 case VINF_PATM_PATCH_TRAP_GP:
1436 case VINF_PATM_PATCH_INT3:
1437 case VINF_PATM_CHECK_PATCH_PAGE:
1438 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1439 case VINF_EM_RAW_GUEST_TRAP:
1440 case VINF_EM_RESCHEDULE_RAW:
1441 break;
1442
1443 default:
1444 if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip) && !(pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_TF))
1445 LogIt(0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1446 break;
1447 }
1448 /*
1449 * Let's go paranoid!
1450 */
1451 if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1452 && PGMMapHasConflicts(pVM))
1453 {
1454 PGMMapCheck(pVM);
1455 AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1456 return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1457 }
1458#endif /* VBOX_STRICT */
1459
1460 /*
1461 * Process the returned status code.
1462 */
1463 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1464 {
1465 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1466 break;
1467 }
1468 rc = emR3RawHandleRC(pVM, pVCpu, rc);
1469 if (rc != VINF_SUCCESS)
1470 {
1471 rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
1472 if (rc != VINF_SUCCESS)
1473 {
1474 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1475 break;
1476 }
1477 }
1478
1479 /*
1480 * Check and execute forced actions.
1481 */
1482#ifdef VBOX_HIGH_RES_TIMERS_HACK
1483 TMTimerPollVoid(pVM, pVCpu);
1484#endif
1485 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1486 if ( VM_FF_IS_ANY_SET(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK | VM_FF_PGM_NO_MEMORY)
1487 || VMCPU_FF_IS_ANY_SET(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1488 {
1489 Assert(pVCpu->cpum.GstCtx.eflags.Bits.u1VM || (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) != (EMIsRawRing1Enabled(pVM) ? 2U : 1U));
1490
1491 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1492 rc = emR3ForcedActions(pVM, pVCpu, rc);
1493 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1494 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1495 if ( rc != VINF_SUCCESS
1496 && rc != VINF_EM_RESCHEDULE_RAW)
1497 {
1498 rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
1499 if (rc != VINF_SUCCESS)
1500 {
1501 *pfFFDone = true;
1502 break;
1503 }
1504 }
1505 }
1506 }
1507
1508 /*
1509 * Return to outer loop.
1510 */
1511#if defined(LOG_ENABLED) && defined(DEBUG)
1512 RTLogFlush(NULL);
1513#endif
1514 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1515 return rc;
1516}
1517
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