VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EM.cpp@ 87040

Last change on this file since 87040 was 87040, checked in by vboxsync, 3 years ago

VMM: Better fix for r141682 - Fix delivery of external interrupts when executing nested-guests. Fixes nested-guest SMP hangs described in bugref:9562#c18
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1/* $Id: EM.cpp 87040 2020-12-04 06:28:01Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HmExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34
35/*********************************************************************************************************************************
36* Header Files *
37*********************************************************************************************************************************/
38#define LOG_GROUP LOG_GROUP_EM
39#define VMCPU_INCL_CPUM_GST_CTX /* for CPUM_IMPORT_GUEST_STATE_RET */
40#include <VBox/vmm/em.h>
41#include <VBox/vmm/vmm.h>
42#include <VBox/vmm/selm.h>
43#include <VBox/vmm/trpm.h>
44#include <VBox/vmm/iem.h>
45#include <VBox/vmm/nem.h>
46#include <VBox/vmm/iom.h>
47#include <VBox/vmm/dbgf.h>
48#include <VBox/vmm/pgm.h>
49#include <VBox/vmm/apic.h>
50#include <VBox/vmm/tm.h>
51#include <VBox/vmm/mm.h>
52#include <VBox/vmm/ssm.h>
53#include <VBox/vmm/pdmapi.h>
54#include <VBox/vmm/pdmcritsect.h>
55#include <VBox/vmm/pdmqueue.h>
56#include <VBox/vmm/hm.h>
57#include "EMInternal.h"
58#include <VBox/vmm/vm.h>
59#include <VBox/vmm/uvm.h>
60#include <VBox/vmm/cpumdis.h>
61#include <VBox/dis.h>
62#include <VBox/disopcode.h>
63#include <VBox/err.h>
64#include "VMMTracing.h"
65
66#include <iprt/asm.h>
67#include <iprt/string.h>
68#include <iprt/stream.h>
69#include <iprt/thread.h>
70
71
72/*********************************************************************************************************************************
73* Internal Functions *
74*********************************************************************************************************************************/
75static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
76static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
77#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
78static const char *emR3GetStateName(EMSTATE enmState);
79#endif
80static VBOXSTRICTRC emR3Debug(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc);
81#if defined(VBOX_WITH_REM) || defined(DEBUG)
82static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
83#endif
84static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
85
86
87/**
88 * Initializes the EM.
89 *
90 * @returns VBox status code.
91 * @param pVM The cross context VM structure.
92 */
93VMMR3_INT_DECL(int) EMR3Init(PVM pVM)
94{
95 LogFlow(("EMR3Init\n"));
96 /*
97 * Assert alignment and sizes.
98 */
99 AssertCompileMemberAlignment(VM, em.s, 32);
100 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
101 AssertCompile(RT_SIZEOFMEMB(VMCPU, em.s.u.FatalLongJump) <= RT_SIZEOFMEMB(VMCPU, em.s.u.achPaddingFatalLongJump));
102 AssertCompile(RT_SIZEOFMEMB(VMCPU, em.s) <= RT_SIZEOFMEMB(VMCPU, em.padding));
103
104 /*
105 * Init the structure.
106 */
107 PCFGMNODE pCfgRoot = CFGMR3GetRoot(pVM);
108 PCFGMNODE pCfgEM = CFGMR3GetChild(pCfgRoot, "EM");
109
110 int rc = CFGMR3QueryBoolDef(pCfgEM, "IemExecutesAll", &pVM->em.s.fIemExecutesAll, false);
111 AssertLogRelRCReturn(rc, rc);
112
113 bool fEnabled;
114 rc = CFGMR3QueryBoolDef(pCfgEM, "TripleFaultReset", &fEnabled, false);
115 AssertLogRelRCReturn(rc, rc);
116 pVM->em.s.fGuruOnTripleFault = !fEnabled;
117 if (!pVM->em.s.fGuruOnTripleFault && pVM->cCpus > 1)
118 {
119 LogRel(("EM: Overriding /EM/TripleFaultReset, must be false on SMP.\n"));
120 pVM->em.s.fGuruOnTripleFault = true;
121 }
122
123 LogRel(("EMR3Init: fIemExecutesAll=%RTbool fGuruOnTripleFault=%RTbool\n", pVM->em.s.fIemExecutesAll, pVM->em.s.fGuruOnTripleFault));
124
125 /** @cfgm{/EM/ExitOptimizationEnabled, bool, true}
126 * Whether to try correlate exit history in any context, detect hot spots and
127 * try optimize these using IEM if there are other exits close by. This
128 * overrides the context specific settings. */
129 bool fExitOptimizationEnabled = true;
130 rc = CFGMR3QueryBoolDef(pCfgEM, "ExitOptimizationEnabled", &fExitOptimizationEnabled, true);
131 AssertLogRelRCReturn(rc, rc);
132
133 /** @cfgm{/EM/ExitOptimizationEnabledR0, bool, true}
134 * Whether to optimize exits in ring-0. Setting this to false will also disable
135 * the /EM/ExitOptimizationEnabledR0PreemptDisabled setting. Depending on preemption
136 * capabilities of the host kernel, this optimization may be unavailable. */
137 bool fExitOptimizationEnabledR0 = true;
138 rc = CFGMR3QueryBoolDef(pCfgEM, "ExitOptimizationEnabledR0", &fExitOptimizationEnabledR0, true);
139 AssertLogRelRCReturn(rc, rc);
140 fExitOptimizationEnabledR0 &= fExitOptimizationEnabled;
141
142 /** @cfgm{/EM/ExitOptimizationEnabledR0PreemptDisabled, bool, false}
143 * Whether to optimize exits in ring-0 when preemption is disable (or preemption
144 * hooks are in effect). */
145 /** @todo change the default to true here */
146 bool fExitOptimizationEnabledR0PreemptDisabled = true;
147 rc = CFGMR3QueryBoolDef(pCfgEM, "ExitOptimizationEnabledR0PreemptDisabled", &fExitOptimizationEnabledR0PreemptDisabled, false);
148 AssertLogRelRCReturn(rc, rc);
149 fExitOptimizationEnabledR0PreemptDisabled &= fExitOptimizationEnabledR0;
150
151 /** @cfgm{/EM/HistoryExecMaxInstructions, integer, 16, 65535, 8192}
152 * Maximum number of instruction to let EMHistoryExec execute in one go. */
153 uint16_t cHistoryExecMaxInstructions = 8192;
154 rc = CFGMR3QueryU16Def(pCfgEM, "HistoryExecMaxInstructions", &cHistoryExecMaxInstructions, cHistoryExecMaxInstructions);
155 AssertLogRelRCReturn(rc, rc);
156 if (cHistoryExecMaxInstructions < 16)
157 return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS, "/EM/HistoryExecMaxInstructions value is too small, min 16");
158
159 /** @cfgm{/EM/HistoryProbeMaxInstructionsWithoutExit, integer, 2, 65535, 24 for HM, 32 for NEM}
160 * Maximum number of instruction between exits during probing. */
161 uint16_t cHistoryProbeMaxInstructionsWithoutExit = 24;
162#ifdef RT_OS_WINDOWS
163 if (VM_IS_NEM_ENABLED(pVM))
164 cHistoryProbeMaxInstructionsWithoutExit = 32;
165#endif
166 rc = CFGMR3QueryU16Def(pCfgEM, "HistoryProbeMaxInstructionsWithoutExit", &cHistoryProbeMaxInstructionsWithoutExit,
167 cHistoryProbeMaxInstructionsWithoutExit);
168 AssertLogRelRCReturn(rc, rc);
169 if (cHistoryProbeMaxInstructionsWithoutExit < 2)
170 return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
171 "/EM/HistoryProbeMaxInstructionsWithoutExit value is too small, min 16");
172
173 /** @cfgm{/EM/HistoryProbMinInstructions, integer, 0, 65535, depends}
174 * The default is (/EM/HistoryProbeMaxInstructionsWithoutExit + 1) * 3. */
175 uint16_t cHistoryProbeMinInstructions = cHistoryProbeMaxInstructionsWithoutExit < 0x5554
176 ? (cHistoryProbeMaxInstructionsWithoutExit + 1) * 3 : 0xffff;
177 rc = CFGMR3QueryU16Def(pCfgEM, "HistoryProbMinInstructions", &cHistoryProbeMinInstructions,
178 cHistoryProbeMinInstructions);
179 AssertLogRelRCReturn(rc, rc);
180
181 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
182 {
183 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
184 pVCpu->em.s.fExitOptimizationEnabled = fExitOptimizationEnabled;
185 pVCpu->em.s.fExitOptimizationEnabledR0 = fExitOptimizationEnabledR0;
186 pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled = fExitOptimizationEnabledR0PreemptDisabled;
187 pVCpu->em.s.cHistoryExecMaxInstructions = cHistoryExecMaxInstructions;
188 pVCpu->em.s.cHistoryProbeMinInstructions = cHistoryProbeMinInstructions;
189 pVCpu->em.s.cHistoryProbeMaxInstructionsWithoutExit = cHistoryProbeMaxInstructionsWithoutExit;
190 }
191
192 /*
193 * Saved state.
194 */
195 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
196 NULL, NULL, NULL,
197 NULL, emR3Save, NULL,
198 NULL, emR3Load, NULL);
199 if (RT_FAILURE(rc))
200 return rc;
201
202 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
203 {
204 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
205
206 pVCpu->em.s.enmState = idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
207 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
208 pVCpu->em.s.u64TimeSliceStart = 0; /* paranoia */
209 pVCpu->em.s.idxContinueExitRec = UINT16_MAX;
210
211# define EM_REG_COUNTER(a, b, c) \
212 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
213 AssertRC(rc);
214
215# define EM_REG_COUNTER_USED(a, b, c) \
216 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, idCpu); \
217 AssertRC(rc);
218
219# define EM_REG_PROFILE(a, b, c) \
220 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
221 AssertRC(rc);
222
223# define EM_REG_PROFILE_ADV(a, b, c) \
224 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
225 AssertRC(rc);
226
227 /*
228 * Statistics.
229 */
230#ifdef VBOX_WITH_STATISTICS
231 PEMSTATS pStats;
232 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
233 if (RT_FAILURE(rc))
234 return rc;
235
236 pVCpu->em.s.pStatsR3 = pStats;
237 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
238
239# if 1 /* rawmode only? */
240 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%u/R3/PrivInst/IoRestarted", "I/O instructions restarted in ring-3.");
241 EM_REG_COUNTER_USED(&pStats->StatIoIem, "/EM/CPU%u/R3/PrivInst/IoIem", "I/O instructions end to IEM in ring-3.");
242 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%u/R3/PrivInst/Cli", "Number of cli instructions.");
243 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%u/R3/PrivInst/Sti", "Number of sli instructions.");
244 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%u/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
245 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%u/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
246 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%u/R3/PrivInst/Misc", "Number of misc. instructions.");
247 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%u/R3/PrivInst/Mov CR0, X", "Number of mov CR0 write instructions.");
248 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%u/R3/PrivInst/Mov CR1, X", "Number of mov CR1 write instructions.");
249 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%u/R3/PrivInst/Mov CR2, X", "Number of mov CR2 write instructions.");
250 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%u/R3/PrivInst/Mov CR3, X", "Number of mov CR3 write instructions.");
251 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%u/R3/PrivInst/Mov CR4, X", "Number of mov CR4 write instructions.");
252 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%u/R3/PrivInst/Mov X, CR0", "Number of mov CR0 read instructions.");
253 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%u/R3/PrivInst/Mov X, CR1", "Number of mov CR1 read instructions.");
254 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%u/R3/PrivInst/Mov X, CR2", "Number of mov CR2 read instructions.");
255 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%u/R3/PrivInst/Mov X, CR3", "Number of mov CR3 read instructions.");
256 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%u/R3/PrivInst/Mov X, CR4", "Number of mov CR4 read instructions.");
257 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%u/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
258 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%u/R3/PrivInst/Iret", "Number of iret instructions.");
259 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%u/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
260 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%u/R3/PrivInst/Lidt", "Number of lidt instructions.");
261 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%u/R3/PrivInst/Lldt", "Number of lldt instructions.");
262 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%u/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
263 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%u/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
264 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%u/R3/PrivInst/Syscall", "Number of syscall instructions.");
265 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%u/R3/PrivInst/Sysret", "Number of sysret instructions.");
266 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%u/Cli/Total", "Total number of cli instructions executed.");
267#endif
268 pVCpu->em.s.pCliStatTree = 0;
269
270 /* these should be considered for release statistics. */
271 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%u/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
272 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%u/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
273 EM_REG_PROFILE(&pVCpu->em.s.StatHMEntry, "/PROF/CPU%u/EM/HMEnter", "Profiling Hardware Accelerated Mode entry overhead.");
274 EM_REG_PROFILE(&pVCpu->em.s.StatHMExec, "/PROF/CPU%u/EM/HMExec", "Profiling Hardware Accelerated Mode execution.");
275 EM_REG_COUNTER(&pVCpu->em.s.StatHMExecuteCalled, "/PROF/CPU%u/EM/HMExecuteCalled", "Number of times enmR3HMExecute is called.");
276 EM_REG_PROFILE(&pVCpu->em.s.StatIEMEmu, "/PROF/CPU%u/EM/IEMEmuSingle", "Profiling single instruction IEM execution.");
277 EM_REG_PROFILE(&pVCpu->em.s.StatIEMThenREM, "/PROF/CPU%u/EM/IEMThenRem", "Profiling IEM-then-REM instruction execution (by IEM).");
278 EM_REG_PROFILE(&pVCpu->em.s.StatNEMEntry, "/PROF/CPU%u/EM/NEMEnter", "Profiling NEM entry overhead.");
279#endif /* VBOX_WITH_STATISTICS */
280 EM_REG_PROFILE(&pVCpu->em.s.StatNEMExec, "/PROF/CPU%u/EM/NEMExec", "Profiling NEM execution.");
281 EM_REG_COUNTER(&pVCpu->em.s.StatNEMExecuteCalled, "/PROF/CPU%u/EM/NEMExecuteCalled", "Number of times enmR3NEMExecute is called.");
282#ifdef VBOX_WITH_STATISTICS
283 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%u/EM/REMEmuSingle", "Profiling single instruction REM execution.");
284 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%u/EM/REMExec", "Profiling REM execution.");
285 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%u/EM/REMSync", "Profiling REM context syncing.");
286 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%u/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
287 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%u/EM/RAWExec", "Profiling Raw Mode execution.");
288 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%u/EM/RAWTail", "Profiling Raw Mode tail overhead.");
289#endif /* VBOX_WITH_STATISTICS */
290
291 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%u/EM/ForcedActions", "Profiling forced action execution.");
292 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%u/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
293 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%u/EM/Capped", "Profiling capped state (sleep).");
294 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%u/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
295 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%u/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
296
297 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%u/EM/Total", "Profiling EMR3ExecuteVM.");
298
299 rc = STAMR3RegisterF(pVM, &pVCpu->em.s.iNextExit, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
300 "Number of recorded exits.", "/PROF/CPU%u/EM/RecordedExits", idCpu);
301 AssertRC(rc);
302
303 /* History record statistics */
304 rc = STAMR3RegisterF(pVM, &pVCpu->em.s.cExitRecordUsed, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
305 "Number of used hash table entries.", "/EM/CPU%u/ExitHashing/Used", idCpu);
306 AssertRC(rc);
307
308 for (uint32_t iStep = 0; iStep < RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits); iStep++)
309 {
310 rc = STAMR3RegisterF(pVM, &pVCpu->em.s.aStatHistoryRecHits[iStep], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
311 "Number of hits at this step.", "/EM/CPU%u/ExitHashing/Step%02u-Hits", idCpu, iStep);
312 AssertRC(rc);
313 rc = STAMR3RegisterF(pVM, &pVCpu->em.s.aStatHistoryRecTypeChanged[iStep], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
314 "Number of type changes at this step.", "/EM/CPU%u/ExitHashing/Step%02u-TypeChanges", idCpu, iStep);
315 AssertRC(rc);
316 rc = STAMR3RegisterF(pVM, &pVCpu->em.s.aStatHistoryRecTypeChanged[iStep], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
317 "Number of replacments at this step.", "/EM/CPU%u/ExitHashing/Step%02u-Replacments", idCpu, iStep);
318 AssertRC(rc);
319 rc = STAMR3RegisterF(pVM, &pVCpu->em.s.aStatHistoryRecNew[iStep], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
320 "Number of new inserts at this step.", "/EM/CPU%u/ExitHashing/Step%02u-NewInserts", idCpu, iStep);
321 AssertRC(rc);
322 }
323
324 EM_REG_PROFILE(&pVCpu->em.s.StatHistoryExec, "/EM/CPU%u/ExitOpt/Exec", "Profiling normal EMHistoryExec operation.");
325 EM_REG_COUNTER(&pVCpu->em.s.StatHistoryExecSavedExits, "/EM/CPU%u/ExitOpt/ExecSavedExit", "Net number of saved exits.");
326 EM_REG_COUNTER(&pVCpu->em.s.StatHistoryExecInstructions, "/EM/CPU%u/ExitOpt/ExecInstructions", "Number of instructions executed during normal operation.");
327 EM_REG_PROFILE(&pVCpu->em.s.StatHistoryProbe, "/EM/CPU%u/ExitOpt/Probe", "Profiling EMHistoryExec when probing.");
328 EM_REG_COUNTER(&pVCpu->em.s.StatHistoryProbeInstructions, "/EM/CPU%u/ExitOpt/ProbeInstructions", "Number of instructions executed during probing.");
329 EM_REG_COUNTER(&pVCpu->em.s.StatHistoryProbedNormal, "/EM/CPU%u/ExitOpt/ProbedNormal", "Number of EMEXITACTION_NORMAL_PROBED results.");
330 EM_REG_COUNTER(&pVCpu->em.s.StatHistoryProbedExecWithMax, "/EM/CPU%u/ExitOpt/ProbedExecWithMax", "Number of EMEXITACTION_EXEC_WITH_MAX results.");
331 EM_REG_COUNTER(&pVCpu->em.s.StatHistoryProbedToRing3, "/EM/CPU%u/ExitOpt/ProbedToRing3", "Number of ring-3 probe continuations.");
332 }
333
334 emR3InitDbg(pVM);
335 return VINF_SUCCESS;
336}
337
338
339/**
340 * Called when a VM initialization stage is completed.
341 *
342 * @returns VBox status code.
343 * @param pVM The cross context VM structure.
344 * @param enmWhat The initialization state that was completed.
345 */
346VMMR3_INT_DECL(int) EMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
347{
348 if (enmWhat == VMINITCOMPLETED_RING0)
349 LogRel(("EM: Exit history optimizations: enabled=%RTbool enabled-r0=%RTbool enabled-r0-no-preemption=%RTbool\n",
350 pVM->apCpusR3[0]->em.s.fExitOptimizationEnabled, pVM->apCpusR3[0]->em.s.fExitOptimizationEnabledR0,
351 pVM->apCpusR3[0]->em.s.fExitOptimizationEnabledR0PreemptDisabled));
352 return VINF_SUCCESS;
353}
354
355
356/**
357 * Applies relocations to data and code managed by this
358 * component. This function will be called at init and
359 * whenever the VMM need to relocate it self inside the GC.
360 *
361 * @param pVM The cross context VM structure.
362 */
363VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM)
364{
365 LogFlow(("EMR3Relocate\n"));
366 RT_NOREF(pVM);
367}
368
369
370/**
371 * Reset the EM state for a CPU.
372 *
373 * Called by EMR3Reset and hot plugging.
374 *
375 * @param pVCpu The cross context virtual CPU structure.
376 */
377VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
378{
379 /* Reset scheduling state. */
380 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_UNHALT);
381
382 /* VMR3ResetFF may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
383 out of the HALTED state here so that enmPrevState doesn't end up as
384 HALTED when EMR3Execute returns. */
385 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
386 {
387 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
388 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
389 }
390}
391
392
393/**
394 * Reset notification.
395 *
396 * @param pVM The cross context VM structure.
397 */
398VMMR3_INT_DECL(void) EMR3Reset(PVM pVM)
399{
400 Log(("EMR3Reset: \n"));
401 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
402 EMR3ResetCpu(pVM->apCpusR3[idCpu]);
403}
404
405
406/**
407 * Terminates the EM.
408 *
409 * Termination means cleaning up and freeing all resources,
410 * the VM it self is at this point powered off or suspended.
411 *
412 * @returns VBox status code.
413 * @param pVM The cross context VM structure.
414 */
415VMMR3_INT_DECL(int) EMR3Term(PVM pVM)
416{
417 RT_NOREF(pVM);
418 return VINF_SUCCESS;
419}
420
421
422/**
423 * Execute state save operation.
424 *
425 * @returns VBox status code.
426 * @param pVM The cross context VM structure.
427 * @param pSSM SSM operation handle.
428 */
429static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
430{
431 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
432 {
433 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
434
435 SSMR3PutBool(pSSM, false /*fForceRAW*/);
436
437 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
438 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
439 SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
440
441 /* Save mwait state. */
442 SSMR3PutU32(pSSM, pVCpu->em.s.MWait.fWait);
443 SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRAX);
444 SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRCX);
445 SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRAX);
446 SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRCX);
447 int rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRDX);
448 AssertRCReturn(rc, rc);
449 }
450 return VINF_SUCCESS;
451}
452
453
454/**
455 * Execute state load operation.
456 *
457 * @returns VBox status code.
458 * @param pVM The cross context VM structure.
459 * @param pSSM SSM operation handle.
460 * @param uVersion Data layout version.
461 * @param uPass The data pass.
462 */
463static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
464{
465 /*
466 * Validate version.
467 */
468 if ( uVersion > EM_SAVED_STATE_VERSION
469 || uVersion < EM_SAVED_STATE_VERSION_PRE_SMP)
470 {
471 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
472 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
473 }
474 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
475
476 /*
477 * Load the saved state.
478 */
479 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
480 {
481 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
482
483 bool fForceRAWIgnored;
484 int rc = SSMR3GetBool(pSSM, &fForceRAWIgnored);
485 AssertRCReturn(rc, rc);
486
487 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
488 {
489 SSM_GET_ENUM32_RET(pSSM, pVCpu->em.s.enmPrevState, EMSTATE);
490 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
491
492 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
493 }
494 if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
495 {
496 /* Load mwait state. */
497 rc = SSMR3GetU32(pSSM, &pVCpu->em.s.MWait.fWait);
498 AssertRCReturn(rc, rc);
499 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRAX);
500 AssertRCReturn(rc, rc);
501 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRCX);
502 AssertRCReturn(rc, rc);
503 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRAX);
504 AssertRCReturn(rc, rc);
505 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRCX);
506 AssertRCReturn(rc, rc);
507 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRDX);
508 AssertRCReturn(rc, rc);
509 }
510
511 Assert(!pVCpu->em.s.pCliStatTree);
512 }
513 return VINF_SUCCESS;
514}
515
516
517/**
518 * Argument packet for emR3SetExecutionPolicy.
519 */
520struct EMR3SETEXECPOLICYARGS
521{
522 EMEXECPOLICY enmPolicy;
523 bool fEnforce;
524};
525
526
527/**
528 * @callback_method_impl{FNVMMEMTRENDEZVOUS, Rendezvous callback for EMR3SetExecutionPolicy.}
529 */
530static DECLCALLBACK(VBOXSTRICTRC) emR3SetExecutionPolicy(PVM pVM, PVMCPU pVCpu, void *pvUser)
531{
532 /*
533 * Only the first CPU changes the variables.
534 */
535 if (pVCpu->idCpu == 0)
536 {
537 struct EMR3SETEXECPOLICYARGS *pArgs = (struct EMR3SETEXECPOLICYARGS *)pvUser;
538 switch (pArgs->enmPolicy)
539 {
540 case EMEXECPOLICY_RECOMPILE_RING0:
541 case EMEXECPOLICY_RECOMPILE_RING3:
542 break;
543 case EMEXECPOLICY_IEM_ALL:
544 pVM->em.s.fIemExecutesAll = pArgs->fEnforce;
545 break;
546 default:
547 AssertFailedReturn(VERR_INVALID_PARAMETER);
548 }
549 Log(("EM: Set execution policy (fIemExecutesAll=%RTbool)\n", pVM->em.s.fIemExecutesAll));
550 }
551
552 /*
553 * Force rescheduling if in RAW, HM, NEM, IEM, or REM.
554 */
555 return pVCpu->em.s.enmState == EMSTATE_RAW
556 || pVCpu->em.s.enmState == EMSTATE_HM
557 || pVCpu->em.s.enmState == EMSTATE_NEM
558 || pVCpu->em.s.enmState == EMSTATE_IEM
559 || pVCpu->em.s.enmState == EMSTATE_REM
560 || pVCpu->em.s.enmState == EMSTATE_IEM_THEN_REM
561 ? VINF_EM_RESCHEDULE
562 : VINF_SUCCESS;
563}
564
565
566/**
567 * Changes an execution scheduling policy parameter.
568 *
569 * This is used to enable or disable raw-mode / hardware-virtualization
570 * execution of user and supervisor code.
571 *
572 * @returns VINF_SUCCESS on success.
573 * @returns VINF_RESCHEDULE if a rescheduling might be required.
574 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
575 *
576 * @param pUVM The user mode VM handle.
577 * @param enmPolicy The scheduling policy to change.
578 * @param fEnforce Whether to enforce the policy or not.
579 */
580VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce)
581{
582 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
583 VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
584 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
585
586 struct EMR3SETEXECPOLICYARGS Args = { enmPolicy, fEnforce };
587 return VMMR3EmtRendezvous(pUVM->pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
588}
589
590
591/**
592 * Queries an execution scheduling policy parameter.
593 *
594 * @returns VBox status code
595 * @param pUVM The user mode VM handle.
596 * @param enmPolicy The scheduling policy to query.
597 * @param pfEnforced Where to return the current value.
598 */
599VMMR3DECL(int) EMR3QueryExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool *pfEnforced)
600{
601 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
602 AssertPtrReturn(pfEnforced, VERR_INVALID_POINTER);
603 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
604 PVM pVM = pUVM->pVM;
605 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
606
607 /* No need to bother EMTs with a query. */
608 switch (enmPolicy)
609 {
610 case EMEXECPOLICY_RECOMPILE_RING0:
611 case EMEXECPOLICY_RECOMPILE_RING3:
612 *pfEnforced = false;
613 break;
614 case EMEXECPOLICY_IEM_ALL:
615 *pfEnforced = pVM->em.s.fIemExecutesAll;
616 break;
617 default:
618 AssertFailedReturn(VERR_INTERNAL_ERROR_2);
619 }
620
621 return VINF_SUCCESS;
622}
623
624
625/**
626 * Queries the main execution engine of the VM.
627 *
628 * @returns VBox status code
629 * @param pUVM The user mode VM handle.
630 * @param pbMainExecutionEngine Where to return the result, VM_EXEC_ENGINE_XXX.
631 */
632VMMR3DECL(int) EMR3QueryMainExecutionEngine(PUVM pUVM, uint8_t *pbMainExecutionEngine)
633{
634 AssertPtrReturn(pbMainExecutionEngine, VERR_INVALID_POINTER);
635 *pbMainExecutionEngine = VM_EXEC_ENGINE_NOT_SET;
636
637 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
638 PVM pVM = pUVM->pVM;
639 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
640
641 *pbMainExecutionEngine = pVM->bMainExecutionEngine;
642 return VINF_SUCCESS;
643}
644
645
646/**
647 * Raise a fatal error.
648 *
649 * Safely terminate the VM with full state report and stuff. This function
650 * will naturally never return.
651 *
652 * @param pVCpu The cross context virtual CPU structure.
653 * @param rc VBox status code.
654 */
655VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
656{
657 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
658 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
659}
660
661
662#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
663/**
664 * Gets the EM state name.
665 *
666 * @returns pointer to read only state name,
667 * @param enmState The state.
668 */
669static const char *emR3GetStateName(EMSTATE enmState)
670{
671 switch (enmState)
672 {
673 case EMSTATE_NONE: return "EMSTATE_NONE";
674 case EMSTATE_RAW: return "EMSTATE_RAW";
675 case EMSTATE_HM: return "EMSTATE_HM";
676 case EMSTATE_IEM: return "EMSTATE_IEM";
677 case EMSTATE_REM: return "EMSTATE_REM";
678 case EMSTATE_HALTED: return "EMSTATE_HALTED";
679 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
680 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
681 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
682 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
683 case EMSTATE_DEBUG_GUEST_HM: return "EMSTATE_DEBUG_GUEST_HM";
684 case EMSTATE_DEBUG_GUEST_IEM: return "EMSTATE_DEBUG_GUEST_IEM";
685 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
686 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
687 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
688 case EMSTATE_IEM_THEN_REM: return "EMSTATE_IEM_THEN_REM";
689 case EMSTATE_NEM: return "EMSTATE_NEM";
690 case EMSTATE_DEBUG_GUEST_NEM: return "EMSTATE_DEBUG_GUEST_NEM";
691 default: return "Unknown!";
692 }
693}
694#endif /* LOG_ENABLED || VBOX_STRICT */
695
696
697/**
698 * Handle pending ring-3 I/O port write.
699 *
700 * This is in response to a VINF_EM_PENDING_R3_IOPORT_WRITE status code returned
701 * by EMRZSetPendingIoPortWrite() in ring-0 or raw-mode context.
702 *
703 * @returns Strict VBox status code.
704 * @param pVM The cross context VM structure.
705 * @param pVCpu The cross context virtual CPU structure.
706 */
707VBOXSTRICTRC emR3ExecutePendingIoPortWrite(PVM pVM, PVMCPU pVCpu)
708{
709 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS);
710
711 /* Get and clear the pending data. */
712 RTIOPORT const uPort = pVCpu->em.s.PendingIoPortAccess.uPort;
713 uint32_t const uValue = pVCpu->em.s.PendingIoPortAccess.uValue;
714 uint8_t const cbValue = pVCpu->em.s.PendingIoPortAccess.cbValue;
715 uint8_t const cbInstr = pVCpu->em.s.PendingIoPortAccess.cbInstr;
716 pVCpu->em.s.PendingIoPortAccess.cbValue = 0;
717
718 /* Assert sanity. */
719 switch (cbValue)
720 {
721 case 1: Assert(!(cbValue & UINT32_C(0xffffff00))); break;
722 case 2: Assert(!(cbValue & UINT32_C(0xffff0000))); break;
723 case 4: break;
724 default: AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_EM_INTERNAL_ERROR);
725 }
726 AssertReturn(cbInstr <= 15 && cbInstr >= 1, VERR_EM_INTERNAL_ERROR);
727
728 /* Do the work.*/
729 VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, uPort, uValue, cbValue);
730 LogFlow(("EM/OUT: %#x, %#x LB %u -> %Rrc\n", uPort, uValue, cbValue, VBOXSTRICTRC_VAL(rcStrict) ));
731 if (IOM_SUCCESS(rcStrict))
732 {
733 pVCpu->cpum.GstCtx.rip += cbInstr;
734 pVCpu->cpum.GstCtx.rflags.Bits.u1RF = 0;
735 }
736 return rcStrict;
737}
738
739
740/**
741 * Handle pending ring-3 I/O port write.
742 *
743 * This is in response to a VINF_EM_PENDING_R3_IOPORT_WRITE status code returned
744 * by EMRZSetPendingIoPortRead() in ring-0 or raw-mode context.
745 *
746 * @returns Strict VBox status code.
747 * @param pVM The cross context VM structure.
748 * @param pVCpu The cross context virtual CPU structure.
749 */
750VBOXSTRICTRC emR3ExecutePendingIoPortRead(PVM pVM, PVMCPU pVCpu)
751{
752 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_RAX);
753
754 /* Get and clear the pending data. */
755 RTIOPORT const uPort = pVCpu->em.s.PendingIoPortAccess.uPort;
756 uint8_t const cbValue = pVCpu->em.s.PendingIoPortAccess.cbValue;
757 uint8_t const cbInstr = pVCpu->em.s.PendingIoPortAccess.cbInstr;
758 pVCpu->em.s.PendingIoPortAccess.cbValue = 0;
759
760 /* Assert sanity. */
761 switch (cbValue)
762 {
763 case 1: break;
764 case 2: break;
765 case 4: break;
766 default: AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_EM_INTERNAL_ERROR);
767 }
768 AssertReturn(pVCpu->em.s.PendingIoPortAccess.uValue == UINT32_C(0x52454144) /* READ*/, VERR_EM_INTERNAL_ERROR);
769 AssertReturn(cbInstr <= 15 && cbInstr >= 1, VERR_EM_INTERNAL_ERROR);
770
771 /* Do the work.*/
772 uint32_t uValue = 0;
773 VBOXSTRICTRC rcStrict = IOMIOPortRead(pVM, pVCpu, uPort, &uValue, cbValue);
774 LogFlow(("EM/IN: %#x LB %u -> %Rrc, %#x\n", uPort, cbValue, VBOXSTRICTRC_VAL(rcStrict), uValue ));
775 if (IOM_SUCCESS(rcStrict))
776 {
777 if (cbValue == 4)
778 pVCpu->cpum.GstCtx.rax = uValue;
779 else if (cbValue == 2)
780 pVCpu->cpum.GstCtx.ax = (uint16_t)uValue;
781 else
782 pVCpu->cpum.GstCtx.al = (uint8_t)uValue;
783 pVCpu->cpum.GstCtx.rip += cbInstr;
784 pVCpu->cpum.GstCtx.rflags.Bits.u1RF = 0;
785 }
786 return rcStrict;
787}
788
789
790/**
791 * Debug loop.
792 *
793 * @returns VBox status code for EM.
794 * @param pVM The cross context VM structure.
795 * @param pVCpu The cross context virtual CPU structure.
796 * @param rc Current EM VBox status code.
797 */
798static VBOXSTRICTRC emR3Debug(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc)
799{
800 for (;;)
801 {
802 Log(("emR3Debug: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
803 const VBOXSTRICTRC rcLast = rc;
804
805 /*
806 * Debug related RC.
807 */
808 switch (VBOXSTRICTRC_VAL(rc))
809 {
810 /*
811 * Single step an instruction.
812 */
813 case VINF_EM_DBG_STEP:
814 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
815 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
816 AssertLogRelMsgFailedStmt(("Bad EM state."), VERR_EM_INTERNAL_ERROR);
817 else if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HM)
818 rc = EMR3HmSingleInstruction(pVM, pVCpu, 0 /*fFlags*/);
819 else if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_NEM)
820 rc = VBOXSTRICTRC_TODO(emR3NemSingleInstruction(pVM, pVCpu, 0 /*fFlags*/));
821#ifdef VBOX_WITH_REM /** @todo fix me? */
822 else if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM)
823 rc = emR3RemStep(pVM, pVCpu);
824#endif
825 else
826 {
827 rc = IEMExecOne(pVCpu); /** @todo add dedicated interface... */
828 if (rc == VINF_SUCCESS || rc == VINF_EM_RESCHEDULE)
829 rc = VINF_EM_DBG_STEPPED;
830 }
831 break;
832
833 /*
834 * Simple events: stepped, breakpoint, stop/assertion.
835 */
836 case VINF_EM_DBG_STEPPED:
837 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
838 break;
839
840 case VINF_EM_DBG_BREAKPOINT:
841 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
842 break;
843
844 case VINF_EM_DBG_STOP:
845 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
846 break;
847
848 case VINF_EM_DBG_EVENT:
849 rc = DBGFR3EventHandlePending(pVM, pVCpu);
850 break;
851
852 case VINF_EM_DBG_HYPER_STEPPED:
853 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
854 break;
855
856 case VINF_EM_DBG_HYPER_BREAKPOINT:
857 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
858 break;
859
860 case VINF_EM_DBG_HYPER_ASSERTION:
861 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
862 RTLogFlush(NULL);
863 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
864 break;
865
866 /*
867 * Guru meditation.
868 */
869 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
870 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
871 break;
872 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
873 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
874 break;
875 case VINF_EM_TRIPLE_FAULT: /** @todo Make a guru meditation event! */
876 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VINF_EM_TRIPLE_FAULT", 0, NULL, NULL);
877 break;
878
879 default: /** @todo don't use default for guru, but make special errors code! */
880 {
881 LogRel(("emR3Debug: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
882 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
883 break;
884 }
885 }
886
887 /*
888 * Process the result.
889 */
890 switch (VBOXSTRICTRC_VAL(rc))
891 {
892 /*
893 * Continue the debugging loop.
894 */
895 case VINF_EM_DBG_STEP:
896 case VINF_EM_DBG_STOP:
897 case VINF_EM_DBG_EVENT:
898 case VINF_EM_DBG_STEPPED:
899 case VINF_EM_DBG_BREAKPOINT:
900 case VINF_EM_DBG_HYPER_STEPPED:
901 case VINF_EM_DBG_HYPER_BREAKPOINT:
902 case VINF_EM_DBG_HYPER_ASSERTION:
903 break;
904
905 /*
906 * Resuming execution (in some form) has to be done here if we got
907 * a hypervisor debug event.
908 */
909 case VINF_SUCCESS:
910 case VINF_EM_RESUME:
911 case VINF_EM_SUSPEND:
912 case VINF_EM_RESCHEDULE:
913 case VINF_EM_RESCHEDULE_RAW:
914 case VINF_EM_RESCHEDULE_REM:
915 case VINF_EM_HALT:
916 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
917 AssertLogRelMsgFailedReturn(("Not implemented\n"), VERR_EM_INTERNAL_ERROR);
918 if (rc == VINF_SUCCESS)
919 rc = VINF_EM_RESCHEDULE;
920 return rc;
921
922 /*
923 * The debugger isn't attached.
924 * We'll simply turn the thing off since that's the easiest thing to do.
925 */
926 case VERR_DBGF_NOT_ATTACHED:
927 switch (VBOXSTRICTRC_VAL(rcLast))
928 {
929 case VINF_EM_DBG_HYPER_STEPPED:
930 case VINF_EM_DBG_HYPER_BREAKPOINT:
931 case VINF_EM_DBG_HYPER_ASSERTION:
932 case VERR_TRPM_PANIC:
933 case VERR_TRPM_DONT_PANIC:
934 case VERR_VMM_RING0_ASSERTION:
935 case VERR_VMM_HYPER_CR3_MISMATCH:
936 case VERR_VMM_RING3_CALL_DISABLED:
937 return rcLast;
938 }
939 return VINF_EM_OFF;
940
941 /*
942 * Status codes terminating the VM in one or another sense.
943 */
944 case VINF_EM_TERMINATE:
945 case VINF_EM_OFF:
946 case VINF_EM_RESET:
947 case VINF_EM_NO_MEMORY:
948 case VINF_EM_RAW_STALE_SELECTOR:
949 case VINF_EM_RAW_IRET_TRAP:
950 case VERR_TRPM_PANIC:
951 case VERR_TRPM_DONT_PANIC:
952 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
953 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
954 case VERR_VMM_RING0_ASSERTION:
955 case VERR_VMM_HYPER_CR3_MISMATCH:
956 case VERR_VMM_RING3_CALL_DISABLED:
957 case VERR_INTERNAL_ERROR:
958 case VERR_INTERNAL_ERROR_2:
959 case VERR_INTERNAL_ERROR_3:
960 case VERR_INTERNAL_ERROR_4:
961 case VERR_INTERNAL_ERROR_5:
962 case VERR_IPE_UNEXPECTED_STATUS:
963 case VERR_IPE_UNEXPECTED_INFO_STATUS:
964 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
965 return rc;
966
967 /*
968 * The rest is unexpected, and will keep us here.
969 */
970 default:
971 AssertMsgFailed(("Unexpected rc %Rrc!\n", VBOXSTRICTRC_VAL(rc)));
972 break;
973 }
974 } /* debug for ever */
975}
976
977
978#if defined(VBOX_WITH_REM) || defined(DEBUG)
979/**
980 * Steps recompiled code.
981 *
982 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
983 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
984 *
985 * @param pVM The cross context VM structure.
986 * @param pVCpu The cross context virtual CPU structure.
987 */
988static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
989{
990 Log3(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
991
992 int rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
993
994 Log3(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
995 return rc;
996}
997#endif /* VBOX_WITH_REM || DEBUG */
998
999
1000/**
1001 * Executes recompiled code.
1002 *
1003 * This function contains the recompiler version of the inner
1004 * execution loop (the outer loop being in EMR3ExecuteVM()).
1005 *
1006 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1007 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1008 *
1009 * @param pVM The cross context VM structure.
1010 * @param pVCpu The cross context virtual CPU structure.
1011 * @param pfFFDone Where to store an indicator telling whether or not
1012 * FFs were done before returning.
1013 *
1014 */
1015static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1016{
1017#ifdef LOG_ENABLED
1018 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
1019
1020 if (pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
1021 Log(("EMV86: %04X:%08X IF=%d\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF));
1022 else
1023 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, (uint32_t)pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.eflags.u));
1024#endif
1025 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
1026
1027#if defined(VBOX_STRICT) && defined(DEBUG_bird)
1028 AssertMsg( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1029 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo @bugref{1419} - get flat address. */
1030 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1031#endif
1032
1033 /*
1034 * Spin till we get a forced action which returns anything but VINF_SUCCESS
1035 * or the REM suggests raw-mode execution.
1036 */
1037 *pfFFDone = false;
1038 uint32_t cLoops = 0;
1039 int rc = VINF_SUCCESS;
1040 for (;;)
1041 {
1042 /*
1043 * Execute REM.
1044 */
1045 if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1046 {
1047 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
1048 rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu, 8192 /*cMaxInstructions*/, 4095 /*cPollRate*/, NULL /*pcInstructions*/));
1049 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
1050 }
1051 else
1052 {
1053 /* Give up this time slice; virtual time continues */
1054 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1055 RTThreadSleep(5);
1056 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1057 rc = VINF_SUCCESS;
1058 }
1059
1060 /*
1061 * Deal with high priority post execution FFs before doing anything
1062 * else. Sync back the state and leave the lock to be on the safe side.
1063 */
1064 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1065 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1066 rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc));
1067
1068 /*
1069 * Process the returned status code.
1070 */
1071 if (rc != VINF_SUCCESS)
1072 {
1073 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1074 break;
1075 if (rc != VINF_REM_INTERRUPED_FF)
1076 {
1077 /* Try dodge unimplemented IEM trouble by reschduling. */
1078 if ( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1079 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED)
1080 {
1081 EMSTATE enmNewState = emR3Reschedule(pVM, pVCpu);
1082 if (enmNewState != EMSTATE_REM && enmNewState != EMSTATE_IEM_THEN_REM)
1083 {
1084 rc = VINF_EM_RESCHEDULE;
1085 break;
1086 }
1087 }
1088
1089 /*
1090 * Anything which is not known to us means an internal error
1091 * and the termination of the VM!
1092 */
1093 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1094 break;
1095 }
1096 }
1097
1098
1099 /*
1100 * Check and execute forced actions.
1101 *
1102 * Sync back the VM state and leave the lock before calling any of
1103 * these, you never know what's going to happen here.
1104 */
1105#ifdef VBOX_HIGH_RES_TIMERS_HACK
1106 TMTimerPollVoid(pVM, pVCpu);
1107#endif
1108 AssertCompile(VMCPU_FF_ALL_REM_MASK & VMCPU_FF_TIMER);
1109 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_ALL_REM_MASK)
1110 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_REM_MASK) )
1111 {
1112 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1113 rc = emR3ForcedActions(pVM, pVCpu, rc);
1114 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1115 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1116 if ( rc != VINF_SUCCESS
1117 && rc != VINF_EM_RESCHEDULE_REM)
1118 {
1119 *pfFFDone = true;
1120 break;
1121 }
1122 }
1123
1124 /*
1125 * Have to check if we can get back to fast execution mode every so often.
1126 */
1127 if (!(++cLoops & 7))
1128 {
1129 EMSTATE enmCheck = emR3Reschedule(pVM, pVCpu);
1130 if ( enmCheck != EMSTATE_REM
1131 && enmCheck != EMSTATE_IEM_THEN_REM)
1132 return VINF_EM_RESCHEDULE;
1133 }
1134
1135 } /* The Inner Loop, recompiled execution mode version. */
1136
1137 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1138 return rc;
1139}
1140
1141
1142#ifdef DEBUG
1143
1144int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1145{
1146 EMSTATE enmOldState = pVCpu->em.s.enmState;
1147
1148 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1149
1150 Log(("Single step BEGIN:\n"));
1151 for (uint32_t i = 0; i < cIterations; i++)
1152 {
1153 DBGFR3PrgStep(pVCpu);
1154 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
1155 emR3RemStep(pVM, pVCpu);
1156 if (emR3Reschedule(pVM, pVCpu) != EMSTATE_REM)
1157 break;
1158 }
1159 Log(("Single step END:\n"));
1160 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1161 pVCpu->em.s.enmState = enmOldState;
1162 return VINF_EM_RESCHEDULE;
1163}
1164
1165#endif /* DEBUG */
1166
1167
1168/**
1169 * Try execute the problematic code in IEM first, then fall back on REM if there
1170 * is too much of it or if IEM doesn't implement something.
1171 *
1172 * @returns Strict VBox status code from IEMExecLots.
1173 * @param pVM The cross context VM structure.
1174 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1175 * @param pfFFDone Force flags done indicator.
1176 *
1177 * @thread EMT(pVCpu)
1178 */
1179static VBOXSTRICTRC emR3ExecuteIemThenRem(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1180{
1181 LogFlow(("emR3ExecuteIemThenRem: %04x:%RGv\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestRIP(pVCpu)));
1182 *pfFFDone = false;
1183
1184 /*
1185 * Execute in IEM for a while.
1186 */
1187 while (pVCpu->em.s.cIemThenRemInstructions < 1024)
1188 {
1189 uint32_t cInstructions;
1190 VBOXSTRICTRC rcStrict = IEMExecLots(pVCpu, 1024 - pVCpu->em.s.cIemThenRemInstructions /*cMaxInstructions*/,
1191 UINT32_MAX/2 /*cPollRate*/, &cInstructions);
1192 pVCpu->em.s.cIemThenRemInstructions += cInstructions;
1193 if (rcStrict != VINF_SUCCESS)
1194 {
1195 if ( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1196 || rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED)
1197 break;
1198
1199 Log(("emR3ExecuteIemThenRem: returns %Rrc after %u instructions\n",
1200 VBOXSTRICTRC_VAL(rcStrict), pVCpu->em.s.cIemThenRemInstructions));
1201 return rcStrict;
1202 }
1203
1204 EMSTATE enmNewState = emR3Reschedule(pVM, pVCpu);
1205 if (enmNewState != EMSTATE_REM && enmNewState != EMSTATE_IEM_THEN_REM)
1206 {
1207 LogFlow(("emR3ExecuteIemThenRem: -> %d (%s) after %u instructions\n",
1208 enmNewState, emR3GetStateName(enmNewState), pVCpu->em.s.cIemThenRemInstructions));
1209 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1210 pVCpu->em.s.enmState = enmNewState;
1211 return VINF_SUCCESS;
1212 }
1213
1214 /*
1215 * Check for pending actions.
1216 */
1217 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_ALL_REM_MASK)
1218 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_REM_MASK & ~VMCPU_FF_UNHALT))
1219 return VINF_SUCCESS;
1220 }
1221
1222 /*
1223 * Switch to REM.
1224 */
1225 Log(("emR3ExecuteIemThenRem: -> EMSTATE_REM (after %u instructions)\n", pVCpu->em.s.cIemThenRemInstructions));
1226 pVCpu->em.s.enmState = EMSTATE_REM;
1227 return VINF_SUCCESS;
1228}
1229
1230
1231/**
1232 * Decides whether to execute RAW, HWACC or REM.
1233 *
1234 * @returns new EM state
1235 * @param pVM The cross context VM structure.
1236 * @param pVCpu The cross context virtual CPU structure.
1237 */
1238EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu)
1239{
1240 /*
1241 * We stay in the wait for SIPI state unless explicitly told otherwise.
1242 */
1243 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1244 return EMSTATE_WAIT_SIPI;
1245
1246 /*
1247 * Execute everything in IEM?
1248 */
1249 if (pVM->em.s.fIemExecutesAll)
1250 return EMSTATE_IEM;
1251
1252 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1253 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1254 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1255
1256 X86EFLAGS EFlags = pVCpu->cpum.GstCtx.eflags;
1257 if (!VM_IS_RAW_MODE_ENABLED(pVM))
1258 {
1259 if (VM_IS_HM_ENABLED(pVM))
1260 {
1261 if (HMCanExecuteGuest(pVM, pVCpu, &pVCpu->cpum.GstCtx))
1262 return EMSTATE_HM;
1263 }
1264 else if (NEMR3CanExecuteGuest(pVM, pVCpu))
1265 return EMSTATE_NEM;
1266
1267 /*
1268 * Note! Raw mode and hw accelerated mode are incompatible. The latter
1269 * turns off monitoring features essential for raw mode!
1270 */
1271 return EMSTATE_IEM_THEN_REM;
1272 }
1273
1274 /*
1275 * Standard raw-mode:
1276 *
1277 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1278 * or 32 bits protected mode ring 0 code
1279 *
1280 * The tests are ordered by the likelihood of being true during normal execution.
1281 */
1282 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1283 {
1284 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1285 return EMSTATE_REM;
1286 }
1287
1288# ifndef VBOX_RAW_V86
1289 if (EFlags.u32 & X86_EFL_VM) {
1290 Log2(("raw mode refused: VM_MASK\n"));
1291 return EMSTATE_REM;
1292 }
1293# endif
1294
1295 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1296 uint32_t u32CR0 = pVCpu->cpum.GstCtx.cr0;
1297 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1298 {
1299 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1300 return EMSTATE_REM;
1301 }
1302
1303 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1304 {
1305 uint32_t u32Dummy, u32Features;
1306
1307 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1308 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1309 return EMSTATE_REM;
1310 }
1311
1312 unsigned uSS = pVCpu->cpum.GstCtx.ss.Sel;
1313 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1VM
1314 || (uSS & X86_SEL_RPL) == 3)
1315 {
1316 if (!(EFlags.u32 & X86_EFL_IF))
1317 {
1318 Log2(("raw mode refused: IF (RawR3)\n"));
1319 return EMSTATE_REM;
1320 }
1321
1322 if (!(u32CR0 & X86_CR0_WP))
1323 {
1324 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1325 return EMSTATE_REM;
1326 }
1327 }
1328 else
1329 {
1330 /* Only ring 0 supervisor code. */
1331 if ((uSS & X86_SEL_RPL) != 0)
1332 {
1333 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1334 return EMSTATE_REM;
1335 }
1336
1337 // Let's start with pure 32 bits ring 0 code first
1338 /** @todo What's pure 32-bit mode? flat? */
1339 if ( !(pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
1340 || !(pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig))
1341 {
1342 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1343 return EMSTATE_REM;
1344 }
1345
1346 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1347 if (!(u32CR0 & X86_CR0_WP))
1348 {
1349 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1350 return EMSTATE_REM;
1351 }
1352
1353# if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1354 if (!(EFlags.u32 & X86_EFL_IF))
1355 {
1356 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1357 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1358 return EMSTATE_REM;
1359 }
1360# endif
1361
1362# ifndef VBOX_WITH_RAW_RING1
1363 /** @todo still necessary??? */
1364 if (EFlags.Bits.u2IOPL != 0)
1365 {
1366 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1367 return EMSTATE_REM;
1368 }
1369# endif
1370 }
1371
1372 /*
1373 * Stale hidden selectors means raw-mode is unsafe (being very careful).
1374 */
1375 if (pVCpu->cpum.GstCtx.cs.fFlags & CPUMSELREG_FLAGS_STALE)
1376 {
1377 Log2(("raw mode refused: stale CS\n"));
1378 return EMSTATE_REM;
1379 }
1380 if (pVCpu->cpum.GstCtx.ss.fFlags & CPUMSELREG_FLAGS_STALE)
1381 {
1382 Log2(("raw mode refused: stale SS\n"));
1383 return EMSTATE_REM;
1384 }
1385 if (pVCpu->cpum.GstCtx.ds.fFlags & CPUMSELREG_FLAGS_STALE)
1386 {
1387 Log2(("raw mode refused: stale DS\n"));
1388 return EMSTATE_REM;
1389 }
1390 if (pVCpu->cpum.GstCtx.es.fFlags & CPUMSELREG_FLAGS_STALE)
1391 {
1392 Log2(("raw mode refused: stale ES\n"));
1393 return EMSTATE_REM;
1394 }
1395 if (pVCpu->cpum.GstCtx.fs.fFlags & CPUMSELREG_FLAGS_STALE)
1396 {
1397 Log2(("raw mode refused: stale FS\n"));
1398 return EMSTATE_REM;
1399 }
1400 if (pVCpu->cpum.GstCtx.gs.fFlags & CPUMSELREG_FLAGS_STALE)
1401 {
1402 Log2(("raw mode refused: stale GS\n"));
1403 return EMSTATE_REM;
1404 }
1405
1406# ifdef VBOX_WITH_SAFE_STR
1407 if (pVCpu->cpum.GstCtx.tr.Sel == 0)
1408 {
1409 Log(("Raw mode refused -> TR=0\n"));
1410 return EMSTATE_REM;
1411 }
1412# endif
1413
1414 /*Assert(PGMPhysIsA20Enabled(pVCpu));*/
1415 return EMSTATE_RAW;
1416}
1417
1418
1419/**
1420 * Executes all high priority post execution force actions.
1421 *
1422 * @returns Strict VBox status code. Typically @a rc, but may be upgraded to
1423 * fatal error status code.
1424 *
1425 * @param pVM The cross context VM structure.
1426 * @param pVCpu The cross context virtual CPU structure.
1427 * @param rc The current strict VBox status code rc.
1428 */
1429VBOXSTRICTRC emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc)
1430{
1431 VBOXVMM_EM_FF_HIGH(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, VBOXSTRICTRC_VAL(rc));
1432
1433 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PDM_CRITSECT))
1434 PDMCritSectBothFF(pVCpu);
1435
1436 /* Update CR3 (Nested Paging case for HM). */
1437 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
1438 {
1439 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER, rc);
1440 int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
1441 if (RT_FAILURE(rc2))
1442 return rc2;
1443 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
1444 }
1445
1446 /* Update PAE PDPEs. This must be done *after* PGMUpdateCR3() and used only by the Nested Paging case for HM. */
1447 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
1448 {
1449 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER, rc);
1450 if (CPUMIsGuestInPAEMode(pVCpu))
1451 {
1452 PX86PDPE pPdpes = HMGetPaePdpes(pVCpu);
1453 AssertPtr(pPdpes);
1454
1455 PGMGstUpdatePaePdpes(pVCpu, pPdpes);
1456 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
1457 }
1458 else
1459 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1460 }
1461
1462 /* IEM has pending work (typically memory write after INS instruction). */
1463 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_IEM))
1464 rc = IEMR3ProcessForceFlag(pVM, pVCpu, rc);
1465
1466 /* IOM has pending work (comitting an I/O or MMIO write). */
1467 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_IOM))
1468 {
1469 rc = IOMR3ProcessForceFlag(pVM, pVCpu, rc);
1470 if (pVCpu->em.s.idxContinueExitRec >= RT_ELEMENTS(pVCpu->em.s.aExitRecords))
1471 { /* half likely, or at least it's a line shorter. */ }
1472 else if (rc == VINF_SUCCESS)
1473 rc = VINF_EM_RESUME_R3_HISTORY_EXEC;
1474 else
1475 pVCpu->em.s.idxContinueExitRec = UINT16_MAX;
1476 }
1477
1478 if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
1479 {
1480 if ( rc > VINF_EM_NO_MEMORY
1481 && rc <= VINF_EM_LAST)
1482 rc = VINF_EM_NO_MEMORY;
1483 }
1484
1485 return rc;
1486}
1487
1488
1489/**
1490 * Helper for emR3ForcedActions() for VMX external interrupt VM-exit.
1491 *
1492 * @returns VBox status code.
1493 * @retval VINF_NO_CHANGE if the VMX external interrupt intercept was not active.
1494 * @param pVCpu The cross context virtual CPU structure.
1495 */
1496static int emR3VmxNstGstIntrIntercept(PVMCPU pVCpu)
1497{
1498#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1499 /* Handle the "external interrupt" VM-exit intercept. */
1500 if (CPUMIsGuestVmxPinCtlsSet(&pVCpu->cpum.GstCtx, VMX_PIN_CTLS_EXT_INT_EXIT))
1501 {
1502 VBOXSTRICTRC rcStrict = IEMExecVmxVmexitExtInt(pVCpu, 0 /* uVector */, true /* fIntPending */);
1503 AssertMsg( rcStrict != VINF_PGM_CHANGE_MODE
1504 && rcStrict != VINF_VMX_VMEXIT
1505 && rcStrict != VINF_NO_CHANGE, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1506 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
1507 return VBOXSTRICTRC_TODO(rcStrict);
1508 }
1509#else
1510 RT_NOREF(pVCpu);
1511#endif
1512 return VINF_NO_CHANGE;
1513}
1514
1515
1516/**
1517 * Helper for emR3ForcedActions() for SVM interrupt intercept.
1518 *
1519 * @returns VBox status code.
1520 * @retval VINF_NO_CHANGE if the SVM external interrupt intercept was not active.
1521 * @param pVCpu The cross context virtual CPU structure.
1522 */
1523static int emR3SvmNstGstIntrIntercept(PVMCPU pVCpu)
1524{
1525#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1526 /* Handle the physical interrupt intercept (can be masked by the nested hypervisor). */
1527 if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_INTR))
1528 {
1529 CPUM_ASSERT_NOT_EXTRN(pVCpu, IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK);
1530 VBOXSTRICTRC rcStrict = IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
1531 if (RT_SUCCESS(rcStrict))
1532 {
1533 AssertMsg( rcStrict != VINF_PGM_CHANGE_MODE
1534 && rcStrict != VINF_SVM_VMEXIT
1535 && rcStrict != VINF_NO_CHANGE, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1536 return VBOXSTRICTRC_VAL(rcStrict);
1537 }
1538
1539 AssertMsgFailed(("INTR #VMEXIT failed! rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1540 return VINF_EM_TRIPLE_FAULT;
1541 }
1542#else
1543 NOREF(pVCpu);
1544#endif
1545 return VINF_NO_CHANGE;
1546}
1547
1548
1549/**
1550 * Helper for emR3ForcedActions() for SVM virtual interrupt intercept.
1551 *
1552 * @returns VBox status code.
1553 * @retval VINF_NO_CHANGE if the SVM virtual interrupt intercept was not active.
1554 * @param pVCpu The cross context virtual CPU structure.
1555 */
1556static int emR3SvmNstGstVirtIntrIntercept(PVMCPU pVCpu)
1557{
1558#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1559 if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_VINTR))
1560 {
1561 CPUM_ASSERT_NOT_EXTRN(pVCpu, IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK);
1562 VBOXSTRICTRC rcStrict = IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
1563 if (RT_SUCCESS(rcStrict))
1564 {
1565 Assert(rcStrict != VINF_PGM_CHANGE_MODE);
1566 Assert(rcStrict != VINF_SVM_VMEXIT);
1567 return VBOXSTRICTRC_VAL(rcStrict);
1568 }
1569 AssertMsgFailed(("VINTR #VMEXIT failed! rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1570 return VINF_EM_TRIPLE_FAULT;
1571 }
1572#else
1573 NOREF(pVCpu);
1574#endif
1575 return VINF_NO_CHANGE;
1576}
1577
1578
1579/**
1580 * Executes all pending forced actions.
1581 *
1582 * Forced actions can cause execution delays and execution
1583 * rescheduling. The first we deal with using action priority, so
1584 * that for instance pending timers aren't scheduled and ran until
1585 * right before execution. The rescheduling we deal with using
1586 * return codes. The same goes for VM termination, only in that case
1587 * we exit everything.
1588 *
1589 * @returns VBox status code of equal or greater importance/severity than rc.
1590 * The most important ones are: VINF_EM_RESCHEDULE,
1591 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1592 *
1593 * @param pVM The cross context VM structure.
1594 * @param pVCpu The cross context virtual CPU structure.
1595 * @param rc The current rc.
1596 *
1597 */
1598int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1599{
1600 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1601#ifdef VBOX_STRICT
1602 int rcIrq = VINF_SUCCESS;
1603#endif
1604 int rc2;
1605#define UPDATE_RC() \
1606 do { \
1607 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1608 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1609 break; \
1610 if (!rc || rc2 < rc) \
1611 rc = rc2; \
1612 } while (0)
1613 VBOXVMM_EM_FF_ALL(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1614
1615 /*
1616 * Post execution chunk first.
1617 */
1618 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1619 || (VMCPU_FF_NORMAL_PRIORITY_POST_MASK && VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK)) )
1620 {
1621 /*
1622 * EMT Rendezvous (must be serviced before termination).
1623 */
1624 if (VM_FF_IS_SET(pVM, VM_FF_EMT_RENDEZVOUS))
1625 {
1626 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK, rc);
1627 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1628 UPDATE_RC();
1629 /** @todo HACK ALERT! The following test is to make sure EM+TM
1630 * thinks the VM is stopped/reset before the next VM state change
1631 * is made. We need a better solution for this, or at least make it
1632 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1633 * VINF_EM_SUSPEND). */
1634 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1635 {
1636 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1637 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1638 return rc;
1639 }
1640 }
1641
1642 /*
1643 * State change request (cleared by vmR3SetStateLocked).
1644 */
1645 if (VM_FF_IS_SET(pVM, VM_FF_CHECK_VM_STATE))
1646 {
1647 VMSTATE enmState = VMR3GetState(pVM);
1648 switch (enmState)
1649 {
1650 case VMSTATE_FATAL_ERROR:
1651 case VMSTATE_FATAL_ERROR_LS:
1652 case VMSTATE_GURU_MEDITATION:
1653 case VMSTATE_GURU_MEDITATION_LS:
1654 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1655 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1656 return VINF_EM_SUSPEND;
1657
1658 case VMSTATE_DESTROYING:
1659 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1660 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1661 return VINF_EM_TERMINATE;
1662
1663 default:
1664 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1665 }
1666 }
1667
1668 /*
1669 * Debugger Facility polling.
1670 */
1671 if ( VM_FF_IS_SET(pVM, VM_FF_DBGF)
1672 || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_DBGF) )
1673 {
1674 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK, rc);
1675 rc2 = DBGFR3VMMForcedAction(pVM, pVCpu);
1676 UPDATE_RC();
1677 }
1678
1679 /*
1680 * Postponed reset request.
1681 */
1682 if (VM_FF_TEST_AND_CLEAR(pVM, VM_FF_RESET))
1683 {
1684 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK, rc);
1685 rc2 = VBOXSTRICTRC_TODO(VMR3ResetFF(pVM));
1686 UPDATE_RC();
1687 }
1688
1689 /*
1690 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1691 */
1692 if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
1693 {
1694 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1695 UPDATE_RC();
1696 if (rc == VINF_EM_NO_MEMORY)
1697 return rc;
1698 }
1699
1700 /* check that we got them all */
1701 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1702 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_DBGF);
1703 }
1704
1705 /*
1706 * Normal priority then.
1707 * (Executed in no particular order.)
1708 */
1709 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1710 {
1711 /*
1712 * PDM Queues are pending.
1713 */
1714 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1715 PDMR3QueueFlushAll(pVM);
1716
1717 /*
1718 * PDM DMA transfers are pending.
1719 */
1720 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1721 PDMR3DmaRun(pVM);
1722
1723 /*
1724 * EMT Rendezvous (make sure they are handled before the requests).
1725 */
1726 if (VM_FF_IS_SET(pVM, VM_FF_EMT_RENDEZVOUS))
1727 {
1728 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK, rc);
1729 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1730 UPDATE_RC();
1731 /** @todo HACK ALERT! The following test is to make sure EM+TM
1732 * thinks the VM is stopped/reset before the next VM state change
1733 * is made. We need a better solution for this, or at least make it
1734 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1735 * VINF_EM_SUSPEND). */
1736 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1737 {
1738 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1739 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1740 return rc;
1741 }
1742 }
1743
1744 /*
1745 * Requests from other threads.
1746 */
1747 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1748 {
1749 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK, rc);
1750 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY, false /*fPriorityOnly*/);
1751 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1752 {
1753 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1754 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1755 return rc2;
1756 }
1757 UPDATE_RC();
1758 /** @todo HACK ALERT! The following test is to make sure EM+TM
1759 * thinks the VM is stopped/reset before the next VM state change
1760 * is made. We need a better solution for this, or at least make it
1761 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1762 * VINF_EM_SUSPEND). */
1763 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1764 {
1765 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1766 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1767 return rc;
1768 }
1769 }
1770
1771 /* check that we got them all */
1772 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS));
1773 }
1774
1775 /*
1776 * Normal priority then. (per-VCPU)
1777 * (Executed in no particular order.)
1778 */
1779 if ( !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)
1780 && VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1781 {
1782 /*
1783 * Requests from other threads.
1784 */
1785 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
1786 {
1787 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK, rc);
1788 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, false /*fPriorityOnly*/);
1789 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1790 {
1791 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1792 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1793 return rc2;
1794 }
1795 UPDATE_RC();
1796 /** @todo HACK ALERT! The following test is to make sure EM+TM
1797 * thinks the VM is stopped/reset before the next VM state change
1798 * is made. We need a better solution for this, or at least make it
1799 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1800 * VINF_EM_SUSPEND). */
1801 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1802 {
1803 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1804 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1805 return rc;
1806 }
1807 }
1808
1809 /* check that we got them all */
1810 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~VMCPU_FF_REQUEST));
1811 }
1812
1813 /*
1814 * High priority pre execution chunk last.
1815 * (Executed in ascending priority order.)
1816 */
1817 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1818 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1819 {
1820 /*
1821 * Timers before interrupts.
1822 */
1823 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TIMER)
1824 && !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
1825 TMR3TimerQueuesDo(pVM);
1826
1827 /*
1828 * Pick up asynchronously posted interrupts into the APIC.
1829 */
1830 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
1831 APICUpdatePendingInterrupts(pVCpu);
1832
1833 /*
1834 * The instruction following an emulated STI should *always* be executed!
1835 *
1836 * Note! We intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if
1837 * the eip is the same as the inhibited instr address. Before we
1838 * are able to execute this instruction in raw mode (iret to
1839 * guest code) an external interrupt might force a world switch
1840 * again. Possibly allowing a guest interrupt to be dispatched
1841 * in the process. This could break the guest. Sounds very
1842 * unlikely, but such timing sensitive problem are not as rare as
1843 * you might think.
1844 */
1845 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1846 && !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
1847 {
1848 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
1849 if (CPUMGetGuestRIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1850 {
1851 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1852 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1853 }
1854 else
1855 Log(("Leaving VMCPU_FF_INHIBIT_INTERRUPTS set at %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
1856 }
1857
1858 /** @todo SMIs. If we implement SMIs, this is where they will have to be
1859 * delivered. */
1860
1861#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1862 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_PREEMPT_TIMER))
1863 {
1864 /*
1865 * VMX Nested-guest APIC-write pending (can cause VM-exits).
1866 * Takes priority over even SMI and INIT signals.
1867 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
1868 */
1869 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
1870 {
1871 rc2 = VBOXSTRICTRC_VAL(IEMExecVmxVmexitApicWrite(pVCpu));
1872 if (rc2 != VINF_VMX_INTERCEPT_NOT_ACTIVE)
1873 UPDATE_RC();
1874 }
1875
1876 /*
1877 * VMX Nested-guest monitor-trap flag (MTF) VM-exit.
1878 * Takes priority over "Traps on the previous instruction".
1879 * See Intel spec. 6.9 "Priority Among Simultaneous Exceptions And Interrupts".
1880 */
1881 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF))
1882 {
1883 rc2 = VBOXSTRICTRC_VAL(IEMExecVmxVmexit(pVCpu, VMX_EXIT_MTF, 0 /* uExitQual */));
1884 Assert(rc2 != VINF_VMX_INTERCEPT_NOT_ACTIVE);
1885 UPDATE_RC();
1886 }
1887
1888 /*
1889 * VMX Nested-guest preemption timer VM-exit.
1890 * Takes priority over NMI-window VM-exits.
1891 */
1892 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER))
1893 {
1894 rc2 = VBOXSTRICTRC_VAL(IEMExecVmxVmexitPreemptTimer(pVCpu));
1895 Assert(rc2 != VINF_VMX_INTERCEPT_NOT_ACTIVE);
1896 UPDATE_RC();
1897 }
1898 }
1899#endif
1900
1901 /*
1902 * Guest event injection.
1903 */
1904 bool fWakeupPending = false;
1905 if ( !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)
1906 && (!rc || rc >= VINF_EM_RESCHEDULE_HM)
1907 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) /* Interrupt shadows block both NMIs and interrupts. */
1908 && !TRPMHasTrap(pVCpu)) /* An event could already be scheduled for dispatching. */
1909 {
1910 bool fInVmxNonRootMode;
1911 bool fInSvmHwvirtMode;
1912 bool const fInNestedGuest = CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.GstCtx);
1913 if (fInNestedGuest)
1914 {
1915 fInVmxNonRootMode = CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx);
1916 fInSvmHwvirtMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
1917 }
1918 else
1919 {
1920 fInVmxNonRootMode = false;
1921 fInSvmHwvirtMode = false;
1922 }
1923
1924 bool fGif = CPUMGetGuestGif(&pVCpu->cpum.GstCtx);
1925 if (fGif)
1926 {
1927#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1928 /*
1929 * VMX NMI-window VM-exit.
1930 * Takes priority over non-maskable interrupts (NMIs).
1931 * Interrupt shadows block NMI-window VM-exits.
1932 * Any event that is already in TRPM (e.g. injected during VM-entry) takes priority.
1933 *
1934 * See Intel spec. 25.2 "Other Causes Of VM Exits".
1935 * See Intel spec. 26.7.6 "NMI-Window Exiting".
1936 */
1937 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW)
1938 && !CPUMIsGuestVmxVirtNmiBlocking(&pVCpu->cpum.GstCtx))
1939 {
1940 Assert(CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_NMI_WINDOW_EXIT));
1941 Assert(CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx));
1942 rc2 = VBOXSTRICTRC_VAL(IEMExecVmxVmexit(pVCpu, VMX_EXIT_NMI_WINDOW, 0 /* uExitQual */));
1943 AssertMsg( rc2 != VINF_VMX_INTERCEPT_NOT_ACTIVE
1944 && rc2 != VINF_PGM_CHANGE_MODE
1945 && rc2 != VINF_VMX_VMEXIT
1946 && rc2 != VINF_NO_CHANGE, ("%Rrc\n", rc2));
1947 UPDATE_RC();
1948 }
1949 else
1950#endif
1951 /*
1952 * NMIs (take priority over external interrupts).
1953 */
1954 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
1955 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1956 {
1957#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1958 if ( fInVmxNonRootMode
1959 && CPUMIsGuestVmxPinCtlsSet(&pVCpu->cpum.GstCtx, VMX_PIN_CTLS_NMI_EXIT))
1960 {
1961 rc2 = VBOXSTRICTRC_VAL(IEMExecVmxVmexitXcptNmi(pVCpu));
1962 Assert(rc2 != VINF_VMX_INTERCEPT_NOT_ACTIVE);
1963 UPDATE_RC();
1964 }
1965 else
1966#endif
1967#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1968 if ( fInSvmHwvirtMode
1969 && CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_NMI))
1970 {
1971 rc2 = VBOXSTRICTRC_VAL(IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */));
1972 AssertMsg( rc2 != VINF_PGM_CHANGE_MODE
1973 && rc2 != VINF_SVM_VMEXIT
1974 && rc2 != VINF_NO_CHANGE, ("%Rrc\n", rc2));
1975 UPDATE_RC();
1976 }
1977 else
1978#endif
1979 {
1980 rc2 = TRPMAssertTrap(pVCpu, X86_XCPT_NMI, TRPM_TRAP);
1981 if (rc2 == VINF_SUCCESS)
1982 {
1983 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
1984 fWakeupPending = true;
1985 if (pVM->em.s.fIemExecutesAll)
1986 rc2 = VINF_EM_RESCHEDULE;
1987 else
1988 {
1989 rc2 = HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM
1990 : VM_IS_NEM_ENABLED(pVM) ? VINF_EM_RESCHEDULE
1991 : VINF_EM_RESCHEDULE_REM;
1992 }
1993 }
1994 UPDATE_RC();
1995 }
1996 }
1997#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1998 /*
1999 * VMX Interrupt-window VM-exits.
2000 * Takes priority over external interrupts.
2001 */
2002 else if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW)
2003 && CPUMIsGuestVmxVirtIntrEnabled(&pVCpu->cpum.GstCtx))
2004 {
2005 Assert(CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_INT_WINDOW_EXIT));
2006 Assert(CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx));
2007 rc2 = VBOXSTRICTRC_VAL(IEMExecVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW, 0 /* uExitQual */));
2008 AssertMsg( rc2 != VINF_VMX_INTERCEPT_NOT_ACTIVE
2009 && rc2 != VINF_PGM_CHANGE_MODE
2010 && rc2 != VINF_VMX_VMEXIT
2011 && rc2 != VINF_NO_CHANGE, ("%Rrc\n", rc2));
2012 UPDATE_RC();
2013 }
2014#endif
2015#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2016 /** @todo NSTSVM: Handle this for SVM here too later not when an interrupt is
2017 * actually pending like we currently do. */
2018#endif
2019 /*
2020 * External interrupts.
2021 */
2022 else
2023 {
2024 /*
2025 * VMX: virtual interrupts takes priority over physical interrupts.
2026 * SVM: physical interrupts takes priority over virtual interrupts.
2027 */
2028 if ( fInVmxNonRootMode
2029 && VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
2030 && CPUMIsGuestVmxVirtIntrEnabled(&pVCpu->cpum.GstCtx))
2031 {
2032 /** @todo NSTVMX: virtual-interrupt delivery. */
2033 rc2 = VINF_SUCCESS;
2034 }
2035 else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)
2036 && CPUMIsGuestPhysIntrEnabled(pVCpu))
2037 {
2038 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
2039 if (fInVmxNonRootMode)
2040 rc2 = emR3VmxNstGstIntrIntercept(pVCpu);
2041 else if (fInSvmHwvirtMode)
2042 rc2 = emR3SvmNstGstIntrIntercept(pVCpu);
2043 else
2044 rc2 = VINF_NO_CHANGE;
2045
2046 if (rc2 == VINF_NO_CHANGE)
2047 {
2048 bool fInjected = false;
2049 CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
2050 /** @todo this really isn't nice, should properly handle this */
2051 /* Note! This can still cause a VM-exit (on Intel). */
2052 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT, &fInjected);
2053 fWakeupPending = true;
2054 if ( pVM->em.s.fIemExecutesAll
2055 && ( rc2 == VINF_EM_RESCHEDULE_REM
2056 || rc2 == VINF_EM_RESCHEDULE_HM
2057 || rc2 == VINF_EM_RESCHEDULE_RAW))
2058 {
2059 rc2 = VINF_EM_RESCHEDULE;
2060 }
2061#ifdef VBOX_STRICT
2062 if (fInjected)
2063 rcIrq = rc2;
2064#endif
2065 }
2066 UPDATE_RC();
2067 }
2068 else if ( fInSvmHwvirtMode
2069 && VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
2070 && CPUMIsGuestSvmVirtIntrEnabled(pVCpu, &pVCpu->cpum.GstCtx))
2071 {
2072 rc2 = emR3SvmNstGstVirtIntrIntercept(pVCpu);
2073 if (rc2 == VINF_NO_CHANGE)
2074 {
2075 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2076 uint8_t const uNstGstVector = CPUMGetGuestSvmVirtIntrVector(&pVCpu->cpum.GstCtx);
2077 AssertMsg(uNstGstVector > 0 && uNstGstVector <= X86_XCPT_LAST, ("Invalid VINTR %#x\n", uNstGstVector));
2078 TRPMAssertTrap(pVCpu, uNstGstVector, TRPM_HARDWARE_INT);
2079 Log(("EM: Asserting nested-guest virt. hardware intr: %#x\n", uNstGstVector));
2080 rc2 = VINF_EM_RESCHEDULE;
2081#ifdef VBOX_STRICT
2082 rcIrq = rc2;
2083#endif
2084 }
2085 UPDATE_RC();
2086 }
2087 }
2088 }
2089 }
2090
2091 /*
2092 * Allocate handy pages.
2093 */
2094 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
2095 {
2096 rc2 = PGMR3PhysAllocateHandyPages(pVM);
2097 UPDATE_RC();
2098 }
2099
2100 /*
2101 * Debugger Facility request.
2102 */
2103 if ( ( VM_FF_IS_SET(pVM, VM_FF_DBGF)
2104 || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_DBGF) )
2105 && !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY) )
2106 {
2107 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK, rc);
2108 rc2 = DBGFR3VMMForcedAction(pVM, pVCpu);
2109 UPDATE_RC();
2110 }
2111
2112 /*
2113 * EMT Rendezvous (must be serviced before termination).
2114 */
2115 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
2116 && VM_FF_IS_SET(pVM, VM_FF_EMT_RENDEZVOUS))
2117 {
2118 CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK, rc);
2119 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
2120 UPDATE_RC();
2121 /** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
2122 * stopped/reset before the next VM state change is made. We need a better
2123 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
2124 * && rc >= VINF_EM_SUSPEND). */
2125 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
2126 {
2127 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
2128 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
2129 return rc;
2130 }
2131 }
2132
2133 /*
2134 * State change request (cleared by vmR3SetStateLocked).
2135 */
2136 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
2137 && VM_FF_IS_SET(pVM, VM_FF_CHECK_VM_STATE))
2138 {
2139 VMSTATE enmState = VMR3GetState(pVM);
2140 switch (enmState)
2141 {
2142 case VMSTATE_FATAL_ERROR:
2143 case VMSTATE_FATAL_ERROR_LS:
2144 case VMSTATE_GURU_MEDITATION:
2145 case VMSTATE_GURU_MEDITATION_LS:
2146 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
2147 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
2148 return VINF_EM_SUSPEND;
2149
2150 case VMSTATE_DESTROYING:
2151 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
2152 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
2153 return VINF_EM_TERMINATE;
2154
2155 default:
2156 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
2157 }
2158 }
2159
2160 /*
2161 * Out of memory? Since most of our fellow high priority actions may cause us
2162 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
2163 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
2164 * than us since we can terminate without allocating more memory.
2165 */
2166 if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2167 {
2168 rc2 = PGMR3PhysAllocateHandyPages(pVM);
2169 UPDATE_RC();
2170 if (rc == VINF_EM_NO_MEMORY)
2171 return rc;
2172 }
2173
2174 /*
2175 * If the virtual sync clock is still stopped, make TM restart it.
2176 */
2177 if (VM_FF_IS_SET(pVM, VM_FF_TM_VIRTUAL_SYNC))
2178 TMR3VirtualSyncFF(pVM, pVCpu);
2179
2180#ifdef DEBUG
2181 /*
2182 * Debug, pause the VM.
2183 */
2184 if (VM_FF_IS_SET(pVM, VM_FF_DEBUG_SUSPEND))
2185 {
2186 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
2187 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
2188 return VINF_EM_SUSPEND;
2189 }
2190#endif
2191
2192 /* check that we got them all */
2193 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
2194 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_DBGF | VMCPU_FF_INTERRUPT_NESTED_GUEST | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_APIC_WRITE | VMCPU_FF_VMX_PREEMPT_TIMER | VMCPU_FF_VMX_INT_WINDOW | VMCPU_FF_VMX_NMI_WINDOW));
2195 }
2196
2197#undef UPDATE_RC
2198 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
2199 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
2200 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
2201 return rc;
2202}
2203
2204
2205/**
2206 * Check if the preset execution time cap restricts guest execution scheduling.
2207 *
2208 * @returns true if allowed, false otherwise
2209 * @param pVM The cross context VM structure.
2210 * @param pVCpu The cross context virtual CPU structure.
2211 */
2212bool emR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
2213{
2214 uint64_t u64UserTime, u64KernelTime;
2215
2216 if ( pVM->uCpuExecutionCap != 100
2217 && RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
2218 {
2219 uint64_t u64TimeNow = RTTimeMilliTS();
2220 if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
2221 {
2222 /* New time slice. */
2223 pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
2224 pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
2225 pVCpu->em.s.u64TimeSliceExec = 0;
2226 }
2227 pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
2228
2229 Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
2230 if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
2231 return false;
2232 }
2233 return true;
2234}
2235
2236
2237/**
2238 * Execute VM.
2239 *
2240 * This function is the main loop of the VM. The emulation thread
2241 * calls this function when the VM has been successfully constructed
2242 * and we're ready for executing the VM.
2243 *
2244 * Returning from this function means that the VM is turned off or
2245 * suspended (state already saved) and deconstruction is next in line.
2246 *
2247 * All interaction from other thread are done using forced actions
2248 * and signalling of the wait object.
2249 *
2250 * @returns VBox status code, informational status codes may indicate failure.
2251 * @param pVM The cross context VM structure.
2252 * @param pVCpu The cross context virtual CPU structure.
2253 */
2254VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
2255{
2256 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s)\n",
2257 pVM,
2258 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
2259 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
2260 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState) ));
2261 VM_ASSERT_EMT(pVM);
2262 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
2263 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
2264 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
2265 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
2266
2267 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
2268 if (rc == 0)
2269 {
2270 /*
2271 * Start the virtual time.
2272 */
2273 TMR3NotifyResume(pVM, pVCpu);
2274
2275 /*
2276 * The Outer Main Loop.
2277 */
2278 bool fFFDone = false;
2279
2280 /* Reschedule right away to start in the right state. */
2281 rc = VINF_SUCCESS;
2282
2283 /* If resuming after a pause or a state load, restore the previous
2284 state or else we'll start executing code. Else, just reschedule. */
2285 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
2286 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2287 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
2288 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2289 else
2290 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu);
2291 pVCpu->em.s.cIemThenRemInstructions = 0;
2292 Log(("EMR3ExecuteVM: enmState=%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
2293
2294 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2295 for (;;)
2296 {
2297 /*
2298 * Before we can schedule anything (we're here because
2299 * scheduling is required) we must service any pending
2300 * forced actions to avoid any pending action causing
2301 * immediate rescheduling upon entering an inner loop
2302 *
2303 * Do forced actions.
2304 */
2305 if ( !fFFDone
2306 && RT_SUCCESS(rc)
2307 && rc != VINF_EM_TERMINATE
2308 && rc != VINF_EM_OFF
2309 && ( VM_FF_IS_ANY_SET(pVM, VM_FF_ALL_REM_MASK)
2310 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_REM_MASK & ~VMCPU_FF_UNHALT)))
2311 {
2312 rc = emR3ForcedActions(pVM, pVCpu, rc);
2313 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
2314 }
2315 else if (fFFDone)
2316 fFFDone = false;
2317
2318 /*
2319 * Now what to do?
2320 */
2321 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
2322 EMSTATE const enmOldState = pVCpu->em.s.enmState;
2323 switch (rc)
2324 {
2325 /*
2326 * Keep doing what we're currently doing.
2327 */
2328 case VINF_SUCCESS:
2329 break;
2330
2331 /*
2332 * Reschedule - to raw-mode execution.
2333 */
2334/** @todo r=bird: consider merging VINF_EM_RESCHEDULE_RAW with VINF_EM_RESCHEDULE_HM, they serve the same purpose here at least. */
2335 case VINF_EM_RESCHEDULE_RAW:
2336 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM);
2337 if (VM_IS_RAW_MODE_ENABLED(pVM))
2338 {
2339 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", enmOldState, EMSTATE_RAW));
2340 pVCpu->em.s.enmState = EMSTATE_RAW;
2341 }
2342 else
2343 {
2344 AssertLogRelFailed();
2345 pVCpu->em.s.enmState = EMSTATE_NONE;
2346 }
2347 break;
2348
2349 /*
2350 * Reschedule - to HM or NEM.
2351 */
2352 case VINF_EM_RESCHEDULE_HM:
2353 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM);
2354 if (VM_IS_HM_ENABLED(pVM))
2355 {
2356 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HM: %d -> %d (EMSTATE_HM)\n", enmOldState, EMSTATE_HM));
2357 pVCpu->em.s.enmState = EMSTATE_HM;
2358 }
2359 else if (VM_IS_NEM_ENABLED(pVM))
2360 {
2361 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HM: %d -> %d (EMSTATE_NEM)\n", enmOldState, EMSTATE_NEM));
2362 pVCpu->em.s.enmState = EMSTATE_NEM;
2363 }
2364 else
2365 {
2366 AssertLogRelFailed();
2367 pVCpu->em.s.enmState = EMSTATE_NONE;
2368 }
2369 break;
2370
2371 /*
2372 * Reschedule - to recompiled execution.
2373 */
2374 case VINF_EM_RESCHEDULE_REM:
2375 Assert(!pVM->em.s.fIemExecutesAll || pVCpu->em.s.enmState != EMSTATE_IEM);
2376 if (!VM_IS_RAW_MODE_ENABLED(pVM))
2377 {
2378 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_IEM_THEN_REM)\n",
2379 enmOldState, EMSTATE_IEM_THEN_REM));
2380 if (pVCpu->em.s.enmState != EMSTATE_IEM_THEN_REM)
2381 {
2382 pVCpu->em.s.enmState = EMSTATE_IEM_THEN_REM;
2383 pVCpu->em.s.cIemThenRemInstructions = 0;
2384 }
2385 }
2386 else
2387 {
2388 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", enmOldState, EMSTATE_REM));
2389 pVCpu->em.s.enmState = EMSTATE_REM;
2390 }
2391 break;
2392
2393 /*
2394 * Resume.
2395 */
2396 case VINF_EM_RESUME:
2397 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", enmOldState));
2398 /* Don't reschedule in the halted or wait for SIPI case. */
2399 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2400 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
2401 {
2402 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2403 break;
2404 }
2405 /* fall through and get scheduled. */
2406 RT_FALL_THRU();
2407
2408 /*
2409 * Reschedule.
2410 */
2411 case VINF_EM_RESCHEDULE:
2412 {
2413 EMSTATE enmState = emR3Reschedule(pVM, pVCpu);
2414 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2415 if (pVCpu->em.s.enmState != enmState && enmState == EMSTATE_IEM_THEN_REM)
2416 pVCpu->em.s.cIemThenRemInstructions = 0;
2417 pVCpu->em.s.enmState = enmState;
2418 break;
2419 }
2420
2421 /*
2422 * Halted.
2423 */
2424 case VINF_EM_HALT:
2425 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", enmOldState, EMSTATE_HALTED));
2426 pVCpu->em.s.enmState = EMSTATE_HALTED;
2427 break;
2428
2429 /*
2430 * Switch to the wait for SIPI state (application processor only)
2431 */
2432 case VINF_EM_WAIT_SIPI:
2433 Assert(pVCpu->idCpu != 0);
2434 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", enmOldState, EMSTATE_WAIT_SIPI));
2435 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2436 break;
2437
2438
2439 /*
2440 * Suspend.
2441 */
2442 case VINF_EM_SUSPEND:
2443 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2444 Assert(enmOldState != EMSTATE_SUSPENDED);
2445 pVCpu->em.s.enmPrevState = enmOldState;
2446 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2447 break;
2448
2449 /*
2450 * Reset.
2451 * We might end up doing a double reset for now, we'll have to clean up the mess later.
2452 */
2453 case VINF_EM_RESET:
2454 {
2455 if (pVCpu->idCpu == 0)
2456 {
2457 EMSTATE enmState = emR3Reschedule(pVM, pVCpu);
2458 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2459 if (pVCpu->em.s.enmState != enmState && enmState == EMSTATE_IEM_THEN_REM)
2460 pVCpu->em.s.cIemThenRemInstructions = 0;
2461 pVCpu->em.s.enmState = enmState;
2462 }
2463 else
2464 {
2465 /* All other VCPUs go into the wait for SIPI state. */
2466 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2467 }
2468 break;
2469 }
2470
2471 /*
2472 * Power Off.
2473 */
2474 case VINF_EM_OFF:
2475 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2476 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2477 TMR3NotifySuspend(pVM, pVCpu);
2478 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2479 return rc;
2480
2481 /*
2482 * Terminate the VM.
2483 */
2484 case VINF_EM_TERMINATE:
2485 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2486 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2487 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
2488 TMR3NotifySuspend(pVM, pVCpu);
2489 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2490 return rc;
2491
2492
2493 /*
2494 * Out of memory, suspend the VM and stuff.
2495 */
2496 case VINF_EM_NO_MEMORY:
2497 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2498 Assert(enmOldState != EMSTATE_SUSPENDED);
2499 pVCpu->em.s.enmPrevState = enmOldState;
2500 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2501 TMR3NotifySuspend(pVM, pVCpu);
2502 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2503
2504 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
2505 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
2506 if (rc != VINF_EM_SUSPEND)
2507 {
2508 if (RT_SUCCESS_NP(rc))
2509 {
2510 AssertLogRelMsgFailed(("%Rrc\n", rc));
2511 rc = VERR_EM_INTERNAL_ERROR;
2512 }
2513 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2514 }
2515 return rc;
2516
2517 /*
2518 * Guest debug events.
2519 */
2520 case VINF_EM_DBG_STEPPED:
2521 case VINF_EM_DBG_STOP:
2522 case VINF_EM_DBG_EVENT:
2523 case VINF_EM_DBG_BREAKPOINT:
2524 case VINF_EM_DBG_STEP:
2525 if (enmOldState == EMSTATE_RAW)
2526 {
2527 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_RAW));
2528 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
2529 }
2530 else if (enmOldState == EMSTATE_HM)
2531 {
2532 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_HM));
2533 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HM;
2534 }
2535 else if (enmOldState == EMSTATE_NEM)
2536 {
2537 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_NEM));
2538 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_NEM;
2539 }
2540 else if (enmOldState == EMSTATE_REM)
2541 {
2542 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_REM));
2543 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
2544 }
2545 else
2546 {
2547 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_IEM));
2548 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_IEM;
2549 }
2550 break;
2551
2552 /*
2553 * Hypervisor debug events.
2554 */
2555 case VINF_EM_DBG_HYPER_STEPPED:
2556 case VINF_EM_DBG_HYPER_BREAKPOINT:
2557 case VINF_EM_DBG_HYPER_ASSERTION:
2558 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_HYPER));
2559 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
2560 break;
2561
2562 /*
2563 * Triple fault.
2564 */
2565 case VINF_EM_TRIPLE_FAULT:
2566 if (!pVM->em.s.fGuruOnTripleFault)
2567 {
2568 Log(("EMR3ExecuteVM: VINF_EM_TRIPLE_FAULT: CPU reset...\n"));
2569 rc = VBOXSTRICTRC_TODO(VMR3ResetTripleFault(pVM));
2570 Log2(("EMR3ExecuteVM: VINF_EM_TRIPLE_FAULT: %d -> %d (rc=%Rrc)\n", enmOldState, pVCpu->em.s.enmState, rc));
2571 continue;
2572 }
2573 /* Else fall through and trigger a guru. */
2574 RT_FALL_THRU();
2575
2576 case VERR_VMM_RING0_ASSERTION:
2577 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2578 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2579 break;
2580
2581 /*
2582 * Any error code showing up here other than the ones we
2583 * know and process above are considered to be FATAL.
2584 *
2585 * Unknown warnings and informational status codes are also
2586 * included in this.
2587 */
2588 default:
2589 if (RT_SUCCESS_NP(rc))
2590 {
2591 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
2592 rc = VERR_EM_INTERNAL_ERROR;
2593 }
2594 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2595 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2596 break;
2597 }
2598
2599 /*
2600 * Act on state transition.
2601 */
2602 EMSTATE const enmNewState = pVCpu->em.s.enmState;
2603 if (enmOldState != enmNewState)
2604 {
2605 VBOXVMM_EM_STATE_CHANGED(pVCpu, enmOldState, enmNewState, rc);
2606
2607 /* Clear MWait flags and the unhalt FF. */
2608 if ( enmOldState == EMSTATE_HALTED
2609 && ( (pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_ACTIVE)
2610 || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_UNHALT))
2611 && ( enmNewState == EMSTATE_RAW
2612 || enmNewState == EMSTATE_HM
2613 || enmNewState == EMSTATE_NEM
2614 || enmNewState == EMSTATE_REM
2615 || enmNewState == EMSTATE_IEM_THEN_REM
2616 || enmNewState == EMSTATE_DEBUG_GUEST_RAW
2617 || enmNewState == EMSTATE_DEBUG_GUEST_HM
2618 || enmNewState == EMSTATE_DEBUG_GUEST_NEM
2619 || enmNewState == EMSTATE_DEBUG_GUEST_IEM
2620 || enmNewState == EMSTATE_DEBUG_GUEST_REM) )
2621 {
2622 if (pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_ACTIVE)
2623 {
2624 LogFlow(("EMR3ExecuteVM: Clearing MWAIT\n"));
2625 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
2626 }
2627 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_UNHALT))
2628 {
2629 LogFlow(("EMR3ExecuteVM: Clearing UNHALT\n"));
2630 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_UNHALT);
2631 }
2632 }
2633 }
2634 else
2635 VBOXVMM_EM_STATE_UNCHANGED(pVCpu, enmNewState, rc);
2636
2637 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
2638 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2639
2640 /*
2641 * Act on the new state.
2642 */
2643 switch (enmNewState)
2644 {
2645 /*
2646 * Execute raw.
2647 */
2648 case EMSTATE_RAW:
2649 AssertLogRelMsgFailed(("%Rrc\n", rc));
2650 rc = VERR_EM_INTERNAL_ERROR;
2651 break;
2652
2653 /*
2654 * Execute hardware accelerated raw.
2655 */
2656 case EMSTATE_HM:
2657 rc = emR3HmExecute(pVM, pVCpu, &fFFDone);
2658 break;
2659
2660 /*
2661 * Execute hardware accelerated raw.
2662 */
2663 case EMSTATE_NEM:
2664 rc = VBOXSTRICTRC_TODO(emR3NemExecute(pVM, pVCpu, &fFFDone));
2665 break;
2666
2667 /*
2668 * Execute recompiled.
2669 */
2670 case EMSTATE_REM:
2671 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2672 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2673 break;
2674
2675 /*
2676 * Execute in the interpreter.
2677 */
2678 case EMSTATE_IEM:
2679 {
2680 uint32_t cInstructions = 0;
2681#if 0 /* For testing purposes. */
2682 STAM_PROFILE_START(&pVCpu->em.s.StatHmExec, x1);
2683 rc = VBOXSTRICTRC_TODO(EMR3HmSingleInstruction(pVM, pVCpu, EM_ONE_INS_FLAGS_RIP_CHANGE));
2684 STAM_PROFILE_STOP(&pVCpu->em.s.StatHmExec, x1);
2685 if (rc == VINF_EM_DBG_STEPPED || rc == VINF_EM_RESCHEDULE_HM || rc == VINF_EM_RESCHEDULE_REM || rc == VINF_EM_RESCHEDULE_RAW)
2686 rc = VINF_SUCCESS;
2687 else if (rc == VERR_EM_CANNOT_EXEC_GUEST)
2688#endif
2689 rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu, 4096 /*cMaxInstructions*/, 2047 /*cPollRate*/, &cInstructions));
2690 if (pVM->em.s.fIemExecutesAll)
2691 {
2692 Assert(rc != VINF_EM_RESCHEDULE_REM);
2693 Assert(rc != VINF_EM_RESCHEDULE_RAW);
2694 Assert(rc != VINF_EM_RESCHEDULE_HM);
2695#ifdef VBOX_HIGH_RES_TIMERS_HACK
2696 if (cInstructions < 2048)
2697 TMTimerPollVoid(pVM, pVCpu);
2698#endif
2699 }
2700 fFFDone = false;
2701 break;
2702 }
2703
2704 /*
2705 * Execute in IEM, hoping we can quickly switch aback to HM
2706 * or RAW execution. If our hopes fail, we go to REM.
2707 */
2708 case EMSTATE_IEM_THEN_REM:
2709 {
2710 STAM_PROFILE_START(&pVCpu->em.s.StatIEMThenREM, pIemThenRem);
2711 rc = VBOXSTRICTRC_TODO(emR3ExecuteIemThenRem(pVM, pVCpu, &fFFDone));
2712 STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMThenREM, pIemThenRem);
2713 break;
2714 }
2715
2716 /*
2717 * Application processor execution halted until SIPI.
2718 */
2719 case EMSTATE_WAIT_SIPI:
2720 /* no break */
2721 /*
2722 * hlt - execution halted until interrupt.
2723 */
2724 case EMSTATE_HALTED:
2725 {
2726 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2727 /* If HM (or someone else) store a pending interrupt in
2728 TRPM, it must be dispatched ASAP without any halting.
2729 Anything pending in TRPM has been accepted and the CPU
2730 should already be the right state to receive it. */
2731 if (TRPMHasTrap(pVCpu))
2732 rc = VINF_EM_RESCHEDULE;
2733 /* MWAIT has a special extension where it's woken up when
2734 an interrupt is pending even when IF=0. */
2735 else if ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2736 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2737 {
2738 rc = VMR3WaitHalted(pVM, pVCpu, false /*fIgnoreInterrupts*/);
2739 if (rc == VINF_SUCCESS)
2740 {
2741 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2742 APICUpdatePendingInterrupts(pVCpu);
2743
2744 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
2745 | VMCPU_FF_INTERRUPT_NESTED_GUEST
2746 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_UNHALT))
2747 {
2748 Log(("EMR3ExecuteVM: Triggering reschedule on pending IRQ after MWAIT\n"));
2749 rc = VINF_EM_RESCHEDULE;
2750 }
2751 }
2752 }
2753 else
2754 {
2755 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2756 /* We're only interested in NMI/SMIs here which have their own FFs, so we don't need to
2757 check VMCPU_FF_UPDATE_APIC here. */
2758 if ( rc == VINF_SUCCESS
2759 && VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_UNHALT))
2760 {
2761 Log(("EMR3ExecuteVM: Triggering reschedule on pending NMI/SMI/UNHALT after HLT\n"));
2762 rc = VINF_EM_RESCHEDULE;
2763 }
2764 }
2765
2766 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2767 break;
2768 }
2769
2770 /*
2771 * Suspended - return to VM.cpp.
2772 */
2773 case EMSTATE_SUSPENDED:
2774 TMR3NotifySuspend(pVM, pVCpu);
2775 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2776 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2777 return VINF_EM_SUSPEND;
2778
2779 /*
2780 * Debugging in the guest.
2781 */
2782 case EMSTATE_DEBUG_GUEST_RAW:
2783 case EMSTATE_DEBUG_GUEST_HM:
2784 case EMSTATE_DEBUG_GUEST_NEM:
2785 case EMSTATE_DEBUG_GUEST_IEM:
2786 case EMSTATE_DEBUG_GUEST_REM:
2787 TMR3NotifySuspend(pVM, pVCpu);
2788 rc = VBOXSTRICTRC_TODO(emR3Debug(pVM, pVCpu, rc));
2789 TMR3NotifyResume(pVM, pVCpu);
2790 Log2(("EMR3ExecuteVM: emR3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2791 break;
2792
2793 /*
2794 * Debugging in the hypervisor.
2795 */
2796 case EMSTATE_DEBUG_HYPER:
2797 {
2798 TMR3NotifySuspend(pVM, pVCpu);
2799 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2800
2801 rc = VBOXSTRICTRC_TODO(emR3Debug(pVM, pVCpu, rc));
2802 Log2(("EMR3ExecuteVM: emR3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2803 if (rc != VINF_SUCCESS)
2804 {
2805 if (rc == VINF_EM_OFF || rc == VINF_EM_TERMINATE)
2806 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2807 else
2808 {
2809 /* switch to guru meditation mode */
2810 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2811 VMR3SetGuruMeditation(pVM); /* This notifies the other EMTs. */
2812 VMMR3FatalDump(pVM, pVCpu, rc);
2813 }
2814 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2815 return rc;
2816 }
2817
2818 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2819 TMR3NotifyResume(pVM, pVCpu);
2820 break;
2821 }
2822
2823 /*
2824 * Guru meditation takes place in the debugger.
2825 */
2826 case EMSTATE_GURU_MEDITATION:
2827 {
2828 TMR3NotifySuspend(pVM, pVCpu);
2829 VMR3SetGuruMeditation(pVM); /* This notifies the other EMTs. */
2830 VMMR3FatalDump(pVM, pVCpu, rc);
2831 emR3Debug(pVM, pVCpu, rc);
2832 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2833 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2834 return rc;
2835 }
2836
2837 /*
2838 * The states we don't expect here.
2839 */
2840 case EMSTATE_NONE:
2841 case EMSTATE_TERMINATING:
2842 default:
2843 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2844 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2845 TMR3NotifySuspend(pVM, pVCpu);
2846 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2847 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2848 return VERR_EM_INTERNAL_ERROR;
2849 }
2850 } /* The Outer Main Loop */
2851 }
2852 else
2853 {
2854 /*
2855 * Fatal error.
2856 */
2857 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2858 TMR3NotifySuspend(pVM, pVCpu);
2859 VMR3SetGuruMeditation(pVM); /* This notifies the other EMTs. */
2860 VMMR3FatalDump(pVM, pVCpu, rc);
2861 emR3Debug(pVM, pVCpu, rc);
2862 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2863 /** @todo change the VM state! */
2864 return rc;
2865 }
2866
2867 /* not reached */
2868}
2869
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