VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 74795

Last change on this file since 74795 was 71805, checked in by vboxsync, 6 years ago

VMM/CPUM: Nit - stat description typo.
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1/* $Id: CPUMR3Db.cpp 71805 2018-04-10 09:37:55Z vboxsync $ */
2/** @file
3 * CPUM - CPU database part.
4 */
5
6/*
7 * Copyright (C) 2013-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include "CPUMInternal.h"
25#include <VBox/vmm/vm.h>
26#include <VBox/vmm/mm.h>
27
28#include <VBox/err.h>
29#include <iprt/asm-amd64-x86.h>
30#include <iprt/mem.h>
31#include <iprt/string.h>
32
33
34/*********************************************************************************************************************************
35* Structures and Typedefs *
36*********************************************************************************************************************************/
37typedef struct CPUMDBENTRY
38{
39 /** The CPU name. */
40 const char *pszName;
41 /** The full CPU name. */
42 const char *pszFullName;
43 /** The CPU vendor (CPUMCPUVENDOR). */
44 uint8_t enmVendor;
45 /** The CPU family. */
46 uint8_t uFamily;
47 /** The CPU model. */
48 uint8_t uModel;
49 /** The CPU stepping. */
50 uint8_t uStepping;
51 /** The microarchitecture. */
52 CPUMMICROARCH enmMicroarch;
53 /** Scalable bus frequency used for reporting other frequencies. */
54 uint64_t uScalableBusFreq;
55 /** Flags - CPUDB_F_XXX. */
56 uint32_t fFlags;
57 /** The maximum physical address with of the CPU. This should correspond to
58 * the value in CPUID leaf 0x80000008 when present. */
59 uint8_t cMaxPhysAddrWidth;
60 /** The MXCSR mask. */
61 uint32_t fMxCsrMask;
62 /** Pointer to an array of CPUID leaves. */
63 PCCPUMCPUIDLEAF paCpuIdLeaves;
64 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
65 uint32_t cCpuIdLeaves;
66 /** The method used to deal with unknown CPUID leaves. */
67 CPUMUNKNOWNCPUID enmUnknownCpuId;
68 /** The default unknown CPUID value. */
69 CPUMCPUID DefUnknownCpuId;
70
71 /** MSR mask. Several microarchitectures ignore the higher bits of ECX in
72 * the RDMSR and WRMSR instructions. */
73 uint32_t fMsrMask;
74
75 /** The number of ranges in the table pointed to b paMsrRanges. */
76 uint32_t cMsrRanges;
77 /** MSR ranges for this CPU. */
78 PCCPUMMSRRANGE paMsrRanges;
79} CPUMDBENTRY;
80
81
82/*********************************************************************************************************************************
83* Defined Constants And Macros *
84*********************************************************************************************************************************/
85/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
86 * @{ */
87/** Should execute all in IEM.
88 * @todo Implement this - currently done in Main... */
89#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
90/** @} */
91
92
93/** @def NULL_ALONE
94 * For eliminating an unnecessary data dependency in standalone builds (for
95 * VBoxSVC). */
96/** @def ZERO_ALONE
97 * For eliminating an unnecessary data size dependency in standalone builds (for
98 * VBoxSVC). */
99#ifndef CPUM_DB_STANDALONE
100# define NULL_ALONE(a_aTable) a_aTable
101# define ZERO_ALONE(a_cTable) a_cTable
102#else
103# define NULL_ALONE(a_aTable) NULL
104# define ZERO_ALONE(a_cTable) 0
105#endif
106
107
108/** @name Short macros for the MSR range entries.
109 *
110 * These are rather cryptic, but this is to reduce the attack on the right
111 * margin.
112 *
113 * @{ */
114/** Alias one MSR onto another (a_uTarget). */
115#define MAL(a_uMsr, a_szName, a_uTarget) \
116 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
117/** Functions handles everything. */
118#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
119 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
120/** Functions handles everything, with GP mask. */
121#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
122 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
123/** Function handlers, read-only. */
124#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
125 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
126/** Function handlers, ignore all writes. */
127#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
128 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
129/** Function handlers, with value. */
130#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
131 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
132/** Function handlers, with write ignore mask. */
133#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
134 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
135/** Function handlers, extended version. */
136#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
137 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
138/** Function handlers, with CPUMCPU storage variable. */
139#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
140 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
141 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
142/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
143#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
144 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
145 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
146/** Read-only fixed value. */
147#define MVO(a_uMsr, a_szName, a_uValue) \
148 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
149/** Read-only fixed value, ignores all writes. */
150#define MVI(a_uMsr, a_szName, a_uValue) \
151 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
152/** Read fixed value, ignore writes outside GP mask. */
153#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
154 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
155/** Read fixed value, extended version with both GP and ignore masks. */
156#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
157 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
158/** The short form, no CPUM backing. */
159#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163/** Range: Functions handles everything. */
164#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
165 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
166/** Range: Read fixed value, read-only. */
167#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
168 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
169/** Range: Read fixed value, ignore writes. */
170#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
171 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
172/** Range: The short form, no CPUM backing. */
173#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
174 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
175 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
176
177/** Internal form used by the macros. */
178#ifdef VBOX_WITH_STATISTICS
179# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
180 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
181 { 0 }, { 0 }, { 0 }, { 0 } }
182#else
183# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
184 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
185#endif
186/** @} */
187
188#ifndef CPUM_DB_STANDALONE
189
190#include "cpus/Intel_Core_i7_6700K.h"
191#include "cpus/Intel_Core_i7_5600U.h"
192#include "cpus/Intel_Core_i7_3960X.h"
193#include "cpus/Intel_Core_i5_3570.h"
194#include "cpus/Intel_Core_i7_2635QM.h"
195#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
196#include "cpus/Intel_Core2_X6800_2_93GHz.h"
197#include "cpus/Intel_Core2_T7600_2_33GHz.h"
198#include "cpus/Intel_Core_Duo_T2600_2_16GHz.h"
199#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
200#include "cpus/Intel_Pentium_4_3_00GHz.h"
201#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
202#include "cpus/Intel_Atom_330_1_60GHz.h"
203#include "cpus/Intel_80486.h"
204#include "cpus/Intel_80386.h"
205#include "cpus/Intel_80286.h"
206#include "cpus/Intel_80186.h"
207#include "cpus/Intel_8086.h"
208
209#include "cpus/AMD_FX_8150_Eight_Core.h"
210#include "cpus/AMD_Phenom_II_X6_1100T.h"
211#include "cpus/Quad_Core_AMD_Opteron_2384.h"
212#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
213#include "cpus/AMD_Athlon_64_3200.h"
214
215#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
216
217
218
219/**
220 * The database entries.
221 *
222 * 1. The first entry is special. It is the fallback for unknown
223 * processors. Thus, it better be pretty representative.
224 *
225 * 2. The first entry for a CPU vendor is likewise important as it is
226 * the default entry for that vendor.
227 *
228 * Generally we put the most recent CPUs first, since these tend to have the
229 * most complicated and backwards compatible list of MSRs.
230 */
231static CPUMDBENTRY const * const g_apCpumDbEntries[] =
232{
233#ifdef VBOX_CPUDB_Intel_Core_i7_6700K
234 &g_Entry_Intel_Core_i7_6700K,
235#endif
236#ifdef VBOX_CPUDB_Intel_Core_i7_5600U
237 &g_Entry_Intel_Core_i7_5600U,
238#endif
239#ifdef VBOX_CPUDB_Intel_Core_i5_3570
240 &g_Entry_Intel_Core_i5_3570,
241#endif
242#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
243 &g_Entry_Intel_Core_i7_3960X,
244#endif
245#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM
246 &g_Entry_Intel_Core_i7_2635QM,
247#endif
248#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz
249 &g_Entry_Intel_Pentium_N3530_2_16GHz,
250#endif
251#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz
252 &g_Entry_Intel_Atom_330_1_60GHz,
253#endif
254#ifdef VBOX_CPUDB_Intel_Pentium_M_processor_2_00GHz
255 &g_Entry_Intel_Pentium_M_processor_2_00GHz,
256#endif
257#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
258 &g_Entry_Intel_Xeon_X5482_3_20GHz,
259#endif
260#ifdef VBOX_CPUDB_Intel_Core2_X6800_2_93GHz
261 &g_Entry_Intel_Core2_X6800_2_93GHz,
262#endif
263#ifdef VBOX_CPUDB_Intel_Core2_T7600_2_33GHz
264 &g_Entry_Intel_Core2_T7600_2_33GHz,
265#endif
266#ifdef VBOX_CPUDB_Intel_Core_Duo_T2600_2_16GHz
267 &g_Entry_Intel_Core_Duo_T2600_2_16GHz,
268#endif
269#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
270 &g_Entry_Intel_Pentium_4_3_00GHz,
271#endif
272#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
273 &g_Entry_Intel_Pentium_4_3_00GHz,
274#endif
275/** @todo pentium, pentium mmx, pentium pro, pentium II, pentium III */
276#ifdef VBOX_CPUDB_Intel_80486
277 &g_Entry_Intel_80486,
278#endif
279#ifdef VBOX_CPUDB_Intel_80386
280 &g_Entry_Intel_80386,
281#endif
282#ifdef VBOX_CPUDB_Intel_80286
283 &g_Entry_Intel_80286,
284#endif
285#ifdef VBOX_CPUDB_Intel_80186
286 &g_Entry_Intel_80186,
287#endif
288#ifdef VBOX_CPUDB_Intel_8086
289 &g_Entry_Intel_8086,
290#endif
291
292#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
293 &g_Entry_AMD_FX_8150_Eight_Core,
294#endif
295#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
296 &g_Entry_AMD_Phenom_II_X6_1100T,
297#endif
298#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
299 &g_Entry_Quad_Core_AMD_Opteron_2384,
300#endif
301#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
302 &g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
303#endif
304#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
305 &g_Entry_AMD_Athlon_64_3200,
306#endif
307
308#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
309 &g_Entry_VIA_QuadCore_L4700_1_2_GHz,
310#endif
311
312#ifdef VBOX_CPUDB_NEC_V20
313 &g_Entry_NEC_V20,
314#endif
315};
316
317
318
319/**
320 * Binary search used by cpumR3MsrRangesInsert and has some special properties
321 * wrt to mismatches.
322 *
323 * @returns Insert location.
324 * @param paMsrRanges The MSR ranges to search.
325 * @param cMsrRanges The number of MSR ranges.
326 * @param uMsr What to search for.
327 */
328static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
329{
330 if (!cMsrRanges)
331 return 0;
332
333 uint32_t iStart = 0;
334 uint32_t iLast = cMsrRanges - 1;
335 for (;;)
336 {
337 uint32_t i = iStart + (iLast - iStart + 1) / 2;
338 if ( uMsr >= paMsrRanges[i].uFirst
339 && uMsr <= paMsrRanges[i].uLast)
340 return i;
341 if (uMsr < paMsrRanges[i].uFirst)
342 {
343 if (i <= iStart)
344 return i;
345 iLast = i - 1;
346 }
347 else
348 {
349 if (i >= iLast)
350 {
351 if (i < cMsrRanges)
352 i++;
353 return i;
354 }
355 iStart = i + 1;
356 }
357 }
358}
359
360
361/**
362 * Ensures that there is space for at least @a cNewRanges in the table,
363 * reallocating the table if necessary.
364 *
365 * @returns Pointer to the MSR ranges on success, NULL on failure. On failure
366 * @a *ppaMsrRanges is freed and set to NULL.
367 * @param pVM The cross context VM structure. If NULL,
368 * use the process heap, otherwise the VM's hyper heap.
369 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
370 * @param cMsrRanges The current number of ranges.
371 * @param cNewRanges The number of ranges to be added.
372 */
373static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
374{
375 uint32_t cMsrRangesAllocated;
376 if (!pVM)
377 cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
378 else
379 {
380 /*
381 * We're using the hyper heap now, but when the range array was copied over to it from
382 * the host-context heap, we only copy the exact size and not the ensured size.
383 * See @bugref{7270}.
384 */
385 cMsrRangesAllocated = cMsrRanges;
386 }
387 if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
388 {
389 void *pvNew;
390 uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
391 if (pVM)
392 {
393 Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
394 Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
395
396 size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
397 size_t cbNew = cNew * sizeof(**ppaMsrRanges);
398 int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
399 if (RT_FAILURE(rc))
400 {
401 *ppaMsrRanges = NULL;
402 pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
403 pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
404 LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
405 return NULL;
406 }
407 *ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
408 }
409 else
410 {
411 pvNew = RTMemRealloc(*ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
412 if (!pvNew)
413 {
414 RTMemFree(*ppaMsrRanges);
415 *ppaMsrRanges = NULL;
416 return NULL;
417 }
418 }
419 *ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
420 }
421
422 if (pVM)
423 {
424 /* Update R0 and RC pointers. */
425 Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
426 pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
427 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
428 }
429
430 return *ppaMsrRanges;
431}
432
433
434/**
435 * Inserts a new MSR range in into an sorted MSR range array.
436 *
437 * If the new MSR range overlaps existing ranges, the existing ones will be
438 * adjusted/removed to fit in the new one.
439 *
440 * @returns VBox status code.
441 * @retval VINF_SUCCESS
442 * @retval VERR_NO_MEMORY
443 *
444 * @param pVM The cross context VM structure. If NULL,
445 * use the process heap, otherwise the VM's hyper heap.
446 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
447 * Must be NULL if using the hyper heap.
448 * @param pcMsrRanges The variable holding number of ranges. Must be NULL
449 * if using the hyper heap.
450 * @param pNewRange The new range.
451 */
452int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange)
453{
454 Assert(pNewRange->uLast >= pNewRange->uFirst);
455 Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
456 Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
457
458 /*
459 * Validate and use the VM's MSR ranges array if we are using the hyper heap.
460 */
461 if (pVM)
462 {
463 AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
464 AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
465
466 ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
467 pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
468 }
469 else
470 {
471 AssertReturn(ppaMsrRanges, VERR_INVALID_POINTER);
472 AssertReturn(pcMsrRanges, VERR_INVALID_POINTER);
473 }
474
475 uint32_t cMsrRanges = *pcMsrRanges;
476 PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
477
478 /*
479 * Optimize the linear insertion case where we add new entries at the end.
480 */
481 if ( cMsrRanges > 0
482 && paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
483 {
484 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
485 if (!paMsrRanges)
486 return VERR_NO_MEMORY;
487 paMsrRanges[cMsrRanges] = *pNewRange;
488 *pcMsrRanges += 1;
489 }
490 else
491 {
492 uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
493 Assert(i == cMsrRanges || pNewRange->uFirst <= paMsrRanges[i].uLast);
494 Assert(i == 0 || pNewRange->uFirst > paMsrRanges[i - 1].uLast);
495
496 /*
497 * Adding an entirely new entry?
498 */
499 if ( i >= cMsrRanges
500 || pNewRange->uLast < paMsrRanges[i].uFirst)
501 {
502 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
503 if (!paMsrRanges)
504 return VERR_NO_MEMORY;
505 if (i < cMsrRanges)
506 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
507 paMsrRanges[i] = *pNewRange;
508 *pcMsrRanges += 1;
509 }
510 /*
511 * Replace existing entry?
512 */
513 else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
514 && pNewRange->uLast == paMsrRanges[i].uLast)
515 paMsrRanges[i] = *pNewRange;
516 /*
517 * Splitting an existing entry?
518 */
519 else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
520 && pNewRange->uLast < paMsrRanges[i].uLast)
521 {
522 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
523 if (!paMsrRanges)
524 return VERR_NO_MEMORY;
525 if (i < cMsrRanges)
526 memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
527 paMsrRanges[i + 1] = *pNewRange;
528 paMsrRanges[i + 2] = paMsrRanges[i];
529 paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
530 paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
531 *pcMsrRanges += 2;
532 }
533 /*
534 * Complicated scenarios that can affect more than one range.
535 *
536 * The current code does not optimize memmove calls when replacing
537 * one or more existing ranges, because it's tedious to deal with and
538 * not expected to be a frequent usage scenario.
539 */
540 else
541 {
542 /* Adjust start of first match? */
543 if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
544 && pNewRange->uLast < paMsrRanges[i].uLast)
545 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
546 else
547 {
548 /* Adjust end of first match? */
549 if (pNewRange->uFirst > paMsrRanges[i].uFirst)
550 {
551 Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
552 paMsrRanges[i].uLast = pNewRange->uFirst - 1;
553 i++;
554 }
555 /* Replace the whole first match (lazy bird). */
556 else
557 {
558 if (i + 1 < cMsrRanges)
559 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
560 cMsrRanges = *pcMsrRanges -= 1;
561 }
562
563 /* Do the new range affect more ranges? */
564 while ( i < cMsrRanges
565 && pNewRange->uLast >= paMsrRanges[i].uFirst)
566 {
567 if (pNewRange->uLast < paMsrRanges[i].uLast)
568 {
569 /* Adjust the start of it, then we're done. */
570 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
571 break;
572 }
573
574 /* Remove it entirely. */
575 if (i + 1 < cMsrRanges)
576 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
577 cMsrRanges = *pcMsrRanges -= 1;
578 }
579 }
580
581 /* Now, perform a normal insertion. */
582 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
583 if (!paMsrRanges)
584 return VERR_NO_MEMORY;
585 if (i < cMsrRanges)
586 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
587 paMsrRanges[i] = *pNewRange;
588 *pcMsrRanges += 1;
589 }
590 }
591
592 return VINF_SUCCESS;
593}
594
595
596/**
597 * Worker for cpumR3MsrApplyFudge that applies one table.
598 *
599 * @returns VBox status code.
600 * @param pVM The cross context VM structure.
601 * @param paRanges Array of MSRs to fudge.
602 * @param cRanges Number of MSRs in the array.
603 */
604static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
605{
606 for (uint32_t i = 0; i < cRanges; i++)
607 if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
608 {
609 LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
610 int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
611 &paRanges[i]);
612 if (RT_FAILURE(rc))
613 return rc;
614 }
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Fudges the MSRs that guest are known to access in some odd cases.
621 *
622 * A typical example is a VM that has been moved between different hosts where
623 * for instance the cpu vendor differs.
624 *
625 * Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
626 * Atom Silvermont), where features reported thru CPUID aren't present in the
627 * MSRs (e.g. AMD64_TSC_AUX).
628 *
629 *
630 * @returns VBox status code.
631 * @param pVM The cross context VM structure.
632 */
633int cpumR3MsrApplyFudge(PVM pVM)
634{
635 /*
636 * Basic.
637 */
638 static CPUMMSRRANGE const s_aFudgeMsrs[] =
639 {
640 MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
641 MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
642 MVO(0x00000017, "IA32_PLATFORM_ID", 0),
643 MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
644 MVI(0x0000008b, "BIOS_SIGN", 0),
645 MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
646 MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
647 MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
648 MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
649 MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
650 MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
651 MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
652 MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
653 MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
654 MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
655 MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
656 MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
657 };
658 int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
659 AssertLogRelRCReturn(rc, rc);
660
661 /*
662 * XP might mistake opterons and other newer CPUs for P4s.
663 */
664 if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
665 {
666 static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
667 {
668 MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
669 };
670 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
671 AssertLogRelRCReturn(rc, rc);
672 }
673
674 if (pVM->cpum.s.GuestFeatures.fRdTscP)
675 {
676 static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
677 {
678 MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
679 };
680 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
681 AssertLogRelRCReturn(rc, rc);
682 }
683
684 return rc;
685}
686
687
688/**
689 * Do we consider @a enmConsider a better match for @a enmTarget than
690 * @a enmFound?
691 *
692 * Only called when @a enmConsider isn't exactly what we're looking for.
693 *
694 * @returns true/false.
695 * @param enmConsider The new microarch to consider.
696 * @param enmTarget The target microarch.
697 * @param enmFound The best microarch match we've found thus far.
698 */
699DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
700{
701 Assert(enmConsider != enmTarget);
702
703 /*
704 * If we've got an march match, don't bother with enmConsider.
705 */
706 if (enmFound == enmTarget)
707 return false;
708
709 /*
710 * Found is below: Pick 'consider' if it's closer to the target or above it.
711 */
712 if (enmFound < enmTarget)
713 return enmConsider > enmFound;
714
715 /*
716 * Found is above: Pick 'consider' if it's also above (paranoia: or equal)
717 * and but closer to the target.
718 */
719 return enmConsider >= enmTarget && enmConsider < enmFound;
720}
721
722
723/**
724 * Do we consider @a enmConsider a better match for @a enmTarget than
725 * @a enmFound?
726 *
727 * Only called for intel family 06h CPUs.
728 *
729 * @returns true/false.
730 * @param enmConsider The new microarch to consider.
731 * @param enmTarget The target microarch.
732 * @param enmFound The best microarch match we've found thus far.
733 */
734static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
735{
736 /* Check intel family 06h claims. */
737 AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
738 false);
739 AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
740 false);
741
742 /* Put matches out of the way. */
743 if (enmConsider == enmTarget)
744 return true;
745 if (enmFound == enmTarget)
746 return false;
747
748 /* If found isn't a family 06h march, whatever we're considering must be a better choice. */
749 if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
750 || enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
751 return true;
752
753 /*
754 * The family 06h stuff is split into three categories:
755 * - Common P6 heritage
756 * - Core
757 * - Atom
758 *
759 * Determin which of the three arguments are Atom marchs, because that's
760 * all we need to make the right choice.
761 */
762 bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
763 bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
764 bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
765
766 /*
767 * Want atom:
768 */
769 if (fTargetAtom)
770 {
771 /* Pick the atom if we've got one of each.*/
772 if (fConsiderAtom != fFoundAtom)
773 return fConsiderAtom;
774 /* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
775 Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
776 if (!fConsiderAtom)
777 {
778 if (enmConsider > enmFound)
779 return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
780 return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
781 }
782 /* else: same category, default comparison rules. */
783 Assert(fConsiderAtom && fFoundAtom);
784 }
785 /*
786 * Want non-atom:
787 */
788 /* Pick the non-atom if we've got one of each. */
789 else if (fConsiderAtom != fFoundAtom)
790 return fFoundAtom;
791 /* If we've only got atoms under consideration, pick the older one just to pick something. */
792 else if (fConsiderAtom)
793 return enmConsider < enmFound;
794 else
795 Assert(!fConsiderAtom && !fFoundAtom);
796
797 /*
798 * Same basic category. Do same compare as caller.
799 */
800 return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
801}
802
803
804int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
805{
806 CPUMDBENTRY const *pEntry = NULL;
807 int rc;
808
809 if (!strcmp(pszName, "host"))
810 {
811 /*
812 * Create a CPU database entry for the host CPU. This means getting
813 * the CPUID bits from the real CPU and grabbing the closest matching
814 * database entry for MSRs.
815 */
816 rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
817 if (RT_FAILURE(rc))
818 return rc;
819 rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
820 if (RT_FAILURE(rc))
821 return rc;
822 pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
823
824 /* Lookup database entry for MSRs. */
825 CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
826 pInfo->paCpuIdLeavesR3[0].uEbx,
827 pInfo->paCpuIdLeavesR3[0].uEcx,
828 pInfo->paCpuIdLeavesR3[0].uEdx);
829 uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
830 uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
831 uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
832 uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
833 CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
834
835 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
836 {
837 CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
838 if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
839 {
840 /* Match against Family, Microarch, model and stepping. Except
841 for family, always match the closer with preference given to
842 the later/older ones. */
843 if (pCur->uFamily == uFamily)
844 {
845 if (pCur->enmMicroarch == enmMicroarch)
846 {
847 if (pCur->uModel == uModel)
848 {
849 if (pCur->uStepping == uStepping)
850 {
851 /* Perfect match. */
852 pEntry = pCur;
853 break;
854 }
855
856 if ( !pEntry
857 || pEntry->uModel != uModel
858 || pEntry->enmMicroarch != enmMicroarch
859 || pEntry->uFamily != uFamily)
860 pEntry = pCur;
861 else if ( pCur->uStepping >= uStepping
862 ? pCur->uStepping < pEntry->uStepping || pEntry->uStepping < uStepping
863 : pCur->uStepping > pEntry->uStepping)
864 pEntry = pCur;
865 }
866 else if ( !pEntry
867 || pEntry->enmMicroarch != enmMicroarch
868 || pEntry->uFamily != uFamily)
869 pEntry = pCur;
870 else if ( pCur->uModel >= uModel
871 ? pCur->uModel < pEntry->uModel || pEntry->uModel < uModel
872 : pCur->uModel > pEntry->uModel)
873 pEntry = pCur;
874 }
875 else if ( !pEntry
876 || pEntry->uFamily != uFamily)
877 pEntry = pCur;
878 /* Special march matching rules applies to intel family 06h. */
879 else if ( enmVendor == CPUMCPUVENDOR_INTEL
880 && uFamily == 6
881 ? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
882 : cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
883 pEntry = pCur;
884 }
885 /* We don't do closeness matching on family, we use the first
886 entry for the CPU vendor instead. (P4 workaround.) */
887 else if (!pEntry)
888 pEntry = pCur;
889 }
890 }
891
892 if (pEntry)
893 LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
894 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
895 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
896 pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
897 else
898 {
899 pEntry = g_apCpumDbEntries[0];
900 LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
901 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
902 pEntry->pszName));
903 }
904 }
905 else
906 {
907 /*
908 * We're supposed to be emulating a specific CPU that is included in
909 * our CPU database. The CPUID tables needs to be copied onto the
910 * heap so the caller can modify them and so they can be freed like
911 * in the host case above.
912 */
913 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
914 if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
915 {
916 pEntry = g_apCpumDbEntries[i];
917 break;
918 }
919 if (!pEntry)
920 {
921 LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
922 return VERR_CPUM_DB_CPU_NOT_FOUND;
923 }
924
925 pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
926 if (pEntry->cCpuIdLeaves)
927 {
928 /* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
929 size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
930 pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
931 sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
932 cbExtra);
933 if (!pInfo->paCpuIdLeavesR3)
934 return VERR_NO_MEMORY;
935 }
936 else
937 pInfo->paCpuIdLeavesR3 = NULL;
938
939 pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
940 pInfo->DefCpuId = pEntry->DefUnknownCpuId;
941 pInfo->fMxCsrMask = pEntry->fMxCsrMask;
942
943 LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
944 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
945 pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
946 }
947
948 pInfo->fMsrMask = pEntry->fMsrMask;
949 pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
950 pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
951 pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
952 pInfo->paMsrRangesR0 = NIL_RTR0PTR;
953 pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
954 pInfo->paMsrRangesRC = NIL_RTRCPTR;
955
956 /*
957 * Copy the MSR range.
958 */
959 uint32_t cMsrs = 0;
960 PCPUMMSRRANGE paMsrs = NULL;
961
962 PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
963 uint32_t cLeft = pEntry->cMsrRanges;
964 while (cLeft-- > 0)
965 {
966 rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
967 if (RT_FAILURE(rc))
968 {
969 Assert(!paMsrs); /* The above function frees this. */
970 RTMemFree(pInfo->paCpuIdLeavesR3);
971 pInfo->paCpuIdLeavesR3 = NULL;
972 return rc;
973 }
974 pCurMsr++;
975 }
976
977 pInfo->paMsrRangesR3 = paMsrs;
978 pInfo->cMsrRanges = cMsrs;
979 return VINF_SUCCESS;
980}
981
982
983/**
984 * Insert an MSR range into the VM.
985 *
986 * If the new MSR range overlaps existing ranges, the existing ones will be
987 * adjusted/removed to fit in the new one.
988 *
989 * @returns VBox status code.
990 * @param pVM The cross context VM structure.
991 * @param pNewRange Pointer to the MSR range being inserted.
992 */
993VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
994{
995 AssertReturn(pVM, VERR_INVALID_PARAMETER);
996 AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
997
998 return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges */, NULL /* pcMsrRanges */, pNewRange);
999}
1000
1001
1002/**
1003 * Register statistics for the MSRs.
1004 *
1005 * This must not be called before the MSRs have been finalized and moved to the
1006 * hyper heap.
1007 *
1008 * @returns VBox status code.
1009 * @param pVM The cross context VM structure.
1010 */
1011int cpumR3MsrRegStats(PVM pVM)
1012{
1013 /*
1014 * Global statistics.
1015 */
1016 PCPUM pCpum = &pVM->cpum.s;
1017 STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
1018 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1019 STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
1020 STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
1021 STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
1022 STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
1023 STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
1024 STAMUNIT_OCCURENCES, "All WRMSRs making it to CPUM.");
1025 STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1026 STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1027 STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1028 STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1029 STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1030 STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1031
1032
1033# ifdef VBOX_WITH_STATISTICS
1034 /*
1035 * Per range.
1036 */
1037 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1038 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1039 for (uint32_t i = 0; i < cRanges; i++)
1040 {
1041 char szName[160];
1042 ssize_t cchName;
1043
1044 if (paRanges[i].uFirst == paRanges[i].uLast)
1045 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1046 paRanges[i].uFirst, paRanges[i].szName);
1047 else
1048 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1049 paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1050
1051 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1052 STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1053
1054 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1055 STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1056
1057 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1058 STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1059
1060 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1061 STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1062 }
1063# endif /* VBOX_WITH_STATISTICS */
1064
1065 return VINF_SUCCESS;
1066}
1067
1068#endif /* !CPUM_DB_STANDALONE */
1069
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