CPUMR3CpuId.cpp@ 107763

Last change on this file since 107763 was 107749, checked in by vboxsync, 4 months ago
VMM/CPUM: Pass thru more MSR_IA32_SPEC_CTRL related stuff to the guest. jiraref:VBP-947
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 308.6 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 107749 2025-01-14 10:28:53Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#include <VBox/vmm/cpum.h>
34	#include <VBox/vmm/dbgf.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/nem.h>
37	#include <VBox/vmm/ssm.h>
38	#include "CPUMInternal.h"
39	#include <VBox/vmm/vmcc.h>
40	#include <VBox/sup.h>
41
42	#include <VBox/err.h>
43	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
44	# include <iprt/asm-amd64-x86.h>
45	#endif
46	#include <iprt/ctype.h>
47	#include <iprt/mem.h>
48	#include <iprt/string.h>
49	#include <iprt/x86-helpers.h>
50
51
52	/*********************************************************************************************************************************
53	* Defined Constants And Macros *
54	*********************************************************************************************************************************/
55	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
56	#define CPUM_CPUID_MAX_LEAVES 2048
57
58
59	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
60	/**
61	* Determins the host CPU MXCSR mask.
62	*
63	* @returns MXCSR mask.
64	*/
65	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
66	{
67	if ( ASMHasCpuId()
68	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
69	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
70	{
71	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
72	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
73	RT_ZERO(*pState);
74	ASMFxSave(pState);
75	if (pState->MXCSR_MASK == 0)
76	return 0xffbf;
77	return pState->MXCSR_MASK;
78	}
79	return 0;
80	}
81	#endif
82
83
84
85	#ifndef IN_VBOX_CPU_REPORT
86	/**
87	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
88	*
89	* @returns true if found, false it not.
90	* @param paLeaves The CPUID leaves to search. This is sorted.
91	* @param cLeaves The number of leaves in the array.
92	* @param uLeaf The leaf to locate.
93	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
94	* @param pLegacy The legacy output leaf.
95	*/
96	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
97	PCPUMCPUID pLegacy)
98	{
99	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, uLeaf, uSubLeaf);
100	if (pLeaf)
101	{
102	pLegacy->uEax = pLeaf->uEax;
103	pLegacy->uEbx = pLeaf->uEbx;
104	pLegacy->uEcx = pLeaf->uEcx;
105	pLegacy->uEdx = pLeaf->uEdx;
106	return true;
107	}
108	return false;
109	}
110	#endif /* IN_VBOX_CPU_REPORT */
111
112
113	/**
114	* Inserts a CPU ID leaf, replacing any existing ones.
115	*
116	* When inserting a simple leaf where we already got a series of sub-leaves with
117	* the same leaf number (eax), the simple leaf will replace the whole series.
118	*
119	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
120	* host-context heap and has only been allocated/reallocated by the
121	* cpumCpuIdEnsureSpace function.
122	*
123	* @returns VBox status code.
124	* @param pVM The cross context VM structure. If NULL, use
125	* the process heap, otherwise the VM's hyper heap.
126	* @param ppaLeaves Pointer to the pointer to the array of sorted
127	* CPUID leaves and sub-leaves. Must be NULL if using
128	* the hyper heap.
129	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
130	* be NULL if using the hyper heap.
131	* @param pNewLeaf Pointer to the data of the new leaf we're about to
132	* insert.
133	*/
134	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
135	{
136	/*
137	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
138	*/
139	if (pVM)
140	{
141	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
142	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
143	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
144
145	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
146	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
147	}
148
149	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
150	uint32_t cLeaves = *pcLeaves;
151
152	/*
153	* Validate the new leaf a little.
154	*/
155	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
156	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
157	VERR_INVALID_FLAGS);
158	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
159	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
160	VERR_INVALID_PARAMETER);
161	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
162	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
163	VERR_INVALID_PARAMETER);
164	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
165	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
166	VERR_INVALID_PARAMETER);
167
168	/*
169	* Find insertion point. The lazy bird uses the same excuse as in
170	* cpumCpuIdGetLeaf(), but optimizes for linear insertion (saved state).
171	*/
172	uint32_t i;
173	if ( cLeaves > 0
174	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
175	{
176	/* Add at end. */
177	i = cLeaves;
178	}
179	else if ( cLeaves > 0
180	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
181	{
182	/* Either replacing the last leaf or dealing with sub-leaves. Spool
183	back to the first sub-leaf to pretend we did the linear search. */
184	i = cLeaves - 1;
185	while ( i > 0
186	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
187	i--;
188	}
189	else
190	{
191	/* Linear search from the start. */
192	i = 0;
193	while ( i < cLeaves
194	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
195	i++;
196	}
197	if ( i < cLeaves
198	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
199	{
200	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
201	{
202	/*
203	* The sub-leaf mask differs, replace all existing leaves with the
204	* same leaf number.
205	*/
206	uint32_t c = 1;
207	while ( i + c < cLeaves
208	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
209	c++;
210	if (c > 1 && i + c < cLeaves)
211	{
212	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
213	*pcLeaves = cLeaves -= c - 1;
214	}
215
216	paLeaves[i] = *pNewLeaf;
217	#ifdef VBOX_STRICT
218	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
219	#endif
220	return VINF_SUCCESS;
221	}
222
223	/* Find sub-leaf insertion point. */
224	while ( i < cLeaves
225	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
226	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
227	i++;
228
229	/*
230	* If we've got an exactly matching leaf, replace it.
231	*/
232	if ( i < cLeaves
233	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
234	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
235	{
236	paLeaves[i] = *pNewLeaf;
237	#ifdef VBOX_STRICT
238	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
239	#endif
240	return VINF_SUCCESS;
241	}
242	}
243
244	/*
245	* Adding a new leaf at 'i'.
246	*/
247	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
248	paLeaves = cpumCpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
249	if (!paLeaves)
250	return VERR_NO_MEMORY;
251
252	if (i < cLeaves)
253	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
254	*pcLeaves += 1;
255	paLeaves[i] = *pNewLeaf;
256
257	#ifdef VBOX_STRICT
258	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
259	#endif
260	return VINF_SUCCESS;
261	}
262
263
264	#ifndef IN_VBOX_CPU_REPORT
265	/**
266	* Removes a range of CPUID leaves.
267	*
268	* This will not reallocate the array.
269	*
270	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
271	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
272	* @param uFirst The first leaf.
273	* @param uLast The last leaf.
274	*/
275	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
276	{
277	uint32_t cLeaves = *pcLeaves;
278
279	Assert(uFirst <= uLast);
280
281	/*
282	* Find the first one.
283	*/
284	uint32_t iFirst = 0;
285	while ( iFirst < cLeaves
286	&& paLeaves[iFirst].uLeaf < uFirst)
287	iFirst++;
288
289	/*
290	* Find the end (last + 1).
291	*/
292	uint32_t iEnd = iFirst;
293	while ( iEnd < cLeaves
294	&& paLeaves[iEnd].uLeaf <= uLast)
295	iEnd++;
296
297	/*
298	* Adjust the array if anything needs removing.
299	*/
300	if (iFirst < iEnd)
301	{
302	if (iEnd < cLeaves)
303	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
304	*pcLeaves = cLeaves -= (iEnd - iFirst);
305	}
306
307	# ifdef VBOX_STRICT
308	cpumCpuIdAssertOrder(paLeaves, *pcLeaves);
309	# endif
310	}
311	#endif /* IN_VBOX_CPU_REPORT */
312
313
314	/**
315	* Gets a CPU ID leaf.
316	*
317	* @returns VBox status code.
318	* @param pVM The cross context VM structure.
319	* @param pLeaf Where to store the found leaf.
320	* @param uLeaf The leaf to locate.
321	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
322	*/
323	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
324	{
325	PCPUMCPUIDLEAF pcLeaf = cpumCpuIdGetLeafInt(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
326	uLeaf, uSubLeaf);
327	if (pcLeaf)
328	{
329	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
330	return VINF_SUCCESS;
331	}
332
333	return VERR_NOT_FOUND;
334	}
335
336
337	/**
338	* Gets all the leaves.
339	*
340	* This only works after the CPUID leaves have been initialized. The interface
341	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
342	*
343	* @returns Pointer to the array of leaves. NULL on failure.
344	* @param pVM The cross context VM structure.
345	* @param pcLeaves Where to return the number of leaves.
346	*/
347	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
348	{
349	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
350	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
351	}
352
353
354	/**
355	* Inserts a CPU ID leaf, replacing any existing ones.
356	*
357	* @returns VBox status code.
358	* @param pVM The cross context VM structure.
359	* @param pNewLeaf Pointer to the leaf being inserted.
360	*/
361	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
362	{
363	/*
364	* Validate parameters.
365	*/
366	AssertReturn(pVM, VERR_INVALID_PARAMETER);
367	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
368
369	/*
370	* Disallow replacing CPU ID leaves that this API currently cannot manage.
371	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
372	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
373	*/
374	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
375	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
376	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
377	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
378	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
379	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
380	{
381	return VERR_NOT_SUPPORTED;
382	}
383
384	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
385	}
386
387
388	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
389	/**
390	* Determines the method the CPU uses to handle unknown CPUID leaves.
391	*
392	* @returns VBox status code.
393	* @param penmUnknownMethod Where to return the method.
394	* @param pDefUnknown Where to return default unknown values. This
395	* will be set, even if the resulting method
396	* doesn't actually needs it.
397	*/
398	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
399	{
400	uint32_t uLastStd = ASMCpuId_EAX(0);
401	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
402	if (!RTX86IsValidExtRange(uLastExt))
403	uLastExt = 0x80000000;
404
405	uint32_t auChecks[] =
406	{
407	uLastStd + 1,
408	uLastStd + 5,
409	uLastStd + 8,
410	uLastStd + 32,
411	uLastStd + 251,
412	uLastExt + 1,
413	uLastExt + 8,
414	uLastExt + 15,
415	uLastExt + 63,
416	uLastExt + 255,
417	0x7fbbffcc,
418	0x833f7872,
419	0xefff2353,
420	0x35779456,
421	0x1ef6d33e,
422	};
423
424	static const uint32_t s_auValues[] =
425	{
426	0xa95d2156,
427	0x00000001,
428	0x00000002,
429	0x00000008,
430	0x00000000,
431	0x55773399,
432	0x93401769,
433	0x12039587,
434	};
435
436	/*
437	* Simple method, all zeros.
438	*/
439	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
440	pDefUnknown->uEax = 0;
441	pDefUnknown->uEbx = 0;
442	pDefUnknown->uEcx = 0;
443	pDefUnknown->uEdx = 0;
444
445	/*
446	* Intel has been observed returning the last standard leaf.
447	*/
448	uint32_t auLast[4];
449	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
450
451	uint32_t cChecks = RT_ELEMENTS(auChecks);
452	while (cChecks > 0)
453	{
454	uint32_t auCur[4];
455	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
456	if (memcmp(auCur, auLast, sizeof(auCur)))
457	break;
458	cChecks--;
459	}
460	if (cChecks == 0)
461	{
462	/* Now, what happens when the input changes? Esp. ECX. */
463	uint32_t cTotal = 0;
464	uint32_t cSame = 0;
465	uint32_t cLastWithEcx = 0;
466	uint32_t cNeither = 0;
467	uint32_t cValues = RT_ELEMENTS(s_auValues);
468	while (cValues > 0)
469	{
470	uint32_t uValue = s_auValues[cValues - 1];
471	uint32_t auLastWithEcx[4];
472	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
473	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
474
475	cChecks = RT_ELEMENTS(auChecks);
476	while (cChecks > 0)
477	{
478	uint32_t auCur[4];
479	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
480	if (!memcmp(auCur, auLast, sizeof(auCur)))
481	{
482	cSame++;
483	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
484	cLastWithEcx++;
485	}
486	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
487	cLastWithEcx++;
488	else
489	cNeither++;
490	cTotal++;
491	cChecks--;
492	}
493	cValues--;
494	}
495
496	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
497	if (cSame == cTotal)
498	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
499	else if (cLastWithEcx == cTotal)
500	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
501	else
502	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
503	pDefUnknown->uEax = auLast[0];
504	pDefUnknown->uEbx = auLast[1];
505	pDefUnknown->uEcx = auLast[2];
506	pDefUnknown->uEdx = auLast[3];
507	return VINF_SUCCESS;
508	}
509
510	/*
511	* Unchanged register values?
512	*/
513	cChecks = RT_ELEMENTS(auChecks);
514	while (cChecks > 0)
515	{
516	uint32_t const uLeaf = auChecks[cChecks - 1];
517	uint32_t cValues = RT_ELEMENTS(s_auValues);
518	while (cValues > 0)
519	{
520	uint32_t uValue = s_auValues[cValues - 1];
521	uint32_t auCur[4];
522	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
523	if ( auCur[0] != uLeaf
524	\|\| auCur[1] != uValue
525	\|\| auCur[2] != uValue
526	\|\| auCur[3] != uValue)
527	break;
528	cValues--;
529	}
530	if (cValues != 0)
531	break;
532	cChecks--;
533	}
534	if (cChecks == 0)
535	{
536	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
537	return VINF_SUCCESS;
538	}
539
540	/*
541	* Just go with the simple method.
542	*/
543	return VINF_SUCCESS;
544	}
545	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
546
547
548	/**
549	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
550	*
551	* @returns Read only name string.
552	* @param enmUnknownMethod The method to translate.
553	*/
554	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
555	{
556	switch (enmUnknownMethod)
557	{
558	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
559	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
560	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
561	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
562
563	case CPUMUNKNOWNCPUID_INVALID:
564	case CPUMUNKNOWNCPUID_END:
565	case CPUMUNKNOWNCPUID_32BIT_HACK:
566	break;
567	}
568	return "Invalid-unknown-CPUID-method";
569	}
570
571
572	/*
573	*
574	* Init related code.
575	* Init related code.
576	* Init related code.
577	*
578	*
579	*/
580	#ifndef IN_VBOX_CPU_REPORT
581
582
583	/**
584	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
585	*
586	* This ignores the fSubLeafMask.
587	*
588	* @returns Pointer to the matching leaf, or NULL if not found.
589	* @param pCpum The CPUM instance data.
590	* @param uLeaf The leaf to locate.
591	* @param uSubLeaf The subleaf to locate.
592	*/
593	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
594	{
595	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
596	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
597	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
598	if (iEnd)
599	{
600	uint32_t iBegin = 0;
601	for (;;)
602	{
603	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
604	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
605	if (uNeedle < uCur)
606	{
607	if (i > iBegin)
608	iEnd = i;
609	else
610	break;
611	}
612	else if (uNeedle > uCur)
613	{
614	if (i + 1 < iEnd)
615	iBegin = i + 1;
616	else
617	break;
618	}
619	else
620	return &paLeaves[i];
621	}
622	}
623	return NULL;
624	}
625
626
627	/**
628	* Loads MSR range overrides.
629	*
630	* This must be called before the MSR ranges are moved from the normal heap to
631	* the hyper heap!
632	*
633	* @returns VBox status code (VMSetError called).
634	* @param pVM The cross context VM structure.
635	* @param pMsrNode The CFGM node with the MSR overrides.
636	*/
637	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
638	{
639	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
640	{
641	/*
642	* Assemble a valid MSR range.
643	*/
644	CPUMMSRRANGE MsrRange;
645	MsrRange.offCpumCpu = 0;
646	MsrRange.fReserved = 0;
647
648	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
649	if (RT_FAILURE(rc))
650	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
651
652	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
653	if (RT_FAILURE(rc))
654	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
655	MsrRange.szName, rc);
656
657	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
658	if (RT_FAILURE(rc))
659	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
660	MsrRange.szName, rc);
661
662	char szType[32];
663	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
664	if (RT_FAILURE(rc))
665	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
666	MsrRange.szName, rc);
667	if (!RTStrICmp(szType, "FixedValue"))
668	{
669	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
670	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
671
672	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
673	if (RT_FAILURE(rc))
674	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
675	MsrRange.szName, rc);
676
677	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
678	if (RT_FAILURE(rc))
679	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
680	MsrRange.szName, rc);
681
682	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
683	if (RT_FAILURE(rc))
684	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
685	MsrRange.szName, rc);
686	}
687	else
688	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
689	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
690
691	/*
692	* Insert the range into the table (replaces/splits/shrinks existing
693	* MSR ranges).
694	*/
695	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
696	&MsrRange);
697	if (RT_FAILURE(rc))
698	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
699	}
700
701	return VINF_SUCCESS;
702	}
703
704
705	/**
706	* Loads CPUID leaf overrides.
707	*
708	* This must be called before the CPUID leaves are moved from the normal
709	* heap to the hyper heap!
710	*
711	* @returns VBox status code (VMSetError called).
712	* @param pVM The cross context VM structure.
713	* @param pParentNode The CFGM node with the CPUID leaves.
714	* @param pszLabel How to label the overrides we're loading.
715	*/
716	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
717	{
718	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
719	{
720	/*
721	* Get the leaf and subleaf numbers.
722	*/
723	char szName[128];
724	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
725	if (RT_FAILURE(rc))
726	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
727
728	/* The leaf number is either specified directly or thru the node name. */
729	uint32_t uLeaf;
730	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
731	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
732	{
733	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
734	if (rc != VINF_SUCCESS)
735	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
736	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
737	}
738	else if (RT_FAILURE(rc))
739	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
740	pszLabel, szName, rc);
741
742	uint32_t uSubLeaf;
743	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
744	if (RT_FAILURE(rc))
745	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
746	pszLabel, szName, rc);
747
748	uint32_t fSubLeafMask;
749	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
750	if (RT_FAILURE(rc))
751	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
752	pszLabel, szName, rc);
753
754	/*
755	* Look up the specified leaf, since the output register values
756	* defaults to any existing values. This allows overriding a single
757	* register, without needing to know the other values.
758	*/
759	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
760	CPUMCPUIDLEAF Leaf;
761	if (pLeaf)
762	Leaf = *pLeaf;
763	else
764	RT_ZERO(Leaf);
765	Leaf.uLeaf = uLeaf;
766	Leaf.uSubLeaf = uSubLeaf;
767	Leaf.fSubLeafMask = fSubLeafMask;
768
769	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
770	if (RT_FAILURE(rc))
771	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
772	pszLabel, szName, rc);
773	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
774	if (RT_FAILURE(rc))
775	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
776	pszLabel, szName, rc);
777	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
778	if (RT_FAILURE(rc))
779	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
780	pszLabel, szName, rc);
781	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
782	if (RT_FAILURE(rc))
783	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
784	pszLabel, szName, rc);
785
786	/*
787	* Insert the leaf into the table (replaces existing ones).
788	*/
789	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
790	&Leaf);
791	if (RT_FAILURE(rc))
792	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
793	}
794
795	return VINF_SUCCESS;
796	}
797
798
799
800	/**
801	* Fetches overrides for a CPUID leaf.
802	*
803	* @returns VBox status code.
804	* @param pLeaf The leaf to load the overrides into.
805	* @param pCfgNode The CFGM node containing the overrides
806	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
807	* @param iLeaf The CPUID leaf number.
808	*/
809	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
810	{
811	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
812	if (pLeafNode)
813	{
814	uint32_t u32;
815	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
816	if (RT_SUCCESS(rc))
817	pLeaf->uEax = u32;
818	else
819	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
820
821	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
822	if (RT_SUCCESS(rc))
823	pLeaf->uEbx = u32;
824	else
825	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
826
827	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
828	if (RT_SUCCESS(rc))
829	pLeaf->uEcx = u32;
830	else
831	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
832
833	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
834	if (RT_SUCCESS(rc))
835	pLeaf->uEdx = u32;
836	else
837	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
838
839	}
840	return VINF_SUCCESS;
841	}
842
843
844	/**
845	* Load the overrides for a set of CPUID leaves.
846	*
847	* @returns VBox status code.
848	* @param paLeaves The leaf array.
849	* @param cLeaves The number of leaves.
850	* @param uStart The start leaf number.
851	* @param pCfgNode The CFGM node containing the overrides
852	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
853	*/
854	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
855	{
856	for (uint32_t i = 0; i < cLeaves; i++)
857	{
858	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
859	if (RT_FAILURE(rc))
860	return rc;
861	}
862
863	return VINF_SUCCESS;
864	}
865
866
867	/**
868	* Installs the CPUID leaves and explods the data into structures like
869	* GuestFeatures and CPUMCTX::aoffXState.
870	*
871	* @returns VBox status code.
872	* @param pVM The cross context VM structure.
873	* @param pCpum The CPUM part of @a VM.
874	* @param paLeaves The leaves. These will be copied (but not freed).
875	* @param cLeaves The number of leaves.
876	* @param pMsrs The MSRs.
877	*/
878	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
879	{
880	# ifdef VBOX_STRICT
881	cpumCpuIdAssertOrder(paLeaves, cLeaves);
882	# endif
883
884	/*
885	* Install the CPUID information.
886	*/
887	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
888	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
889	VERR_CPUM_IPE_1); /** @todo better status! */
890	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
891	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
892	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
893	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
894
895	/*
896	* Update the default CPUID leaf if necessary.
897	*/
898	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
899	{
900	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
901	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
902	{
903	/* We don't use CPUID(0).eax here because of the NT hack that only
904	changes that value without actually removing any leaves. */
905	uint32_t i = 0;
906	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
907	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
908	{
909	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
910	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
911	i++;
912	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
913	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
914	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
915	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
916	}
917	break;
918	}
919	default:
920	break;
921	}
922
923	/*
924	* Explode the guest CPU features.
925	*/
926	int rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
927	&pCpum->GuestFeatures);
928	AssertLogRelRCReturn(rc, rc);
929
930	/*
931	* Adjust the scalable bus frequency according to the CPUID information
932	* we're now using.
933	*/
934	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
935	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
936	? UINT64_C(100000000) /* 100MHz */
937	: UINT64_C(133333333); /* 133MHz */
938
939	/*
940	* Populate the legacy arrays. Currently used for everything, later only
941	* for patch manager.
942	*/
943	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
944	{
945	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
946	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
947	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
948	};
949	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
950	{
951	uint32_t cLeft = aOldRanges[i].cCpuIds;
952	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
953	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
954	while (cLeft-- > 0)
955	{
956	uLeaf--;
957	pLegacyLeaf--;
958
959	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
960	if (pLeaf)
961	{
962	pLegacyLeaf->uEax = pLeaf->uEax;
963	pLegacyLeaf->uEbx = pLeaf->uEbx;
964	pLegacyLeaf->uEcx = pLeaf->uEcx;
965	pLegacyLeaf->uEdx = pLeaf->uEdx;
966	}
967	else
968	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
969	}
970	}
971
972	/*
973	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
974	*/
975	PVMCPU pVCpu0 = pVM->apCpusR3[0];
976	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
977	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
978	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
979	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
980	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
981	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
982	{
983	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
984	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
985	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
986	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
987	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
988	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
989	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
990	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
991	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
992	pCpum->GuestFeatures.cbMaxExtendedState),
993	VERR_CPUM_IPE_1);
994	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
995	}
996
997	/* Copy the CPU #0 data to the other CPUs. */
998	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
999	{
1000	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1001	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
1002	}
1003
1004	return VINF_SUCCESS;
1005	}
1006
1007
1008	/** @name Instruction Set Extension Options
1009	* @{ */
1010	/** Configuration option type (extended boolean, really). */
1011	typedef uint8_t CPUMISAEXTCFG;
1012	/** Always disable the extension. */
1013	#define CPUMISAEXTCFG_DISABLED false
1014	/** Enable the extension if it's supported by the host CPU. */
1015	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
1016	/** Enable the extension if it's supported by the host CPU or when on ARM64. */
1017	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1018	# define CPUMISAEXTCFG_ENABLED_SUPPORTED_OR_NOT_AMD64 CPUMISAEXTCFG_ENABLED_SUPPORTED
1019	#else
1020	# define CPUMISAEXTCFG_ENABLED_SUPPORTED_OR_NOT_AMD64 CPUMISAEXTCFG_ENABLED_ALWAYS
1021	#endif
1022	/** Enable the extension if it's supported by the host CPU, but don't let
1023	* the portable CPUID feature disable it. */
1024	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
1025	/** Always enable the extension. */
1026	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
1027	/** @} */
1028
1029	/**
1030	* CPUID Configuration (from CFGM).
1031	*
1032	* @remarks The members aren't document since we would only be duplicating the
1033	* \@cfgm entries in cpumR3CpuIdReadConfig.
1034	*/
1035	typedef struct CPUMCPUIDCONFIG
1036	{
1037	bool fNt4LeafLimit;
1038	bool fInvariantTsc;
1039	bool fInvariantApic;
1040	bool fForceVme;
1041	bool fNestedHWVirt;
1042
1043	CPUMISAEXTCFG enmCmpXchg16b;
1044	CPUMISAEXTCFG enmMonitor;
1045	CPUMISAEXTCFG enmMWaitExtensions;
1046	CPUMISAEXTCFG enmSse41;
1047	CPUMISAEXTCFG enmSse42;
1048	CPUMISAEXTCFG enmAvx;
1049	CPUMISAEXTCFG enmAvx2;
1050	CPUMISAEXTCFG enmXSave;
1051	CPUMISAEXTCFG enmAesNi;
1052	CPUMISAEXTCFG enmPClMul;
1053	CPUMISAEXTCFG enmPopCnt;
1054	CPUMISAEXTCFG enmMovBe;
1055	CPUMISAEXTCFG enmRdRand;
1056	CPUMISAEXTCFG enmRdSeed;
1057	CPUMISAEXTCFG enmSha;
1058	CPUMISAEXTCFG enmAdx;
1059	CPUMISAEXTCFG enmCLFlushOpt;
1060	CPUMISAEXTCFG enmFsGsBase;
1061	CPUMISAEXTCFG enmPcid;
1062	CPUMISAEXTCFG enmInvpcid;
1063	CPUMISAEXTCFG enmFlushCmdMsr;
1064	CPUMISAEXTCFG enmMdsClear;
1065	CPUMISAEXTCFG enmArchCapMsr;
1066	CPUMISAEXTCFG enmFma;
1067	CPUMISAEXTCFG enmF16c;
1068	CPUMISAEXTCFG enmMcdtNo;
1069	CPUMISAEXTCFG enmMonitorMitgNo;
1070
1071	CPUMISAEXTCFG enmAbm;
1072	CPUMISAEXTCFG enmSse4A;
1073	CPUMISAEXTCFG enmMisAlnSse;
1074	CPUMISAEXTCFG enm3dNowPrf;
1075	CPUMISAEXTCFG enmAmdExtMmx;
1076
1077	uint32_t uMaxStdLeaf;
1078	uint32_t uMaxExtLeaf;
1079	uint32_t uMaxCentaurLeaf;
1080	uint32_t uMaxIntelFamilyModelStep;
1081	char szCpuName[128];
1082	} CPUMCPUIDCONFIG;
1083	/** Pointer to CPUID config (from CFGM). */
1084	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
1085
1086
1087	/**
1088	* Mini CPU selection support for making Mac OS X happy.
1089	*
1090	* Executes the /CPUM/MaxIntelFamilyModelStep config.
1091	*
1092	* @param pCpum The CPUM instance data.
1093	* @param pConfig The CPUID configuration we've read from CFGM.
1094	*/
1095	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1096	{
1097	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1098	{
1099	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1100	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
1101	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
1102	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
1103	0);
1104	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
1105	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1106	{
1107	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1108	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1109	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1110	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1111	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1112	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1113	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1114	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1115	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1116	pStdFeatureLeaf->uEax = uNew;
1117	}
1118	}
1119	}
1120
1121
1122
1123	/**
1124	* Limit it the number of entries, zapping the remainder.
1125	*
1126	* The limits are masking off stuff about power saving and similar, this
1127	* is perhaps a bit crudely done as there is probably some relatively harmless
1128	* info too in these leaves (like words about having a constant TSC).
1129	*
1130	* @param pCpum The CPUM instance data.
1131	* @param pConfig The CPUID configuration we've read from CFGM.
1132	*/
1133	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1134	{
1135	/*
1136	* Standard leaves.
1137	*/
1138	uint32_t uSubLeaf = 0;
1139	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
1140	if (pCurLeaf)
1141	{
1142	uint32_t uLimit = pCurLeaf->uEax;
1143	if (uLimit <= UINT32_C(0x000fffff))
1144	{
1145	if (uLimit > pConfig->uMaxStdLeaf)
1146	{
1147	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
1148	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1149	uLimit + 1, UINT32_C(0x000fffff));
1150	}
1151
1152	/* NT4 hack, no zapping of extra leaves here. */
1153	if (pConfig->fNt4LeafLimit && uLimit > 3)
1154	pCurLeaf->uEax = uLimit = 3;
1155
1156	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
1157	pCurLeaf->uEax = uLimit;
1158	}
1159	else
1160	{
1161	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
1162	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1163	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
1164	}
1165	}
1166
1167	/*
1168	* Extended leaves.
1169	*/
1170	uSubLeaf = 0;
1171	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
1172	if (pCurLeaf)
1173	{
1174	uint32_t uLimit = pCurLeaf->uEax;
1175	if ( uLimit >= UINT32_C(0x80000000)
1176	&& uLimit <= UINT32_C(0x800fffff))
1177	{
1178	if (uLimit > pConfig->uMaxExtLeaf)
1179	{
1180	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
1181	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1182	uLimit + 1, UINT32_C(0x800fffff));
1183	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
1184	pCurLeaf->uEax = uLimit;
1185	}
1186	}
1187	else
1188	{
1189	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
1190	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1191	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
1192	}
1193	}
1194
1195	/*
1196	* Centaur leaves (VIA).
1197	*/
1198	uSubLeaf = 0;
1199	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
1200	if (pCurLeaf)
1201	{
1202	uint32_t uLimit = pCurLeaf->uEax;
1203	if ( uLimit >= UINT32_C(0xc0000000)
1204	&& uLimit <= UINT32_C(0xc00fffff))
1205	{
1206	if (uLimit > pConfig->uMaxCentaurLeaf)
1207	{
1208	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
1209	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1210	uLimit + 1, UINT32_C(0xcfffffff));
1211	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
1212	pCurLeaf->uEax = uLimit;
1213	}
1214	}
1215	else
1216	{
1217	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
1218	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1219	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
1220	}
1221	}
1222	}
1223
1224
1225	/**
1226	* Clears a CPUID leaf and all sub-leaves (to zero).
1227	*
1228	* @param pCpum The CPUM instance data.
1229	* @param uLeaf The leaf to clear.
1230	*/
1231	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
1232	{
1233	uint32_t uSubLeaf = 0;
1234	PCPUMCPUIDLEAF pCurLeaf;
1235	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
1236	{
1237	pCurLeaf->uEax = 0;
1238	pCurLeaf->uEbx = 0;
1239	pCurLeaf->uEcx = 0;
1240	pCurLeaf->uEdx = 0;
1241	uSubLeaf++;
1242	}
1243	}
1244
1245
1246	/**
1247	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
1248	* the given leaf.
1249	*
1250	* @returns pLeaf.
1251	* @param pCpum The CPUM instance data.
1252	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
1253	*/
1254	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
1255	{
1256	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
1257	if (pLeaf->fSubLeafMask != 0)
1258	{
1259	/*
1260	* Figure out how many sub-leaves in need of removal (we'll keep the first).
1261	* Log everything while we're at it.
1262	*/
1263	LogRel(("CPUM:\n"
1264	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
1265	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
1266	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
1267	for (;;)
1268	{
1269	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
1270	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
1271	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
1272	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
1273	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
1274	break;
1275	pSubLeaf++;
1276	}
1277	LogRel(("CPUM:\n"));
1278
1279	/*
1280	* Remove the offending sub-leaves.
1281	*/
1282	if (pSubLeaf != pLeaf)
1283	{
1284	if (pSubLeaf != pLast)
1285	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
1286	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
1287	}
1288
1289	/*
1290	* Convert the first sub-leaf into a single leaf.
1291	*/
1292	pLeaf->uSubLeaf = 0;
1293	pLeaf->fSubLeafMask = 0;
1294	}
1295	return pLeaf;
1296	}
1297
1298
1299	/**
1300	* Sanitizes and adjust the CPUID leaves.
1301	*
1302	* Drop features that aren't virtualized (or virtualizable). Adjust information
1303	* and capabilities to fit the virtualized hardware. Remove information the
1304	* guest shouldn't have (because it's wrong in the virtual world or because it
1305	* gives away host details) or that we don't have documentation for and no idea
1306	* what means.
1307	*
1308	* @returns VBox status code.
1309	* @param pVM The cross context VM structure (for cCpus).
1310	* @param pCpum The CPUM instance data.
1311	* @param pConfig The CPUID configuration we've read from CFGM.
1312	*/
1313	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1314	{
1315	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1316	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1317	{ \
1318	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1319	(a_pLeafReg) &= ~(uint32_t)(fMask); \
1320	}
1321	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1322	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1323	{ \
1324	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1325	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1326	}
1327	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
1328	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
1329	&& ((a_pLeafReg) & (fBitMask)) \
1330	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
1331	{ \
1332	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1333	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1334	}
1335	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1336
1337	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
1338	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
1339	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1340	PCCPUMFEATURES const pHstFeat = &pCpum->HostFeatures.s;
1341	#else
1342	PCCPUMFEATURES const pHstFeat = &pCpum->GuestFeatures;
1343	#endif
1344	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
1345	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
1346	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
1347	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
1348	#define PASSTHRU_FEATURE_NOT_IEM(enmConfig, fHostFeature, fConst) \
1349	PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, !VM_IS_EXEC_ENGINE_IEM(pVM), fConst)
1350	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
1351
1352	/* Cpuid 1:
1353	* EAX: CPU model, family and stepping.
1354	*
1355	* ECX + EDX: Supported features. Only report features we can support.
1356	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1357	* options may require adjusting (i.e. stripping what was enabled).
1358	*
1359	* EBX: Branding, CLFLUSH line size, logical processors per package and
1360	* initial APIC ID.
1361	*/
1362	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
1363	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1364	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
1365
1366	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1367	\| X86_CPUID_FEATURE_EDX_VME
1368	\| X86_CPUID_FEATURE_EDX_DE
1369	\| X86_CPUID_FEATURE_EDX_PSE
1370	\| X86_CPUID_FEATURE_EDX_TSC
1371	\| X86_CPUID_FEATURE_EDX_MSR
1372	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1373	\| X86_CPUID_FEATURE_EDX_MCE
1374	\| X86_CPUID_FEATURE_EDX_CX8
1375	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1376	//\| RT_BIT_32(10) - not defined
1377	\| X86_CPUID_FEATURE_EDX_SEP
1378	\| X86_CPUID_FEATURE_EDX_MTRR
1379	\| X86_CPUID_FEATURE_EDX_PGE
1380	\| X86_CPUID_FEATURE_EDX_MCA
1381	\| X86_CPUID_FEATURE_EDX_CMOV
1382	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
1383	\| X86_CPUID_FEATURE_EDX_PSE36
1384	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1385	\| X86_CPUID_FEATURE_EDX_CLFSH
1386	//\| RT_BIT_32(20) - not defined
1387	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
1388	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
1389	\| X86_CPUID_FEATURE_EDX_MMX
1390	\| X86_CPUID_FEATURE_EDX_FXSR
1391	\| X86_CPUID_FEATURE_EDX_SSE
1392	\| X86_CPUID_FEATURE_EDX_SSE2
1393	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1394	\| X86_CPUID_FEATURE_EDX_HTT
1395	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1396	//\| RT_BIT_32(30) - not defined
1397	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1398	;
1399	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
1400	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
1401	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
1402	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1403	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
1404	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1405	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
1406	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
1407	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1408	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1409	\| X86_CPUID_FEATURE_ECX_SSSE3
1410	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1411	\| PASSTHRU_FEATURE(pConfig->enmFma, pHstFeat->fFma, X86_CPUID_FEATURE_ECX_FMA)
1412	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
1413	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1414	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1415	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
1416	\| PASSTHRU_FEATURE_NOT_IEM(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
1417	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
1418	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
1419	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
1420	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
1421	\| PASSTHRU_FEATURE(pConfig->enmMovBe, pHstFeat->fMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
1422	\| PASSTHRU_FEATURE(pConfig->enmPopCnt, pHstFeat->fPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
1423	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
1424	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
1425	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
1426	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
1427	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
1428	\| PASSTHRU_FEATURE(pConfig->enmF16c, pHstFeat->fF16c, X86_CPUID_FEATURE_ECX_F16C)
1429	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
1430	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
1431	;
1432
1433	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1434	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1435	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
1436	{
1437	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
1438	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
1439	}
1440
1441	if (pCpum->u8PortableCpuIdLevel > 0)
1442	{
1443	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1444	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1445	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
1446	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
1447	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
1448	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
1449	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
1450	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
1451	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
1452	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
1453	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
1454	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
1455	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
1456	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
1457	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
1458	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1459	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1460	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1461	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1462	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1463
1464	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP ///??
1465	\| X86_CPUID_FEATURE_EDX_PSN
1466	\| X86_CPUID_FEATURE_EDX_DS
1467	\| X86_CPUID_FEATURE_EDX_ACPI
1468	\| X86_CPUID_FEATURE_EDX_SS
1469	\| X86_CPUID_FEATURE_EDX_TM
1470	\| X86_CPUID_FEATURE_EDX_PBE
1471	)));
1472	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
1473	\| X86_CPUID_FEATURE_ECX_CPLDS
1474	\| X86_CPUID_FEATURE_ECX_AES
1475	\| X86_CPUID_FEATURE_ECX_VMX
1476	\| X86_CPUID_FEATURE_ECX_SMX
1477	\| X86_CPUID_FEATURE_ECX_EST
1478	\| X86_CPUID_FEATURE_ECX_TM2
1479	\| X86_CPUID_FEATURE_ECX_CNTXID
1480	\| X86_CPUID_FEATURE_ECX_FMA
1481	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1482	\| X86_CPUID_FEATURE_ECX_PDCM
1483	\| X86_CPUID_FEATURE_ECX_DCA
1484	\| X86_CPUID_FEATURE_ECX_OSXSAVE
1485	)));
1486	}
1487
1488	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
1489	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
1490
1491	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
1492	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
1493	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
1494	*/
1495	#ifdef VBOX_WITH_MULTI_CORE
1496	if (pVM->cCpus > 1)
1497	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
1498	#endif
1499	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
1500	{
1501	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
1502	core times the number of CPU cores per processor */
1503	#ifdef VBOX_WITH_MULTI_CORE
1504	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
1505	#else
1506	/* Single logical processor in a package. */
1507	pStdFeatureLeaf->uEbx \|= (1 << 16);
1508	#endif
1509	}
1510
1511	uint32_t uMicrocodeRev;
1512	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
1513	if (RT_SUCCESS(rc))
1514	{
1515	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
1516	}
1517	else
1518	{
1519	uMicrocodeRev = 0;
1520	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
1521	}
1522
1523	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
1524	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
1525	*/
1526	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
1527	/** @todo The following ASSUMES that Hygon uses the same version numbering
1528	* as AMD and that they shipped buggy firmware. */
1529	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
1530	&& uMicrocodeRev < 0x8001126
1531	&& !pConfig->fForceVme)
1532	{
1533	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
1534	LogRel(("CPUM: Zen VME workaround engaged\n"));
1535	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
1536	}
1537
1538	/* Force standard feature bits. */
1539	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
1540	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
1541	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
1542	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
1543	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
1544	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
1545	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1546	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
1547	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1548	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
1549	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
1550	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
1551	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1552	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
1553	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
1554	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
1555	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
1556	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
1557	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1558	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
1559	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
1560	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
1561
1562	pStdFeatureLeaf = NULL; /* Must refetch! */
1563
1564	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
1565	* AMD:
1566	* EAX: CPU model, family and stepping.
1567	*
1568	* ECX + EDX: Supported features. Only report features we can support.
1569	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1570	* options may require adjusting (i.e. stripping what was enabled).
1571	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
1572	*
1573	* EBX: Branding ID and package type (or reserved).
1574	*
1575	* Intel and probably most others:
1576	* EAX: 0
1577	* EBX: 0
1578	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
1579	*/
1580	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
1581	if (pExtFeatureLeaf)
1582	{
1583	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
1584
1585	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1586	\| X86_CPUID_AMD_FEATURE_EDX_VME
1587	\| X86_CPUID_AMD_FEATURE_EDX_DE
1588	\| X86_CPUID_AMD_FEATURE_EDX_PSE
1589	\| X86_CPUID_AMD_FEATURE_EDX_TSC
1590	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1591	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
1592	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1593	\| X86_CPUID_AMD_FEATURE_EDX_CX8
1594	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1595	//\| RT_BIT_32(10) - reserved
1596	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1597	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
1598	\| X86_CPUID_AMD_FEATURE_EDX_PGE
1599	\| X86_CPUID_AMD_FEATURE_EDX_MCA
1600	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
1601	\| X86_CPUID_AMD_FEATURE_EDX_PAT
1602	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
1603	//\| RT_BIT_32(18) - reserved
1604	//\| RT_BIT_32(19) - reserved
1605	\| X86_CPUID_EXT_FEATURE_EDX_NX
1606	//\| RT_BIT_32(21) - reserved
1607	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
1608	\| X86_CPUID_AMD_FEATURE_EDX_MMX
1609	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
1610	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
1611	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1612	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1613	//\| RT_BIT_32(28) - reserved
1614	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1615	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1616	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
1617	;
1618	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1619	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
1620	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
1621	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1622	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
1623	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1624	\| PASSTHRU_FEATURE(pConfig->enmAbm, pHstFeat->fAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
1625	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
1626	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
1627	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1628	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1629	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
1630	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
1631	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1632	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
1633	//\| RT_BIT_32(14) - reserved
1634	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
1635	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
1636	//\| RT_BIT_32(17) - reserved
1637	//\| RT_BIT_32(18) - reserved
1638	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
1639	//\| RT_BIT_32(20) - reserved
1640	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
1641	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
1642	//\| RT_BIT_32(23) - reserved
1643	//\| RT_BIT_32(24) - reserved
1644	//\| RT_BIT_32(25) - reserved
1645	//\| RT_BIT_32(26) - reserved
1646	//\| RT_BIT_32(27) - reserved
1647	//\| RT_BIT_32(28) - reserved
1648	//\| RT_BIT_32(29) - reserved
1649	//\| RT_BIT_32(30) - reserved
1650	//\| RT_BIT_32(31) - reserved
1651	;
1652	#ifdef VBOX_WITH_MULTI_CORE
1653	if ( pVM->cCpus > 1
1654	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
1655	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
1656	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
1657	#endif
1658
1659	if (pCpum->u8PortableCpuIdLevel > 0)
1660	{
1661	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1662	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
1663	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
1664	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
1665	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
1666	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
1667	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
1668	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
1669	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
1670	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
1671	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1672	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1673	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1674	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1675	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1676	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1677
1678	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
1679	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1680	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1681	\| X86_CPUID_AMD_FEATURE_ECX_IBS
1682	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1683	\| X86_CPUID_AMD_FEATURE_ECX_WDT
1684	\| X86_CPUID_AMD_FEATURE_ECX_LWP
1685	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
1686	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
1687	\| UINT32_C(0xff964000)
1688	)));
1689	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1690	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1691	\| RT_BIT(18)
1692	\| RT_BIT(19)
1693	\| RT_BIT(21)
1694	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1695	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1696	\| RT_BIT(28)
1697	)));
1698	}
1699
1700	/* Force extended feature bits. */
1701	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
1702	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
1703	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
1704	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
1705	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
1706	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
1707	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
1708	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
1709	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1710	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
1711	}
1712	pExtFeatureLeaf = NULL; /* Must refetch! */
1713
1714
1715	/* Cpuid 2:
1716	* Intel: (Nondeterministic) Cache and TLB information
1717	* AMD: Reserved
1718	* VIA: Reserved
1719	* Safe to expose.
1720	*/
1721	uint32_t uSubLeaf = 0;
1722	PCPUMCPUIDLEAF pCurLeaf;
1723	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
1724	{
1725	if ((pCurLeaf->uEax & 0xff) > 1)
1726	{
1727	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1728	pCurLeaf->uEax &= UINT32_C(0xffffff01);
1729	}
1730	uSubLeaf++;
1731	}
1732
1733	/* Cpuid 3:
1734	* Intel: EAX, EBX - reserved (transmeta uses these)
1735	* ECX, EDX - Processor Serial Number if available, otherwise reserved
1736	* AMD: Reserved
1737	* VIA: Reserved
1738	* Safe to expose
1739	*/
1740	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1741	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
1742	{
1743	uSubLeaf = 0;
1744	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
1745	{
1746	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1747	if (pCpum->u8PortableCpuIdLevel > 0)
1748	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1749	uSubLeaf++;
1750	}
1751	}
1752
1753	/* Cpuid 4 + ECX:
1754	* Intel: Deterministic Cache Parameters Leaf.
1755	* AMD: Reserved
1756	* VIA: Reserved
1757	* Safe to expose, except for EAX:
1758	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1759	* Bits 31-26: Maximum number of processor cores in this physical package**
1760	* Note: These SMP values are constant regardless of ECX
1761	*/
1762	uSubLeaf = 0;
1763	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
1764	{
1765	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
1766	#ifdef VBOX_WITH_MULTI_CORE
1767	if ( pVM->cCpus > 1
1768	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1769	{
1770	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1771	/* One logical processor with possibly multiple cores. */
1772	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1773	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
1774	}
1775	#endif
1776	uSubLeaf++;
1777	}
1778
1779	/* Cpuid 5: Monitor/mwait Leaf
1780	* Intel: ECX, EDX - reserved
1781	* EAX, EBX - Smallest and largest monitor line size
1782	* AMD: EDX - reserved
1783	* EAX, EBX - Smallest and largest monitor line size
1784	* ECX - extensions (ignored for now)
1785	* VIA: Reserved
1786	* Safe to expose
1787	*/
1788	uSubLeaf = 0;
1789	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
1790	{
1791	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1792	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1793	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1794
1795	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1796	if (pConfig->enmMWaitExtensions)
1797	{
1798	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1799	/** @todo for now we just expose host's MWAIT C-states, although conceptually
1800	it shall be part of our power management virtualization model */
1801	#if 0
1802	/* MWAIT sub C-states */
1803	pCurLeaf->uEdx =
1804	(0 << 0) /* 0 in C0 */ \|
1805	(2 << 4) /* 2 in C1 */ \|
1806	(2 << 8) /* 2 in C2 */ \|
1807	(2 << 12) /* 2 in C3 */ \|
1808	(0 << 16) /* 0 in C4 */
1809	;
1810	#endif
1811	}
1812	else
1813	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1814	uSubLeaf++;
1815	}
1816
1817	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
1818	* Intel: Various thermal and power management related stuff.
1819	* AMD: EBX, EDX - reserved.
1820	* EAX - Bit two is ARAT, indicating that APIC timers run at a constant
1821	* rate regardless of processor P-states. Same as Intel.
1822	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
1823	* present. Same as Intel.
1824	* VIA: ??
1825	*
1826	* We clear everything except for the ARAT bit which is important for Windows 11.
1827	*/
1828	uSubLeaf = 0;
1829	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 6, uSubLeaf)) != NULL)
1830	{
1831	pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1832	pCurLeaf->uEax &= 0
1833	\| X86_CPUID_POWER_EAX_ARAT
1834	;
1835
1836	/* Since we emulate the APIC timers, we can normally set the ARAT bit
1837	* regardless of whether the host CPU sets it or not. Intel sets the ARAT
1838	* bit circa since the Westmere generation, AMD probably only since Zen.
1839	* See @bugref{10567}.
1840	*/
1841	if (pConfig->fInvariantApic)
1842	pCurLeaf->uEax \|= X86_CPUID_POWER_EAX_ARAT;
1843
1844	uSubLeaf++;
1845	}
1846
1847	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
1848	* EAX: Number of sub leaves.
1849	* EBX+ECX+EDX: Feature flags
1850	*
1851	* We only have documentation for one sub-leaf, so clear all other (no need
1852	* to remove them as such, just set them to zero).
1853	*
1854	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1855	* options may require adjusting (i.e. stripping what was enabled).
1856	*/
1857	uSubLeaf = 0;
1858	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
1859	{
1860	switch (uSubLeaf)
1861	{
1862	case 0:
1863	{
1864	pCurLeaf->uEax = RT_MIN(pCurLeaf->uEax, 2); /* Max ECX input is 2. */
1865	pCurLeaf->uEbx &= 0
1866	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
1867	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
1868	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
1869	\| X86_CPUID_STEXT_FEATURE_EBX_BMI1
1870	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
1871	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
1872	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
1873	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
1874	\| X86_CPUID_STEXT_FEATURE_EBX_BMI2
1875	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
1876	\| PASSTHRU_FEATURE_NOT_IEM(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
1877	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
1878	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
1879	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
1880	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
1881	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
1882	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
1883	//\| RT_BIT(17) - reserved
1884	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
1885	\| PASSTHRU_FEATURE(pConfig->enmAdx, pHstFeat->fAdx, X86_CPUID_STEXT_FEATURE_EBX_ADX)
1886	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
1887	//\| RT_BIT(21) - reserved
1888	//\| RT_BIT(22) - reserved
1889	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
1890	//\| RT_BIT(24) - reserved
1891	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
1892	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
1893	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
1894	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
1895	\| PASSTHRU_FEATURE(pConfig->enmSha, pHstFeat->fSha, X86_CPUID_STEXT_FEATURE_EBX_SHA)
1896	//\| RT_BIT(30) - reserved
1897	//\| RT_BIT(31) - reserved
1898	;
1899	pCurLeaf->uEcx &= 0
1900	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
1901	;
1902	pCurLeaf->uEdx &= 0
1903	//\| X86_CPUID_STEXT_FEATURE_EDX_SRBDS_CTRL RT_BIT(9)
1904	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
1905	//\| X86_CPUID_STEXT_FEATURE_EDX_TSX_FORCE_ABORT RT_BIT_32(11)
1906	//\| X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT(20)
1907	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
1908	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
1909	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
1910	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
1911	//\| X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
1912	//\| X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
1913	;
1914
1915	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1916	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1917	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
1918	{
1919	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1920	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
1921	}
1922
1923	if (pCpum->u8PortableCpuIdLevel > 0)
1924	{
1925	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
1926	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
1927	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
1928	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
1929	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1930	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
1931	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1932	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
1933	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, ADX, X86_CPUID_STEXT_FEATURE_EBX_ADX, pConfig->enmAdx);
1934	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
1935	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
1936	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
1937	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
1938	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
1939	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA, pConfig->enmSha);
1940	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
1941	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
1942	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
1943	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
1944	}
1945
1946	/* Dependencies. */
1947	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
1948	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1949
1950	/* Force standard feature bits. */
1951	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
1952	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
1953	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1954	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
1955	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
1956	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
1957	if (pConfig->enmAdx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1958	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_ADX;
1959	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1960	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
1961	if (pConfig->enmSha == CPUMISAEXTCFG_ENABLED_ALWAYS)
1962	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_SHA;
1963	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
1964	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1965	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1966	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
1967	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
1968	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1969	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1970	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
1971	break;
1972	}
1973
1974	case 2:
1975	{
1976	pCurLeaf->uEax = 0;
1977	pCurLeaf->uEbx = 0;
1978	pCurLeaf->uEcx = 0;
1979	pCurLeaf->uEdx &= 0
1980	//\| X86_CPUID_STEXT_FEATURE_2_EDX_PSFD RT_BIT_32(0)
1981	//\| X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL RT_BIT_32(1)
1982	//\| X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL RT_BIT_32(2)
1983	//\| X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U RT_BIT_32(3)
1984	//\| X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL RT_BIT_32(4)
1985	\| PASSTHRU_FEATURE(pConfig->enmMcdtNo, pHstFeat->fMcdtNo, X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO)
1986	//\| X86_CPUID_STEXT_FEATURE_2_EDX_UC_LOCK_DIS RT_BIT_32(6)
1987	//\| Bit 7 - MONITOR_MITG_NO - No need for MONITOR/UMONITOR power mitigrations. */
1988	\| PASSTHRU_FEATURE(pConfig->enmMonitorMitgNo, pHstFeat->fMonitorMitgNo, X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO)
1989	;
1990
1991	/* Force standard feature bits. */
1992	if (pConfig->enmMcdtNo == CPUMISAEXTCFG_ENABLED_ALWAYS)
1993	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO;
1994	if (pConfig->enmMonitorMitgNo == CPUMISAEXTCFG_ENABLED_ALWAYS)
1995	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO;
1996	break;
1997	}
1998
1999	default:
2000	/* Invalid index, all values are zero. */
2001	pCurLeaf->uEax = 0;
2002	pCurLeaf->uEbx = 0;
2003	pCurLeaf->uEcx = 0;
2004	pCurLeaf->uEdx = 0;
2005	break;
2006	}
2007	uSubLeaf++;
2008	}
2009
2010	/* Cpuid 8: Marked as reserved by Intel and AMD.
2011	* We zero this since we don't know what it may have been used for.
2012	*/
2013	cpumR3CpuIdZeroLeaf(pCpum, 8);
2014
2015	/* Cpuid 9: Direct Cache Access (DCA) Parameters
2016	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2017	* EBX, ECX, EDX - reserved.
2018	* AMD: Reserved
2019	* VIA: ??
2020	*
2021	* We zero this.
2022	*/
2023	cpumR3CpuIdZeroLeaf(pCpum, 9);
2024
2025	/* Cpuid 0xa: Architectural Performance Monitor Features
2026	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2027	* EBX, ECX, EDX - reserved.
2028	* AMD: Reserved
2029	* VIA: ??
2030	*
2031	* We zero this, for now at least.
2032	*/
2033	cpumR3CpuIdZeroLeaf(pCpum, 10);
2034
2035	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
2036	* Intel: EAX - APCI ID shift right for next level.
2037	* EBX - Factory configured cores/threads at this level.
2038	* ECX - Level number (same as input) and level type (1,2,0).
2039	* EDX - Extended initial APIC ID.
2040	* AMD: Reserved
2041	* VIA: ??
2042	*/
2043	uSubLeaf = 0;
2044	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
2045	{
2046	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2047	{
2048	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
2049	if (bLevelType == 1)
2050	{
2051	/* Thread level - we don't do threads at the moment. */
2052	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
2053	pCurLeaf->uEbx = 1;
2054	}
2055	else if (bLevelType == 2)
2056	{
2057	/* Core level. */
2058	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
2059	#ifdef VBOX_WITH_MULTI_CORE
2060	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
2061	pCurLeaf->uEax++;
2062	#endif
2063	pCurLeaf->uEbx = pVM->cCpus;
2064	}
2065	else
2066	{
2067	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
2068	pCurLeaf->uEax = 0;
2069	pCurLeaf->uEbx = 0;
2070	pCurLeaf->uEcx = 0;
2071	}
2072	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
2073	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
2074	}
2075	else
2076	{
2077	pCurLeaf->uEax = 0;
2078	pCurLeaf->uEbx = 0;
2079	pCurLeaf->uEcx = 0;
2080	pCurLeaf->uEdx = 0;
2081	}
2082	uSubLeaf++;
2083	}
2084
2085	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
2086	* We zero this since we don't know what it may have been used for.
2087	*/
2088	cpumR3CpuIdZeroLeaf(pCpum, 12);
2089
2090	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
2091	* ECX=0: EAX - Valid bits in XCR0[31:0].
2092	* EBX - Maximum state size as per current XCR0 value.
2093	* ECX - Maximum state size for all supported features.
2094	* EDX - Valid bits in XCR0[63:32].
2095	* ECX=1: EAX - Various X-features.
2096	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
2097	* ECX - Valid bits in IA32_XSS[31:0].
2098	* EDX - Valid bits in IA32_XSS[63:32].
2099	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2100	* if the bit invalid all four registers are set to zero.
2101	* EAX - The state size for this feature.
2102	* EBX - The state byte offset of this feature.
2103	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2104	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
2105	*
2106	* Clear them all as we don't currently implement extended CPU state.
2107	*/
2108	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
2109	uint64_t fGuestXcr0Mask = 0;
2110	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2111	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
2112	{
2113	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
2114	if (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX)
2115	fGuestXcr0Mask \|= XSAVE_C_YMM;
2116	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
2117	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
2118	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
2119	fGuestXcr0Mask &= pCpum->fXStateHostMask;
2120
2121	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
2122	}
2123	pStdFeatureLeaf = NULL;
2124	pCpum->fXStateGuestMask = fGuestXcr0Mask;
2125
2126	/* Work the sub-leaves. */
2127	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
2128	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
2129	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
2130	{
2131	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
2132	if (pCurLeaf)
2133	{
2134	if (fGuestXcr0Mask)
2135	{
2136	switch (uSubLeaf)
2137	{
2138	case 0:
2139	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
2140	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
2141	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2142	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
2143	VERR_CPUM_IPE_1);
2144	cbXSaveMaxActual = pCurLeaf->uEcx;
2145	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
2146	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
2147	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
2148	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
2149	VERR_CPUM_IPE_2);
2150	continue;
2151	case 1:
2152	pCurLeaf->uEax &= 0;
2153	pCurLeaf->uEcx &= 0;
2154	pCurLeaf->uEdx &= 0;
2155	/** @todo what about checking ebx? */
2156	continue;
2157	default:
2158	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
2159	{
2160	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
2161	&& pCurLeaf->uEax > 0
2162	&& pCurLeaf->uEbx < cbXSaveMaxActual
2163	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2164	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
2165	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
2166	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
2167	VERR_CPUM_IPE_2);
2168	AssertLogRel(!(pCurLeaf->uEcx & 1));
2169	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
2170	pCurLeaf->uEdx = 0; /* it's reserved... */
2171	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
2172	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
2173	continue;
2174	}
2175	break;
2176	}
2177	}
2178
2179	/* Clear the leaf. */
2180	pCurLeaf->uEax = 0;
2181	pCurLeaf->uEbx = 0;
2182	pCurLeaf->uEcx = 0;
2183	pCurLeaf->uEdx = 0;
2184	}
2185	}
2186
2187	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
2188	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
2189	{
2190	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
2191	if (pCurLeaf)
2192	{
2193	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
2194	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
2195	pCurLeaf->uEbx = cbXSaveMaxReport;
2196	pCurLeaf->uEcx = cbXSaveMaxReport;
2197	}
2198	}
2199
2200	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
2201	* We zero this since we don't know what it may have been used for.
2202	*/
2203	cpumR3CpuIdZeroLeaf(pCpum, 14);
2204
2205	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
2206	* also known as Intel Resource Director Technology (RDT) Monitoring
2207	* We zero this as we don't currently virtualize PQM.
2208	*/
2209	cpumR3CpuIdZeroLeaf(pCpum, 15);
2210
2211	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
2212	* also known as Intel Resource Director Technology (RDT) Allocation
2213	* We zero this as we don't currently virtualize PQE.
2214	*/
2215	cpumR3CpuIdZeroLeaf(pCpum, 16);
2216
2217	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
2218	* We zero this since we don't know what it may have been used for.
2219	*/
2220	cpumR3CpuIdZeroLeaf(pCpum, 17);
2221
2222	/* Cpuid 0x12 + ECX: SGX resource enumeration.
2223	* We zero this as we don't currently virtualize this.
2224	*/
2225	cpumR3CpuIdZeroLeaf(pCpum, 18);
2226
2227	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
2228	* We zero this since we don't know what it may have been used for.
2229	*/
2230	cpumR3CpuIdZeroLeaf(pCpum, 19);
2231
2232	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2233	* We zero this as we don't currently virtualize this.
2234	*/
2235	cpumR3CpuIdZeroLeaf(pCpum, 20);
2236
2237	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2238	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2239	* EAX - denominator (unsigned).
2240	* EBX - numerator (unsigned).
2241	* ECX, EDX - reserved.
2242	* AMD: Reserved / undefined / not implemented.
2243	* VIA: Reserved / undefined / not implemented.
2244	* We zero this as we don't currently virtualize this.
2245	*/
2246	cpumR3CpuIdZeroLeaf(pCpum, 21);
2247
2248	/* Cpuid 0x16: Processor frequency info
2249	* Intel: EAX - Core base frequency in MHz.
2250	* EBX - Core maximum frequency in MHz.
2251	* ECX - Bus (reference) frequency in MHz.
2252	* EDX - Reserved.
2253	* AMD: Reserved / undefined / not implemented.
2254	* VIA: Reserved / undefined / not implemented.
2255	* We zero this as we don't currently virtualize this.
2256	*/
2257	cpumR3CpuIdZeroLeaf(pCpum, 22);
2258
2259	/* Cpuid 0x17..0x10000000: Unknown.
2260	* We don't know these and what they mean, so remove them. */
2261	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2262	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2263
2264
2265	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2266	* We remove all these as we're a hypervisor and must provide our own.
2267	*/
2268	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2269	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2270
2271
2272	/* Cpuid 0x80000000 is harmless. */
2273
2274	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2275
2276	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
2277
2278	/* Cpuid 0x80000005 & 0x80000006 contain information about L1, L2 & L3 cache and TLB identifiers.
2279	* Safe to pass on to the guest.
2280	*
2281	* AMD: 0x80000005 L1 cache information
2282	* 0x80000006 L2/L3 cache information
2283	* Intel: 0x80000005 reserved
2284	* 0x80000006 L2 cache information
2285	* VIA: 0x80000005 TLB and L1 cache information
2286	* 0x80000006 L2 cache information
2287	*/
2288
2289	uSubLeaf = 0;
2290	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000006), uSubLeaf)) != NULL)
2291	{
2292	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2293	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2294	{
2295	/*
2296	* Some AMD CPUs (e.g. Ryzen 7940HS) report zero L3 cache line size here and refer
2297	* to CPUID Fn8000_001D. This triggers division by zero in Linux if the
2298	* TopologyExtensions aka TOPOEXT bit in Fn8000_0001_ECX is not set, or if the kernel
2299	* is old enough (e.g. Linux 3.13) that it does not know about the topology extension
2300	* CPUID leaves.
2301	* We put a non-zero value in the cache line size here, if possible the actual value
2302	* gleaned from Fn8000_001D, or worst case a made-up valid number.
2303	*/
2304	PCPUMCPUIDLEAF pTopoLeaf;
2305	uint32_t uTopoSubLeaf;
2306	uint32_t uCacheLineSize;
2307
2308	if ((pCurLeaf->uEdx & 0xff) == 0)
2309	{
2310	uTopoSubLeaf = 0;
2311
2312	uCacheLineSize = 64; /* Use 64-byte line size as a fallback. */
2313
2314	/* Find L3 cache information. Have to check the cache level in EAX. */
2315	while ((pTopoLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uTopoSubLeaf)) != NULL)
2316	{
2317	if (((pTopoLeaf->uEax >> 5) & 0x07) == 3) {
2318	uCacheLineSize = (pTopoLeaf->uEbx & 0xfff) + 1;
2319	/* Fn8000_0006 can't report power of two line sizes greater than 128. */
2320	if (uCacheLineSize > 128)
2321	uCacheLineSize = 128;
2322
2323	break;
2324	}
2325	uTopoSubLeaf++;
2326	}
2327
2328	Assert(uCacheLineSize < 256);
2329	pCurLeaf->uEdx \|= uCacheLineSize;
2330	LogRel(("CPUM: AMD L3 cache line size in CPUID leaf 0x80000006 was zero, adjusting to %u\n", uCacheLineSize));
2331	}
2332	}
2333	uSubLeaf++;
2334	}
2335
2336	/* Cpuid 0x80000007: Advanced Power Management Information.
2337	* AMD: EAX: Processor feedback capabilities.
2338	* EBX: RAS capabilites.
2339	* ECX: Advanced power monitoring interface.
2340	* EDX: Enhanced power management capabilities.
2341	* Intel: EAX, EBX, ECX - reserved.
2342	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
2343	* VIA: Reserved
2344	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
2345	*/
2346	uSubLeaf = 0;
2347	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
2348	{
2349	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
2350	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2351	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2352	{
2353	/*
2354	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
2355	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
2356	* bit is now configurable.
2357	*/
2358	pCurLeaf->uEdx &= 0
2359	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
2360	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
2361	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
2362	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
2363	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
2364	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
2365	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
2366	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
2367	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
2368	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
2369	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
2370	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
2371	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
2372	\| 0;
2373	}
2374	else
2375	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2376	if (!pConfig->fInvariantTsc)
2377	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2378	uSubLeaf++;
2379	}
2380
2381	/* Cpuid 0x80000008:
2382	* AMD: EAX: Long Mode Size Identifiers
2383	* EBX: Extended Feature Identifiers
2384	* ECX: Number of cores + APICIdCoreIdSize
2385	* EDX: RDPRU Register Identifier Range
2386	* Intel: EAX: Virtual/Physical address Size
2387	* EBX, ECX, EDX - reserved
2388	* VIA: EAX: Virtual/Physical address Size
2389	* EBX, ECX, EDX - reserved
2390	*
2391	* We only expose the virtual+pysical address size to the guest atm.
2392	* On AMD we set the core count, but not the apic id stuff as we're
2393	* currently not doing the apic id assignments in a compatible manner.
2394	*/
2395	uSubLeaf = 0;
2396	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
2397	{
2398	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
2399	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2400	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2401	{
2402	/* Expose XSaveErPtr aka RstrFpErrPtrs to guest. */
2403	pCurLeaf->uEbx &= X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR; /* reserved - [12] == IBPB */
2404	}
2405	else
2406	pCurLeaf->uEbx = 0; /* reserved */
2407
2408	pCurLeaf->uEdx = 0; /* reserved */
2409
2410	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
2411	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
2412	pCurLeaf->uEcx = 0;
2413	#ifdef VBOX_WITH_MULTI_CORE
2414	if ( pVM->cCpus > 1
2415	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2416	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
2417	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
2418	#endif
2419	uSubLeaf++;
2420	}
2421
2422	/* Cpuid 0x80000009: Reserved
2423	* We zero this since we don't know what it may have been used for.
2424	*/
2425	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
2426
2427	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
2428	* AMD: EAX - SVM revision.
2429	* EBX - Number of ASIDs.
2430	* ECX - Reserved.
2431	* EDX - SVM Feature identification.
2432	*/
2433	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2434	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2435	{
2436	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2437	if ( pExtFeatureLeaf
2438	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
2439	{
2440	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
2441	if (pSvmFeatureLeaf)
2442	{
2443	pSvmFeatureLeaf->uEax = 0x1;
2444	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
2445	pSvmFeatureLeaf->uEcx = 0;
2446	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
2447	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
2448	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2449	}
2450	else
2451	{
2452	/* Should never happen. */
2453	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
2454	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2455	}
2456	}
2457	else
2458	{
2459	/* If SVM is not supported, this is reserved, zero out. */
2460	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2461	}
2462	}
2463	else
2464	{
2465	/* Cpuid 0x8000000a: Reserved on Intel.
2466	* We zero this since we don't know what it may have been used for.
2467	*/
2468	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2469	}
2470
2471	/* Cpuid 0x8000000b thru 0x80000018: Reserved
2472	* We clear these as we don't know what purpose they might have. */
2473	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
2474	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
2475
2476	/* Cpuid 0x80000019: TLB configuration
2477	* Seems to be harmless, pass them thru as is. */
2478
2479	/* Cpuid 0x8000001a: Peformance optimization identifiers.
2480	* Strip anything we don't know what is or addresses feature we don't implement. */
2481	uSubLeaf = 0;
2482	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
2483	{
2484	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
2485	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
2486	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
2487	;
2488	pCurLeaf->uEbx = 0; /* reserved */
2489	pCurLeaf->uEcx = 0; /* reserved */
2490	pCurLeaf->uEdx = 0; /* reserved */
2491	uSubLeaf++;
2492	}
2493
2494	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
2495	* Clear this as we don't currently virtualize this feature. */
2496	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
2497
2498	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
2499	* Clear this as we don't currently virtualize this feature. */
2500	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
2501
2502	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
2503	* We need to sanitize the cores per cache (EAX[25:14]).
2504	*
2505	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
2506	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
2507	* slightly different meaning.
2508	*/
2509	uSubLeaf = 0;
2510	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
2511	{
2512	#ifdef VBOX_WITH_MULTI_CORE
2513	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
2514	if (cCores > pVM->cCpus)
2515	cCores = pVM->cCpus;
2516	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2517	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
2518	#else
2519	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2520	#endif
2521	uSubLeaf++;
2522	}
2523
2524	/* Cpuid 0x8000001e: Get APIC / unit / node information.
2525	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
2526	* setup, we have one compute unit with all the cores in it. Single node.
2527	*/
2528	uSubLeaf = 0;
2529	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
2530	{
2531	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
2532	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2533	{
2534	#ifdef VBOX_WITH_MULTI_CORE
2535	pCurLeaf->uEbx = pVM->cCpus < 0x100
2536	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
2537	#else
2538	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
2539	#endif
2540	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
2541	}
2542	else
2543	{
2544	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
2545	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
2546	pCurLeaf->uEbx = 0; /* Reserved. */
2547	pCurLeaf->uEcx = 0; /* Reserved. */
2548	}
2549	pCurLeaf->uEdx = 0; /* Reserved. */
2550	uSubLeaf++;
2551	}
2552
2553	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
2554	* We don't know these and what they mean, so remove them. */
2555	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2556	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
2557
2558	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
2559	* Just pass it thru for now. */
2560
2561	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
2562	* Just pass it thru for now. */
2563
2564	/* Cpuid 0xc0000000: Centaur stuff.
2565	* Harmless, pass it thru. */
2566
2567	/* Cpuid 0xc0000001: Centaur features.
2568	* VIA: EAX - Family, model, stepping.
2569	* EDX - Centaur extended feature flags. Nothing interesting, except may
2570	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
2571	* EBX, ECX - reserved.
2572	* We keep EAX but strips the rest.
2573	*/
2574	uSubLeaf = 0;
2575	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
2576	{
2577	pCurLeaf->uEbx = 0;
2578	pCurLeaf->uEcx = 0;
2579	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
2580	uSubLeaf++;
2581	}
2582
2583	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
2584	* We only have fixed stale values, but should be harmless. */
2585
2586	/* Cpuid 0xc0000003: Reserved.
2587	* We zero this since we don't know what it may have been used for.
2588	*/
2589	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
2590
2591	/* Cpuid 0xc0000004: Centaur Performance Info.
2592	* We only have fixed stale values, but should be harmless. */
2593
2594
2595	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
2596	* We don't know these and what they mean, so remove them. */
2597	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2598	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
2599
2600	return VINF_SUCCESS;
2601	#undef PORTABLE_DISABLE_FEATURE_BIT
2602	#undef PORTABLE_CLEAR_BITS_WHEN
2603	}
2604
2605
2606	/**
2607	* Reads a value in /CPUM/IsaExts/ node.
2608	*
2609	* @returns VBox status code (error message raised).
2610	* @param pVM The cross context VM structure. (For errors.)
2611	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2612	* @param pszValueName The value / extension name.
2613	* @param penmValue Where to return the choice.
2614	* @param enmDefault The default choice.
2615	*/
2616	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2617	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2618	{
2619	/*
2620	* Try integer encoding first.
2621	*/
2622	uint64_t uValue;
2623	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
2624	if (RT_SUCCESS(rc))
2625	switch (uValue)
2626	{
2627	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
2628	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
2629	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
2630	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
2631	default:
2632	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2633	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2634	pszValueName, uValue);
2635	}
2636	/*
2637	* If missing, use default.
2638	*/
2639	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
2640	*penmValue = enmDefault;
2641	else
2642	{
2643	if (rc == VERR_CFGM_NOT_INTEGER)
2644	{
2645	/*
2646	* Not an integer, try read it as a string.
2647	*/
2648	char szValue[32];
2649	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
2650	if (RT_SUCCESS(rc))
2651	{
2652	RTStrToLower(szValue);
2653	size_t cchValue = strlen(szValue);
2654	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
2655	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
2656	*penmValue = CPUMISAEXTCFG_DISABLED;
2657	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
2658	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
2659	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
2660	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
2661	else if (EQ("portable"))
2662	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
2663	else if (EQ("default") \|\| EQ("def"))
2664	*penmValue = enmDefault;
2665	else
2666	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2667	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2668	pszValueName, uValue);
2669	#undef EQ
2670	}
2671	}
2672	if (RT_FAILURE(rc))
2673	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
2674	}
2675	return VINF_SUCCESS;
2676	}
2677
2678
2679	/**
2680	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
2681	*
2682	* @returns VBox status code (error message raised).
2683	* @param pVM The cross context VM structure. (For errors.)
2684	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2685	* @param pszValueName The value / extension name.
2686	* @param penmValue Where to return the choice.
2687	* @param enmDefault The default choice.
2688	* @param fAllowed Allowed choice. Applied both to the result and to
2689	* the default value.
2690	*/
2691	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2692	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
2693	{
2694	int rc;
2695	if (fAllowed)
2696	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2697	else
2698	{
2699	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
2700	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
2701	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
2702	*penmValue = CPUMISAEXTCFG_DISABLED;
2703	}
2704	return rc;
2705	}
2706
2707
2708	/**
2709	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
2710	*
2711	* @returns VBox status code (error message raised).
2712	* @param pVM The cross context VM structure. (For errors.)
2713	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2714	* @param pCpumCfg The /CPUM node (can be NULL).
2715	* @param pszValueName The value / extension name.
2716	* @param penmValue Where to return the choice.
2717	* @param enmDefault The default choice.
2718	*/
2719	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
2720	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2721	{
2722	if (CFGMR3Exists(pCpumCfg, pszValueName))
2723	{
2724	if (!CFGMR3Exists(pIsaExts, pszValueName))
2725	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
2726	else
2727	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
2728	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
2729	pszValueName, pszValueName);
2730
2731	bool fLegacy;
2732	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
2733	if (RT_SUCCESS(rc))
2734	{
2735	*penmValue = fLegacy;
2736	return VINF_SUCCESS;
2737	}
2738	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
2739	}
2740
2741	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2742	}
2743
2744
2745	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
2746	{
2747	int rc;
2748
2749	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
2750	* When non-zero CPUID features that could cause portability issues will be
2751	* stripped. The higher the value the more features gets stripped. Higher
2752	* values should only be used when older CPUs are involved since it may
2753	* harm performance and maybe also cause problems with specific guests. */
2754	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
2755	AssertLogRelRCReturn(rc, rc);
2756
2757	/** @cfgm{/CPUM/GuestCpuName, string}
2758	* The name of the CPU we're to emulate. The default is the host CPU.
2759	* Note! CPUs other than "host" one is currently unsupported. */
2760	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
2761	AssertLogRelRCReturn(rc, rc);
2762
2763	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
2764	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
2765	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
2766	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
2767	*/
2768	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
2769	AssertLogRelRCReturn(rc, rc);
2770
2771	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
2772	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
2773	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
2774	* 64-bit linux guests which assume the presence of AMD performance counters
2775	* that we do not virtualize.
2776	*/
2777	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
2778	AssertLogRelRCReturn(rc, rc);
2779
2780	/** @cfgm{/CPUM/InvariantApic, boolean, true}
2781	* Set the Always Running APIC Timer (ARAT) flag in lea if true; otherwise
2782	* pass through the host setting. The Windows 10/11 HAL won't use APIC timers
2783	* unless the ARAT bit is set. Note that both Intel and AMD set this bit.
2784	*/
2785	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantApic", &pConfig->fInvariantApic, true);
2786	AssertLogRelRCReturn(rc, rc);
2787
2788	/** @cfgm{/CPUM/ForceVme, boolean, false}
2789	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
2790	* By default the flag is passed thru as is from the host CPU, except
2791	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
2792	* guests and DOS boxes in general.
2793	*/
2794	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
2795	AssertLogRelRCReturn(rc, rc);
2796
2797	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
2798	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
2799	* probably going to be a temporary hack, so don't depend on this.
2800	* The 1st byte of the value is the stepping, the 2nd byte value is the model
2801	* number and the 3rd byte value is the family, and the 4th value must be zero.
2802	*/
2803	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
2804	AssertLogRelRCReturn(rc, rc);
2805
2806	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
2807	* The last standard leaf to keep. The actual last value that is stored in EAX
2808	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
2809	* removed. (This works independently of and differently from NT4LeafLimit.)
2810	* The default is usually set to what we're able to reasonably sanitize.
2811	*/
2812	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
2813	AssertLogRelRCReturn(rc, rc);
2814
2815	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
2816	* The last extended leaf to keep. The actual last value that is stored in EAX
2817	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
2818	* leaf are removed. The default is set to what we're able to sanitize.
2819	*/
2820	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
2821	AssertLogRelRCReturn(rc, rc);
2822
2823	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
2824	* The last extended leaf to keep. The actual last value that is stored in EAX
2825	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
2826	* leaf are removed. The default is set to what we're able to sanitize.
2827	*/
2828	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
2829	AssertLogRelRCReturn(rc, rc);
2830
2831	#ifdef RT_ARCH_AMD64 /** @todo next VT-x/AMD-V on non-AMD64 hosts */
2832	bool fQueryNestedHwvirt = false
2833	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2834	\|\| pVM->cpum.s.HostFeatures.s.enmCpuVendor == CPUMCPUVENDOR_AMD
2835	\|\| pVM->cpum.s.HostFeatures.s.enmCpuVendor == CPUMCPUVENDOR_HYGON
2836	#endif
2837	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2838	\|\| pVM->cpum.s.HostFeatures.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
2839	\|\| pVM->cpum.s.HostFeatures.s.enmCpuVendor == CPUMCPUVENDOR_VIA
2840	#endif
2841	;
2842	if (fQueryNestedHwvirt)
2843	{
2844	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
2845	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
2846	* The default is false, and when enabled requires a 64-bit CPU with support for
2847	* nested-paging and AMD-V or unrestricted guest mode.
2848	*/
2849	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
2850	AssertLogRelRCReturn(rc, rc);
2851	if (pConfig->fNestedHWVirt)
2852	{
2853	/** @todo Think about enabling this later with NEM/KVM. */
2854	if (VM_IS_NEM_ENABLED(pVM))
2855	{
2856	LogRel(("CPUM: Warning! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
2857	pConfig->fNestedHWVirt = false;
2858	}
2859	else if (!fNestedPagingAndFullGuestExec)
2860	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
2861	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
2862	}
2863	}
2864	#endif /** @todo */
2865
2866	/*
2867	* Instruction Set Architecture (ISA) Extensions.
2868	*/
2869	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
2870	if (pIsaExts)
2871	{
2872	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
2873	"CMPXCHG16B"
2874	"\|MONITOR"
2875	"\|MWaitExtensions"
2876	"\|SSE4.1"
2877	"\|SSE4.2"
2878	"\|XSAVE"
2879	"\|AVX"
2880	"\|AVX2"
2881	"\|AESNI"
2882	"\|PCLMUL"
2883	"\|POPCNT"
2884	"\|MOVBE"
2885	"\|RDRAND"
2886	"\|RDSEED"
2887	"\|ADX"
2888	"\|CLFLUSHOPT"
2889	"\|SHA"
2890	"\|FSGSBASE"
2891	"\|PCID"
2892	"\|INVPCID"
2893	"\|FlushCmdMsr"
2894	"\|MdsClear"
2895	"\|ArchCapMsr"
2896	"\|FMA"
2897	"\|F16C"
2898	"\|McdtNo"
2899	"\|MonitorMitgNo"
2900	"\|ABM"
2901	"\|SSE4A"
2902	"\|MISALNSSE"
2903	"\|3DNOWPRF"
2904	"\|AXMMX"
2905	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
2906	if (RT_FAILURE(rc))
2907	return rc;
2908	}
2909
2910	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
2911	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
2912	* hardware virtualization have it.
2913	*/
2914	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
2915	AssertLogRelRCReturn(rc, rc);
2916
2917	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
2918	* Expose MONITOR/MWAIT instructions to the guest.
2919	*/
2920	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
2921	AssertLogRelRCReturn(rc, rc);
2922
2923	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
2924	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
2925	* break on interrupt feature (bit 1).
2926	*/
2927	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
2928	AssertLogRelRCReturn(rc, rc);
2929
2930	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
2931	* Expose SSE4.1 to the guest if available.
2932	*/
2933	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
2934	AssertLogRelRCReturn(rc, rc);
2935
2936	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
2937	* Expose SSE4.2 to the guest if available.
2938	*/
2939	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
2940	AssertLogRelRCReturn(rc, rc);
2941
2942	#ifdef RT_ARCH_AMD64
2943	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.s.fXSaveRstor
2944	&& pVM->cpum.s.HostFeatures.s.fOpSysXSaveRstor
2945	&& ( VM_IS_NEM_ENABLED(pVM)
2946	? NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR
2947	: VM_IS_EXEC_ENGINE_IEM(pVM)
2948	? true
2949	: fNestedPagingAndFullGuestExec);
2950	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
2951	#else
2952	bool const fMayHaveXSave = true;
2953	uint64_t const fXStateHostMask = XSAVE_C_YMM \| XSAVE_C_SSE \| XSAVE_C_X87;
2954	#endif
2955
2956	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
2957	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
2958	* default is to only expose this to VMs with nested paging and AMD-V or
2959	* unrestricted guest execution mode. Not possible to force this one without
2960	* host support at the moment.
2961	*/
2962	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, true,
2963	fMayHaveXSave /fAllowed/);
2964	AssertLogRelRCReturn(rc, rc);
2965
2966	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
2967	* Expose the AVX instruction set extensions to the guest if available and
2968	* XSAVE is exposed too. For the time being the default is to only expose this
2969	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2970	*/
2971	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
2972	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2973	AssertLogRelRCReturn(rc, rc);
2974
2975	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
2976	* Expose the AVX2 instruction set extensions to the guest if available and
2977	* XSAVE is exposed too. For the time being the default is to only expose this
2978	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2979	*/
2980	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
2981	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2982	AssertLogRelRCReturn(rc, rc);
2983
2984	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
2985	* Whether to expose the AES instructions to the guest. For the time being the
2986	* default is to only do this for VMs with nested paging and AMD-V or
2987	* unrestricted guest mode.
2988	*/
2989	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
2990	AssertLogRelRCReturn(rc, rc);
2991
2992	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
2993	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
2994	* being the default is to only do this for VMs with nested paging and AMD-V or
2995	* unrestricted guest mode.
2996	*/
2997	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
2998	AssertLogRelRCReturn(rc, rc);
2999
3000	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, true}
3001	* Whether to expose the POPCNT instructions to the guest.
3002	*/
3003	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3004	AssertLogRelRCReturn(rc, rc);
3005
3006	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3007	* Whether to expose the MOVBE instructions to the guest. For the time
3008	* being the default is to only do this for VMs with nested paging and AMD-V or
3009	* unrestricted guest mode.
3010	*/
3011	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, true);
3012	AssertLogRelRCReturn(rc, rc);
3013
3014	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3015	* Whether to expose the RDRAND instructions to the guest. For the time being
3016	* the default is to only do this for VMs with nested paging and AMD-V or
3017	* unrestricted guest mode.
3018	*/
3019	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3020	AssertLogRelRCReturn(rc, rc);
3021
3022	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3023	* Whether to expose the RDSEED instructions to the guest. For the time being
3024	* the default is to only do this for VMs with nested paging and AMD-V or
3025	* unrestricted guest mode.
3026	*/
3027	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3028	AssertLogRelRCReturn(rc, rc);
3029
3030	/** @cfgm{/CPUM/IsaExts/ADX, isaextcfg, depends}
3031	* Whether to expose the ADX instructions to the guest. For the time being
3032	* the default is to only do this for VMs with nested paging and AMD-V or
3033	* unrestricted guest mode.
3034	*/
3035	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ADX", &pConfig->enmAdx, fNestedPagingAndFullGuestExec);
3036	AssertLogRelRCReturn(rc, rc);
3037
3038	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3039	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3040	* being the default is to only do this for VMs with nested paging and AMD-V or
3041	* unrestricted guest mode.
3042	*/
3043	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3044	AssertLogRelRCReturn(rc, rc);
3045
3046	/** @cfgm{/CPUM/IsaExts/SHA, isaextcfg, depends}
3047	* Whether to expose the SHA instructions to the guest. For the time being
3048	* the default is to only do this for VMs with nested paging and AMD-V or
3049	* unrestricted guest mode.
3050	*/
3051	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SHA", &pConfig->enmSha, fNestedPagingAndFullGuestExec);
3052	AssertLogRelRCReturn(rc, rc);
3053
3054	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
3055	* Whether to expose the read/write FSGSBASE instructions to the guest.
3056	*/
3057	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
3058	AssertLogRelRCReturn(rc, rc);
3059
3060	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
3061	* Whether to expose the PCID feature to the guest.
3062	*/
3063	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
3064	AssertLogRelRCReturn(rc, rc);
3065
3066	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
3067	* Whether to expose the INVPCID instruction to the guest.
3068	*/
3069	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
3070	AssertLogRelRCReturn(rc, rc);
3071
3072	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
3073	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
3074	*/
3075	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3076	AssertLogRelRCReturn(rc, rc);
3077
3078	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
3079	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
3080	* the guest. Requires FlushCmdMsr to be present too.
3081	*/
3082	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3083	AssertLogRelRCReturn(rc, rc);
3084
3085	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
3086	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
3087	*/
3088	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED_OR_NOT_AMD64);
3089	AssertLogRelRCReturn(rc, rc);
3090
3091	/** @cfgm{/CPUM/IsaExts/FMA, boolean, depends}
3092	* Expose the FMA instruction set extensions to the guest if available and
3093	* XSAVE is exposed too. For the time being the default is to only expose this
3094	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3095	*/
3096	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "FMA", &pConfig->enmFma, fNestedPagingAndFullGuestExec /* temporarily */,
3097	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3098	AssertLogRelRCReturn(rc, rc);
3099
3100	/** @cfgm{/CPUM/IsaExts/F16C, boolean, depends}
3101	* Expose the F16C instruction set extensions to the guest if available and
3102	* XSAVE is exposed too. For the time being the default is to only expose this
3103	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3104	*/
3105	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "F16C", &pConfig->enmF16c, fNestedPagingAndFullGuestExec /* temporarily */,
3106	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3107	AssertLogRelRCReturn(rc, rc);
3108
3109	/** @cfgm{/CPUM/IsaExts/McdtNo, isaextcfg, true}
3110	* Whether the CPU is not susceptible to the MXCSR configuration dependent
3111	* timing (MCDT) behaviour.
3112	*/
3113	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "McdtNo", &pConfig->enmMcdtNo, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3114	AssertLogRelRCReturn(rc, rc);
3115
3116	/** @cfgm{/CPUM/IsaExts/MonitorMitgNo, isaextcfg, true}
3117	* Whether the CPU is not susceptible MONITOR/UMONITOR internal table capacity
3118	* issues.
3119	*/
3120	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MonitorMitgNo", &pConfig->enmMonitorMitgNo, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3121	AssertLogRelRCReturn(rc, rc);
3122
3123
3124	/* AMD: */
3125
3126	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, true}
3127	* Whether to expose the AMD ABM instructions to the guest.
3128	*/
3129	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3130	AssertLogRelRCReturn(rc, rc);
3131
3132	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3133	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3134	* being the default is to only do this for VMs with nested paging and AMD-V or
3135	* unrestricted guest mode.
3136	*/
3137	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3138	AssertLogRelRCReturn(rc, rc);
3139
3140	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3141	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3142	* the time being the default is to only do this for VMs with nested paging and
3143	* AMD-V or unrestricted guest mode.
3144	*/
3145	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3146	AssertLogRelRCReturn(rc, rc);
3147
3148	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3149	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3150	* For the time being the default is to only do this for VMs with nested paging
3151	* and AMD-V or unrestricted guest mode.
3152	*/
3153	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3154	AssertLogRelRCReturn(rc, rc);
3155
3156	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3157	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3158	* the default is to only do this for VMs with nested paging and AMD-V or
3159	* unrestricted guest mode.
3160	*/
3161	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3162	AssertLogRelRCReturn(rc, rc);
3163
3164	return VINF_SUCCESS;
3165	}
3166
3167
3168	/**
3169	* Checks and fixes the maximum physical address width supported by the
3170	* variable-range MTRR MSRs to be consistent with what is reported in CPUID.
3171	*
3172	* @returns VBox status code.
3173	* @param pVM The cross context VM structure.
3174	* @param cVarMtrrs The number of variable-range MTRRs reported to the guest.
3175	*/
3176	static int cpumR3FixVarMtrrPhysAddrWidths(PVM pVM, uint8_t const cVarMtrrs)
3177	{
3178	AssertLogRelMsgReturn(cVarMtrrs <= RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs),
3179	("Invalid number of variable range MTRRs reported (%u)\n", cVarMtrrs),
3180	VERR_CPUM_IPE_2);
3181
3182	/*
3183	* CPUID determines the actual maximum physical address width reported and supported.
3184	* If the CPU DB profile reported fewer address bits, we must correct it here by
3185	* updating the MSR write #GP masks of all the variable-range MTRR MSRs. Otherwise,
3186	* they cause problems when guests write to these MTRR MSRs, see @bugref{10498#c32}.
3187	*/
3188	PCPUMMSRRANGE pBaseRange0 = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSBASE0);
3189	AssertLogRelMsgReturn(pBaseRange0, ("Failed to lookup the IA32_MTRR_PHYSBASE[0] MSR range\n"), VERR_NOT_FOUND);
3190
3191	PCPUMMSRRANGE pMaskRange0 = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSMASK0);
3192	AssertLogRelMsgReturn(pMaskRange0, ("Failed to lookup the IA32_MTRR_PHYSMASK[0] MSR range\n"), VERR_NOT_FOUND);
3193
3194	uint64_t const fPhysBaseWrGpMask = pBaseRange0->fWrGpMask;
3195	uint64_t const fPhysMaskWrGpMask = pMaskRange0->fWrGpMask;
3196
3197	uint8_t const cGuestMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3198	uint8_t const cProfilePhysBaseMaxPhysAddrWidth = ASMBitLastSetU64(~fPhysBaseWrGpMask);
3199	uint8_t const cProfilePhysMaskMaxPhysAddrWidth = ASMBitLastSetU64(~fPhysMaskWrGpMask);
3200
3201	AssertLogRelMsgReturn(cProfilePhysBaseMaxPhysAddrWidth == cProfilePhysMaskMaxPhysAddrWidth,
3202	("IA32_MTRR_PHYSBASE and IA32_MTRR_PHYSMASK report different physical address widths (%u and %u)\n",
3203	cProfilePhysBaseMaxPhysAddrWidth, cProfilePhysMaskMaxPhysAddrWidth),
3204	VERR_CPUM_IPE_2);
3205	AssertLogRelMsgReturn(cProfilePhysBaseMaxPhysAddrWidth > 12 && cProfilePhysBaseMaxPhysAddrWidth <= 64,
3206	("IA32_MTRR_PHYSBASE and IA32_MTRR_PHYSMASK reports an invalid physical address width of %u bits\n",
3207	cProfilePhysBaseMaxPhysAddrWidth), VERR_CPUM_IPE_2);
3208
3209	if (cProfilePhysBaseMaxPhysAddrWidth < cGuestMaxPhysAddrWidth)
3210	{
3211	uint64_t fNewPhysBaseWrGpMask = fPhysBaseWrGpMask;
3212	uint64_t fNewPhysMaskWrGpMask = fPhysMaskWrGpMask;
3213	int8_t cBits = cGuestMaxPhysAddrWidth - cProfilePhysBaseMaxPhysAddrWidth;
3214	while (cBits)
3215	{
3216	uint64_t const fWrGpAndMask = ~(uint64_t)RT_BIT_64(cProfilePhysBaseMaxPhysAddrWidth + cBits - 1);
3217	fNewPhysBaseWrGpMask &= fWrGpAndMask;
3218	fNewPhysMaskWrGpMask &= fWrGpAndMask;
3219	--cBits;
3220	}
3221
3222	for (uint8_t iVarMtrr = 1; iVarMtrr < cVarMtrrs; iVarMtrr++)
3223	{
3224	PCPUMMSRRANGE pBaseRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSBASE0 + (iVarMtrr * 2));
3225	AssertLogRelMsgReturn(pBaseRange, ("Failed to lookup the IA32_MTRR_PHYSBASE[%u] MSR range\n", iVarMtrr),
3226	VERR_NOT_FOUND);
3227
3228	PCPUMMSRRANGE pMaskRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSMASK0 + (iVarMtrr * 2));
3229	AssertLogRelMsgReturn(pMaskRange, ("Failed to lookup the IA32_MTRR_PHYSMASK[%u] MSR range\n", iVarMtrr),
3230	VERR_NOT_FOUND);
3231
3232	AssertLogRelMsgReturn(pBaseRange->fWrGpMask == fPhysBaseWrGpMask,
3233	("IA32_MTRR_PHYSBASE[%u] write GP mask (%#016RX64) differs from IA32_MTRR_PHYSBASE[0] write GP mask (%#016RX64)\n",
3234	iVarMtrr, pBaseRange->fWrGpMask, fPhysBaseWrGpMask),
3235	VERR_CPUM_IPE_1);
3236	AssertLogRelMsgReturn(pMaskRange->fWrGpMask == fPhysMaskWrGpMask,
3237	("IA32_MTRR_PHYSMASK[%u] write GP mask (%#016RX64) differs from IA32_MTRR_PHYSMASK[0] write GP mask (%#016RX64)\n",
3238	iVarMtrr, pMaskRange->fWrGpMask, fPhysMaskWrGpMask),
3239	VERR_CPUM_IPE_1);
3240
3241	pBaseRange->fWrGpMask = fNewPhysBaseWrGpMask;
3242	pMaskRange->fWrGpMask = fNewPhysMaskWrGpMask;
3243	}
3244
3245	pBaseRange0->fWrGpMask = fNewPhysBaseWrGpMask;
3246	pMaskRange0->fWrGpMask = fNewPhysMaskWrGpMask;
3247
3248	LogRel(("CPUM: Updated IA32_MTRR_PHYSBASE[0..%u] MSR write #GP mask (old=%#016RX64 new=%#016RX64)\n",
3249	cVarMtrrs - 1, fPhysBaseWrGpMask, fNewPhysBaseWrGpMask));
3250	LogRel(("CPUM: Updated IA32_MTRR_PHYSMASK[0..%u] MSR write #GP mask (old=%#016RX64 new=%#016RX64)\n",
3251	cVarMtrrs - 1, fPhysMaskWrGpMask, fNewPhysMaskWrGpMask));
3252	}
3253
3254	return VINF_SUCCESS;
3255	}
3256
3257
3258	/**
3259	* Inserts variable-range MTRR MSR ranges based on the given count.
3260	*
3261	* Since we need to insert the MSRs beyond what the CPU profile has inserted, we
3262	* reinsert the whole range here since the variable-range MTRR MSR read+write
3263	* functions handle ranges as well as the \#GP checking.
3264	*
3265	* @returns VBox status code.
3266	* @param pVM The cross context VM structure.
3267	* @param cVarMtrrs The number of variable-range MTRRs to insert. This must be
3268	* less than or equal to CPUMCTX_MAX_MTRRVAR_COUNT.
3269	*/
3270	static int cpumR3VarMtrrMsrRangeInsert(PVM pVM, uint8_t const cVarMtrrs)
3271	{
3272	#ifdef VBOX_WITH_STATISTICS
3273	# define CPUM_MTRR_PHYSBASE_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3274	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysBaseN, kCpumMsrWrFn_Ia32MtrrPhysBaseN, 0, 0, a_uValue, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
3275	# define CPUM_MTRR_PHYSMASK_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3276	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysMaskN, kCpumMsrWrFn_Ia32MtrrPhysMaskN, 0, 0, a_uValue, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
3277	#else
3278	# define CPUM_MTRR_PHYSBASE_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3279	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysBaseN, kCpumMsrWrFn_Ia32MtrrPhysBaseN, 0, 0, a_uValue, 0, 0, a_szName }
3280	# define CPUM_MTRR_PHYSMASK_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3281	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysMaskN, kCpumMsrWrFn_Ia32MtrrPhysMaskN, 0, 0, a_uValue, 0, 0, a_szName }
3282	#endif
3283	static CPUMMSRRANGE const s_aMsrRanges_MtrrPhysBase[CPUMCTX_MAX_MTRRVAR_COUNT] =
3284	{
3285	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE0, 0, "MSR_IA32_MTRR_PHYSBASE0"),
3286	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE1, 1, "MSR_IA32_MTRR_PHYSBASE1"),
3287	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE2, 2, "MSR_IA32_MTRR_PHYSBASE2"),
3288	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE3, 3, "MSR_IA32_MTRR_PHYSBASE3"),
3289	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE4, 4, "MSR_IA32_MTRR_PHYSBASE4"),
3290	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE5, 5, "MSR_IA32_MTRR_PHYSBASE5"),
3291	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE6, 6, "MSR_IA32_MTRR_PHYSBASE6"),
3292	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE7, 7, "MSR_IA32_MTRR_PHYSBASE7"),
3293	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE8, 8, "MSR_IA32_MTRR_PHYSBASE8"),
3294	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9, 9, "MSR_IA32_MTRR_PHYSBASE9"),
3295	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 2, 10, "MSR_IA32_MTRR_PHYSBASE10"),
3296	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 4, 11, "MSR_IA32_MTRR_PHYSBASE11"),
3297	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 6, 12, "MSR_IA32_MTRR_PHYSBASE12"),
3298	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 8, 13, "MSR_IA32_MTRR_PHYSBASE13"),
3299	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 10, 14, "MSR_IA32_MTRR_PHYSBASE14"),
3300	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 12, 15, "MSR_IA32_MTRR_PHYSBASE15"),
3301	};
3302	static CPUMMSRRANGE const s_aMsrRanges_MtrrPhysMask[CPUMCTX_MAX_MTRRVAR_COUNT] =
3303	{
3304	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK0, 0, "MSR_IA32_MTRR_PHYSMASK0"),
3305	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK1, 1, "MSR_IA32_MTRR_PHYSMASK1"),
3306	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK2, 2, "MSR_IA32_MTRR_PHYSMASK2"),
3307	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK3, 3, "MSR_IA32_MTRR_PHYSMASK3"),
3308	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK4, 4, "MSR_IA32_MTRR_PHYSMASK4"),
3309	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK5, 5, "MSR_IA32_MTRR_PHYSMASK5"),
3310	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK6, 6, "MSR_IA32_MTRR_PHYSMASK6"),
3311	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK7, 7, "MSR_IA32_MTRR_PHYSMASK7"),
3312	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK8, 8, "MSR_IA32_MTRR_PHYSMASK8"),
3313	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9, 9, "MSR_IA32_MTRR_PHYSMASK9"),
3314	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 2, 10, "MSR_IA32_MTRR_PHYSMASK10"),
3315	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 4, 11, "MSR_IA32_MTRR_PHYSMASK11"),
3316	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 6, 12, "MSR_IA32_MTRR_PHYSMASK12"),
3317	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 8, 13, "MSR_IA32_MTRR_PHYSMASK13"),
3318	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 10, 14, "MSR_IA32_MTRR_PHYSMASK14"),
3319	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 12, 15, "MSR_IA32_MTRR_PHYSMASK15"),
3320	};
3321	AssertCompile(RT_ELEMENTS(s_aMsrRanges_MtrrPhysBase) == RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3322	AssertCompile(RT_ELEMENTS(s_aMsrRanges_MtrrPhysMask) == RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3323
3324	Assert(cVarMtrrs <= RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3325	for (unsigned i = 0; i < cVarMtrrs; i++)
3326	{
3327	int rc = CPUMR3MsrRangesInsert(pVM, &s_aMsrRanges_MtrrPhysBase[i]);
3328	AssertLogRelRCReturn(rc, rc);
3329	rc = CPUMR3MsrRangesInsert(pVM, &s_aMsrRanges_MtrrPhysMask[i]);
3330	AssertLogRelRCReturn(rc, rc);
3331	}
3332	return VINF_SUCCESS;
3333
3334	#undef CPUM_MTRR_PHYSBASE_MSRRANGE
3335	#undef CPUM_MTRR_PHYSMASK_MSRRANGE
3336	}
3337
3338
3339	/**
3340	* Initialize MTRR capability based on what the guest CPU profile (typically host)
3341	* supports.
3342	*
3343	* @returns VBox status code.
3344	* @param pVM The cross context VM structure.
3345	* @param fMtrrVarCountIsVirt Whether the variable-range MTRR count is fully
3346	* virtualized (@c true) or derived from the CPU
3347	* profile (@c false).
3348	*/
3349	static int cpumR3InitMtrrCap(PVM pVM, bool fMtrrVarCountIsVirt)
3350	{
3351	#ifdef RT_ARCH_AMD64
3352	Assert(pVM->cpum.s.HostFeatures.s.fMtrr);
3353	#endif
3354
3355	/* Lookup the number of variable-range MTRRs supported by the CPU profile. */
3356	PCCPUMMSRRANGE pMtrrCapRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_CAP);
3357	AssertLogRelMsgReturn(pMtrrCapRange, ("Failed to lookup IA32_MTRR_CAP MSR range\n"), VERR_NOT_FOUND);
3358	uint8_t const cProfileVarRangeRegs = pMtrrCapRange->uValue & MSR_IA32_MTRR_CAP_VCNT_MASK;
3359
3360	/* Construct guest MTRR support capabilities. */
3361	uint8_t const cGuestVarRangeRegs = fMtrrVarCountIsVirt ? CPUMCTX_MAX_MTRRVAR_COUNT
3362	: RT_MIN(cProfileVarRangeRegs, CPUMCTX_MAX_MTRRVAR_COUNT);
3363	uint64_t const uGstMtrrCap = cGuestVarRangeRegs
3364	\| MSR_IA32_MTRR_CAP_FIX
3365	\| MSR_IA32_MTRR_CAP_WC;
3366	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3367	{
3368	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3369	pVCpu->cpum.s.GuestMsrs.msr.MtrrCap = uGstMtrrCap;
3370	pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = MSR_IA32_MTRR_DEF_TYPE_FIXED_EN
3371	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN
3372	\| X86_MTRR_MT_UC;
3373	}
3374
3375	if (fMtrrVarCountIsVirt)
3376	{
3377	/*
3378	* Insert the full variable-range MTRR MSR range ourselves so it extends beyond what is
3379	* typically reported by the hardware CPU profile.
3380	*/
3381	LogRel(("CPUM: Enabled fixed-range MTRRs and %u (virtualized) variable-range MTRRs\n", cGuestVarRangeRegs));
3382	return cpumR3VarMtrrMsrRangeInsert(pVM, cGuestVarRangeRegs);
3383	}
3384
3385	/*
3386	* Ensure that the maximum physical address width supported by the variable-range MTRRs
3387	* are consistent with what is reported to the guest via CPUID.
3388	*/
3389	LogRel(("CPUM: Enabled fixed-range MTRRs and %u (CPU profile derived) variable-range MTRRs\n", cGuestVarRangeRegs));
3390	return cpumR3FixVarMtrrPhysAddrWidths(pVM, cGuestVarRangeRegs);
3391	}
3392
3393
3394	/**
3395	* Initializes the emulated CPU's CPUID & MSR information.
3396	*
3397	* @returns VBox status code.
3398	* @param pVM The cross context VM structure.
3399	* @param pHostMsrs Pointer to the host MSRs.
3400	*/
3401	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
3402	{
3403	Assert(pHostMsrs);
3404
3405	PCPUM pCpum = &pVM->cpum.s;
3406	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3407
3408	/*
3409	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
3410	* on construction and manage everything from here on.
3411	*/
3412	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3413	{
3414	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3415	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
3416	}
3417
3418	/*
3419	* Read the configuration.
3420	*/
3421	CPUMCPUIDCONFIG Config;
3422	RT_ZERO(Config);
3423
3424	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM)
3425	\|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
3426	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
3427	AssertRCReturn(rc, rc);
3428
3429	/*
3430	* Get the guest CPU data from the database and/or the host.
3431	*
3432	* The CPUID and MSRs are currently living on the regular heap to avoid
3433	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3434	* API for the hyper heap). This means special cleanup considerations.
3435	*/
3436	/** @todo The hyper heap will be removed ASAP, so the final destination is
3437	* now a fixed sized arrays in the VM structure. Maybe we can simplify
3438	* this allocation fun a little now? Or maybe it's too convenient for
3439	* the CPU reporter code... No time to figure that out now. */
3440	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3441	if (RT_FAILURE(rc))
3442	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3443	? VMSetError(pVM, rc, RT_SRC_POS,
3444	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3445	: rc;
3446
3447	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3448	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
3449	{
3450	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
3451	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3452	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
3453	}
3454	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3455	#else
3456	LogRel(("CPUM: MXCSR_MASK=%#x\n", pCpum->GuestInfo.fMxCsrMask));
3457	#endif
3458
3459	/** @cfgm{/CPUM/GuestMicrocodeRev,32-bit}
3460	* CPU microcode revision number to use. If UINT32_MAX we use the host
3461	* revision of the host CPU for the host-cpu profile and the database entry if a
3462	* specific one is selected (amd64 host only). */
3463	rc = CFGMR3QueryU32Def(pCpumCfg, "GuestMicrocodeRevision", &pCpum->GuestInfo.uMicrocodeRevision, UINT32_MAX);
3464	AssertLogRelRCReturn(rc, rc);
3465	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3466	if ( pCpum->GuestInfo.uMicrocodeRevision == UINT32_MAX
3467	&& strcmp(Config.szCpuName, "host") == 0)
3468	{
3469	rc = SUPR3QueryMicrocodeRev(&pCpum->GuestInfo.uMicrocodeRevision);
3470	if (RT_FAILURE(rc))
3471	pCpum->GuestInfo.uMicrocodeRevision = UINT32_MAX;
3472	}
3473	#endif
3474
3475	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3476	* Overrides the guest MSRs.
3477	*/
3478	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3479
3480	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3481	* Overrides the CPUID leaf values (from the host CPU usually) used for
3482	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3483	* values when moving a VM to a different machine. Another use is restricting
3484	* (or extending) the feature set exposed to the guest. */
3485	if (RT_SUCCESS(rc))
3486	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3487
3488	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3489	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3490	"Found unsupported configuration node '/CPUM/CPUID/'. "
3491	"Please use IMachine::setCPUIDLeaf() instead.");
3492
3493	CPUMMSRS GuestMsrs;
3494	RT_ZERO(GuestMsrs);
3495
3496	/*
3497	* Pre-explode the CPUID info.
3498	*/
3499	if (RT_SUCCESS(rc))
3500	rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
3501	&pCpum->GuestFeatures);
3502
3503	/*
3504	* Sanitize the cpuid information passed on to the guest.
3505	*/
3506	if (RT_SUCCESS(rc))
3507	{
3508	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3509	if (RT_SUCCESS(rc))
3510	{
3511	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3512	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3513	}
3514	}
3515
3516	/*
3517	* Move the CPUID array over to the static VM structure allocation
3518	* and explode guest CPU features again. We must do this before
3519	* reconciling MSRs with CPUIDs and applying any fudging (esp on ARM64).
3520	*/
3521	if (RT_SUCCESS(rc))
3522	{
3523	void * const pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3524	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3525	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
3526	AssertLogRelRC(rc);
3527	RTMemFree(pvFree);
3528	if (RT_SUCCESS(rc))
3529	{
3530	/*
3531	* Setup MSRs introduced in microcode updates or that are otherwise not in
3532	* the CPU profile, but are advertised in the CPUID info we just sanitized.
3533	*/
3534	if (RT_SUCCESS(rc))
3535	rc = cpumR3MsrReconcileWithCpuId(pVM);
3536	/*
3537	* MSR fudging.
3538	*/
3539	if (RT_SUCCESS(rc))
3540	{
3541	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3542	* Fudges some common MSRs if not present in the selected CPU database entry.
3543	* This is for trying to keep VMs running when moved between different hosts
3544	* and different CPU vendors. */
3545	bool fEnable;
3546	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3547	if (RT_SUCCESS(rc) && fEnable)
3548	{
3549	rc = cpumR3MsrApplyFudge(pVM);
3550	AssertLogRelRC(rc);
3551	}
3552	}
3553	if (RT_SUCCESS(rc))
3554	{
3555	/*
3556	* Move the MSR arrays over to the static VM structure allocation.
3557	*/
3558	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
3559	("%u\n", pCpum->GuestInfo.cMsrRanges));
3560	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
3561	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
3562	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3563	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
3564
3565	/*
3566	* Some more configuration that we're applying at the end of everything
3567	* via the CPUMR3SetGuestCpuIdFeature API.
3568	*/
3569
3570	/* Check if 64-bit guest supported was enabled. */
3571	bool fEnable64bit;
3572	rc = CFGMR3QueryBoolDef(pCpumCfg, "Enable64bit", &fEnable64bit, false);
3573	AssertRCReturn(rc, rc);
3574	if (fEnable64bit)
3575	{
3576	/* In case of a CPU upgrade: */
3577	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
3578	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
3579	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3580	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
3581	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3582
3583	/* The actual feature: */
3584	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
3585	}
3586
3587	/* Check if PAE was explicitely enabled by the user. */
3588	bool fEnable;
3589	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, fEnable64bit);
3590	AssertRCReturn(rc, rc);
3591	if (fEnable && !pVM->cpum.s.GuestFeatures.fPae)
3592	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3593
3594	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3595	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, fEnable64bit);
3596	AssertRCReturn(rc, rc);
3597	if (fEnable && !pVM->cpum.s.GuestFeatures.fNoExecute)
3598	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3599
3600	/* Check if speculation control is enabled. */
3601	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
3602	AssertRCReturn(rc, rc);
3603	if (fEnable)
3604	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
3605	else
3606	{
3607	/*
3608	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
3609	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
3610	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
3611	*
3612	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
3613	* EIP: _raw_spin_lock+0x14/0x30
3614	* EFLAGS: 00010046 CPU: 0
3615	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
3616	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
3617	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
3618	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
3619	* Call Trace:
3620	* speculative_store_bypass_update+0x8e/0x180
3621	* ssb_prctl_set+0xc0/0xe0
3622	* arch_seccomp_spec_mitigate+0x1d/0x20
3623	* do_seccomp+0x3cb/0x610
3624	* SyS_seccomp+0x16/0x20
3625	* do_fast_syscall_32+0x7f/0x1d0
3626	* entry_SYSENTER_32+0x4e/0x7c
3627	*
3628	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
3629	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
3630	*
3631	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
3632	* guest to not even try.
3633	*/
3634	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3635	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3636	{
3637	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
3638	if (pLeaf)
3639	{
3640	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
3641	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
3642	}
3643	}
3644	}
3645
3646	/*
3647	* MTRR support.
3648	* We've always reported the MTRR feature bit in CPUID.
3649	* Here we allow exposing MTRRs with reasonable default values (especially required
3650	* by Windows 10 guests with Hyper-V enabled). The MTRR support isn't feature
3651	* complete, see @bugref{10318} and bugref{10498}.
3652	*/
3653	if (pVM->cpum.s.GuestFeatures.fMtrr)
3654	{
3655	/** @cfgm{/CPUM/MtrrWrite, boolean, true}
3656	* Whether to enable MTRR read-write support. This overrides the MTRR read-only CFGM
3657	* setting. */
3658	bool fEnableMtrrReadWrite;
3659	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrReadWrite", &fEnableMtrrReadWrite, true);
3660	AssertRCReturn(rc, rc);
3661	if (fEnableMtrrReadWrite)
3662	{
3663	pVM->cpum.s.fMtrrRead = true;
3664	pVM->cpum.s.fMtrrWrite = true;
3665	LogRel(("CPUM: Enabled MTRR read-write support\n"));
3666	}
3667	else
3668	{
3669	/** @cfgm{/CPUM/MtrrReadOnly, boolean, false}
3670	* Whether to enable MTRR read-only support and to initialize mapping of guest
3671	* memory via MTRRs. When disabled, MTRRs are left blank, returns 0 on reads and
3672	* ignores writes. Some guests like GNU/Linux recognize a virtual system when MTRRs
3673	* are left blank but some guests may expect their RAM to be mapped via MTRRs
3674	* similar to real hardware. */
3675	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrReadOnly", &pVM->cpum.s.fMtrrRead, false);
3676	AssertRCReturn(rc, rc);
3677	LogRel(("CPUM: Enabled MTRR read-only support\n"));
3678	}
3679
3680	/* Setup MTRR capability based on what the guest CPU profile (typically host) supports. */
3681	Assert(!pVM->cpum.s.fMtrrWrite \|\| pVM->cpum.s.fMtrrRead);
3682	if (pVM->cpum.s.fMtrrRead)
3683	{
3684	/** @cfgm{/CPUM/MtrrVarCountIsVirtual, boolean, true}
3685	* When enabled, the number of variable-range MTRRs are virtualized. When disabled,
3686	* the number of variable-range MTRRs are derived from the CPU profile. Unless
3687	* guests have problems with a virtualized number of variable-range MTRRs, it is
3688	* recommended to keep this enabled so that there are sufficient MTRRs to fully
3689	* describe all regions of the guest RAM. */
3690	bool fMtrrVarCountIsVirt;
3691	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrVarCountIsVirtual", &fMtrrVarCountIsVirt, true);
3692	AssertRCReturn(rc, rc);
3693
3694	rc = cpumR3InitMtrrCap(pVM, fMtrrVarCountIsVirt);
3695	if (RT_SUCCESS(rc))
3696	{ /* likely */ }
3697	else
3698	return rc;
3699	}
3700	}
3701
3702	/*
3703	* Finally, initialize guest VMX MSRs.
3704	*
3705	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
3706	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
3707	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
3708	*/
3709	/** @todo r=bird: given that long mode never used to be enabled before the
3710	* VMINITCOMPLETED_RING0 state, and we're a lot earlier here in ring-3
3711	* init, the above comment cannot be entirely accurate. */
3712	if (pVM->cpum.s.GuestFeatures.fVmx)
3713	{
3714	Assert(Config.fNestedHWVirt);
3715	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, pCpumCfg, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
3716
3717	/* Copy MSRs to all VCPUs */
3718	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
3719	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3720	{
3721	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3722	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
3723	}
3724	}
3725
3726	return VINF_SUCCESS;
3727	}
3728
3729	/*
3730	* Failed before/while switching to internal VM structure storage.
3731	*/
3732	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3733	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3734	}
3735	}
3736	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3737	pCpum->GuestInfo.paMsrRangesR3 = NULL;
3738	return rc;
3739	}
3740
3741
3742	/**
3743	* Sets a CPUID feature bit during VM initialization.
3744	*
3745	* Since the CPUID feature bits are generally related to CPU features, other
3746	* CPUM configuration like MSRs can also be modified by calls to this API.
3747	*
3748	* @param pVM The cross context VM structure.
3749	* @param enmFeature The feature to set.
3750	*/
3751	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3752	{
3753	PCPUMCPUIDLEAF pLeaf;
3754	PCPUMMSRRANGE pMsrRange;
3755
3756	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3757	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3758	if (!pVM->cpum.s.HostFeatures.s. a_fFeature) \
3759	{ \
3760	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when the host doesn't support it!\n")); \
3761	return; \
3762	} else do { } while (0)
3763	#else
3764	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) do { } while (0)
3765	#endif
3766
3767	#define GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3768	do \
3769	{ \
3770	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001)); \
3771	if (!pLeaf) \
3772	{ \
3773	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when no 0x80000001 CPUID leaf!\n")); \
3774	return; \
3775	} \
3776	CHECK_X86_HOST_FEATURE_RET(a_fFeature,a_szFeature); \
3777	} while (0)
3778
3779	switch (enmFeature)
3780	{
3781	/*
3782	* Set the APIC bit in both feature masks.
3783	*/
3784	case CPUMCPUIDFEATURE_APIC:
3785	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3786	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3787	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
3788
3789	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3790	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3791	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
3792
3793	pVM->cpum.s.GuestFeatures.fApic = 1;
3794
3795	/* Make sure we've got the APICBASE MSR present. */
3796	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3797	if (!pMsrRange)
3798	{
3799	static CPUMMSRRANGE const s_ApicBase =
3800	{
3801	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
3802	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
3803	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3804	/.szName = / "IA32_APIC_BASE"
3805	};
3806	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
3807	AssertLogRelRC(rc);
3808	}
3809
3810	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
3811	break;
3812
3813	/*
3814	* Set the x2APIC bit in the standard feature mask.
3815	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
3816	*/
3817	case CPUMCPUIDFEATURE_X2APIC:
3818	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3819	if (pLeaf)
3820	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
3821	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
3822
3823	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
3824	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3825	if (pMsrRange)
3826	{
3827	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
3828	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
3829	}
3830
3831	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
3832	break;
3833
3834	/*
3835	* Set the sysenter/sysexit bit in the standard feature mask.
3836	* Assumes the caller knows what it's doing! (host must support these)
3837	*/
3838	case CPUMCPUIDFEATURE_SEP:
3839	CHECK_X86_HOST_FEATURE_RET(fSysEnter, "SEP");
3840	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3841	if (pLeaf)
3842	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
3843	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
3844	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
3845	break;
3846
3847	/*
3848	* Set the syscall/sysret bit in the extended feature mask.
3849	* Assumes the caller knows what it's doing! (host must support these)
3850	*/
3851	case CPUMCPUIDFEATURE_SYSCALL:
3852	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fSysCall, "SYSCALL/SYSRET");
3853
3854	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
3855	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
3856	pVM->cpum.s.GuestFeatures.fSysCall = 1;
3857	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
3858	break;
3859
3860	/*
3861	* Set the PAE bit in both feature masks.
3862	* Assumes the caller knows what it's doing! (host must support these)
3863	*/
3864	case CPUMCPUIDFEATURE_PAE:
3865	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3866	if (pLeaf)
3867	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
3868
3869	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3870	if ( pLeaf
3871	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3872	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3873	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
3874
3875	pVM->cpum.s.GuestFeatures.fPae = 1;
3876	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
3877	break;
3878
3879	/*
3880	* Set the LONG MODE bit in the extended feature mask.
3881	* Assumes the caller knows what it's doing! (host must support these)
3882	*/
3883	case CPUMCPUIDFEATURE_LONG_MODE:
3884	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLongMode, "LONG MODE");
3885
3886	/* Valid for both Intel and AMD. */
3887	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3888	pVM->cpum.s.GuestFeatures.fLongMode = 1;
3889	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3890	if (pVM->cpum.s.GuestFeatures.fVmx)
3891	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3892	{
3893	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3894	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3895	}
3896	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
3897	break;
3898
3899	/*
3900	* Set the NX/XD bit in the extended feature mask.
3901	* Assumes the caller knows what it's doing! (host must support these)
3902	*/
3903	case CPUMCPUIDFEATURE_NX:
3904	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fNoExecute, "NX/XD");
3905
3906	/* Valid for both Intel and AMD. */
3907	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
3908	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
3909	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
3910	break;
3911
3912
3913	/*
3914	* Set the LAHF/SAHF support in 64-bit mode.
3915	* Assumes the caller knows what it's doing! (host must support this)
3916	*/
3917	case CPUMCPUIDFEATURE_LAHF:
3918	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLahfSahf, "LAHF/SAHF");
3919
3920	/* Valid for both Intel and AMD. */
3921	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3922	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
3923	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
3924	break;
3925
3926	/*
3927	* Set the RDTSCP support bit.
3928	* Assumes the caller knows what it's doing! (host must support this)
3929	*/
3930	case CPUMCPUIDFEATURE_RDTSCP:
3931	if (pVM->cpum.s.u8PortableCpuIdLevel > 0)
3932	return;
3933	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fRdTscP, "RDTSCP");
3934	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3935
3936	/* Valid for both Intel and AMD. */
3937	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3938	pVM->cpum.s.GuestFeatures.fRdTscP = 1;
3939	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
3940	break;
3941
3942	/*
3943	* Set the Hypervisor Present bit in the standard feature mask.
3944	*/
3945	case CPUMCPUIDFEATURE_HVP:
3946	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3947	if (pLeaf)
3948	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
3949	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
3950	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
3951	break;
3952
3953	/*
3954	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
3955	* on Intel CPUs, and different on AMDs.
3956	*/
3957	case CPUMCPUIDFEATURE_SPEC_CTRL:
3958	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3959	{
3960	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3961	#ifdef RT_ARCH_AMD64
3962	if ( !pLeaf
3963	\|\| !(pVM->cpum.s.HostFeatures.s.fIbpb \|\| pVM->cpum.s.HostFeatures.s.fIbrs))
3964	{
3965	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
3966	return;
3967	}
3968	#else
3969	if (!pLeaf)
3970	{
3971	LogRel(("CPUM: WARNING! Can't turn on Speculation Control without leaf 0x00000007!\n"));
3972	return;
3973	}
3974	#endif
3975
3976	/* The feature can be enabled. Let's see what we can actually do. */
3977	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
3978
3979	#ifdef RT_ARCH_AMD64
3980	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
3981	if (pVM->cpum.s.HostFeatures.s.fIbrs)
3982	#endif
3983	{
3984	/** @todo make this more configurable? */
3985	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
3986	pVM->cpum.s.GuestFeatures.fIbrs = 1;
3987	#ifdef RT_ARCH_AMD64
3988	if (pVM->cpum.s.HostFeatures.s.fStibp)
3989	#endif
3990	{
3991	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
3992	pVM->cpum.s.GuestFeatures.fStibp = 1;
3993	}
3994
3995	#ifdef RT_ARCH_AMD64
3996	if (pVM->cpum.s.HostFeatures.s.fSsbd)
3997	#endif
3998	{
3999	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_SSBD;
4000	pVM->cpum.s.GuestFeatures.fSsbd = 1;
4001	}
4002
4003	PCPUMCPUIDLEAF const pSubLeaf2 = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 2);
4004	if (pSubLeaf2)
4005	{
4006	#ifdef RT_ARCH_AMD64
4007	if (pVM->cpum.s.HostFeatures.s.fPsfd)
4008	#endif
4009	{
4010	pSubLeaf2->uEdx \|= X86_CPUID_STEXT_FEATURE_2_EDX_PSFD;
4011	pVM->cpum.s.GuestFeatures.fPsfd = 1;
4012	}
4013
4014	#ifdef RT_ARCH_AMD64
4015	if (pVM->cpum.s.HostFeatures.s.fIpredCtrl)
4016	#endif
4017	{
4018	pSubLeaf2->uEdx \|= X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL;
4019	pVM->cpum.s.GuestFeatures.fIpredCtrl = 1;
4020	}
4021
4022	#ifdef RT_ARCH_AMD64
4023	if (pVM->cpum.s.HostFeatures.s.fRrsbaCtrl)
4024	#endif
4025	{
4026	pSubLeaf2->uEdx \|= X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL;
4027	pVM->cpum.s.GuestFeatures.fRrsbaCtrl = 1;
4028	}
4029
4030	#ifdef RT_ARCH_AMD64
4031	if (pVM->cpum.s.HostFeatures.s.fDdpdU)
4032	#endif
4033	{
4034	pSubLeaf2->uEdx \|= X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U;
4035	pVM->cpum.s.GuestFeatures.fDdpdU = 1;
4036	}
4037
4038	#ifdef RT_ARCH_AMD64
4039	if (pVM->cpum.s.HostFeatures.s.fBhiCtrl)
4040	#endif
4041	{
4042	pSubLeaf2->uEdx \|= X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL;
4043	pVM->cpum.s.GuestFeatures.fBhiCtrl = 1;
4044	}
4045	}
4046
4047	/* Make sure we have the speculation control MSR... */
4048	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4049	if (!pMsrRange)
4050	{
4051	static CPUMMSRRANGE const s_SpecCtrl =
4052	{
4053	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4054	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4055	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4056	/.szName = / "IA32_SPEC_CTRL"
4057	};
4058	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4059	AssertLogRelRC(rc);
4060	}
4061
4062	/* ... and the predictor command MSR. */
4063	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4064	if (!pMsrRange)
4065	{
4066	/** @todo incorrect fWrGpMask. */
4067	static CPUMMSRRANGE const s_SpecCtrl =
4068	{
4069	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4070	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4071	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4072	/.szName = / "IA32_PRED_CMD"
4073	};
4074	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4075	AssertLogRelRC(rc);
4076	}
4077
4078	}
4079
4080	#ifdef RT_ARCH_AMD64
4081	if (pVM->cpum.s.HostFeatures.s.fArchCap)
4082	#endif
4083	{
4084	/* Install the architectural capabilities MSR. */
4085	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4086	if (!pMsrRange)
4087	{
4088	static CPUMMSRRANGE const s_ArchCaps =
4089	{
4090	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4091	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4092	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4093	/.szName = / "IA32_ARCH_CAPABILITIES"
4094	};
4095	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4096	AssertLogRelRC(rc);
4097	}
4098
4099	/* Advertise IBRS_ALL if present at this point... */
4100	#ifdef RT_ARCH_AMD64
4101	if (pVM->cpum.s.HostFeatures.s.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
4102	#endif
4103	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
4104	}
4105
4106	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4107	}
4108	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4109	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
4110	{
4111	/* The precise details of AMD's implementation are not yet clear. */
4112	}
4113	break;
4114
4115	default:
4116	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4117	break;
4118	}
4119
4120	/** @todo can probably kill this as this API is now init time only... */
4121	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4122	{
4123	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4124	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4125	}
4126
4127	#undef GET_8000_0001_CHECK_X86_HOST_FEATURE_RET
4128	#undef CHECK_X86_HOST_FEATURE_RET
4129	}
4130
4131
4132	/**
4133	* Queries a CPUID feature bit.
4134	*
4135	* @returns boolean for feature presence
4136	* @param pVM The cross context VM structure.
4137	* @param enmFeature The feature to query.
4138	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4139	*/
4140	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4141	{
4142	switch (enmFeature)
4143	{
4144	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4145	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4146	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4147	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4148	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4149	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4150	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4151	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4152	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4153	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4154	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4155	case CPUMCPUIDFEATURE_INVALID:
4156	case CPUMCPUIDFEATURE_32BIT_HACK:
4157	break;
4158	}
4159	AssertFailed();
4160	return false;
4161	}
4162
4163
4164	/**
4165	* Clears a CPUID feature bit.
4166	*
4167	* @param pVM The cross context VM structure.
4168	* @param enmFeature The feature to clear.
4169	*
4170	* @deprecated Probably better to default the feature to disabled and only allow
4171	* setting (enabling) it during construction.
4172	*/
4173	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4174	{
4175	PCPUMCPUIDLEAF pLeaf;
4176	switch (enmFeature)
4177	{
4178	case CPUMCPUIDFEATURE_APIC:
4179	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4180	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4181	if (pLeaf)
4182	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4183
4184	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4185	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4186	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4187
4188	pVM->cpum.s.GuestFeatures.fApic = 0;
4189	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4190	break;
4191
4192	case CPUMCPUIDFEATURE_X2APIC:
4193	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4194	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4195	if (pLeaf)
4196	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4197	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4198	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4199	break;
4200
4201	#if 0
4202	case CPUMCPUIDFEATURE_PAE:
4203	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4204	if (pLeaf)
4205	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4206
4207	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4208	if ( pLeaf
4209	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4210	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4211	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4212
4213	pVM->cpum.s.GuestFeatures.fPae = 0;
4214	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4215	break;
4216
4217	case CPUMCPUIDFEATURE_LONG_MODE:
4218	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4219	if (pLeaf)
4220	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4221	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4222	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
4223	if (pVM->cpum.s.GuestFeatures.fVmx)
4224	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4225	{
4226	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4227	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4228	}
4229	break;
4230
4231	case CPUMCPUIDFEATURE_LAHF:
4232	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4233	if (pLeaf)
4234	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4235	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4236	break;
4237	#endif
4238	case CPUMCPUIDFEATURE_RDTSCP:
4239	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4240	if (pLeaf)
4241	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4242	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4243	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4244	break;
4245
4246	#if 0
4247	case CPUMCPUIDFEATURE_HVP:
4248	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4249	if (pLeaf)
4250	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4251	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4252	break;
4253
4254	case CPUMCPUIDFEATURE_SPEC_CTRL:
4255	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4256	if (pLeaf)
4257	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
4258	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
4259	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4260	break;
4261	#endif
4262	default:
4263	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4264	break;
4265	}
4266
4267	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4268	{
4269	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4270	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4271	}
4272	}
4273
4274
4275	/**
4276	* Do some final polishing after all calls to CPUMR3SetGuestCpuIdFeature and
4277	* CPUMR3ClearGuestCpuIdFeature are (probably) done.
4278	*
4279	* @param pVM The cross context VM structure.
4280	*/
4281	void cpumR3CpuIdRing3InitDone(PVM pVM)
4282	{
4283	/*
4284	* Do not advertise NX w/o PAE, seems to confuse windows 7 (black screen very
4285	* early in real mode).
4286	*/
4287	PCPUMCPUIDLEAF pStdLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4288	PCPUMCPUIDLEAF pExtLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4289	if (pStdLeaf && pExtLeaf)
4290	{
4291	if ( !(pStdLeaf->uEdx & X86_CPUID_FEATURE_EDX_PAE)
4292	&& (pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX))
4293	pExtLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_NX;
4294	}
4295	}
4296
4297
4298	/*
4299	*
4300	*
4301	* Saved state related code.
4302	* Saved state related code.
4303	* Saved state related code.
4304	*
4305	*
4306	*/
4307
4308	/**
4309	* Called both in pass 0 and the final pass.
4310	*
4311	* @param pVM The cross context VM structure.
4312	* @param pSSM The saved state handle.
4313	*/
4314	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4315	{
4316	/*
4317	* Save all the CPU ID leaves.
4318	*/
4319	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4320	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4321	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4322	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4323
4324	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4325
4326	/*
4327	* Save a good portion of the raw CPU IDs as well as they may come in
4328	* handy when validating features for raw mode.
4329	*/
4330	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4331	CPUMCPUID aRawStd[16];
4332	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4333	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4334	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4335	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4336
4337	CPUMCPUID aRawExt[32];
4338	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4339	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4340	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4341	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4342
4343	#else
4344	/* Two zero counts on non-x86 hosts. */
4345	SSMR3PutU32(pSSM, 0);
4346	SSMR3PutU32(pSSM, 0);
4347	#endif
4348	}
4349
4350
4351	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4352	{
4353	uint32_t cCpuIds;
4354	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4355	if (RT_SUCCESS(rc))
4356	{
4357	if (cCpuIds < 64)
4358	{
4359	for (uint32_t i = 0; i < cCpuIds; i++)
4360	{
4361	CPUMCPUID CpuId;
4362	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4363	if (RT_FAILURE(rc))
4364	break;
4365
4366	CPUMCPUIDLEAF NewLeaf;
4367	NewLeaf.uLeaf = uBase + i;
4368	NewLeaf.uSubLeaf = 0;
4369	NewLeaf.fSubLeafMask = 0;
4370	NewLeaf.uEax = CpuId.uEax;
4371	NewLeaf.uEbx = CpuId.uEbx;
4372	NewLeaf.uEcx = CpuId.uEcx;
4373	NewLeaf.uEdx = CpuId.uEdx;
4374	NewLeaf.fFlags = 0;
4375	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4376	}
4377	}
4378	else
4379	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4380	}
4381	if (RT_FAILURE(rc))
4382	{
4383	RTMemFree(*ppaLeaves);
4384	*ppaLeaves = NULL;
4385	*pcLeaves = 0;
4386	}
4387	return rc;
4388	}
4389
4390
4391	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4392	{
4393	*ppaLeaves = NULL;
4394	*pcLeaves = 0;
4395
4396	int rc;
4397	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4398	{
4399	/*
4400	* The new format. Starts by declaring the leave size and count.
4401	*/
4402	uint32_t cbLeaf;
4403	SSMR3GetU32(pSSM, &cbLeaf);
4404	uint32_t cLeaves;
4405	rc = SSMR3GetU32(pSSM, &cLeaves);
4406	if (RT_SUCCESS(rc))
4407	{
4408	if (cbLeaf == sizeof(**ppaLeaves))
4409	{
4410	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4411	{
4412	/*
4413	* Load the leaves one by one.
4414	*
4415	* The uPrev stuff is a kludge for working around a week worth of bad saved
4416	* states during the CPUID revamp in March 2015. We saved too many leaves
4417	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4418	* garbage entires at the end of the array when restoring. We also had
4419	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4420	* this kludge doesn't deal correctly with that, but who cares...
4421	*/
4422	uint32_t uPrev = 0;
4423	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4424	{
4425	CPUMCPUIDLEAF Leaf;
4426	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4427	if (RT_SUCCESS(rc))
4428	{
4429	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4430	\|\| Leaf.uLeaf >= uPrev)
4431	{
4432	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4433	uPrev = Leaf.uLeaf;
4434	}
4435	else
4436	uPrev = UINT32_MAX;
4437	}
4438	}
4439	}
4440	else
4441	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4442	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4443	}
4444	else
4445	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4446	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4447	}
4448	}
4449	else
4450	{
4451	/*
4452	* The old format with its three inflexible arrays.
4453	*/
4454	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4455	if (RT_SUCCESS(rc))
4456	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4457	if (RT_SUCCESS(rc))
4458	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4459	if (RT_SUCCESS(rc))
4460	{
4461	/*
4462	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4463	*/
4464	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(ppaLeaves, pcLeaves, 0, 0);
4465	if ( pLeaf
4466	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4467	{
4468	CPUMCPUIDLEAF Leaf;
4469	Leaf.uLeaf = 4;
4470	Leaf.fSubLeafMask = UINT32_MAX;
4471	Leaf.uSubLeaf = 0;
4472	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4473	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4474	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4475	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4476	\| UINT32_C(63); /* system coherency line size - 1 */
4477	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4478	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4479	\| (UINT32_C(1) << 5) /* cache level */
4480	\| UINT32_C(1); /* cache type (data) */
4481	Leaf.fFlags = 0;
4482	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4483	if (RT_SUCCESS(rc))
4484	{
4485	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4486	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4487	}
4488	if (RT_SUCCESS(rc))
4489	{
4490	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4491	Leaf.uEcx = 4095; /* sets - 1 */
4492	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4493	Leaf.uEbx \|= UINT32_C(23) << 22;
4494	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4495	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4496	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4497	Leaf.uEax \|= UINT32_C(2) << 5;
4498	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4499	}
4500	}
4501	}
4502	}
4503	return rc;
4504	}
4505
4506
4507	/**
4508	* Loads the CPU ID leaves saved by pass 0, inner worker.
4509	*
4510	* @returns VBox status code.
4511	* @param pVM The cross context VM structure.
4512	* @param pSSM The saved state handle.
4513	* @param uVersion The format version.
4514	* @param paLeaves Guest CPUID leaves loaded from the state.
4515	* @param cLeaves The number of leaves in @a paLeaves.
4516	* @param pMsrs The guest MSRs.
4517	*/
4518	static int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
4519	{
4520	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4521	#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
4522	AssertMsgFailed(("Port me!"));
4523	#endif
4524
4525	/*
4526	* Continue loading the state into stack buffers.
4527	*/
4528	CPUMCPUID GuestDefCpuId;
4529	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4530	AssertRCReturn(rc, rc);
4531
4532	CPUMCPUID aRawStd[16];
4533	uint32_t cRawStd;
4534	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4535	if (cRawStd > RT_ELEMENTS(aRawStd))
4536	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4537	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4538	AssertRCReturn(rc, rc);
4539	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4540	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4541	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4542	#else
4543	RT_ZERO(aRawStd[i]);
4544	#endif
4545
4546	CPUMCPUID aRawExt[32];
4547	uint32_t cRawExt;
4548	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4549	if (cRawExt > RT_ELEMENTS(aRawExt))
4550	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4551	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4552	AssertRCReturn(rc, rc);
4553	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4554	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4555	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4556	#else
4557	RT_ZERO(aRawExt[i]);
4558	#endif
4559
4560	/*
4561	* Get the raw CPU IDs for the current host.
4562	*/
4563	CPUMCPUID aHostRawStd[16];
4564	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4565	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4566	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4567	#else
4568	RT_ZERO(aHostRawStd);
4569	#endif
4570
4571	CPUMCPUID aHostRawExt[32];
4572	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4573	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4574	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4575	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4576	#else
4577	RT_ZERO(aHostRawExt);
4578	#endif
4579
4580	/*
4581	* Get the host and guest overrides so we don't reject the state because
4582	* some feature was enabled thru these interfaces.
4583	* Note! We currently only need the feature leaves, so skip rest.
4584	*/
4585	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4586	CPUMCPUID aHostOverrideStd[2];
4587	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4588	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4589
4590	CPUMCPUID aHostOverrideExt[2];
4591	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4592	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4593
4594	/*
4595	* This can be skipped.
4596	*
4597	* @note On ARM we disable the strict checks for now because we can't verify with what the host supports
4598	* and just assume the interpreter/recompiler supports everything what was exposed earlier.
4599	*/
4600	bool fStrictCpuIdChecks;
4601	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks,
4602	#ifdef RT_ARCH_ARM64
4603	false
4604	#else
4605	true
4606	#endif
4607	);
4608
4609	/*
4610	* Define a bunch of macros for simplifying the santizing/checking code below.
4611	*/
4612	/* Generic expression + failure message. */
4613	#define CPUID_CHECK_RET(expr, fmt) \
4614	do { \
4615	if (!(expr)) \
4616	{ \
4617	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4618	if (fStrictCpuIdChecks) \
4619	{ \
4620	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4621	RTStrFree(pszMsg); \
4622	return rcCpuid; \
4623	} \
4624	LogRel(("CPUM: %s\n", pszMsg)); \
4625	RTStrFree(pszMsg); \
4626	} \
4627	} while (0)
4628	#define CPUID_CHECK_WRN(expr, fmt) \
4629	do { \
4630	if (!(expr)) \
4631	LogRel(fmt); \
4632	} while (0)
4633
4634	/* For comparing two values and bitch if they differs. */
4635	#define CPUID_CHECK2_RET(what, host, saved) \
4636	do { \
4637	if ((host) != (saved)) \
4638	{ \
4639	if (fStrictCpuIdChecks) \
4640	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4641	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4642	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4643	} \
4644	} while (0)
4645	#define CPUID_CHECK2_WRN(what, host, saved) \
4646	do { \
4647	if ((host) != (saved)) \
4648	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4649	} while (0)
4650
4651	/* For checking raw cpu features (raw mode). */
4652	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4653	do { \
4654	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4655	{ \
4656	if (fStrictCpuIdChecks) \
4657	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4658	N_(#bit " mismatch: host=%d saved=%d"), \
4659	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4660	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4661	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4662	} \
4663	} while (0)
4664	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4665	do { \
4666	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4667	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4668	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4669	} while (0)
4670	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4671
4672	/* For checking guest features. */
4673	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4674	do { \
4675	if ( (aGuestCpuId##set [1].reg & bit) \
4676	&& !(aHostRaw##set [1].reg & bit) \
4677	&& !(aHostOverride##set [1].reg & bit) \
4678	) \
4679	{ \
4680	if (fStrictCpuIdChecks) \
4681	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4682	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4683	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4684	} \
4685	} while (0)
4686	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4687	do { \
4688	if ( (aGuestCpuId##set [1].reg & bit) \
4689	&& !(aHostRaw##set [1].reg & bit) \
4690	&& !(aHostOverride##set [1].reg & bit) \
4691	) \
4692	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4693	} while (0)
4694	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4695	do { \
4696	if ( (aGuestCpuId##set [1].reg & bit) \
4697	&& !(aHostRaw##set [1].reg & bit) \
4698	&& !(aHostOverride##set [1].reg & bit) \
4699	) \
4700	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4701	} while (0)
4702	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4703
4704	/* For checking guest features if AMD guest CPU. */
4705	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4706	do { \
4707	if ( (aGuestCpuId##set [1].reg & bit) \
4708	&& fGuestAmd \
4709	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4710	&& !(aHostOverride##set [1].reg & bit) \
4711	) \
4712	{ \
4713	if (fStrictCpuIdChecks) \
4714	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4715	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4716	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4717	} \
4718	} while (0)
4719	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4720	do { \
4721	if ( (aGuestCpuId##set [1].reg & bit) \
4722	&& fGuestAmd \
4723	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4724	&& !(aHostOverride##set [1].reg & bit) \
4725	) \
4726	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4727	} while (0)
4728	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4729	do { \
4730	if ( (aGuestCpuId##set [1].reg & bit) \
4731	&& fGuestAmd \
4732	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4733	&& !(aHostOverride##set [1].reg & bit) \
4734	) \
4735	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4736	} while (0)
4737	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4738
4739	/* For checking AMD features which have a corresponding bit in the standard
4740	range. (Intel defines very few bits in the extended feature sets.) */
4741	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4742	do { \
4743	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4744	&& !(fHostAmd \
4745	? aHostRawExt[1].reg & (ExtBit) \
4746	: aHostRawStd[1].reg & (StdBit)) \
4747	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4748	) \
4749	{ \
4750	if (fStrictCpuIdChecks) \
4751	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4752	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4753	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4754	} \
4755	} while (0)
4756	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4757	do { \
4758	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4759	&& !(fHostAmd \
4760	? aHostRawExt[1].reg & (ExtBit) \
4761	: aHostRawStd[1].reg & (StdBit)) \
4762	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4763	) \
4764	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4765	} while (0)
4766	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4767	do { \
4768	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4769	&& !(fHostAmd \
4770	? aHostRawExt[1].reg & (ExtBit) \
4771	: aHostRawStd[1].reg & (StdBit)) \
4772	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4773	) \
4774	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4775	} while (0)
4776	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4777
4778
4779	/*
4780	* Verify that we can support the features already exposed to the guest on
4781	* this host.
4782	*
4783	* Most of the features we're emulating requires intercepting instruction
4784	* and doing it the slow way, so there is no need to warn when they aren't
4785	* present in the host CPU. Thus we use IGN instead of EMU on these.
4786	*
4787	* Trailing comments:
4788	* "EMU" - Possible to emulate, could be lots of work and very slow.
4789	* "EMU?" - Can this be emulated?
4790	*/
4791	CPUMCPUID aGuestCpuIdStd[2];
4792	RT_ZERO(aGuestCpuIdStd);
4793	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4794
4795	/* CPUID(1).ecx */
4796	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4797	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4798	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4799	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4800	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4801	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4802	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4803	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4804	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4805	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4806	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4807	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4808	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4809	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4810	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4811	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4812	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4813	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4814	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4815	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4816	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4817	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4818	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4819	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4820	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4821	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4822	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4823	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4824	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4825	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4826	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4827	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4828
4829	/* CPUID(1).edx */
4830	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4831	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4832	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4833	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4834	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4835	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4836	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4837	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4838	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4839	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4840	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4841	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4842	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4843	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4844	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4845	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4846	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4847	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4848	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4849	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4850	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4851	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4852	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4853	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4854	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4855	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4856	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4857	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4858	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4859	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4860	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4861	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4862
4863	/* CPUID(0x80000000). */
4864	CPUMCPUID aGuestCpuIdExt[2];
4865	RT_ZERO(aGuestCpuIdExt);
4866	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4867	{
4868	/** @todo deal with no 0x80000001 on the host. */
4869	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
4870	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4871	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
4872	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4873
4874	/* CPUID(0x80000001).ecx */
4875	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4876	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4877	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4878	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4879	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4880	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4881	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4882	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4883	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4884	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4885	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4886	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4887	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4888	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4889	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4890	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4891	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4892	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4893	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4894	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4895	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4896	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4897	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4898	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4899	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4900	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4901	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4902	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4903	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4904	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4905	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4906	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4907
4908	/* CPUID(0x80000001).edx */
4909	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4910	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4911	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4912	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4913	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4914	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4915	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4916	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4917	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4918	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4919	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4920	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4921	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4922	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4923	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4924	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4925	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4926	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4927	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4928	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4929	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4930	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4931	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4932	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4933	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4934	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4935	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4936	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4937	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4938	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4939	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4940	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4941	}
4942
4943	/** @todo check leaf 7 */
4944
4945	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4946	* ECX=0: EAX - Valid bits in XCR0[31:0].
4947	* EBX - Maximum state size as per current XCR0 value.
4948	* ECX - Maximum state size for all supported features.
4949	* EDX - Valid bits in XCR0[63:32].
4950	* ECX=1: EAX - Various X-features.
4951	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4952	* ECX - Valid bits in IA32_XSS[31:0].
4953	* EDX - Valid bits in IA32_XSS[63:32].
4954	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4955	* if the bit invalid all four registers are set to zero.
4956	* EAX - The state size for this feature.
4957	* EBX - The state byte offset of this feature.
4958	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4959	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4960	*/
4961	uint64_t fGuestXcr0Mask = 0;
4962	PCPUMCPUIDLEAF pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4963	if ( pCurLeaf
4964	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4965	&& ( pCurLeaf->uEax
4966	\|\| pCurLeaf->uEbx
4967	\|\| pCurLeaf->uEcx
4968	\|\| pCurLeaf->uEdx) )
4969	{
4970	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4971	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4972	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4973	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4974	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4975	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4976	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4977	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4978
4979	/* We don't support any additional features yet. */
4980	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4981	if (pCurLeaf && pCurLeaf->uEax)
4982	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4983	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4984	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4985	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4986	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4987	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4988
4989
4990	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4991	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4992	{
4993	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4994	if (pCurLeaf)
4995	{
4996	/* If advertised, the state component offset and size must match the one used by host. */
4997	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4998	{
4999	CPUMCPUID RawHost;
5000	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5001	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5002	if ( RawHost.uEbx != pCurLeaf->uEbx
5003	\|\| RawHost.uEax != pCurLeaf->uEax)
5004	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5005	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5006	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5007	}
5008	}
5009	}
5010	#endif
5011	}
5012	/* Clear leaf 0xd just in case we're loading an old state... */
5013	else if (pCurLeaf)
5014	{
5015	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5016	{
5017	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5018	if (pCurLeaf)
5019	{
5020	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5021	\|\| ( pCurLeaf->uEax == 0
5022	&& pCurLeaf->uEbx == 0
5023	&& pCurLeaf->uEcx == 0
5024	&& pCurLeaf->uEdx == 0),
5025	("uVersion=%#x; %#x %#x %#x %#x\n",
5026	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5027	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5028	}
5029	}
5030	}
5031
5032	/* Update the fXStateGuestMask value for the VM. */
5033	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5034	{
5035	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5036	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5037	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5038	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5039	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5040	}
5041
5042	#undef CPUID_CHECK_RET
5043	#undef CPUID_CHECK_WRN
5044	#undef CPUID_CHECK2_RET
5045	#undef CPUID_CHECK2_WRN
5046	#undef CPUID_RAW_FEATURE_RET
5047	#undef CPUID_RAW_FEATURE_WRN
5048	#undef CPUID_RAW_FEATURE_IGN
5049	#undef CPUID_GST_FEATURE_RET
5050	#undef CPUID_GST_FEATURE_WRN
5051	#undef CPUID_GST_FEATURE_EMU
5052	#undef CPUID_GST_FEATURE_IGN
5053	#undef CPUID_GST_FEATURE2_RET
5054	#undef CPUID_GST_FEATURE2_WRN
5055	#undef CPUID_GST_FEATURE2_EMU
5056	#undef CPUID_GST_FEATURE2_IGN
5057	#undef CPUID_GST_AMD_FEATURE_RET
5058	#undef CPUID_GST_AMD_FEATURE_WRN
5059	#undef CPUID_GST_AMD_FEATURE_EMU
5060	#undef CPUID_GST_AMD_FEATURE_IGN
5061
5062	/*
5063	* We're good, commit the CPU ID leaves.
5064	*/
5065	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5066	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
5067	AssertLogRelRCReturn(rc, rc);
5068
5069	return VINF_SUCCESS;
5070	}
5071
5072
5073	/**
5074	* Loads the CPU ID leaves saved by pass 0, x86 targets.
5075	*
5076	* @returns VBox status code.
5077	* @param pVM The cross context VM structure.
5078	* @param pSSM The saved state handle.
5079	* @param uVersion The format version.
5080	* @param pMsrs The guest MSRs.
5081	*/
5082	int cpumR3LoadCpuIdX86(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
5083	{
5084	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5085
5086	/*
5087	* Load the CPUID leaves array first and call worker to do the rest, just so
5088	* we can free the memory when we need to without ending up in column 1000.
5089	*/
5090	PCPUMCPUIDLEAF paLeaves;
5091	uint32_t cLeaves;
5092	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5093	AssertRC(rc);
5094	if (RT_SUCCESS(rc))
5095	{
5096	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
5097	RTMemFree(paLeaves);
5098	}
5099	return rc;
5100	}
5101
5102
5103
5104	/**
5105	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5106	*
5107	* @returns VBox status code.
5108	* @param pVM The cross context VM structure.
5109	* @param pSSM The saved state handle.
5110	* @param uVersion The format version.
5111	*/
5112	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5113	{
5114	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5115
5116	/*
5117	* Restore the CPUID leaves.
5118	*
5119	* Note that we support restoring less than the current amount of standard
5120	* leaves because we've been allowed more is newer version of VBox.
5121	*/
5122	uint32_t cElements;
5123	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5124	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5125	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5126	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5127
5128	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5129	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5130	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5131	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5132
5133	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5134	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5135	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5136	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5137
5138	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5139
5140	/*
5141	* Check that the basic cpuid id information is unchanged.
5142	*/
5143	/** @todo we should check the 64 bits capabilities too! */
5144	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5145	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5146	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5147	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5148	#endif
5149	uint32_t au32CpuIdSaved[8];
5150	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5151	if (RT_SUCCESS(rc))
5152	{
5153	/* Ignore CPU stepping. */
5154	au32CpuId[4] &= 0xfffffff0;
5155	au32CpuIdSaved[4] &= 0xfffffff0;
5156
5157	/* Ignore APIC ID (AMD specs). */
5158	au32CpuId[5] &= ~0xff000000;
5159	au32CpuIdSaved[5] &= ~0xff000000;
5160
5161	/* Ignore the number of Logical CPUs (AMD specs). */
5162	au32CpuId[5] &= ~0x00ff0000;
5163	au32CpuIdSaved[5] &= ~0x00ff0000;
5164
5165	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5166	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5167	\| X86_CPUID_FEATURE_ECX_VMX
5168	\| X86_CPUID_FEATURE_ECX_SMX
5169	\| X86_CPUID_FEATURE_ECX_EST
5170	\| X86_CPUID_FEATURE_ECX_TM2
5171	\| X86_CPUID_FEATURE_ECX_CNTXID
5172	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5173	\| X86_CPUID_FEATURE_ECX_PDCM
5174	\| X86_CPUID_FEATURE_ECX_DCA
5175	\| X86_CPUID_FEATURE_ECX_X2APIC
5176	);
5177	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5178	\| X86_CPUID_FEATURE_ECX_VMX
5179	\| X86_CPUID_FEATURE_ECX_SMX
5180	\| X86_CPUID_FEATURE_ECX_EST
5181	\| X86_CPUID_FEATURE_ECX_TM2
5182	\| X86_CPUID_FEATURE_ECX_CNTXID
5183	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5184	\| X86_CPUID_FEATURE_ECX_PDCM
5185	\| X86_CPUID_FEATURE_ECX_DCA
5186	\| X86_CPUID_FEATURE_ECX_X2APIC
5187	);
5188
5189	/* Make sure we don't forget to update the masks when enabling
5190	* features in the future.
5191	*/
5192	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5193	( X86_CPUID_FEATURE_ECX_DTES64
5194	\| X86_CPUID_FEATURE_ECX_VMX
5195	\| X86_CPUID_FEATURE_ECX_SMX
5196	\| X86_CPUID_FEATURE_ECX_EST
5197	\| X86_CPUID_FEATURE_ECX_TM2
5198	\| X86_CPUID_FEATURE_ECX_CNTXID
5199	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5200	\| X86_CPUID_FEATURE_ECX_PDCM
5201	\| X86_CPUID_FEATURE_ECX_DCA
5202	\| X86_CPUID_FEATURE_ECX_X2APIC
5203	)));
5204	/* do the compare */
5205	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5206	{
5207	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5208	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5209	"Saved=%.*Rhxs\n"
5210	"Real =%.*Rhxs\n",
5211	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5212	sizeof(au32CpuId), au32CpuId));
5213	else
5214	{
5215	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5216	"Saved=%.*Rhxs\n"
5217	"Real =%.*Rhxs\n",
5218	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5219	sizeof(au32CpuId), au32CpuId));
5220	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5221	}
5222	}
5223	}
5224
5225	return rc;
5226	}
5227
5228
5229
5230	/*
5231	*
5232	*
5233	* CPUID Info Handler.
5234	* CPUID Info Handler.
5235	* CPUID Info Handler.
5236	*
5237	*
5238	*/
5239
5240
5241
5242	/**
5243	* Get L1 cache / TLS associativity.
5244	*/
5245	static const char getCacheAss(unsigned u, char pszBuf)
5246	{
5247	if (u == 0)
5248	return "res0 ";
5249	if (u == 1)
5250	return "direct";
5251	if (u == 255)
5252	return "fully";
5253	if (u >= 256)
5254	return "???";
5255
5256	RTStrPrintf(pszBuf, 16, "%d way", u);
5257	return pszBuf;
5258	}
5259
5260
5261	/**
5262	* Get L2/L3 cache associativity.
5263	*/
5264	static const char *getL23CacheAss(unsigned u)
5265	{
5266	switch (u)
5267	{
5268	case 0: return "off ";
5269	case 1: return "direct";
5270	case 2: return "2 way ";
5271	case 3: return "3 way ";
5272	case 4: return "4 way ";
5273	case 5: return "6 way ";
5274	case 6: return "8 way ";
5275	case 7: return "res7 ";
5276	case 8: return "16 way";
5277	case 9: return "tpoext"; /* Overridden by Fn8000_001D */
5278	case 10: return "32 way";
5279	case 11: return "48 way";
5280	case 12: return "64 way";
5281	case 13: return "96 way";
5282	case 14: return "128way";
5283	case 15: return "fully ";
5284	default: return "????";
5285	}
5286	}
5287
5288
5289	/** CPUID(1).EDX field descriptions. */
5290	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5291	{
5292	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5293	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5294	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5295	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5296	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5297	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5298	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5299	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5300	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5301	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5302	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5303	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5304	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5305	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5306	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5307	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5308	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5309	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5310	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5311	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5312	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5313	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5314	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5315	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5316	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5317	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5318	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5319	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5320	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5321	DBGFREGSUBFIELD_TERMINATOR()
5322	};
5323
5324	/** CPUID(1).ECX field descriptions. */
5325	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5326	{
5327	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5328	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5329	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5330	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5331	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5332	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5333	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5334	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5335	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5336	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5337	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5338	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5339	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5340	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5341	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5342	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5343	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5344	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5345	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5346	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5347	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5348	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5349	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5350	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5351	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5352	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5353	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5354	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5355	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5356	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5357	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5358	DBGFREGSUBFIELD_TERMINATOR()
5359	};
5360
5361	/** CPUID(7,0).EBX field descriptions. */
5362	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5363	{
5364	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5365	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5366	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
5367	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5368	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5369	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5370	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
5371	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5372	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5373	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5374	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5375	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5376	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5377	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5378	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5379	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5380	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5381	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5382	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5383	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5384	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5385	DBGFREGSUBFIELD_RO("CLWB\0" "CLWB instruction", 24, 1, 0),
5386	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5387	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5388	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5389	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5390	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5391	DBGFREGSUBFIELD_TERMINATOR()
5392	};
5393
5394	/** CPUID(7,0).ECX field descriptions. */
5395	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5396	{
5397	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5398	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
5399	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5400	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
5401	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
5402	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
5403	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
5404	DBGFREGSUBFIELD_TERMINATOR()
5405	};
5406
5407	/** CPUID(7,0).EDX field descriptions. */
5408	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
5409	{
5410	DBGFREGSUBFIELD_RO("MCU_OPT_CTRL\0" "Supports IA32_MCU_OPT_CTRL ", 9, 1, 0),
5411	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
5412	DBGFREGSUBFIELD_RO("TSX_FORCE_ABORT\0" "Supports IA32_TSX_FORCE_ABORT", 11, 1, 0),
5413	DBGFREGSUBFIELD_RO("CET_IBT\0" "Supports indirect branch tracking w/ CET", 20, 1, 0),
5414	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
5415	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
5416	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
5417	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
5418	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
5419	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
5420	DBGFREGSUBFIELD_TERMINATOR()
5421	};
5422
5423
5424	/** CPUID(7,2).EBX field descriptions. */
5425	static DBGFREGSUBFIELD const g_aLeaf7Sub2EbxSubFields[] =
5426	{
5427	DBGFREGSUBFIELD_TERMINATOR()
5428	};
5429
5430	/** CPUID(7,2).ECX field descriptions. */
5431	static DBGFREGSUBFIELD const g_aLeaf7Sub2EcxSubFields[] =
5432	{
5433	DBGFREGSUBFIELD_TERMINATOR()
5434	};
5435
5436	/** CPUID(7,2).EDX field descriptions. */
5437	static DBGFREGSUBFIELD const g_aLeaf7Sub2EdxSubFields[] =
5438	{
5439	DBGFREGSUBFIELD_RO("PSFD\0" "Supports IA32_SPEC_CTRL[7] (PSFD)", 0, 1, 0),
5440	DBGFREGSUBFIELD_RO("IPRED_CTRL\0" "Supports IA32_SPEC_CTRL[4:3] (IPRED_DIS)", 1, 1, 0),
5441	DBGFREGSUBFIELD_RO("RRSBA_CTRL\0" "Supports IA32_SPEC_CTRL[6:5] (RRSBA_DIS)", 2, 1, 0),
5442	DBGFREGSUBFIELD_RO("DDPD_U\0" "Supports IA32_SPEC_CTRL[8] (DDPD_U)", 3, 1, 0),
5443	DBGFREGSUBFIELD_RO("BHI_CTRL\0" "Supports IA32_SPEC_CTRL[10] (BHI_DIS_S) ", 4, 1, 0),
5444	DBGFREGSUBFIELD_RO("MCDT_NO\0" "No MXCSR Config Dependent Timing issues", 5, 1, 0),
5445	DBGFREGSUBFIELD_RO("UC_LOCK_DIS\0" "Supports UC-lock disable and causing #AC", 6, 1, 0),
5446	DBGFREGSUBFIELD_RO("MONITOR_MITG_NO\0" "No MONITOR/UMONITOR power issues", 7, 1, 0),
5447	DBGFREGSUBFIELD_TERMINATOR()
5448	};
5449
5450
5451	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5452	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5453	{
5454	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5455	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5456	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5457	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5458	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5459	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5460	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5461	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5462	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5463	DBGFREGSUBFIELD_TERMINATOR()
5464	};
5465
5466	/** CPUID(13,1).EAX field descriptions. */
5467	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5468	{
5469	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5470	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5471	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5472	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5473	DBGFREGSUBFIELD_TERMINATOR()
5474	};
5475
5476
5477	/** CPUID(0x80000001,0).EDX field descriptions. */
5478	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5479	{
5480	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5481	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5482	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5483	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5484	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5485	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5486	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5487	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5488	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5489	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5490	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5491	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5492	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5493	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5494	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5495	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5496	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5497	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5498	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5499	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5500	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5501	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5502	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5503	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5504	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5505	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5506	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5507	DBGFREGSUBFIELD_TERMINATOR()
5508	};
5509
5510	/** CPUID(0x80000001,0).ECX field descriptions. */
5511	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5512	{
5513	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5514	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5515	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
5516	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5517	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5518	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5519	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5520	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5521	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5522	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5523	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5524	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5525	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5526	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5527	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5528	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5529	DBGFREGSUBFIELD_RO("TCE\0" "Translation Cache Extension support", 17, 1, 0),
5530	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5531	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5532	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5533	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
5534	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
5535	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
5536	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
5537	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
5538	DBGFREGSUBFIELD_RO("MONITORX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
5539	DBGFREGSUBFIELD_RO("AddrMaskExt\0" "BP Addressing masking extended to bit 31", 30, 1, 0),
5540	DBGFREGSUBFIELD_TERMINATOR()
5541	};
5542
5543	/** CPUID(0x8000000a,0).EDX field descriptions. */
5544	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
5545	{
5546	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
5547	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
5548	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
5549	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
5550	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
5551	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
5552	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
5553	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
5554	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
5555	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
5556	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
5557	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
5558	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
5559	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
5560	DBGFREGSUBFIELD_RO("x2AVIC\0" "AVIC support for x2APIC mode", 18, 1, 0),
5561	DBGFREGSUBFIELD_RO("SSSCheck\0" "SVM supervisor shadow stack restrictions", 19, 1, 0),
5562	DBGFREGSUBFIELD_RO("SpecCtrl\0" "SPEC_CTRL virtualization", 20, 1, 0),
5563	DBGFREGSUBFIELD_RO("ROGPT\0" "Read-Only Guest Page Table feature support", 21, 1, 0),
5564	DBGFREGSUBFIELD_RO("HOST_MCE_OVERRIDE\0" "Guest #MC can be intercepted", 23, 1, 0),
5565	DBGFREGSUBFIELD_RO("TlbiCtl\0" "INVLPGB/TLBSYNC enable and intercept", 24, 1, 0),
5566	DBGFREGSUBFIELD_RO("VNMI\0" "NMI Virtualization", 25, 1, 0),
5567	DBGFREGSUBFIELD_RO("IbsVirt\0" "IBS Virtualization", 26, 1, 0),
5568	DBGFREGSUBFIELD_RO("ExtLvtAvicAccessChg\0" "Extended LVT AVIC access changes", 27, 1, 0),
5569	DBGFREGSUBFIELD_RO("NestedVirtVmcbAddrChk\0""Guest VMCB address check", 28, 1, 0),
5570	DBGFREGSUBFIELD_RO("BusLockThreshold\0" "Bus Lock Threshold", 29, 1, 0),
5571	DBGFREGSUBFIELD_TERMINATOR()
5572	};
5573
5574
5575	/** CPUID(0x80000007,0).EDX field descriptions. */
5576	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
5577	{
5578	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
5579	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
5580	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
5581	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
5582	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
5583	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
5584	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
5585	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
5586	DBGFREGSUBFIELD_RO("CPB\0" "Core Performance Boost", 9, 1, 0),
5587	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
5588	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
5589	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
5590	DBGFREGSUBFIELD_RO("ConnectedStandby\0" "Connected Standby", 13, 1, 0),
5591	DBGFREGSUBFIELD_RO("RAPL\0" "Running average power limit", 14, 1, 0),
5592	DBGFREGSUBFIELD_TERMINATOR()
5593	};
5594
5595	/** CPUID(0x80000008,0).EBX field descriptions. */
5596	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
5597	{
5598	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
5599	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
5600	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR)", 2, 1, 0),
5601	DBGFREGSUBFIELD_RO("INVLPGB\0" "INVLPGB and TLBSYNC instructions", 3, 1, 0),
5602	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
5603	DBGFREGSUBFIELD_RO("BE\0" "Bandwidth Enforcement extension", 6, 1, 0),
5604	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
5605	DBGFREGSUBFIELD_RO("WBNOINVD\0" "WBNOINVD instruction", 9, 1, 0),
5606	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
5607	DBGFREGSUBFIELD_RO("INT_WBINVD\0" "WBINVD/WBNOINVD interruptible", 13, 1, 0),
5608	DBGFREGSUBFIELD_RO("IBRS\0" "Indirect Branch Restricted Speculation", 14, 1, 0),
5609	DBGFREGSUBFIELD_RO("STIBP\0" "Single Thread Indirect Branch Prediction", 15, 1, 0),
5610	DBGFREGSUBFIELD_RO("IbrsAlwaysOn\0" "Processor prefers that IBRS be left on", 16, 1, 0),
5611	DBGFREGSUBFIELD_RO("StibpAlwaysOn\0""Processor prefers that STIBP be left on", 17, 1, 0),
5612	DBGFREGSUBFIELD_RO("IbrsPreferred\0""IBRS preferred over software solution", 18, 1, 0),
5613	DBGFREGSUBFIELD_RO("IbrsSameMode\0" "IBRS limits same mode speculation", 19, 1, 0),
5614	DBGFREGSUBFIELD_RO("EferLmsleUnsupported\0" "EFER.LMSLE is unsupported", 20, 1, 0),
5615	DBGFREGSUBFIELD_RO("INVLPGBnestedPages\0" "INVLPGB for nested translation", 21, 1, 0),
5616	DBGFREGSUBFIELD_RO("SSBD\0" "Speculative Store Bypass Disable", 24, 1, 0),
5617	DBGFREGSUBFIELD_RO("SsbdVirtSpecCtrl\0" "Use VIRT_SPEC_CTL for SSBD", 25, 1, 0),
5618	DBGFREGSUBFIELD_RO("SsbdNotRequired\0" "SSBD not needed on this processor", 26, 1, 0),
5619	DBGFREGSUBFIELD_RO("CPPC\0" "Collaborative Processor Performance Control", 27, 1, 0),
5620	DBGFREGSUBFIELD_RO("PSFD\0" "Predictive Store Forward Disable", 28, 1, 0),
5621	DBGFREGSUBFIELD_RO("BTC_NO\0" "Unaffected by branch type confusion", 29, 1, 0),
5622	DBGFREGSUBFIELD_RO("IBPB_RET\0" "Clears RA predictor when PRED_CMD.IBPB set", 30, 1, 0),
5623	DBGFREGSUBFIELD_TERMINATOR()
5624	};
5625
5626
5627	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5628	const char *pszLeadIn, uint32_t cchWidth)
5629	{
5630	if (pszLeadIn)
5631	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5632
5633	for (uint32_t iBit = 0; iBit < 32; iBit++)
5634	if (RT_BIT_32(iBit) & uVal)
5635	{
5636	while ( pDesc->pszName != NULL
5637	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5638	pDesc++;
5639	if ( pDesc->pszName != NULL
5640	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5641	{
5642	if (pDesc->cBits == 1)
5643	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5644	else
5645	{
5646	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5647	if (pDesc->cBits < 32)
5648	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5649	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5650	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5651	}
5652	}
5653	else
5654	pHlp->pfnPrintf(pHlp, " %u", iBit);
5655	}
5656	if (pszLeadIn)
5657	pHlp->pfnPrintf(pHlp, "\n");
5658	}
5659
5660
5661	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5662	const char *pszLeadIn, uint32_t cchWidth)
5663	{
5664	if (pszLeadIn)
5665	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5666
5667	for (uint32_t iBit = 0; iBit < 64; iBit++)
5668	if (RT_BIT_64(iBit) & uVal)
5669	{
5670	while ( pDesc->pszName != NULL
5671	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5672	pDesc++;
5673	if ( pDesc->pszName != NULL
5674	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5675	{
5676	if (pDesc->cBits == 1)
5677	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5678	else
5679	{
5680	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5681	if (pDesc->cBits < 64)
5682	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5683	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5684	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5685	}
5686	}
5687	else
5688	pHlp->pfnPrintf(pHlp, " %u", iBit);
5689	}
5690	if (pszLeadIn)
5691	pHlp->pfnPrintf(pHlp, "\n");
5692	}
5693
5694
5695	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5696	const char *pszLeadIn, uint32_t cchWidth)
5697	{
5698	if (!uVal)
5699	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5700	else
5701	{
5702	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5703	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5704	pHlp->pfnPrintf(pHlp, " )\n");
5705	}
5706	}
5707
5708
5709	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5710	uint32_t cchWidth)
5711	{
5712	uint32_t uCombined = uVal1 \| uVal2;
5713	for (uint32_t iBit = 0; iBit < 32; iBit++)
5714	if ( (RT_BIT_32(iBit) & uCombined)
5715	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5716	{
5717	while ( pDesc->pszName != NULL
5718	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5719	pDesc++;
5720
5721	if ( pDesc->pszName != NULL
5722	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5723	{
5724	size_t cchMnemonic = strlen(pDesc->pszName);
5725	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5726	size_t cchDesc = strlen(pszDesc);
5727	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5728	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5729	if (pDesc->cBits < 32)
5730	{
5731	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5732	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5733	}
5734
5735	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5736	pDesc->pszName, pszDesc,
5737	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5738	uFieldValue1, uFieldValue2);
5739
5740	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5741	pDesc++;
5742	}
5743	else
5744	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5745	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5746	}
5747	}
5748
5749
5750	/**
5751	* Produces a detailed summary of standard leaf 0x00000001.
5752	*
5753	* @param pHlp The info helper functions.
5754	* @param pCurLeaf The 0x00000001 leaf.
5755	* @param fVerbose Whether to be very verbose or not.
5756	* @param fIntel Set if intel CPU.
5757	*/
5758	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5759	{
5760	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5761	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5762	uint32_t uEAX = pCurLeaf->uEax;
5763	uint32_t uEBX = pCurLeaf->uEbx;
5764
5765	pHlp->pfnPrintf(pHlp,
5766	"%36s %2d \tExtended: %d \tEffective: %d\n"
5767	"%36s %2d \tExtended: %d \tEffective: %d\n"
5768	"%36s %d\n"
5769	"%36s %d (%s)\n"
5770	"%36s %#04x\n"
5771	"%36s %d\n"
5772	"%36s %d\n"
5773	"%36s %#04x\n"
5774	,
5775	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5776	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5777	"Stepping:", RTX86GetCpuStepping(uEAX),
5778	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5779	"APIC ID:", (uEBX >> 24) & 0xff,
5780	"Logical CPUs:",(uEBX >> 16) & 0xff,
5781	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5782	"Brand ID:", (uEBX >> 0) & 0xff);
5783	if (fVerbose)
5784	{
5785	CPUMCPUID Host = {0};
5786	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5787	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5788	#endif
5789	pHlp->pfnPrintf(pHlp, "Features\n");
5790	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5791	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5792	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5793	}
5794	else
5795	{
5796	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5797	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5798	}
5799	}
5800
5801
5802	/**
5803	* Produces a detailed summary of standard leaf 0x00000007.
5804	*
5805	* @param pHlp The info helper functions.
5806	* @param paLeaves The CPUID leaves array.
5807	* @param cLeaves The number of leaves in the array.
5808	* @param pCurLeaf The first 0x00000007 leaf.
5809	* @param fVerbose Whether to be very verbose or not.
5810	*/
5811	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5812	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5813	{
5814	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5815	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5816	for (;;)
5817	{
5818	CPUMCPUID Host = {0};
5819	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5820	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5821	#endif
5822
5823	switch (pCurLeaf->uSubLeaf)
5824	{
5825	case 0:
5826	if (fVerbose)
5827	{
5828	pHlp->pfnPrintf(pHlp, " Sub-leaf 0\n");
5829	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5830	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5831	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5832	if (pCurLeaf->uEdx \|\| Host.uEdx)
5833	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
5834	}
5835	else
5836	{
5837	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features #0 EBX:", 36);
5838	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features #0 ECX:", 36);
5839	if (pCurLeaf->uEdx)
5840	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features #0 EDX:", 36);
5841	}
5842	break;
5843
5844	/** @todo case 1 */
5845
5846	case 2:
5847	if (fVerbose)
5848	{
5849	pHlp->pfnPrintf(pHlp, " Sub-leaf 2\n");
5850	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5851	if (pCurLeaf->uEbx \|\| Host.uEbx)
5852	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub2EbxSubFields, 56);
5853	if (pCurLeaf->uEcx \|\| Host.uEcx)
5854	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub2EcxSubFields, 56);
5855	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub2EdxSubFields, 56);
5856	}
5857	else
5858	{
5859	if (pCurLeaf->uEbx)
5860	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub2EbxSubFields, "Ext Features #2 EBX:", 36);
5861	if (pCurLeaf->uEcx)
5862	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub2EcxSubFields, "Ext Features #2 ECX:", 36);
5863	if (pCurLeaf->uEdx)
5864	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub2EdxSubFields, "Ext Features #2 EDX:", 36);
5865	}
5866	break;
5867
5868	default:
5869	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5870	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5871	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5872	break;
5873
5874	}
5875
5876	/* advance. */
5877	pCurLeaf++;
5878	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5879	\|\| pCurLeaf->uLeaf != 0x7)
5880	break;
5881	}
5882	}
5883
5884
5885	/**
5886	* Produces a detailed summary of standard leaf 0x0000000d.
5887	*
5888	* @param pHlp The info helper functions.
5889	* @param paLeaves The CPUID leaves array.
5890	* @param cLeaves The number of leaves in the array.
5891	* @param pCurLeaf The first 0x00000007 leaf.
5892	* @param fVerbose Whether to be very verbose or not.
5893	*/
5894	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5895	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5896	{
5897	RT_NOREF_PV(fVerbose);
5898	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5899	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5900	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5901	{
5902	CPUMCPUID Host = {0};
5903	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5904	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5905	#endif
5906
5907	switch (uSubLeaf)
5908	{
5909	case 0:
5910	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5911	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5912	pCurLeaf->uEbx, pCurLeaf->uEcx);
5913	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5914
5915	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5916	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5917	"Valid XCR0 bits, guest:", 42);
5918	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5919	"Valid XCR0 bits, host:", 42);
5920	break;
5921
5922	case 1:
5923	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5924	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5925	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5926
5927	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5928	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5929	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5930
5931	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5932	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5933	" Valid IA32_XSS bits, guest:", 42);
5934	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5935	" Valid IA32_XSS bits, host:", 42);
5936	break;
5937
5938	default:
5939	if ( pCurLeaf
5940	&& pCurLeaf->uSubLeaf == uSubLeaf
5941	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5942	{
5943	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5944	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5945	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5946	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5947	if (pCurLeaf->uEdx)
5948	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5949	pHlp->pfnPrintf(pHlp, " --");
5950	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5951	pHlp->pfnPrintf(pHlp, "\n");
5952	}
5953	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5954	{
5955	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5956	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5957	if (Host.uEcx & ~RT_BIT_32(0))
5958	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5959	if (Host.uEdx)
5960	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5961	pHlp->pfnPrintf(pHlp, " --");
5962	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5963	pHlp->pfnPrintf(pHlp, "\n");
5964	}
5965	break;
5966
5967	}
5968
5969	/* advance. */
5970	if (pCurLeaf)
5971	{
5972	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5973	&& pCurLeaf->uSubLeaf <= uSubLeaf
5974	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5975	pCurLeaf++;
5976	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5977	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5978	pCurLeaf = NULL;
5979	}
5980	}
5981	}
5982
5983
5984	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5985	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5986	{
5987	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5988	&& pCurLeaf->uLeaf <= uUpToLeaf)
5989	{
5990	pHlp->pfnPrintf(pHlp,
5991	" %s\n"
5992	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5993	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5994	&& pCurLeaf->uLeaf <= uUpToLeaf)
5995	{
5996	CPUMCPUID Host = {0};
5997	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5998	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5999	#endif
6000	pHlp->pfnPrintf(pHlp,
6001	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6002	"Hst: %08x %08x %08x %08x\n",
6003	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6004	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6005	pCurLeaf++;
6006	}
6007	}
6008
6009	return pCurLeaf;
6010	}
6011
6012
6013	/**
6014	* Display the guest CpuId leaves.
6015	*
6016	* @param pVM The cross context VM structure.
6017	* @param pHlp The info helper functions.
6018	* @param pszArgs "terse", "default" or "verbose".
6019	*/
6020	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6021	{
6022	/*
6023	* Parse the argument.
6024	*/
6025	unsigned iVerbosity = 1;
6026	if (pszArgs)
6027	{
6028	pszArgs = RTStrStripL(pszArgs);
6029	if (!strcmp(pszArgs, "terse"))
6030	iVerbosity--;
6031	else if (!strcmp(pszArgs, "verbose"))
6032	iVerbosity++;
6033	}
6034
6035	uint32_t uLeaf;
6036	CPUMCPUID Host = {0};
6037	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6038	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6039	PCCPUMCPUIDLEAF pCurLeaf;
6040	PCCPUMCPUIDLEAF pNextLeaf;
6041	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6042	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6043	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6044
6045	/*
6046	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6047	*/
6048	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6049	uint32_t cHstMax = ASMCpuId_EAX(0);
6050	#else
6051	uint32_t cHstMax = 0;
6052	#endif
6053	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6054	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6055	pHlp->pfnPrintf(pHlp,
6056	" Raw Standard CPUID Leaves\n"
6057	" Leaf/sub-leaf eax ebx ecx edx\n");
6058	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6059	{
6060	uint32_t cMaxSubLeaves = 1;
6061	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6062	cMaxSubLeaves = 16;
6063	else if (uLeaf == 0xd)
6064	cMaxSubLeaves = 128;
6065
6066	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6067	{
6068	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6069	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6070	#endif
6071	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6072	&& pCurLeaf->uLeaf == uLeaf
6073	&& pCurLeaf->uSubLeaf == uSubLeaf)
6074	{
6075	pHlp->pfnPrintf(pHlp,
6076	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6077	"Hst: %08x %08x %08x %08x\n",
6078	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6079	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6080	pCurLeaf++;
6081	}
6082	else if ( uLeaf != 0xd
6083	\|\| uSubLeaf <= 1
6084	\|\| Host.uEbx != 0 )
6085	pHlp->pfnPrintf(pHlp,
6086	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6087	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6088
6089	/* Done? */
6090	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6091	\|\| pCurLeaf->uLeaf != uLeaf)
6092	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6093	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6094	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6095	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6096	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6097	)
6098	)
6099	break;
6100	}
6101	}
6102	pNextLeaf = pCurLeaf;
6103
6104	/*
6105	* If verbose, decode it.
6106	*/
6107	if (iVerbosity && paLeaves[0].uLeaf == 0)
6108	pHlp->pfnPrintf(pHlp,
6109	"%36s %.04s%.04s%.04s\n"
6110	"%36s 0x00000000-%#010x\n"
6111	,
6112	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6113	"Supports:", paLeaves[0].uEax);
6114
6115	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6116	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6117
6118	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6119	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6120
6121	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6122	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6123
6124	pCurLeaf = pNextLeaf;
6125
6126	/*
6127	* Hypervisor leaves.
6128	*
6129	* Unlike most of the other leaves reported, the guest hypervisor leaves
6130	* aren't a subset of the host CPUID bits.
6131	*/
6132	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6133
6134	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6135	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6136	#endif
6137	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6138	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6139	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6140	cMax = RT_MAX(cHstMax, cGstMax);
6141	if (cMax >= UINT32_C(0x40000000))
6142	{
6143	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6144
6145	/** @todo dump these in more detail. */
6146
6147	pCurLeaf = pNextLeaf;
6148	}
6149
6150
6151	/*
6152	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6153	* Implemented after AMD specs.
6154	*/
6155	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6156
6157	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6158	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6159	#endif
6160	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6161	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6162	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6163	cMax = RT_MAX(cHstMax, cGstMax);
6164	if (cMax >= UINT32_C(0x80000000))
6165	{
6166
6167	pHlp->pfnPrintf(pHlp,
6168	" Raw Extended CPUID Leaves\n"
6169	" Leaf/sub-leaf eax ebx ecx edx\n");
6170	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6171	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6172	{
6173	uint32_t cMaxSubLeaves = 1;
6174	if (uLeaf == UINT32_C(0x8000001d))
6175	cMaxSubLeaves = 16;
6176
6177	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6178	{
6179	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6180	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6181	#endif
6182	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6183	&& pCurLeaf->uLeaf == uLeaf
6184	&& pCurLeaf->uSubLeaf == uSubLeaf)
6185	{
6186	pHlp->pfnPrintf(pHlp,
6187	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6188	"Hst: %08x %08x %08x %08x\n",
6189	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6190	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6191	pCurLeaf++;
6192	}
6193	else if ( uLeaf != 0xd
6194	\|\| uSubLeaf <= 1
6195	\|\| Host.uEbx != 0 )
6196	pHlp->pfnPrintf(pHlp,
6197	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6198	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6199
6200	/* Done? */
6201	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6202	\|\| pCurLeaf->uLeaf != uLeaf)
6203	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6204	break;
6205	}
6206	}
6207	pNextLeaf = pCurLeaf;
6208
6209	/*
6210	* Understandable output
6211	*/
6212	if (iVerbosity)
6213	pHlp->pfnPrintf(pHlp,
6214	"Ext Name: %.4s%.4s%.4s\n"
6215	"Ext Supports: 0x80000000-%#010x\n",
6216	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6217
6218	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6219	if (iVerbosity && pCurLeaf)
6220	{
6221	uint32_t uEAX = pCurLeaf->uEax;
6222	pHlp->pfnPrintf(pHlp,
6223	"Family: %d \tExtended: %d \tEffective: %d\n"
6224	"Model: %d \tExtended: %d \tEffective: %d\n"
6225	"Stepping: %d\n"
6226	"Brand ID: %#05x\n",
6227	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
6228	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
6229	RTX86GetCpuStepping(uEAX),
6230	pCurLeaf->uEbx & 0xfff);
6231
6232	if (iVerbosity == 1)
6233	{
6234	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6235	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6236	}
6237	else
6238	{
6239	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6240	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6241	#endif
6242	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6243	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6244	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6245	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6246	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6247	{
6248	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6249	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6250	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6251	#endif
6252	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6253	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6254	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6255	}
6256	}
6257	}
6258
6259	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6260	{
6261	char szString[443+1] = {0};
6262	uint32_t pu32 = (uint32_t )szString;
6263	*pu32++ = pCurLeaf->uEax;
6264	*pu32++ = pCurLeaf->uEbx;
6265	*pu32++ = pCurLeaf->uEcx;
6266	*pu32++ = pCurLeaf->uEdx;
6267	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6268	if (pCurLeaf)
6269	{
6270	*pu32++ = pCurLeaf->uEax;
6271	*pu32++ = pCurLeaf->uEbx;
6272	*pu32++ = pCurLeaf->uEcx;
6273	*pu32++ = pCurLeaf->uEdx;
6274	}
6275	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6276	if (pCurLeaf)
6277	{
6278	*pu32++ = pCurLeaf->uEax;
6279	*pu32++ = pCurLeaf->uEbx;
6280	*pu32++ = pCurLeaf->uEcx;
6281	*pu32++ = pCurLeaf->uEdx;
6282	}
6283	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6284	}
6285
6286	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6287	{
6288	uint32_t uEAX = pCurLeaf->uEax;
6289	uint32_t uEBX = pCurLeaf->uEbx;
6290	uint32_t uECX = pCurLeaf->uEcx;
6291	uint32_t uEDX = pCurLeaf->uEdx;
6292	char sz1[32];
6293	char sz2[32];
6294
6295	pHlp->pfnPrintf(pHlp,
6296	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6297	"TLB 2/4M Data: %s %3d entries\n",
6298	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6299	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6300	pHlp->pfnPrintf(pHlp,
6301	"TLB 4K Instr/Uni: %s %3d entries\n"
6302	"TLB 4K Data: %s %3d entries\n",
6303	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6304	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6305	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6306	"L1 Instr Cache Lines Per Tag: %d\n"
6307	"L1 Instr Cache Associativity: %s\n"
6308	"L1 Instr Cache Size: %d KB\n",
6309	(uEDX >> 0) & 0xff,
6310	(uEDX >> 8) & 0xff,
6311	getCacheAss((uEDX >> 16) & 0xff, sz1),
6312	(uEDX >> 24) & 0xff);
6313	pHlp->pfnPrintf(pHlp,
6314	"L1 Data Cache Line Size: %d bytes\n"
6315	"L1 Data Cache Lines Per Tag: %d\n"
6316	"L1 Data Cache Associativity: %s\n"
6317	"L1 Data Cache Size: %d KB\n",
6318	(uECX >> 0) & 0xff,
6319	(uECX >> 8) & 0xff,
6320	getCacheAss((uECX >> 16) & 0xff, sz1),
6321	(uECX >> 24) & 0xff);
6322	}
6323
6324	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6325	{
6326	uint32_t uEAX = pCurLeaf->uEax;
6327	uint32_t uEBX = pCurLeaf->uEbx;
6328	uint32_t uECX = pCurLeaf->uEcx;
6329	uint32_t uEDX = pCurLeaf->uEdx;
6330
6331	pHlp->pfnPrintf(pHlp,
6332	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6333	"L2 TLB 2/4M Data: %s %4d entries\n",
6334	getL23CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6335	getL23CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6336	pHlp->pfnPrintf(pHlp,
6337	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6338	"L2 TLB 4K Data: %s %4d entries\n",
6339	getL23CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6340	getL23CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6341	pHlp->pfnPrintf(pHlp,
6342	"L2 Cache Line Size: %d bytes\n"
6343	"L2 Cache Lines Per Tag: %d\n"
6344	"L2 Cache Associativity: %s\n"
6345	"L2 Cache Size: %d KB\n",
6346	(uECX >> 0) & 0xff,
6347	(uECX >> 8) & 0xf,
6348	getL23CacheAss((uECX >> 12) & 0xf),
6349	(uECX >> 16) & 0xffff);
6350	pHlp->pfnPrintf(pHlp,
6351	"L3 Cache Line Size: %d bytes\n"
6352	"L3 Cache Lines Per Tag: %d\n"
6353	"L3 Cache Associativity: %s\n"
6354	"L3 Cache Size: %d KB\n",
6355	(uEDX >> 0) & 0xff,
6356	(uEDX >> 8) & 0xf,
6357	getL23CacheAss((uEDX >> 12) & 0xf),
6358	((uEDX >> 18) & 0x3fff) * 512);
6359	}
6360
6361	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6362	{
6363	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6364	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6365	#endif
6366	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
6367	{
6368	if (iVerbosity < 1)
6369	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
6370	else
6371	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
6372	}
6373	}
6374
6375	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
6376	if (pCurLeaf != NULL)
6377	{
6378	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6379	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6380	#endif
6381	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
6382	{
6383	if (iVerbosity < 1)
6384	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
6385	else
6386	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
6387	}
6388
6389	if (iVerbosity)
6390	{
6391	uint32_t uEAX = pCurLeaf->uEax;
6392	uint32_t uECX = pCurLeaf->uEcx;
6393
6394	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
6395	* AMD if we get 0, the guest physical address width should be taken from
6396	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
6397	* for guests using nested paging. */
6398	pHlp->pfnPrintf(pHlp,
6399	"Physical Address Width: %d bits\n"
6400	"Virtual Address Width: %d bits\n"
6401	"Guest Physical Address Width: %d bits\n",
6402	(uEAX >> 0) & 0xff,
6403	(uEAX >> 8) & 0xff,
6404	(uEAX >> 16) & 0xff);
6405
6406	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
6407	* count here). */
6408	pHlp->pfnPrintf(pHlp,
6409	"Physical Core Count: %d\n",
6410	((uECX >> 0) & 0xff) + 1);
6411	}
6412	}
6413
6414	pCurLeaf = pNextLeaf;
6415	}
6416
6417
6418
6419	/*
6420	* Centaur.
6421	*/
6422	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6423
6424	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6425	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6426	#endif
6427	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6428	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6429	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6430	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6431	cMax = RT_MAX(cHstMax, cGstMax);
6432	if (cMax >= UINT32_C(0xc0000000))
6433	{
6434	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6435
6436	/*
6437	* Understandable output
6438	*/
6439	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6440	pHlp->pfnPrintf(pHlp,
6441	"Centaur Supports: 0xc0000000-%#010x\n",
6442	pCurLeaf->uEax);
6443
6444	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6445	{
6446	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6447	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6448	#endif
6449	uint32_t uEdxGst = pCurLeaf->uEdx;
6450	uint32_t uEdxHst = Host.uEdx;
6451
6452	if (iVerbosity == 1)
6453	{
6454	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6455	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6456	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6457	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6458	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6459	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6460	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6461	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6462	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6463	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6464	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6465	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6466	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6467	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6468	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6469	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6470	for (unsigned iBit = 14; iBit < 32; iBit++)
6471	if (uEdxGst & RT_BIT(iBit))
6472	pHlp->pfnPrintf(pHlp, " %d", iBit);
6473	pHlp->pfnPrintf(pHlp, "\n");
6474	}
6475	else
6476	{
6477	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6478	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6479	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6480	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6481	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6482	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6483	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6484	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6485	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6486	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6487	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6488	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6489	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6490	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6491	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6492	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6493	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6494	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6495	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6496	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6497	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6498	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6499	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6500	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6501	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6502	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6503	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6504	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6505	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6506	for (unsigned iBit = 27; iBit < 32; iBit++)
6507	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6508	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6509	pHlp->pfnPrintf(pHlp, "\n");
6510	}
6511	}
6512
6513	pCurLeaf = pNextLeaf;
6514	}
6515
6516	/*
6517	* The remainder.
6518	*/
6519	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6520	}
6521
6522	#endif /* !IN_VBOX_CPU_REPORT */
6523

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 107763

Download in other formats: