CPUMDbg.cpp@ 55048

Last change on this file since 55048 was 55048, checked in by vboxsync, 10 years ago
VMM,REM: Allocate the FPU/SSE/AVX/FUTURE state stuff. We need to use pointers to substates anyway and this will make CPUMCPU much smaller.
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1	/* $Id: CPUMDbg.cpp 55048 2015-03-31 18:49:19Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4	*/
5
6	/*
7	* Copyright (C) 2010-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/pdmapi.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/param.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/thread.h>
32	#include <iprt/string.h>
33	#include <iprt/uint128.h>
34
35
36	/**
37	* @interface_method_impl{DBGFREGDESC, pfnGet}
38	*/
39	static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
40	{
41	PVMCPU pVCpu = (PVMCPU)pvUser;
42	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
43
44	VMCPU_ASSERT_EMT(pVCpu);
45
46	switch (pDesc->enmType)
47	{
48	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
49	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
50	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
51	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
52	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
53	default:
54	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
55	}
56	}
57
58
59	/**
60	* @interface_method_impl{DBGFREGDESC, pfnSet}
61	*/
62	static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
63	{
64	PVMCPU pVCpu = (PVMCPU)pvUser;
65	void pv = (uint8_t )&pVCpu->cpum + pDesc->offRegister;
66
67	VMCPU_ASSERT_EMT(pVCpu);
68
69	switch (pDesc->enmType)
70	{
71	case DBGFREGVALTYPE_U8:
72	(uint8_t )pv &= ~pfMask->u8;
73	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
74	return VINF_SUCCESS;
75
76	case DBGFREGVALTYPE_U16:
77	(uint16_t )pv &= ~pfMask->u16;
78	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
79	return VINF_SUCCESS;
80
81	case DBGFREGVALTYPE_U32:
82	(uint32_t )pv &= ~pfMask->u32;
83	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
84	return VINF_SUCCESS;
85
86	case DBGFREGVALTYPE_U64:
87	(uint64_t )pv &= ~pfMask->u64;
88	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
89	return VINF_SUCCESS;
90
91	case DBGFREGVALTYPE_U128:
92	{
93	RTUINT128U Val;
94	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
95	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
96	return VINF_SUCCESS;
97	}
98
99	default:
100	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
101	}
102	}
103
104
105	/**
106	* @interface_method_impl{DBGFREGDESC, pfnGet}
107	*/
108	static DECLCALLBACK(int) cpumR3RegGet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
109	{
110	PVMCPU pVCpu = (PVMCPU)pvUser;
111	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
112
113	VMCPU_ASSERT_EMT(pVCpu);
114
115	switch (pDesc->enmType)
116	{
117	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
118	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
119	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
120	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
121	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
122	default:
123	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
124	}
125	}
126
127
128	/**
129	* @interface_method_impl{DBGFREGDESC, pfnSet}
130	*/
131	static DECLCALLBACK(int) cpumR3RegSet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
132	{
133	PVMCPU pVCpu = (PVMCPU)pvUser;
134	void pv = (uint8_t )&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
135
136	VMCPU_ASSERT_EMT(pVCpu);
137
138	switch (pDesc->enmType)
139	{
140	case DBGFREGVALTYPE_U8:
141	(uint8_t )pv &= ~pfMask->u8;
142	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
143	return VINF_SUCCESS;
144
145	case DBGFREGVALTYPE_U16:
146	(uint16_t )pv &= ~pfMask->u16;
147	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
148	return VINF_SUCCESS;
149
150	case DBGFREGVALTYPE_U32:
151	(uint32_t )pv &= ~pfMask->u32;
152	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
153	return VINF_SUCCESS;
154
155	case DBGFREGVALTYPE_U64:
156	(uint64_t )pv &= ~pfMask->u64;
157	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
158	return VINF_SUCCESS;
159
160	case DBGFREGVALTYPE_U128:
161	{
162	RTUINT128U Val;
163	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
164	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
165	return VINF_SUCCESS;
166	}
167
168	default:
169	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
170	}
171	}
172
173
174
175	/**
176	* @interface_method_impl{DBGFREGDESC, pfnGet}
177	*/
178	static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
179	{
180	/** @todo perform a selector load, updating hidden selectors and stuff. */
181	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
182	return VERR_NOT_IMPLEMENTED;
183	}
184
185
186	/**
187	* @interface_method_impl{DBGFREGDESC, pfnGet}
188	*/
189	static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
190	{
191	PVMCPU pVCpu = (PVMCPU)pvUser;
192	VBOXGDTR const pGdtr = (VBOXGDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
193
194	VMCPU_ASSERT_EMT(pVCpu);
195	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
196
197	pValue->dtr.u32Limit = pGdtr->cbGdt;
198	pValue->dtr.u64Base = pGdtr->pGdt;
199	return VINF_SUCCESS;
200	}
201
202
203	/**
204	* @interface_method_impl{DBGFREGDESC, pfnGet}
205	*/
206	static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
207	{
208	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
209	return VERR_NOT_IMPLEMENTED;
210	}
211
212
213	/**
214	* @interface_method_impl{DBGFREGDESC, pfnGet}
215	*/
216	static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
217	{
218	PVMCPU pVCpu = (PVMCPU)pvUser;
219	VBOXIDTR const pIdtr = (VBOXIDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
220
221	VMCPU_ASSERT_EMT(pVCpu);
222	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
223
224	pValue->dtr.u32Limit = pIdtr->cbIdt;
225	pValue->dtr.u64Base = pIdtr->pIdt;
226	return VINF_SUCCESS;
227	}
228
229
230	/**
231	* @interface_method_impl{DBGFREGDESC, pfnGet}
232	*/
233	static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
234	{
235	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
236	return VERR_NOT_IMPLEMENTED;
237	}
238
239
240	/**
241	* Is the FPU state in FXSAVE format or not.
242	*
243	* @returns true if it is, false if it's in FNSAVE.
244	* @param pVCpu Pointer to the VMCPU.
245	*/
246	DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu)
247	{
248	#ifdef RT_ARCH_AMD64
249	NOREF(pVCpu);
250	return true;
251	#else
252	return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR;
253	#endif
254	}
255
256
257	/**
258	* Determins the tag register value for a CPU register when the FPU state
259	* format is FXSAVE.
260	*
261	* @returns The tag register value.
262	* @param pFpu Pointer to the guest FPU.
263	* @param iReg The register number (0..7).
264	*/
265	DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
266	{
267	/*
268	* See table 11-1 in the AMD docs.
269	*/
270	if (!(pFpu->FTW & RT_BIT_32(iReg)))
271	return 3; /* b11 - empty */
272
273	uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
274	if (uExp == 0)
275	{
276	if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
277	return 1; /* b01 - zero */
278	return 2; /* b10 - special */
279	}
280
281	if (uExp == UINT16_C(0xffff))
282	return 2; /* b10 - special */
283
284	if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
285	return 2; /* b10 - special */
286
287	return 0; /* b00 - valid (normal) */
288	}
289
290
291	/**
292	* @interface_method_impl{DBGFREGDESC, pfnGet}
293	*/
294	static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
295	{
296	PVMCPU pVCpu = (PVMCPU)pvUser;
297	PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
298
299	VMCPU_ASSERT_EMT(pVCpu);
300	Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
301
302	if (cpumR3RegIsFxSaveFormat(pVCpu))
303	pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
304	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
305	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
306	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
307	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
308	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
309	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
310	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
311	else
312	{
313	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)pFpu;
314	pValue->u16 = pOldFpu->FTW;
315	}
316	return VINF_SUCCESS;
317	}
318
319
320	/**
321	* @interface_method_impl{DBGFREGDESC, pfnGet}
322	*/
323	static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
324	{
325	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
326	return VERR_DBGF_READ_ONLY_REGISTER;
327	}
328
329
330	/**
331	* @interface_method_impl{DBGFREGDESC, pfnGet}
332	*/
333	static DECLCALLBACK(int) cpumR3RegGet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
334	{
335	switch (pDesc->enmType)
336	{
337	case DBGFREGVALTYPE_U8: pValue->u8 = 0; return VINF_SUCCESS;
338	case DBGFREGVALTYPE_U16: pValue->u16 = 0; return VINF_SUCCESS;
339	case DBGFREGVALTYPE_U32: pValue->u32 = 0; return VINF_SUCCESS;
340	case DBGFREGVALTYPE_U64: pValue->u64 = 0; return VINF_SUCCESS;
341	case DBGFREGVALTYPE_U128:
342	RT_ZERO(pValue->u128);
343	return VINF_SUCCESS;
344	case DBGFREGVALTYPE_DTR:
345	pValue->dtr.u32Limit = 0;
346	pValue->dtr.u64Base = 0;
347	return VINF_SUCCESS;
348	case DBGFREGVALTYPE_R80:
349	RT_ZERO(pValue->r80Ex);
350	return VINF_SUCCESS;
351	default:
352	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
353	}
354	}
355
356
357	/**
358	* @interface_method_impl{DBGFREGDESC, pfnSet}
359	*/
360	static DECLCALLBACK(int) cpumR3RegSet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
361	{
362	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
363	return VERR_DBGF_READ_ONLY_REGISTER;
364	}
365
366
367
368	/*
369	*
370	* Guest register access functions.
371	*
372	*/
373
374	/**
375	* @interface_method_impl{DBGFREGDESC, pfnGet}
376	*/
377	static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
378	{
379	PVMCPU pVCpu = (PVMCPU)pvUser;
380	VMCPU_ASSERT_EMT(pVCpu);
381
382	uint64_t u64Value;
383	int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
384	AssertRCReturn(rc, rc);
385	switch (pDesc->enmType)
386	{
387	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
388	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
389	default:
390	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
391	}
392	return VINF_SUCCESS;
393	}
394
395
396	/**
397	* @interface_method_impl{DBGFREGDESC, pfnGet}
398	*/
399	static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
400	{
401	int rc;
402	PVMCPU pVCpu = (PVMCPU)pvUser;
403
404	VMCPU_ASSERT_EMT(pVCpu);
405
406	/*
407	* Calculate the new value.
408	*/
409	uint64_t u64Value;
410	uint64_t fMask;
411	uint64_t fMaskMax;
412	switch (pDesc->enmType)
413	{
414	case DBGFREGVALTYPE_U64:
415	u64Value = pValue->u64;
416	fMask = pfMask->u64;
417	fMaskMax = UINT64_MAX;
418	break;
419	case DBGFREGVALTYPE_U32:
420	u64Value = pValue->u32;
421	fMask = pfMask->u32;
422	fMaskMax = UINT32_MAX;
423	break;
424	default:
425	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
426	}
427	if (fMask != fMaskMax)
428	{
429	uint64_t u64FullValue;
430	rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
431	if (RT_FAILURE(rc))
432	return rc;
433	u64Value = (u64FullValue & ~fMask)
434	\| (u64Value & fMask);
435	}
436
437	/*
438	* Perform the assignment.
439	*/
440	switch (pDesc->offRegister)
441	{
442	case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
443	case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
444	case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
445	case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
446	case 8: rc = PDMApicSetTPR(pVCpu, (uint8_t)(u64Value << 4)); break;
447	default:
448	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
449	}
450	return rc;
451	}
452
453
454	/**
455	* @interface_method_impl{DBGFREGDESC, pfnGet}
456	*/
457	static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
458	{
459	PVMCPU pVCpu = (PVMCPU)pvUser;
460	VMCPU_ASSERT_EMT(pVCpu);
461
462	uint64_t u64Value;
463	int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
464	AssertRCReturn(rc, rc);
465	switch (pDesc->enmType)
466	{
467	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
468	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
469	default:
470	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
471	}
472	return VINF_SUCCESS;
473	}
474
475
476	/**
477	* @interface_method_impl{DBGFREGDESC, pfnGet}
478	*/
479	static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
480	{
481	int rc;
482	PVMCPU pVCpu = (PVMCPU)pvUser;
483
484	VMCPU_ASSERT_EMT(pVCpu);
485
486	/*
487	* Calculate the new value.
488	*/
489	uint64_t u64Value;
490	uint64_t fMask;
491	uint64_t fMaskMax;
492	switch (pDesc->enmType)
493	{
494	case DBGFREGVALTYPE_U64:
495	u64Value = pValue->u64;
496	fMask = pfMask->u64;
497	fMaskMax = UINT64_MAX;
498	break;
499	case DBGFREGVALTYPE_U32:
500	u64Value = pValue->u32;
501	fMask = pfMask->u32;
502	fMaskMax = UINT32_MAX;
503	break;
504	default:
505	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
506	}
507	if (fMask != fMaskMax)
508	{
509	uint64_t u64FullValue;
510	rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
511	if (RT_FAILURE(rc))
512	return rc;
513	u64Value = (u64FullValue & ~fMask)
514	\| (u64Value & fMask);
515	}
516
517	/*
518	* Perform the assignment.
519	*/
520	return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
521	}
522
523
524	/**
525	* @interface_method_impl{DBGFREGDESC, pfnGet}
526	*/
527	static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
528	{
529	PVMCPU pVCpu = (PVMCPU)pvUser;
530	VMCPU_ASSERT_EMT(pVCpu);
531
532	uint64_t u64Value;
533	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
534	if (rcStrict == VINF_SUCCESS)
535	{
536	switch (pDesc->enmType)
537	{
538	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
539	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
540	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
541	default:
542	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
543	}
544	return VBOXSTRICTRC_VAL(rcStrict);
545	}
546
547	/** @todo what to do about errors? */
548	Assert(RT_FAILURE_NP(rcStrict));
549	return VBOXSTRICTRC_VAL(rcStrict);
550	}
551
552
553	/**
554	* @interface_method_impl{DBGFREGDESC, pfnGet}
555	*/
556	static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
557	{
558	PVMCPU pVCpu = (PVMCPU)pvUser;
559
560	VMCPU_ASSERT_EMT(pVCpu);
561
562	/*
563	* Calculate the new value.
564	*/
565	uint64_t u64Value;
566	uint64_t fMask;
567	uint64_t fMaskMax;
568	switch (pDesc->enmType)
569	{
570	case DBGFREGVALTYPE_U64:
571	u64Value = pValue->u64;
572	fMask = pfMask->u64;
573	fMaskMax = UINT64_MAX;
574	break;
575	case DBGFREGVALTYPE_U32:
576	u64Value = pValue->u32;
577	fMask = pfMask->u32;
578	fMaskMax = UINT32_MAX;
579	break;
580	case DBGFREGVALTYPE_U16:
581	u64Value = pValue->u16;
582	fMask = pfMask->u16;
583	fMaskMax = UINT16_MAX;
584	break;
585	default:
586	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
587	}
588	if (fMask != fMaskMax)
589	{
590	uint64_t u64FullValue;
591	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
592	if (rcStrict != VINF_SUCCESS)
593	{
594	AssertRC(RT_FAILURE_NP(rcStrict));
595	return VBOXSTRICTRC_VAL(rcStrict);
596	}
597	u64Value = (u64FullValue & ~fMask)
598	\| (u64Value & fMask);
599	}
600
601	/*
602	* Perform the assignment.
603	*/
604	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
605	if (rcStrict == VINF_SUCCESS)
606	return VINF_SUCCESS;
607	AssertRC(RT_FAILURE_NP(rcStrict));
608	return VBOXSTRICTRC_VAL(rcStrict);
609	}
610
611
612	/**
613	* @interface_method_impl{DBGFREGDESC, pfnGet}
614	*/
615	static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
616	{
617	PVMCPU pVCpu = (PVMCPU)pvUser;
618	VMCPU_ASSERT_EMT(pVCpu);
619	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
620
621	PX86FXSTATE pFpuCtx = &pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87;
622	if (cpumR3RegIsFxSaveFormat(pVCpu))
623	{
624	unsigned iReg = (pFpuCtx->FSW >> 11) & 7;
625	iReg += pDesc->offRegister;
626	iReg &= 7;
627	pValue->r80Ex = pFpuCtx->aRegs[iReg].r80Ex;
628	}
629	else
630	{
631	PCX86FPUSTATE pOldFpuCtx = (PCX86FPUSTATE)pFpuCtx;
632
633	unsigned iReg = (pOldFpuCtx->FSW >> 11) & 7;
634	iReg += pDesc->offRegister;
635	iReg &= 7;
636	pValue->r80Ex = pOldFpuCtx->regs[iReg].r80Ex;
637	}
638
639	return VINF_SUCCESS;
640	}
641
642
643	/**
644	* @interface_method_impl{DBGFREGDESC, pfnGet}
645	*/
646	static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
647	{
648	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
649	return VERR_NOT_IMPLEMENTED;
650	}
651
652
653
654	/*
655	*
656	* Hypervisor register access functions.
657	*
658	*/
659
660	/**
661	* @interface_method_impl{DBGFREGDESC, pfnGet}
662	*/
663	static DECLCALLBACK(int) cpumR3RegHyperGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
664	{
665	PVMCPU pVCpu = (PVMCPU)pvUser;
666	VMCPU_ASSERT_EMT(pVCpu);
667
668	uint64_t u64Value;
669	switch (pDesc->offRegister)
670	{
671	case 0: u64Value = UINT64_MAX; break;
672	case 2: u64Value = UINT64_MAX; break;
673	case 3: u64Value = CPUMGetHyperCR3(pVCpu); break;
674	case 4: u64Value = UINT64_MAX; break;
675	case 8: u64Value = UINT64_MAX; break;
676	default:
677	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
678	}
679	switch (pDesc->enmType)
680	{
681	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
682	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
683	default:
684	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
685	}
686	return VINF_SUCCESS;
687	}
688
689
690	/**
691	* @interface_method_impl{DBGFREGDESC, pfnGet}
692	*/
693	static DECLCALLBACK(int) cpumR3RegHyperSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
694	{
695	/* Not settable, prevents killing your host. */
696	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
697	return VERR_ACCESS_DENIED;
698	}
699
700
701	/**
702	* @interface_method_impl{DBGFREGDESC, pfnGet}
703	*/
704	static DECLCALLBACK(int) cpumR3RegHyperGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
705	{
706	PVMCPU pVCpu = (PVMCPU)pvUser;
707	VMCPU_ASSERT_EMT(pVCpu);
708
709	uint64_t u64Value;
710	switch (pDesc->offRegister)
711	{
712	case 0: u64Value = CPUMGetHyperDR0(pVCpu); break;
713	case 1: u64Value = CPUMGetHyperDR1(pVCpu); break;
714	case 2: u64Value = CPUMGetHyperDR2(pVCpu); break;
715	case 3: u64Value = CPUMGetHyperDR3(pVCpu); break;
716	case 6: u64Value = CPUMGetHyperDR6(pVCpu); break;
717	case 7: u64Value = CPUMGetHyperDR7(pVCpu); break;
718	default:
719	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
720	}
721	switch (pDesc->enmType)
722	{
723	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
724	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
725	default:
726	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
727	}
728	return VINF_SUCCESS;
729	}
730
731
732	/**
733	* @interface_method_impl{DBGFREGDESC, pfnGet}
734	*/
735	static DECLCALLBACK(int) cpumR3RegHyperSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
736	{
737	/* Not settable, prevents killing your host. */
738	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
739	return VERR_ACCESS_DENIED;
740	}
741
742
743	/**
744	* @interface_method_impl{DBGFREGDESC, pfnGet}
745	*/
746	static DECLCALLBACK(int) cpumR3RegHyperGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
747	{
748	NOREF(pvUser);
749
750	/* Not availble at present, return all FFs to keep things quiet */
751	uint64_t u64Value = UINT64_MAX;
752	switch (pDesc->enmType)
753	{
754	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
755	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
756	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
757	default:
758	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
759	}
760	return VINF_SUCCESS;
761	}
762
763
764	/**
765	* @interface_method_impl{DBGFREGDESC, pfnGet}
766	*/
767	static DECLCALLBACK(int) cpumR3RegHyperSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
768	{
769	/* Not settable, return failure. */
770	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
771	return VERR_ACCESS_DENIED;
772	}
773
774
775	/*
776	* Set up aliases.
777	*/
778	#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
779	static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
780	{ \
781	{ psz32, DBGFREGVALTYPE_U32 }, \
782	{ psz16, DBGFREGVALTYPE_U16 }, \
783	{ psz8, DBGFREGVALTYPE_U8 }, \
784	{ NULL, DBGFREGVALTYPE_INVALID } \
785	}
786	CPUMREGALIAS_STD(rax, "eax", "ax", "al");
787	CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
788	CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
789	CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
790	CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
791	CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
792	CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
793	CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
794	CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
795	CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
796	CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
797	CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
798	CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
799	CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
800	CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
801	CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
802	CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
803	CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
804	#undef CPUMREGALIAS_STD
805
806	static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
807	{
808	{ "fpuip16", DBGFREGVALTYPE_U16 },
809	{ NULL, DBGFREGVALTYPE_INVALID }
810	};
811
812	static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
813	{
814	{ "fpudp16", DBGFREGVALTYPE_U16 },
815	{ NULL, DBGFREGVALTYPE_INVALID }
816	};
817
818	static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
819	{
820	{ "msw", DBGFREGVALTYPE_U16 },
821	{ NULL, DBGFREGVALTYPE_INVALID }
822	};
823
824	/*
825	* Sub fields.
826	*/
827	/** Sub-fields for the (hidden) segment attribute register. */
828	static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
829	{
830	DBGFREGSUBFIELD_RW("type", 0, 4, 0),
831	DBGFREGSUBFIELD_RW("s", 4, 1, 0),
832	DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
833	DBGFREGSUBFIELD_RW("p", 7, 1, 0),
834	DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
835	DBGFREGSUBFIELD_RW("l", 13, 1, 0),
836	DBGFREGSUBFIELD_RW("d", 14, 1, 0),
837	DBGFREGSUBFIELD_RW("g", 15, 1, 0),
838	DBGFREGSUBFIELD_TERMINATOR()
839	};
840
841	/** Sub-fields for the flags register. */
842	static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
843	{
844	DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
845	DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
846	DBGFREGSUBFIELD_RW("af", 4, 1, 0),
847	DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
848	DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
849	DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
850	DBGFREGSUBFIELD_RW("if", 9, 1, 0),
851	DBGFREGSUBFIELD_RW("df", 10, 1, 0),
852	DBGFREGSUBFIELD_RW("of", 11, 1, 0),
853	DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
854	DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
855	DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
856	DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
857	DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
858	DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
859	DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
860	DBGFREGSUBFIELD_RW("id", 21, 1, 0),
861	DBGFREGSUBFIELD_TERMINATOR()
862	};
863
864	/** Sub-fields for the FPU control word register. */
865	static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
866	{
867	DBGFREGSUBFIELD_RW("im", 1, 1, 0),
868	DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
869	DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
870	DBGFREGSUBFIELD_RW("om", 4, 1, 0),
871	DBGFREGSUBFIELD_RW("um", 5, 1, 0),
872	DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
873	DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
874	DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
875	DBGFREGSUBFIELD_RW("x", 12, 1, 0),
876	DBGFREGSUBFIELD_TERMINATOR()
877	};
878
879	/** Sub-fields for the FPU status word register. */
880	static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
881	{
882	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
883	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
884	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
885	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
886	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
887	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
888	DBGFREGSUBFIELD_RW("se", 6, 1, 0),
889	DBGFREGSUBFIELD_RW("es", 7, 1, 0),
890	DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
891	DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
892	DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
893	DBGFREGSUBFIELD_RW("top", 11, 3, 0),
894	DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
895	DBGFREGSUBFIELD_RW("b", 15, 1, 0),
896	DBGFREGSUBFIELD_TERMINATOR()
897	};
898
899	/** Sub-fields for the FPU tag word register. */
900	static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
901	{
902	DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
903	DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
904	DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
905	DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
906	DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
907	DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
908	DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
909	DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
910	DBGFREGSUBFIELD_TERMINATOR()
911	};
912
913	/** Sub-fields for the Multimedia Extensions Control and Status Register. */
914	static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
915	{
916	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
917	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
918	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
919	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
920	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
921	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
922	DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
923	DBGFREGSUBFIELD_RW("im", 7, 1, 0),
924	DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
925	DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
926	DBGFREGSUBFIELD_RW("om", 10, 1, 0),
927	DBGFREGSUBFIELD_RW("um", 11, 1, 0),
928	DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
929	DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
930	DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
931	DBGFREGSUBFIELD_TERMINATOR()
932	};
933
934	/** Sub-fields for the FPU tag word register. */
935	static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
936	{
937	DBGFREGSUBFIELD_RW("man", 0, 64, 0),
938	DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
939	DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
940	DBGFREGSUBFIELD_TERMINATOR()
941	};
942
943	/** Sub-fields for the MMX registers. */
944	static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
945	{
946	DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
947	DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
948	DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
949	DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
950	DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
951	DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
952	DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
953	DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
954	DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
955	DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
956	DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
957	DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
958	DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
959	DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
960	DBGFREGSUBFIELD_TERMINATOR()
961	};
962
963	/** Sub-fields for the XMM registers. */
964	static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
965	{
966	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
967	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
968	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
969	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
970	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
971	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
972	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
973	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
974	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
975	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
976	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
977	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
978	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
979	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
980	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
981	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
982	DBGFREGSUBFIELD_TERMINATOR()
983	};
984
985	/** Sub-fields for the CR0 register. */
986	static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
987	{
988	DBGFREGSUBFIELD_RW("pe", 0, 1, 0),
989	DBGFREGSUBFIELD_RW("mp", 1, 1, 0),
990	DBGFREGSUBFIELD_RW("em", 2, 1, 0),
991	DBGFREGSUBFIELD_RW("ts", 3, 1, 0),
992	DBGFREGSUBFIELD_RO("et", 4, 1, 0),
993	DBGFREGSUBFIELD_RW("ne", 5, 1, 0),
994	DBGFREGSUBFIELD_RW("wp", 16, 1, 0),
995	DBGFREGSUBFIELD_RW("am", 18, 1, 0),
996	DBGFREGSUBFIELD_RW("nw", 29, 1, 0),
997	DBGFREGSUBFIELD_RW("cd", 30, 1, 0),
998	DBGFREGSUBFIELD_RW("pg", 31, 1, 0),
999	DBGFREGSUBFIELD_TERMINATOR()
1000	};
1001
1002	/** Sub-fields for the CR3 register. */
1003	static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
1004	{
1005	DBGFREGSUBFIELD_RW("pwt", 3, 1, 0),
1006	DBGFREGSUBFIELD_RW("pcd", 4, 1, 0),
1007	DBGFREGSUBFIELD_TERMINATOR()
1008	};
1009
1010	/** Sub-fields for the CR4 register. */
1011	static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
1012	{
1013	DBGFREGSUBFIELD_RW("vme", 0, 1, 0),
1014	DBGFREGSUBFIELD_RW("pvi", 1, 1, 0),
1015	DBGFREGSUBFIELD_RW("tsd", 2, 1, 0),
1016	DBGFREGSUBFIELD_RW("de", 3, 1, 0),
1017	DBGFREGSUBFIELD_RW("pse", 4, 1, 0),
1018	DBGFREGSUBFIELD_RW("pae", 5, 1, 0),
1019	DBGFREGSUBFIELD_RW("mce", 6, 1, 0),
1020	DBGFREGSUBFIELD_RW("pge", 7, 1, 0),
1021	DBGFREGSUBFIELD_RW("pce", 8, 1, 0),
1022	DBGFREGSUBFIELD_RW("osfxsr", 9, 1, 0),
1023	DBGFREGSUBFIELD_RW("osxmmeexcpt", 10, 1, 0),
1024	DBGFREGSUBFIELD_RW("vmxe", 13, 1, 0),
1025	DBGFREGSUBFIELD_RW("smxe", 14, 1, 0),
1026	DBGFREGSUBFIELD_RW("pcide", 17, 1, 0),
1027	DBGFREGSUBFIELD_RW("osxsave", 18, 1, 0),
1028	DBGFREGSUBFIELD_RW("smep", 20, 1, 0),
1029	DBGFREGSUBFIELD_RW("smap", 21, 1, 0),
1030	DBGFREGSUBFIELD_TERMINATOR()
1031	};
1032
1033	/** Sub-fields for the DR6 register. */
1034	static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
1035	{
1036	DBGFREGSUBFIELD_RW("b0", 0, 1, 0),
1037	DBGFREGSUBFIELD_RW("b1", 1, 1, 0),
1038	DBGFREGSUBFIELD_RW("b2", 2, 1, 0),
1039	DBGFREGSUBFIELD_RW("b3", 3, 1, 0),
1040	DBGFREGSUBFIELD_RW("bd", 13, 1, 0),
1041	DBGFREGSUBFIELD_RW("bs", 14, 1, 0),
1042	DBGFREGSUBFIELD_RW("bt", 15, 1, 0),
1043	DBGFREGSUBFIELD_TERMINATOR()
1044	};
1045
1046	/** Sub-fields for the DR7 register. */
1047	static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
1048	{
1049	DBGFREGSUBFIELD_RW("l0", 0, 1, 0),
1050	DBGFREGSUBFIELD_RW("g0", 1, 1, 0),
1051	DBGFREGSUBFIELD_RW("l1", 2, 1, 0),
1052	DBGFREGSUBFIELD_RW("g1", 3, 1, 0),
1053	DBGFREGSUBFIELD_RW("l2", 4, 1, 0),
1054	DBGFREGSUBFIELD_RW("g2", 5, 1, 0),
1055	DBGFREGSUBFIELD_RW("l3", 6, 1, 0),
1056	DBGFREGSUBFIELD_RW("g3", 7, 1, 0),
1057	DBGFREGSUBFIELD_RW("le", 8, 1, 0),
1058	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1059	DBGFREGSUBFIELD_RW("gd", 13, 1, 0),
1060	DBGFREGSUBFIELD_RW("rw0", 16, 2, 0),
1061	DBGFREGSUBFIELD_RW("len0", 18, 2, 0),
1062	DBGFREGSUBFIELD_RW("rw1", 20, 2, 0),
1063	DBGFREGSUBFIELD_RW("len1", 22, 2, 0),
1064	DBGFREGSUBFIELD_RW("rw2", 24, 2, 0),
1065	DBGFREGSUBFIELD_RW("len2", 26, 2, 0),
1066	DBGFREGSUBFIELD_RW("rw3", 28, 2, 0),
1067	DBGFREGSUBFIELD_RW("len3", 30, 2, 0),
1068	DBGFREGSUBFIELD_TERMINATOR()
1069	};
1070
1071	/** Sub-fields for the CR_PAT MSR. */
1072	static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
1073	{
1074	DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
1075	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1076	DBGFREGSUBFIELD_RW("base", 12, 20, 12),
1077	DBGFREGSUBFIELD_TERMINATOR()
1078	};
1079
1080	/** Sub-fields for the CR_PAT MSR. */
1081	static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
1082	{
1083	/** @todo */
1084	DBGFREGSUBFIELD_TERMINATOR()
1085	};
1086
1087	/** Sub-fields for the PERF_STATUS MSR. */
1088	static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
1089	{
1090	/** @todo */
1091	DBGFREGSUBFIELD_TERMINATOR()
1092	};
1093
1094	/** Sub-fields for the EFER MSR. */
1095	static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
1096	{
1097	/** @todo */
1098	DBGFREGSUBFIELD_TERMINATOR()
1099	};
1100
1101	/** Sub-fields for the STAR MSR. */
1102	static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
1103	{
1104	/** @todo */
1105	DBGFREGSUBFIELD_TERMINATOR()
1106	};
1107
1108	/** Sub-fields for the CSTAR MSR. */
1109	static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
1110	{
1111	/** @todo */
1112	DBGFREGSUBFIELD_TERMINATOR()
1113	};
1114
1115	/** Sub-fields for the LSTAR MSR. */
1116	static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
1117	{
1118	/** @todo */
1119	DBGFREGSUBFIELD_TERMINATOR()
1120	};
1121
1122	/** Sub-fields for the SF_MASK MSR. */
1123	static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
1124	{
1125	/** @todo */
1126	DBGFREGSUBFIELD_TERMINATOR()
1127	};
1128
1129
1130	/** @name Macros for producing register descriptor table entries.
1131	* @{ */
1132	#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1133	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1134
1135	#define CPU_REG_REG(UName, LName) \
1136	CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
1137
1138	#define CPU_REG_SEG(UName, LName) \
1139	CPU_REG_RW_AS(#LName, UName, U16, LName.Sel, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
1140	CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
1141	CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
1142	CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
1143
1144	#define CPU_REG_MM(n) \
1145	CPU_REG_XS_RW_AS("mm" #n, MM##n, U64, x87.aRegs[n].mmx, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mmN)
1146
1147	#define CPU_REG_XMM(n) \
1148	CPU_REG_XS_RW_AS("xmm" #n, XMM##n, U128, x87.aXMM[n].xmm, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_xmmN)
1149	/** @} */
1150
1151
1152	/**
1153	* The guest register descriptors.
1154	*/
1155	static DBGFREGDESC const g_aCpumRegGstDescs[] =
1156	{
1157	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1158	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1159	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1160	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1161	#define CPU_REG_XS_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1162	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1163	#define CPU_REG_XS_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1164	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1165	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1166	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
1167	#define CPU_REG_ST(n) \
1168	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
1169
1170	CPU_REG_REG(RAX, rax),
1171	CPU_REG_REG(RCX, rcx),
1172	CPU_REG_REG(RDX, rdx),
1173	CPU_REG_REG(RBX, rbx),
1174	CPU_REG_REG(RSP, rsp),
1175	CPU_REG_REG(RBP, rbp),
1176	CPU_REG_REG(RSI, rsi),
1177	CPU_REG_REG(RDI, rdi),
1178	CPU_REG_REG(R8, r8),
1179	CPU_REG_REG(R9, r9),
1180	CPU_REG_REG(R10, r10),
1181	CPU_REG_REG(R11, r11),
1182	CPU_REG_REG(R12, r12),
1183	CPU_REG_REG(R13, r13),
1184	CPU_REG_REG(R14, r14),
1185	CPU_REG_REG(R15, r15),
1186	CPU_REG_SEG(CS, cs),
1187	CPU_REG_SEG(DS, ds),
1188	CPU_REG_SEG(ES, es),
1189	CPU_REG_SEG(FS, fs),
1190	CPU_REG_SEG(GS, gs),
1191	CPU_REG_SEG(SS, ss),
1192	CPU_REG_REG(RIP, rip),
1193	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1194	CPU_REG_XS_RW_AS("fcw", FCW, U16, x87.FCW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fcw ),
1195	CPU_REG_XS_RW_AS("fsw", FSW, U16, x87.FSW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fsw ),
1196	CPU_REG_XS_RO_AS("ftw", FTW, U16, x87, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1197	CPU_REG_XS_RW_AS("fop", FOP, U16, x87.FOP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1198	CPU_REG_XS_RW_AS("fpuip", FPUIP, U32, x87.FPUIP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpuip, NULL ),
1199	CPU_REG_XS_RW_AS("fpucs", FPUCS, U16, x87.CS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1200	CPU_REG_XS_RW_AS("fpudp", FPUDP, U32, x87.FPUDP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpudp, NULL ),
1201	CPU_REG_XS_RW_AS("fpuds", FPUDS, U16, x87.DS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1202	CPU_REG_XS_RW_AS("mxcsr", MXCSR, U32, x87.MXCSR, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1203	CPU_REG_XS_RW_AS("mxcsr_mask", MXCSR_MASK, U32, x87.MXCSR_MASK, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1204	CPU_REG_ST(0),
1205	CPU_REG_ST(1),
1206	CPU_REG_ST(2),
1207	CPU_REG_ST(3),
1208	CPU_REG_ST(4),
1209	CPU_REG_ST(5),
1210	CPU_REG_ST(6),
1211	CPU_REG_ST(7),
1212	CPU_REG_MM(0),
1213	CPU_REG_MM(1),
1214	CPU_REG_MM(2),
1215	CPU_REG_MM(3),
1216	CPU_REG_MM(4),
1217	CPU_REG_MM(5),
1218	CPU_REG_MM(6),
1219	CPU_REG_MM(7),
1220	CPU_REG_XMM(0),
1221	CPU_REG_XMM(1),
1222	CPU_REG_XMM(2),
1223	CPU_REG_XMM(3),
1224	CPU_REG_XMM(4),
1225	CPU_REG_XMM(5),
1226	CPU_REG_XMM(6),
1227	CPU_REG_XMM(7),
1228	CPU_REG_XMM(8),
1229	CPU_REG_XMM(9),
1230	CPU_REG_XMM(10),
1231	CPU_REG_XMM(11),
1232	CPU_REG_XMM(12),
1233	CPU_REG_XMM(13),
1234	CPU_REG_XMM(14),
1235	CPU_REG_XMM(15),
1236	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1237	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1238	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1239	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1240	CPU_REG_SEG(LDTR, ldtr),
1241	CPU_REG_SEG(TR, tr),
1242	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1243	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1244	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
1245	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
1246	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1247	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1248	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1249	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1250	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1251	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
1252	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
1253	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1254	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1255	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1256	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1257	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1258	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1259	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1260	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1261	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1262	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1263	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1264	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1265	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1266	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1267	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1268	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1269	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1270	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1271	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1272	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1273	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1274	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1275	DBGFREGDESC_TERMINATOR()
1276
1277	#undef CPU_REG_RW_AS
1278	#undef CPU_REG_RO_AS
1279	#undef CPU_REG_MSR
1280	#undef CPU_REG_ST
1281	};
1282
1283
1284	/**
1285	* The hypervisor (raw-mode) register descriptors.
1286	*/
1287	static DBGFREGDESC const g_aCpumRegHyperDescs[] =
1288	{
1289	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1290	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1291	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1292	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1293	#define CPU_REG_DUMMY(a_szName, a_RegSuff, a_TypeSuff) \
1294	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, 0, cpumR3RegGet_Dummy, cpumR3RegSet_Dummy, NULL, NULL}
1295	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1296	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegHyperGet_msr, cpumR3RegHyperSet_msr, NULL, a_paSubFields)
1297
1298	CPU_REG_REG(RAX, rax),
1299	CPU_REG_REG(RCX, rcx),
1300	CPU_REG_REG(RDX, rdx),
1301	CPU_REG_REG(RBX, rbx),
1302	CPU_REG_REG(RSP, rsp),
1303	CPU_REG_REG(RBP, rbp),
1304	CPU_REG_REG(RSI, rsi),
1305	CPU_REG_REG(RDI, rdi),
1306	CPU_REG_REG(R8, r8),
1307	CPU_REG_REG(R9, r9),
1308	CPU_REG_REG(R10, r10),
1309	CPU_REG_REG(R11, r11),
1310	CPU_REG_REG(R12, r12),
1311	CPU_REG_REG(R13, r13),
1312	CPU_REG_REG(R14, r14),
1313	CPU_REG_REG(R15, r15),
1314	CPU_REG_SEG(CS, cs),
1315	CPU_REG_SEG(DS, ds),
1316	CPU_REG_SEG(ES, es),
1317	CPU_REG_SEG(FS, fs),
1318	CPU_REG_SEG(GS, gs),
1319	CPU_REG_SEG(SS, ss),
1320	CPU_REG_REG(RIP, rip),
1321	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1322	CPU_REG_DUMMY("fcw", FCW, U16),
1323	CPU_REG_DUMMY("fsw", FSW, U16),
1324	CPU_REG_DUMMY("ftw", FTW, U16),
1325	CPU_REG_DUMMY("fop", FOP, U16),
1326	CPU_REG_DUMMY("fpuip", FPUIP, U32),
1327	CPU_REG_DUMMY("fpucs", FPUCS, U16),
1328	CPU_REG_DUMMY("fpudp", FPUDP, U32),
1329	CPU_REG_DUMMY("fpuds", FPUDS, U16),
1330	CPU_REG_DUMMY("mxcsr", MXCSR, U32),
1331	CPU_REG_DUMMY("mxcsr_mask", MXCSR_MASK, U32),
1332	CPU_REG_DUMMY("st0", ST0, R80),
1333	CPU_REG_DUMMY("st1", ST1, R80),
1334	CPU_REG_DUMMY("st2", ST2, R80),
1335	CPU_REG_DUMMY("st3", ST3, R80),
1336	CPU_REG_DUMMY("st4", ST4, R80),
1337	CPU_REG_DUMMY("st5", ST5, R80),
1338	CPU_REG_DUMMY("st6", ST6, R80),
1339	CPU_REG_DUMMY("st7", ST7, R80),
1340	CPU_REG_DUMMY("mm0", MM0, U64),
1341	CPU_REG_DUMMY("mm1", MM1, U64),
1342	CPU_REG_DUMMY("mm2", MM2, U64),
1343	CPU_REG_DUMMY("mm3", MM3, U64),
1344	CPU_REG_DUMMY("mm4", MM4, U64),
1345	CPU_REG_DUMMY("mm5", MM5, U64),
1346	CPU_REG_DUMMY("mm6", MM6, U64),
1347	CPU_REG_DUMMY("mm7", MM7, U64),
1348	CPU_REG_DUMMY("xmm0", XMM0, U128),
1349	CPU_REG_DUMMY("xmm1", XMM1, U128),
1350	CPU_REG_DUMMY("xmm2", XMM2, U128),
1351	CPU_REG_DUMMY("xmm3", XMM3, U128),
1352	CPU_REG_DUMMY("xmm4", XMM4, U128),
1353	CPU_REG_DUMMY("xmm5", XMM5, U128),
1354	CPU_REG_DUMMY("xmm6", XMM6, U128),
1355	CPU_REG_DUMMY("xmm7", XMM7, U128),
1356	CPU_REG_DUMMY("xmm8", XMM8, U128),
1357	CPU_REG_DUMMY("xmm9", XMM9, U128),
1358	CPU_REG_DUMMY("xmm10", XMM10, U128),
1359	CPU_REG_DUMMY("xmm11", XMM11, U128),
1360	CPU_REG_DUMMY("xmm12", XMM12, U128),
1361	CPU_REG_DUMMY("xmm13", XMM13, U128),
1362	CPU_REG_DUMMY("xmm14", XMM14, U128),
1363	CPU_REG_DUMMY("xmm15", XMM15, U128),
1364	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1365	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1366	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1367	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1368	CPU_REG_SEG(LDTR, ldtr),
1369	CPU_REG_SEG(TR, tr),
1370	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1371	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1372	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr3 ),
1373	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr4 ),
1374	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1375	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1376	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1377	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1378	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1379	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr6 ),
1380	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr7 ),
1381	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1382	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1383	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1384	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1385	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1386	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1387	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1388	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1389	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1390	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1391	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1392	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1393	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1394	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1395	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1396	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1397	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1398	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1399	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1400	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1401	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1402	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1403	DBGFREGDESC_TERMINATOR()
1404	#undef CPU_REG_RW_AS
1405	#undef CPU_REG_RO_AS
1406	#undef CPU_REG_MSR
1407	#undef CPU_REG_ST
1408	};
1409
1410
1411	/**
1412	* Initializes the debugger related sides of the CPUM component.
1413	*
1414	* Called by CPUMR3Init.
1415	*
1416	* @returns VBox status code.
1417	* @param pVM Pointer to the VM.
1418	*/
1419	int cpumR3DbgInit(PVM pVM)
1420	{
1421	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1422	{
1423	int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /fGuestRegs/);
1424	AssertLogRelRCReturn(rc, rc);
1425	rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /fGuestRegs/);
1426	AssertLogRelRCReturn(rc, rc);
1427	}
1428
1429	return VINF_SUCCESS;
1430	}
1431

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 55048

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