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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 74795

Last change on this file since 74795 was 69111, checked in by vboxsync, 7 years ago
(C) year
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File size: 61.6 KB

Rev	Line
[31491]	1	/* $Id: CPUMDbg.cpp 69111 2017-10-17 14:26:02Z vboxsync $ */
	2	/** @file
[35410]	3	* CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
[31491]	4	*/
	5
	6	/*
[69111]	7	* Copyright (C) 2010-2017 Oracle Corporation
[31491]	8	*
	9	* This file is part of VirtualBox Open Source Edition (OSE), as
	10	* available from http://www.virtualbox.org. This file is free software;
	11	* you can redistribute it and/or modify it under the terms of the GNU
	12	* General Public License (GPL) as published by the Free Software
	13	* Foundation, in version 2 as it comes in the "COPYING" file of the
	14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
	15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
	16	*/
	17
	18
[57358]	19	/*********************************************************************************************************************************
	20	* Header Files *
	21	*********************************************************************************************************************************/
[31491]	22	#define LOG_GROUP LOG_GROUP_DBGF
[35468]	23	#include <VBox/vmm/cpum.h>
[35346]	24	#include <VBox/vmm/dbgf.h>
[64655]	25	#include <VBox/vmm/apic.h>
[35468]	26	#include "CPUMInternal.h"
[35346]	27	#include <VBox/vmm/vm.h>
[31491]	28	#include <VBox/param.h>
	29	#include <VBox/err.h>
	30	#include <VBox/log.h>
[35468]	31	#include <iprt/thread.h>
[55048]	32	#include <iprt/string.h>
[35490]	33	#include <iprt/uint128.h>
[31491]	34
	35
[35468]	36	/**
[58116]	37	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35468]	38	*/
	39	static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
[35410]	40	{
[35468]	41	PVMCPU pVCpu = (PVMCPU)pvUser;
[35601]	42	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
[35468]	43
	44	VMCPU_ASSERT_EMT(pVCpu);
	45
	46	switch (pDesc->enmType)
	47	{
	48	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
	49	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
	50	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
	51	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
	52	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
[66885]	53	case DBGFREGVALTYPE_U256: pValue->u256 = *(PCRTUINT256U )pv; return VINF_SUCCESS;
	54	case DBGFREGVALTYPE_U512: pValue->u512 = *(PCRTUINT512U )pv; return VINF_SUCCESS;
[35468]	55	default:
[39405]	56	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35468]	57	}
	58	}
	59
	60
	61	/**
[58116]	62	* @interface_method_impl{DBGFREGDESC,pfnSet}
[35468]	63	*/
	64	static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
	65	{
	66	PVMCPU pVCpu = (PVMCPU)pvUser;
[35601]	67	void pv = (uint8_t )&pVCpu->cpum + pDesc->offRegister;
[35468]	68
	69	VMCPU_ASSERT_EMT(pVCpu);
	70
	71	switch (pDesc->enmType)
	72	{
	73	case DBGFREGVALTYPE_U8:
	74	(uint8_t )pv &= ~pfMask->u8;
	75	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
	76	return VINF_SUCCESS;
	77
	78	case DBGFREGVALTYPE_U16:
	79	(uint16_t )pv &= ~pfMask->u16;
	80	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
	81	return VINF_SUCCESS;
	82
	83	case DBGFREGVALTYPE_U32:
	84	(uint32_t )pv &= ~pfMask->u32;
	85	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
	86	return VINF_SUCCESS;
	87
	88	case DBGFREGVALTYPE_U64:
	89	(uint64_t )pv &= ~pfMask->u64;
	90	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
	91	return VINF_SUCCESS;
	92
	93	case DBGFREGVALTYPE_U128:
[35490]	94	{
	95	RTUINT128U Val;
	96	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
	97	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
[35468]	98	return VINF_SUCCESS;
[35490]	99	}
[35468]	100
	101	default:
[39405]	102	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35468]	103	}
	104	}
	105
	106
	107	/**
[58116]	108	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35468]	109	*/
[55048]	110	static DECLCALLBACK(int) cpumR3RegGet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
	111	{
	112	PVMCPU pVCpu = (PVMCPU)pvUser;
	113	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
	114
	115	VMCPU_ASSERT_EMT(pVCpu);
	116
	117	switch (pDesc->enmType)
	118	{
	119	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
	120	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
	121	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
	122	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
	123	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
	124	default:
	125	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
	126	}
	127	}
	128
	129
	130	/**
[58116]	131	* @interface_method_impl{DBGFREGDESC,pfnSet}
[55048]	132	*/
	133	static DECLCALLBACK(int) cpumR3RegSet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
	134	{
	135	PVMCPU pVCpu = (PVMCPU)pvUser;
	136	void pv = (uint8_t )&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
	137
	138	VMCPU_ASSERT_EMT(pVCpu);
	139
	140	switch (pDesc->enmType)
	141	{
	142	case DBGFREGVALTYPE_U8:
	143	(uint8_t )pv &= ~pfMask->u8;
	144	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
	145	return VINF_SUCCESS;
	146
	147	case DBGFREGVALTYPE_U16:
	148	(uint16_t )pv &= ~pfMask->u16;
	149	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
	150	return VINF_SUCCESS;
	151
	152	case DBGFREGVALTYPE_U32:
	153	(uint32_t )pv &= ~pfMask->u32;
	154	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
	155	return VINF_SUCCESS;
	156
	157	case DBGFREGVALTYPE_U64:
	158	(uint64_t )pv &= ~pfMask->u64;
	159	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
	160	return VINF_SUCCESS;
	161
	162	case DBGFREGVALTYPE_U128:
	163	{
	164	RTUINT128U Val;
	165	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
	166	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
	167	return VINF_SUCCESS;
	168	}
	169
	170	default:
	171	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
	172	}
	173	}
	174
	175
	176
	177	/**
[58116]	178	* @interface_method_impl{DBGFREGDESC,pfnGet}
[55048]	179	*/
[35468]	180	static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
	181	{
	182	/** @todo perform a selector load, updating hidden selectors and stuff. */
[39078]	183	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
[35410]	184	return VERR_NOT_IMPLEMENTED;
	185	}
[31491]	186
[35468]	187
[35490]	188	/**
[58116]	189	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	190	*/
[35601]	191	static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
[35410]	192	{
[35601]	193	PVMCPU pVCpu = (PVMCPU)pvUser;
	194	VBOXGDTR const pGdtr = (VBOXGDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
	195
	196	VMCPU_ASSERT_EMT(pVCpu);
	197	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
	198
	199	pValue->dtr.u32Limit = pGdtr->cbGdt;
	200	pValue->dtr.u64Base = pGdtr->pGdt;
	201	return VINF_SUCCESS;
	202	}
	203
	204
	205	/**
[58116]	206	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35601]	207	*/
	208	static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
	209	{
[39078]	210	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
[35601]	211	return VERR_NOT_IMPLEMENTED;
	212	}
	213
	214
	215	/**
[58116]	216	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35601]	217	*/
	218	static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
	219	{
	220	PVMCPU pVCpu = (PVMCPU)pvUser;
	221	VBOXIDTR const pIdtr = (VBOXIDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
	222
	223	VMCPU_ASSERT_EMT(pVCpu);
	224	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
	225
	226	pValue->dtr.u32Limit = pIdtr->cbIdt;
	227	pValue->dtr.u64Base = pIdtr->pIdt;
	228	return VINF_SUCCESS;
	229	}
	230
	231
	232	/**
[58116]	233	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35601]	234	*/
	235	static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
	236	{
[39078]	237	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
[35601]	238	return VERR_NOT_IMPLEMENTED;
	239	}
	240
	241
	242	/**
	243	* Determins the tag register value for a CPU register when the FPU state
	244	* format is FXSAVE.
	245	*
	246	* @returns The tag register value.
[41801]	247	* @param pFpu Pointer to the guest FPU.
[35601]	248	* @param iReg The register number (0..7).
	249	*/
	250	DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
	251	{
	252	/*
	253	* See table 11-1 in the AMD docs.
	254	*/
	255	if (!(pFpu->FTW & RT_BIT_32(iReg)))
	256	return 3; /* b11 - empty */
	257
	258	uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
	259	if (uExp == 0)
	260	{
	261	if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
	262	return 1; /* b01 - zero */
	263	return 2; /* b10 - special */
	264	}
	265
	266	if (uExp == UINT16_C(0xffff))
	267	return 2; /* b10 - special */
	268
	269	if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
	270	return 2; /* b10 - special */
	271
	272	return 0; /* b00 - valid (normal) */
	273	}
	274
	275
	276	/**
[58116]	277	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35601]	278	*/
	279	static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
	280	{
	281	PVMCPU pVCpu = (PVMCPU)pvUser;
	282	PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
	283
	284	VMCPU_ASSERT_EMT(pVCpu);
	285	Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
	286
[55062]	287	pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
	288	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
	289	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
	290	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
	291	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
	292	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
	293	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
	294	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
[35601]	295	return VINF_SUCCESS;
	296	}
	297
	298
	299	/**
[58116]	300	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35601]	301	*/
	302	static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
	303	{
[39078]	304	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
[35601]	305	return VERR_DBGF_READ_ONLY_REGISTER;
	306	}
	307
	308
[55048]	309	/**
[58116]	310	* @interface_method_impl{DBGFREGDESC,pfnGet}
[55048]	311	*/
	312	static DECLCALLBACK(int) cpumR3RegGet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
	313	{
[62637]	314	RT_NOREF_PV(pvUser);
[55048]	315	switch (pDesc->enmType)
	316	{
	317	case DBGFREGVALTYPE_U8: pValue->u8 = 0; return VINF_SUCCESS;
	318	case DBGFREGVALTYPE_U16: pValue->u16 = 0; return VINF_SUCCESS;
	319	case DBGFREGVALTYPE_U32: pValue->u32 = 0; return VINF_SUCCESS;
	320	case DBGFREGVALTYPE_U64: pValue->u64 = 0; return VINF_SUCCESS;
	321	case DBGFREGVALTYPE_U128:
	322	RT_ZERO(pValue->u128);
	323	return VINF_SUCCESS;
	324	case DBGFREGVALTYPE_DTR:
	325	pValue->dtr.u32Limit = 0;
	326	pValue->dtr.u64Base = 0;
	327	return VINF_SUCCESS;
	328	case DBGFREGVALTYPE_R80:
	329	RT_ZERO(pValue->r80Ex);
	330	return VINF_SUCCESS;
	331	default:
	332	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
	333	}
	334	}
[35601]	335
[55048]	336
	337	/**
[58116]	338	* @interface_method_impl{DBGFREGDESC,pfnSet}
[55048]	339	*/
	340	static DECLCALLBACK(int) cpumR3RegSet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
	341	{
	342	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
	343	return VERR_DBGF_READ_ONLY_REGISTER;
	344	}
	345
	346
[66885]	347	/**
	348	* @interface_method_impl{DBGFREGDESC,pfnGet}
	349	*/
	350	static DECLCALLBACK(int) cpumR3RegGet_ymm(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
	351	{
	352	PVMCPU pVCpu = (PVMCPU)pvUser;
	353	uint32_t iReg = pDesc->offRegister;
[55048]	354
[66885]	355	Assert(pDesc->enmType == DBGFREGVALTYPE_U256);
	356	VMCPU_ASSERT_EMT(pVCpu);
	357
	358	if (iReg < 16)
	359	{
	360	pValue->u256.DQWords.dqw0 = pVCpu->cpum.s.Guest.pXStateR3->x87.aXMM[iReg].uXmm;
	361	pValue->u256.DQWords.dqw1 = pVCpu->cpum.s.Guest.pXStateR3->u.YmmHi.aYmmHi[iReg].uXmm;
	362	return VINF_SUCCESS;
	363	}
	364	return VERR_NOT_IMPLEMENTED;
	365	}
	366
	367
	368	/**
	369	* @interface_method_impl{DBGFREGDESC,pfnSet}
	370	*/
	371	static DECLCALLBACK(int) cpumR3RegSet_ymm(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
	372	{
	373	PVMCPU pVCpu = (PVMCPU)pvUser;
	374	uint32_t iReg = pDesc->offRegister;
	375
	376	Assert(pDesc->enmType == DBGFREGVALTYPE_U256);
	377	VMCPU_ASSERT_EMT(pVCpu);
	378
	379	if (iReg < 16)
	380	{
	381	RTUINT128U Val;
	382	RTUInt128AssignAnd(&pVCpu->cpum.s.Guest.pXStateR3->x87.aXMM[iReg].uXmm,
	383	RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u256.DQWords.dqw0)));
	384	RTUInt128AssignOr(&pVCpu->cpum.s.Guest.pXStateR3->u.YmmHi.aYmmHi[iReg].uXmm,
	385	RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
	386
	387	}
	388	return VERR_NOT_IMPLEMENTED;
	389	}
	390
	391
[35601]	392	/*
	393	*
	394	* Guest register access functions.
	395	*
	396	*/
	397
	398	/**
[58116]	399	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35601]	400	*/
	401	static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
	402	{
[39034]	403	PVMCPU pVCpu = (PVMCPU)pvUser;
[35490]	404	VMCPU_ASSERT_EMT(pVCpu);
	405
	406	uint64_t u64Value;
	407	int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
[67052]	408	if (rc == VERR_PDM_NO_APIC_INSTANCE) /* CR8 might not be available, see @bugref{8868}.*/
	409	u64Value = 0;
	410	else
	411	AssertRCReturn(rc, rc);
[35490]	412	switch (pDesc->enmType)
	413	{
	414	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
	415	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
	416	default:
[39405]	417	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35490]	418	}
	419	return VINF_SUCCESS;
[35410]	420	}
[31491]	421
[35490]	422
	423	/**
[58116]	424	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	425	*/
[35601]	426	static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
[35312]	427	{
[35490]	428	int rc;
[39034]	429	PVMCPU pVCpu = (PVMCPU)pvUser;
[35490]	430
	431	VMCPU_ASSERT_EMT(pVCpu);
	432
	433	/*
	434	* Calculate the new value.
	435	*/
	436	uint64_t u64Value;
	437	uint64_t fMask;
	438	uint64_t fMaskMax;
	439	switch (pDesc->enmType)
	440	{
	441	case DBGFREGVALTYPE_U64:
	442	u64Value = pValue->u64;
	443	fMask = pfMask->u64;
	444	fMaskMax = UINT64_MAX;
	445	break;
	446	case DBGFREGVALTYPE_U32:
	447	u64Value = pValue->u32;
	448	fMask = pfMask->u32;
	449	fMaskMax = UINT32_MAX;
	450	break;
[40076]	451	default:
[39405]	452	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35490]	453	}
	454	if (fMask != fMaskMax)
	455	{
	456	uint64_t u64FullValue;
	457	rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
	458	if (RT_FAILURE(rc))
	459	return rc;
	460	u64Value = (u64FullValue & ~fMask)
	461	\| (u64Value & fMask);
	462	}
	463
	464	/*
	465	* Perform the assignment.
	466	*/
	467	switch (pDesc->offRegister)
	468	{
	469	case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
	470	case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
	471	case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
	472	case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
[64655]	473	case 8: rc = APICSetTpr(pVCpu, (uint8_t)(u64Value << 4)); break;
[35490]	474	default:
[39405]	475	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35490]	476	}
	477	return rc;
[35410]	478	}
[35312]	479
[35490]	480
	481	/**
[58116]	482	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	483	*/
[35601]	484	static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
[35312]	485	{
[39034]	486	PVMCPU pVCpu = (PVMCPU)pvUser;
[35490]	487	VMCPU_ASSERT_EMT(pVCpu);
	488
	489	uint64_t u64Value;
	490	int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
	491	AssertRCReturn(rc, rc);
	492	switch (pDesc->enmType)
	493	{
	494	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
	495	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
	496	default:
[39405]	497	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35490]	498	}
	499	return VINF_SUCCESS;
[35410]	500	}
[35312]	501
[35490]	502
	503	/**
[58116]	504	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	505	*/
[35601]	506	static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
[35312]	507	{
[35490]	508	int rc;
[39034]	509	PVMCPU pVCpu = (PVMCPU)pvUser;
[35490]	510
	511	VMCPU_ASSERT_EMT(pVCpu);
	512
	513	/*
	514	* Calculate the new value.
	515	*/
	516	uint64_t u64Value;
	517	uint64_t fMask;
	518	uint64_t fMaskMax;
	519	switch (pDesc->enmType)
	520	{
	521	case DBGFREGVALTYPE_U64:
	522	u64Value = pValue->u64;
	523	fMask = pfMask->u64;
	524	fMaskMax = UINT64_MAX;
	525	break;
	526	case DBGFREGVALTYPE_U32:
	527	u64Value = pValue->u32;
	528	fMask = pfMask->u32;
	529	fMaskMax = UINT32_MAX;
	530	break;
[40076]	531	default:
[39405]	532	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35490]	533	}
	534	if (fMask != fMaskMax)
	535	{
	536	uint64_t u64FullValue;
	537	rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
	538	if (RT_FAILURE(rc))
	539	return rc;
	540	u64Value = (u64FullValue & ~fMask)
	541	\| (u64Value & fMask);
	542	}
	543
	544	/*
	545	* Perform the assignment.
	546	*/
	547	return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
[35410]	548	}
[35312]	549
[35490]	550
	551	/**
[58116]	552	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	553	*/
[35601]	554	static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
[35410]	555	{
[39034]	556	PVMCPU pVCpu = (PVMCPU)pvUser;
	557	VMCPU_ASSERT_EMT(pVCpu);
[35490]	558
	559	uint64_t u64Value;
[53466]	560	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
	561	if (rcStrict == VINF_SUCCESS)
[35490]	562	{
	563	switch (pDesc->enmType)
	564	{
	565	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
	566	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
	567	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
	568	default:
[39405]	569	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35490]	570	}
[54047]	571	return VBOXSTRICTRC_VAL(rcStrict);
[35490]	572	}
[54047]	573
[35490]	574	/** @todo what to do about errors? */
[53466]	575	Assert(RT_FAILURE_NP(rcStrict));
	576	return VBOXSTRICTRC_VAL(rcStrict);
[35410]	577	}
[35312]	578
[35490]	579
	580	/**
[58116]	581	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	582	*/
[35601]	583	static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
[35410]	584	{
[53466]	585	PVMCPU pVCpu = (PVMCPU)pvUser;
[35490]	586
	587	VMCPU_ASSERT_EMT(pVCpu);
	588
	589	/*
	590	* Calculate the new value.
	591	*/
	592	uint64_t u64Value;
	593	uint64_t fMask;
	594	uint64_t fMaskMax;
	595	switch (pDesc->enmType)
	596	{
	597	case DBGFREGVALTYPE_U64:
	598	u64Value = pValue->u64;
	599	fMask = pfMask->u64;
	600	fMaskMax = UINT64_MAX;
	601	break;
	602	case DBGFREGVALTYPE_U32:
	603	u64Value = pValue->u32;
	604	fMask = pfMask->u32;
	605	fMaskMax = UINT32_MAX;
	606	break;
	607	case DBGFREGVALTYPE_U16:
	608	u64Value = pValue->u16;
	609	fMask = pfMask->u16;
	610	fMaskMax = UINT16_MAX;
	611	break;
[40076]	612	default:
[39405]	613	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35490]	614	}
	615	if (fMask != fMaskMax)
	616	{
	617	uint64_t u64FullValue;
[53466]	618	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
	619	if (rcStrict != VINF_SUCCESS)
	620	{
	621	AssertRC(RT_FAILURE_NP(rcStrict));
	622	return VBOXSTRICTRC_VAL(rcStrict);
	623	}
[35490]	624	u64Value = (u64FullValue & ~fMask)
	625	\| (u64Value & fMask);
	626	}
	627
	628	/*
	629	* Perform the assignment.
	630	*/
[53466]	631	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
	632	if (rcStrict == VINF_SUCCESS)
	633	return VINF_SUCCESS;
	634	AssertRC(RT_FAILURE_NP(rcStrict));
	635	return VBOXSTRICTRC_VAL(rcStrict);
[35410]	636	}
[35312]	637
[35490]	638
	639	/**
[58116]	640	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	641	*/
[35601]	642	static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
[35410]	643	{
[39034]	644	PVMCPU pVCpu = (PVMCPU)pvUser;
[35490]	645	VMCPU_ASSERT_EMT(pVCpu);
[35601]	646	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
[35490]	647
[55048]	648	PX86FXSTATE pFpuCtx = &pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87;
[55062]	649	unsigned iReg = (pFpuCtx->FSW >> 11) & 7;
	650	iReg += pDesc->offRegister;
	651	iReg &= 7;
	652	pValue->r80Ex = pFpuCtx->aRegs[iReg].r80Ex;
[35601]	653
[35490]	654	return VINF_SUCCESS;
[35410]	655	}
[35312]	656
[35490]	657
	658	/**
[58116]	659	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	660	*/
[35601]	661	static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
[35410]	662	{
[39078]	663	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
[35410]	664	return VERR_NOT_IMPLEMENTED;
	665	}
	666
[35490]	667
[35601]	668
	669	/*
	670	*
	671	* Hypervisor register access functions.
	672	*
	673	*/
	674
[35490]	675	/**
[58116]	676	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	677	*/
[35601]	678	static DECLCALLBACK(int) cpumR3RegHyperGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
[35410]	679	{
[35601]	680	PVMCPU pVCpu = (PVMCPU)pvUser;
[35490]	681	VMCPU_ASSERT_EMT(pVCpu);
	682
[35601]	683	uint64_t u64Value;
	684	switch (pDesc->offRegister)
	685	{
	686	case 0: u64Value = UINT64_MAX; break;
	687	case 2: u64Value = UINT64_MAX; break;
	688	case 3: u64Value = CPUMGetHyperCR3(pVCpu); break;
	689	case 4: u64Value = UINT64_MAX; break;
	690	case 8: u64Value = UINT64_MAX; break;
	691	default:
[39405]	692	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35601]	693	}
	694	switch (pDesc->enmType)
	695	{
	696	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
	697	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
	698	default:
[39405]	699	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35601]	700	}
[35490]	701	return VINF_SUCCESS;
[35410]	702	}
	703
[35490]	704
	705	/**
[58116]	706	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	707	*/
[35601]	708	static DECLCALLBACK(int) cpumR3RegHyperSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
[35410]	709	{
[35601]	710	/* Not settable, prevents killing your host. */
[39078]	711	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
[35601]	712	return VERR_ACCESS_DENIED;
[35410]	713	}
	714
[35513]	715
[35490]	716	/**
[58116]	717	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35513]	718	*/
[35601]	719	static DECLCALLBACK(int) cpumR3RegHyperGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
[35513]	720	{
[39034]	721	PVMCPU pVCpu = (PVMCPU)pvUser;
[35601]	722	VMCPU_ASSERT_EMT(pVCpu);
	723
	724	uint64_t u64Value;
	725	switch (pDesc->offRegister)
	726	{
	727	case 0: u64Value = CPUMGetHyperDR0(pVCpu); break;
	728	case 1: u64Value = CPUMGetHyperDR1(pVCpu); break;
	729	case 2: u64Value = CPUMGetHyperDR2(pVCpu); break;
	730	case 3: u64Value = CPUMGetHyperDR3(pVCpu); break;
	731	case 6: u64Value = CPUMGetHyperDR6(pVCpu); break;
	732	case 7: u64Value = CPUMGetHyperDR7(pVCpu); break;
	733	default:
[39405]	734	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35601]	735	}
	736	switch (pDesc->enmType)
	737	{
	738	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
	739	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
	740	default:
[39405]	741	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35601]	742	}
	743	return VINF_SUCCESS;
[35513]	744	}
	745
	746
	747	/**
[58116]	748	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35513]	749	*/
[35601]	750	static DECLCALLBACK(int) cpumR3RegHyperSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
[35513]	751	{
[35601]	752	/* Not settable, prevents killing your host. */
[39078]	753	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
[35601]	754	return VERR_ACCESS_DENIED;
[35513]	755	}
	756
	757
	758	/**
[58116]	759	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	760	*/
[35601]	761	static DECLCALLBACK(int) cpumR3RegHyperGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
[35410]	762	{
[39078]	763	NOREF(pvUser);
	764
[35601]	765	/* Not availble at present, return all FFs to keep things quiet */
	766	uint64_t u64Value = UINT64_MAX;
	767	switch (pDesc->enmType)
[35513]	768	{
[35601]	769	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
	770	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
	771	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
	772	default:
[39405]	773	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
[35513]	774	}
	775	return VINF_SUCCESS;
[35410]	776	}
	777
[35513]	778
[35490]	779	/**
[58116]	780	* @interface_method_impl{DBGFREGDESC,pfnGet}
[35490]	781	*/
[35601]	782	static DECLCALLBACK(int) cpumR3RegHyperSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
[35410]	783	{
[35601]	784	/* Not settable, return failure. */
	785	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
	786	return VERR_ACCESS_DENIED;
[35410]	787	}
	788
[35513]	789
[35312]	790	/*
	791	* Set up aliases.
	792	*/
[35468]	793	#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
	794	static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
[35312]	795	{ \
[35468]	796	{ psz32, DBGFREGVALTYPE_U32 }, \
	797	{ psz16, DBGFREGVALTYPE_U16 }, \
	798	{ psz8, DBGFREGVALTYPE_U8 }, \
	799	{ NULL, DBGFREGVALTYPE_INVALID } \
[35312]	800	}
[35468]	801	CPUMREGALIAS_STD(rax, "eax", "ax", "al");
	802	CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
	803	CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
	804	CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
	805	CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
	806	CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
	807	CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
	808	CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
	809	CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
	810	CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
	811	CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
	812	CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
	813	CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
	814	CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
	815	CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
	816	CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
	817	CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
	818	CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
	819	#undef CPUMREGALIAS_STD
[35312]	820
[35468]	821	static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
[35312]	822	{
[35490]	823	{ "fpuip16", DBGFREGVALTYPE_U16 },
[35312]	824	{ NULL, DBGFREGVALTYPE_INVALID }
	825	};
	826
[35468]	827	static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
[35312]	828	{
[35490]	829	{ "fpudp16", DBGFREGVALTYPE_U16 },
[35312]	830	{ NULL, DBGFREGVALTYPE_INVALID }
	831	};
	832
[35468]	833	static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
[35312]	834	{
	835	{ "msw", DBGFREGVALTYPE_U16 },
	836	{ NULL, DBGFREGVALTYPE_INVALID }
	837	};
	838
	839	/*
	840	* Sub fields.
	841	*/
	842	/** Sub-fields for the (hidden) segment attribute register. */
[35468]	843	static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
[35312]	844	{
[35468]	845	DBGFREGSUBFIELD_RW("type", 0, 4, 0),
	846	DBGFREGSUBFIELD_RW("s", 4, 1, 0),
	847	DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
	848	DBGFREGSUBFIELD_RW("p", 7, 1, 0),
	849	DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
	850	DBGFREGSUBFIELD_RW("l", 13, 1, 0),
	851	DBGFREGSUBFIELD_RW("d", 14, 1, 0),
	852	DBGFREGSUBFIELD_RW("g", 15, 1, 0),
	853	DBGFREGSUBFIELD_TERMINATOR()
[35312]	854	};
	855
	856	/** Sub-fields for the flags register. */
[35468]	857	static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
[35312]	858	{
[35468]	859	DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
	860	DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
	861	DBGFREGSUBFIELD_RW("af", 4, 1, 0),
	862	DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
	863	DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
	864	DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
	865	DBGFREGSUBFIELD_RW("if", 9, 1, 0),
	866	DBGFREGSUBFIELD_RW("df", 10, 1, 0),
	867	DBGFREGSUBFIELD_RW("of", 11, 1, 0),
	868	DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
	869	DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
	870	DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
	871	DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
	872	DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
	873	DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
	874	DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
	875	DBGFREGSUBFIELD_RW("id", 21, 1, 0),
	876	DBGFREGSUBFIELD_TERMINATOR()
[35312]	877	};
	878
	879	/** Sub-fields for the FPU control word register. */
[35468]	880	static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
[35312]	881	{
[35468]	882	DBGFREGSUBFIELD_RW("im", 1, 1, 0),
	883	DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
	884	DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
	885	DBGFREGSUBFIELD_RW("om", 4, 1, 0),
	886	DBGFREGSUBFIELD_RW("um", 5, 1, 0),
	887	DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
	888	DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
	889	DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
	890	DBGFREGSUBFIELD_RW("x", 12, 1, 0),
	891	DBGFREGSUBFIELD_TERMINATOR()
[35312]	892	};
	893
	894	/** Sub-fields for the FPU status word register. */
[35468]	895	static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
[35312]	896	{
[35468]	897	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
	898	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
	899	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
	900	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
	901	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
	902	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
	903	DBGFREGSUBFIELD_RW("se", 6, 1, 0),
	904	DBGFREGSUBFIELD_RW("es", 7, 1, 0),
	905	DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
	906	DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
	907	DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
	908	DBGFREGSUBFIELD_RW("top", 11, 3, 0),
	909	DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
	910	DBGFREGSUBFIELD_RW("b", 15, 1, 0),
	911	DBGFREGSUBFIELD_TERMINATOR()
[35312]	912	};
	913
	914	/** Sub-fields for the FPU tag word register. */
[35468]	915	static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
[35312]	916	{
[35468]	917	DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
	918	DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
	919	DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
	920	DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
	921	DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
	922	DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
	923	DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
	924	DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
	925	DBGFREGSUBFIELD_TERMINATOR()
[35312]	926	};
	927
	928	/** Sub-fields for the Multimedia Extensions Control and Status Register. */
[35468]	929	static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
[35312]	930	{
[35468]	931	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
	932	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
	933	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
	934	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
	935	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
	936	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
	937	DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
	938	DBGFREGSUBFIELD_RW("im", 7, 1, 0),
	939	DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
	940	DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
	941	DBGFREGSUBFIELD_RW("om", 10, 1, 0),
	942	DBGFREGSUBFIELD_RW("um", 11, 1, 0),
	943	DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
	944	DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
	945	DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
	946	DBGFREGSUBFIELD_TERMINATOR()
[35312]	947	};
	948
	949	/** Sub-fields for the FPU tag word register. */
[35468]	950	static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
[35312]	951	{
[35468]	952	DBGFREGSUBFIELD_RW("man", 0, 64, 0),
	953	DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
	954	DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
	955	DBGFREGSUBFIELD_TERMINATOR()
[35312]	956	};
	957
	958	/** Sub-fields for the MMX registers. */
[35468]	959	static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
[35312]	960	{
[35468]	961	DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
	962	DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
	963	DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
	964	DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
	965	DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
	966	DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
	967	DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
	968	DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
	969	DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
	970	DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
	971	DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
	972	DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
	973	DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
	974	DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
	975	DBGFREGSUBFIELD_TERMINATOR()
[35312]	976	};
	977
	978	/** Sub-fields for the XMM registers. */
[35468]	979	static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
[35312]	980	{
[35468]	981	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
	982	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
	983	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
	984	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
	985	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
	986	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
	987	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
	988	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
	989	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
	990	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
	991	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
	992	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
	993	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
	994	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
	995	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
	996	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
	997	DBGFREGSUBFIELD_TERMINATOR()
[35312]	998	};
	999
[66885]	1000	#if 0 /* needs special accessor, too lazy for that now. */
	1001	/** Sub-fields for the YMM registers. */
	1002	static DBGFREGSUBFIELD const g_aCpumRegFields_ymmN[] =
	1003	{
	1004	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
	1005	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
	1006	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
	1007	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
	1008	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
	1009	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
	1010	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
	1011	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
	1012	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
	1013	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
	1014	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
	1015	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
	1016	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
	1017	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
	1018	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
	1019	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
	1020	DBGFREGSUBFIELD_RW("r4", 128, 32, 0),
	1021	DBGFREGSUBFIELD_RW("r4.man", 128+ 0, 23, 0),
	1022	DBGFREGSUBFIELD_RW("r4.exp", 128+23, 8, 0),
	1023	DBGFREGSUBFIELD_RW("r4.sig", 128+31, 1, 0),
	1024	DBGFREGSUBFIELD_RW("r5", 160, 32, 0),
	1025	DBGFREGSUBFIELD_RW("r5.man", 160+ 0, 23, 0),
	1026	DBGFREGSUBFIELD_RW("r5.exp", 160+23, 8, 0),
	1027	DBGFREGSUBFIELD_RW("r5.sig", 160+31, 1, 0),
	1028	DBGFREGSUBFIELD_RW("r6", 192, 32, 0),
	1029	DBGFREGSUBFIELD_RW("r6.man", 192+ 0, 23, 0),
	1030	DBGFREGSUBFIELD_RW("r6.exp", 192+23, 8, 0),
	1031	DBGFREGSUBFIELD_RW("r6.sig", 192+31, 1, 0),
	1032	DBGFREGSUBFIELD_RW("r7", 224, 32, 0),
	1033	DBGFREGSUBFIELD_RW("r7.man", 224+ 0, 23, 0),
	1034	DBGFREGSUBFIELD_RW("r7.exp", 224+23, 8, 0),
	1035	DBGFREGSUBFIELD_RW("r7.sig", 224+31, 1, 0),
	1036	DBGFREGSUBFIELD_TERMINATOR()
	1037	};
	1038	#endif
	1039
[35312]	1040	/** Sub-fields for the CR0 register. */
[35468]	1041	static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
[35312]	1042	{
[45793]	1043	DBGFREGSUBFIELD_RW("pe", 0, 1, 0),
	1044	DBGFREGSUBFIELD_RW("mp", 1, 1, 0),
	1045	DBGFREGSUBFIELD_RW("em", 2, 1, 0),
	1046	DBGFREGSUBFIELD_RW("ts", 3, 1, 0),
	1047	DBGFREGSUBFIELD_RO("et", 4, 1, 0),
	1048	DBGFREGSUBFIELD_RW("ne", 5, 1, 0),
	1049	DBGFREGSUBFIELD_RW("wp", 16, 1, 0),
	1050	DBGFREGSUBFIELD_RW("am", 18, 1, 0),
	1051	DBGFREGSUBFIELD_RW("nw", 29, 1, 0),
	1052	DBGFREGSUBFIELD_RW("cd", 30, 1, 0),
	1053	DBGFREGSUBFIELD_RW("pg", 31, 1, 0),
[35468]	1054	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1055	};
	1056
	1057	/** Sub-fields for the CR3 register. */
[35468]	1058	static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
[35312]	1059	{
[45793]	1060	DBGFREGSUBFIELD_RW("pwt", 3, 1, 0),
	1061	DBGFREGSUBFIELD_RW("pcd", 4, 1, 0),
[35468]	1062	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1063	};
	1064
	1065	/** Sub-fields for the CR4 register. */
[35468]	1066	static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
[35312]	1067	{
[45793]	1068	DBGFREGSUBFIELD_RW("vme", 0, 1, 0),
	1069	DBGFREGSUBFIELD_RW("pvi", 1, 1, 0),
	1070	DBGFREGSUBFIELD_RW("tsd", 2, 1, 0),
	1071	DBGFREGSUBFIELD_RW("de", 3, 1, 0),
	1072	DBGFREGSUBFIELD_RW("pse", 4, 1, 0),
	1073	DBGFREGSUBFIELD_RW("pae", 5, 1, 0),
	1074	DBGFREGSUBFIELD_RW("mce", 6, 1, 0),
	1075	DBGFREGSUBFIELD_RW("pge", 7, 1, 0),
	1076	DBGFREGSUBFIELD_RW("pce", 8, 1, 0),
[54862]	1077	DBGFREGSUBFIELD_RW("osfxsr", 9, 1, 0),
[45793]	1078	DBGFREGSUBFIELD_RW("osxmmeexcpt", 10, 1, 0),
[54862]	1079	DBGFREGSUBFIELD_RW("vmxe", 13, 1, 0),
	1080	DBGFREGSUBFIELD_RW("smxe", 14, 1, 0),
	1081	DBGFREGSUBFIELD_RW("pcide", 17, 1, 0),
	1082	DBGFREGSUBFIELD_RW("osxsave", 18, 1, 0),
	1083	DBGFREGSUBFIELD_RW("smep", 20, 1, 0),
	1084	DBGFREGSUBFIELD_RW("smap", 21, 1, 0),
[35468]	1085	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1086	};
	1087
	1088	/** Sub-fields for the DR6 register. */
[35468]	1089	static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
[35312]	1090	{
[45793]	1091	DBGFREGSUBFIELD_RW("b0", 0, 1, 0),
	1092	DBGFREGSUBFIELD_RW("b1", 1, 1, 0),
	1093	DBGFREGSUBFIELD_RW("b2", 2, 1, 0),
	1094	DBGFREGSUBFIELD_RW("b3", 3, 1, 0),
	1095	DBGFREGSUBFIELD_RW("bd", 13, 1, 0),
	1096	DBGFREGSUBFIELD_RW("bs", 14, 1, 0),
	1097	DBGFREGSUBFIELD_RW("bt", 15, 1, 0),
[35468]	1098	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1099	};
	1100
	1101	/** Sub-fields for the DR7 register. */
[35468]	1102	static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
[35312]	1103	{
[45793]	1104	DBGFREGSUBFIELD_RW("l0", 0, 1, 0),
	1105	DBGFREGSUBFIELD_RW("g0", 1, 1, 0),
	1106	DBGFREGSUBFIELD_RW("l1", 2, 1, 0),
	1107	DBGFREGSUBFIELD_RW("g1", 3, 1, 0),
	1108	DBGFREGSUBFIELD_RW("l2", 4, 1, 0),
	1109	DBGFREGSUBFIELD_RW("g2", 5, 1, 0),
	1110	DBGFREGSUBFIELD_RW("l3", 6, 1, 0),
	1111	DBGFREGSUBFIELD_RW("g3", 7, 1, 0),
	1112	DBGFREGSUBFIELD_RW("le", 8, 1, 0),
	1113	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
	1114	DBGFREGSUBFIELD_RW("gd", 13, 1, 0),
	1115	DBGFREGSUBFIELD_RW("rw0", 16, 2, 0),
	1116	DBGFREGSUBFIELD_RW("len0", 18, 2, 0),
	1117	DBGFREGSUBFIELD_RW("rw1", 20, 2, 0),
	1118	DBGFREGSUBFIELD_RW("len1", 22, 2, 0),
	1119	DBGFREGSUBFIELD_RW("rw2", 24, 2, 0),
	1120	DBGFREGSUBFIELD_RW("len2", 26, 2, 0),
	1121	DBGFREGSUBFIELD_RW("rw3", 28, 2, 0),
	1122	DBGFREGSUBFIELD_RW("len3", 30, 2, 0),
[35468]	1123	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1124	};
	1125
	1126	/** Sub-fields for the CR_PAT MSR. */
[35468]	1127	static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
[35312]	1128	{
[35468]	1129	DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
	1130	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
	1131	DBGFREGSUBFIELD_RW("base", 12, 20, 12),
	1132	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1133	};
	1134
	1135	/** Sub-fields for the CR_PAT MSR. */
[35468]	1136	static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
[35312]	1137	{
	1138	/** @todo */
[35468]	1139	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1140	};
	1141
	1142	/** Sub-fields for the PERF_STATUS MSR. */
[35468]	1143	static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
[35312]	1144	{
	1145	/** @todo */
[35468]	1146	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1147	};
	1148
	1149	/** Sub-fields for the EFER MSR. */
[35468]	1150	static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
[35312]	1151	{
	1152	/** @todo */
[35468]	1153	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1154	};
	1155
	1156	/** Sub-fields for the STAR MSR. */
[35468]	1157	static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
[35312]	1158	{
	1159	/** @todo */
[35468]	1160	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1161	};
	1162
	1163	/** Sub-fields for the CSTAR MSR. */
[35468]	1164	static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
[35312]	1165	{
	1166	/** @todo */
[35468]	1167	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1168	};
	1169
	1170	/** Sub-fields for the LSTAR MSR. */
[35468]	1171	static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
[35312]	1172	{
	1173	/** @todo */
[35468]	1174	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1175	};
	1176
[63465]	1177	#if 0 /** @todo */
[35312]	1178	/** Sub-fields for the SF_MASK MSR. */
[35468]	1179	static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
[35312]	1180	{
	1181	/** @todo */
[35468]	1182	DBGFREGSUBFIELD_TERMINATOR()
[35312]	1183	};
[63465]	1184	#endif
[35312]	1185
	1186
[35601]	1187	/** @name Macros for producing register descriptor table entries.
	1188	* @{ */
	1189	#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
	1190	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
[35312]	1191
[35601]	1192	#define CPU_REG_REG(UName, LName) \
	1193	CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
	1194
	1195	#define CPU_REG_SEG(UName, LName) \
[41906]	1196	CPU_REG_RW_AS(#LName, UName, U16, LName.Sel, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
	1197	CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
	1198	CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
	1199	CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
[35601]	1200
	1201	#define CPU_REG_MM(n) \
[66885]	1202	CPU_REG_XS_RW_AS("mm" #n, MM##n, U64, x87.aRegs[n].mmx, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mmN)
[35601]	1203
	1204	#define CPU_REG_XMM(n) \
[66885]	1205	CPU_REG_XS_RW_AS("xmm" #n, XMM##n, U128, x87.aXMM[n].xmm, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_xmmN)
	1206
	1207	#define CPU_REG_YMM(n) \
	1208	{ "ymm" #n, DBGFREG_YMM##n, DBGFREGVALTYPE_U256, 0 /fFlags/, n, cpumR3RegGet_ymm, cpumR3RegSet_ymm, NULL /paAliases/, NULL /paSubFields/ }
	1209
[35601]	1210	/** @} */
	1211
	1212
[35312]	1213	/**
[35601]	1214	* The guest register descriptors.
[35312]	1215	*/
[35601]	1216	static DBGFREGDESC const g_aCpumRegGstDescs[] =
[35312]	1217	{
[35601]	1218	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
	1219	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
	1220	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
	1221	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
[55048]	1222	#define CPU_REG_XS_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
	1223	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
	1224	#define CPU_REG_XS_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
	1225	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
[35601]	1226	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
	1227	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
	1228	#define CPU_REG_ST(n) \
	1229	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
[35490]	1230
[35601]	1231	CPU_REG_REG(RAX, rax),
	1232	CPU_REG_REG(RCX, rcx),
	1233	CPU_REG_REG(RDX, rdx),
	1234	CPU_REG_REG(RBX, rbx),
	1235	CPU_REG_REG(RSP, rsp),
	1236	CPU_REG_REG(RBP, rbp),
	1237	CPU_REG_REG(RSI, rsi),
	1238	CPU_REG_REG(RDI, rdi),
	1239	CPU_REG_REG(R8, r8),
	1240	CPU_REG_REG(R9, r9),
	1241	CPU_REG_REG(R10, r10),
	1242	CPU_REG_REG(R11, r11),
	1243	CPU_REG_REG(R12, r12),
	1244	CPU_REG_REG(R13, r13),
	1245	CPU_REG_REG(R14, r14),
	1246	CPU_REG_REG(R15, r15),
	1247	CPU_REG_SEG(CS, cs),
	1248	CPU_REG_SEG(DS, ds),
	1249	CPU_REG_SEG(ES, es),
	1250	CPU_REG_SEG(FS, fs),
	1251	CPU_REG_SEG(GS, gs),
	1252	CPU_REG_SEG(SS, ss),
	1253	CPU_REG_REG(RIP, rip),
[55048]	1254	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
	1255	CPU_REG_XS_RW_AS("fcw", FCW, U16, x87.FCW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fcw ),
	1256	CPU_REG_XS_RW_AS("fsw", FSW, U16, x87.FSW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fsw ),
	1257	CPU_REG_XS_RO_AS("ftw", FTW, U16, x87, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
	1258	CPU_REG_XS_RW_AS("fop", FOP, U16, x87.FOP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
	1259	CPU_REG_XS_RW_AS("fpuip", FPUIP, U32, x87.FPUIP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpuip, NULL ),
	1260	CPU_REG_XS_RW_AS("fpucs", FPUCS, U16, x87.CS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
	1261	CPU_REG_XS_RW_AS("fpudp", FPUDP, U32, x87.FPUDP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpudp, NULL ),
	1262	CPU_REG_XS_RW_AS("fpuds", FPUDS, U16, x87.DS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
	1263	CPU_REG_XS_RW_AS("mxcsr", MXCSR, U32, x87.MXCSR, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
	1264	CPU_REG_XS_RW_AS("mxcsr_mask", MXCSR_MASK, U32, x87.MXCSR_MASK, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
[35601]	1265	CPU_REG_ST(0),
	1266	CPU_REG_ST(1),
	1267	CPU_REG_ST(2),
	1268	CPU_REG_ST(3),
	1269	CPU_REG_ST(4),
	1270	CPU_REG_ST(5),
	1271	CPU_REG_ST(6),
	1272	CPU_REG_ST(7),
	1273	CPU_REG_MM(0),
	1274	CPU_REG_MM(1),
	1275	CPU_REG_MM(2),
	1276	CPU_REG_MM(3),
	1277	CPU_REG_MM(4),
	1278	CPU_REG_MM(5),
	1279	CPU_REG_MM(6),
	1280	CPU_REG_MM(7),
	1281	CPU_REG_XMM(0),
	1282	CPU_REG_XMM(1),
	1283	CPU_REG_XMM(2),
	1284	CPU_REG_XMM(3),
	1285	CPU_REG_XMM(4),
	1286	CPU_REG_XMM(5),
	1287	CPU_REG_XMM(6),
	1288	CPU_REG_XMM(7),
	1289	CPU_REG_XMM(8),
	1290	CPU_REG_XMM(9),
	1291	CPU_REG_XMM(10),
	1292	CPU_REG_XMM(11),
	1293	CPU_REG_XMM(12),
	1294	CPU_REG_XMM(13),
	1295	CPU_REG_XMM(14),
	1296	CPU_REG_XMM(15),
[66885]	1297	CPU_REG_YMM(0),
	1298	CPU_REG_YMM(1),
	1299	CPU_REG_YMM(2),
	1300	CPU_REG_YMM(3),
	1301	CPU_REG_YMM(4),
	1302	CPU_REG_YMM(5),
	1303	CPU_REG_YMM(6),
	1304	CPU_REG_YMM(7),
	1305	CPU_REG_YMM(8),
	1306	CPU_REG_YMM(9),
	1307	CPU_REG_YMM(10),
	1308	CPU_REG_YMM(11),
	1309	CPU_REG_YMM(12),
	1310	CPU_REG_YMM(13),
	1311	CPU_REG_YMM(14),
	1312	CPU_REG_YMM(15),
[35601]	1313	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
[35625]	1314	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
[35601]	1315	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
[35625]	1316	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
[35601]	1317	CPU_REG_SEG(LDTR, ldtr),
	1318	CPU_REG_SEG(TR, tr),
[35625]	1319	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
	1320	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
	1321	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
	1322	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
	1323	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
	1324	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
	1325	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
	1326	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
	1327	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
	1328	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
	1329	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
[35601]	1330	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
	1331	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
	1332	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
	1333	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
	1334	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
	1335	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
	1336	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
	1337	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
	1338	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
	1339	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
	1340	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
	1341	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
	1342	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
	1343	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
	1344	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
	1345	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
	1346	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
	1347	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
	1348	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
	1349	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
	1350	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
	1351	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
[35490]	1352	DBGFREGDESC_TERMINATOR()
[35601]	1353
	1354	#undef CPU_REG_RW_AS
	1355	#undef CPU_REG_RO_AS
	1356	#undef CPU_REG_MSR
	1357	#undef CPU_REG_ST
[35312]	1358	};
	1359
[35490]	1360
	1361	/**
[35601]	1362	* The hypervisor (raw-mode) register descriptors.
	1363	*/
	1364	static DBGFREGDESC const g_aCpumRegHyperDescs[] =
	1365	{
	1366	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
	1367	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
	1368	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
	1369	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
[55048]	1370	#define CPU_REG_DUMMY(a_szName, a_RegSuff, a_TypeSuff) \
	1371	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, 0, cpumR3RegGet_Dummy, cpumR3RegSet_Dummy, NULL, NULL}
[35601]	1372	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
	1373	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegHyperGet_msr, cpumR3RegHyperSet_msr, NULL, a_paSubFields)
	1374
	1375	CPU_REG_REG(RAX, rax),
	1376	CPU_REG_REG(RCX, rcx),
	1377	CPU_REG_REG(RDX, rdx),
	1378	CPU_REG_REG(RBX, rbx),
	1379	CPU_REG_REG(RSP, rsp),
	1380	CPU_REG_REG(RBP, rbp),
	1381	CPU_REG_REG(RSI, rsi),
	1382	CPU_REG_REG(RDI, rdi),
	1383	CPU_REG_REG(R8, r8),
	1384	CPU_REG_REG(R9, r9),
	1385	CPU_REG_REG(R10, r10),
	1386	CPU_REG_REG(R11, r11),
	1387	CPU_REG_REG(R12, r12),
	1388	CPU_REG_REG(R13, r13),
	1389	CPU_REG_REG(R14, r14),
	1390	CPU_REG_REG(R15, r15),
	1391	CPU_REG_SEG(CS, cs),
	1392	CPU_REG_SEG(DS, ds),
	1393	CPU_REG_SEG(ES, es),
	1394	CPU_REG_SEG(FS, fs),
	1395	CPU_REG_SEG(GS, gs),
	1396	CPU_REG_SEG(SS, ss),
	1397	CPU_REG_REG(RIP, rip),
	1398	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
[55048]	1399	CPU_REG_DUMMY("fcw", FCW, U16),
	1400	CPU_REG_DUMMY("fsw", FSW, U16),
	1401	CPU_REG_DUMMY("ftw", FTW, U16),
	1402	CPU_REG_DUMMY("fop", FOP, U16),
	1403	CPU_REG_DUMMY("fpuip", FPUIP, U32),
	1404	CPU_REG_DUMMY("fpucs", FPUCS, U16),
	1405	CPU_REG_DUMMY("fpudp", FPUDP, U32),
	1406	CPU_REG_DUMMY("fpuds", FPUDS, U16),
	1407	CPU_REG_DUMMY("mxcsr", MXCSR, U32),
	1408	CPU_REG_DUMMY("mxcsr_mask", MXCSR_MASK, U32),
	1409	CPU_REG_DUMMY("st0", ST0, R80),
	1410	CPU_REG_DUMMY("st1", ST1, R80),
	1411	CPU_REG_DUMMY("st2", ST2, R80),
	1412	CPU_REG_DUMMY("st3", ST3, R80),
	1413	CPU_REG_DUMMY("st4", ST4, R80),
	1414	CPU_REG_DUMMY("st5", ST5, R80),
	1415	CPU_REG_DUMMY("st6", ST6, R80),
	1416	CPU_REG_DUMMY("st7", ST7, R80),
	1417	CPU_REG_DUMMY("mm0", MM0, U64),
	1418	CPU_REG_DUMMY("mm1", MM1, U64),
	1419	CPU_REG_DUMMY("mm2", MM2, U64),
	1420	CPU_REG_DUMMY("mm3", MM3, U64),
	1421	CPU_REG_DUMMY("mm4", MM4, U64),
	1422	CPU_REG_DUMMY("mm5", MM5, U64),
	1423	CPU_REG_DUMMY("mm6", MM6, U64),
	1424	CPU_REG_DUMMY("mm7", MM7, U64),
	1425	CPU_REG_DUMMY("xmm0", XMM0, U128),
	1426	CPU_REG_DUMMY("xmm1", XMM1, U128),
	1427	CPU_REG_DUMMY("xmm2", XMM2, U128),
	1428	CPU_REG_DUMMY("xmm3", XMM3, U128),
	1429	CPU_REG_DUMMY("xmm4", XMM4, U128),
	1430	CPU_REG_DUMMY("xmm5", XMM5, U128),
	1431	CPU_REG_DUMMY("xmm6", XMM6, U128),
	1432	CPU_REG_DUMMY("xmm7", XMM7, U128),
	1433	CPU_REG_DUMMY("xmm8", XMM8, U128),
	1434	CPU_REG_DUMMY("xmm9", XMM9, U128),
	1435	CPU_REG_DUMMY("xmm10", XMM10, U128),
	1436	CPU_REG_DUMMY("xmm11", XMM11, U128),
	1437	CPU_REG_DUMMY("xmm12", XMM12, U128),
	1438	CPU_REG_DUMMY("xmm13", XMM13, U128),
	1439	CPU_REG_DUMMY("xmm14", XMM14, U128),
	1440	CPU_REG_DUMMY("xmm15", XMM15, U128),
[66885]	1441	CPU_REG_DUMMY("ymm0", YMM0, U256),
	1442	CPU_REG_DUMMY("ymm1", YMM1, U256),
	1443	CPU_REG_DUMMY("ymm2", YMM2, U256),
	1444	CPU_REG_DUMMY("ymm3", YMM3, U256),
	1445	CPU_REG_DUMMY("ymm4", YMM4, U256),
	1446	CPU_REG_DUMMY("ymm5", YMM5, U256),
	1447	CPU_REG_DUMMY("ymm6", YMM6, U256),
	1448	CPU_REG_DUMMY("ymm7", YMM7, U256),
	1449	CPU_REG_DUMMY("ymm8", YMM8, U256),
	1450	CPU_REG_DUMMY("ymm9", YMM9, U256),
	1451	CPU_REG_DUMMY("ymm10", YMM10, U256),
	1452	CPU_REG_DUMMY("ymm11", YMM11, U256),
	1453	CPU_REG_DUMMY("ymm12", YMM12, U256),
	1454	CPU_REG_DUMMY("ymm13", YMM13, U256),
	1455	CPU_REG_DUMMY("ymm14", YMM14, U256),
	1456	CPU_REG_DUMMY("ymm15", YMM15, U256),
[35601]	1457	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
[35625]	1458	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
[35601]	1459	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
[35625]	1460	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
[35601]	1461	CPU_REG_SEG(LDTR, ldtr),
	1462	CPU_REG_SEG(TR, tr),
	1463	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
	1464	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
	1465	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr3 ),
	1466	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr4 ),
	1467	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
	1468	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
	1469	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
	1470	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
	1471	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
	1472	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr6 ),
	1473	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr7 ),
	1474	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
	1475	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
	1476	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
	1477	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
	1478	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
	1479	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
	1480	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
	1481	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
	1482	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
	1483	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
	1484	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
	1485	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
	1486	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
	1487	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
	1488	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
	1489	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
	1490	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
	1491	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
	1492	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
	1493	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
	1494	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
	1495	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
	1496	DBGFREGDESC_TERMINATOR()
	1497	#undef CPU_REG_RW_AS
	1498	#undef CPU_REG_RO_AS
	1499	#undef CPU_REG_MSR
	1500	#undef CPU_REG_ST
	1501	};
	1502
	1503
	1504	/**
[35490]	1505	* Initializes the debugger related sides of the CPUM component.
	1506	*
	1507	* Called by CPUMR3Init.
	1508	*
	1509	* @returns VBox status code.
[58122]	1510	* @param pVM The cross context VM structure.
[35490]	1511	*/
	1512	int cpumR3DbgInit(PVM pVM)
	1513	{
	1514	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
	1515	{
[35601]	1516	int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /fGuestRegs/);
[35490]	1517	AssertLogRelRCReturn(rc, rc);
[35601]	1518	rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /fGuestRegs/);
	1519	AssertLogRelRCReturn(rc, rc);
[35490]	1520	}
	1521
	1522	return VINF_SUCCESS;
	1523	}
	1524

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