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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM-armv8.cpp@ 99740

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1/* $Id: CPUM-armv8.cpp 99739 2023-05-11 01:01:08Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager (ARMv8 variant).
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28/** @page pg_cpum CPUM - CPU Monitor / Manager
29 *
30 * The CPU Monitor / Manager keeps track of all the CPU registers.
31 * This is the ARMv8 variant which is doing much less than its x86/amd64
32 * counterpart due to the fact that we currently only support the NEM backends
33 * for running ARM guests. It might become complex iff we decide to implement our
34 * own hypervisor.
35 *
36 * @section sec_cpum_logging_armv8 Logging Level Assignments.
37 *
38 * Following log level assignments:
39 * - @todo
40 *
41 */
42
43
44/*********************************************************************************************************************************
45* Header Files *
46*********************************************************************************************************************************/
47#define LOG_GROUP LOG_GROUP_CPUM
48#define CPUM_WITH_NONCONST_HOST_FEATURES
49#include <VBox/vmm/cpum.h>
50#include <VBox/vmm/cpumdis.h>
51#include <VBox/vmm/pgm.h>
52#include <VBox/vmm/mm.h>
53#include <VBox/vmm/em.h>
54#include <VBox/vmm/iem.h>
55#include <VBox/vmm/dbgf.h>
56#include <VBox/vmm/ssm.h>
57#include "CPUMInternal-armv8.h"
58#include <VBox/vmm/vm.h>
59
60#include <VBox/param.h>
61#include <VBox/dis.h>
62#include <VBox/err.h>
63#include <VBox/log.h>
64#include <iprt/assert.h>
65#include <iprt/cpuset.h>
66#include <iprt/mem.h>
67#include <iprt/mp.h>
68#include <iprt/string.h>
69#include <iprt/armv8.h>
70
71
72/*********************************************************************************************************************************
73* Structures and Typedefs *
74*********************************************************************************************************************************/
75
76/**
77 * What kind of cpu info dump to perform.
78 */
79typedef enum CPUMDUMPTYPE
80{
81 CPUMDUMPTYPE_TERSE,
82 CPUMDUMPTYPE_DEFAULT,
83 CPUMDUMPTYPE_VERBOSE
84} CPUMDUMPTYPE;
85/** Pointer to a cpu info dump type. */
86typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
87
88
89/*********************************************************************************************************************************
90* Internal Functions *
91*********************************************************************************************************************************/
92static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
93static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
94static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
95static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
96static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
97static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
98static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
99static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100
101
102/*********************************************************************************************************************************
103* Global Variables *
104*********************************************************************************************************************************/
105#if 0 /** @todo Will come later. */
106/** Saved state field descriptors for CPUMCTX. */
107static const SSMFIELD g_aCpumCtxFields[] =
108{
109 SSMFIELD_ENTRY( CPUMCTX, aGRegs[0].x),
110 SSMFIELD_ENTRY( CPUMCTX, aGRegs[1].x),
111 SSMFIELD_ENTRY( CPUMCTX, aGRegs[2].x),
112 SSMFIELD_ENTRY( CPUMCTX, aGRegs[3].x),
113 SSMFIELD_ENTRY( CPUMCTX, aGRegs[4].x),
114 SSMFIELD_ENTRY( CPUMCTX, aGRegs[5].x),
115 SSMFIELD_ENTRY( CPUMCTX, aGRegs[6].x),
116 SSMFIELD_ENTRY( CPUMCTX, aGRegs[7].x),
117 SSMFIELD_ENTRY( CPUMCTX, aGRegs[8].x),
118 SSMFIELD_ENTRY( CPUMCTX, aGRegs[9].x),
119 SSMFIELD_ENTRY( CPUMCTX, aGRegs[10].x),
120 SSMFIELD_ENTRY( CPUMCTX, aGRegs[11].x),
121 SSMFIELD_ENTRY( CPUMCTX, aGRegs[12].x),
122 SSMFIELD_ENTRY( CPUMCTX, aGRegs[13].x),
123 SSMFIELD_ENTRY( CPUMCTX, aGRegs[14].x),
124 SSMFIELD_ENTRY( CPUMCTX, aGRegs[15].x),
125 SSMFIELD_ENTRY( CPUMCTX, aGRegs[16].x),
126 SSMFIELD_ENTRY( CPUMCTX, aGRegs[17].x),
127 SSMFIELD_ENTRY( CPUMCTX, aGRegs[18].x),
128 SSMFIELD_ENTRY( CPUMCTX, aGRegs[19].x),
129 SSMFIELD_ENTRY( CPUMCTX, aGRegs[20].x),
130 SSMFIELD_ENTRY( CPUMCTX, aGRegs[21].x),
131 SSMFIELD_ENTRY( CPUMCTX, aGRegs[22].x),
132 SSMFIELD_ENTRY( CPUMCTX, aGRegs[23].x),
133 SSMFIELD_ENTRY( CPUMCTX, aGRegs[24].x),
134 SSMFIELD_ENTRY( CPUMCTX, aGRegs[25].x),
135 SSMFIELD_ENTRY( CPUMCTX, aGRegs[26].x),
136 SSMFIELD_ENTRY( CPUMCTX, aGRegs[27].x),
137 SSMFIELD_ENTRY( CPUMCTX, aGRegs[28].x),
138 SSMFIELD_ENTRY( CPUMCTX, aGRegs[29].x),
139 SSMFIELD_ENTRY( CPUMCTX, aGRegs[30].x),
140 SSMFIELD_ENTRY( CPUMCTX, aVRegs[0].v),
141 SSMFIELD_ENTRY( CPUMCTX, aVRegs[1].v),
142 SSMFIELD_ENTRY( CPUMCTX, aVRegs[2].v),
143 SSMFIELD_ENTRY( CPUMCTX, aVRegs[3].v),
144 SSMFIELD_ENTRY( CPUMCTX, aVRegs[4].v),
145 SSMFIELD_ENTRY( CPUMCTX, aVRegs[5].v),
146 SSMFIELD_ENTRY( CPUMCTX, aVRegs[6].v),
147 SSMFIELD_ENTRY( CPUMCTX, aVRegs[7].v),
148 SSMFIELD_ENTRY( CPUMCTX, aVRegs[8].v),
149 SSMFIELD_ENTRY( CPUMCTX, aVRegs[9].v),
150 SSMFIELD_ENTRY( CPUMCTX, aVRegs[10].v),
151 SSMFIELD_ENTRY( CPUMCTX, aVRegs[11].v),
152 SSMFIELD_ENTRY( CPUMCTX, aVRegs[12].v),
153 SSMFIELD_ENTRY( CPUMCTX, aVRegs[13].v),
154 SSMFIELD_ENTRY( CPUMCTX, aVRegs[14].v),
155 SSMFIELD_ENTRY( CPUMCTX, aVRegs[15].v),
156 SSMFIELD_ENTRY( CPUMCTX, aVRegs[16].v),
157 SSMFIELD_ENTRY( CPUMCTX, aVRegs[17].v),
158 SSMFIELD_ENTRY( CPUMCTX, aVRegs[18].v),
159 SSMFIELD_ENTRY( CPUMCTX, aVRegs[19].v),
160 SSMFIELD_ENTRY( CPUMCTX, aVRegs[20].v),
161 SSMFIELD_ENTRY( CPUMCTX, aVRegs[21].v),
162 SSMFIELD_ENTRY( CPUMCTX, aVRegs[22].v),
163 SSMFIELD_ENTRY( CPUMCTX, aVRegs[23].v),
164 SSMFIELD_ENTRY( CPUMCTX, aVRegs[24].v),
165 SSMFIELD_ENTRY( CPUMCTX, aVRegs[25].v),
166 SSMFIELD_ENTRY( CPUMCTX, aVRegs[26].v),
167 SSMFIELD_ENTRY( CPUMCTX, aVRegs[27].v),
168 SSMFIELD_ENTRY( CPUMCTX, aVRegs[28].v),
169 SSMFIELD_ENTRY( CPUMCTX, aVRegs[29].v),
170 SSMFIELD_ENTRY( CPUMCTX, aVRegs[30].v),
171 SSMFIELD_ENTRY( CPUMCTX, aVRegs[31].v),
172 SSMFIELD_ENTRY( CPUMCTX, aSpReg[0].u64),
173 SSMFIELD_ENTRY( CPUMCTX, aSpReg[1].u64),
174 SSMFIELD_ENTRY( CPUMCTX, Pc.u64),
175 SSMFIELD_ENTRY( CPUMCTX, Spsr.u64),
176 SSMFIELD_ENTRY( CPUMCTX, Elr.u64),
177 SSMFIELD_ENTRY( CPUMCTX, fpcr),
178 SSMFIELD_ENTRY( CPUMCTX, fpsr),
179 SSMFIELD_ENTRY( CPUMCTX, fPState),
180 /** @todo */
181 SSMFIELD_ENTRY_TERM()
182};
183#endif
184
185
186/**
187 * Initializes the CPUM.
188 *
189 * @returns VBox status code.
190 * @param pVM The cross context VM structure.
191 */
192VMMR3DECL(int) CPUMR3Init(PVM pVM)
193{
194 LogFlow(("CPUMR3Init\n"));
195
196 /*
197 * Assert alignment, sizes and tables.
198 */
199 AssertCompileMemberAlignment(VM, cpum.s, 32);
200 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
201 AssertCompileSizeAlignment(CPUMCTX, 64);
202 AssertCompileMemberAlignment(VM, cpum, 64);
203 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
204#ifdef VBOX_STRICT
205 int rc2 = cpumR3SysRegStrictInitChecks();
206 AssertRCReturn(rc2, rc2);
207#endif
208
209 pVM->cpum.s.GuestInfo.paSysRegRangesR3 = &pVM->cpum.s.GuestInfo.aSysRegRanges[0];
210
211 /*
212 * Register saved state data item.
213 */
214 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
215 NULL, cpumR3LiveExec, NULL,
216 NULL, cpumR3SaveExec, NULL,
217 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
218 if (RT_FAILURE(rc))
219 return rc;
220
221 /*
222 * Register info handlers and registers with the debugger facility.
223 */
224 DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
225 &cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
226 DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
227 &cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
228
229 rc = cpumR3DbgInit(pVM);
230 if (RT_FAILURE(rc))
231 return rc;
232
233 /*
234 * Initialize the general guest CPU state.
235 */
236 CPUMR3Reset(pVM);
237
238 return VINF_SUCCESS;
239}
240
241
242/**
243 * Applies relocations to data and code managed by this
244 * component. This function will be called at init and
245 * whenever the VMM need to relocate it self inside the GC.
246 *
247 * The CPUM will update the addresses used by the switcher.
248 *
249 * @param pVM The cross context VM structure.
250 */
251VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
252{
253 RT_NOREF(pVM);
254}
255
256
257/**
258 * Terminates the CPUM.
259 *
260 * Termination means cleaning up and freeing all resources,
261 * the VM it self is at this point powered off or suspended.
262 *
263 * @returns VBox status code.
264 * @param pVM The cross context VM structure.
265 */
266VMMR3DECL(int) CPUMR3Term(PVM pVM)
267{
268 RT_NOREF(pVM);
269 return VINF_SUCCESS;
270}
271
272
273/**
274 * Resets a virtual CPU.
275 *
276 * Used by CPUMR3Reset and CPU hot plugging.
277 *
278 * @param pVM The cross context VM structure.
279 * @param pVCpu The cross context virtual CPU structure of the CPU that is
280 * being reset. This may differ from the current EMT.
281 */
282VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
283{
284 RT_NOREF(pVM);
285
286 /** @todo anything different for VCPU > 0? */
287 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
288
289 /*
290 * Initialize everything to ZERO first.
291 */
292 RT_BZERO(pCtx, sizeof(*pCtx));
293
294 /* Start in Supervisor mode. */
295 /** @todo Differentiate between Aarch64 and Aarch32 configuation. */
296 pCtx->fPState = ARMV8_SPSR_EL2_AARCH64_SET_EL(ARMV8_AARCH64_EL_1)
297 | ARMV8_SPSR_EL2_AARCH64_SP
298 | ARMV8_SPSR_EL2_AARCH64_D
299 | ARMV8_SPSR_EL2_AARCH64_A
300 | ARMV8_SPSR_EL2_AARCH64_I
301 | ARMV8_SPSR_EL2_AARCH64_F;
302 /** @todo */
303}
304
305
306/**
307 * Resets the CPU.
308 *
309 * @param pVM The cross context VM structure.
310 */
311VMMR3DECL(void) CPUMR3Reset(PVM pVM)
312{
313 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
314 {
315 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
316 CPUMR3ResetCpu(pVM, pVCpu);
317 }
318}
319
320
321
322
323/**
324 * Pass 0 live exec callback.
325 *
326 * @returns VINF_SSM_DONT_CALL_AGAIN.
327 * @param pVM The cross context VM structure.
328 * @param pSSM The saved state handle.
329 * @param uPass The pass (0).
330 */
331static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
332{
333 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
334 /** @todo */ RT_NOREF(pVM, pSSM);
335 return VINF_SSM_DONT_CALL_AGAIN;
336}
337
338
339/**
340 * Execute state save operation.
341 *
342 * @returns VBox status code.
343 * @param pVM The cross context VM structure.
344 * @param pSSM SSM operation handle.
345 */
346static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
347{
348 /*
349 * Save.
350 */
351 SSMR3PutU32(pSSM, pVM->cCpus);
352 /** @todo */
353 return VINF_SUCCESS;
354}
355
356
357/**
358 * @callback_method_impl{FNSSMINTLOADPREP}
359 */
360static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
361{
362 RT_NOREF(pSSM);
363 pVM->cpum.s.fPendingRestore = true;
364 return VINF_SUCCESS;
365}
366
367
368/**
369 * @callback_method_impl{FNSSMINTLOADEXEC}
370 */
371static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
372{
373 /*
374 * Validate version.
375 */
376 /** @todo */ RT_NOREF(pSSM, uVersion);
377
378 if (uPass == SSM_PASS_FINAL)
379 {
380 /** @todo */
381 }
382
383 pVM->cpum.s.fPendingRestore = false;
384 return VINF_SUCCESS;
385}
386
387
388/**
389 * @callback_method_impl{FNSSMINTLOADDONE}
390 */
391static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
392{
393 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
394 return VINF_SUCCESS;
395
396 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
397 if (pVM->cpum.s.fPendingRestore)
398 {
399 LogRel(("CPUM: Missing state!\n"));
400 return VERR_INTERNAL_ERROR_2;
401 }
402
403 /** @todo */
404 return VINF_SUCCESS;
405}
406
407
408/**
409 * Checks if the CPUM state restore is still pending.
410 *
411 * @returns true / false.
412 * @param pVM The cross context VM structure.
413 */
414VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
415{
416 return pVM->cpum.s.fPendingRestore;
417}
418
419
420/**
421 * Formats the PSTATE value into mnemonics.
422 *
423 * @param pszPState Where to write the mnemonics. (Assumes sufficient buffer space.)
424 * @param fPState The PSTATE value with both guest hardware and VBox
425 * internal bits included.
426 */
427static void cpumR3InfoFormatPState(char *pszPState, uint32_t fPState)
428{
429 /*
430 * Format the flags.
431 */
432 static const struct
433 {
434 const char *pszSet; const char *pszClear; uint32_t fFlag;
435 } s_aFlags[] =
436 {
437 { NULL, NULL, 0 }, /** @todo */
438 };
439 char *psz = pszPState;
440 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
441 {
442 const char *pszAdd = s_aFlags[i].fFlag & fPState ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
443 if (pszAdd)
444 {
445 strcpy(psz, pszAdd);
446 psz += strlen(pszAdd);
447 *psz++ = ' ';
448 }
449 }
450 psz[-1] = '\0';
451}
452
453
454/**
455 * Formats a full register dump.
456 *
457 * @param pVM The cross context VM structure.
458 * @param pCtx The context to format.
459 * @param pHlp Output functions.
460 * @param enmType The dump type.
461 * @param pszPrefix Register name prefix.
462 */
463static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
464{
465 RT_NOREF(pVM, pHlp, enmType, pszPrefix);
466
467 /*
468 * Format the PSTATE.
469 */
470 char szPState[80];
471 cpumR3InfoFormatPState(&szPState[0], pCtx->fPState);
472
473 /** @todo */
474}
475
476
477/**
478 * Display all cpu states and any other cpum info.
479 *
480 * @param pVM The cross context VM structure.
481 * @param pHlp The info helper functions.
482 * @param pszArgs Arguments, ignored.
483 */
484static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
485{
486 cpumR3InfoGuest(pVM, pHlp, pszArgs);
487 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
488}
489
490
491/**
492 * Parses the info argument.
493 *
494 * The argument starts with 'verbose', 'terse' or 'default' and then
495 * continues with the comment string.
496 *
497 * @param pszArgs The pointer to the argument string.
498 * @param penmType Where to store the dump type request.
499 * @param ppszComment Where to store the pointer to the comment string.
500 */
501static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
502{
503 if (!pszArgs)
504 {
505 *penmType = CPUMDUMPTYPE_DEFAULT;
506 *ppszComment = "";
507 }
508 else
509 {
510 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
511 {
512 pszArgs += 7;
513 *penmType = CPUMDUMPTYPE_VERBOSE;
514 }
515 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
516 {
517 pszArgs += 5;
518 *penmType = CPUMDUMPTYPE_TERSE;
519 }
520 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
521 {
522 pszArgs += 7;
523 *penmType = CPUMDUMPTYPE_DEFAULT;
524 }
525 else
526 *penmType = CPUMDUMPTYPE_DEFAULT;
527 *ppszComment = RTStrStripL(pszArgs);
528 }
529}
530
531
532/**
533 * Display the guest cpu state.
534 *
535 * @param pVM The cross context VM structure.
536 * @param pHlp The info helper functions.
537 * @param pszArgs Arguments.
538 */
539static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
540{
541 CPUMDUMPTYPE enmType;
542 const char *pszComment;
543 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
544
545 PVMCPU pVCpu = VMMGetCpu(pVM);
546 if (!pVCpu)
547 pVCpu = pVM->apCpusR3[0];
548
549 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
550
551 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
552 cpumR3InfoOne(pVM, pCtx, pHlp, enmType, "");
553}
554
555
556/**
557 * Display the current guest instruction
558 *
559 * @param pVM The cross context VM structure.
560 * @param pHlp The info helper functions.
561 * @param pszArgs Arguments, ignored.
562 */
563static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
564{
565 NOREF(pszArgs);
566
567 PVMCPU pVCpu = VMMGetCpu(pVM);
568 if (!pVCpu)
569 pVCpu = pVM->apCpusR3[0];
570
571 char szInstruction[256];
572 szInstruction[0] = '\0';
573 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
574 pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
575}
576
577
578/**
579 * Called when the ring-3 init phase completes.
580 *
581 * @returns VBox status code.
582 * @param pVM The cross context VM structure.
583 * @param enmWhat Which init phase.
584 */
585VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
586{
587 RT_NOREF(pVM, enmWhat);
588 return VINF_SUCCESS;
589}
590
591
592/**
593 * Called when the ring-0 init phases completed.
594 *
595 * @param pVM The cross context VM structure.
596 */
597VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
598{
599 /*
600 * Enable log buffering as we're going to log a lot of lines.
601 */
602 bool const fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
603
604 /*
605 * Log the cpuid.
606 */
607 RTCPUSET OnlineSet;
608 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
609 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
610 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
611 RTCPUID cCores = RTMpGetCoreCount();
612 if (cCores)
613 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
614 RT_NOREF(pVM);
615#if 0 /** @todo Someting similar. */
616 LogRel(("************************* CPUID dump ************************\n"));
617 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
618 LogRel(("\n"));
619 DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
620 LogRel(("******************** End of CPUID dump **********************\n"));
621#endif
622
623 /*
624 * Restore the log buffering state to what it was previously.
625 */
626 RTLogRelSetBuffering(fOldBuffered);
627}
628
629
630/**
631 * Marks the guest debug state as active.
632 *
633 * @param pVCpu The cross context virtual CPU structure.
634 *
635 * @note This is used solely by NEM (hence the name) to set the correct flags here
636 * without loading the host's DRx registers, which is not possible from ring-3 anyway.
637 * The specific NEM backends have to make sure to load the correct values.
638 */
639VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
640{
641 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
642 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
643}
644
645
646/**
647 * Marks the hyper debug state as active.
648 *
649 * @param pVCpu The cross context virtual CPU structure.
650 *
651 * @note This is used solely by NEM (hence the name) to set the correct flags here
652 * without loading the host's debug registers, which is not possible from ring-3 anyway.
653 * The specific NEM backends have to make sure to load the correct values.
654 */
655VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
656{
657 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
658 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
659}
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