CPUM-armv8.cpp@ 108843

Last change on this file since 108843 was 108758, checked in by vboxsync, 6 weeks ago
VMM/Arm: Add ACTLR_EL1 to the CPU state, bugref:10392
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1	/* $Id: CPUM-armv8.cpp 108758 2025-03-26 16:05:20Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager (ARMv8 variant).
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_cpum CPUM - CPU Monitor / Manager
29	*
30	* The CPU Monitor / Manager keeps track of all the CPU registers.
31	* This is the ARMv8 variant which is doing much less than its x86/AMD6464
32	* counterpart due to the fact that we currently only support the NEM backends
33	* for running ARM guests. It might become complex iff we decide to implement our
34	* own hypervisor.
35	*
36	* @section sec_cpum_logging_armv8 Logging Level Assignments.
37	*
38	* Following log level assignments:
39	* - @todo
40	*
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_CPUM
48	#define CPUM_WITH_NONCONST_HOST_FEATURES
49	#include <VBox/vmm/cpum.h>
50	#include <VBox/vmm/cpumdis.h>
51	#include <VBox/vmm/pgm.h>
52	#include <VBox/vmm/mm.h>
53	#include <VBox/vmm/em.h>
54	#include <VBox/vmm/iem.h>
55	#include <VBox/vmm/dbgf.h>
56	#include <VBox/vmm/ssm.h>
57	#include "CPUMInternal-armv8.h"
58	#include <VBox/vmm/vm.h>
59
60	#include <VBox/param.h>
61	#include <VBox/dis.h>
62	#include <VBox/err.h>
63	#include <VBox/log.h>
64	#include <iprt/assert.h>
65	#include <iprt/cpuset.h>
66	#include <iprt/mem.h>
67	#include <iprt/mp.h>
68	#include <iprt/string.h>
69	#include <iprt/armv8.h>
70
71
72	/*********************************************************************************************************************************
73	* Defined Constants And Macros *
74	*********************************************************************************************************************************/
75
76	/** Internal form used by the macros. */
77	#ifdef VBOX_WITH_STATISTICS
78	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
79	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
80	{ 0 }, { 0 }, { 0 }, { 0 } }
81	#else
82	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
83	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
84	#endif
85
86	/** Function handlers, extended version. */
87	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
88	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
89	/** Function handlers, read-only. */
90	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
91	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
92	/** Read-only fixed value, ignores all writes. */
93	#define MVI(a_uMsr, a_szName, a_uValue) \
94	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_FixedValue, kCpumSysRegWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
95	/** Read/Write value from/to CPUMCTX. */
96	#define MVRW(a_uMsr, a_szName, a_offCpum) \
97	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_ReadCpumOff, kCpumSysRegWrFn_WriteCpumOff, (uint32_t)a_offCpum, 0, UINT64_MAX, 0, a_szName)
98
99
100	/*********************************************************************************************************************************
101	* Structures and Typedefs *
102	*********************************************************************************************************************************/
103
104	/**
105	* What kind of cpu info dump to perform.
106	*/
107	typedef enum CPUMDUMPTYPE
108	{
109	CPUMDUMPTYPE_TERSE,
110	CPUMDUMPTYPE_DEFAULT,
111	CPUMDUMPTYPE_VERBOSE
112	} CPUMDUMPTYPE;
113	/** Pointer to a cpu info dump type. */
114	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
115
116
117	/*********************************************************************************************************************************
118	* Internal Functions *
119	*********************************************************************************************************************************/
120	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
121	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
122	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
123	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
124	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
125	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128
129
130	/*********************************************************************************************************************************
131	* Global Variables *
132	*********************************************************************************************************************************/
133	#if defined(RT_ARCH_ARM64)
134	/** Host CPU features. */
135	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
136	#endif
137
138	/**
139	* System register ranges.
140	*/
141	static CPUMSYSREGRANGE const g_aSysRegRanges[] =
142	{
143	MFX(ARMV8_AARCH64_SYSREG_OSLAR_EL1, "OSLAR_EL1", WriteOnly, OslarEl1, 0, UINT64_C(0xfffffffffffffffe), UINT64_C(0xfffffffffffffffe)),
144	MFO(ARMV8_AARCH64_SYSREG_OSLSR_EL1, "OSLSR_EL1", OslsrEl1),
145	MVI(ARMV8_AARCH64_SYSREG_OSDLR_EL1, "OSDLR_EL1", 0),
146	MVRW(ARMV8_AARCH64_SYSREG_MDSCR_EL1, "MDSCR_EL1", RT_UOFFSETOF(CPUMCTX, Mdscr)),
147	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(0), "DBGBVR0_EL1", RT_UOFFSETOF(CPUMCTX, aBp[0].Value)),
148	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(1), "DBGBVR1_EL1", RT_UOFFSETOF(CPUMCTX, aBp[1].Value)),
149	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(2), "DBGBVR2_EL1", RT_UOFFSETOF(CPUMCTX, aBp[2].Value)),
150	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(3), "DBGBVR3_EL1", RT_UOFFSETOF(CPUMCTX, aBp[3].Value)),
151	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(4), "DBGBVR4_EL1", RT_UOFFSETOF(CPUMCTX, aBp[4].Value)),
152	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(5), "DBGBVR5_EL1", RT_UOFFSETOF(CPUMCTX, aBp[5].Value)),
153	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(6), "DBGBVR6_EL1", RT_UOFFSETOF(CPUMCTX, aBp[6].Value)),
154	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(7), "DBGBVR7_EL1", RT_UOFFSETOF(CPUMCTX, aBp[7].Value)),
155	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(8), "DBGBVR8_EL1", RT_UOFFSETOF(CPUMCTX, aBp[8].Value)),
156	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(9), "DBGBVR9_EL9", RT_UOFFSETOF(CPUMCTX, aBp[9].Value)),
157	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(10), "DBGBVR10_EL1", RT_UOFFSETOF(CPUMCTX, aBp[10].Value)),
158	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(11), "DBGBVR11_EL1", RT_UOFFSETOF(CPUMCTX, aBp[11].Value)),
159	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(12), "DBGBVR12_EL1", RT_UOFFSETOF(CPUMCTX, aBp[12].Value)),
160	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(13), "DBGBVR13_EL1", RT_UOFFSETOF(CPUMCTX, aBp[13].Value)),
161	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(14), "DBGBVR14_EL1", RT_UOFFSETOF(CPUMCTX, aBp[14].Value)),
162	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(15), "DBGBVR15_EL1", RT_UOFFSETOF(CPUMCTX, aBp[15].Value)),
163	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(0), "DBGBCR0_EL1", RT_UOFFSETOF(CPUMCTX, aBp[0].Ctrl)),
164	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(1), "DBGBCR1_EL1", RT_UOFFSETOF(CPUMCTX, aBp[1].Ctrl)),
165	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(2), "DBGBCR2_EL1", RT_UOFFSETOF(CPUMCTX, aBp[2].Ctrl)),
166	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(3), "DBGBCR3_EL1", RT_UOFFSETOF(CPUMCTX, aBp[3].Ctrl)),
167	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(4), "DBGBCR4_EL1", RT_UOFFSETOF(CPUMCTX, aBp[4].Ctrl)),
168	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(5), "DBGBCR5_EL1", RT_UOFFSETOF(CPUMCTX, aBp[5].Ctrl)),
169	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(6), "DBGBCR6_EL1", RT_UOFFSETOF(CPUMCTX, aBp[6].Ctrl)),
170	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(7), "DBGBCR7_EL1", RT_UOFFSETOF(CPUMCTX, aBp[7].Ctrl)),
171	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(8), "DBGBCR8_EL1", RT_UOFFSETOF(CPUMCTX, aBp[8].Ctrl)),
172	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(9), "DBGBCR9_EL9", RT_UOFFSETOF(CPUMCTX, aBp[9].Ctrl)),
173	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(10), "DBGBCR10_EL1", RT_UOFFSETOF(CPUMCTX, aBp[10].Ctrl)),
174	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(11), "DBGBCR11_EL1", RT_UOFFSETOF(CPUMCTX, aBp[11].Ctrl)),
175	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(12), "DBGBCR12_EL1", RT_UOFFSETOF(CPUMCTX, aBp[12].Ctrl)),
176	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(13), "DBGBCR13_EL1", RT_UOFFSETOF(CPUMCTX, aBp[13].Ctrl)),
177	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(14), "DBGBCR14_EL1", RT_UOFFSETOF(CPUMCTX, aBp[14].Ctrl)),
178	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(15), "DBGBCR15_EL1", RT_UOFFSETOF(CPUMCTX, aBp[15].Ctrl)),
179	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(0), "DBGWVR0_EL1", RT_UOFFSETOF(CPUMCTX, aWp[0].Value)),
180	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(1), "DBGWVR1_EL1", RT_UOFFSETOF(CPUMCTX, aWp[1].Value)),
181	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(2), "DBGWVR2_EL1", RT_UOFFSETOF(CPUMCTX, aWp[2].Value)),
182	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(3), "DBGWVR3_EL1", RT_UOFFSETOF(CPUMCTX, aWp[3].Value)),
183	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(4), "DBGWVR4_EL1", RT_UOFFSETOF(CPUMCTX, aWp[4].Value)),
184	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(5), "DBGWVR5_EL1", RT_UOFFSETOF(CPUMCTX, aWp[5].Value)),
185	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(6), "DBGWVR6_EL1", RT_UOFFSETOF(CPUMCTX, aWp[6].Value)),
186	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(7), "DBGWVR7_EL1", RT_UOFFSETOF(CPUMCTX, aWp[7].Value)),
187	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(8), "DBGWVR8_EL1", RT_UOFFSETOF(CPUMCTX, aWp[8].Value)),
188	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(9), "DBGWVR9_EL9", RT_UOFFSETOF(CPUMCTX, aWp[9].Value)),
189	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(10), "DBGWVR10_EL1", RT_UOFFSETOF(CPUMCTX, aWp[10].Value)),
190	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(11), "DBGWVR11_EL1", RT_UOFFSETOF(CPUMCTX, aWp[11].Value)),
191	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(12), "DBGWVR12_EL1", RT_UOFFSETOF(CPUMCTX, aWp[12].Value)),
192	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(13), "DBGWVR13_EL1", RT_UOFFSETOF(CPUMCTX, aWp[13].Value)),
193	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(14), "DBGWVR14_EL1", RT_UOFFSETOF(CPUMCTX, aWp[14].Value)),
194	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(15), "DBGWVR15_EL1", RT_UOFFSETOF(CPUMCTX, aWp[15].Value)),
195	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(0), "DBGWCR0_EL1", RT_UOFFSETOF(CPUMCTX, aWp[0].Ctrl)),
196	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(1), "DBGWCR1_EL1", RT_UOFFSETOF(CPUMCTX, aWp[1].Ctrl)),
197	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(2), "DBGWCR2_EL1", RT_UOFFSETOF(CPUMCTX, aWp[2].Ctrl)),
198	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(3), "DBGWCR3_EL1", RT_UOFFSETOF(CPUMCTX, aWp[3].Ctrl)),
199	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(4), "DBGWCR4_EL1", RT_UOFFSETOF(CPUMCTX, aWp[4].Ctrl)),
200	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(5), "DBGWCR5_EL1", RT_UOFFSETOF(CPUMCTX, aWp[5].Ctrl)),
201	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(6), "DBGWCR6_EL1", RT_UOFFSETOF(CPUMCTX, aWp[6].Ctrl)),
202	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(7), "DBGWCR7_EL1", RT_UOFFSETOF(CPUMCTX, aWp[7].Ctrl)),
203	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(8), "DBGWCR8_EL1", RT_UOFFSETOF(CPUMCTX, aWp[8].Ctrl)),
204	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(9), "DBGWCR9_EL9", RT_UOFFSETOF(CPUMCTX, aWp[9].Ctrl)),
205	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(10), "DBGWCR10_EL1", RT_UOFFSETOF(CPUMCTX, aWp[10].Ctrl)),
206	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(11), "DBGWCR11_EL1", RT_UOFFSETOF(CPUMCTX, aWp[11].Ctrl)),
207	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(12), "DBGWCR12_EL1", RT_UOFFSETOF(CPUMCTX, aWp[12].Ctrl)),
208	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(13), "DBGWCR13_EL1", RT_UOFFSETOF(CPUMCTX, aWp[13].Ctrl)),
209	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(14), "DBGWCR14_EL1", RT_UOFFSETOF(CPUMCTX, aWp[14].Ctrl)),
210	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(15), "DBGWCR15_EL1", RT_UOFFSETOF(CPUMCTX, aWp[15].Ctrl)),
211	};
212
213
214	/** Saved state field descriptors for CPUMCTX. */
215	static const SSMFIELD g_aCpumCtxFields[] =
216	{
217	SSMFIELD_ENTRY( CPUMCTX, aGRegs[0].x),
218	SSMFIELD_ENTRY( CPUMCTX, aGRegs[1].x),
219	SSMFIELD_ENTRY( CPUMCTX, aGRegs[2].x),
220	SSMFIELD_ENTRY( CPUMCTX, aGRegs[3].x),
221	SSMFIELD_ENTRY( CPUMCTX, aGRegs[4].x),
222	SSMFIELD_ENTRY( CPUMCTX, aGRegs[5].x),
223	SSMFIELD_ENTRY( CPUMCTX, aGRegs[6].x),
224	SSMFIELD_ENTRY( CPUMCTX, aGRegs[7].x),
225	SSMFIELD_ENTRY( CPUMCTX, aGRegs[8].x),
226	SSMFIELD_ENTRY( CPUMCTX, aGRegs[9].x),
227	SSMFIELD_ENTRY( CPUMCTX, aGRegs[10].x),
228	SSMFIELD_ENTRY( CPUMCTX, aGRegs[11].x),
229	SSMFIELD_ENTRY( CPUMCTX, aGRegs[12].x),
230	SSMFIELD_ENTRY( CPUMCTX, aGRegs[13].x),
231	SSMFIELD_ENTRY( CPUMCTX, aGRegs[14].x),
232	SSMFIELD_ENTRY( CPUMCTX, aGRegs[15].x),
233	SSMFIELD_ENTRY( CPUMCTX, aGRegs[16].x),
234	SSMFIELD_ENTRY( CPUMCTX, aGRegs[17].x),
235	SSMFIELD_ENTRY( CPUMCTX, aGRegs[18].x),
236	SSMFIELD_ENTRY( CPUMCTX, aGRegs[19].x),
237	SSMFIELD_ENTRY( CPUMCTX, aGRegs[20].x),
238	SSMFIELD_ENTRY( CPUMCTX, aGRegs[21].x),
239	SSMFIELD_ENTRY( CPUMCTX, aGRegs[22].x),
240	SSMFIELD_ENTRY( CPUMCTX, aGRegs[23].x),
241	SSMFIELD_ENTRY( CPUMCTX, aGRegs[24].x),
242	SSMFIELD_ENTRY( CPUMCTX, aGRegs[25].x),
243	SSMFIELD_ENTRY( CPUMCTX, aGRegs[26].x),
244	SSMFIELD_ENTRY( CPUMCTX, aGRegs[27].x),
245	SSMFIELD_ENTRY( CPUMCTX, aGRegs[28].x),
246	SSMFIELD_ENTRY( CPUMCTX, aGRegs[29].x),
247	SSMFIELD_ENTRY( CPUMCTX, aGRegs[30].x),
248	SSMFIELD_ENTRY( CPUMCTX, aVRegs[0].v),
249	SSMFIELD_ENTRY( CPUMCTX, aVRegs[1].v),
250	SSMFIELD_ENTRY( CPUMCTX, aVRegs[2].v),
251	SSMFIELD_ENTRY( CPUMCTX, aVRegs[3].v),
252	SSMFIELD_ENTRY( CPUMCTX, aVRegs[4].v),
253	SSMFIELD_ENTRY( CPUMCTX, aVRegs[5].v),
254	SSMFIELD_ENTRY( CPUMCTX, aVRegs[6].v),
255	SSMFIELD_ENTRY( CPUMCTX, aVRegs[7].v),
256	SSMFIELD_ENTRY( CPUMCTX, aVRegs[8].v),
257	SSMFIELD_ENTRY( CPUMCTX, aVRegs[9].v),
258	SSMFIELD_ENTRY( CPUMCTX, aVRegs[10].v),
259	SSMFIELD_ENTRY( CPUMCTX, aVRegs[11].v),
260	SSMFIELD_ENTRY( CPUMCTX, aVRegs[12].v),
261	SSMFIELD_ENTRY( CPUMCTX, aVRegs[13].v),
262	SSMFIELD_ENTRY( CPUMCTX, aVRegs[14].v),
263	SSMFIELD_ENTRY( CPUMCTX, aVRegs[15].v),
264	SSMFIELD_ENTRY( CPUMCTX, aVRegs[16].v),
265	SSMFIELD_ENTRY( CPUMCTX, aVRegs[17].v),
266	SSMFIELD_ENTRY( CPUMCTX, aVRegs[18].v),
267	SSMFIELD_ENTRY( CPUMCTX, aVRegs[19].v),
268	SSMFIELD_ENTRY( CPUMCTX, aVRegs[20].v),
269	SSMFIELD_ENTRY( CPUMCTX, aVRegs[21].v),
270	SSMFIELD_ENTRY( CPUMCTX, aVRegs[22].v),
271	SSMFIELD_ENTRY( CPUMCTX, aVRegs[23].v),
272	SSMFIELD_ENTRY( CPUMCTX, aVRegs[24].v),
273	SSMFIELD_ENTRY( CPUMCTX, aVRegs[25].v),
274	SSMFIELD_ENTRY( CPUMCTX, aVRegs[26].v),
275	SSMFIELD_ENTRY( CPUMCTX, aVRegs[27].v),
276	SSMFIELD_ENTRY( CPUMCTX, aVRegs[28].v),
277	SSMFIELD_ENTRY( CPUMCTX, aVRegs[29].v),
278	SSMFIELD_ENTRY( CPUMCTX, aVRegs[30].v),
279	SSMFIELD_ENTRY( CPUMCTX, aVRegs[31].v),
280	SSMFIELD_ENTRY( CPUMCTX, aSpReg[0].u64),
281	SSMFIELD_ENTRY( CPUMCTX, aSpReg[1].u64),
282	SSMFIELD_ENTRY( CPUMCTX, Pc.u64),
283	SSMFIELD_ENTRY( CPUMCTX, Spsr.u64),
284	SSMFIELD_ENTRY( CPUMCTX, Elr.u64),
285	SSMFIELD_ENTRY( CPUMCTX, Sctlr.u64),
286	SSMFIELD_ENTRY( CPUMCTX, Tcr.u64),
287	SSMFIELD_ENTRY( CPUMCTX, Ttbr0.u64),
288	SSMFIELD_ENTRY( CPUMCTX, Ttbr1.u64),
289	SSMFIELD_ENTRY( CPUMCTX, VBar.u64),
290	SSMFIELD_ENTRY( CPUMCTX, aBp[0].Ctrl.u64),
291	SSMFIELD_ENTRY( CPUMCTX, aBp[0].Value.u64),
292	SSMFIELD_ENTRY( CPUMCTX, aBp[1].Ctrl.u64),
293	SSMFIELD_ENTRY( CPUMCTX, aBp[1].Value.u64),
294	SSMFIELD_ENTRY( CPUMCTX, aBp[2].Ctrl.u64),
295	SSMFIELD_ENTRY( CPUMCTX, aBp[2].Value.u64),
296	SSMFIELD_ENTRY( CPUMCTX, aBp[3].Ctrl.u64),
297	SSMFIELD_ENTRY( CPUMCTX, aBp[3].Value.u64),
298	SSMFIELD_ENTRY( CPUMCTX, aBp[4].Ctrl.u64),
299	SSMFIELD_ENTRY( CPUMCTX, aBp[4].Value.u64),
300	SSMFIELD_ENTRY( CPUMCTX, aBp[5].Ctrl.u64),
301	SSMFIELD_ENTRY( CPUMCTX, aBp[5].Value.u64),
302	SSMFIELD_ENTRY( CPUMCTX, aBp[6].Ctrl.u64),
303	SSMFIELD_ENTRY( CPUMCTX, aBp[6].Value.u64),
304	SSMFIELD_ENTRY( CPUMCTX, aBp[7].Ctrl.u64),
305	SSMFIELD_ENTRY( CPUMCTX, aBp[7].Value.u64),
306	SSMFIELD_ENTRY( CPUMCTX, aBp[8].Ctrl.u64),
307	SSMFIELD_ENTRY( CPUMCTX, aBp[8].Value.u64),
308	SSMFIELD_ENTRY( CPUMCTX, aBp[9].Ctrl.u64),
309	SSMFIELD_ENTRY( CPUMCTX, aBp[9].Value.u64),
310	SSMFIELD_ENTRY( CPUMCTX, aBp[10].Ctrl.u64),
311	SSMFIELD_ENTRY( CPUMCTX, aBp[10].Value.u64),
312	SSMFIELD_ENTRY( CPUMCTX, aBp[11].Ctrl.u64),
313	SSMFIELD_ENTRY( CPUMCTX, aBp[11].Value.u64),
314	SSMFIELD_ENTRY( CPUMCTX, aBp[12].Ctrl.u64),
315	SSMFIELD_ENTRY( CPUMCTX, aBp[12].Value.u64),
316	SSMFIELD_ENTRY( CPUMCTX, aBp[13].Ctrl.u64),
317	SSMFIELD_ENTRY( CPUMCTX, aBp[13].Value.u64),
318	SSMFIELD_ENTRY( CPUMCTX, aBp[14].Ctrl.u64),
319	SSMFIELD_ENTRY( CPUMCTX, aBp[14].Value.u64),
320	SSMFIELD_ENTRY( CPUMCTX, aBp[15].Ctrl.u64),
321	SSMFIELD_ENTRY( CPUMCTX, aBp[15].Value.u64),
322	SSMFIELD_ENTRY( CPUMCTX, aWp[0].Ctrl.u64),
323	SSMFIELD_ENTRY( CPUMCTX, aWp[0].Value.u64),
324	SSMFIELD_ENTRY( CPUMCTX, aWp[1].Ctrl.u64),
325	SSMFIELD_ENTRY( CPUMCTX, aWp[1].Value.u64),
326	SSMFIELD_ENTRY( CPUMCTX, aWp[2].Ctrl.u64),
327	SSMFIELD_ENTRY( CPUMCTX, aWp[2].Value.u64),
328	SSMFIELD_ENTRY( CPUMCTX, aWp[3].Ctrl.u64),
329	SSMFIELD_ENTRY( CPUMCTX, aWp[3].Value.u64),
330	SSMFIELD_ENTRY( CPUMCTX, aWp[4].Ctrl.u64),
331	SSMFIELD_ENTRY( CPUMCTX, aWp[4].Value.u64),
332	SSMFIELD_ENTRY( CPUMCTX, aWp[5].Ctrl.u64),
333	SSMFIELD_ENTRY( CPUMCTX, aWp[5].Value.u64),
334	SSMFIELD_ENTRY( CPUMCTX, aWp[6].Ctrl.u64),
335	SSMFIELD_ENTRY( CPUMCTX, aWp[6].Value.u64),
336	SSMFIELD_ENTRY( CPUMCTX, aWp[7].Ctrl.u64),
337	SSMFIELD_ENTRY( CPUMCTX, aWp[7].Value.u64),
338	SSMFIELD_ENTRY( CPUMCTX, aWp[8].Ctrl.u64),
339	SSMFIELD_ENTRY( CPUMCTX, aWp[8].Value.u64),
340	SSMFIELD_ENTRY( CPUMCTX, aWp[9].Ctrl.u64),
341	SSMFIELD_ENTRY( CPUMCTX, aWp[9].Value.u64),
342	SSMFIELD_ENTRY( CPUMCTX, aWp[10].Ctrl.u64),
343	SSMFIELD_ENTRY( CPUMCTX, aWp[10].Value.u64),
344	SSMFIELD_ENTRY( CPUMCTX, aWp[11].Ctrl.u64),
345	SSMFIELD_ENTRY( CPUMCTX, aWp[11].Value.u64),
346	SSMFIELD_ENTRY( CPUMCTX, aWp[12].Ctrl.u64),
347	SSMFIELD_ENTRY( CPUMCTX, aWp[12].Value.u64),
348	SSMFIELD_ENTRY( CPUMCTX, aWp[13].Ctrl.u64),
349	SSMFIELD_ENTRY( CPUMCTX, aWp[13].Value.u64),
350	SSMFIELD_ENTRY( CPUMCTX, aWp[14].Ctrl.u64),
351	SSMFIELD_ENTRY( CPUMCTX, aWp[14].Value.u64),
352	SSMFIELD_ENTRY( CPUMCTX, aWp[15].Ctrl.u64),
353	SSMFIELD_ENTRY( CPUMCTX, aWp[15].Value.u64),
354	SSMFIELD_ENTRY( CPUMCTX, Mdscr.u64),
355	SSMFIELD_ENTRY( CPUMCTX, Apda.Low.u64),
356	SSMFIELD_ENTRY( CPUMCTX, Apda.High.u64),
357	SSMFIELD_ENTRY( CPUMCTX, Apdb.Low.u64),
358	SSMFIELD_ENTRY( CPUMCTX, Apdb.High.u64),
359	SSMFIELD_ENTRY( CPUMCTX, Apga.Low.u64),
360	SSMFIELD_ENTRY( CPUMCTX, Apga.High.u64),
361	SSMFIELD_ENTRY( CPUMCTX, Apia.Low.u64),
362	SSMFIELD_ENTRY( CPUMCTX, Apia.High.u64),
363	SSMFIELD_ENTRY( CPUMCTX, Apib.Low.u64),
364	SSMFIELD_ENTRY( CPUMCTX, Apib.High.u64),
365	SSMFIELD_ENTRY( CPUMCTX, Afsr0.u64),
366	SSMFIELD_ENTRY( CPUMCTX, Afsr1.u64),
367	SSMFIELD_ENTRY( CPUMCTX, Amair.u64),
368	SSMFIELD_ENTRY( CPUMCTX, CntKCtl.u64),
369	SSMFIELD_ENTRY( CPUMCTX, ContextIdr.u64),
370	SSMFIELD_ENTRY( CPUMCTX, Cpacr.u64),
371	SSMFIELD_ENTRY( CPUMCTX, Csselr.u64),
372	SSMFIELD_ENTRY( CPUMCTX, Esr.u64),
373	SSMFIELD_ENTRY( CPUMCTX, Far.u64),
374	SSMFIELD_ENTRY( CPUMCTX, Mair.u64),
375	SSMFIELD_ENTRY( CPUMCTX, Par.u64),
376	SSMFIELD_ENTRY( CPUMCTX, TpIdrRoEl0.u64),
377	SSMFIELD_ENTRY( CPUMCTX, aTpIdr[0].u64),
378	SSMFIELD_ENTRY( CPUMCTX, aTpIdr[1].u64),
379	SSMFIELD_ENTRY( CPUMCTX, MDccInt.u64),
380	SSMFIELD_ENTRY( CPUMCTX, fpcr),
381	SSMFIELD_ENTRY( CPUMCTX, fpsr),
382	SSMFIELD_ENTRY( CPUMCTX, fPState),
383	SSMFIELD_ENTRY( CPUMCTX, fOsLck),
384	SSMFIELD_ENTRY( CPUMCTX, CntvCtlEl0),
385	SSMFIELD_ENTRY( CPUMCTX, CntvCValEl0),
386	/** @name EL2 support:
387	* @{ */
388	SSMFIELD_ENTRY( CPUMCTX, CntHCtlEl2),
389	SSMFIELD_ENTRY( CPUMCTX, CntHpCtlEl2),
390	SSMFIELD_ENTRY( CPUMCTX, CntHpCValEl2),
391	SSMFIELD_ENTRY( CPUMCTX, CntHpTValEl2),
392	SSMFIELD_ENTRY( CPUMCTX, CntVOffEl2),
393	SSMFIELD_ENTRY( CPUMCTX, CptrEl2),
394	SSMFIELD_ENTRY( CPUMCTX, ElrEl2),
395	SSMFIELD_ENTRY( CPUMCTX, EsrEl2),
396	SSMFIELD_ENTRY( CPUMCTX, FarEl2),
397	SSMFIELD_ENTRY( CPUMCTX, HcrEl2),
398	SSMFIELD_ENTRY( CPUMCTX, HpFarEl2),
399	SSMFIELD_ENTRY( CPUMCTX, MairEl2),
400	SSMFIELD_ENTRY( CPUMCTX, MdcrEl2),
401	SSMFIELD_ENTRY( CPUMCTX, SctlrEl2),
402	SSMFIELD_ENTRY( CPUMCTX, SpsrEl2),
403	SSMFIELD_ENTRY( CPUMCTX, SpEl2),
404	SSMFIELD_ENTRY( CPUMCTX, TcrEl2),
405	SSMFIELD_ENTRY( CPUMCTX, TpidrEl2),
406	SSMFIELD_ENTRY( CPUMCTX, Ttbr0El2),
407	SSMFIELD_ENTRY( CPUMCTX, Ttbr1El2),
408	SSMFIELD_ENTRY( CPUMCTX, VBarEl2),
409	SSMFIELD_ENTRY( CPUMCTX, VMpidrEl2),
410	SSMFIELD_ENTRY( CPUMCTX, VPidrEl2),
411	SSMFIELD_ENTRY( CPUMCTX, VTcrEl2),
412	SSMFIELD_ENTRY( CPUMCTX, VTtbrEl2),
413	/** @} */
414
415	SSMFIELD_ENTRY_TERM()
416	};
417
418	/**
419	* Additional fields for v2
420	*/
421	static const SSMFIELD g_aCpumCtxFieldsV2[] =
422	{
423	SSMFIELD_ENTRY( CPUMCTX, Actlr.u64),
424	SSMFIELD_ENTRY_TERM()
425	};
426
427
428	/**
429	* Initializes the guest system register states.
430	*
431	* @returns VBox status code.
432	* @param pVM The cross context VM structure.
433	*/
434	static int cpumR3InitSysRegs(PVM pVM)
435	{
436	for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges); i++)
437	{
438	int rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges[i]);
439	AssertLogRelRCReturn(rc, rc);
440	}
441
442	return VINF_SUCCESS;
443	}
444
445
446	/**
447	* Initializes the CPUM.
448	*
449	* @returns VBox status code.
450	* @param pVM The cross context VM structure.
451	*/
452	VMMR3DECL(int) CPUMR3Init(PVM pVM)
453	{
454	LogFlow(("CPUMR3Init\n"));
455
456	/*
457	* Assert alignment, sizes and tables.
458	*/
459	AssertCompileMemberAlignment(VM, cpum.s, 32);
460	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
461	AssertCompileSizeAlignment(CPUMCTX, 64);
462	AssertCompileMemberAlignment(VM, cpum, 64);
463	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
464	#ifdef VBOX_STRICT
465	int rc2 = cpumR3SysRegStrictInitChecks();
466	AssertRCReturn(rc2, rc2);
467	#endif
468
469	pVM->cpum.s.GuestInfo.paSysRegRangesR3 = &pVM->cpum.s.GuestInfo.aSysRegRanges[0];
470	pVM->cpum.s.bResetEl = ARMV8_AARCH64_EL_1;
471
472	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
473
474	/** @cfgm{/CPUM/ResetPcValue, string}
475	* Program counter value after a reset, sets the address of the first instruction to execute. */
476	int rc = CFGMR3QueryU64Def(pCpumCfg, "ResetPcValue", &pVM->cpum.s.u64ResetPc, 0);
477	AssertLogRelRCReturn(rc, rc);
478
479	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
480	* Whether to expose the hardware virtualization (EL2) feature to the guest.
481	* The default is false, and when enabled requires a 64-bit CPU and a NEM backend
482	* supporting it.
483	*/
484	bool fNestedHWVirt = false;
485	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &fNestedHWVirt, false);
486	AssertLogRelRCReturn(rc, rc);
487	if (fNestedHWVirt)
488	pVM->cpum.s.bResetEl = ARMV8_AARCH64_EL_2;
489
490	/*
491	* Register saved state data item.
492	*/
493	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
494	NULL, cpumR3LiveExec, NULL,
495	NULL, cpumR3SaveExec, NULL,
496	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
497	if (RT_FAILURE(rc))
498	return rc;
499
500	/*
501	* Register info handlers and registers with the debugger facility.
502	*/
503	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
504	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
505	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
506	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
507	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
508	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
509	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid information.",
510	&cpumR3CpuIdInfo);
511	DBGFR3InfoRegisterInternal( pVM, "cpufeat", "Displays the guest features.",
512	&cpumR3CpuFeatInfo);
513
514	rc = cpumR3DbgInit(pVM);
515	if (RT_FAILURE(rc))
516	return rc;
517
518	/*
519	* Initialize the Guest system register states.
520	*/
521	rc = cpumR3InitSysRegs(pVM);
522	if (RT_FAILURE(rc))
523	return rc;
524
525	/*
526	* Initialize the general guest CPU state.
527	*/
528	CPUMR3Reset(pVM);
529
530	return VINF_SUCCESS;
531	}
532
533
534	/**
535	* Applies relocations to data and code managed by this
536	* component. This function will be called at init and
537	* whenever the VMM need to relocate it self inside the GC.
538	*
539	* The CPUM will update the addresses used by the switcher.
540	*
541	* @param pVM The cross context VM structure.
542	*/
543	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
544	{
545	RT_NOREF(pVM);
546	}
547
548
549	/**
550	* Terminates the CPUM.
551	*
552	* Termination means cleaning up and freeing all resources,
553	* the VM it self is at this point powered off or suspended.
554	*
555	* @returns VBox status code.
556	* @param pVM The cross context VM structure.
557	*/
558	VMMR3DECL(int) CPUMR3Term(PVM pVM)
559	{
560	RT_NOREF(pVM);
561	return VINF_SUCCESS;
562	}
563
564
565	/**
566	* Resets a virtual CPU.
567	*
568	* Used by CPUMR3Reset and CPU hot plugging.
569	*
570	* @param pVM The cross context VM structure.
571	* @param pVCpu The cross context virtual CPU structure of the CPU that is
572	* being reset. This may differ from the current EMT.
573	*/
574	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
575	{
576	RT_NOREF(pVM);
577
578	/** @todo anything different for VCPU > 0? */
579	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
580
581	/*
582	* Initialize everything to ZERO first.
583	*/
584	RT_BZERO(pCtx, sizeof(*pCtx));
585
586	/* Start in Supervisor mode. */
587	/** @todo Differentiate between Aarch64 and Aarch32 configuation. */
588	pCtx->fPState = ARMV8_SPSR_EL2_AARCH64_SET_EL(pVM->cpum.s.bResetEl)
589	\| ARMV8_SPSR_EL2_AARCH64_SP
590	\| ARMV8_SPSR_EL2_AARCH64_D
591	\| ARMV8_SPSR_EL2_AARCH64_A
592	\| ARMV8_SPSR_EL2_AARCH64_I
593	\| ARMV8_SPSR_EL2_AARCH64_F;
594
595	pCtx->Pc.u64 = pVM->cpum.s.u64ResetPc;
596	/** @todo */
597	}
598
599
600	/**
601	* Resets the CPU.
602	*
603	* @param pVM The cross context VM structure.
604	*/
605	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
606	{
607	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
608	{
609	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
610	CPUMR3ResetCpu(pVM, pVCpu);
611	}
612	}
613
614
615
616
617	/**
618	* Pass 0 live exec callback.
619	*
620	* @returns VINF_SSM_DONT_CALL_AGAIN.
621	* @param pVM The cross context VM structure.
622	* @param pSSM The saved state handle.
623	* @param uPass The pass (0).
624	*/
625	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
626	{
627	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
628	cpumR3SaveCpuId(pVM, pSSM);
629	return VINF_SSM_DONT_CALL_AGAIN;
630	}
631
632
633	/**
634	* Execute state save operation.
635	*
636	* @returns VBox status code.
637	* @param pVM The cross context VM structure.
638	* @param pSSM SSM operation handle.
639	*/
640	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
641	{
642	/*
643	* Save.
644	*/
645	SSMR3PutU32(pSSM, pVM->cCpus);
646	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
647	{
648	PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
649	PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
650
651	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
652	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFieldsV2, NULL);
653
654	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
655	}
656
657	cpumR3SaveCpuId(pVM, pSSM);
658	return VINF_SUCCESS;
659	}
660
661
662	/**
663	* @callback_method_impl{FNSSMINTLOADPREP}
664	*/
665	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
666	{
667	RT_NOREF(pSSM);
668	pVM->cpum.s.fPendingRestore = true;
669	return VINF_SUCCESS;
670	}
671
672
673	/**
674	* @callback_method_impl{FNSSMINTLOADEXEC}
675	*/
676	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
677	{
678	/*
679	* Validate version.
680	*/
681	if ( uVersion != CPUM_SAVED_STATE_VERSION
682	&& uVersion != CPUM_SAVED_STATE_VERSION_ARMV8_V1)
683	{
684	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
685	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
686	}
687
688	if (uPass == SSM_PASS_FINAL)
689	{
690	uint32_t cCpus;
691	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
692	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
693	VERR_SSM_UNEXPECTED_DATA);
694
695	/*
696	* Do the per-CPU restoring.
697	*/
698	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
699	{
700	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
701	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
702
703	/*
704	* Restore the CPUMCTX structure.
705	*/
706	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
707	AssertRCReturn(rc, rc);
708
709	if (uVersion == CPUM_SAVED_STATE_VERSION_ARMV8_V2)
710	{
711	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFieldsV2, NULL);
712	AssertRCReturn(rc, rc);
713	}
714
715	/*
716	* Restore a couple of flags.
717	*/
718	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
719	}
720	}
721
722	pVM->cpum.s.fPendingRestore = false;
723
724	/* Load CPUID and explode guest features. */
725	return cpumR3LoadCpuIdArmV8(pVM, pSSM, uVersion);
726	}
727
728
729	/**
730	* @callback_method_impl{FNSSMINTLOADDONE}
731	*/
732	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
733	{
734	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
735	return VINF_SUCCESS;
736
737	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
738	if (pVM->cpum.s.fPendingRestore)
739	{
740	LogRel(("CPUM: Missing state!\n"));
741	return VERR_INTERNAL_ERROR_2;
742	}
743
744	/** @todo */
745	return VINF_SUCCESS;
746	}
747
748
749	/**
750	* Checks if the CPUM state restore is still pending.
751	*
752	* @returns true / false.
753	* @param pVM The cross context VM structure.
754	*/
755	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
756	{
757	return pVM->cpum.s.fPendingRestore;
758	}
759
760
761	/**
762	* Formats the PSTATE value into mnemonics.
763	*
764	* @param pszPState Where to write the mnemonics. (Assumes sufficient buffer space.)
765	* @param fPState The PSTATE value with both guest hardware and VBox
766	* internal bits included.
767	*/
768	static void cpumR3InfoFormatPState(char *pszPState, uint32_t fPState)
769	{
770	/*
771	* Format the flags.
772	*/
773	static const struct
774	{
775	const char pszSet; const char pszClear; uint32_t fFlag;
776	} s_aFlags[] =
777	{
778	{ "SP", "nSP", ARMV8_SPSR_EL2_AARCH64_SP },
779	{ "M4", "nM4", ARMV8_SPSR_EL2_AARCH64_M4 },
780	{ "T", "nT", ARMV8_SPSR_EL2_AARCH64_T },
781	{ "nF", "F", ARMV8_SPSR_EL2_AARCH64_F },
782	{ "nI", "I", ARMV8_SPSR_EL2_AARCH64_I },
783	{ "nA", "A", ARMV8_SPSR_EL2_AARCH64_A },
784	{ "nD", "D", ARMV8_SPSR_EL2_AARCH64_D },
785	{ "V", "nV", ARMV8_SPSR_EL2_AARCH64_V },
786	{ "C", "nC", ARMV8_SPSR_EL2_AARCH64_C },
787	{ "Z", "nZ", ARMV8_SPSR_EL2_AARCH64_Z },
788	{ "N", "nN", ARMV8_SPSR_EL2_AARCH64_N },
789	};
790	char *psz = pszPState;
791	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
792	{
793	const char *pszAdd = s_aFlags[i].fFlag & fPState ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
794	if (pszAdd)
795	{
796	strcpy(psz, pszAdd);
797	psz += strlen(pszAdd);
798	*psz++ = ' ';
799	}
800	}
801	psz[-1] = '\0';
802	}
803
804
805	/**
806	* Formats a full register dump.
807	*
808	* @param pVM The cross context VM structure.
809	* @param pCtx The context to format.
810	* @param pHlp Output functions.
811	* @param enmType The dump type.
812	*/
813	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType)
814	{
815	RT_NOREF(pVM);
816
817	/*
818	* Format the PSTATE.
819	*/
820	char szPState[80];
821	cpumR3InfoFormatPState(&szPState[0], pCtx->fPState);
822
823	/*
824	* Format the registers.
825	*/
826	switch (enmType)
827	{
828	case CPUMDUMPTYPE_TERSE:
829	if (CPUMIsGuestIn64BitCodeEx(pCtx))
830	pHlp->pfnPrintf(pHlp,
831	"x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
832	"x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
833	"x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
834	"x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
835	"x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
836	"x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
837	"x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
838	"x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
839	"pc=%016RX64 pstate=%016RX64 %s\n"
840	"sp_el0=%016RX64 sp_el1=%016RX64\n",
841	pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
842	pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
843	pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
844	pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
845	pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
846	pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
847	pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
848	pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
849	pCtx->Pc.u64, pCtx->fPState, szPState,
850	pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64);
851	else
852	AssertFailed();
853	break;
854
855	case CPUMDUMPTYPE_DEFAULT:
856	if (CPUMIsGuestIn64BitCodeEx(pCtx))
857	pHlp->pfnPrintf(pHlp,
858	"x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
859	"x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
860	"x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
861	"x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
862	"x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
863	"x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
864	"x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
865	"x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
866	"pc=%016RX64 pstate=%016RX64 %s\n"
867	"sp_el0=%016RX64 sp_el1=%016RX64 sctlr_el1=%016RX64\n"
868	"tcr_el1=%016RX64 ttbr0_el1=%016RX64 ttbr1_el1=%016RX64\n"
869	"vbar_el1=%016RX64 elr_el1=%016RX64 esr_el1=%016RX64\n",
870	pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
871	pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
872	pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
873	pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
874	pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
875	pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
876	pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
877	pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
878	pCtx->Pc.u64, pCtx->fPState, szPState,
879	pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64, pCtx->Sctlr.u64,
880	pCtx->Tcr.u64, pCtx->Ttbr0.u64, pCtx->Ttbr1.u64,
881	pCtx->VBar.u64, pCtx->Elr.u64, pCtx->Esr.u64);
882	else
883	AssertFailed();
884	break;
885
886	case CPUMDUMPTYPE_VERBOSE:
887	if (CPUMIsGuestIn64BitCodeEx(pCtx))
888	pHlp->pfnPrintf(pHlp,
889	"x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
890	"x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
891	"x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
892	"x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
893	"x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
894	"x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
895	"x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
896	"x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
897	"pc=%016RX64 pstate=%016RX64 %s\n"
898	"sp_el0=%016RX64 sp_el1=%016RX64 sctlr_el1=%016RX64\n"
899	"tcr_el1=%016RX64 ttbr0_el1=%016RX64 ttbr1_el1=%016RX64\n"
900	"vbar_el1=%016RX64 elr_el1=%016RX64 esr_el1=%016RX64\n"
901	"contextidr_el1=%016RX64 tpidrr0_el0=%016RX64\n"
902	"tpidr_el0=%016RX64 tpidr_el1=%016RX64\n"
903	"far_el1=%016RX64 mair_el1=%016RX64 par_el1=%016RX64\n"
904	"cntv_ctl_el0=%016RX64 cntv_val_el0=%016RX64\n"
905	"afsr0_el1=%016RX64 afsr0_el1=%016RX64 amair_el1=%016RX64\n"
906	"cntkctl_el1=%016RX64 cpacr_el1=%016RX64 csselr_el1=%016RX64\n"
907	"mdccint_el1=%016RX64\n",
908	pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
909	pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
910	pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
911	pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
912	pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
913	pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
914	pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
915	pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
916	pCtx->Pc.u64, pCtx->fPState, szPState,
917	pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64, pCtx->Sctlr.u64,
918	pCtx->Tcr.u64, pCtx->Ttbr0.u64, pCtx->Ttbr1.u64,
919	pCtx->VBar.u64, pCtx->Elr.u64, pCtx->Esr.u64,
920	pCtx->ContextIdr.u64, pCtx->TpIdrRoEl0.u64,
921	pCtx->aTpIdr[0].u64, pCtx->aTpIdr[1].u64,
922	pCtx->Far.u64, pCtx->Mair.u64, pCtx->Par.u64,
923	pCtx->CntvCtlEl0, pCtx->CntvCValEl0,
924	pCtx->Afsr0.u64, pCtx->Afsr1.u64, pCtx->Amair.u64,
925	pCtx->CntKCtl.u64, pCtx->Cpacr.u64, pCtx->Csselr.u64,
926	pCtx->MDccInt.u64);
927	else
928	AssertFailed();
929
930	pHlp->pfnPrintf(pHlp, "fpcr=%016RX64 fpsr=%016RX64\n", pCtx->fpcr, pCtx->fpsr);
931	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aVRegs); i++)
932	pHlp->pfnPrintf(pHlp,
933	i & 1
934	? "q%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
935	: "q%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
936	i, i < 10 ? " " : "",
937	pCtx->aVRegs[i].au32[3],
938	pCtx->aVRegs[i].au32[2],
939	pCtx->aVRegs[i].au32[1],
940	pCtx->aVRegs[i].au32[0]);
941
942	pHlp->pfnPrintf(pHlp, "mdscr_el1=%016RX64\n", pCtx->Mdscr.u64);
943	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aBp); i++)
944	pHlp->pfnPrintf(pHlp, "DbgBp%u%s: Control=%016RX64 Value=%016RX64\n",
945	i, i < 10 ? " " : "",
946	pCtx->aBp[i].Ctrl, pCtx->aBp[i].Value);
947
948	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aWp); i++)
949	pHlp->pfnPrintf(pHlp, "DbgWp%u%s: Control=%016RX64 Value=%016RX64\n",
950	i, i < 10 ? " " : "",
951	pCtx->aWp[i].Ctrl, pCtx->aWp[i].Value);
952
953	pHlp->pfnPrintf(pHlp, "APDAKey=%016RX64'%016RX64\n", pCtx->Apda.High.u64, pCtx->Apda.Low.u64);
954	pHlp->pfnPrintf(pHlp, "APDBKey=%016RX64'%016RX64\n", pCtx->Apdb.High.u64, pCtx->Apdb.Low.u64);
955	pHlp->pfnPrintf(pHlp, "APGAKey=%016RX64'%016RX64\n", pCtx->Apga.High.u64, pCtx->Apga.Low.u64);
956	pHlp->pfnPrintf(pHlp, "APIAKey=%016RX64'%016RX64\n", pCtx->Apia.High.u64, pCtx->Apia.Low.u64);
957	pHlp->pfnPrintf(pHlp, "APIBKey=%016RX64'%016RX64\n", pCtx->Apib.High.u64, pCtx->Apib.Low.u64);
958
959	break;
960	}
961	}
962
963
964	/**
965	* Display all cpu states and any other cpum info.
966	*
967	* @param pVM The cross context VM structure.
968	* @param pHlp The info helper functions.
969	* @param pszArgs Arguments, ignored.
970	*/
971	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
972	{
973	cpumR3InfoGuest(pVM, pHlp, pszArgs);
974	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
975	}
976
977
978	/**
979	* Parses the info argument.
980	*
981	* The argument starts with 'verbose', 'terse' or 'default' and then
982	* continues with the comment string.
983	*
984	* @param pszArgs The pointer to the argument string.
985	* @param penmType Where to store the dump type request.
986	* @param ppszComment Where to store the pointer to the comment string.
987	*/
988	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
989	{
990	if (!pszArgs)
991	{
992	*penmType = CPUMDUMPTYPE_DEFAULT;
993	*ppszComment = "";
994	}
995	else
996	{
997	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
998	{
999	pszArgs += 7;
1000	*penmType = CPUMDUMPTYPE_VERBOSE;
1001	}
1002	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
1003	{
1004	pszArgs += 5;
1005	*penmType = CPUMDUMPTYPE_TERSE;
1006	}
1007	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
1008	{
1009	pszArgs += 7;
1010	*penmType = CPUMDUMPTYPE_DEFAULT;
1011	}
1012	else
1013	*penmType = CPUMDUMPTYPE_DEFAULT;
1014	*ppszComment = RTStrStripL(pszArgs);
1015	}
1016	}
1017
1018
1019	/**
1020	* Display the guest cpu state.
1021	*
1022	* @param pVM The cross context VM structure.
1023	* @param pHlp The info helper functions.
1024	* @param pszArgs Arguments.
1025	*/
1026	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1027	{
1028	CPUMDUMPTYPE enmType;
1029	const char *pszComment;
1030	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1031
1032	PVMCPU pVCpu = VMMGetCpu(pVM);
1033	if (!pVCpu)
1034	pVCpu = pVM->apCpusR3[0];
1035
1036	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1037
1038	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1039	cpumR3InfoOne(pVM, pCtx, pHlp, enmType);
1040	}
1041
1042
1043	/**
1044	* Display the current guest instruction
1045	*
1046	* @param pVM The cross context VM structure.
1047	* @param pHlp The info helper functions.
1048	* @param pszArgs Arguments, ignored.
1049	*/
1050	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1051	{
1052	NOREF(pszArgs);
1053
1054	PVMCPU pVCpu = VMMGetCpu(pVM);
1055	if (!pVCpu)
1056	pVCpu = pVM->apCpusR3[0];
1057
1058	char szInstruction[256];
1059	szInstruction[0] = '\0';
1060	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1061	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
1062	}
1063
1064
1065	/**
1066	* Called when the ring-3 init phase completes.
1067	*
1068	* @returns VBox status code.
1069	* @param pVM The cross context VM structure.
1070	* @param enmWhat Which init phase.
1071	*/
1072	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1073	{
1074	RT_NOREF(pVM, enmWhat);
1075	return VINF_SUCCESS;
1076	}
1077
1078
1079	/**
1080	* Called when the ring-0 init phases completed.
1081	*
1082	* @param pVM The cross context VM structure.
1083	*/
1084	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
1085	{
1086	/*
1087	* Enable log buffering as we're going to log a lot of lines.
1088	*/
1089	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1090
1091	/*
1092	* Log the cpuid.
1093	*/
1094	RTCPUSET OnlineSet;
1095	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
1096	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
1097	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
1098	RTCPUID cCores = RTMpGetCoreCount();
1099	if (cCores)
1100	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
1101	LogRel(("*********************** CPUID dump **********************\n"));
1102	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
1103	LogRel(("\n"));
1104	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
1105	LogRel(("****************** End of CPUID dump ********************\n"));
1106
1107	LogRel(("****************** CPU feature dump *********************\n"));
1108	DBGFR3Info(pVM->pUVM, "cpufeat", "verbose", DBGFR3InfoLogRelHlp());
1109	LogRel(("\n"));
1110	DBGFR3_INFO_LOG_SAFE(pVM, "cpufeat", "verbose"); /* macro */
1111	LogRel(("*************** End of CPU feature dump *****************\n"));
1112
1113	/*
1114	* Restore the log buffering state to what it was previously.
1115	*/
1116	RTLogRelSetBuffering(fOldBuffered);
1117	}
1118
1119	#if 0 /* nobody is are using these atm, they are for AMD64/darwin only */
1120	/**
1121	* Marks the guest debug state as active.
1122	*
1123	* @param pVCpu The cross context virtual CPU structure.
1124	*
1125	* @note This is used solely by NEM (hence the name) to set the correct flags here
1126	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
1127	* The specific NEM backends have to make sure to load the correct values.
1128	*/
1129	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
1130	{
1131	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
1132	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
1133	}
1134
1135
1136	/**
1137	* Marks the hyper debug state as active.
1138	*
1139	* @param pVCpu The cross context virtual CPU structure.
1140	*
1141	* @note This is used solely by NEM (hence the name) to set the correct flags here
1142	* without loading the host's debug registers, which is not possible from ring-3 anyway.
1143	* The specific NEM backends have to make sure to load the correct values.
1144	*/
1145	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
1146	{
1147	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
1148	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
1149	}
1150	#endif

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM-armv8.cpp@ 108843

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