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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM-armv8.cpp@ 101539

Last change on this file since 101539 was 101539, checked in by vboxsync, 7 months ago

DIS,VMM,DBGC,IPRT,++: Some disassembler tweaks and TB disassembly work. bugref:10371 bugref:9898
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1/* $Id: CPUM-armv8.cpp 101539 2023-10-22 02:43:09Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager (ARMv8 variant).
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28/** @page pg_cpum CPUM - CPU Monitor / Manager
29 *
30 * The CPU Monitor / Manager keeps track of all the CPU registers.
31 * This is the ARMv8 variant which is doing much less than its x86/AMD6464
32 * counterpart due to the fact that we currently only support the NEM backends
33 * for running ARM guests. It might become complex iff we decide to implement our
34 * own hypervisor.
35 *
36 * @section sec_cpum_logging_armv8 Logging Level Assignments.
37 *
38 * Following log level assignments:
39 * - @todo
40 *
41 */
42
43
44/*********************************************************************************************************************************
45* Header Files *
46*********************************************************************************************************************************/
47#define LOG_GROUP LOG_GROUP_CPUM
48#define CPUM_WITH_NONCONST_HOST_FEATURES
49#include <VBox/vmm/cpum.h>
50#include <VBox/vmm/cpumdis.h>
51#include <VBox/vmm/pgm.h>
52#include <VBox/vmm/mm.h>
53#include <VBox/vmm/em.h>
54#include <VBox/vmm/iem.h>
55#include <VBox/vmm/dbgf.h>
56#include <VBox/vmm/ssm.h>
57#include "CPUMInternal-armv8.h"
58#include <VBox/vmm/vm.h>
59
60#include <VBox/param.h>
61#include <VBox/dis.h>
62#include <VBox/err.h>
63#include <VBox/log.h>
64#include <iprt/assert.h>
65#include <iprt/cpuset.h>
66#include <iprt/mem.h>
67#include <iprt/mp.h>
68#include <iprt/string.h>
69#include <iprt/armv8.h>
70
71
72/*********************************************************************************************************************************
73* Defined Constants And Macros *
74*********************************************************************************************************************************/
75
76/** Internal form used by the macros. */
77#ifdef VBOX_WITH_STATISTICS
78# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
79 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
80 { 0 }, { 0 }, { 0 }, { 0 } }
81#else
82# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
83 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
84#endif
85
86/** Function handlers, extended version. */
87#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
88 RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
89/** Function handlers, read-only. */
90#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
91 RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
92/** Read-only fixed value, ignores all writes. */
93#define MVI(a_uMsr, a_szName, a_uValue) \
94 RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_FixedValue, kCpumSysRegWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
95
96
97/*********************************************************************************************************************************
98* Structures and Typedefs *
99*********************************************************************************************************************************/
100
101/**
102 * What kind of cpu info dump to perform.
103 */
104typedef enum CPUMDUMPTYPE
105{
106 CPUMDUMPTYPE_TERSE,
107 CPUMDUMPTYPE_DEFAULT,
108 CPUMDUMPTYPE_VERBOSE
109} CPUMDUMPTYPE;
110/** Pointer to a cpu info dump type. */
111typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
112
113
114/*********************************************************************************************************************************
115* Internal Functions *
116*********************************************************************************************************************************/
117static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
118static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
119static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
120static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
121static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
122static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
123static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125
126
127/*********************************************************************************************************************************
128* Global Variables *
129*********************************************************************************************************************************/
130#if defined(RT_ARCH_ARM64)
131/** Host CPU features. */
132DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
133#endif
134
135/**
136 * System register ranges.
137 */
138static CPUMSYSREGRANGE const g_aSysRegRanges[] =
139{
140 MFX(ARMV8_AARCH64_SYSREG_OSLAR_EL1, "OSLAR_EL1", WriteOnly, OslarEl1, 0, UINT64_C(0xfffffffffffffffe), UINT64_C(0xfffffffffffffffe)),
141 MFO(ARMV8_AARCH64_SYSREG_OSLSR_EL1, "OSLSR_EL1", OslsrEl1),
142 MVI(ARMV8_AARCH64_SYSREG_OSDLR_EL1, "OSDLR_EL1", 0)
143};
144
145
146/** Saved state field descriptors for CPUMCTX. */
147static const SSMFIELD g_aCpumCtxFields[] =
148{
149 SSMFIELD_ENTRY( CPUMCTX, aGRegs[0].x),
150 SSMFIELD_ENTRY( CPUMCTX, aGRegs[1].x),
151 SSMFIELD_ENTRY( CPUMCTX, aGRegs[2].x),
152 SSMFIELD_ENTRY( CPUMCTX, aGRegs[3].x),
153 SSMFIELD_ENTRY( CPUMCTX, aGRegs[4].x),
154 SSMFIELD_ENTRY( CPUMCTX, aGRegs[5].x),
155 SSMFIELD_ENTRY( CPUMCTX, aGRegs[6].x),
156 SSMFIELD_ENTRY( CPUMCTX, aGRegs[7].x),
157 SSMFIELD_ENTRY( CPUMCTX, aGRegs[8].x),
158 SSMFIELD_ENTRY( CPUMCTX, aGRegs[9].x),
159 SSMFIELD_ENTRY( CPUMCTX, aGRegs[10].x),
160 SSMFIELD_ENTRY( CPUMCTX, aGRegs[11].x),
161 SSMFIELD_ENTRY( CPUMCTX, aGRegs[12].x),
162 SSMFIELD_ENTRY( CPUMCTX, aGRegs[13].x),
163 SSMFIELD_ENTRY( CPUMCTX, aGRegs[14].x),
164 SSMFIELD_ENTRY( CPUMCTX, aGRegs[15].x),
165 SSMFIELD_ENTRY( CPUMCTX, aGRegs[16].x),
166 SSMFIELD_ENTRY( CPUMCTX, aGRegs[17].x),
167 SSMFIELD_ENTRY( CPUMCTX, aGRegs[18].x),
168 SSMFIELD_ENTRY( CPUMCTX, aGRegs[19].x),
169 SSMFIELD_ENTRY( CPUMCTX, aGRegs[20].x),
170 SSMFIELD_ENTRY( CPUMCTX, aGRegs[21].x),
171 SSMFIELD_ENTRY( CPUMCTX, aGRegs[22].x),
172 SSMFIELD_ENTRY( CPUMCTX, aGRegs[23].x),
173 SSMFIELD_ENTRY( CPUMCTX, aGRegs[24].x),
174 SSMFIELD_ENTRY( CPUMCTX, aGRegs[25].x),
175 SSMFIELD_ENTRY( CPUMCTX, aGRegs[26].x),
176 SSMFIELD_ENTRY( CPUMCTX, aGRegs[27].x),
177 SSMFIELD_ENTRY( CPUMCTX, aGRegs[28].x),
178 SSMFIELD_ENTRY( CPUMCTX, aGRegs[29].x),
179 SSMFIELD_ENTRY( CPUMCTX, aGRegs[30].x),
180 SSMFIELD_ENTRY( CPUMCTX, aVRegs[0].v),
181 SSMFIELD_ENTRY( CPUMCTX, aVRegs[1].v),
182 SSMFIELD_ENTRY( CPUMCTX, aVRegs[2].v),
183 SSMFIELD_ENTRY( CPUMCTX, aVRegs[3].v),
184 SSMFIELD_ENTRY( CPUMCTX, aVRegs[4].v),
185 SSMFIELD_ENTRY( CPUMCTX, aVRegs[5].v),
186 SSMFIELD_ENTRY( CPUMCTX, aVRegs[6].v),
187 SSMFIELD_ENTRY( CPUMCTX, aVRegs[7].v),
188 SSMFIELD_ENTRY( CPUMCTX, aVRegs[8].v),
189 SSMFIELD_ENTRY( CPUMCTX, aVRegs[9].v),
190 SSMFIELD_ENTRY( CPUMCTX, aVRegs[10].v),
191 SSMFIELD_ENTRY( CPUMCTX, aVRegs[11].v),
192 SSMFIELD_ENTRY( CPUMCTX, aVRegs[12].v),
193 SSMFIELD_ENTRY( CPUMCTX, aVRegs[13].v),
194 SSMFIELD_ENTRY( CPUMCTX, aVRegs[14].v),
195 SSMFIELD_ENTRY( CPUMCTX, aVRegs[15].v),
196 SSMFIELD_ENTRY( CPUMCTX, aVRegs[16].v),
197 SSMFIELD_ENTRY( CPUMCTX, aVRegs[17].v),
198 SSMFIELD_ENTRY( CPUMCTX, aVRegs[18].v),
199 SSMFIELD_ENTRY( CPUMCTX, aVRegs[19].v),
200 SSMFIELD_ENTRY( CPUMCTX, aVRegs[20].v),
201 SSMFIELD_ENTRY( CPUMCTX, aVRegs[21].v),
202 SSMFIELD_ENTRY( CPUMCTX, aVRegs[22].v),
203 SSMFIELD_ENTRY( CPUMCTX, aVRegs[23].v),
204 SSMFIELD_ENTRY( CPUMCTX, aVRegs[24].v),
205 SSMFIELD_ENTRY( CPUMCTX, aVRegs[25].v),
206 SSMFIELD_ENTRY( CPUMCTX, aVRegs[26].v),
207 SSMFIELD_ENTRY( CPUMCTX, aVRegs[27].v),
208 SSMFIELD_ENTRY( CPUMCTX, aVRegs[28].v),
209 SSMFIELD_ENTRY( CPUMCTX, aVRegs[29].v),
210 SSMFIELD_ENTRY( CPUMCTX, aVRegs[30].v),
211 SSMFIELD_ENTRY( CPUMCTX, aVRegs[31].v),
212 SSMFIELD_ENTRY( CPUMCTX, aSpReg[0].u64),
213 SSMFIELD_ENTRY( CPUMCTX, aSpReg[1].u64),
214 SSMFIELD_ENTRY( CPUMCTX, Pc.u64),
215 SSMFIELD_ENTRY( CPUMCTX, Spsr.u64),
216 SSMFIELD_ENTRY( CPUMCTX, Elr.u64),
217 SSMFIELD_ENTRY( CPUMCTX, Sctlr.u64),
218 SSMFIELD_ENTRY( CPUMCTX, Tcr.u64),
219 SSMFIELD_ENTRY( CPUMCTX, Ttbr0.u64),
220 SSMFIELD_ENTRY( CPUMCTX, Ttbr1.u64),
221 SSMFIELD_ENTRY( CPUMCTX, VBar.u64),
222 SSMFIELD_ENTRY( CPUMCTX, aBp[0].Ctrl.u64),
223 SSMFIELD_ENTRY( CPUMCTX, aBp[0].Value.u64),
224 SSMFIELD_ENTRY( CPUMCTX, aBp[1].Ctrl.u64),
225 SSMFIELD_ENTRY( CPUMCTX, aBp[1].Value.u64),
226 SSMFIELD_ENTRY( CPUMCTX, aBp[2].Ctrl.u64),
227 SSMFIELD_ENTRY( CPUMCTX, aBp[2].Value.u64),
228 SSMFIELD_ENTRY( CPUMCTX, aBp[3].Ctrl.u64),
229 SSMFIELD_ENTRY( CPUMCTX, aBp[3].Value.u64),
230 SSMFIELD_ENTRY( CPUMCTX, aBp[4].Ctrl.u64),
231 SSMFIELD_ENTRY( CPUMCTX, aBp[4].Value.u64),
232 SSMFIELD_ENTRY( CPUMCTX, aBp[5].Ctrl.u64),
233 SSMFIELD_ENTRY( CPUMCTX, aBp[5].Value.u64),
234 SSMFIELD_ENTRY( CPUMCTX, aBp[6].Ctrl.u64),
235 SSMFIELD_ENTRY( CPUMCTX, aBp[6].Value.u64),
236 SSMFIELD_ENTRY( CPUMCTX, aBp[7].Ctrl.u64),
237 SSMFIELD_ENTRY( CPUMCTX, aBp[7].Value.u64),
238 SSMFIELD_ENTRY( CPUMCTX, aBp[8].Ctrl.u64),
239 SSMFIELD_ENTRY( CPUMCTX, aBp[8].Value.u64),
240 SSMFIELD_ENTRY( CPUMCTX, aBp[9].Ctrl.u64),
241 SSMFIELD_ENTRY( CPUMCTX, aBp[9].Value.u64),
242 SSMFIELD_ENTRY( CPUMCTX, aBp[10].Ctrl.u64),
243 SSMFIELD_ENTRY( CPUMCTX, aBp[10].Value.u64),
244 SSMFIELD_ENTRY( CPUMCTX, aBp[11].Ctrl.u64),
245 SSMFIELD_ENTRY( CPUMCTX, aBp[11].Value.u64),
246 SSMFIELD_ENTRY( CPUMCTX, aBp[12].Ctrl.u64),
247 SSMFIELD_ENTRY( CPUMCTX, aBp[12].Value.u64),
248 SSMFIELD_ENTRY( CPUMCTX, aBp[13].Ctrl.u64),
249 SSMFIELD_ENTRY( CPUMCTX, aBp[13].Value.u64),
250 SSMFIELD_ENTRY( CPUMCTX, aBp[14].Ctrl.u64),
251 SSMFIELD_ENTRY( CPUMCTX, aBp[14].Value.u64),
252 SSMFIELD_ENTRY( CPUMCTX, aBp[15].Ctrl.u64),
253 SSMFIELD_ENTRY( CPUMCTX, aBp[15].Value.u64),
254 SSMFIELD_ENTRY( CPUMCTX, aWp[0].Ctrl.u64),
255 SSMFIELD_ENTRY( CPUMCTX, aWp[0].Value.u64),
256 SSMFIELD_ENTRY( CPUMCTX, aWp[1].Ctrl.u64),
257 SSMFIELD_ENTRY( CPUMCTX, aWp[1].Value.u64),
258 SSMFIELD_ENTRY( CPUMCTX, aWp[2].Ctrl.u64),
259 SSMFIELD_ENTRY( CPUMCTX, aWp[2].Value.u64),
260 SSMFIELD_ENTRY( CPUMCTX, aWp[3].Ctrl.u64),
261 SSMFIELD_ENTRY( CPUMCTX, aWp[3].Value.u64),
262 SSMFIELD_ENTRY( CPUMCTX, aWp[4].Ctrl.u64),
263 SSMFIELD_ENTRY( CPUMCTX, aWp[4].Value.u64),
264 SSMFIELD_ENTRY( CPUMCTX, aWp[5].Ctrl.u64),
265 SSMFIELD_ENTRY( CPUMCTX, aWp[5].Value.u64),
266 SSMFIELD_ENTRY( CPUMCTX, aWp[6].Ctrl.u64),
267 SSMFIELD_ENTRY( CPUMCTX, aWp[6].Value.u64),
268 SSMFIELD_ENTRY( CPUMCTX, aWp[7].Ctrl.u64),
269 SSMFIELD_ENTRY( CPUMCTX, aWp[7].Value.u64),
270 SSMFIELD_ENTRY( CPUMCTX, aWp[8].Ctrl.u64),
271 SSMFIELD_ENTRY( CPUMCTX, aWp[8].Value.u64),
272 SSMFIELD_ENTRY( CPUMCTX, aWp[9].Ctrl.u64),
273 SSMFIELD_ENTRY( CPUMCTX, aWp[9].Value.u64),
274 SSMFIELD_ENTRY( CPUMCTX, aWp[10].Ctrl.u64),
275 SSMFIELD_ENTRY( CPUMCTX, aWp[10].Value.u64),
276 SSMFIELD_ENTRY( CPUMCTX, aWp[11].Ctrl.u64),
277 SSMFIELD_ENTRY( CPUMCTX, aWp[11].Value.u64),
278 SSMFIELD_ENTRY( CPUMCTX, aWp[12].Ctrl.u64),
279 SSMFIELD_ENTRY( CPUMCTX, aWp[12].Value.u64),
280 SSMFIELD_ENTRY( CPUMCTX, aWp[13].Ctrl.u64),
281 SSMFIELD_ENTRY( CPUMCTX, aWp[13].Value.u64),
282 SSMFIELD_ENTRY( CPUMCTX, aWp[14].Ctrl.u64),
283 SSMFIELD_ENTRY( CPUMCTX, aWp[14].Value.u64),
284 SSMFIELD_ENTRY( CPUMCTX, aWp[15].Ctrl.u64),
285 SSMFIELD_ENTRY( CPUMCTX, aWp[15].Value.u64),
286 SSMFIELD_ENTRY( CPUMCTX, Mdscr.u64),
287 SSMFIELD_ENTRY( CPUMCTX, Apda.Low.u64),
288 SSMFIELD_ENTRY( CPUMCTX, Apda.High.u64),
289 SSMFIELD_ENTRY( CPUMCTX, Apdb.Low.u64),
290 SSMFIELD_ENTRY( CPUMCTX, Apdb.High.u64),
291 SSMFIELD_ENTRY( CPUMCTX, Apga.Low.u64),
292 SSMFIELD_ENTRY( CPUMCTX, Apga.High.u64),
293 SSMFIELD_ENTRY( CPUMCTX, Apia.Low.u64),
294 SSMFIELD_ENTRY( CPUMCTX, Apia.High.u64),
295 SSMFIELD_ENTRY( CPUMCTX, Apib.Low.u64),
296 SSMFIELD_ENTRY( CPUMCTX, Apib.High.u64),
297 SSMFIELD_ENTRY( CPUMCTX, Afsr0.u64),
298 SSMFIELD_ENTRY( CPUMCTX, Afsr1.u64),
299 SSMFIELD_ENTRY( CPUMCTX, Amair.u64),
300 SSMFIELD_ENTRY( CPUMCTX, CntKCtl.u64),
301 SSMFIELD_ENTRY( CPUMCTX, ContextIdr.u64),
302 SSMFIELD_ENTRY( CPUMCTX, Cpacr.u64),
303 SSMFIELD_ENTRY( CPUMCTX, Csselr.u64),
304 SSMFIELD_ENTRY( CPUMCTX, Esr.u64),
305 SSMFIELD_ENTRY( CPUMCTX, Far.u64),
306 SSMFIELD_ENTRY( CPUMCTX, Mair.u64),
307 SSMFIELD_ENTRY( CPUMCTX, Par.u64),
308 SSMFIELD_ENTRY( CPUMCTX, TpIdrRoEl0.u64),
309 SSMFIELD_ENTRY( CPUMCTX, aTpIdr[0].u64),
310 SSMFIELD_ENTRY( CPUMCTX, aTpIdr[1].u64),
311 SSMFIELD_ENTRY( CPUMCTX, MDccInt.u64),
312 SSMFIELD_ENTRY( CPUMCTX, fpcr),
313 SSMFIELD_ENTRY( CPUMCTX, fpsr),
314 SSMFIELD_ENTRY( CPUMCTX, fPState),
315 SSMFIELD_ENTRY( CPUMCTX, fOsLck),
316 SSMFIELD_ENTRY( CPUMCTX, CntvCtlEl0),
317 SSMFIELD_ENTRY( CPUMCTX, CntvCValEl0),
318 SSMFIELD_ENTRY_TERM()
319};
320
321
322/**
323 * Initializes the guest system register states.
324 *
325 * @returns VBox status code.
326 * @param pVM The cross context VM structure.
327 */
328static int cpumR3InitSysRegs(PVM pVM)
329{
330 for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges); i++)
331 {
332 int rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges[i]);
333 AssertLogRelRCReturn(rc, rc);
334 }
335
336 return VINF_SUCCESS;
337}
338
339
340/**
341 * Initializes the CPUM.
342 *
343 * @returns VBox status code.
344 * @param pVM The cross context VM structure.
345 */
346VMMR3DECL(int) CPUMR3Init(PVM pVM)
347{
348 LogFlow(("CPUMR3Init\n"));
349
350 /*
351 * Assert alignment, sizes and tables.
352 */
353 AssertCompileMemberAlignment(VM, cpum.s, 32);
354 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
355 AssertCompileSizeAlignment(CPUMCTX, 64);
356 AssertCompileMemberAlignment(VM, cpum, 64);
357 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
358#ifdef VBOX_STRICT
359 int rc2 = cpumR3SysRegStrictInitChecks();
360 AssertRCReturn(rc2, rc2);
361#endif
362
363 pVM->cpum.s.GuestInfo.paSysRegRangesR3 = &pVM->cpum.s.GuestInfo.aSysRegRanges[0];
364
365 /*
366 * Register saved state data item.
367 */
368 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
369 NULL, cpumR3LiveExec, NULL,
370 NULL, cpumR3SaveExec, NULL,
371 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
372 if (RT_FAILURE(rc))
373 return rc;
374
375 /*
376 * Register info handlers and registers with the debugger facility.
377 */
378 DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
379 &cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
380 DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
381 &cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
382 DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
383 &cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
384 DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid information.",
385 &cpumR3CpuIdInfo);
386 DBGFR3InfoRegisterInternal( pVM, "cpufeat", "Displays the guest features.",
387 &cpumR3CpuFeatInfo);
388
389 rc = cpumR3DbgInit(pVM);
390 if (RT_FAILURE(rc))
391 return rc;
392
393 /*
394 * Initialize the Guest system register states.
395 */
396 rc = cpumR3InitSysRegs(pVM);
397 if (RT_FAILURE(rc))
398 return rc;
399
400 /*
401 * Initialize the general guest CPU state.
402 */
403 CPUMR3Reset(pVM);
404
405 return VINF_SUCCESS;
406}
407
408
409/**
410 * Applies relocations to data and code managed by this
411 * component. This function will be called at init and
412 * whenever the VMM need to relocate it self inside the GC.
413 *
414 * The CPUM will update the addresses used by the switcher.
415 *
416 * @param pVM The cross context VM structure.
417 */
418VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
419{
420 RT_NOREF(pVM);
421}
422
423
424/**
425 * Terminates the CPUM.
426 *
427 * Termination means cleaning up and freeing all resources,
428 * the VM it self is at this point powered off or suspended.
429 *
430 * @returns VBox status code.
431 * @param pVM The cross context VM structure.
432 */
433VMMR3DECL(int) CPUMR3Term(PVM pVM)
434{
435 RT_NOREF(pVM);
436 return VINF_SUCCESS;
437}
438
439
440/**
441 * Resets a virtual CPU.
442 *
443 * Used by CPUMR3Reset and CPU hot plugging.
444 *
445 * @param pVM The cross context VM structure.
446 * @param pVCpu The cross context virtual CPU structure of the CPU that is
447 * being reset. This may differ from the current EMT.
448 */
449VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
450{
451 RT_NOREF(pVM);
452
453 /** @todo anything different for VCPU > 0? */
454 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
455
456 /*
457 * Initialize everything to ZERO first.
458 */
459 RT_BZERO(pCtx, sizeof(*pCtx));
460
461 /* Start in Supervisor mode. */
462 /** @todo Differentiate between Aarch64 and Aarch32 configuation. */
463 pCtx->fPState = ARMV8_SPSR_EL2_AARCH64_SET_EL(ARMV8_AARCH64_EL_1)
464 | ARMV8_SPSR_EL2_AARCH64_SP
465 | ARMV8_SPSR_EL2_AARCH64_D
466 | ARMV8_SPSR_EL2_AARCH64_A
467 | ARMV8_SPSR_EL2_AARCH64_I
468 | ARMV8_SPSR_EL2_AARCH64_F;
469 /** @todo */
470}
471
472
473/**
474 * Resets the CPU.
475 *
476 * @param pVM The cross context VM structure.
477 */
478VMMR3DECL(void) CPUMR3Reset(PVM pVM)
479{
480 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
481 {
482 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
483 CPUMR3ResetCpu(pVM, pVCpu);
484 }
485}
486
487
488
489
490/**
491 * Pass 0 live exec callback.
492 *
493 * @returns VINF_SSM_DONT_CALL_AGAIN.
494 * @param pVM The cross context VM structure.
495 * @param pSSM The saved state handle.
496 * @param uPass The pass (0).
497 */
498static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
499{
500 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
501 cpumR3SaveCpuId(pVM, pSSM);
502 return VINF_SSM_DONT_CALL_AGAIN;
503}
504
505
506/**
507 * Execute state save operation.
508 *
509 * @returns VBox status code.
510 * @param pVM The cross context VM structure.
511 * @param pSSM SSM operation handle.
512 */
513static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
514{
515 /*
516 * Save.
517 */
518 SSMR3PutU32(pSSM, pVM->cCpus);
519 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
520 {
521 PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
522 PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
523
524 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
525
526 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
527 }
528
529 cpumR3SaveCpuId(pVM, pSSM);
530 return VINF_SUCCESS;
531}
532
533
534/**
535 * @callback_method_impl{FNSSMINTLOADPREP}
536 */
537static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
538{
539 RT_NOREF(pSSM);
540 pVM->cpum.s.fPendingRestore = true;
541 return VINF_SUCCESS;
542}
543
544
545/**
546 * @callback_method_impl{FNSSMINTLOADEXEC}
547 */
548static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
549{
550 /*
551 * Validate version.
552 */
553 if (uVersion != CPUM_SAVED_STATE_VERSION)
554 {
555 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
556 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
557 }
558
559 if (uPass == SSM_PASS_FINAL)
560 {
561 uint32_t cCpus;
562 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
563 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
564 VERR_SSM_UNEXPECTED_DATA);
565
566 /*
567 * Do the per-CPU restoring.
568 */
569 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
570 {
571 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
572 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
573
574 /*
575 * Restore the CPUMCTX structure.
576 */
577 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
578 AssertRCReturn(rc, rc);
579
580 /*
581 * Restore a couple of flags.
582 */
583 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
584 }
585 }
586
587 pVM->cpum.s.fPendingRestore = false;
588
589 /* Load CPUID and explode guest features. */
590 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
591}
592
593
594/**
595 * @callback_method_impl{FNSSMINTLOADDONE}
596 */
597static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
598{
599 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
600 return VINF_SUCCESS;
601
602 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
603 if (pVM->cpum.s.fPendingRestore)
604 {
605 LogRel(("CPUM: Missing state!\n"));
606 return VERR_INTERNAL_ERROR_2;
607 }
608
609 /** @todo */
610 return VINF_SUCCESS;
611}
612
613
614/**
615 * Checks if the CPUM state restore is still pending.
616 *
617 * @returns true / false.
618 * @param pVM The cross context VM structure.
619 */
620VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
621{
622 return pVM->cpum.s.fPendingRestore;
623}
624
625
626/**
627 * Formats the PSTATE value into mnemonics.
628 *
629 * @param pszPState Where to write the mnemonics. (Assumes sufficient buffer space.)
630 * @param fPState The PSTATE value with both guest hardware and VBox
631 * internal bits included.
632 */
633static void cpumR3InfoFormatPState(char *pszPState, uint32_t fPState)
634{
635 /*
636 * Format the flags.
637 */
638 static const struct
639 {
640 const char *pszSet; const char *pszClear; uint32_t fFlag;
641 } s_aFlags[] =
642 {
643 { "SP", "nSP", ARMV8_SPSR_EL2_AARCH64_SP },
644 { "M4", "nM4", ARMV8_SPSR_EL2_AARCH64_M4 },
645 { "T", "nT", ARMV8_SPSR_EL2_AARCH64_T },
646 { "nF", "F", ARMV8_SPSR_EL2_AARCH64_F },
647 { "nI", "I", ARMV8_SPSR_EL2_AARCH64_I },
648 { "nA", "A", ARMV8_SPSR_EL2_AARCH64_A },
649 { "nD", "D", ARMV8_SPSR_EL2_AARCH64_D },
650 { "V", "nV", ARMV8_SPSR_EL2_AARCH64_V },
651 { "C", "nC", ARMV8_SPSR_EL2_AARCH64_C },
652 { "Z", "nZ", ARMV8_SPSR_EL2_AARCH64_Z },
653 { "N", "nN", ARMV8_SPSR_EL2_AARCH64_N },
654 };
655 char *psz = pszPState;
656 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
657 {
658 const char *pszAdd = s_aFlags[i].fFlag & fPState ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
659 if (pszAdd)
660 {
661 strcpy(psz, pszAdd);
662 psz += strlen(pszAdd);
663 *psz++ = ' ';
664 }
665 }
666 psz[-1] = '\0';
667}
668
669
670/**
671 * Formats a full register dump.
672 *
673 * @param pVM The cross context VM structure.
674 * @param pCtx The context to format.
675 * @param pHlp Output functions.
676 * @param enmType The dump type.
677 */
678static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType)
679{
680 RT_NOREF(pVM);
681
682 /*
683 * Format the PSTATE.
684 */
685 char szPState[80];
686 cpumR3InfoFormatPState(&szPState[0], pCtx->fPState);
687
688 /*
689 * Format the registers.
690 */
691 switch (enmType)
692 {
693 case CPUMDUMPTYPE_TERSE:
694 if (CPUMIsGuestIn64BitCodeEx(pCtx))
695 pHlp->pfnPrintf(pHlp,
696 "x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
697 "x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
698 "x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
699 "x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
700 "x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
701 "x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
702 "x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
703 "x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
704 "pc=%016RX64 pstate=%016RX64 %s\n"
705 "sp_el0=%016RX64 sp_el1=%016RX64\n",
706 pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
707 pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
708 pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
709 pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
710 pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
711 pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
712 pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
713 pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
714 pCtx->Pc.u64, pCtx->fPState, szPState,
715 pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64);
716 else
717 AssertFailed();
718 break;
719
720 case CPUMDUMPTYPE_DEFAULT:
721 if (CPUMIsGuestIn64BitCodeEx(pCtx))
722 pHlp->pfnPrintf(pHlp,
723 "x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
724 "x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
725 "x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
726 "x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
727 "x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
728 "x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
729 "x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
730 "x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
731 "pc=%016RX64 pstate=%016RX64 %s\n"
732 "sp_el0=%016RX64 sp_el1=%016RX64 sctlr_el1=%016RX64\n"
733 "tcr_el1=%016RX64 ttbr0_el1=%016RX64 ttbr1_el1=%016RX64\n"
734 "vbar_el1=%016RX64 elr_el1=%016RX64 esr_el1=%016RX64\n",
735 pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
736 pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
737 pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
738 pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
739 pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
740 pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
741 pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
742 pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
743 pCtx->Pc.u64, pCtx->fPState, szPState,
744 pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64, pCtx->Sctlr.u64,
745 pCtx->Tcr.u64, pCtx->Ttbr0.u64, pCtx->Ttbr1.u64,
746 pCtx->VBar.u64, pCtx->Elr.u64, pCtx->Esr.u64);
747 else
748 AssertFailed();
749 break;
750
751 case CPUMDUMPTYPE_VERBOSE:
752 if (CPUMIsGuestIn64BitCodeEx(pCtx))
753 pHlp->pfnPrintf(pHlp,
754 "x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
755 "x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
756 "x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
757 "x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
758 "x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
759 "x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
760 "x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
761 "x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
762 "pc=%016RX64 pstate=%016RX64 %s\n"
763 "sp_el0=%016RX64 sp_el1=%016RX64 sctlr_el1=%016RX64\n"
764 "tcr_el1=%016RX64 ttbr0_el1=%016RX64 ttbr1_el1=%016RX64\n"
765 "vbar_el1=%016RX64 elr_el1=%016RX64 esr_el1=%016RX64\n"
766 "contextidr_el1=%016RX64 tpidrr0_el0=%016RX64\n"
767 "tpidr_el0=%016RX64 tpidr_el1=%016RX64\n"
768 "far_el1=%016RX64 mair_el1=%016RX64 par_el1=%016RX64\n"
769 "cntv_ctl_el0=%016RX64 cntv_val_el0=%016RX64\n"
770 "afsr0_el1=%016RX64 afsr0_el1=%016RX64 amair_el1=%016RX64\n"
771 "cntkctl_el1=%016RX64 cpacr_el1=%016RX64 csselr_el1=%016RX64\n"
772 "mdccint_el1=%016RX64\n",
773 pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
774 pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
775 pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
776 pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
777 pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
778 pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
779 pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
780 pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
781 pCtx->Pc.u64, pCtx->fPState, szPState,
782 pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64, pCtx->Sctlr.u64,
783 pCtx->Tcr.u64, pCtx->Ttbr0.u64, pCtx->Ttbr1.u64,
784 pCtx->VBar.u64, pCtx->Elr.u64, pCtx->Esr.u64,
785 pCtx->ContextIdr.u64, pCtx->TpIdrRoEl0.u64,
786 pCtx->aTpIdr[0].u64, pCtx->aTpIdr[1].u64,
787 pCtx->Far.u64, pCtx->Mair.u64, pCtx->Par.u64,
788 pCtx->CntvCtlEl0, pCtx->CntvCValEl0,
789 pCtx->Afsr0.u64, pCtx->Afsr1.u64, pCtx->Amair.u64,
790 pCtx->CntKCtl.u64, pCtx->Cpacr.u64, pCtx->Csselr.u64,
791 pCtx->MDccInt.u64);
792 else
793 AssertFailed();
794
795 pHlp->pfnPrintf(pHlp, "fpcr=%016RX64 fpsr=%016RX64\n", pCtx->fpcr, pCtx->fpsr);
796 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aVRegs); i++)
797 pHlp->pfnPrintf(pHlp,
798 i & 1
799 ? "q%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
800 : "q%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
801 i, i < 10 ? " " : "",
802 pCtx->aVRegs[i].au32[3],
803 pCtx->aVRegs[i].au32[2],
804 pCtx->aVRegs[i].au32[1],
805 pCtx->aVRegs[i].au32[0]);
806
807 pHlp->pfnPrintf(pHlp, "mdscr_el1=%016RX64\n", pCtx->Mdscr.u64);
808 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aBp); i++)
809 pHlp->pfnPrintf(pHlp, "DbgBp%u%s: Control=%016RX64 Value=%016RX64\n",
810 i, i < 10 ? " " : "",
811 pCtx->aBp[i].Ctrl, pCtx->aBp[i].Value);
812
813 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aWp); i++)
814 pHlp->pfnPrintf(pHlp, "DbgWp%u%s: Control=%016RX64 Value=%016RX64\n",
815 i, i < 10 ? " " : "",
816 pCtx->aWp[i].Ctrl, pCtx->aWp[i].Value);
817
818 pHlp->pfnPrintf(pHlp, "APDAKey=%016RX64'%016RX64\n", pCtx->Apda.High.u64, pCtx->Apda.Low.u64);
819 pHlp->pfnPrintf(pHlp, "APDBKey=%016RX64'%016RX64\n", pCtx->Apdb.High.u64, pCtx->Apdb.Low.u64);
820 pHlp->pfnPrintf(pHlp, "APGAKey=%016RX64'%016RX64\n", pCtx->Apga.High.u64, pCtx->Apga.Low.u64);
821 pHlp->pfnPrintf(pHlp, "APIAKey=%016RX64'%016RX64\n", pCtx->Apia.High.u64, pCtx->Apia.Low.u64);
822 pHlp->pfnPrintf(pHlp, "APIBKey=%016RX64'%016RX64\n", pCtx->Apib.High.u64, pCtx->Apib.Low.u64);
823
824 break;
825 }
826}
827
828
829/**
830 * Display all cpu states and any other cpum info.
831 *
832 * @param pVM The cross context VM structure.
833 * @param pHlp The info helper functions.
834 * @param pszArgs Arguments, ignored.
835 */
836static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
837{
838 cpumR3InfoGuest(pVM, pHlp, pszArgs);
839 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
840}
841
842
843/**
844 * Parses the info argument.
845 *
846 * The argument starts with 'verbose', 'terse' or 'default' and then
847 * continues with the comment string.
848 *
849 * @param pszArgs The pointer to the argument string.
850 * @param penmType Where to store the dump type request.
851 * @param ppszComment Where to store the pointer to the comment string.
852 */
853static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
854{
855 if (!pszArgs)
856 {
857 *penmType = CPUMDUMPTYPE_DEFAULT;
858 *ppszComment = "";
859 }
860 else
861 {
862 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
863 {
864 pszArgs += 7;
865 *penmType = CPUMDUMPTYPE_VERBOSE;
866 }
867 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
868 {
869 pszArgs += 5;
870 *penmType = CPUMDUMPTYPE_TERSE;
871 }
872 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
873 {
874 pszArgs += 7;
875 *penmType = CPUMDUMPTYPE_DEFAULT;
876 }
877 else
878 *penmType = CPUMDUMPTYPE_DEFAULT;
879 *ppszComment = RTStrStripL(pszArgs);
880 }
881}
882
883
884/**
885 * Display the guest cpu state.
886 *
887 * @param pVM The cross context VM structure.
888 * @param pHlp The info helper functions.
889 * @param pszArgs Arguments.
890 */
891static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
892{
893 CPUMDUMPTYPE enmType;
894 const char *pszComment;
895 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
896
897 PVMCPU pVCpu = VMMGetCpu(pVM);
898 if (!pVCpu)
899 pVCpu = pVM->apCpusR3[0];
900
901 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
902
903 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
904 cpumR3InfoOne(pVM, pCtx, pHlp, enmType);
905}
906
907
908/**
909 * Display the current guest instruction
910 *
911 * @param pVM The cross context VM structure.
912 * @param pHlp The info helper functions.
913 * @param pszArgs Arguments, ignored.
914 */
915static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
916{
917 NOREF(pszArgs);
918
919 PVMCPU pVCpu = VMMGetCpu(pVM);
920 if (!pVCpu)
921 pVCpu = pVM->apCpusR3[0];
922
923 char szInstruction[256];
924 szInstruction[0] = '\0';
925 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
926 pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
927}
928
929
930/**
931 * Called when the ring-3 init phase completes.
932 *
933 * @returns VBox status code.
934 * @param pVM The cross context VM structure.
935 * @param enmWhat Which init phase.
936 */
937VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
938{
939 RT_NOREF(pVM, enmWhat);
940 return VINF_SUCCESS;
941}
942
943
944/**
945 * Called when the ring-0 init phases completed.
946 *
947 * @param pVM The cross context VM structure.
948 */
949VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
950{
951 /*
952 * Enable log buffering as we're going to log a lot of lines.
953 */
954 bool const fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
955
956 /*
957 * Log the cpuid.
958 */
959 RTCPUSET OnlineSet;
960 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
961 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
962 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
963 RTCPUID cCores = RTMpGetCoreCount();
964 if (cCores)
965 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
966 LogRel(("************************* CPUID dump ************************\n"));
967 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
968 LogRel(("\n"));
969 DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
970 LogRel(("******************** End of CPUID dump **********************\n"));
971
972 LogRel(("******************** CPU feature dump ***********************\n"));
973 DBGFR3Info(pVM->pUVM, "cpufeat", "verbose", DBGFR3InfoLogRelHlp());
974 LogRel(("\n"));
975 DBGFR3_INFO_LOG_SAFE(pVM, "cpufeat", "verbose"); /* macro */
976 LogRel(("***************** End of CPU feature dump *******************\n"));
977
978 /*
979 * Restore the log buffering state to what it was previously.
980 */
981 RTLogRelSetBuffering(fOldBuffered);
982}
983
984
985/**
986 * Marks the guest debug state as active.
987 *
988 * @param pVCpu The cross context virtual CPU structure.
989 *
990 * @note This is used solely by NEM (hence the name) to set the correct flags here
991 * without loading the host's DRx registers, which is not possible from ring-3 anyway.
992 * The specific NEM backends have to make sure to load the correct values.
993 */
994VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
995{
996 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
997 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
998}
999
1000
1001/**
1002 * Marks the hyper debug state as active.
1003 *
1004 * @param pVCpu The cross context virtual CPU structure.
1005 *
1006 * @note This is used solely by NEM (hence the name) to set the correct flags here
1007 * without loading the host's debug registers, which is not possible from ring-3 anyway.
1008 * The specific NEM backends have to make sure to load the correct values.
1009 */
1010VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
1011{
1012 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
1013 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
1014}
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