VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/APIC.cpp@ 96860

Last change on this file since 96860 was 96407, checked in by vboxsync, 22 months ago

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1/* $Id: APIC.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_APIC
33#include <VBox/log.h>
34#include "APICInternal.h"
35#include <VBox/vmm/apic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/hm.h>
38#include <VBox/vmm/mm.h>
39#include <VBox/vmm/pdmdev.h>
40#include <VBox/vmm/ssm.h>
41#include <VBox/vmm/vm.h>
42
43
44#ifndef VBOX_DEVICE_STRUCT_TESTCASE
45
46
47/*********************************************************************************************************************************
48* Defined Constants And Macros *
49*********************************************************************************************************************************/
50/** The current APIC saved state version. */
51#define APIC_SAVED_STATE_VERSION 5
52/** VirtualBox 5.1 beta2 - pre fActiveLintX. */
53#define APIC_SAVED_STATE_VERSION_VBOX_51_BETA2 4
54/** The saved state version used by VirtualBox 5.0 and
55 * earlier. */
56#define APIC_SAVED_STATE_VERSION_VBOX_50 3
57/** The saved state version used by VirtualBox v3 and earlier.
58 * This does not include the config. */
59#define APIC_SAVED_STATE_VERSION_VBOX_30 2
60/** Some ancient version... */
61#define APIC_SAVED_STATE_VERSION_ANCIENT 1
62
63#ifdef VBOX_WITH_STATISTICS
64# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
65 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
66# define X2APIC_MSRRANGE_INVALID(a_uFirst, a_uLast, a_szName) \
67 { (a_uFirst), (a_uLast), kCpumMsrRdFn_WriteOnly, kCpumMsrWrFn_ReadOnly, 0, 0, 0, 0, UINT64_MAX /*fWrGpMask*/, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
68#else
69# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
70 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName }
71# define X2APIC_MSRRANGE_INVALID(a_uFirst, a_uLast, a_szName) \
72 { (a_uFirst), (a_uLast), kCpumMsrRdFn_WriteOnly, kCpumMsrWrFn_ReadOnly, 0, 0, 0, 0, UINT64_MAX /*fWrGpMask*/, a_szName }
73#endif
74
75
76/*********************************************************************************************************************************
77* Global Variables *
78*********************************************************************************************************************************/
79/**
80 * MSR range supported by the x2APIC.
81 * See Intel spec. 10.12.2 "x2APIC Register Availability".
82 */
83static CPUMMSRRANGE const g_MsrRange_x2Apic = X2APIC_MSRRANGE(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range");
84static CPUMMSRRANGE const g_MsrRange_x2Apic_Invalid = X2APIC_MSRRANGE_INVALID(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range invalid");
85#undef X2APIC_MSRRANGE
86#undef X2APIC_MSRRANGE_GP
87
88/** Saved state field descriptors for XAPICPAGE. */
89static const SSMFIELD g_aXApicPageFields[] =
90{
91 SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
92 SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
93 SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
94 SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
95 SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
96 SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
97 SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
98 SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
99 SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
100 SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
101 SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
102 SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
103 SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
104 SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
105 SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
106 SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
107 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
108 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
109 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
110 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
111 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
112 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
113 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
114 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
115 SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
116 SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
117 SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
118 SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
119 SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
120 SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
121 SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
122 SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
123 SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
124 SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
125 SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
126 SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
127 SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
128 SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
129 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
130 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
131 SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
132 SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
133 SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
134 SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
135 SSMFIELD_ENTRY_TERM()
136};
137
138/** Saved state field descriptors for X2APICPAGE. */
139static const SSMFIELD g_aX2ApicPageFields[] =
140{
141 SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
142 SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
143 SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
144 SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
145 SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
146 SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
147 SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
148 SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
149 SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
150 SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
151 SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
152 SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
153 SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
154 SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
155 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
156 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
157 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
158 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
159 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
160 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
161 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
162 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
163 SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
164 SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
165 SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
166 SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
167 SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
168 SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
169 SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
170 SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
171 SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
172 SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
173 SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
174 SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
175 SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
176 SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
177 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
178 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
179 SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
180 SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
181 SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
182 SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
183 SSMFIELD_ENTRY_TERM()
184};
185
186
187/**
188 * Sets the CPUID feature bits for the APIC mode.
189 *
190 * @param pVM The cross context VM structure.
191 * @param enmMode The APIC mode.
192 */
193static void apicR3SetCpuIdFeatureLevel(PVM pVM, PDMAPICMODE enmMode)
194{
195 switch (enmMode)
196 {
197 case PDMAPICMODE_NONE:
198 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
199 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
200 break;
201
202 case PDMAPICMODE_APIC:
203 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
204 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
205 break;
206
207 case PDMAPICMODE_X2APIC:
208 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
209 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
210 break;
211
212 default:
213 AssertMsgFailed(("Unknown/invalid APIC mode: %d\n", (int)enmMode));
214 }
215}
216
217
218/**
219 * Receives an INIT IPI.
220 *
221 * @param pVCpu The cross context virtual CPU structure.
222 */
223VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
224{
225 VMCPU_ASSERT_EMT(pVCpu);
226 LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
227 apicInitIpi(pVCpu);
228}
229
230
231/**
232 * Sets whether Hyper-V compatibility mode (MSR interface) is enabled or not.
233 *
234 * This mode is a hybrid of xAPIC and x2APIC modes, some caveats:
235 * 1. MSRs are used even ones that are missing (illegal) in x2APIC like DFR.
236 * 2. A single ICR is used by the guest to send IPIs rather than 2 ICR writes.
237 * 3. It is unclear what the behaviour will be when invalid bits are set,
238 * currently we follow x2APIC behaviour of causing a \#GP.
239 *
240 * @param pVM The cross context VM structure.
241 * @param fHyperVCompatMode Whether the compatibility mode is enabled.
242 */
243VMMR3_INT_DECL(void) APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode)
244{
245 Assert(pVM);
246 PAPIC pApic = VM_TO_APIC(pVM);
247 pApic->fHyperVCompatMode = fHyperVCompatMode;
248
249 if (fHyperVCompatMode)
250 LogRel(("APIC: Enabling Hyper-V x2APIC compatibility mode\n"));
251
252 int rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
253 AssertLogRelRC(rc);
254}
255
256
257/**
258 * Helper for dumping an APIC 256-bit sparse register.
259 *
260 * @param pApicReg The APIC 256-bit spare register.
261 * @param pHlp The debug output helper.
262 */
263static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
264{
265 ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
266 unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
267 XAPIC256BITREG ApicReg;
268 RT_ZERO(ApicReg);
269
270 pHlp->pfnPrintf(pHlp, " ");
271 for (ssize_t i = cFragments - 1; i >= 0; i--)
272 {
273 uint32_t const uFragment = pApicReg->u[i].u32Reg;
274 ApicReg.u[i].u32Reg = uFragment;
275 pHlp->pfnPrintf(pHlp, "%08x", uFragment);
276 }
277 pHlp->pfnPrintf(pHlp, "\n");
278
279 uint32_t cPending = 0;
280 pHlp->pfnPrintf(pHlp, " Pending:");
281 for (ssize_t i = cFragments - 1; i >= 0; i--)
282 {
283 uint32_t uFragment = ApicReg.u[i].u32Reg;
284 if (uFragment)
285 {
286 do
287 {
288 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
289 --idxSetBit;
290 ASMBitClear(&uFragment, idxSetBit);
291
292 idxSetBit += (i * cBitsPerFragment);
293 pHlp->pfnPrintf(pHlp, " %#02x", idxSetBit);
294 ++cPending;
295 } while (uFragment);
296 }
297 }
298 if (!cPending)
299 pHlp->pfnPrintf(pHlp, " None");
300 pHlp->pfnPrintf(pHlp, "\n");
301}
302
303
304/**
305 * Helper for dumping an APIC pending-interrupt bitmap.
306 *
307 * @param pApicPib The pending-interrupt bitmap.
308 * @param pHlp The debug output helper.
309 */
310static void apicR3DbgInfoPib(PCAPICPIB pApicPib, PCDBGFINFOHLP pHlp)
311{
312 /* Copy the pending-interrupt bitmap as an APIC 256-bit sparse register. */
313 XAPIC256BITREG ApicReg;
314 RT_ZERO(ApicReg);
315 ssize_t const cFragmentsDst = RT_ELEMENTS(ApicReg.u);
316 ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->au64VectorBitmap);
317 AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->au64VectorBitmap));
318 for (ssize_t idxPib = cFragmentsSrc - 1, idxReg = cFragmentsDst - 1; idxPib >= 0; idxPib--, idxReg -= 2)
319 {
320 uint64_t const uFragment = pApicPib->au64VectorBitmap[idxPib];
321 uint32_t const uFragmentLo = RT_LO_U32(uFragment);
322 uint32_t const uFragmentHi = RT_HI_U32(uFragment);
323 ApicReg.u[idxReg].u32Reg = uFragmentHi;
324 ApicReg.u[idxReg - 1].u32Reg = uFragmentLo;
325 }
326
327 /* Dump it. */
328 apicR3DbgInfo256BitReg(&ApicReg, pHlp);
329}
330
331
332/**
333 * Dumps basic APIC state.
334 *
335 * @param pVM The cross context VM structure.
336 * @param pHlp The info helpers.
337 * @param pszArgs Arguments, ignored.
338 */
339static DECLCALLBACK(void) apicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
340{
341 NOREF(pszArgs);
342 PVMCPU pVCpu = VMMGetCpu(pVM);
343 if (!pVCpu)
344 pVCpu = pVM->apCpusR3[0];
345
346 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
347 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
348 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
349
350 uint64_t const uBaseMsr = pApicCpu->uApicBaseMsr;
351 APICMODE const enmMode = apicGetMode(uBaseMsr);
352 bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
353
354 pHlp->pfnPrintf(pHlp, "APIC%u:\n", pVCpu->idCpu);
355 pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
356 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr));
357 pHlp->pfnPrintf(pHlp, " Mode = %u (%s)\n", enmMode, apicGetModeName(enmMode));
358 if (fX2ApicMode)
359 {
360 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
361 pX2ApicPage->id.u32ApicId);
362 }
363 else
364 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
365 pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
366 pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
367 pHlp->pfnPrintf(pHlp, " Max LVT entry index (0..N) = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
368 pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
369 if (!fX2ApicMode)
370 pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
371 pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
372 pHlp->pfnPrintf(pHlp, " Task-priority class = %#x\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >> 4);
373 pHlp->pfnPrintf(pHlp, " Task-priority subclass = %#x\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
374 pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
375 pHlp->pfnPrintf(pHlp, " Processor-priority class = %#x\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr) >> 4);
376 pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %#x\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
377 if (!fX2ApicMode)
378 pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
379 pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
380 pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
381 : pXApicPage->ldr.u.u8LogicalApicId);
382 if (!fX2ApicMode)
383 {
384 pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
385 pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
386 apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
387 }
388 pHlp->pfnPrintf(pHlp, " SVR = %#x\n", pXApicPage->svr.all.u32Svr);
389 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
390 pXApicPage->svr.u.u8SpuriousVector);
391 pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
392 pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
393 pHlp->pfnPrintf(pHlp, " ISR\n");
394 apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
395 pHlp->pfnPrintf(pHlp, " TMR\n");
396 apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
397 pHlp->pfnPrintf(pHlp, " IRR\n");
398 apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
399 pHlp->pfnPrintf(pHlp, " PIB\n");
400 apicR3DbgInfoPib((PCAPICPIB)pApicCpu->pvApicPibR3, pHlp);
401 pHlp->pfnPrintf(pHlp, " Level PIB\n");
402 apicR3DbgInfoPib(&pApicCpu->ApicPibLevel, pHlp);
403 pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
404 pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
405 pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
406 pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
407 pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
408 pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
409 pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
410 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
411 pXApicPage->icr_lo.u.u8Vector);
412 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
413 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
414 pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
415 apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
416 if (!fX2ApicMode)
417 pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
418 pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
419 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
420 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
421 pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
422 apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
423 pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
424 pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
425 : pXApicPage->icr_hi.u.u8Dest);
426}
427
428
429/**
430 * Helper for dumping the LVT timer.
431 *
432 * @param pVCpu The cross context virtual CPU structure.
433 * @param pHlp The debug output helper.
434 */
435static void apicR3InfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
436{
437 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
438 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
439 pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
440 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
441 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
442 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
443 pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
444 apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
445}
446
447
448/**
449 * Dumps APIC Local Vector Table (LVT) information.
450 *
451 * @param pVM The cross context VM structure.
452 * @param pHlp The info helpers.
453 * @param pszArgs Arguments, ignored.
454 */
455static DECLCALLBACK(void) apicR3InfoLvt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
456{
457 NOREF(pszArgs);
458 PVMCPU pVCpu = VMMGetCpu(pVM);
459 if (!pVCpu)
460 pVCpu = pVM->apCpusR3[0];
461
462 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
463
464 /*
465 * Delivery modes available in the LVT entries. They're different (more reserved stuff) from the
466 * ICR delivery modes and hence we don't use apicGetDeliveryMode but mostly because we want small,
467 * fixed-length strings to fit our formatting needs here.
468 */
469 static const char * const s_apszLvtDeliveryModes[] =
470 {
471 "Fixed ",
472 "Rsvd ",
473 "SMI ",
474 "Rsvd ",
475 "NMI ",
476 "INIT ",
477 "Rsvd ",
478 "ExtINT"
479 };
480 /* Delivery Status. */
481 static const char * const s_apszLvtDeliveryStatus[] =
482 {
483 "Idle",
484 "Pend"
485 };
486 const char *pszNotApplicable = "";
487
488 pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC Local Vector Table (LVT):\n", pVCpu->idCpu);
489 pHlp->pfnPrintf(pHlp, "lvt timermode mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
490 /* Timer. */
491 {
492 /* Timer modes. */
493 static const char * const s_apszLvtTimerModes[] =
494 {
495 "One-shot ",
496 "Periodic ",
497 "TSC-dline"
498 };
499 const uint32_t uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
500 const XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
501 const char *pszTimerMode = s_apszLvtTimerModes[enmTimerMode];
502 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtTimer);
503 const uint8_t uDeliveryStatus = uLvtTimer & XAPIC_LVT_DELIVERY_STATUS;
504 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
505 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
506
507 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
508 "Timer",
509 pszTimerMode,
510 uMask,
511 pszNotApplicable, /* TriggerMode */
512 pszNotApplicable, /* Remote IRR */
513 pszNotApplicable, /* Polarity */
514 pszDeliveryStatus,
515 pszNotApplicable, /* Delivery Mode */
516 uVector,
517 uVector);
518 }
519
520#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
521 /* Thermal sensor. */
522 {
523 uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
524 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtThermal);
525 const uint8_t uDeliveryStatus = uLvtThermal & XAPIC_LVT_DELIVERY_STATUS;
526 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
527 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtThermal);
528 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
529 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtThermal);
530
531 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
532 "Thermal",
533 pszNotApplicable, /* Timer mode */
534 uMask,
535 pszNotApplicable, /* TriggerMode */
536 pszNotApplicable, /* Remote IRR */
537 pszNotApplicable, /* Polarity */
538 pszDeliveryStatus,
539 pszDeliveryMode,
540 uVector,
541 uVector);
542 }
543#endif
544
545 /* Performance Monitor Counters. */
546 {
547 uint32_t const uLvtPerf = pXApicPage->lvt_thermal.all.u32LvtThermal;
548 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtPerf);
549 const uint8_t uDeliveryStatus = uLvtPerf & XAPIC_LVT_DELIVERY_STATUS;
550 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
551 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtPerf);
552 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
553 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtPerf);
554
555 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
556 "Perf",
557 pszNotApplicable, /* Timer mode */
558 uMask,
559 pszNotApplicable, /* TriggerMode */
560 pszNotApplicable, /* Remote IRR */
561 pszNotApplicable, /* Polarity */
562 pszDeliveryStatus,
563 pszDeliveryMode,
564 uVector,
565 uVector);
566 }
567
568 /* LINT0, LINT1. */
569 {
570 /* LINTx name. */
571 static const char * const s_apszLvtLint[] =
572 {
573 "LINT0",
574 "LINT1"
575 };
576 /* Trigger mode. */
577 static const char * const s_apszLvtTriggerModes[] =
578 {
579 "Edge ",
580 "Level"
581 };
582 /* Polarity. */
583 static const char * const s_apszLvtPolarity[] =
584 {
585 "ActiveHi",
586 "ActiveLo"
587 };
588
589 uint32_t aLvtLint[2];
590 aLvtLint[0] = pXApicPage->lvt_lint0.all.u32LvtLint0;
591 aLvtLint[1] = pXApicPage->lvt_lint1.all.u32LvtLint1;
592 for (size_t i = 0; i < RT_ELEMENTS(aLvtLint); i++)
593 {
594 uint32_t const uLvtLint = aLvtLint[i];
595 const char *pszLint = s_apszLvtLint[i];
596 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtLint);
597 const XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvtLint);
598 const char *pszTriggerMode = s_apszLvtTriggerModes[enmTriggerMode];
599 const uint8_t uRemoteIrr = XAPIC_LVT_GET_REMOTE_IRR(uLvtLint);
600 const uint8_t uPolarity = XAPIC_LVT_GET_POLARITY(uLvtLint);
601 const char *pszPolarity = s_apszLvtPolarity[uPolarity];
602 const uint8_t uDeliveryStatus = uLvtLint & XAPIC_LVT_DELIVERY_STATUS;
603 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
604 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint);
605 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
606 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtLint);
607
608 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %u %8s %4s %6s %3u (%#x)\n",
609 pszLint,
610 pszNotApplicable, /* Timer mode */
611 uMask,
612 pszTriggerMode,
613 uRemoteIrr,
614 pszPolarity,
615 pszDeliveryStatus,
616 pszDeliveryMode,
617 uVector,
618 uVector);
619 }
620 }
621
622 /* Error. */
623 {
624 uint32_t const uLvtError = pXApicPage->lvt_thermal.all.u32LvtThermal;
625 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtError);
626 const uint8_t uDeliveryStatus = uLvtError & XAPIC_LVT_DELIVERY_STATUS;
627 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
628 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtError);
629 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
630 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtError);
631
632 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
633 "Error",
634 pszNotApplicable, /* Timer mode */
635 uMask,
636 pszNotApplicable, /* TriggerMode */
637 pszNotApplicable, /* Remote IRR */
638 pszNotApplicable, /* Polarity */
639 pszDeliveryStatus,
640 pszDeliveryMode,
641 uVector,
642 uVector);
643 }
644}
645
646
647/**
648 * Dumps the APIC timer information.
649 *
650 * @param pVM The cross context VM structure.
651 * @param pHlp The info helpers.
652 * @param pszArgs Arguments, ignored.
653 */
654static DECLCALLBACK(void) apicR3InfoTimer(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
655{
656 NOREF(pszArgs);
657 PVMCPU pVCpu = VMMGetCpu(pVM);
658 if (!pVCpu)
659 pVCpu = pVM->apCpusR3[0];
660
661 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
662 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
663
664 pHlp->pfnPrintf(pHlp, "VCPU[%u] Local APIC timer:\n", pVCpu->idCpu);
665 pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
666 pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
667 pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
668 pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
669 pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
670 apicR3InfoLvtTimer(pVCpu, pHlp);
671}
672
673
674#ifdef APIC_FUZZY_SSM_COMPAT_TEST
675
676/**
677 * Reads a 32-bit register at a specified offset.
678 *
679 * @returns The value at the specified offset.
680 * @param pXApicPage The xAPIC page.
681 * @param offReg The offset of the register being read.
682 *
683 * @remarks Duplicate of apicReadRaw32()!
684 */
685static uint32_t apicR3ReadRawR32(PCXAPICPAGE pXApicPage, uint16_t offReg)
686{
687 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
688 uint8_t const *pbXApic = (const uint8_t *)pXApicPage;
689 uint32_t const uValue = *(const uint32_t *)(pbXApic + offReg);
690 return uValue;
691}
692
693
694/**
695 * Helper for dumping per-VCPU APIC state to the release logger.
696 *
697 * This is primarily concerned about the APIC state relevant for saved-states.
698 *
699 * @param pVCpu The cross context virtual CPU structure.
700 * @param pszPrefix A caller supplied prefix before dumping the state.
701 * @param uVersion Data layout version.
702 */
703static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix, uint32_t uVersion)
704{
705 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
706
707 LogRel(("APIC%u: %s (version %u):\n", pVCpu->idCpu, pszPrefix, uVersion));
708
709 switch (uVersion)
710 {
711 case APIC_SAVED_STATE_VERSION:
712 case APIC_SAVED_STATE_VERSION_VBOX_51_BETA2:
713 {
714 /* The auxiliary state. */
715 LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
716 LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
717
718 /* The timer. */
719 LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
720 LogRel(("APIC%u: uHintedTimerInitialCount = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerInitialCount));
721 LogRel(("APIC%u: uHintedTimerShift = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
722
723 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
724 LogRel(("APIC%u: uTimerICR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
725 LogRel(("APIC%u: uTimerCCR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
726
727 /* The PIBs. */
728 LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
729 LogRel(("APIC%u: Level PIB: %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), &pApicCpu->ApicPibLevel));
730
731 /* The LINT0, LINT1 interrupt line active states. */
732 LogRel(("APIC%u: fActiveLint0 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint0));
733 LogRel(("APIC%u: fActiveLint1 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint1));
734
735 /* The APIC page. */
736 LogRel(("APIC%u: APIC page: %.*Rhxs\n", pVCpu->idCpu, sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
737 break;
738 }
739
740 case APIC_SAVED_STATE_VERSION_VBOX_50:
741 case APIC_SAVED_STATE_VERSION_VBOX_30:
742 case APIC_SAVED_STATE_VERSION_ANCIENT:
743 {
744 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
745 LogRel(("APIC%u: uApicBaseMsr = %#RX32\n", pVCpu->idCpu, RT_LO_U32(pApicCpu->uApicBaseMsr)));
746 LogRel(("APIC%u: uId = %#RX32\n", pVCpu->idCpu, pXApicPage->id.u8ApicId));
747 LogRel(("APIC%u: uPhysId = N/A\n", pVCpu->idCpu));
748 LogRel(("APIC%u: uArbId = N/A\n", pVCpu->idCpu));
749 LogRel(("APIC%u: uTpr = %#RX32\n", pVCpu->idCpu, pXApicPage->tpr.u8Tpr));
750 LogRel(("APIC%u: uSvr = %#RX32\n", pVCpu->idCpu, pXApicPage->svr.all.u32Svr));
751 LogRel(("APIC%u: uLdr = %#x\n", pVCpu->idCpu, pXApicPage->ldr.all.u32Ldr));
752 LogRel(("APIC%u: uDfr = %#x\n", pVCpu->idCpu, pXApicPage->dfr.all.u32Dfr));
753
754 for (size_t i = 0; i < 8; i++)
755 {
756 LogRel(("APIC%u: Isr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->isr.u[i].u32Reg));
757 LogRel(("APIC%u: Tmr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->tmr.u[i].u32Reg));
758 LogRel(("APIC%u: Irr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->irr.u[i].u32Reg));
759 }
760
761 for (size_t i = 0; i < XAPIC_MAX_LVT_ENTRIES_P4; i++)
762 {
763 uint16_t const offReg = XAPIC_OFF_LVT_START + (i << 4);
764 LogRel(("APIC%u: Lvt[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, apicR3ReadRawR32(pXApicPage, offReg)));
765 }
766
767 LogRel(("APIC%u: uEsr = %#RX32\n", pVCpu->idCpu, pXApicPage->esr.all.u32Errors));
768 LogRel(("APIC%u: uIcr_Lo = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
769 LogRel(("APIC%u: uIcr_Hi = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
770 LogRel(("APIC%u: uTimerDcr = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_dcr.all.u32DivideValue));
771 LogRel(("APIC%u: uCountShift = %#RX32\n", pVCpu->idCpu, apicGetTimerShift(pXApicPage)));
772 LogRel(("APIC%u: uInitialCount = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
773 LogRel(("APIC%u: u64InitialCountLoadTime = %#RX64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
774 LogRel(("APIC%u: u64NextTime / TimerCCR = %#RX64\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
775 break;
776 }
777
778 default:
779 {
780 LogRel(("APIC: apicR3DumpState: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
781 break;
782 }
783 }
784}
785
786#endif /* APIC_FUZZY_SSM_COMPAT_TEST */
787
788/**
789 * Worker for saving per-VM APIC data.
790 *
791 * @returns VBox status code.
792 * @param pDevIns The device instance.
793 * @param pVM The cross context VM structure.
794 * @param pSSM The SSM handle.
795 */
796static int apicR3SaveVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
797{
798 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
799 PAPIC pApic = VM_TO_APIC(pVM);
800 pHlp->pfnSSMPutU32(pSSM, pVM->cCpus);
801 pHlp->pfnSSMPutBool(pSSM, pApic->fIoApicPresent);
802 return pHlp->pfnSSMPutU32(pSSM, pApic->enmMaxMode);
803}
804
805
806/**
807 * Worker for loading per-VM APIC data.
808 *
809 * @returns VBox status code.
810 * @param pDevIns The device instance.
811 * @param pVM The cross context VM structure.
812 * @param pSSM The SSM handle.
813 */
814static int apicR3LoadVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
815{
816 PAPIC pApic = VM_TO_APIC(pVM);
817 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
818
819 /* Load and verify number of CPUs. */
820 uint32_t cCpus;
821 int rc = pHlp->pfnSSMGetU32(pSSM, &cCpus);
822 AssertRCReturn(rc, rc);
823 if (cCpus != pVM->cCpus)
824 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
825
826 /* Load and verify I/O APIC presence. */
827 bool fIoApicPresent;
828 rc = pHlp->pfnSSMGetBool(pSSM, &fIoApicPresent);
829 AssertRCReturn(rc, rc);
830 if (fIoApicPresent != pApic->fIoApicPresent)
831 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
832 fIoApicPresent, pApic->fIoApicPresent);
833
834 /* Load and verify configured max APIC mode. */
835 uint32_t uSavedMaxApicMode;
836 rc = pHlp->pfnSSMGetU32(pSSM, &uSavedMaxApicMode);
837 AssertRCReturn(rc, rc);
838 if (uSavedMaxApicMode != (uint32_t)pApic->enmMaxMode)
839 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u config=%u"),
840 uSavedMaxApicMode, pApic->enmMaxMode);
841 return VINF_SUCCESS;
842}
843
844
845/**
846 * Worker for loading per-VCPU APIC data for legacy (old) saved-states.
847 *
848 * @returns VBox status code.
849 * @param pDevIns The device instance.
850 * @param pVCpu The cross context virtual CPU structure.
851 * @param pSSM The SSM handle.
852 * @param uVersion Data layout version.
853 */
854static int apicR3LoadLegacyVCpuData(PPDMDEVINS pDevIns, PVMCPU pVCpu, PSSMHANDLE pSSM, uint32_t uVersion)
855{
856 AssertReturn(uVersion <= APIC_SAVED_STATE_VERSION_VBOX_50, VERR_NOT_SUPPORTED);
857
858 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
859 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
860 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
861
862 uint32_t uApicBaseLo;
863 int rc = pHlp->pfnSSMGetU32(pSSM, &uApicBaseLo);
864 AssertRCReturn(rc, rc);
865 pApicCpu->uApicBaseMsr = uApicBaseLo;
866 Log2(("APIC%u: apicR3LoadLegacyVCpuData: uApicBaseMsr=%#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
867
868 switch (uVersion)
869 {
870 case APIC_SAVED_STATE_VERSION_VBOX_50:
871 case APIC_SAVED_STATE_VERSION_VBOX_30:
872 {
873 uint32_t uApicId, uPhysApicId, uArbId;
874 pHlp->pfnSSMGetU32(pSSM, &uApicId); pXApicPage->id.u8ApicId = uApicId;
875 pHlp->pfnSSMGetU32(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
876 pHlp->pfnSSMGetU32(pSSM, &uArbId); NOREF(uArbId); /* ArbID is & was unused. */
877 break;
878 }
879
880 case APIC_SAVED_STATE_VERSION_ANCIENT:
881 {
882 uint8_t uPhysApicId;
883 pHlp->pfnSSMGetU8(pSSM, &pXApicPage->id.u8ApicId);
884 pHlp->pfnSSMGetU8(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
885 break;
886 }
887
888 default:
889 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
890 }
891
892 uint32_t u32Tpr;
893 pHlp->pfnSSMGetU32(pSSM, &u32Tpr);
894 pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR_VALID;
895
896 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->svr.all.u32Svr);
897 pHlp->pfnSSMGetU8(pSSM, &pXApicPage->ldr.u.u8LogicalApicId);
898
899 uint8_t uDfr;
900 pHlp->pfnSSMGetU8(pSSM, &uDfr);
901 pXApicPage->dfr.u.u4Model = uDfr >> 4;
902
903 AssertCompile(RT_ELEMENTS(pXApicPage->isr.u) == 8);
904 AssertCompile(RT_ELEMENTS(pXApicPage->tmr.u) == 8);
905 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 8);
906 for (size_t i = 0; i < 8; i++)
907 {
908 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->isr.u[i].u32Reg);
909 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->tmr.u[i].u32Reg);
910 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->irr.u[i].u32Reg);
911 }
912
913 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_timer.all.u32LvtTimer);
914 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_thermal.all.u32LvtThermal);
915 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_perf.all.u32LvtPerf);
916 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_lint0.all.u32LvtLint0);
917 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_lint1.all.u32LvtLint1);
918 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_error.all.u32LvtError);
919
920 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->esr.all.u32Errors);
921 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->icr_lo.all.u32IcrLo);
922 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->icr_hi.all.u32IcrHi);
923
924 uint32_t u32TimerShift;
925 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue);
926 pHlp->pfnSSMGetU32(pSSM, &u32TimerShift);
927 /*
928 * Old implementation may have left the timer shift uninitialized until
929 * the timer configuration register was written. Unfortunately zero is
930 * also a valid timer shift value, so we're just going to ignore it
931 * completely. The shift count can always be derived from the DCR.
932 * See @bugref{8245#c98}.
933 */
934 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
935
936 pHlp->pfnSSMGetU32(pSSM, &pXApicPage->timer_icr.u32InitialCount);
937 pHlp->pfnSSMGetU64(pSSM, &pApicCpu->u64TimerInitial);
938 uint64_t uNextTS;
939 rc = pHlp->pfnSSMGetU64(pSSM, &uNextTS); AssertRCReturn(rc, rc);
940 if (uNextTS >= pApicCpu->u64TimerInitial + ((pXApicPage->timer_icr.u32InitialCount + 1) << uTimerShift))
941 pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
942
943 rc = PDMDevHlpTimerLoad(pDevIns, pApicCpu->hTimer, pSSM);
944 AssertRCReturn(rc, rc);
945 Assert(pApicCpu->uHintedTimerInitialCount == 0);
946 Assert(pApicCpu->uHintedTimerShift == 0);
947 if (PDMDevHlpTimerIsActive(pDevIns, pApicCpu->hTimer))
948 {
949 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
950 apicHintTimerFreq(pDevIns, pApicCpu, uInitialCount, uTimerShift);
951 }
952
953 return rc;
954}
955
956
957/**
958 * @copydoc FNSSMDEVSAVEEXEC
959 */
960static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
961{
962 PVM pVM = PDMDevHlpGetVM(pDevIns);
963 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
964
965 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
966
967 LogFlow(("APIC: apicR3SaveExec\n"));
968
969 /* Save per-VM data. */
970 int rc = apicR3SaveVMData(pDevIns, pVM, pSSM);
971 AssertRCReturn(rc, rc);
972
973 /* Save per-VCPU data.*/
974 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
975 {
976 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
977 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
978
979 /* Update interrupts from the pending-interrupts bitmaps to the IRR. */
980 APICUpdatePendingInterrupts(pVCpu);
981
982 /* Save the auxiliary data. */
983 pHlp->pfnSSMPutU64(pSSM, pApicCpu->uApicBaseMsr);
984 pHlp->pfnSSMPutU32(pSSM, pApicCpu->uEsrInternal);
985
986 /* Save the APIC page. */
987 if (XAPIC_IN_X2APIC_MODE(pVCpu))
988 pHlp->pfnSSMPutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
989 else
990 pHlp->pfnSSMPutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
991
992 /* Save the timer. */
993 pHlp->pfnSSMPutU64(pSSM, pApicCpu->u64TimerInitial);
994 PDMDevHlpTimerSave(pDevIns, pApicCpu->hTimer, pSSM);
995
996 /* Save the LINT0, LINT1 interrupt line states. */
997 pHlp->pfnSSMPutBool(pSSM, pApicCpu->fActiveLint0);
998 pHlp->pfnSSMPutBool(pSSM, pApicCpu->fActiveLint1);
999
1000#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1001 apicR3DumpState(pVCpu, "Saved state", APIC_SAVED_STATE_VERSION);
1002#endif
1003 }
1004
1005#ifdef APIC_FUZZY_SSM_COMPAT_TEST
1006 /* The state is fuzzy, don't even bother trying to load the guest. */
1007 return VERR_INVALID_STATE;
1008#else
1009 return rc;
1010#endif
1011}
1012
1013
1014/**
1015 * @copydoc FNSSMDEVLOADEXEC
1016 */
1017static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1018{
1019 PVM pVM = PDMDevHlpGetVM(pDevIns);
1020 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1021
1022 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1023 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
1024
1025 LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1026
1027 /* Weed out invalid versions. */
1028 if ( uVersion != APIC_SAVED_STATE_VERSION
1029 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_51_BETA2
1030 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
1031 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
1032 && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
1033 {
1034 LogRel(("APIC: apicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1035 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1036 }
1037
1038 int rc = VINF_SUCCESS;
1039 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
1040 {
1041 rc = apicR3LoadVMData(pDevIns, pVM, pSSM);
1042 AssertRCReturn(rc, rc);
1043
1044 if (uVersion == APIC_SAVED_STATE_VERSION)
1045 { /* Load any new additional per-VM data. */ }
1046 }
1047
1048 /*
1049 * Restore per CPU state.
1050 *
1051 * Note! PDM will restore the VMCPU_FF_INTERRUPT_APIC flag for us.
1052 * This code doesn't touch it. No devices should make us touch
1053 * it later during the restore either, only during the 'done' phase.
1054 */
1055 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1056 {
1057 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1058 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1059
1060 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_50)
1061 {
1062 /* Load the auxiliary data. */
1063 pHlp->pfnSSMGetU64V(pSSM, &pApicCpu->uApicBaseMsr);
1064 pHlp->pfnSSMGetU32(pSSM, &pApicCpu->uEsrInternal);
1065
1066 /* Load the APIC page. */
1067 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1068 pHlp->pfnSSMGetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1069 else
1070 pHlp->pfnSSMGetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1071
1072 /* Load the timer. */
1073 rc = pHlp->pfnSSMGetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
1074 rc = PDMDevHlpTimerLoad(pDevIns, pApicCpu->hTimer, pSSM); AssertRCReturn(rc, rc);
1075 Assert(pApicCpu->uHintedTimerShift == 0);
1076 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1077 if (PDMDevHlpTimerIsActive(pDevIns, pApicCpu->hTimer))
1078 {
1079 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1080 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1081 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1082 apicHintTimerFreq(pDevIns, pApicCpu, uInitialCount, uTimerShift);
1083 }
1084
1085 /* Load the LINT0, LINT1 interrupt line states. */
1086 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_51_BETA2)
1087 {
1088 pHlp->pfnSSMGetBoolV(pSSM, &pApicCpu->fActiveLint0);
1089 pHlp->pfnSSMGetBoolV(pSSM, &pApicCpu->fActiveLint1);
1090 }
1091 }
1092 else
1093 {
1094 rc = apicR3LoadLegacyVCpuData(pDevIns, pVCpu, pSSM, uVersion);
1095 AssertRCReturn(rc, rc);
1096 }
1097
1098 /*
1099 * Check that we're still good wrt restored data, then tell CPUM about the current CPUID[1].EDX[9] visibility.
1100 */
1101 rc = pHlp->pfnSSMHandleGetStatus(pSSM);
1102 AssertRCReturn(rc, rc);
1103 CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN));
1104
1105#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1106 apicR3DumpState(pVCpu, "Loaded state", uVersion);
1107#endif
1108 }
1109
1110 return rc;
1111}
1112
1113
1114/**
1115 * @callback_method_impl{FNTMTIMERDEV}
1116 *
1117 * @note pvUser points to the VMCPU.
1118 *
1119 * @remarks Currently this function is invoked on the last EMT, see @c
1120 * idTimerCpu in tmR3TimerCallback(). However, the code does -not-
1121 * rely on this and is designed to work with being invoked on any
1122 * thread.
1123 */
1124static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1125{
1126 PVMCPU pVCpu = (PVMCPU)pvUser;
1127 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1128 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pApicCpu->hTimer));
1129 Assert(pVCpu);
1130 LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
1131 RT_NOREF(pDevIns, hTimer, pApicCpu);
1132
1133 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1134 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
1135#ifdef VBOX_WITH_STATISTICS
1136 STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
1137#endif
1138 if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
1139 {
1140 uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
1141 Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
1142 apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE, 0 /* uSrcTag */);
1143 }
1144
1145 XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
1146 switch (enmTimerMode)
1147 {
1148 case XAPICTIMERMODE_PERIODIC:
1149 {
1150 /* The initial-count register determines if the periodic timer is re-armed. */
1151 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1152 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1153 if (uInitialCount)
1154 {
1155 Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1156 apicStartTimer(pVCpu, uInitialCount);
1157 }
1158 break;
1159 }
1160
1161 case XAPICTIMERMODE_ONESHOT:
1162 {
1163 pXApicPage->timer_ccr.u32CurrentCount = 0;
1164 break;
1165 }
1166
1167 case XAPICTIMERMODE_TSC_DEADLINE:
1168 {
1169 /** @todo implement TSC deadline. */
1170 AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
1171 break;
1172 }
1173 }
1174}
1175
1176
1177/**
1178 * @interface_method_impl{PDMDEVREG,pfnReset}
1179 */
1180DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
1181{
1182 PVM pVM = PDMDevHlpGetVM(pDevIns);
1183 VM_ASSERT_EMT0(pVM);
1184 VM_ASSERT_IS_NOT_RUNNING(pVM);
1185
1186 LogFlow(("APIC: apicR3Reset\n"));
1187
1188 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1189 {
1190 PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
1191 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
1192
1193 if (PDMDevHlpTimerIsActive(pDevIns, pApicCpu->hTimer))
1194 PDMDevHlpTimerStop(pDevIns, pApicCpu->hTimer);
1195
1196 apicResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
1197
1198 /* Clear the interrupt pending force flag. */
1199 apicClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
1200 }
1201}
1202
1203
1204/**
1205 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1206 */
1207DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1208{
1209 RT_NOREF(pDevIns, offDelta);
1210}
1211
1212
1213/**
1214 * Terminates the APIC state.
1215 *
1216 * @param pVM The cross context VM structure.
1217 */
1218static void apicR3TermState(PVM pVM)
1219{
1220 PAPIC pApic = VM_TO_APIC(pVM);
1221 LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
1222
1223 /* Unmap and free the PIB. */
1224 if (pApic->pvApicPibR3 != NIL_RTR3PTR)
1225 {
1226 size_t const cPages = pApic->cbApicPib >> HOST_PAGE_SHIFT;
1227 if (cPages == 1)
1228 SUPR3PageFreeEx(pApic->pvApicPibR3, cPages);
1229 else
1230 SUPR3ContFree(pApic->pvApicPibR3, cPages);
1231 pApic->pvApicPibR3 = NIL_RTR3PTR;
1232 pApic->pvApicPibR0 = NIL_RTR0PTR;
1233 }
1234
1235 /* Unmap and free the virtual-APIC pages. */
1236 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1237 {
1238 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1239 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1240
1241 pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
1242 pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
1243
1244 if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
1245 {
1246 SUPR3PageFreeEx(pApicCpu->pvApicPageR3, 1 /* cPages */);
1247 pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
1248 pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
1249 }
1250 }
1251}
1252
1253
1254/**
1255 * Initializes the APIC state.
1256 *
1257 * @returns VBox status code.
1258 * @param pVM The cross context VM structure.
1259 */
1260static int apicR3InitState(PVM pVM)
1261{
1262 PAPIC pApic = VM_TO_APIC(pVM);
1263 LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
1264
1265 /*
1266 * Allocate and map the pending-interrupt bitmap (PIB).
1267 *
1268 * We allocate all the VCPUs' PIBs contiguously in order to save space as
1269 * physically contiguous allocations are rounded to a multiple of page size.
1270 */
1271 Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
1272 Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
1273 pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), HOST_PAGE_SIZE);
1274 size_t const cHostPages = pApic->cbApicPib >> HOST_PAGE_SHIFT;
1275 if (cHostPages == 1)
1276 {
1277 SUPPAGE SupApicPib;
1278 RT_ZERO(SupApicPib);
1279 SupApicPib.Phys = NIL_RTHCPHYS;
1280 int rc = SUPR3PageAllocEx(1 /* cHostPages */, 0 /* fFlags */, &pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
1281 if (RT_SUCCESS(rc))
1282 {
1283 pApic->HCPhysApicPib = SupApicPib.Phys;
1284 AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
1285 }
1286 else
1287 {
1288 LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
1289 return rc;
1290 }
1291 }
1292 else
1293 pApic->pvApicPibR3 = SUPR3ContAlloc(cHostPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
1294
1295 if (pApic->pvApicPibR3)
1296 {
1297 bool const fDriverless = SUPR3IsDriverless();
1298 AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR || fDriverless, VERR_INTERNAL_ERROR);
1299 AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS || fDriverless, VERR_INTERNAL_ERROR);
1300
1301 /* Initialize the PIB. */
1302 RT_BZERO(pApic->pvApicPibR3, pApic->cbApicPib);
1303
1304 /*
1305 * Allocate the map the virtual-APIC pages.
1306 */
1307 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1308 {
1309 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1310 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1311
1312 SUPPAGE SupApicPage;
1313 RT_ZERO(SupApicPage);
1314 SupApicPage.Phys = NIL_RTHCPHYS;
1315
1316 Assert(pVCpu->idCpu == idCpu);
1317 Assert(pApicCpu->pvApicPageR3 == NIL_RTR3PTR);
1318 Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
1319 AssertCompile(sizeof(XAPICPAGE) <= HOST_PAGE_SIZE);
1320 pApicCpu->cbApicPage = sizeof(XAPICPAGE);
1321 int rc = SUPR3PageAllocEx(1 /* cHostPages */, 0 /* fFlags */, &pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
1322 &SupApicPage);
1323 if (RT_SUCCESS(rc))
1324 {
1325 AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR || fDriverless, VERR_INTERNAL_ERROR);
1326 pApicCpu->HCPhysApicPage = SupApicPage.Phys;
1327 AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS || fDriverless, VERR_INTERNAL_ERROR);
1328
1329 /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
1330 uint32_t const offApicPib = idCpu * sizeof(APICPIB);
1331 pApicCpu->pvApicPibR0 = !fDriverless ? (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib) : NIL_RTR0PTR;
1332 pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
1333
1334 /* Initialize the virtual-APIC state. */
1335 RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
1336 apicResetCpu(pVCpu, true /* fResetApicBaseMsr */);
1337
1338#ifdef DEBUG_ramshankar
1339 Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
1340 Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR || fDriverless);
1341 Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
1342#endif
1343 }
1344 else
1345 {
1346 LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", idCpu, pApicCpu->cbApicPage, rc));
1347 apicR3TermState(pVM);
1348 return rc;
1349 }
1350 }
1351
1352#ifdef DEBUG_ramshankar
1353 Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
1354 Assert(pApic->pvApicPibR0 != NIL_RTR0PTR || fDriverless);
1355#endif
1356 return VINF_SUCCESS;
1357 }
1358
1359 LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
1360 pApic->cbApicPib));
1361 return VERR_NO_MEMORY;
1362}
1363
1364
1365/**
1366 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1367 */
1368DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
1369{
1370 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1371 PVM pVM = PDMDevHlpGetVM(pDevIns);
1372 LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
1373
1374 apicR3TermState(pVM);
1375 return VINF_SUCCESS;
1376}
1377
1378
1379/**
1380 * @interface_method_impl{PDMDEVREG,pfnInitComplete}
1381 */
1382DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
1383{
1384 PVM pVM = PDMDevHlpGetVM(pDevIns);
1385 PAPIC pApic = VM_TO_APIC(pVM);
1386
1387 /*
1388 * Init APIC settings that rely on HM and CPUM configurations.
1389 */
1390 CPUMCPUIDLEAF CpuLeaf;
1391 int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
1392 AssertRCReturn(rc, rc);
1393
1394 pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
1395 pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
1396 pApic->fVirtApicRegsEnabled = HMR3AreVirtApicRegsEnabled(pVM->pUVM);
1397
1398 LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
1399 pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
1400
1401 return VINF_SUCCESS;
1402}
1403
1404
1405/**
1406 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1407 */
1408DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1409{
1410 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1411 PAPICDEV pApicDev = PDMDEVINS_2_DATA(pDevIns, PAPICDEV);
1412 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1413 PVM pVM = PDMDevHlpGetVM(pDevIns);
1414 PAPIC pApic = VM_TO_APIC(pVM);
1415 Assert(iInstance == 0); NOREF(iInstance);
1416
1417 /*
1418 * Init the data.
1419 */
1420 pApic->pDevInsR3 = pDevIns;
1421 pApic->fR0Enabled = pDevIns->fR0Enabled;
1422 pApic->fRCEnabled = pDevIns->fRCEnabled;
1423
1424 /*
1425 * Validate APIC settings.
1426 */
1427 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Mode|IOAPIC|NumCPUs|MacOSWorkaround", "");
1428
1429 /** @devcfgm{apic, IOAPIC, bool, true}
1430 * Indicates whether an I/O APIC is present in the system. */
1431 int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
1432 AssertLogRelRCReturn(rc, rc);
1433
1434 /** @devcfgm{apic, Mode, PDMAPICMODE, APIC(2)}
1435 * Max APIC feature level. */
1436 uint8_t uMaxMode;
1437 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Mode", &uMaxMode, PDMAPICMODE_APIC);
1438 AssertLogRelRCReturn(rc, rc);
1439 switch ((PDMAPICMODE)uMaxMode)
1440 {
1441 case PDMAPICMODE_NONE:
1442 LogRel(("APIC: APIC maximum mode configured as 'None', effectively disabled/not-present!\n"));
1443 case PDMAPICMODE_APIC:
1444 case PDMAPICMODE_X2APIC:
1445 break;
1446 default:
1447 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %d unknown.", uMaxMode);
1448 }
1449 pApic->enmMaxMode = (PDMAPICMODE)uMaxMode;
1450
1451 /** @devcfgm{apic, MacOSWorkaround, bool, false}
1452 * Enables a workaround for incorrect MSR_IA32_X2APIC_ID handling in macOS.
1453 *
1454 * Vital code in osfmk/i386/i386_init.c's vstart() routine incorrectly applies a
1455 * 24 right shift to the ID register value (correct for legacy APIC, but
1456 * entirely wrong for x2APIC), with the consequence that all CPUs use the same
1457 * per-cpu data and things panic pretty quickly. There are some shifty ID
1458 * reads in lapic_native.c too, but they are for either harmless (assuming boot
1459 * CPU has ID 0) or are for logging/debugging purposes only. */
1460 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "MacOSWorkaround", &pApic->fMacOSWorkaround, false);
1461 AssertLogRelRCReturn(rc, rc);
1462
1463 /*
1464 * Disable automatic PDM locking for this device.
1465 */
1466 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1467 AssertRCReturn(rc, rc);
1468
1469 /*
1470 * Register the APIC with PDM.
1471 */
1472 rc = PDMDevHlpApicRegister(pDevIns);
1473 AssertLogRelRCReturn(rc, rc);
1474
1475 /*
1476 * Initialize the APIC state.
1477 */
1478 if (pApic->enmMaxMode == PDMAPICMODE_X2APIC)
1479 {
1480 rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
1481 AssertLogRelRCReturn(rc, rc);
1482 }
1483 else
1484 {
1485 /* We currently don't have a function to remove the range, so we register an range which will cause a #GP. */
1486 rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic_Invalid);
1487 AssertLogRelRCReturn(rc, rc);
1488 }
1489
1490 /* Tell CPUM about the APIC feature level so it can adjust APICBASE MSR GP mask and CPUID bits. */
1491 apicR3SetCpuIdFeatureLevel(pVM, pApic->enmMaxMode);
1492
1493 /* Finally, initialize the state. */
1494 rc = apicR3InitState(pVM);
1495 AssertRCReturn(rc, rc);
1496
1497 /*
1498 * Register the MMIO range.
1499 */
1500 PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(pVM->apCpusR3[0]);
1501 RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr);
1502
1503 rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), apicWriteMmio, apicReadMmio,
1504 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "APIC", &pApicDev->hMmio);
1505 AssertRCReturn(rc, rc);
1506
1507 /*
1508 * Create the APIC timers.
1509 */
1510 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1511 {
1512 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1513 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1514 RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
1515 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu,
1516 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, pApicCpu->szTimerDesc, &pApicCpu->hTimer);
1517 AssertRCReturn(rc, rc);
1518 }
1519
1520 /*
1521 * Register saved state callbacks.
1522 */
1523 rc = PDMDevHlpSSMRegister(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pApicDev), apicR3SaveExec, apicR3LoadExec);
1524 AssertRCReturn(rc, rc);
1525
1526 /*
1527 * Register debugger info callbacks.
1528 *
1529 * We use separate callbacks rather than arguments so they can also be
1530 * dumped in an automated fashion while collecting crash diagnostics and
1531 * not just used during live debugging via the VM debugger.
1532 */
1533 DBGFR3InfoRegisterInternalEx(pVM, "apic", "Dumps APIC basic information.", apicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
1534 DBGFR3InfoRegisterInternalEx(pVM, "apiclvt", "Dumps APIC LVT information.", apicR3InfoLvt, DBGFINFO_FLAGS_ALL_EMTS);
1535 DBGFR3InfoRegisterInternalEx(pVM, "apictimer", "Dumps APIC timer information.", apicR3InfoTimer, DBGFINFO_FLAGS_ALL_EMTS);
1536
1537 /*
1538 * Statistics.
1539 */
1540#define APIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
1541 PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, \
1542 STAMUNIT_OCCURENCES, a_pszDesc, a_pszNameFmt, idCpu)
1543#define APIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
1544 PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, \
1545 STAMUNIT_TICKS_PER_CALL, a_pszDesc, a_pszNameFmt, idCpu)
1546
1547 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1548 {
1549 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1550 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1551
1552 APIC_REG_COUNTER(&pApicCpu->StatPostIntrCnt, "%u", "APIC/VCPU stats / number of apicPostInterrupt calls.");
1553 for (size_t i = 0; i < RT_ELEMENTS(pApicCpu->aStatVectors); i++)
1554 PDMDevHlpSTAMRegisterF(pDevIns, &pApicCpu->aStatVectors[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1555 "Number of APICPostInterrupt calls for the vector.", "%u/Vectors/%02x", idCpu, i);
1556
1557#ifdef VBOX_WITH_STATISTICS
1558 APIC_REG_COUNTER(&pApicCpu->StatMmioReadRZ, "%u/RZ/MmioRead", "Number of APIC MMIO reads in RZ.");
1559 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRZ, "%u/RZ/MmioWrite", "Number of APIC MMIO writes in RZ.");
1560 APIC_REG_COUNTER(&pApicCpu->StatMsrReadRZ, "%u/RZ/MsrRead", "Number of APIC MSR reads in RZ.");
1561 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRZ, "%u/RZ/MsrWrite", "Number of APIC MSR writes in RZ.");
1562
1563 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "%u/R3/MmioRead", "Number of APIC MMIO reads in R3.");
1564 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "%u/R3/MmioWrite", "Number of APIC MMIO writes in R3.");
1565 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "%u/R3/MsrRead", "Number of APIC MSR reads in R3.");
1566 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "%u/R3/MsrWrite", "Number of APIC MSR writes in R3.");
1567
1568 APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending,
1569 "%u/PostInterruptAlreadyPending", "Number of times an interrupt is already pending.");
1570 APIC_REG_COUNTER(&pApicCpu->StatTimerCallback, "%u/TimerCallback", "Number of times the timer callback is invoked.");
1571
1572 APIC_REG_COUNTER(&pApicCpu->StatTprWrite, "%u/TprWrite", "Number of TPR writes.");
1573 APIC_REG_COUNTER(&pApicCpu->StatTprRead, "%u/TprRead", "Number of TPR reads.");
1574 APIC_REG_COUNTER(&pApicCpu->StatEoiWrite, "%u/EoiWrite", "Number of EOI writes.");
1575 APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr, "%u/MaskedByTpr", "Number of times TPR masks an interrupt in apicGetInterrupt.");
1576 APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr, "%u/MaskedByPpr", "Number of times PPR masks an interrupt in apicGetInterrupt.");
1577 APIC_REG_COUNTER(&pApicCpu->StatTimerIcrWrite, "%u/TimerIcrWrite", "Number of times the timer ICR is written.");
1578 APIC_REG_COUNTER(&pApicCpu->StatIcrLoWrite, "%u/IcrLoWrite", "Number of times the ICR Lo (send IPI) is written.");
1579 APIC_REG_COUNTER(&pApicCpu->StatIcrHiWrite, "%u/IcrHiWrite", "Number of times the ICR Hi is written.");
1580 APIC_REG_COUNTER(&pApicCpu->StatIcrFullWrite, "%u/IcrFullWrite", "Number of times the ICR full (send IPI, x2APIC) is written.");
1581 APIC_REG_COUNTER(&pApicCpu->StatIdMsrRead, "%u/IdMsrRead", "Number of times the APIC-ID MSR is read.");
1582 APIC_REG_COUNTER(&pApicCpu->StatDcrWrite, "%u/DcrWrite", "Number of times the DCR is written.");
1583 APIC_REG_COUNTER(&pApicCpu->StatDfrWrite, "%u/DfrWrite", "Number of times the DFR is written.");
1584 APIC_REG_COUNTER(&pApicCpu->StatLdrWrite, "%u/LdrWrite", "Number of times the LDR is written.");
1585 APIC_REG_COUNTER(&pApicCpu->StatLvtTimerWrite, "%u/LvtTimerWrite", "Number of times the LVT timer is written.");
1586
1587 APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs,
1588 "/PROF/CPU%u/APIC/UpdatePendingInterrupts", "Profiling of APICUpdatePendingInterrupts");
1589 APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "/PROF/CPU%u/APIC/PostInterrupt", "Profiling of APICPostInterrupt");
1590#endif
1591 }
1592
1593# undef APIC_PROF_COUNTER
1594# undef APIC_REG_ACCESS_COUNTER
1595
1596 return VINF_SUCCESS;
1597}
1598
1599#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1600
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