[60307] | 1 | /* $Id: APIC.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
|
---|
| 2 | /** @file
|
---|
| 3 | * APIC - Advanced Programmable Interrupt Controller.
|
---|
| 4 | */
|
---|
| 5 |
|
---|
| 6 | /*
|
---|
[82968] | 7 | * Copyright (C) 2016-2020 Oracle Corporation
|
---|
[60307] | 8 | *
|
---|
| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
|
---|
| 10 | * available from http://www.virtualbox.org. This file is free software;
|
---|
| 11 | * you can redistribute it and/or modify it under the terms of the GNU
|
---|
| 12 | * General Public License (GPL) as published by the Free Software
|
---|
| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
|
---|
| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
|
---|
| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
|
---|
| 16 | */
|
---|
| 17 |
|
---|
| 18 |
|
---|
| 19 | /*********************************************************************************************************************************
|
---|
| 20 | * Header Files *
|
---|
| 21 | *********************************************************************************************************************************/
|
---|
| 22 | #define LOG_GROUP LOG_GROUP_DEV_APIC
|
---|
| 23 | #include <VBox/log.h>
|
---|
| 24 | #include "APICInternal.h"
|
---|
| 25 | #include <VBox/vmm/cpum.h>
|
---|
| 26 | #include <VBox/vmm/hm.h>
|
---|
| 27 | #include <VBox/vmm/mm.h>
|
---|
| 28 | #include <VBox/vmm/pdmdev.h>
|
---|
| 29 | #include <VBox/vmm/ssm.h>
|
---|
| 30 | #include <VBox/vmm/vm.h>
|
---|
| 31 |
|
---|
| 32 |
|
---|
| 33 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
|
---|
[62460] | 34 |
|
---|
| 35 |
|
---|
[60307] | 36 | /*********************************************************************************************************************************
|
---|
| 37 | * Defined Constants And Macros *
|
---|
| 38 | *********************************************************************************************************************************/
|
---|
| 39 | /** The current APIC saved state version. */
|
---|
[61584] | 40 | #define APIC_SAVED_STATE_VERSION 5
|
---|
| 41 | /** VirtualBox 5.1 beta2 - pre fActiveLintX. */
|
---|
| 42 | #define APIC_SAVED_STATE_VERSION_VBOX_51_BETA2 4
|
---|
[60307] | 43 | /** The saved state version used by VirtualBox 5.0 and
|
---|
| 44 | * earlier. */
|
---|
[61584] | 45 | #define APIC_SAVED_STATE_VERSION_VBOX_50 3
|
---|
[60307] | 46 | /** The saved state version used by VirtualBox v3 and earlier.
|
---|
| 47 | * This does not include the config. */
|
---|
[61584] | 48 | #define APIC_SAVED_STATE_VERSION_VBOX_30 2
|
---|
[60307] | 49 | /** Some ancient version... */
|
---|
[61584] | 50 | #define APIC_SAVED_STATE_VERSION_ANCIENT 1
|
---|
[60307] | 51 |
|
---|
[61608] | 52 | #ifdef VBOX_WITH_STATISTICS
|
---|
| 53 | # define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
|
---|
| 54 | { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
|
---|
[63944] | 55 | # define X2APIC_MSRRANGE_INVALID(a_uFirst, a_uLast, a_szName) \
|
---|
| 56 | { (a_uFirst), (a_uLast), kCpumMsrRdFn_WriteOnly, kCpumMsrWrFn_ReadOnly, 0, 0, 0, 0, UINT64_MAX /*fWrGpMask*/, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
|
---|
[61608] | 57 | #else
|
---|
| 58 | # define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
|
---|
| 59 | { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName }
|
---|
[63944] | 60 | # define X2APIC_MSRRANGE_INVALID(a_uFirst, a_uLast, a_szName) \
|
---|
| 61 | { (a_uFirst), (a_uLast), kCpumMsrRdFn_WriteOnly, kCpumMsrWrFn_ReadOnly, 0, 0, 0, 0, UINT64_MAX /*fWrGpMask*/, a_szName }
|
---|
[61608] | 62 | #endif
|
---|
[60307] | 63 |
|
---|
[61608] | 64 |
|
---|
[60307] | 65 | /*********************************************************************************************************************************
|
---|
| 66 | * Global Variables *
|
---|
| 67 | *********************************************************************************************************************************/
|
---|
[61608] | 68 | /**
|
---|
[61744] | 69 | * MSR range supported by the x2APIC.
|
---|
| 70 | * See Intel spec. 10.12.2 "x2APIC Register Availability".
|
---|
[61608] | 71 | */
|
---|
[61744] | 72 | static CPUMMSRRANGE const g_MsrRange_x2Apic = X2APIC_MSRRANGE(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range");
|
---|
[63944] | 73 | static CPUMMSRRANGE const g_MsrRange_x2Apic_Invalid = X2APIC_MSRRANGE_INVALID(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range invalid");
|
---|
[61608] | 74 | #undef X2APIC_MSRRANGE
|
---|
[63944] | 75 | #undef X2APIC_MSRRANGE_GP
|
---|
[61608] | 76 |
|
---|
[60307] | 77 | /** Saved state field descriptors for XAPICPAGE. */
|
---|
| 78 | static const SSMFIELD g_aXApicPageFields[] =
|
---|
| 79 | {
|
---|
| 80 | SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
|
---|
| 81 | SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
|
---|
| 82 | SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
|
---|
| 83 | SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
|
---|
| 84 | SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
|
---|
| 85 | SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
|
---|
| 86 | SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
|
---|
| 87 | SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
|
---|
| 88 | SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
|
---|
| 89 | SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
|
---|
| 90 | SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
|
---|
| 91 | SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
|
---|
| 92 | SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
|
---|
| 93 | SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
|
---|
| 94 | SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
|
---|
| 95 | SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
|
---|
| 96 | SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
|
---|
| 97 | SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
|
---|
| 98 | SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
|
---|
| 99 | SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
|
---|
| 100 | SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
|
---|
| 101 | SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
|
---|
| 102 | SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
|
---|
| 103 | SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
|
---|
| 104 | SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
|
---|
| 105 | SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
|
---|
| 106 | SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
|
---|
| 107 | SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
|
---|
| 108 | SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
|
---|
| 109 | SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
|
---|
| 110 | SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
|
---|
| 111 | SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
|
---|
| 112 | SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
|
---|
| 113 | SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
|
---|
| 114 | SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
|
---|
| 115 | SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
|
---|
| 116 | SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
|
---|
| 117 | SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
|
---|
| 118 | SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
|
---|
| 119 | SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
|
---|
| 120 | SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
|
---|
| 121 | SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
|
---|
| 122 | SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
|
---|
| 123 | SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
|
---|
| 124 | SSMFIELD_ENTRY_TERM()
|
---|
| 125 | };
|
---|
| 126 |
|
---|
| 127 | /** Saved state field descriptors for X2APICPAGE. */
|
---|
| 128 | static const SSMFIELD g_aX2ApicPageFields[] =
|
---|
| 129 | {
|
---|
| 130 | SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
|
---|
| 131 | SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
|
---|
| 132 | SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
|
---|
| 133 | SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
|
---|
| 134 | SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
|
---|
| 135 | SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
|
---|
| 136 | SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
|
---|
| 137 | SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
|
---|
| 138 | SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
|
---|
| 139 | SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
|
---|
| 140 | SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
|
---|
| 141 | SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
|
---|
| 142 | SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
|
---|
| 143 | SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
|
---|
| 144 | SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
|
---|
| 145 | SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
|
---|
| 146 | SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
|
---|
| 147 | SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
|
---|
| 148 | SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
|
---|
| 149 | SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
|
---|
| 150 | SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
|
---|
| 151 | SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
|
---|
| 152 | SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
|
---|
| 153 | SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
|
---|
| 154 | SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
|
---|
| 155 | SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
|
---|
| 156 | SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
|
---|
| 157 | SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
|
---|
| 158 | SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
|
---|
| 159 | SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
|
---|
| 160 | SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
|
---|
| 161 | SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
|
---|
| 162 | SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
|
---|
| 163 | SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
|
---|
| 164 | SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
|
---|
| 165 | SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
|
---|
| 166 | SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
|
---|
| 167 | SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
|
---|
| 168 | SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
|
---|
| 169 | SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
|
---|
| 170 | SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
|
---|
| 171 | SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
|
---|
| 172 | SSMFIELD_ENTRY_TERM()
|
---|
| 173 | };
|
---|
| 174 |
|
---|
| 175 |
|
---|
| 176 | /**
|
---|
[64596] | 177 | * Sets the CPUID feature bits for the APIC mode.
|
---|
| 178 | *
|
---|
| 179 | * @param pVM The cross context VM structure.
|
---|
| 180 | * @param enmMode The APIC mode.
|
---|
| 181 | */
|
---|
| 182 | static void apicR3SetCpuIdFeatureLevel(PVM pVM, PDMAPICMODE enmMode)
|
---|
| 183 | {
|
---|
| 184 | switch (enmMode)
|
---|
| 185 | {
|
---|
| 186 | case PDMAPICMODE_NONE:
|
---|
| 187 | CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
|
---|
| 188 | CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
|
---|
| 189 | break;
|
---|
| 190 |
|
---|
| 191 | case PDMAPICMODE_APIC:
|
---|
| 192 | CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
|
---|
| 193 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
|
---|
| 194 | break;
|
---|
| 195 |
|
---|
| 196 | case PDMAPICMODE_X2APIC:
|
---|
| 197 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
|
---|
| 198 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
|
---|
| 199 | break;
|
---|
| 200 |
|
---|
| 201 | default:
|
---|
| 202 | AssertMsgFailed(("Unknown/invalid APIC mode: %d\n", (int)enmMode));
|
---|
| 203 | }
|
---|
| 204 | }
|
---|
| 205 |
|
---|
| 206 |
|
---|
| 207 | /**
|
---|
[60307] | 208 | * Receives an INIT IPI.
|
---|
| 209 | *
|
---|
| 210 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 211 | */
|
---|
| 212 | VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
|
---|
| 213 | {
|
---|
| 214 | VMCPU_ASSERT_EMT(pVCpu);
|
---|
[60459] | 215 | LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
|
---|
[73281] | 216 | apicInitIpi(pVCpu);
|
---|
[60307] | 217 | }
|
---|
| 218 |
|
---|
| 219 |
|
---|
| 220 | /**
|
---|
[63888] | 221 | * Sets whether Hyper-V compatibility mode (MSR interface) is enabled or not.
|
---|
[63632] | 222 | *
|
---|
[63907] | 223 | * This mode is a hybrid of xAPIC and x2APIC modes, some caveats:
|
---|
| 224 | * 1. MSRs are used even ones that are missing (illegal) in x2APIC like DFR.
|
---|
| 225 | * 2. A single ICR is used by the guest to send IPIs rather than 2 ICR writes.
|
---|
| 226 | * 3. It is unclear what the behaviour will be when invalid bits are set,
|
---|
| 227 | * currently we follow x2APIC behaviour of causing a \#GP.
|
---|
| 228 | *
|
---|
[63632] | 229 | * @param pVM The cross context VM structure.
|
---|
| 230 | * @param fHyperVCompatMode Whether the compatibility mode is enabled.
|
---|
| 231 | */
|
---|
| 232 | VMMR3_INT_DECL(void) APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode)
|
---|
| 233 | {
|
---|
| 234 | Assert(pVM);
|
---|
| 235 | PAPIC pApic = VM_TO_APIC(pVM);
|
---|
| 236 | pApic->fHyperVCompatMode = fHyperVCompatMode;
|
---|
[63888] | 237 |
|
---|
[71280] | 238 | if (fHyperVCompatMode)
|
---|
| 239 | LogRel(("APIC: Enabling Hyper-V x2APIC compatibility mode\n"));
|
---|
| 240 |
|
---|
[63888] | 241 | int rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
|
---|
[63908] | 242 | AssertLogRelRC(rc);
|
---|
[63632] | 243 | }
|
---|
| 244 |
|
---|
| 245 |
|
---|
| 246 | /**
|
---|
[60307] | 247 | * Helper for dumping an APIC 256-bit sparse register.
|
---|
| 248 | *
|
---|
| 249 | * @param pApicReg The APIC 256-bit spare register.
|
---|
| 250 | * @param pHlp The debug output helper.
|
---|
| 251 | */
|
---|
| 252 | static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
|
---|
| 253 | {
|
---|
| 254 | ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
|
---|
| 255 | unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
|
---|
| 256 | XAPIC256BITREG ApicReg;
|
---|
| 257 | RT_ZERO(ApicReg);
|
---|
| 258 |
|
---|
| 259 | pHlp->pfnPrintf(pHlp, " ");
|
---|
| 260 | for (ssize_t i = cFragments - 1; i >= 0; i--)
|
---|
| 261 | {
|
---|
| 262 | uint32_t const uFragment = pApicReg->u[i].u32Reg;
|
---|
| 263 | ApicReg.u[i].u32Reg = uFragment;
|
---|
| 264 | pHlp->pfnPrintf(pHlp, "%08x", uFragment);
|
---|
| 265 | }
|
---|
| 266 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
| 267 |
|
---|
[60689] | 268 | uint32_t cPending = 0;
|
---|
[60746] | 269 | pHlp->pfnPrintf(pHlp, " Pending:");
|
---|
[60307] | 270 | for (ssize_t i = cFragments - 1; i >= 0; i--)
|
---|
| 271 | {
|
---|
| 272 | uint32_t uFragment = ApicReg.u[i].u32Reg;
|
---|
| 273 | if (uFragment)
|
---|
| 274 | {
|
---|
| 275 | do
|
---|
| 276 | {
|
---|
| 277 | unsigned idxSetBit = ASMBitLastSetU32(uFragment);
|
---|
| 278 | --idxSetBit;
|
---|
| 279 | ASMBitClear(&uFragment, idxSetBit);
|
---|
| 280 |
|
---|
| 281 | idxSetBit += (i * cBitsPerFragment);
|
---|
[60746] | 282 | pHlp->pfnPrintf(pHlp, " %#02x", idxSetBit);
|
---|
[60307] | 283 | ++cPending;
|
---|
| 284 | } while (uFragment);
|
---|
| 285 | }
|
---|
| 286 | }
|
---|
| 287 | if (!cPending)
|
---|
| 288 | pHlp->pfnPrintf(pHlp, " None");
|
---|
| 289 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
| 290 | }
|
---|
| 291 |
|
---|
| 292 |
|
---|
| 293 | /**
|
---|
[60746] | 294 | * Helper for dumping an APIC pending-interrupt bitmap.
|
---|
| 295 | *
|
---|
| 296 | * @param pApicPib The pending-interrupt bitmap.
|
---|
| 297 | * @param pHlp The debug output helper.
|
---|
| 298 | */
|
---|
| 299 | static void apicR3DbgInfoPib(PCAPICPIB pApicPib, PCDBGFINFOHLP pHlp)
|
---|
| 300 | {
|
---|
| 301 | /* Copy the pending-interrupt bitmap as an APIC 256-bit sparse register. */
|
---|
| 302 | XAPIC256BITREG ApicReg;
|
---|
| 303 | RT_ZERO(ApicReg);
|
---|
| 304 | ssize_t const cFragmentsDst = RT_ELEMENTS(ApicReg.u);
|
---|
[63632] | 305 | ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->au64VectorBitmap);
|
---|
| 306 | AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->au64VectorBitmap));
|
---|
[60746] | 307 | for (ssize_t idxPib = cFragmentsSrc - 1, idxReg = cFragmentsDst - 1; idxPib >= 0; idxPib--, idxReg -= 2)
|
---|
| 308 | {
|
---|
[63632] | 309 | uint64_t const uFragment = pApicPib->au64VectorBitmap[idxPib];
|
---|
[60746] | 310 | uint32_t const uFragmentLo = RT_LO_U32(uFragment);
|
---|
| 311 | uint32_t const uFragmentHi = RT_HI_U32(uFragment);
|
---|
| 312 | ApicReg.u[idxReg].u32Reg = uFragmentHi;
|
---|
| 313 | ApicReg.u[idxReg - 1].u32Reg = uFragmentLo;
|
---|
| 314 | }
|
---|
| 315 |
|
---|
| 316 | /* Dump it. */
|
---|
| 317 | apicR3DbgInfo256BitReg(&ApicReg, pHlp);
|
---|
| 318 | }
|
---|
| 319 |
|
---|
| 320 |
|
---|
| 321 | /**
|
---|
[60307] | 322 | * Dumps basic APIC state.
|
---|
| 323 | *
|
---|
[61762] | 324 | * @param pVM The cross context VM structure.
|
---|
[61566] | 325 | * @param pHlp The info helpers.
|
---|
| 326 | * @param pszArgs Arguments, ignored.
|
---|
[60307] | 327 | */
|
---|
[61566] | 328 | static DECLCALLBACK(void) apicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
[60307] | 329 | {
|
---|
[61566] | 330 | NOREF(pszArgs);
|
---|
[61575] | 331 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
| 332 | if (!pVCpu)
|
---|
[80191] | 333 | pVCpu = pVM->apCpusR3[0];
|
---|
[61575] | 334 |
|
---|
[60307] | 335 | PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
| 336 | PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
|
---|
| 337 | PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
|
---|
[60646] | 338 |
|
---|
| 339 | uint64_t const uBaseMsr = pApicCpu->uApicBaseMsr;
|
---|
| 340 | APICMODE const enmMode = apicGetMode(uBaseMsr);
|
---|
[60307] | 341 | bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
|
---|
| 342 |
|
---|
[61741] | 343 | pHlp->pfnPrintf(pHlp, "APIC%u:\n", pVCpu->idCpu);
|
---|
[60646] | 344 | pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
|
---|
[61072] | 345 | MSR_IA32_APICBASE_GET_ADDR(uBaseMsr));
|
---|
[61739] | 346 | pHlp->pfnPrintf(pHlp, " Mode = %u (%s)\n", enmMode, apicGetModeName(enmMode));
|
---|
[60307] | 347 | if (fX2ApicMode)
|
---|
| 348 | {
|
---|
| 349 | pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
|
---|
| 350 | pX2ApicPage->id.u32ApicId);
|
---|
| 351 | }
|
---|
| 352 | else
|
---|
| 353 | pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
|
---|
| 354 | pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
|
---|
[61741] | 355 | pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
|
---|
| 356 | pHlp->pfnPrintf(pHlp, " Max LVT entry index (0..N) = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
|
---|
| 357 | pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
|
---|
[60307] | 358 | if (!fX2ApicMode)
|
---|
| 359 | pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
|
---|
| 360 | pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
|
---|
[61769] | 361 | pHlp->pfnPrintf(pHlp, " Task-priority class = %#x\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >> 4);
|
---|
[61741] | 362 | pHlp->pfnPrintf(pHlp, " Task-priority subclass = %#x\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
|
---|
[60307] | 363 | pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
|
---|
[61769] | 364 | pHlp->pfnPrintf(pHlp, " Processor-priority class = %#x\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr) >> 4);
|
---|
[61741] | 365 | pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %#x\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
|
---|
[60307] | 366 | if (!fX2ApicMode)
|
---|
| 367 | pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
|
---|
[60473] | 368 | pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
|
---|
[61741] | 369 | pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
|
---|
[60307] | 370 | : pXApicPage->ldr.u.u8LogicalApicId);
|
---|
| 371 | if (!fX2ApicMode)
|
---|
| 372 | {
|
---|
[60473] | 373 | pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
|
---|
[61741] | 374 | pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
|
---|
[60307] | 375 | apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
|
---|
| 376 | }
|
---|
[61741] | 377 | pHlp->pfnPrintf(pHlp, " SVR = %#x\n", pXApicPage->svr.all.u32Svr);
|
---|
| 378 | pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
|
---|
[60307] | 379 | pXApicPage->svr.u.u8SpuriousVector);
|
---|
[61741] | 380 | pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
|
---|
| 381 | pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
|
---|
[60307] | 382 | pHlp->pfnPrintf(pHlp, " ISR\n");
|
---|
| 383 | apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
|
---|
| 384 | pHlp->pfnPrintf(pHlp, " TMR\n");
|
---|
| 385 | apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
|
---|
| 386 | pHlp->pfnPrintf(pHlp, " IRR\n");
|
---|
| 387 | apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
|
---|
[60746] | 388 | pHlp->pfnPrintf(pHlp, " PIB\n");
|
---|
| 389 | apicR3DbgInfoPib((PCAPICPIB)pApicCpu->pvApicPibR3, pHlp);
|
---|
| 390 | pHlp->pfnPrintf(pHlp, " Level PIB\n");
|
---|
| 391 | apicR3DbgInfoPib(&pApicCpu->ApicPibLevel, pHlp);
|
---|
[60428] | 392 | pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
|
---|
[60307] | 393 | pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
|
---|
[61741] | 394 | pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
|
---|
| 395 | pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
|
---|
| 396 | pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
|
---|
| 397 | pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
|
---|
[60516] | 398 | pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
|
---|
[61741] | 399 | pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
|
---|
| 400 | pXApicPage->icr_lo.u.u8Vector);
|
---|
| 401 | pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
|
---|
[60307] | 402 | apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
|
---|
[61741] | 403 | pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
|
---|
[60307] | 404 | apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
|
---|
| 405 | if (!fX2ApicMode)
|
---|
[61741] | 406 | pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
|
---|
| 407 | pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
|
---|
| 408 | pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
|
---|
[60307] | 409 | apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
|
---|
[61741] | 410 | pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
|
---|
[60307] | 411 | apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
|
---|
| 412 | pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
|
---|
[61741] | 413 | pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
|
---|
[60307] | 414 | : pXApicPage->icr_hi.u.u8Dest);
|
---|
| 415 | }
|
---|
| 416 |
|
---|
| 417 |
|
---|
| 418 | /**
|
---|
| 419 | * Helper for dumping the LVT timer.
|
---|
| 420 | *
|
---|
| 421 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 422 | * @param pHlp The debug output helper.
|
---|
| 423 | */
|
---|
[61566] | 424 | static void apicR3InfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
|
---|
[60307] | 425 | {
|
---|
| 426 | PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
|
---|
| 427 | uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
|
---|
| 428 | pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
|
---|
[61741] | 429 | pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
|
---|
| 430 | pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
|
---|
| 431 | pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
|
---|
| 432 | pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
|
---|
[60307] | 433 | apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
|
---|
| 434 | }
|
---|
| 435 |
|
---|
| 436 |
|
---|
| 437 | /**
|
---|
[61566] | 438 | * Dumps APIC Local Vector Table (LVT) information.
|
---|
[60307] | 439 | *
|
---|
[61762] | 440 | * @param pVM The cross context VM structure.
|
---|
[61566] | 441 | * @param pHlp The info helpers.
|
---|
| 442 | * @param pszArgs Arguments, ignored.
|
---|
[60307] | 443 | */
|
---|
[61566] | 444 | static DECLCALLBACK(void) apicR3InfoLvt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
[60307] | 445 | {
|
---|
[61566] | 446 | NOREF(pszArgs);
|
---|
[61575] | 447 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
| 448 | if (!pVCpu)
|
---|
[80191] | 449 | pVCpu = pVM->apCpusR3[0];
|
---|
[61575] | 450 |
|
---|
[60307] | 451 | PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
|
---|
| 452 |
|
---|
[61575] | 453 | /*
|
---|
| 454 | * Delivery modes available in the LVT entries. They're different (more reserved stuff) from the
|
---|
| 455 | * ICR delivery modes and hence we don't use apicGetDeliveryMode but mostly because we want small,
|
---|
| 456 | * fixed-length strings to fit our formatting needs here.
|
---|
| 457 | */
|
---|
| 458 | static const char * const s_apszLvtDeliveryModes[] =
|
---|
| 459 | {
|
---|
| 460 | "Fixed ",
|
---|
| 461 | "Rsvd ",
|
---|
| 462 | "SMI ",
|
---|
| 463 | "Rsvd ",
|
---|
| 464 | "NMI ",
|
---|
| 465 | "INIT ",
|
---|
| 466 | "Rsvd ",
|
---|
| 467 | "ExtINT"
|
---|
| 468 | };
|
---|
| 469 | /* Delivery Status. */
|
---|
| 470 | static const char * const s_apszLvtDeliveryStatus[] =
|
---|
| 471 | {
|
---|
| 472 | "Idle",
|
---|
| 473 | "Pend"
|
---|
| 474 | };
|
---|
| 475 | const char *pszNotApplicable = "";
|
---|
[60307] | 476 |
|
---|
[61586] | 477 | pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC Local Vector Table (LVT):\n", pVCpu->idCpu);
|
---|
[61575] | 478 | pHlp->pfnPrintf(pHlp, "lvt timermode mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
|
---|
| 479 | /* Timer. */
|
---|
| 480 | {
|
---|
| 481 | /* Timer modes. */
|
---|
| 482 | static const char * const s_apszLvtTimerModes[] =
|
---|
| 483 | {
|
---|
| 484 | "One-shot ",
|
---|
| 485 | "Periodic ",
|
---|
| 486 | "TSC-dline"
|
---|
| 487 | };
|
---|
| 488 | const uint32_t uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
|
---|
| 489 | const XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
|
---|
| 490 | const char *pszTimerMode = s_apszLvtTimerModes[enmTimerMode];
|
---|
| 491 | const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtTimer);
|
---|
| 492 | const uint8_t uDeliveryStatus = uLvtTimer & XAPIC_LVT_DELIVERY_STATUS;
|
---|
| 493 | const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
|
---|
| 494 | const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
|
---|
| 495 |
|
---|
[61579] | 496 | pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
|
---|
[61575] | 497 | "Timer",
|
---|
| 498 | pszTimerMode,
|
---|
| 499 | uMask,
|
---|
| 500 | pszNotApplicable, /* TriggerMode */
|
---|
| 501 | pszNotApplicable, /* Remote IRR */
|
---|
| 502 | pszNotApplicable, /* Polarity */
|
---|
| 503 | pszDeliveryStatus,
|
---|
| 504 | pszNotApplicable, /* Delivery Mode */
|
---|
| 505 | uVector,
|
---|
| 506 | uVector);
|
---|
| 507 | }
|
---|
| 508 |
|
---|
[60307] | 509 | #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
|
---|
[61575] | 510 | /* Thermal sensor. */
|
---|
| 511 | {
|
---|
| 512 | uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
|
---|
| 513 | const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtThermal);
|
---|
| 514 | const uint8_t uDeliveryStatus = uLvtThermal & XAPIC_LVT_DELIVERY_STATUS;
|
---|
| 515 | const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
|
---|
| 516 | const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtThermal);
|
---|
| 517 | const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
|
---|
| 518 | const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtThermal);
|
---|
| 519 |
|
---|
[61579] | 520 | pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
|
---|
[61575] | 521 | "Thermal",
|
---|
| 522 | pszNotApplicable, /* Timer mode */
|
---|
| 523 | uMask,
|
---|
| 524 | pszNotApplicable, /* TriggerMode */
|
---|
| 525 | pszNotApplicable, /* Remote IRR */
|
---|
| 526 | pszNotApplicable, /* Polarity */
|
---|
| 527 | pszDeliveryStatus,
|
---|
| 528 | pszDeliveryMode,
|
---|
| 529 | uVector,
|
---|
| 530 | uVector);
|
---|
| 531 | }
|
---|
[60307] | 532 | #endif
|
---|
| 533 |
|
---|
[61575] | 534 | /* Performance Monitor Counters. */
|
---|
| 535 | {
|
---|
| 536 | uint32_t const uLvtPerf = pXApicPage->lvt_thermal.all.u32LvtThermal;
|
---|
| 537 | const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtPerf);
|
---|
| 538 | const uint8_t uDeliveryStatus = uLvtPerf & XAPIC_LVT_DELIVERY_STATUS;
|
---|
| 539 | const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
|
---|
| 540 | const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtPerf);
|
---|
| 541 | const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
|
---|
| 542 | const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtPerf);
|
---|
[60307] | 543 |
|
---|
[61579] | 544 | pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
|
---|
[61575] | 545 | "Perf",
|
---|
| 546 | pszNotApplicable, /* Timer mode */
|
---|
| 547 | uMask,
|
---|
| 548 | pszNotApplicable, /* TriggerMode */
|
---|
| 549 | pszNotApplicable, /* Remote IRR */
|
---|
| 550 | pszNotApplicable, /* Polarity */
|
---|
| 551 | pszDeliveryStatus,
|
---|
| 552 | pszDeliveryMode,
|
---|
| 553 | uVector,
|
---|
| 554 | uVector);
|
---|
| 555 | }
|
---|
[60307] | 556 |
|
---|
[61575] | 557 | /* LINT0, LINT1. */
|
---|
| 558 | {
|
---|
| 559 | /* LINTx name. */
|
---|
| 560 | static const char * const s_apszLvtLint[] =
|
---|
| 561 | {
|
---|
| 562 | "LINT0",
|
---|
| 563 | "LINT1"
|
---|
| 564 | };
|
---|
| 565 | /* Trigger mode. */
|
---|
| 566 | static const char * const s_apszLvtTriggerModes[] =
|
---|
| 567 | {
|
---|
| 568 | "Edge ",
|
---|
| 569 | "Level"
|
---|
| 570 | };
|
---|
| 571 | /* Polarity. */
|
---|
| 572 | static const char * const s_apszLvtPolarity[] =
|
---|
| 573 | {
|
---|
| 574 | "ActiveHi",
|
---|
| 575 | "ActiveLo"
|
---|
| 576 | };
|
---|
[60307] | 577 |
|
---|
[61575] | 578 | uint32_t aLvtLint[2];
|
---|
| 579 | aLvtLint[0] = pXApicPage->lvt_lint0.all.u32LvtLint0;
|
---|
| 580 | aLvtLint[1] = pXApicPage->lvt_lint1.all.u32LvtLint1;
|
---|
| 581 | for (size_t i = 0; i < RT_ELEMENTS(aLvtLint); i++)
|
---|
| 582 | {
|
---|
| 583 | uint32_t const uLvtLint = aLvtLint[i];
|
---|
| 584 | const char *pszLint = s_apszLvtLint[i];
|
---|
| 585 | const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtLint);
|
---|
| 586 | const XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvtLint);
|
---|
| 587 | const char *pszTriggerMode = s_apszLvtTriggerModes[enmTriggerMode];
|
---|
| 588 | const uint8_t uRemoteIrr = XAPIC_LVT_GET_REMOTE_IRR(uLvtLint);
|
---|
| 589 | const uint8_t uPolarity = XAPIC_LVT_GET_POLARITY(uLvtLint);
|
---|
| 590 | const char *pszPolarity = s_apszLvtPolarity[uPolarity];
|
---|
| 591 | const uint8_t uDeliveryStatus = uLvtLint & XAPIC_LVT_DELIVERY_STATUS;
|
---|
| 592 | const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
|
---|
| 593 | const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint);
|
---|
| 594 | const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
|
---|
| 595 | const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtLint);
|
---|
| 596 |
|
---|
[61579] | 597 | pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %u %8s %4s %6s %3u (%#x)\n",
|
---|
[61575] | 598 | pszLint,
|
---|
| 599 | pszNotApplicable, /* Timer mode */
|
---|
| 600 | uMask,
|
---|
| 601 | pszTriggerMode,
|
---|
| 602 | uRemoteIrr,
|
---|
| 603 | pszPolarity,
|
---|
| 604 | pszDeliveryStatus,
|
---|
| 605 | pszDeliveryMode,
|
---|
| 606 | uVector,
|
---|
| 607 | uVector);
|
---|
| 608 | }
|
---|
| 609 | }
|
---|
| 610 |
|
---|
| 611 | /* Error. */
|
---|
| 612 | {
|
---|
| 613 | uint32_t const uLvtError = pXApicPage->lvt_thermal.all.u32LvtThermal;
|
---|
| 614 | const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtError);
|
---|
| 615 | const uint8_t uDeliveryStatus = uLvtError & XAPIC_LVT_DELIVERY_STATUS;
|
---|
| 616 | const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
|
---|
| 617 | const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtError);
|
---|
| 618 | const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
|
---|
| 619 | const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtError);
|
---|
| 620 |
|
---|
[61579] | 621 | pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
|
---|
[61575] | 622 | "Error",
|
---|
| 623 | pszNotApplicable, /* Timer mode */
|
---|
| 624 | uMask,
|
---|
| 625 | pszNotApplicable, /* TriggerMode */
|
---|
| 626 | pszNotApplicable, /* Remote IRR */
|
---|
| 627 | pszNotApplicable, /* Polarity */
|
---|
| 628 | pszDeliveryStatus,
|
---|
| 629 | pszDeliveryMode,
|
---|
| 630 | uVector,
|
---|
| 631 | uVector);
|
---|
| 632 | }
|
---|
[60307] | 633 | }
|
---|
| 634 |
|
---|
| 635 |
|
---|
| 636 | /**
|
---|
[61566] | 637 | * Dumps the APIC timer information.
|
---|
[60307] | 638 | *
|
---|
[61762] | 639 | * @param pVM The cross context VM structure.
|
---|
[61566] | 640 | * @param pHlp The info helpers.
|
---|
| 641 | * @param pszArgs Arguments, ignored.
|
---|
[60307] | 642 | */
|
---|
[61566] | 643 | static DECLCALLBACK(void) apicR3InfoTimer(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
[60307] | 644 | {
|
---|
[61566] | 645 | NOREF(pszArgs);
|
---|
[61575] | 646 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
| 647 | if (!pVCpu)
|
---|
[80191] | 648 | pVCpu = pVM->apCpusR3[0];
|
---|
[61575] | 649 |
|
---|
[60307] | 650 | PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
|
---|
| 651 | PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
| 652 |
|
---|
[61586] | 653 | pHlp->pfnPrintf(pHlp, "VCPU[%u] Local APIC timer:\n", pVCpu->idCpu);
|
---|
[60307] | 654 | pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
|
---|
| 655 | pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
|
---|
| 656 | pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
|
---|
| 657 | pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
|
---|
[60428] | 658 | pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
|
---|
[61566] | 659 | apicR3InfoLvtTimer(pVCpu, pHlp);
|
---|
[60307] | 660 | }
|
---|
| 661 |
|
---|
| 662 |
|
---|
[61776] | 663 | #ifdef APIC_FUZZY_SSM_COMPAT_TEST
|
---|
[60307] | 664 |
|
---|
| 665 | /**
|
---|
[60695] | 666 | * Reads a 32-bit register at a specified offset.
|
---|
| 667 | *
|
---|
| 668 | * @returns The value at the specified offset.
|
---|
| 669 | * @param pXApicPage The xAPIC page.
|
---|
| 670 | * @param offReg The offset of the register being read.
|
---|
| 671 | *
|
---|
| 672 | * @remarks Duplicate of apicReadRaw32()!
|
---|
| 673 | */
|
---|
| 674 | static uint32_t apicR3ReadRawR32(PCXAPICPAGE pXApicPage, uint16_t offReg)
|
---|
| 675 | {
|
---|
| 676 | Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
|
---|
| 677 | uint8_t const *pbXApic = (const uint8_t *)pXApicPage;
|
---|
| 678 | uint32_t const uValue = *(const uint32_t *)(pbXApic + offReg);
|
---|
| 679 | return uValue;
|
---|
| 680 | }
|
---|
| 681 |
|
---|
| 682 |
|
---|
| 683 | /**
|
---|
[60624] | 684 | * Helper for dumping per-VCPU APIC state to the release logger.
|
---|
| 685 | *
|
---|
| 686 | * This is primarily concerned about the APIC state relevant for saved-states.
|
---|
| 687 | *
|
---|
| 688 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[60630] | 689 | * @param pszPrefix A caller supplied prefix before dumping the state.
|
---|
[60695] | 690 | * @param uVersion Data layout version.
|
---|
[60624] | 691 | */
|
---|
[60695] | 692 | static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix, uint32_t uVersion)
|
---|
[60624] | 693 | {
|
---|
| 694 | PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
| 695 |
|
---|
[60695] | 696 | LogRel(("APIC%u: %s (version %u):\n", pVCpu->idCpu, pszPrefix, uVersion));
|
---|
[60624] | 697 |
|
---|
[60695] | 698 | switch (uVersion)
|
---|
| 699 | {
|
---|
| 700 | case APIC_SAVED_STATE_VERSION:
|
---|
[61584] | 701 | case APIC_SAVED_STATE_VERSION_VBOX_51_BETA2:
|
---|
[60695] | 702 | {
|
---|
| 703 | /* The auxiliary state. */
|
---|
| 704 | LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
|
---|
| 705 | LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
|
---|
[60624] | 706 |
|
---|
[60695] | 707 | /* The timer. */
|
---|
| 708 | LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
|
---|
| 709 | LogRel(("APIC%u: uHintedTimerInitialCount = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerInitialCount));
|
---|
| 710 | LogRel(("APIC%u: uHintedTimerShift = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
|
---|
[60689] | 711 |
|
---|
[60695] | 712 | PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
|
---|
| 713 | LogRel(("APIC%u: uTimerICR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
|
---|
| 714 | LogRel(("APIC%u: uTimerCCR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
|
---|
[60624] | 715 |
|
---|
[60695] | 716 | /* The PIBs. */
|
---|
| 717 | LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
|
---|
| 718 | LogRel(("APIC%u: Level PIB: %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), &pApicCpu->ApicPibLevel));
|
---|
| 719 |
|
---|
[61584] | 720 | /* The LINT0, LINT1 interrupt line active states. */
|
---|
| 721 | LogRel(("APIC%u: fActiveLint0 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint0));
|
---|
| 722 | LogRel(("APIC%u: fActiveLint1 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint1));
|
---|
| 723 |
|
---|
[60695] | 724 | /* The APIC page. */
|
---|
| 725 | LogRel(("APIC%u: APIC page: %.*Rhxs\n", pVCpu->idCpu, sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
|
---|
| 726 | break;
|
---|
| 727 | }
|
---|
| 728 |
|
---|
| 729 | case APIC_SAVED_STATE_VERSION_VBOX_50:
|
---|
| 730 | case APIC_SAVED_STATE_VERSION_VBOX_30:
|
---|
| 731 | case APIC_SAVED_STATE_VERSION_ANCIENT:
|
---|
| 732 | {
|
---|
| 733 | PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
|
---|
| 734 | LogRel(("APIC%u: uApicBaseMsr = %#RX32\n", pVCpu->idCpu, RT_LO_U32(pApicCpu->uApicBaseMsr)));
|
---|
| 735 | LogRel(("APIC%u: uId = %#RX32\n", pVCpu->idCpu, pXApicPage->id.u8ApicId));
|
---|
| 736 | LogRel(("APIC%u: uPhysId = N/A\n", pVCpu->idCpu));
|
---|
| 737 | LogRel(("APIC%u: uArbId = N/A\n", pVCpu->idCpu));
|
---|
[60731] | 738 | LogRel(("APIC%u: uTpr = %#RX32\n", pVCpu->idCpu, pXApicPage->tpr.u8Tpr));
|
---|
[60695] | 739 | LogRel(("APIC%u: uSvr = %#RX32\n", pVCpu->idCpu, pXApicPage->svr.all.u32Svr));
|
---|
| 740 | LogRel(("APIC%u: uLdr = %#x\n", pVCpu->idCpu, pXApicPage->ldr.all.u32Ldr));
|
---|
| 741 | LogRel(("APIC%u: uDfr = %#x\n", pVCpu->idCpu, pXApicPage->dfr.all.u32Dfr));
|
---|
| 742 |
|
---|
| 743 | for (size_t i = 0; i < 8; i++)
|
---|
| 744 | {
|
---|
[60731] | 745 | LogRel(("APIC%u: Isr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->isr.u[i].u32Reg));
|
---|
| 746 | LogRel(("APIC%u: Tmr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->tmr.u[i].u32Reg));
|
---|
| 747 | LogRel(("APIC%u: Irr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->irr.u[i].u32Reg));
|
---|
[60695] | 748 | }
|
---|
| 749 |
|
---|
| 750 | for (size_t i = 0; i < XAPIC_MAX_LVT_ENTRIES_P4; i++)
|
---|
| 751 | {
|
---|
| 752 | uint16_t const offReg = XAPIC_OFF_LVT_START + (i << 4);
|
---|
[60731] | 753 | LogRel(("APIC%u: Lvt[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, apicR3ReadRawR32(pXApicPage, offReg)));
|
---|
[60695] | 754 | }
|
---|
| 755 |
|
---|
| 756 | LogRel(("APIC%u: uEsr = %#RX32\n", pVCpu->idCpu, pXApicPage->esr.all.u32Errors));
|
---|
| 757 | LogRel(("APIC%u: uIcr_Lo = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
|
---|
| 758 | LogRel(("APIC%u: uIcr_Hi = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
|
---|
| 759 | LogRel(("APIC%u: uTimerDcr = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_dcr.all.u32DivideValue));
|
---|
| 760 | LogRel(("APIC%u: uCountShift = %#RX32\n", pVCpu->idCpu, apicGetTimerShift(pXApicPage)));
|
---|
| 761 | LogRel(("APIC%u: uInitialCount = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
|
---|
| 762 | LogRel(("APIC%u: u64InitialCountLoadTime = %#RX64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
|
---|
| 763 | LogRel(("APIC%u: u64NextTime / TimerCCR = %#RX64\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
|
---|
| 764 | break;
|
---|
| 765 | }
|
---|
| 766 |
|
---|
| 767 | default:
|
---|
| 768 | {
|
---|
| 769 | LogRel(("APIC: apicR3DumpState: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
|
---|
| 770 | break;
|
---|
| 771 | }
|
---|
| 772 | }
|
---|
[60624] | 773 | }
|
---|
[61776] | 774 |
|
---|
[60695] | 775 | #endif /* APIC_FUZZY_SSM_COMPAT_TEST */
|
---|
[60624] | 776 |
|
---|
| 777 | /**
|
---|
[60307] | 778 | * Worker for saving per-VM APIC data.
|
---|
| 779 | *
|
---|
| 780 | * @returns VBox status code.
|
---|
[82026] | 781 | * @param pDevIns The device instance.
|
---|
[60307] | 782 | * @param pVM The cross context VM structure.
|
---|
| 783 | * @param pSSM The SSM handle.
|
---|
| 784 | */
|
---|
[82026] | 785 | static int apicR3SaveVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
|
---|
[60307] | 786 | {
|
---|
[82026] | 787 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
| 788 | PAPIC pApic = VM_TO_APIC(pVM);
|
---|
| 789 | pHlp->pfnSSMPutU32(pSSM, pVM->cCpus);
|
---|
| 790 | pHlp->pfnSSMPutBool(pSSM, pApic->fIoApicPresent);
|
---|
| 791 | return pHlp->pfnSSMPutU32(pSSM, pApic->enmMaxMode);
|
---|
[60307] | 792 | }
|
---|
| 793 |
|
---|
| 794 |
|
---|
| 795 | /**
|
---|
[60605] | 796 | * Worker for loading per-VM APIC data.
|
---|
| 797 | *
|
---|
| 798 | * @returns VBox status code.
|
---|
[82026] | 799 | * @param pDevIns The device instance.
|
---|
[60605] | 800 | * @param pVM The cross context VM structure.
|
---|
| 801 | * @param pSSM The SSM handle.
|
---|
| 802 | */
|
---|
[82026] | 803 | static int apicR3LoadVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
|
---|
[60605] | 804 | {
|
---|
[82026] | 805 | PAPIC pApic = VM_TO_APIC(pVM);
|
---|
| 806 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
[60605] | 807 |
|
---|
| 808 | /* Load and verify number of CPUs. */
|
---|
| 809 | uint32_t cCpus;
|
---|
[82026] | 810 | int rc = pHlp->pfnSSMGetU32(pSSM, &cCpus);
|
---|
[60605] | 811 | AssertRCReturn(rc, rc);
|
---|
| 812 | if (cCpus != pVM->cCpus)
|
---|
[82026] | 813 | return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
|
---|
[60605] | 814 |
|
---|
| 815 | /* Load and verify I/O APIC presence. */
|
---|
| 816 | bool fIoApicPresent;
|
---|
[82026] | 817 | rc = pHlp->pfnSSMGetBool(pSSM, &fIoApicPresent);
|
---|
[60605] | 818 | AssertRCReturn(rc, rc);
|
---|
| 819 | if (fIoApicPresent != pApic->fIoApicPresent)
|
---|
[82026] | 820 | return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
|
---|
[82036] | 821 | fIoApicPresent, pApic->fIoApicPresent);
|
---|
[60605] | 822 |
|
---|
[61776] | 823 | /* Load and verify configured max APIC mode. */
|
---|
| 824 | uint32_t uSavedMaxApicMode;
|
---|
[82026] | 825 | rc = pHlp->pfnSSMGetU32(pSSM, &uSavedMaxApicMode);
|
---|
[60605] | 826 | AssertRCReturn(rc, rc);
|
---|
[61777] | 827 | if (uSavedMaxApicMode != (uint32_t)pApic->enmMaxMode)
|
---|
[82026] | 828 | return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u config=%u"),
|
---|
[82036] | 829 | uSavedMaxApicMode, pApic->enmMaxMode);
|
---|
[60605] | 830 | return VINF_SUCCESS;
|
---|
| 831 | }
|
---|
| 832 |
|
---|
| 833 |
|
---|
| 834 | /**
|
---|
[60689] | 835 | * Worker for loading per-VCPU APIC data for legacy (old) saved-states.
|
---|
| 836 | *
|
---|
| 837 | * @returns VBox status code.
|
---|
[82026] | 838 | * @param pDevIns The device instance.
|
---|
[60689] | 839 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 840 | * @param pSSM The SSM handle.
|
---|
| 841 | * @param uVersion Data layout version.
|
---|
| 842 | */
|
---|
[82026] | 843 | static int apicR3LoadLegacyVCpuData(PPDMDEVINS pDevIns, PVMCPU pVCpu, PSSMHANDLE pSSM, uint32_t uVersion)
|
---|
[60689] | 844 | {
|
---|
| 845 | AssertReturn(uVersion <= APIC_SAVED_STATE_VERSION_VBOX_50, VERR_NOT_SUPPORTED);
|
---|
| 846 |
|
---|
[82026] | 847 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
| 848 | PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
| 849 | PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
|
---|
[60689] | 850 |
|
---|
| 851 | uint32_t uApicBaseLo;
|
---|
[82026] | 852 | int rc = pHlp->pfnSSMGetU32(pSSM, &uApicBaseLo);
|
---|
[60689] | 853 | AssertRCReturn(rc, rc);
|
---|
| 854 | pApicCpu->uApicBaseMsr = uApicBaseLo;
|
---|
[60716] | 855 | Log2(("APIC%u: apicR3LoadLegacyVCpuData: uApicBaseMsr=%#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
|
---|
[60689] | 856 |
|
---|
| 857 | switch (uVersion)
|
---|
| 858 | {
|
---|
| 859 | case APIC_SAVED_STATE_VERSION_VBOX_50:
|
---|
| 860 | case APIC_SAVED_STATE_VERSION_VBOX_30:
|
---|
| 861 | {
|
---|
| 862 | uint32_t uApicId, uPhysApicId, uArbId;
|
---|
[82026] | 863 | pHlp->pfnSSMGetU32(pSSM, &uApicId); pXApicPage->id.u8ApicId = uApicId;
|
---|
| 864 | pHlp->pfnSSMGetU32(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
|
---|
| 865 | pHlp->pfnSSMGetU32(pSSM, &uArbId); NOREF(uArbId); /* ArbID is & was unused. */
|
---|
[60689] | 866 | break;
|
---|
| 867 | }
|
---|
| 868 |
|
---|
[60716] | 869 | case APIC_SAVED_STATE_VERSION_ANCIENT:
|
---|
| 870 | {
|
---|
| 871 | uint8_t uPhysApicId;
|
---|
[82026] | 872 | pHlp->pfnSSMGetU8(pSSM, &pXApicPage->id.u8ApicId);
|
---|
| 873 | pHlp->pfnSSMGetU8(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
|
---|
[60716] | 874 | break;
|
---|
| 875 | }
|
---|
| 876 |
|
---|
[60689] | 877 | default:
|
---|
| 878 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
| 879 | }
|
---|
| 880 |
|
---|
| 881 | uint32_t u32Tpr;
|
---|
[82026] | 882 | pHlp->pfnSSMGetU32(pSSM, &u32Tpr);
|
---|
[61078] | 883 | pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR_VALID;
|
---|
[60689] | 884 |
|
---|
[82026] | 885 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->svr.all.u32Svr);
|
---|
| 886 | pHlp->pfnSSMGetU8(pSSM, &pXApicPage->ldr.u.u8LogicalApicId);
|
---|
[60689] | 887 |
|
---|
| 888 | uint8_t uDfr;
|
---|
[82026] | 889 | pHlp->pfnSSMGetU8(pSSM, &uDfr);
|
---|
[60689] | 890 | pXApicPage->dfr.u.u4Model = uDfr >> 4;
|
---|
| 891 |
|
---|
| 892 | AssertCompile(RT_ELEMENTS(pXApicPage->isr.u) == 8);
|
---|
| 893 | AssertCompile(RT_ELEMENTS(pXApicPage->tmr.u) == 8);
|
---|
| 894 | AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 8);
|
---|
| 895 | for (size_t i = 0; i < 8; i++)
|
---|
| 896 | {
|
---|
[82026] | 897 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->isr.u[i].u32Reg);
|
---|
| 898 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->tmr.u[i].u32Reg);
|
---|
| 899 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->irr.u[i].u32Reg);
|
---|
[60689] | 900 | }
|
---|
| 901 |
|
---|
[82026] | 902 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_timer.all.u32LvtTimer);
|
---|
| 903 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_thermal.all.u32LvtThermal);
|
---|
| 904 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_perf.all.u32LvtPerf);
|
---|
| 905 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_lint0.all.u32LvtLint0);
|
---|
| 906 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_lint1.all.u32LvtLint1);
|
---|
| 907 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->lvt_error.all.u32LvtError);
|
---|
[60689] | 908 |
|
---|
[82026] | 909 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->esr.all.u32Errors);
|
---|
| 910 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->icr_lo.all.u32IcrLo);
|
---|
| 911 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->icr_hi.all.u32IcrHi);
|
---|
[60689] | 912 |
|
---|
| 913 | uint32_t u32TimerShift;
|
---|
[82026] | 914 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue);
|
---|
| 915 | pHlp->pfnSSMGetU32(pSSM, &u32TimerShift);
|
---|
[61041] | 916 | /*
|
---|
| 917 | * Old implementation may have left the timer shift uninitialized until
|
---|
| 918 | * the timer configuration register was written. Unfortunately zero is
|
---|
| 919 | * also a valid timer shift value, so we're just going to ignore it
|
---|
| 920 | * completely. The shift count can always be derived from the DCR.
|
---|
| 921 | * See @bugref{8245#c98}.
|
---|
[60858] | 922 | */
|
---|
[60689] | 923 | uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
|
---|
| 924 |
|
---|
[82026] | 925 | pHlp->pfnSSMGetU32(pSSM, &pXApicPage->timer_icr.u32InitialCount);
|
---|
| 926 | pHlp->pfnSSMGetU64(pSSM, &pApicCpu->u64TimerInitial);
|
---|
[60689] | 927 | uint64_t uNextTS;
|
---|
[82026] | 928 | rc = pHlp->pfnSSMGetU64(pSSM, &uNextTS); AssertRCReturn(rc, rc);
|
---|
[60689] | 929 | if (uNextTS >= pApicCpu->u64TimerInitial + ((pXApicPage->timer_icr.u32InitialCount + 1) << uTimerShift))
|
---|
| 930 | pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
|
---|
| 931 |
|
---|
[82031] | 932 | rc = PDMDevHlpTimerLoad(pDevIns, pApicCpu->hTimer, pSSM);
|
---|
[60689] | 933 | AssertRCReturn(rc, rc);
|
---|
| 934 | Assert(pApicCpu->uHintedTimerInitialCount == 0);
|
---|
| 935 | Assert(pApicCpu->uHintedTimerShift == 0);
|
---|
[82031] | 936 | if (PDMDevHlpTimerIsActive(pDevIns, pApicCpu->hTimer))
|
---|
[60689] | 937 | {
|
---|
| 938 | uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
|
---|
[82031] | 939 | apicHintTimerFreq(pDevIns, pApicCpu, uInitialCount, uTimerShift);
|
---|
[60689] | 940 | }
|
---|
| 941 |
|
---|
| 942 | return rc;
|
---|
| 943 | }
|
---|
| 944 |
|
---|
[60307] | 945 |
|
---|
| 946 | /**
|
---|
| 947 | * @copydoc FNSSMDEVSAVEEXEC
|
---|
| 948 | */
|
---|
| 949 | static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
|
---|
| 950 | {
|
---|
[82026] | 951 | PVM pVM = PDMDevHlpGetVM(pDevIns);
|
---|
| 952 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
| 953 |
|
---|
[60307] | 954 | AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
|
---|
| 955 |
|
---|
[60652] | 956 | LogFlow(("APIC: apicR3SaveExec\n"));
|
---|
| 957 |
|
---|
[60307] | 958 | /* Save per-VM data. */
|
---|
[82026] | 959 | int rc = apicR3SaveVMData(pDevIns, pVM, pSSM);
|
---|
[60307] | 960 | AssertRCReturn(rc, rc);
|
---|
| 961 |
|
---|
| 962 | /* Save per-VCPU data.*/
|
---|
| 963 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
| 964 | {
|
---|
[80191] | 965 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
|
---|
[60307] | 966 | PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
| 967 |
|
---|
[60804] | 968 | /* Update interrupts from the pending-interrupts bitmaps to the IRR. */
|
---|
| 969 | APICUpdatePendingInterrupts(pVCpu);
|
---|
| 970 |
|
---|
[60601] | 971 | /* Save the auxiliary data. */
|
---|
[82026] | 972 | pHlp->pfnSSMPutU64(pSSM, pApicCpu->uApicBaseMsr);
|
---|
| 973 | pHlp->pfnSSMPutU32(pSSM, pApicCpu->uEsrInternal);
|
---|
[60307] | 974 |
|
---|
[60601] | 975 | /* Save the APIC page. */
|
---|
| 976 | if (XAPIC_IN_X2APIC_MODE(pVCpu))
|
---|
[82026] | 977 | pHlp->pfnSSMPutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
|
---|
[60601] | 978 | else
|
---|
[82026] | 979 | pHlp->pfnSSMPutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
|
---|
[60601] | 980 |
|
---|
| 981 | /* Save the timer. */
|
---|
[82026] | 982 | pHlp->pfnSSMPutU64(pSSM, pApicCpu->u64TimerInitial);
|
---|
[82031] | 983 | PDMDevHlpTimerSave(pDevIns, pApicCpu->hTimer, pSSM);
|
---|
[60624] | 984 |
|
---|
[61584] | 985 | /* Save the LINT0, LINT1 interrupt line states. */
|
---|
[82026] | 986 | pHlp->pfnSSMPutBool(pSSM, pApicCpu->fActiveLint0);
|
---|
| 987 | pHlp->pfnSSMPutBool(pSSM, pApicCpu->fActiveLint1);
|
---|
[61584] | 988 |
|
---|
[60695] | 989 | #if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
|
---|
| 990 | apicR3DumpState(pVCpu, "Saved state", APIC_SAVED_STATE_VERSION);
|
---|
[60624] | 991 | #endif
|
---|
[60307] | 992 | }
|
---|
| 993 |
|
---|
[60695] | 994 | #ifdef APIC_FUZZY_SSM_COMPAT_TEST
|
---|
| 995 | /* The state is fuzzy, don't even bother trying to load the guest. */
|
---|
| 996 | return VERR_INVALID_STATE;
|
---|
| 997 | #else
|
---|
[60307] | 998 | return rc;
|
---|
[60695] | 999 | #endif
|
---|
[60307] | 1000 | }
|
---|
| 1001 |
|
---|
| 1002 |
|
---|
| 1003 | /**
|
---|
| 1004 | * @copydoc FNSSMDEVLOADEXEC
|
---|
| 1005 | */
|
---|
| 1006 | static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
| 1007 | {
|
---|
[82026] | 1008 | PVM pVM = PDMDevHlpGetVM(pDevIns);
|
---|
| 1009 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
[60689] | 1010 |
|
---|
[60307] | 1011 | AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
|
---|
[60689] | 1012 | AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
|
---|
[60307] | 1013 |
|
---|
[60689] | 1014 | LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
|
---|
[60652] | 1015 |
|
---|
[60307] | 1016 | /* Weed out invalid versions. */
|
---|
[61336] | 1017 | if ( uVersion != APIC_SAVED_STATE_VERSION
|
---|
[61584] | 1018 | && uVersion != APIC_SAVED_STATE_VERSION_VBOX_51_BETA2
|
---|
[61336] | 1019 | && uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
|
---|
| 1020 | && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
|
---|
| 1021 | && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
|
---|
[60307] | 1022 | {
|
---|
[60689] | 1023 | LogRel(("APIC: apicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
|
---|
[60307] | 1024 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
| 1025 | }
|
---|
| 1026 |
|
---|
[60689] | 1027 | int rc = VINF_SUCCESS;
|
---|
[60307] | 1028 | if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
|
---|
| 1029 | {
|
---|
[82026] | 1030 | rc = apicR3LoadVMData(pDevIns, pVM, pSSM);
|
---|
[60689] | 1031 | AssertRCReturn(rc, rc);
|
---|
[60307] | 1032 |
|
---|
| 1033 | if (uVersion == APIC_SAVED_STATE_VERSION)
|
---|
[60605] | 1034 | { /* Load any new additional per-VM data. */ }
|
---|
[60307] | 1035 | }
|
---|
| 1036 |
|
---|
[78208] | 1037 | /*
|
---|
| 1038 | * Restore per CPU state.
|
---|
| 1039 | *
|
---|
| 1040 | * Note! PDM will restore the VMCPU_FF_INTERRUPT_APIC flag for us.
|
---|
| 1041 | * This code doesn't touch it. No devices should make us touch
|
---|
| 1042 | * it later during the restore either, only during the 'done' phase.
|
---|
| 1043 | */
|
---|
[60307] | 1044 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
| 1045 | {
|
---|
[80191] | 1046 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
|
---|
[60307] | 1047 | PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
| 1048 |
|
---|
[61797] | 1049 | if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_50)
|
---|
[60307] | 1050 | {
|
---|
[60605] | 1051 | /* Load the auxiliary data. */
|
---|
[82026] | 1052 | pHlp->pfnSSMGetU64V(pSSM, &pApicCpu->uApicBaseMsr);
|
---|
| 1053 | pHlp->pfnSSMGetU32(pSSM, &pApicCpu->uEsrInternal);
|
---|
[60605] | 1054 |
|
---|
| 1055 | /* Load the APIC page. */
|
---|
| 1056 | if (XAPIC_IN_X2APIC_MODE(pVCpu))
|
---|
[82026] | 1057 | pHlp->pfnSSMGetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
|
---|
[60605] | 1058 | else
|
---|
[82026] | 1059 | pHlp->pfnSSMGetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
|
---|
[60605] | 1060 |
|
---|
| 1061 | /* Load the timer. */
|
---|
[82026] | 1062 | rc = pHlp->pfnSSMGetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
|
---|
[82031] | 1063 | rc = PDMDevHlpTimerLoad(pDevIns, pApicCpu->hTimer, pSSM); AssertRCReturn(rc, rc);
|
---|
[60605] | 1064 | Assert(pApicCpu->uHintedTimerShift == 0);
|
---|
| 1065 | Assert(pApicCpu->uHintedTimerInitialCount == 0);
|
---|
[82031] | 1066 | if (PDMDevHlpTimerIsActive(pDevIns, pApicCpu->hTimer))
|
---|
[60605] | 1067 | {
|
---|
| 1068 | PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
|
---|
| 1069 | uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
|
---|
| 1070 | uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
|
---|
[82031] | 1071 | apicHintTimerFreq(pDevIns, pApicCpu, uInitialCount, uTimerShift);
|
---|
[60605] | 1072 | }
|
---|
[61584] | 1073 |
|
---|
| 1074 | /* Load the LINT0, LINT1 interrupt line states. */
|
---|
| 1075 | if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_51_BETA2)
|
---|
| 1076 | {
|
---|
[82026] | 1077 | pHlp->pfnSSMGetBoolV(pSSM, &pApicCpu->fActiveLint0);
|
---|
| 1078 | pHlp->pfnSSMGetBoolV(pSSM, &pApicCpu->fActiveLint1);
|
---|
[61584] | 1079 | }
|
---|
[60307] | 1080 | }
|
---|
| 1081 | else
|
---|
| 1082 | {
|
---|
[82026] | 1083 | rc = apicR3LoadLegacyVCpuData(pDevIns, pVCpu, pSSM, uVersion);
|
---|
[60689] | 1084 | AssertRCReturn(rc, rc);
|
---|
[60307] | 1085 | }
|
---|
[60689] | 1086 |
|
---|
[61776] | 1087 | /*
|
---|
| 1088 | * Check that we're still good wrt restored data, then tell CPUM about the current CPUID[1].EDX[9] visibility.
|
---|
| 1089 | */
|
---|
[82026] | 1090 | rc = pHlp->pfnSSMHandleGetStatus(pSSM);
|
---|
[61776] | 1091 | AssertRCReturn(rc, rc);
|
---|
| 1092 | CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN));
|
---|
| 1093 |
|
---|
[60695] | 1094 | #if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
|
---|
| 1095 | apicR3DumpState(pVCpu, "Loaded state", uVersion);
|
---|
[60689] | 1096 | #endif
|
---|
[60307] | 1097 | }
|
---|
| 1098 |
|
---|
| 1099 | return rc;
|
---|
| 1100 | }
|
---|
| 1101 |
|
---|
| 1102 |
|
---|
| 1103 | /**
|
---|
[82033] | 1104 | * @callback_method_impl{FNTMTIMERDEV}
|
---|
[60307] | 1105 | *
|
---|
[82033] | 1106 | * @note pvUser points to the VMCPU.
|
---|
[60307] | 1107 | *
|
---|
| 1108 | * @remarks Currently this function is invoked on the last EMT, see @c
|
---|
| 1109 | * idTimerCpu in tmR3TimerCallback(). However, the code does -not-
|
---|
| 1110 | * rely on this and is designed to work with being invoked on any
|
---|
| 1111 | * thread.
|
---|
| 1112 | */
|
---|
| 1113 | static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
|
---|
| 1114 | {
|
---|
[82031] | 1115 | PVMCPU pVCpu = (PVMCPU)pvUser;
|
---|
| 1116 | PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
| 1117 | Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pApicCpu->hTimer));
|
---|
[60307] | 1118 | Assert(pVCpu);
|
---|
[60464] | 1119 | LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
|
---|
[82033] | 1120 | RT_NOREF(pDevIns, pTimer, pApicCpu);
|
---|
[60307] | 1121 |
|
---|
| 1122 | PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
|
---|
[62656] | 1123 | uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
|
---|
| 1124 | #ifdef VBOX_WITH_STATISTICS
|
---|
[60632] | 1125 | STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
|
---|
[62656] | 1126 | #endif
|
---|
[60307] | 1127 | if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
|
---|
| 1128 | {
|
---|
| 1129 | uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
|
---|
[60650] | 1130 | Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
|
---|
[65380] | 1131 | apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE, 0 /* uSrcTag */);
|
---|
[60307] | 1132 | }
|
---|
| 1133 |
|
---|
| 1134 | XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
|
---|
| 1135 | switch (enmTimerMode)
|
---|
| 1136 | {
|
---|
| 1137 | case XAPICTIMERMODE_PERIODIC:
|
---|
| 1138 | {
|
---|
| 1139 | /* The initial-count register determines if the periodic timer is re-armed. */
|
---|
| 1140 | uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
|
---|
| 1141 | pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
|
---|
| 1142 | if (uInitialCount)
|
---|
[60468] | 1143 | {
|
---|
[60650] | 1144 | Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
|
---|
[61794] | 1145 | apicStartTimer(pVCpu, uInitialCount);
|
---|
[60468] | 1146 | }
|
---|
[60307] | 1147 | break;
|
---|
| 1148 | }
|
---|
| 1149 |
|
---|
| 1150 | case XAPICTIMERMODE_ONESHOT:
|
---|
| 1151 | {
|
---|
| 1152 | pXApicPage->timer_ccr.u32CurrentCount = 0;
|
---|
| 1153 | break;
|
---|
| 1154 | }
|
---|
| 1155 |
|
---|
| 1156 | case XAPICTIMERMODE_TSC_DEADLINE:
|
---|
| 1157 | {
|
---|
| 1158 | /** @todo implement TSC deadline. */
|
---|
| 1159 | AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
|
---|
| 1160 | break;
|
---|
| 1161 | }
|
---|
| 1162 | }
|
---|
| 1163 | }
|
---|
| 1164 |
|
---|
| 1165 |
|
---|
| 1166 | /**
|
---|
| 1167 | * @interface_method_impl{PDMDEVREG,pfnReset}
|
---|
| 1168 | */
|
---|
[80531] | 1169 | DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
|
---|
[60307] | 1170 | {
|
---|
[62656] | 1171 | PVM pVM = PDMDevHlpGetVM(pDevIns);
|
---|
[60307] | 1172 | VM_ASSERT_EMT0(pVM);
|
---|
| 1173 | VM_ASSERT_IS_NOT_RUNNING(pVM);
|
---|
| 1174 |
|
---|
[60652] | 1175 | LogFlow(("APIC: apicR3Reset\n"));
|
---|
| 1176 |
|
---|
[60307] | 1177 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
| 1178 | {
|
---|
[80191] | 1179 | PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
|
---|
[60307] | 1180 | PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
|
---|
| 1181 |
|
---|
[82031] | 1182 | if (PDMDevHlpTimerIsActive(pDevIns, pApicCpu->hTimer))
|
---|
| 1183 | PDMDevHlpTimerStop(pDevIns, pApicCpu->hTimer);
|
---|
[60307] | 1184 |
|
---|
[73281] | 1185 | apicResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
|
---|
[60307] | 1186 |
|
---|
| 1187 | /* Clear the interrupt pending force flag. */
|
---|
[61794] | 1188 | apicClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
|
---|
[60307] | 1189 | }
|
---|
| 1190 | }
|
---|
| 1191 |
|
---|
| 1192 |
|
---|
| 1193 | /**
|
---|
| 1194 | * @interface_method_impl{PDMDEVREG,pfnRelocate}
|
---|
| 1195 | */
|
---|
[80531] | 1196 | DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
|
---|
[60307] | 1197 | {
|
---|
[80062] | 1198 | RT_NOREF(pDevIns, offDelta);
|
---|
[60307] | 1199 | }
|
---|
| 1200 |
|
---|
| 1201 |
|
---|
| 1202 | /**
|
---|
[60398] | 1203 | * Terminates the APIC state.
|
---|
| 1204 | *
|
---|
| 1205 | * @param pVM The cross context VM structure.
|
---|
| 1206 | */
|
---|
| 1207 | static void apicR3TermState(PVM pVM)
|
---|
| 1208 | {
|
---|
| 1209 | PAPIC pApic = VM_TO_APIC(pVM);
|
---|
[60456] | 1210 | LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
|
---|
| 1211 |
|
---|
[60468] | 1212 | /* Unmap and free the PIB. */
|
---|
| 1213 | if (pApic->pvApicPibR3 != NIL_RTR3PTR)
|
---|
[60398] | 1214 | {
|
---|
| 1215 | size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
|
---|
| 1216 | if (cPages == 1)
|
---|
[60689] | 1217 | SUPR3PageFreeEx(pApic->pvApicPibR3, cPages);
|
---|
[60398] | 1218 | else
|
---|
[60689] | 1219 | SUPR3ContFree(pApic->pvApicPibR3, cPages);
|
---|
[60468] | 1220 | pApic->pvApicPibR3 = NIL_RTR3PTR;
|
---|
| 1221 | pApic->pvApicPibR0 = NIL_RTR0PTR;
|
---|
[60398] | 1222 | }
|
---|
| 1223 |
|
---|
[60468] | 1224 | /* Unmap and free the virtual-APIC pages. */
|
---|
[60398] | 1225 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
| 1226 | {
|
---|
[80191] | 1227 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
|
---|
[60468] | 1228 | PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
| 1229 |
|
---|
| 1230 | pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
|
---|
| 1231 | pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
|
---|
| 1232 |
|
---|
| 1233 | if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
|
---|
[60398] | 1234 | {
|
---|
[60689] | 1235 | SUPR3PageFreeEx(pApicCpu->pvApicPageR3, 1 /* cPages */);
|
---|
[60468] | 1236 | pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
|
---|
| 1237 | pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
|
---|
[60398] | 1238 | }
|
---|
| 1239 | }
|
---|
| 1240 | }
|
---|
| 1241 |
|
---|
| 1242 |
|
---|
| 1243 | /**
|
---|
| 1244 | * Initializes the APIC state.
|
---|
| 1245 | *
|
---|
| 1246 | * @returns VBox status code.
|
---|
| 1247 | * @param pVM The cross context VM structure.
|
---|
| 1248 | */
|
---|
| 1249 | static int apicR3InitState(PVM pVM)
|
---|
| 1250 | {
|
---|
| 1251 | PAPIC pApic = VM_TO_APIC(pVM);
|
---|
[60456] | 1252 | LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
|
---|
[60398] | 1253 |
|
---|
| 1254 | /*
|
---|
| 1255 | * Allocate and map the pending-interrupt bitmap (PIB).
|
---|
| 1256 | *
|
---|
| 1257 | * We allocate all the VCPUs' PIBs contiguously in order to save space as
|
---|
| 1258 | * physically contiguous allocations are rounded to a multiple of page size.
|
---|
| 1259 | */
|
---|
[60468] | 1260 | Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
|
---|
| 1261 | Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
|
---|
[60398] | 1262 | pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), PAGE_SIZE);
|
---|
| 1263 | size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
|
---|
| 1264 | if (cPages == 1)
|
---|
| 1265 | {
|
---|
| 1266 | SUPPAGE SupApicPib;
|
---|
| 1267 | RT_ZERO(SupApicPib);
|
---|
| 1268 | SupApicPib.Phys = NIL_RTHCPHYS;
|
---|
[60689] | 1269 | int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
|
---|
[60398] | 1270 | if (RT_SUCCESS(rc))
|
---|
| 1271 | {
|
---|
| 1272 | pApic->HCPhysApicPib = SupApicPib.Phys;
|
---|
[60468] | 1273 | AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
|
---|
[60398] | 1274 | }
|
---|
| 1275 | else
|
---|
| 1276 | {
|
---|
| 1277 | LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
|
---|
| 1278 | return rc;
|
---|
| 1279 | }
|
---|
| 1280 | }
|
---|
| 1281 | else
|
---|
| 1282 | pApic->pvApicPibR3 = SUPR3ContAlloc(cPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
|
---|
| 1283 |
|
---|
| 1284 | if (pApic->pvApicPibR3)
|
---|
| 1285 | {
|
---|
[60468] | 1286 | AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
|
---|
| 1287 | AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
|
---|
[60435] | 1288 |
|
---|
[60468] | 1289 | /* Initialize the PIB. */
|
---|
[60689] | 1290 | RT_BZERO(pApic->pvApicPibR3, pApic->cbApicPib);
|
---|
[60468] | 1291 |
|
---|
| 1292 | /*
|
---|
| 1293 | * Allocate the map the virtual-APIC pages.
|
---|
| 1294 | */
|
---|
[60398] | 1295 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
| 1296 | {
|
---|
[80191] | 1297 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
|
---|
[60398] | 1298 | PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
| 1299 |
|
---|
| 1300 | SUPPAGE SupApicPage;
|
---|
| 1301 | RT_ZERO(SupApicPage);
|
---|
| 1302 | SupApicPage.Phys = NIL_RTHCPHYS;
|
---|
| 1303 |
|
---|
[60542] | 1304 | Assert(pVCpu->idCpu == idCpu);
|
---|
[77098] | 1305 | Assert(pApicCpu->pvApicPageR3 == NIL_RTR3PTR);
|
---|
[60468] | 1306 | Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
|
---|
| 1307 | AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
|
---|
[60398] | 1308 | pApicCpu->cbApicPage = sizeof(XAPICPAGE);
|
---|
[60689] | 1309 | int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
|
---|
[60398] | 1310 | &SupApicPage);
|
---|
| 1311 | if (RT_SUCCESS(rc))
|
---|
| 1312 | {
|
---|
[60468] | 1313 | AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR, VERR_INTERNAL_ERROR);
|
---|
| 1314 | AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
|
---|
[60398] | 1315 | pApicCpu->HCPhysApicPage = SupApicPage.Phys;
|
---|
| 1316 |
|
---|
| 1317 | /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
|
---|
[60646] | 1318 | uint32_t const offApicPib = idCpu * sizeof(APICPIB);
|
---|
[60456] | 1319 | pApicCpu->pvApicPibR0 = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
|
---|
| 1320 | pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
|
---|
[60398] | 1321 |
|
---|
| 1322 | /* Initialize the virtual-APIC state. */
|
---|
[60689] | 1323 | RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
|
---|
[73281] | 1324 | apicResetCpu(pVCpu, true /* fResetApicBaseMsr */);
|
---|
[60456] | 1325 |
|
---|
[60468] | 1326 | #ifdef DEBUG_ramshankar
|
---|
| 1327 | Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
|
---|
| 1328 | Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR);
|
---|
| 1329 | Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
|
---|
[60456] | 1330 | #endif
|
---|
[60398] | 1331 | }
|
---|
| 1332 | else
|
---|
| 1333 | {
|
---|
[61124] | 1334 | LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", idCpu, pApicCpu->cbApicPage, rc));
|
---|
[60398] | 1335 | apicR3TermState(pVM);
|
---|
[60468] | 1336 | return rc;
|
---|
[60398] | 1337 | }
|
---|
| 1338 | }
|
---|
| 1339 |
|
---|
[60468] | 1340 | #ifdef DEBUG_ramshankar
|
---|
| 1341 | Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
|
---|
| 1342 | Assert(pApic->pvApicPibR0 != NIL_RTR0PTR);
|
---|
[60456] | 1343 | #endif
|
---|
[60398] | 1344 | return VINF_SUCCESS;
|
---|
| 1345 | }
|
---|
| 1346 |
|
---|
[60468] | 1347 | LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
|
---|
| 1348 | pApic->cbApicPib));
|
---|
[60398] | 1349 | return VERR_NO_MEMORY;
|
---|
| 1350 | }
|
---|
| 1351 |
|
---|
| 1352 |
|
---|
| 1353 | /**
|
---|
| 1354 | * @interface_method_impl{PDMDEVREG,pfnDestruct}
|
---|
| 1355 | */
|
---|
[80531] | 1356 | DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
|
---|
[60398] | 1357 | {
|
---|
[80062] | 1358 | PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
|
---|
[60398] | 1359 | PVM pVM = PDMDevHlpGetVM(pDevIns);
|
---|
[60468] | 1360 | LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
|
---|
| 1361 |
|
---|
[60398] | 1362 | apicR3TermState(pVM);
|
---|
| 1363 | return VINF_SUCCESS;
|
---|
| 1364 | }
|
---|
| 1365 |
|
---|
| 1366 |
|
---|
| 1367 | /**
|
---|
| 1368 | * @interface_method_impl{PDMDEVREG,pfnInitComplete}
|
---|
| 1369 | */
|
---|
[80531] | 1370 | DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
|
---|
[60398] | 1371 | {
|
---|
| 1372 | PVM pVM = PDMDevHlpGetVM(pDevIns);
|
---|
| 1373 | PAPIC pApic = VM_TO_APIC(pVM);
|
---|
| 1374 |
|
---|
[60468] | 1375 | /*
|
---|
| 1376 | * Init APIC settings that rely on HM and CPUM configurations.
|
---|
| 1377 | */
|
---|
[60398] | 1378 | CPUMCPUIDLEAF CpuLeaf;
|
---|
| 1379 | int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
|
---|
| 1380 | AssertRCReturn(rc, rc);
|
---|
[60468] | 1381 |
|
---|
[60398] | 1382 | pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
|
---|
| 1383 | pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
|
---|
| 1384 | pApic->fVirtApicRegsEnabled = HMR3IsVirtApicRegsEnabled(pVM->pUVM);
|
---|
| 1385 |
|
---|
| 1386 | LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
|
---|
| 1387 | pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
|
---|
[60464] | 1388 |
|
---|
[60398] | 1389 | return VINF_SUCCESS;
|
---|
| 1390 | }
|
---|
| 1391 |
|
---|
| 1392 |
|
---|
| 1393 | /**
|
---|
[60307] | 1394 | * @interface_method_impl{PDMDEVREG,pfnConstruct}
|
---|
| 1395 | */
|
---|
[80531] | 1396 | DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
|
---|
[60307] | 1397 | {
|
---|
[80062] | 1398 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
|
---|
[82026] | 1399 | PAPICDEV pApicDev = PDMDEVINS_2_DATA(pDevIns, PAPICDEV);
|
---|
| 1400 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
| 1401 | PVM pVM = PDMDevHlpGetVM(pDevIns);
|
---|
| 1402 | PAPIC pApic = VM_TO_APIC(pVM);
|
---|
[62656] | 1403 | Assert(iInstance == 0); NOREF(iInstance);
|
---|
[60307] | 1404 |
|
---|
| 1405 | /*
|
---|
[61776] | 1406 | * Init the data.
|
---|
| 1407 | */
|
---|
[82031] | 1408 | pApic->pDevInsR3 = pDevIns;
|
---|
[82026] | 1409 | pApic->fR0Enabled = pDevIns->fR0Enabled;
|
---|
| 1410 | pApic->fRCEnabled = pDevIns->fRCEnabled;
|
---|
[61776] | 1411 |
|
---|
| 1412 | /*
|
---|
[60364] | 1413 | * Validate APIC settings.
|
---|
[60307] | 1414 | */
|
---|
[82026] | 1415 | PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Mode|IOAPIC|NumCPUs", "");
|
---|
[60307] | 1416 |
|
---|
[82026] | 1417 | int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
|
---|
[60307] | 1418 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1419 |
|
---|
[61776] | 1420 | /* Max APIC feature level. */
|
---|
| 1421 | uint8_t uMaxMode;
|
---|
[82026] | 1422 | rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Mode", &uMaxMode, PDMAPICMODE_APIC);
|
---|
[60307] | 1423 | AssertLogRelRCReturn(rc, rc);
|
---|
[61776] | 1424 | switch ((PDMAPICMODE)uMaxMode)
|
---|
[60307] | 1425 | {
|
---|
[61776] | 1426 | case PDMAPICMODE_NONE:
|
---|
[64663] | 1427 | LogRel(("APIC: APIC maximum mode configured as 'None', effectively disabled/not-present!\n"));
|
---|
[61776] | 1428 | case PDMAPICMODE_APIC:
|
---|
| 1429 | case PDMAPICMODE_X2APIC:
|
---|
[60720] | 1430 | break;
|
---|
[60307] | 1431 | default:
|
---|
[61776] | 1432 | return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %d unknown.", uMaxMode);
|
---|
[60307] | 1433 | }
|
---|
[61776] | 1434 | pApic->enmMaxMode = (PDMAPICMODE)uMaxMode;
|
---|
[60307] | 1435 |
|
---|
| 1436 | /*
|
---|
| 1437 | * Disable automatic PDM locking for this device.
|
---|
| 1438 | */
|
---|
| 1439 | rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
|
---|
| 1440 | AssertRCReturn(rc, rc);
|
---|
| 1441 |
|
---|
| 1442 | /*
|
---|
[61776] | 1443 | * Register the APIC with PDM.
|
---|
[60307] | 1444 | */
|
---|
[82039] | 1445 | rc = PDMDevHlpApicRegister(pDevIns);
|
---|
[60307] | 1446 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1447 |
|
---|
| 1448 | /*
|
---|
[61776] | 1449 | * Initialize the APIC state.
|
---|
| 1450 | */
|
---|
| 1451 | if (pApic->enmMaxMode == PDMAPICMODE_X2APIC)
|
---|
| 1452 | {
|
---|
| 1453 | rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
|
---|
| 1454 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1455 | }
|
---|
[63944] | 1456 | else
|
---|
| 1457 | {
|
---|
| 1458 | /* We currently don't have a function to remove the range, so we register an range which will cause a #GP. */
|
---|
| 1459 | rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic_Invalid);
|
---|
| 1460 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1461 | }
|
---|
[61776] | 1462 |
|
---|
| 1463 | /* Tell CPUM about the APIC feature level so it can adjust APICBASE MSR GP mask and CPUID bits. */
|
---|
[64596] | 1464 | apicR3SetCpuIdFeatureLevel(pVM, pApic->enmMaxMode);
|
---|
[82026] | 1465 |
|
---|
[64655] | 1466 | /* Finally, initialize the state. */
|
---|
[61776] | 1467 | rc = apicR3InitState(pVM);
|
---|
| 1468 | AssertRCReturn(rc, rc);
|
---|
| 1469 |
|
---|
| 1470 | /*
|
---|
[60307] | 1471 | * Register the MMIO range.
|
---|
| 1472 | */
|
---|
[80191] | 1473 | PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(pVM->apCpusR3[0]);
|
---|
[61072] | 1474 | RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr);
|
---|
[60469] | 1475 |
|
---|
[82026] | 1476 | rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), apicWriteMmio, apicReadMmio,
|
---|
| 1477 | IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "APIC", &pApicDev->hMmio);
|
---|
| 1478 | AssertRCReturn(rc, rc);
|
---|
[60307] | 1479 |
|
---|
| 1480 | /*
|
---|
| 1481 | * Create the APIC timers.
|
---|
| 1482 | */
|
---|
| 1483 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
| 1484 | {
|
---|
[80191] | 1485 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
|
---|
[60307] | 1486 | PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
[60398] | 1487 | RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
|
---|
[82031] | 1488 | rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
|
---|
| 1489 | pApicCpu->szTimerDesc, &pApicCpu->hTimer);
|
---|
[80062] | 1490 | AssertRCReturn(rc, rc);
|
---|
[60307] | 1491 | }
|
---|
| 1492 |
|
---|
| 1493 | /*
|
---|
| 1494 | * Register saved state callbacks.
|
---|
| 1495 | */
|
---|
[82033] | 1496 | rc = PDMDevHlpSSMRegister(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pApicDev), apicR3SaveExec, apicR3LoadExec);
|
---|
| 1497 | AssertRCReturn(rc, rc);
|
---|
[60307] | 1498 |
|
---|
| 1499 | /*
|
---|
[61566] | 1500 | * Register debugger info callbacks.
|
---|
| 1501 | *
|
---|
| 1502 | * We use separate callbacks rather than arguments so they can also be
|
---|
| 1503 | * dumped in an automated fashion while collecting crash diagnostics and
|
---|
| 1504 | * not just used during live debugging via the VM debugger.
|
---|
[60307] | 1505 | */
|
---|
[82033] | 1506 | DBGFR3InfoRegisterInternalEx(pVM, "apic", "Dumps APIC basic information.", apicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
|
---|
| 1507 | DBGFR3InfoRegisterInternalEx(pVM, "apiclvt", "Dumps APIC LVT information.", apicR3InfoLvt, DBGFINFO_FLAGS_ALL_EMTS);
|
---|
| 1508 | DBGFR3InfoRegisterInternalEx(pVM, "apictimer", "Dumps APIC timer information.", apicR3InfoTimer, DBGFINFO_FLAGS_ALL_EMTS);
|
---|
[60307] | 1509 |
|
---|
[60469] | 1510 | #ifdef VBOX_WITH_STATISTICS
|
---|
| 1511 | /*
|
---|
| 1512 | * Statistics.
|
---|
| 1513 | */
|
---|
[82033] | 1514 | #define APIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
|
---|
| 1515 | PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, \
|
---|
| 1516 | STAMUNIT_OCCURENCES, a_pszDesc, a_pszNameFmt, idCpu)
|
---|
| 1517 | # define APIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
|
---|
| 1518 | PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, \
|
---|
| 1519 | STAMUNIT_TICKS_PER_CALL, a_pszDesc, a_pszNameFmt, idCpu)
|
---|
[60469] | 1520 |
|
---|
| 1521 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
| 1522 | {
|
---|
[80191] | 1523 | PVMCPU pVCpu = pVM->apCpusR3[idCpu];
|
---|
[60469] | 1524 | PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
|
---|
| 1525 |
|
---|
[82033] | 1526 | APIC_REG_COUNTER(&pApicCpu->StatMmioReadRZ, "%u/RZ/MmioRead", "Number of APIC MMIO reads in RZ.");
|
---|
| 1527 | APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRZ, "%u/RZ/MmioWrite", "Number of APIC MMIO writes in RZ.");
|
---|
| 1528 | APIC_REG_COUNTER(&pApicCpu->StatMsrReadRZ, "%u/RZ/MsrRead", "Number of APIC MSR reads in RZ.");
|
---|
| 1529 | APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRZ, "%u/RZ/MsrWrite", "Number of APIC MSR writes in RZ.");
|
---|
[60469] | 1530 |
|
---|
[82033] | 1531 | APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "%u/R3/MmioReadR3", "Number of APIC MMIO reads in R3.");
|
---|
| 1532 | APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "%u/R3/MmioWriteR3", "Number of APIC MMIO writes in R3.");
|
---|
| 1533 | APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "%u/R3/MsrReadR3", "Number of APIC MSR reads in R3.");
|
---|
| 1534 | APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "%u/R3/MsrWriteR3", "Number of APIC MSR writes in R3.");
|
---|
[60469] | 1535 |
|
---|
[82033] | 1536 | APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending,
|
---|
| 1537 | "%u/PostInterruptAlreadyPending", "Number of times an interrupt is already pending.");
|
---|
| 1538 | APIC_REG_COUNTER(&pApicCpu->StatTimerCallback, "%u/TimerCallback", "Number of times the timer callback is invoked.");
|
---|
[60593] | 1539 |
|
---|
[82033] | 1540 | APIC_REG_COUNTER(&pApicCpu->StatTprWrite, "%u/TprWrite", "Number of TPR writes.");
|
---|
| 1541 | APIC_REG_COUNTER(&pApicCpu->StatTprRead, "%u/TprRead", "Number of TPR reads.");
|
---|
| 1542 | APIC_REG_COUNTER(&pApicCpu->StatEoiWrite, "%u/EoiWrite", "Number of EOI writes.");
|
---|
| 1543 | APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr, "%u/MaskedByTpr", "Number of times TPR masks an interrupt in apicGetInterrupt.");
|
---|
| 1544 | APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr, "%u/MaskedByPpr", "Number of times PPR masks an interrupt in apicGetInterrupt.");
|
---|
| 1545 | APIC_REG_COUNTER(&pApicCpu->StatTimerIcrWrite, "%u/TimerIcrWrite", "Number of times the timer ICR is written.");
|
---|
| 1546 | APIC_REG_COUNTER(&pApicCpu->StatIcrLoWrite, "%u/IcrLoWrite", "Number of times the ICR Lo (send IPI) is written.");
|
---|
| 1547 | APIC_REG_COUNTER(&pApicCpu->StatIcrHiWrite, "%u/IcrHiWrite", "Number of times the ICR Hi is written.");
|
---|
| 1548 | APIC_REG_COUNTER(&pApicCpu->StatIcrFullWrite, "%u/IcrFullWrite", "Number of times the ICR full (send IPI, x2APIC) is written.");
|
---|
[82792] | 1549 | APIC_REG_COUNTER(&pApicCpu->StatIdMsrRead, "%u/IdMsrRead", "Number of times the APIC-ID MSR is read.");
|
---|
[60752] | 1550 |
|
---|
[82033] | 1551 | APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs,
|
---|
[82035] | 1552 | "/PROF/CPU%u/APIC/UpdatePendingInterrupts", "Profiling of APICUpdatePendingInterrupts");
|
---|
| 1553 | APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "/PROF/CPU%u/APIC/PostInterrupt", "Profiling of APICPostInterrupt");
|
---|
[60469] | 1554 | }
|
---|
[82033] | 1555 |
|
---|
[60593] | 1556 | # undef APIC_PROF_COUNTER
|
---|
[60469] | 1557 | # undef APIC_REG_ACCESS_COUNTER
|
---|
| 1558 | #endif
|
---|
| 1559 |
|
---|
[60307] | 1560 | return VINF_SUCCESS;
|
---|
| 1561 | }
|
---|
| 1562 |
|
---|
| 1563 | #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
|
---|
| 1564 |
|
---|