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source: vbox/trunk/src/VBox/VMM/VMMR3/APIC.cpp@ 76553

Last change on this file since 76553 was 76553, checked in by vboxsync, 5 years ago
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File size: 70.3 KB

Rev	Line
[60307]	1	/* $Id: APIC.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
	2	/** @file
	3	* APIC - Advanced Programmable Interrupt Controller.
	4	*/
	5
	6	/*
[76553]	7	* Copyright (C) 2016-2019 Oracle Corporation
[60307]	8	*
	9	* This file is part of VirtualBox Open Source Edition (OSE), as
	10	* available from http://www.virtualbox.org. This file is free software;
	11	* you can redistribute it and/or modify it under the terms of the GNU
	12	* General Public License (GPL) as published by the Free Software
	13	* Foundation, in version 2 as it comes in the "COPYING" file of the
	14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
	15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
	16	*/
	17
	18
	19	/*********************************************************************************************************************************
	20	* Header Files *
	21	*********************************************************************************************************************************/
	22	#define LOG_GROUP LOG_GROUP_DEV_APIC
	23	#include <VBox/log.h>
	24	#include "APICInternal.h"
	25	#include <VBox/vmm/cpum.h>
	26	#include <VBox/vmm/hm.h>
	27	#include <VBox/vmm/mm.h>
	28	#include <VBox/vmm/pdmdev.h>
	29	#include <VBox/vmm/ssm.h>
	30	#include <VBox/vmm/vm.h>
	31
	32
	33	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
[62460]	34
	35
[60307]	36	/*********************************************************************************************************************************
	37	* Defined Constants And Macros *
	38	*********************************************************************************************************************************/
	39	/** The current APIC saved state version. */
[61584]	40	#define APIC_SAVED_STATE_VERSION 5
	41	/** VirtualBox 5.1 beta2 - pre fActiveLintX. */
	42	#define APIC_SAVED_STATE_VERSION_VBOX_51_BETA2 4
[60307]	43	/** The saved state version used by VirtualBox 5.0 and
	44	* earlier. */
[61584]	45	#define APIC_SAVED_STATE_VERSION_VBOX_50 3
[60307]	46	/** The saved state version used by VirtualBox v3 and earlier.
	47	* This does not include the config. */
[61584]	48	#define APIC_SAVED_STATE_VERSION_VBOX_30 2
[60307]	49	/** Some ancient version... */
[61584]	50	#define APIC_SAVED_STATE_VERSION_ANCIENT 1
[60307]	51
[61608]	52	#ifdef VBOX_WITH_STATISTICS
	53	# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
	54	{ (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
[63944]	55	# define X2APIC_MSRRANGE_INVALID(a_uFirst, a_uLast, a_szName) \
	56	{ (a_uFirst), (a_uLast), kCpumMsrRdFn_WriteOnly, kCpumMsrWrFn_ReadOnly, 0, 0, 0, 0, UINT64_MAX /fWrGpMask/, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
[61608]	57	#else
	58	# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
	59	{ (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName }
[63944]	60	# define X2APIC_MSRRANGE_INVALID(a_uFirst, a_uLast, a_szName) \
	61	{ (a_uFirst), (a_uLast), kCpumMsrRdFn_WriteOnly, kCpumMsrWrFn_ReadOnly, 0, 0, 0, 0, UINT64_MAX /fWrGpMask/, a_szName }
[61608]	62	#endif
[60307]	63
[61608]	64
[60307]	65	/*********************************************************************************************************************************
	66	* Global Variables *
	67	*********************************************************************************************************************************/
[61608]	68	/**
[61744]	69	* MSR range supported by the x2APIC.
	70	* See Intel spec. 10.12.2 "x2APIC Register Availability".
[61608]	71	*/
[61744]	72	static CPUMMSRRANGE const g_MsrRange_x2Apic = X2APIC_MSRRANGE(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range");
[63944]	73	static CPUMMSRRANGE const g_MsrRange_x2Apic_Invalid = X2APIC_MSRRANGE_INVALID(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range invalid");
[61608]	74	#undef X2APIC_MSRRANGE
[63944]	75	#undef X2APIC_MSRRANGE_GP
[61608]	76
[60307]	77	/** Saved state field descriptors for XAPICPAGE. */
	78	static const SSMFIELD g_aXApicPageFields[] =
	79	{
	80	SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
	81	SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
	82	SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
	83	SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
	84	SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
	85	SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
	86	SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
	87	SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
	88	SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
	89	SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
	90	SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
	91	SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
	92	SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
	93	SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
	94	SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
	95	SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
	96	SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
	97	SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
	98	SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
	99	SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
	100	SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
	101	SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
	102	SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
	103	SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
	104	SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
	105	SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
	106	SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
	107	SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
	108	SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
	109	SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
	110	SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
	111	SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
	112	SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
	113	SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
	114	SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
	115	SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
	116	SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
	117	SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
	118	SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
	119	SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
	120	SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
	121	SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
	122	SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
	123	SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
	124	SSMFIELD_ENTRY_TERM()
	125	};
	126
	127	/** Saved state field descriptors for X2APICPAGE. */
	128	static const SSMFIELD g_aX2ApicPageFields[] =
	129	{
	130	SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
	131	SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
	132	SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
	133	SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
	134	SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
	135	SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
	136	SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
	137	SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
	138	SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
	139	SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
	140	SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
	141	SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
	142	SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
	143	SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
	144	SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
	145	SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
	146	SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
	147	SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
	148	SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
	149	SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
	150	SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
	151	SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
	152	SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
	153	SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
	154	SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
	155	SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
	156	SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
	157	SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
	158	SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
	159	SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
	160	SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
	161	SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
	162	SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
	163	SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
	164	SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
	165	SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
	166	SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
	167	SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
	168	SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
	169	SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
	170	SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
	171	SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
	172	SSMFIELD_ENTRY_TERM()
	173	};
	174
	175
	176	/**
[64596]	177	* Sets the CPUID feature bits for the APIC mode.
	178	*
	179	* @param pVM The cross context VM structure.
	180	* @param enmMode The APIC mode.
	181	*/
	182	static void apicR3SetCpuIdFeatureLevel(PVM pVM, PDMAPICMODE enmMode)
	183	{
	184	switch (enmMode)
	185	{
	186	case PDMAPICMODE_NONE:
	187	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
	188	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
	189	break;
	190
	191	case PDMAPICMODE_APIC:
	192	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
	193	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
	194	break;
	195
	196	case PDMAPICMODE_X2APIC:
	197	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
	198	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
	199	break;
	200
	201	default:
	202	AssertMsgFailed(("Unknown/invalid APIC mode: %d\n", (int)enmMode));
	203	}
	204	}
	205
	206
	207	/**
[60307]	208	* Receives an INIT IPI.
	209	*
	210	* @param pVCpu The cross context virtual CPU structure.
	211	*/
	212	VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
	213	{
	214	VMCPU_ASSERT_EMT(pVCpu);
[60459]	215	LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
[73281]	216	apicInitIpi(pVCpu);
[60307]	217	}
	218
	219
	220	/**
[63888]	221	* Sets whether Hyper-V compatibility mode (MSR interface) is enabled or not.
[63632]	222	*
[63907]	223	* This mode is a hybrid of xAPIC and x2APIC modes, some caveats:
	224	* 1. MSRs are used even ones that are missing (illegal) in x2APIC like DFR.
	225	* 2. A single ICR is used by the guest to send IPIs rather than 2 ICR writes.
	226	* 3. It is unclear what the behaviour will be when invalid bits are set,
	227	* currently we follow x2APIC behaviour of causing a \#GP.
	228	*
[63632]	229	* @param pVM The cross context VM structure.
	230	* @param fHyperVCompatMode Whether the compatibility mode is enabled.
	231	*/
	232	VMMR3_INT_DECL(void) APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode)
	233	{
	234	Assert(pVM);
	235	PAPIC pApic = VM_TO_APIC(pVM);
	236	pApic->fHyperVCompatMode = fHyperVCompatMode;
[63888]	237
[71280]	238	if (fHyperVCompatMode)
	239	LogRel(("APIC: Enabling Hyper-V x2APIC compatibility mode\n"));
	240
[63888]	241	int rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
[63908]	242	AssertLogRelRC(rc);
[63632]	243	}
	244
	245
	246	/**
[60307]	247	* Helper for dumping an APIC 256-bit sparse register.
	248	*
	249	* @param pApicReg The APIC 256-bit spare register.
	250	* @param pHlp The debug output helper.
	251	*/
	252	static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
	253	{
	254	ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
	255	unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
	256	XAPIC256BITREG ApicReg;
	257	RT_ZERO(ApicReg);
	258
	259	pHlp->pfnPrintf(pHlp, " ");
	260	for (ssize_t i = cFragments - 1; i >= 0; i--)
	261	{
	262	uint32_t const uFragment = pApicReg->u[i].u32Reg;
	263	ApicReg.u[i].u32Reg = uFragment;
	264	pHlp->pfnPrintf(pHlp, "%08x", uFragment);
	265	}
	266	pHlp->pfnPrintf(pHlp, "\n");
	267
[60689]	268	uint32_t cPending = 0;
[60746]	269	pHlp->pfnPrintf(pHlp, " Pending:");
[60307]	270	for (ssize_t i = cFragments - 1; i >= 0; i--)
	271	{
	272	uint32_t uFragment = ApicReg.u[i].u32Reg;
	273	if (uFragment)
	274	{
	275	do
	276	{
	277	unsigned idxSetBit = ASMBitLastSetU32(uFragment);
	278	--idxSetBit;
	279	ASMBitClear(&uFragment, idxSetBit);
	280
	281	idxSetBit += (i * cBitsPerFragment);
[60746]	282	pHlp->pfnPrintf(pHlp, " %#02x", idxSetBit);
[60307]	283	++cPending;
	284	} while (uFragment);
	285	}
	286	}
	287	if (!cPending)
	288	pHlp->pfnPrintf(pHlp, " None");
	289	pHlp->pfnPrintf(pHlp, "\n");
	290	}
	291
	292
	293	/**
[60746]	294	* Helper for dumping an APIC pending-interrupt bitmap.
	295	*
	296	* @param pApicPib The pending-interrupt bitmap.
	297	* @param pHlp The debug output helper.
	298	*/
	299	static void apicR3DbgInfoPib(PCAPICPIB pApicPib, PCDBGFINFOHLP pHlp)
	300	{
	301	/* Copy the pending-interrupt bitmap as an APIC 256-bit sparse register. */
	302	XAPIC256BITREG ApicReg;
	303	RT_ZERO(ApicReg);
	304	ssize_t const cFragmentsDst = RT_ELEMENTS(ApicReg.u);
[63632]	305	ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->au64VectorBitmap);
	306	AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->au64VectorBitmap));
[60746]	307	for (ssize_t idxPib = cFragmentsSrc - 1, idxReg = cFragmentsDst - 1; idxPib >= 0; idxPib--, idxReg -= 2)
	308	{
[63632]	309	uint64_t const uFragment = pApicPib->au64VectorBitmap[idxPib];
[60746]	310	uint32_t const uFragmentLo = RT_LO_U32(uFragment);
	311	uint32_t const uFragmentHi = RT_HI_U32(uFragment);
	312	ApicReg.u[idxReg].u32Reg = uFragmentHi;
	313	ApicReg.u[idxReg - 1].u32Reg = uFragmentLo;
	314	}
	315
	316	/* Dump it. */
	317	apicR3DbgInfo256BitReg(&ApicReg, pHlp);
	318	}
	319
	320
	321	/**
[60307]	322	* Dumps basic APIC state.
	323	*
[61762]	324	* @param pVM The cross context VM structure.
[61566]	325	* @param pHlp The info helpers.
	326	* @param pszArgs Arguments, ignored.
[60307]	327	*/
[61566]	328	static DECLCALLBACK(void) apicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
[60307]	329	{
[61566]	330	NOREF(pszArgs);
[61575]	331	PVMCPU pVCpu = VMMGetCpu(pVM);
	332	if (!pVCpu)
	333	pVCpu = &pVM->aCpus[0];
	334
[60307]	335	PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	336	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
	337	PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
[60646]	338
	339	uint64_t const uBaseMsr = pApicCpu->uApicBaseMsr;
	340	APICMODE const enmMode = apicGetMode(uBaseMsr);
[60307]	341	bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
	342
[61741]	343	pHlp->pfnPrintf(pHlp, "APIC%u:\n", pVCpu->idCpu);
[60646]	344	pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
[61072]	345	MSR_IA32_APICBASE_GET_ADDR(uBaseMsr));
[61739]	346	pHlp->pfnPrintf(pHlp, " Mode = %u (%s)\n", enmMode, apicGetModeName(enmMode));
[60307]	347	if (fX2ApicMode)
	348	{
	349	pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
	350	pX2ApicPage->id.u32ApicId);
	351	}
	352	else
	353	pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
	354	pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
[61741]	355	pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
	356	pHlp->pfnPrintf(pHlp, " Max LVT entry index (0..N) = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
	357	pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
[60307]	358	if (!fX2ApicMode)
	359	pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
	360	pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
[61769]	361	pHlp->pfnPrintf(pHlp, " Task-priority class = %#x\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >> 4);
[61741]	362	pHlp->pfnPrintf(pHlp, " Task-priority subclass = %#x\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
[60307]	363	pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
[61769]	364	pHlp->pfnPrintf(pHlp, " Processor-priority class = %#x\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr) >> 4);
[61741]	365	pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %#x\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
[60307]	366	if (!fX2ApicMode)
	367	pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
[60473]	368	pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
[61741]	369	pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
[60307]	370	: pXApicPage->ldr.u.u8LogicalApicId);
	371	if (!fX2ApicMode)
	372	{
[60473]	373	pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
[61741]	374	pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
[60307]	375	apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
	376	}
[61741]	377	pHlp->pfnPrintf(pHlp, " SVR = %#x\n", pXApicPage->svr.all.u32Svr);
	378	pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
[60307]	379	pXApicPage->svr.u.u8SpuriousVector);
[61741]	380	pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
	381	pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
[60307]	382	pHlp->pfnPrintf(pHlp, " ISR\n");
	383	apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
	384	pHlp->pfnPrintf(pHlp, " TMR\n");
	385	apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
	386	pHlp->pfnPrintf(pHlp, " IRR\n");
	387	apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
[60746]	388	pHlp->pfnPrintf(pHlp, " PIB\n");
	389	apicR3DbgInfoPib((PCAPICPIB)pApicCpu->pvApicPibR3, pHlp);
	390	pHlp->pfnPrintf(pHlp, " Level PIB\n");
	391	apicR3DbgInfoPib(&pApicCpu->ApicPibLevel, pHlp);
[60428]	392	pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
[60307]	393	pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
[61741]	394	pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
	395	pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
	396	pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
	397	pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
[60516]	398	pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
[61741]	399	pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
	400	pXApicPage->icr_lo.u.u8Vector);
	401	pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
[60307]	402	apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
[61741]	403	pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
[60307]	404	apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
	405	if (!fX2ApicMode)
[61741]	406	pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
	407	pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
	408	pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
[60307]	409	apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
[61741]	410	pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
[60307]	411	apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
	412	pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
[61741]	413	pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
[60307]	414	: pXApicPage->icr_hi.u.u8Dest);
	415	}
	416
	417
	418	/**
	419	* Helper for dumping the LVT timer.
	420	*
	421	* @param pVCpu The cross context virtual CPU structure.
	422	* @param pHlp The debug output helper.
	423	*/
[61566]	424	static void apicR3InfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
[60307]	425	{
	426	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
	427	uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
	428	pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
[61741]	429	pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
	430	pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
	431	pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
	432	pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
[60307]	433	apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
	434	}
	435
	436
	437	/**
[61566]	438	* Dumps APIC Local Vector Table (LVT) information.
[60307]	439	*
[61762]	440	* @param pVM The cross context VM structure.
[61566]	441	* @param pHlp The info helpers.
	442	* @param pszArgs Arguments, ignored.
[60307]	443	*/
[61566]	444	static DECLCALLBACK(void) apicR3InfoLvt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
[60307]	445	{
[61566]	446	NOREF(pszArgs);
[61575]	447	PVMCPU pVCpu = VMMGetCpu(pVM);
	448	if (!pVCpu)
	449	pVCpu = &pVM->aCpus[0];
	450
[60307]	451	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
	452
[61575]	453	/*
	454	* Delivery modes available in the LVT entries. They're different (more reserved stuff) from the
	455	* ICR delivery modes and hence we don't use apicGetDeliveryMode but mostly because we want small,
	456	* fixed-length strings to fit our formatting needs here.
	457	*/
	458	static const char * const s_apszLvtDeliveryModes[] =
	459	{
	460	"Fixed ",
	461	"Rsvd ",
	462	"SMI ",
	463	"Rsvd ",
	464	"NMI ",
	465	"INIT ",
	466	"Rsvd ",
	467	"ExtINT"
	468	};
	469	/* Delivery Status. */
	470	static const char * const s_apszLvtDeliveryStatus[] =
	471	{
	472	"Idle",
	473	"Pend"
	474	};
	475	const char *pszNotApplicable = "";
[60307]	476
[61586]	477	pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC Local Vector Table (LVT):\n", pVCpu->idCpu);
[61575]	478	pHlp->pfnPrintf(pHlp, "lvt timermode mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
	479	/* Timer. */
	480	{
	481	/* Timer modes. */
	482	static const char * const s_apszLvtTimerModes[] =
	483	{
	484	"One-shot ",
	485	"Periodic ",
	486	"TSC-dline"
	487	};
	488	const uint32_t uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
	489	const XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
	490	const char *pszTimerMode = s_apszLvtTimerModes[enmTimerMode];
	491	const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtTimer);
	492	const uint8_t uDeliveryStatus = uLvtTimer & XAPIC_LVT_DELIVERY_STATUS;
	493	const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
	494	const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
	495
[61579]	496	pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
[61575]	497	"Timer",
	498	pszTimerMode,
	499	uMask,
	500	pszNotApplicable, /* TriggerMode */
	501	pszNotApplicable, /* Remote IRR */
	502	pszNotApplicable, /* Polarity */
	503	pszDeliveryStatus,
	504	pszNotApplicable, /* Delivery Mode */
	505	uVector,
	506	uVector);
	507	}
	508
[60307]	509	#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
[61575]	510	/* Thermal sensor. */
	511	{
	512	uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
	513	const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtThermal);
	514	const uint8_t uDeliveryStatus = uLvtThermal & XAPIC_LVT_DELIVERY_STATUS;
	515	const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
	516	const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtThermal);
	517	const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
	518	const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtThermal);
	519
[61579]	520	pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
[61575]	521	"Thermal",
	522	pszNotApplicable, /* Timer mode */
	523	uMask,
	524	pszNotApplicable, /* TriggerMode */
	525	pszNotApplicable, /* Remote IRR */
	526	pszNotApplicable, /* Polarity */
	527	pszDeliveryStatus,
	528	pszDeliveryMode,
	529	uVector,
	530	uVector);
	531	}
[60307]	532	#endif
	533
[61575]	534	/* Performance Monitor Counters. */
	535	{
	536	uint32_t const uLvtPerf = pXApicPage->lvt_thermal.all.u32LvtThermal;
	537	const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtPerf);
	538	const uint8_t uDeliveryStatus = uLvtPerf & XAPIC_LVT_DELIVERY_STATUS;
	539	const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
	540	const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtPerf);
	541	const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
	542	const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtPerf);
[60307]	543
[61579]	544	pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
[61575]	545	"Perf",
	546	pszNotApplicable, /* Timer mode */
	547	uMask,
	548	pszNotApplicable, /* TriggerMode */
	549	pszNotApplicable, /* Remote IRR */
	550	pszNotApplicable, /* Polarity */
	551	pszDeliveryStatus,
	552	pszDeliveryMode,
	553	uVector,
	554	uVector);
	555	}
[60307]	556
[61575]	557	/* LINT0, LINT1. */
	558	{
	559	/* LINTx name. */
	560	static const char * const s_apszLvtLint[] =
	561	{
	562	"LINT0",
	563	"LINT1"
	564	};
	565	/* Trigger mode. */
	566	static const char * const s_apszLvtTriggerModes[] =
	567	{
	568	"Edge ",
	569	"Level"
	570	};
	571	/* Polarity. */
	572	static const char * const s_apszLvtPolarity[] =
	573	{
	574	"ActiveHi",
	575	"ActiveLo"
	576	};
[60307]	577
[61575]	578	uint32_t aLvtLint[2];
	579	aLvtLint[0] = pXApicPage->lvt_lint0.all.u32LvtLint0;
	580	aLvtLint[1] = pXApicPage->lvt_lint1.all.u32LvtLint1;
	581	for (size_t i = 0; i < RT_ELEMENTS(aLvtLint); i++)
	582	{
	583	uint32_t const uLvtLint = aLvtLint[i];
	584	const char *pszLint = s_apszLvtLint[i];
	585	const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtLint);
	586	const XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvtLint);
	587	const char *pszTriggerMode = s_apszLvtTriggerModes[enmTriggerMode];
	588	const uint8_t uRemoteIrr = XAPIC_LVT_GET_REMOTE_IRR(uLvtLint);
	589	const uint8_t uPolarity = XAPIC_LVT_GET_POLARITY(uLvtLint);
	590	const char *pszPolarity = s_apszLvtPolarity[uPolarity];
	591	const uint8_t uDeliveryStatus = uLvtLint & XAPIC_LVT_DELIVERY_STATUS;
	592	const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
	593	const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint);
	594	const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
	595	const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtLint);
	596
[61579]	597	pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %u %8s %4s %6s %3u (%#x)\n",
[61575]	598	pszLint,
	599	pszNotApplicable, /* Timer mode */
	600	uMask,
	601	pszTriggerMode,
	602	uRemoteIrr,
	603	pszPolarity,
	604	pszDeliveryStatus,
	605	pszDeliveryMode,
	606	uVector,
	607	uVector);
	608	}
	609	}
	610
	611	/* Error. */
	612	{
	613	uint32_t const uLvtError = pXApicPage->lvt_thermal.all.u32LvtThermal;
	614	const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtError);
	615	const uint8_t uDeliveryStatus = uLvtError & XAPIC_LVT_DELIVERY_STATUS;
	616	const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
	617	const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtError);
	618	const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
	619	const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtError);
	620
[61579]	621	pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
[61575]	622	"Error",
	623	pszNotApplicable, /* Timer mode */
	624	uMask,
	625	pszNotApplicable, /* TriggerMode */
	626	pszNotApplicable, /* Remote IRR */
	627	pszNotApplicable, /* Polarity */
	628	pszDeliveryStatus,
	629	pszDeliveryMode,
	630	uVector,
	631	uVector);
	632	}
[60307]	633	}
	634
	635
	636	/**
[61566]	637	* Dumps the APIC timer information.
[60307]	638	*
[61762]	639	* @param pVM The cross context VM structure.
[61566]	640	* @param pHlp The info helpers.
	641	* @param pszArgs Arguments, ignored.
[60307]	642	*/
[61566]	643	static DECLCALLBACK(void) apicR3InfoTimer(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
[60307]	644	{
[61566]	645	NOREF(pszArgs);
[61575]	646	PVMCPU pVCpu = VMMGetCpu(pVM);
	647	if (!pVCpu)
	648	pVCpu = &pVM->aCpus[0];
	649
[60307]	650	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
	651	PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	652
[61586]	653	pHlp->pfnPrintf(pHlp, "VCPU[%u] Local APIC timer:\n", pVCpu->idCpu);
[60307]	654	pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
	655	pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
	656	pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
	657	pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
[60428]	658	pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
[61566]	659	apicR3InfoLvtTimer(pVCpu, pHlp);
[60307]	660	}
	661
	662
[61776]	663	#ifdef APIC_FUZZY_SSM_COMPAT_TEST
[60307]	664
	665	/**
[60695]	666	* Reads a 32-bit register at a specified offset.
	667	*
	668	* @returns The value at the specified offset.
	669	* @param pXApicPage The xAPIC page.
	670	* @param offReg The offset of the register being read.
	671	*
	672	* @remarks Duplicate of apicReadRaw32()!
	673	*/
	674	static uint32_t apicR3ReadRawR32(PCXAPICPAGE pXApicPage, uint16_t offReg)
	675	{
	676	Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
	677	uint8_t const pbXApic = (const uint8_t )pXApicPage;
	678	uint32_t const uValue = (const uint32_t )(pbXApic + offReg);
	679	return uValue;
	680	}
	681
	682
	683	/**
[60624]	684	* Helper for dumping per-VCPU APIC state to the release logger.
	685	*
	686	* This is primarily concerned about the APIC state relevant for saved-states.
	687	*
	688	* @param pVCpu The cross context virtual CPU structure.
[60630]	689	* @param pszPrefix A caller supplied prefix before dumping the state.
[60695]	690	* @param uVersion Data layout version.
[60624]	691	*/
[60695]	692	static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix, uint32_t uVersion)
[60624]	693	{
	694	PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	695
[60695]	696	LogRel(("APIC%u: %s (version %u):\n", pVCpu->idCpu, pszPrefix, uVersion));
[60624]	697
[60695]	698	switch (uVersion)
	699	{
	700	case APIC_SAVED_STATE_VERSION:
[61584]	701	case APIC_SAVED_STATE_VERSION_VBOX_51_BETA2:
[60695]	702	{
	703	/* The auxiliary state. */
	704	LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
	705	LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
[60624]	706
[60695]	707	/* The timer. */
	708	LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
	709	LogRel(("APIC%u: uHintedTimerInitialCount = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerInitialCount));
	710	LogRel(("APIC%u: uHintedTimerShift = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
[60689]	711
[60695]	712	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
	713	LogRel(("APIC%u: uTimerICR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
	714	LogRel(("APIC%u: uTimerCCR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
[60624]	715
[60695]	716	/* The PIBs. */
	717	LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
	718	LogRel(("APIC%u: Level PIB: %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), &pApicCpu->ApicPibLevel));
	719
[61584]	720	/* The LINT0, LINT1 interrupt line active states. */
	721	LogRel(("APIC%u: fActiveLint0 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint0));
	722	LogRel(("APIC%u: fActiveLint1 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint1));
	723
[60695]	724	/* The APIC page. */
	725	LogRel(("APIC%u: APIC page: %.*Rhxs\n", pVCpu->idCpu, sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
	726	break;
	727	}
	728
	729	case APIC_SAVED_STATE_VERSION_VBOX_50:
	730	case APIC_SAVED_STATE_VERSION_VBOX_30:
	731	case APIC_SAVED_STATE_VERSION_ANCIENT:
	732	{
	733	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
	734	LogRel(("APIC%u: uApicBaseMsr = %#RX32\n", pVCpu->idCpu, RT_LO_U32(pApicCpu->uApicBaseMsr)));
	735	LogRel(("APIC%u: uId = %#RX32\n", pVCpu->idCpu, pXApicPage->id.u8ApicId));
	736	LogRel(("APIC%u: uPhysId = N/A\n", pVCpu->idCpu));
	737	LogRel(("APIC%u: uArbId = N/A\n", pVCpu->idCpu));
[60731]	738	LogRel(("APIC%u: uTpr = %#RX32\n", pVCpu->idCpu, pXApicPage->tpr.u8Tpr));
[60695]	739	LogRel(("APIC%u: uSvr = %#RX32\n", pVCpu->idCpu, pXApicPage->svr.all.u32Svr));
	740	LogRel(("APIC%u: uLdr = %#x\n", pVCpu->idCpu, pXApicPage->ldr.all.u32Ldr));
	741	LogRel(("APIC%u: uDfr = %#x\n", pVCpu->idCpu, pXApicPage->dfr.all.u32Dfr));
	742
	743	for (size_t i = 0; i < 8; i++)
	744	{
[60731]	745	LogRel(("APIC%u: Isr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->isr.u[i].u32Reg));
	746	LogRel(("APIC%u: Tmr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->tmr.u[i].u32Reg));
	747	LogRel(("APIC%u: Irr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->irr.u[i].u32Reg));
[60695]	748	}
	749
	750	for (size_t i = 0; i < XAPIC_MAX_LVT_ENTRIES_P4; i++)
	751	{
	752	uint16_t const offReg = XAPIC_OFF_LVT_START + (i << 4);
[60731]	753	LogRel(("APIC%u: Lvt[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, apicR3ReadRawR32(pXApicPage, offReg)));
[60695]	754	}
	755
	756	LogRel(("APIC%u: uEsr = %#RX32\n", pVCpu->idCpu, pXApicPage->esr.all.u32Errors));
	757	LogRel(("APIC%u: uIcr_Lo = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
	758	LogRel(("APIC%u: uIcr_Hi = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
	759	LogRel(("APIC%u: uTimerDcr = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_dcr.all.u32DivideValue));
	760	LogRel(("APIC%u: uCountShift = %#RX32\n", pVCpu->idCpu, apicGetTimerShift(pXApicPage)));
	761	LogRel(("APIC%u: uInitialCount = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
	762	LogRel(("APIC%u: u64InitialCountLoadTime = %#RX64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
	763	LogRel(("APIC%u: u64NextTime / TimerCCR = %#RX64\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
	764	break;
	765	}
	766
	767	default:
	768	{
	769	LogRel(("APIC: apicR3DumpState: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
	770	break;
	771	}
	772	}
[60624]	773	}
[61776]	774
[60695]	775	#endif /* APIC_FUZZY_SSM_COMPAT_TEST */
[60624]	776
	777	/**
[60307]	778	* Worker for saving per-VM APIC data.
	779	*
	780	* @returns VBox status code.
	781	* @param pVM The cross context VM structure.
	782	* @param pSSM The SSM handle.
	783	*/
	784	static int apicR3SaveVMData(PVM pVM, PSSMHANDLE pSSM)
	785	{
	786	PAPIC pApic = VM_TO_APIC(pVM);
	787	SSMR3PutU32(pSSM, pVM->cCpus);
	788	SSMR3PutBool(pSSM, pApic->fIoApicPresent);
[61776]	789	return SSMR3PutU32(pSSM, pApic->enmMaxMode);
[60307]	790	}
	791
	792
	793	/**
[60605]	794	* Worker for loading per-VM APIC data.
	795	*
	796	* @returns VBox status code.
	797	* @param pVM The cross context VM structure.
	798	* @param pSSM The SSM handle.
	799	*/
	800	static int apicR3LoadVMData(PVM pVM, PSSMHANDLE pSSM)
	801	{
	802	PAPIC pApic = VM_TO_APIC(pVM);
	803
	804	/* Load and verify number of CPUs. */
	805	uint32_t cCpus;
	806	int rc = SSMR3GetU32(pSSM, &cCpus);
	807	AssertRCReturn(rc, rc);
	808	if (cCpus != pVM->cCpus)
	809	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
	810
	811	/* Load and verify I/O APIC presence. */
	812	bool fIoApicPresent;
	813	rc = SSMR3GetBool(pSSM, &fIoApicPresent);
	814	AssertRCReturn(rc, rc);
	815	if (fIoApicPresent != pApic->fIoApicPresent)
	816	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
	817	fIoApicPresent, pApic->fIoApicPresent);
	818
[61776]	819	/* Load and verify configured max APIC mode. */
	820	uint32_t uSavedMaxApicMode;
	821	rc = SSMR3GetU32(pSSM, &uSavedMaxApicMode);
[60605]	822	AssertRCReturn(rc, rc);
[61777]	823	if (uSavedMaxApicMode != (uint32_t)pApic->enmMaxMode)
[61776]	824	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u config=%u"),
	825	uSavedMaxApicMode, pApic->enmMaxMode);
[60605]	826	return VINF_SUCCESS;
	827	}
	828
	829
	830	/**
[60689]	831	* Worker for loading per-VCPU APIC data for legacy (old) saved-states.
	832	*
	833	* @returns VBox status code.
	834	* @param pVCpu The cross context virtual CPU structure.
	835	* @param pSSM The SSM handle.
	836	* @param uVersion Data layout version.
	837	*/
[62656]	838	static int apicR3LoadLegacyVCpuData(PVMCPU pVCpu, PSSMHANDLE pSSM, uint32_t uVersion)
[60689]	839	{
	840	AssertReturn(uVersion <= APIC_SAVED_STATE_VERSION_VBOX_50, VERR_NOT_SUPPORTED);
	841
	842	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	843	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
	844
	845	uint32_t uApicBaseLo;
	846	int rc = SSMR3GetU32(pSSM, &uApicBaseLo);
	847	AssertRCReturn(rc, rc);
	848	pApicCpu->uApicBaseMsr = uApicBaseLo;
[60716]	849	Log2(("APIC%u: apicR3LoadLegacyVCpuData: uApicBaseMsr=%#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
[60689]	850
	851	switch (uVersion)
	852	{
	853	case APIC_SAVED_STATE_VERSION_VBOX_50:
	854	case APIC_SAVED_STATE_VERSION_VBOX_30:
	855	{
	856	uint32_t uApicId, uPhysApicId, uArbId;
	857	SSMR3GetU32(pSSM, &uApicId); pXApicPage->id.u8ApicId = uApicId;
	858	SSMR3GetU32(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
	859	SSMR3GetU32(pSSM, &uArbId); NOREF(uArbId); /* ArbID is & was unused. */
	860	break;
	861	}
	862
[60716]	863	case APIC_SAVED_STATE_VERSION_ANCIENT:
	864	{
	865	uint8_t uPhysApicId;
	866	SSMR3GetU8(pSSM, &pXApicPage->id.u8ApicId);
	867	SSMR3GetU8(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
	868	break;
	869	}
	870
[60689]	871	default:
	872	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
	873	}
	874
	875	uint32_t u32Tpr;
	876	SSMR3GetU32(pSSM, &u32Tpr);
[61078]	877	pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR_VALID;
[60689]	878
	879	SSMR3GetU32(pSSM, &pXApicPage->svr.all.u32Svr);
	880	SSMR3GetU8(pSSM, &pXApicPage->ldr.u.u8LogicalApicId);
	881
	882	uint8_t uDfr;
	883	SSMR3GetU8(pSSM, &uDfr);
	884	pXApicPage->dfr.u.u4Model = uDfr >> 4;
	885
	886	AssertCompile(RT_ELEMENTS(pXApicPage->isr.u) == 8);
	887	AssertCompile(RT_ELEMENTS(pXApicPage->tmr.u) == 8);
	888	AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 8);
	889	for (size_t i = 0; i < 8; i++)
	890	{
	891	SSMR3GetU32(pSSM, &pXApicPage->isr.u[i].u32Reg);
	892	SSMR3GetU32(pSSM, &pXApicPage->tmr.u[i].u32Reg);
	893	SSMR3GetU32(pSSM, &pXApicPage->irr.u[i].u32Reg);
	894	}
	895
	896	SSMR3GetU32(pSSM, &pXApicPage->lvt_timer.all.u32LvtTimer);
	897	SSMR3GetU32(pSSM, &pXApicPage->lvt_thermal.all.u32LvtThermal);
	898	SSMR3GetU32(pSSM, &pXApicPage->lvt_perf.all.u32LvtPerf);
	899	SSMR3GetU32(pSSM, &pXApicPage->lvt_lint0.all.u32LvtLint0);
	900	SSMR3GetU32(pSSM, &pXApicPage->lvt_lint1.all.u32LvtLint1);
	901	SSMR3GetU32(pSSM, &pXApicPage->lvt_error.all.u32LvtError);
	902
	903	SSMR3GetU32(pSSM, &pXApicPage->esr.all.u32Errors);
	904	SSMR3GetU32(pSSM, &pXApicPage->icr_lo.all.u32IcrLo);
	905	SSMR3GetU32(pSSM, &pXApicPage->icr_hi.all.u32IcrHi);
	906
	907	uint32_t u32TimerShift;
	908	SSMR3GetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue);
	909	SSMR3GetU32(pSSM, &u32TimerShift);
[61041]	910	/*
	911	* Old implementation may have left the timer shift uninitialized until
	912	* the timer configuration register was written. Unfortunately zero is
	913	* also a valid timer shift value, so we're just going to ignore it
	914	* completely. The shift count can always be derived from the DCR.
	915	* See @bugref{8245#c98}.
[60858]	916	*/
[60689]	917	uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
	918
	919	SSMR3GetU32(pSSM, &pXApicPage->timer_icr.u32InitialCount);
	920	SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial);
	921	uint64_t uNextTS;
	922	rc = SSMR3GetU64(pSSM, &uNextTS); AssertRCReturn(rc, rc);
	923	if (uNextTS >= pApicCpu->u64TimerInitial + ((pXApicPage->timer_icr.u32InitialCount + 1) << uTimerShift))
	924	pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
	925
	926	rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);
	927	AssertRCReturn(rc, rc);
	928	Assert(pApicCpu->uHintedTimerInitialCount == 0);
	929	Assert(pApicCpu->uHintedTimerShift == 0);
	930	if (TMTimerIsActive(pApicCpu->pTimerR3))
	931	{
	932	uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
	933	apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
	934	}
	935
	936	return rc;
	937	}
	938
[60307]	939
	940	/**
	941	* @copydoc FNSSMDEVSAVEEXEC
	942	*/
	943	static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
	944	{
[62656]	945	PVM pVM = PDMDevHlpGetVM(pDevIns);
[60307]	946	AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
	947
[60652]	948	LogFlow(("APIC: apicR3SaveExec\n"));
	949
[60307]	950	/* Save per-VM data. */
	951	int rc = apicR3SaveVMData(pVM, pSSM);
	952	AssertRCReturn(rc, rc);
	953
	954	/* Save per-VCPU data.*/
	955	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
	956	{
	957	PVMCPU pVCpu = &pVM->aCpus[idCpu];
	958	PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	959
[60804]	960	/* Update interrupts from the pending-interrupts bitmaps to the IRR. */
	961	APICUpdatePendingInterrupts(pVCpu);
	962
[60601]	963	/* Save the auxiliary data. */
[60307]	964	SSMR3PutU64(pSSM, pApicCpu->uApicBaseMsr);
[60601]	965	SSMR3PutU32(pSSM, pApicCpu->uEsrInternal);
[60307]	966
[60601]	967	/* Save the APIC page. */
	968	if (XAPIC_IN_X2APIC_MODE(pVCpu))
[60605]	969	SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
[60601]	970	else
[60605]	971	SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
[60601]	972
	973	/* Save the timer. */
[60689]	974	SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
[60601]	975	TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
[60624]	976
[61584]	977	/* Save the LINT0, LINT1 interrupt line states. */
	978	SSMR3PutBool(pSSM, pApicCpu->fActiveLint0);
	979	SSMR3PutBool(pSSM, pApicCpu->fActiveLint1);
	980
[60695]	981	#if defined(APIC_FUZZY_SSM_COMPAT_TEST) \|\| defined(DEBUG_ramshankar)
	982	apicR3DumpState(pVCpu, "Saved state", APIC_SAVED_STATE_VERSION);
[60624]	983	#endif
[60307]	984	}
	985
[60695]	986	#ifdef APIC_FUZZY_SSM_COMPAT_TEST
	987	/* The state is fuzzy, don't even bother trying to load the guest. */
	988	return VERR_INVALID_STATE;
	989	#else
[60307]	990	return rc;
[60695]	991	#endif
[60307]	992	}
	993
	994
	995	/**
	996	* @copydoc FNSSMDEVLOADEXEC
	997	*/
	998	static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
	999	{
[62656]	1000	PVM pVM = PDMDevHlpGetVM(pDevIns);
[60689]	1001
[60307]	1002	AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
[60689]	1003	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
[60307]	1004
[60689]	1005	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
[60652]	1006
[60307]	1007	/* Weed out invalid versions. */
[61336]	1008	if ( uVersion != APIC_SAVED_STATE_VERSION
[61584]	1009	&& uVersion != APIC_SAVED_STATE_VERSION_VBOX_51_BETA2
[61336]	1010	&& uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
	1011	&& uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
	1012	&& uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
[60307]	1013	{
[60689]	1014	LogRel(("APIC: apicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
[60307]	1015	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
	1016	}
	1017
[60689]	1018	int rc = VINF_SUCCESS;
[60307]	1019	if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
	1020	{
[60689]	1021	rc = apicR3LoadVMData(pVM, pSSM);
	1022	AssertRCReturn(rc, rc);
[60307]	1023
	1024	if (uVersion == APIC_SAVED_STATE_VERSION)
[60605]	1025	{ /* Load any new additional per-VM data. */ }
[60307]	1026	}
	1027
	1028	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
	1029	{
	1030	PVMCPU pVCpu = &pVM->aCpus[idCpu];
	1031	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	1032
[61797]	1033	if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_50)
[60307]	1034	{
[60605]	1035	/* Load the auxiliary data. */
	1036	SSMR3GetU64(pSSM, (uint64_t *)&pApicCpu->uApicBaseMsr);
	1037	SSMR3GetU32(pSSM, &pApicCpu->uEsrInternal);
	1038
	1039	/* Load the APIC page. */
	1040	if (XAPIC_IN_X2APIC_MODE(pVCpu))
[60689]	1041	SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
[60605]	1042	else
[60689]	1043	SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
[60605]	1044
	1045	/* Load the timer. */
[60689]	1046	rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
[60605]	1047	rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM); AssertRCReturn(rc, rc);
	1048	Assert(pApicCpu->uHintedTimerShift == 0);
	1049	Assert(pApicCpu->uHintedTimerInitialCount == 0);
	1050	if (TMTimerIsActive(pApicCpu->pTimerR3))
	1051	{
	1052	PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
	1053	uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
	1054	uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
	1055	apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
	1056	}
[61584]	1057
	1058	/* Load the LINT0, LINT1 interrupt line states. */
	1059	if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_51_BETA2)
	1060	{
	1061	SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint0);
	1062	SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint1);
	1063	}
[60307]	1064	}
	1065	else
	1066	{
[62656]	1067	rc = apicR3LoadLegacyVCpuData(pVCpu, pSSM, uVersion);
[60689]	1068	AssertRCReturn(rc, rc);
[60307]	1069	}
[60689]	1070
[61776]	1071	/*
	1072	* Check that we're still good wrt restored data, then tell CPUM about the current CPUID[1].EDX[9] visibility.
	1073	*/
	1074	rc = SSMR3HandleGetStatus(pSSM);
	1075	AssertRCReturn(rc, rc);
	1076	CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN));
	1077
[60695]	1078	#if defined(APIC_FUZZY_SSM_COMPAT_TEST) \|\| defined(DEBUG_ramshankar)
	1079	apicR3DumpState(pVCpu, "Loaded state", uVersion);
[60689]	1080	#endif
[60307]	1081	}
	1082
	1083	return rc;
	1084	}
	1085
	1086
	1087	/**
	1088	* The timer callback.
	1089	*
	1090	* @param pDevIns The device instance.
	1091	* @param pTimer The timer handle.
	1092	* @param pvUser Opaque pointer to the VMCPU.
	1093	*
	1094	* @thread Any.
	1095	* @remarks Currently this function is invoked on the last EMT, see @c
	1096	* idTimerCpu in tmR3TimerCallback(). However, the code does -not-
	1097	* rely on this and is designed to work with being invoked on any
	1098	* thread.
	1099	*/
	1100	static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
	1101	{
	1102	PVMCPU pVCpu = (PVMCPU)pvUser;
	1103	Assert(TMTimerIsLockOwner(pTimer));
	1104	Assert(pVCpu);
[60464]	1105	LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
[62656]	1106	RT_NOREF2(pDevIns, pTimer);
[60307]	1107
	1108	PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
[62656]	1109	uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
	1110	#ifdef VBOX_WITH_STATISTICS
[60632]	1111	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	1112	STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
[62656]	1113	#endif
[60307]	1114	if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
	1115	{
	1116	uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
[60650]	1117	Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
[65380]	1118	apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE, 0 /* uSrcTag */);
[60307]	1119	}
	1120
	1121	XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
	1122	switch (enmTimerMode)
	1123	{
	1124	case XAPICTIMERMODE_PERIODIC:
	1125	{
	1126	/* The initial-count register determines if the periodic timer is re-armed. */
	1127	uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
	1128	pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
	1129	if (uInitialCount)
[60468]	1130	{
[60650]	1131	Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
[61794]	1132	apicStartTimer(pVCpu, uInitialCount);
[60468]	1133	}
[60307]	1134	break;
	1135	}
	1136
	1137	case XAPICTIMERMODE_ONESHOT:
	1138	{
	1139	pXApicPage->timer_ccr.u32CurrentCount = 0;
	1140	break;
	1141	}
	1142
	1143	case XAPICTIMERMODE_TSC_DEADLINE:
	1144	{
	1145	/** @todo implement TSC deadline. */
	1146	AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
	1147	break;
	1148	}
	1149	}
	1150	}
	1151
	1152
	1153	/**
	1154	* @interface_method_impl{PDMDEVREG,pfnReset}
	1155	*/
	1156	static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
	1157	{
[62656]	1158	PVM pVM = PDMDevHlpGetVM(pDevIns);
[60307]	1159	VM_ASSERT_EMT0(pVM);
	1160	VM_ASSERT_IS_NOT_RUNNING(pVM);
	1161
[60652]	1162	LogFlow(("APIC: apicR3Reset\n"));
	1163
[60307]	1164	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
	1165	{
	1166	PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
	1167	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
	1168
[60469]	1169	if (TMTimerIsActive(pApicCpu->pTimerR3))
	1170	TMTimerStop(pApicCpu->pTimerR3);
[60307]	1171
[73281]	1172	apicResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
[60307]	1173
	1174	/* Clear the interrupt pending force flag. */
[61794]	1175	apicClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
[60307]	1176	}
	1177	}
	1178
	1179
	1180	/**
	1181	* @interface_method_impl{PDMDEVREG,pfnRelocate}
	1182	*/
	1183	static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
	1184	{
	1185	PVM pVM = PDMDevHlpGetVM(pDevIns);
	1186	PAPIC pApic = VM_TO_APIC(pVM);
	1187	PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
[60469]	1188
[60456]	1189	LogFlow(("APIC: apicR3Relocate: pVM=%p pDevIns=%p offDelta=%RGi\n", pVM, pDevIns, offDelta));
[60307]	1190
[64596]	1191	pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
[60307]	1192
[60716]	1193	pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
	1194	pApic->pvApicPibRC += offDelta;
[60364]	1195
[60307]	1196	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
	1197	{
	1198	PVMCPU pVCpu = &pVM->aCpus[idCpu];
	1199	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	1200	pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
[60364]	1201
[60716]	1202	pApicCpu->pvApicPageRC += offDelta;
	1203	pApicCpu->pvApicPibRC += offDelta;
	1204	Log2(("APIC%u: apicR3Relocate: APIC PIB at %RGv\n", pVCpu->idCpu, pApicCpu->pvApicPibRC));
[60307]	1205	}
	1206	}
	1207
	1208
	1209	/**
[60398]	1210	* Terminates the APIC state.
	1211	*
	1212	* @param pVM The cross context VM structure.
	1213	*/
	1214	static void apicR3TermState(PVM pVM)
	1215	{
	1216	PAPIC pApic = VM_TO_APIC(pVM);
[60456]	1217	LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
	1218
[60468]	1219	/* Unmap and free the PIB. */
	1220	if (pApic->pvApicPibR3 != NIL_RTR3PTR)
[60398]	1221	{
	1222	size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
	1223	if (cPages == 1)
[60689]	1224	SUPR3PageFreeEx(pApic->pvApicPibR3, cPages);
[60398]	1225	else
[60689]	1226	SUPR3ContFree(pApic->pvApicPibR3, cPages);
[60468]	1227	pApic->pvApicPibR3 = NIL_RTR3PTR;
	1228	pApic->pvApicPibR0 = NIL_RTR0PTR;
	1229	pApic->pvApicPibRC = NIL_RTRCPTR;
[60398]	1230	}
	1231
[60468]	1232	/* Unmap and free the virtual-APIC pages. */
[60398]	1233	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
	1234	{
[60468]	1235	PVMCPU pVCpu = &pVM->aCpus[idCpu];
	1236	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	1237
	1238	pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
	1239	pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
	1240	pApicCpu->pvApicPibRC = NIL_RTRCPTR;
	1241
	1242	if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
[60398]	1243	{
[60689]	1244	SUPR3PageFreeEx(pApicCpu->pvApicPageR3, 1 /* cPages */);
[60468]	1245	pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
	1246	pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
	1247	pApicCpu->pvApicPageRC = NIL_RTRCPTR;
[60398]	1248	}
	1249	}
	1250	}
	1251
	1252
	1253	/**
	1254	* Initializes the APIC state.
	1255	*
	1256	* @returns VBox status code.
	1257	* @param pVM The cross context VM structure.
	1258	*/
	1259	static int apicR3InitState(PVM pVM)
	1260	{
	1261	PAPIC pApic = VM_TO_APIC(pVM);
[60456]	1262	LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
[60398]	1263
[60468]	1264	/* With hardware virtualization, we don't need to map the APIC in GC. */
[70948]	1265	bool const fNeedsGCMapping = VM_IS_RAW_MODE_ENABLED(pVM);
[60468]	1266
[60398]	1267	/*
	1268	* Allocate and map the pending-interrupt bitmap (PIB).
	1269	*
	1270	* We allocate all the VCPUs' PIBs contiguously in order to save space as
	1271	* physically contiguous allocations are rounded to a multiple of page size.
	1272	*/
[60468]	1273	Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
	1274	Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
	1275	Assert(pApic->pvApicPibRC == NIL_RTRCPTR);
[60398]	1276	pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), PAGE_SIZE);
	1277	size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
	1278	if (cPages == 1)
	1279	{
	1280	SUPPAGE SupApicPib;
	1281	RT_ZERO(SupApicPib);
	1282	SupApicPib.Phys = NIL_RTHCPHYS;
[60689]	1283	int rc = SUPR3PageAllocEx(1 /* cPages /, 0 / fFlags */, &pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
[60398]	1284	if (RT_SUCCESS(rc))
	1285	{
	1286	pApic->HCPhysApicPib = SupApicPib.Phys;
[60468]	1287	AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
[60398]	1288	}
	1289	else
	1290	{
	1291	LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
	1292	return rc;
	1293	}
	1294	}
	1295	else
	1296	pApic->pvApicPibR3 = SUPR3ContAlloc(cPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
	1297
	1298	if (pApic->pvApicPibR3)
	1299	{
[60468]	1300	AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
	1301	AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
[60435]	1302
[60468]	1303	/* Initialize the PIB. */
[60689]	1304	RT_BZERO(pApic->pvApicPibR3, pApic->cbApicPib);
[60468]	1305
	1306	/* Map the PIB into GC. */
	1307	if (fNeedsGCMapping)
[60398]	1308	{
[60646]	1309	pApic->pvApicPibRC = NIL_RTRCPTR;
[60689]	1310	int rc = MMR3HyperMapHCPhys(pVM, pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
[60398]	1311	"APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
	1312	if (RT_FAILURE(rc))
	1313	{
[60468]	1314	LogRel(("APIC: Failed to map %u bytes for the pending-interrupt bitmap into GC, rc=%Rrc\n", pApic->cbApicPib,
	1315	rc));
[60398]	1316	apicR3TermState(pVM);
	1317	return rc;
	1318	}
[60468]	1319
	1320	AssertLogRelReturn(pApic->pvApicPibRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
[60398]	1321	}
	1322
[60468]	1323	/*
	1324	* Allocate the map the virtual-APIC pages.
	1325	*/
[60398]	1326	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
	1327	{
	1328	PVMCPU pVCpu = &pVM->aCpus[idCpu];
	1329	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	1330
	1331	SUPPAGE SupApicPage;
	1332	RT_ZERO(SupApicPage);
	1333	SupApicPage.Phys = NIL_RTHCPHYS;
	1334
[60542]	1335	Assert(pVCpu->idCpu == idCpu);
[60468]	1336	Assert(pApicCpu->pvApicPageR3 == NIL_RTR0PTR);
	1337	Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
	1338	Assert(pApicCpu->pvApicPageRC == NIL_RTRCPTR);
	1339	AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
[60398]	1340	pApicCpu->cbApicPage = sizeof(XAPICPAGE);
[60689]	1341	int rc = SUPR3PageAllocEx(1 /* cPages /, 0 / fFlags */, &pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
[60398]	1342	&SupApicPage);
	1343	if (RT_SUCCESS(rc))
	1344	{
[60468]	1345	AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR, VERR_INTERNAL_ERROR);
	1346	AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
[60398]	1347	pApicCpu->HCPhysApicPage = SupApicPage.Phys;
	1348
	1349	/* Map the virtual-APIC page into GC. */
[60468]	1350	if (fNeedsGCMapping)
[60398]	1351	{
[60689]	1352	rc = MMR3HyperMapHCPhys(pVM, pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
[60398]	1353	pApicCpu->cbApicPage, "APIC", (PRTGCPTR)&pApicCpu->pvApicPageRC);
	1354	if (RT_FAILURE(rc))
	1355	{
[60468]	1356	LogRel(("APIC%u: Failed to map %u bytes for the virtual-APIC page into GC, rc=%Rrc", idCpu,
[60398]	1357	pApicCpu->cbApicPage, rc));
	1358	apicR3TermState(pVM);
	1359	return rc;
	1360	}
[60468]	1361
	1362	AssertLogRelReturn(pApicCpu->pvApicPageRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
[60398]	1363	}
	1364
	1365	/* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
[60646]	1366	uint32_t const offApicPib = idCpu * sizeof(APICPIB);
[60456]	1367	pApicCpu->pvApicPibR0 = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
	1368	pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
[60468]	1369	if (fNeedsGCMapping)
[60716]	1370	pApicCpu->pvApicPibRC = (RTRCPTR)((RTRCUINTPTR)pApic->pvApicPibRC + offApicPib);
[60398]	1371
	1372	/* Initialize the virtual-APIC state. */
[60689]	1373	RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
[73281]	1374	apicResetCpu(pVCpu, true /* fResetApicBaseMsr */);
[60456]	1375
[60468]	1376	#ifdef DEBUG_ramshankar
	1377	Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
	1378	Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR);
	1379	Assert(!fNeedsGCMapping \|\| pApicCpu->pvApicPibRC != NIL_RTRCPTR);
	1380	Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
	1381	Assert(pApicCpu->pvApicPageR0 != NIL_RTR0PTR);
	1382	Assert(!fNeedsGCMapping \|\| pApicCpu->pvApicPageRC != NIL_RTRCPTR);
[60716]	1383	Assert(!fNeedsGCMapping \|\| pApic->pvApicPibRC == pVM->aCpus[0].apic.s.pvApicPibRC);
[60456]	1384	#endif
[60398]	1385	}
	1386	else
	1387	{
[61124]	1388	LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", idCpu, pApicCpu->cbApicPage, rc));
[60398]	1389	apicR3TermState(pVM);
[60468]	1390	return rc;
[60398]	1391	}
	1392	}
	1393
[60468]	1394	#ifdef DEBUG_ramshankar
	1395	Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
	1396	Assert(pApic->pvApicPibR0 != NIL_RTR0PTR);
	1397	Assert(!fNeedsGCMapping \|\| pApic->pvApicPibRC != NIL_RTRCPTR);
[60456]	1398	#endif
[60398]	1399	return VINF_SUCCESS;
	1400	}
	1401
[60468]	1402	LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
	1403	pApic->cbApicPib));
[60398]	1404	return VERR_NO_MEMORY;
	1405	}
	1406
	1407
	1408	/**
	1409	* @interface_method_impl{PDMDEVREG,pfnDestruct}
	1410	*/
	1411	static DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
	1412	{
	1413	PVM pVM = PDMDevHlpGetVM(pDevIns);
[60468]	1414	LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
	1415
[60398]	1416	apicR3TermState(pVM);
	1417	return VINF_SUCCESS;
	1418	}
	1419
	1420
	1421	/**
	1422	* @interface_method_impl{PDMDEVREG,pfnInitComplete}
	1423	*/
	1424	static DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
	1425	{
	1426	PVM pVM = PDMDevHlpGetVM(pDevIns);
	1427	PAPIC pApic = VM_TO_APIC(pVM);
	1428
[60468]	1429	/*
	1430	* Init APIC settings that rely on HM and CPUM configurations.
	1431	*/
[60398]	1432	CPUMCPUIDLEAF CpuLeaf;
	1433	int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
	1434	AssertRCReturn(rc, rc);
[60468]	1435
[60398]	1436	pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
	1437	pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
	1438	pApic->fVirtApicRegsEnabled = HMR3IsVirtApicRegsEnabled(pVM->pUVM);
	1439
	1440	LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
	1441	pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
[60464]	1442
[60398]	1443	return VINF_SUCCESS;
	1444	}
	1445
	1446
	1447	/**
[60307]	1448	* @interface_method_impl{PDMDEVREG,pfnConstruct}
	1449	*/
	1450	static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
	1451	{
	1452	/*
	1453	* Validate inputs.
	1454	*/
[62656]	1455	Assert(iInstance == 0); NOREF(iInstance);
[60307]	1456	Assert(pDevIns);
	1457
	1458	PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
	1459	PVM pVM = PDMDevHlpGetVM(pDevIns);
	1460	PAPIC pApic = VM_TO_APIC(pVM);
	1461
	1462	/*
[61776]	1463	* Init the data.
	1464	*/
	1465	pApicDev->pDevInsR3 = pDevIns;
	1466	pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
	1467	pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
	1468
	1469	pApic->pApicDevR0 = PDMINS_2_DATA_R0PTR(pDevIns);
	1470	pApic->pApicDevR3 = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
	1471	pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
	1472
	1473	/*
[60364]	1474	* Validate APIC settings.
[60307]	1475	*/
[61116]	1476	if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
	1477	"Mode\0"
	1478	"IOAPIC\0"
	1479	"NumCPUs\0"))
	1480	{
	1481	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
	1482	N_("APIC configuration error: unknown option specified"));
	1483	}
[60307]	1484
[61116]	1485	int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pApic->fRZEnabled, true);
[60307]	1486	AssertLogRelRCReturn(rc, rc);
	1487
	1488	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
	1489	AssertLogRelRCReturn(rc, rc);
	1490
[61776]	1491	/* Max APIC feature level. */
	1492	uint8_t uMaxMode;
	1493	rc = CFGMR3QueryU8Def(pCfg, "Mode", &uMaxMode, PDMAPICMODE_APIC);
[60307]	1494	AssertLogRelRCReturn(rc, rc);
[61776]	1495	switch ((PDMAPICMODE)uMaxMode)
[60307]	1496	{
[61776]	1497	case PDMAPICMODE_NONE:
[64663]	1498	LogRel(("APIC: APIC maximum mode configured as 'None', effectively disabled/not-present!\n"));
[61776]	1499	case PDMAPICMODE_APIC:
	1500	case PDMAPICMODE_X2APIC:
[60720]	1501	break;
[60307]	1502	default:
[61776]	1503	return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %d unknown.", uMaxMode);
[60307]	1504	}
[61776]	1505	pApic->enmMaxMode = (PDMAPICMODE)uMaxMode;
[60307]	1506
	1507	/*
	1508	* Disable automatic PDM locking for this device.
	1509	*/
	1510	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
	1511	AssertRCReturn(rc, rc);
	1512
	1513	/*
[61776]	1514	* Register the APIC with PDM.
[60307]	1515	*/
[64655]	1516	rc = PDMDevHlpAPICRegister(pDevIns);
[60307]	1517	AssertLogRelRCReturn(rc, rc);
	1518
	1519	/*
[61776]	1520	* Initialize the APIC state.
	1521	*/
	1522	if (pApic->enmMaxMode == PDMAPICMODE_X2APIC)
	1523	{
	1524	rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
	1525	AssertLogRelRCReturn(rc, rc);
	1526	}
[63944]	1527	else
	1528	{
	1529	/* We currently don't have a function to remove the range, so we register an range which will cause a #GP. */
	1530	rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic_Invalid);
	1531	AssertLogRelRCReturn(rc, rc);
	1532	}
[61776]	1533
	1534	/* Tell CPUM about the APIC feature level so it can adjust APICBASE MSR GP mask and CPUID bits. */
[64596]	1535	apicR3SetCpuIdFeatureLevel(pVM, pApic->enmMaxMode);
[64655]	1536	/* Finally, initialize the state. */
[61776]	1537	rc = apicR3InitState(pVM);
	1538	AssertRCReturn(rc, rc);
	1539
	1540	/*
[60307]	1541	* Register the MMIO range.
	1542	*/
	1543	PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]);
[61072]	1544	RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr);
[60469]	1545
[60428]	1546	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */,
[60307]	1547	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
[61794]	1548	apicWriteMmio, apicReadMmio, "APIC");
[60307]	1549	if (RT_FAILURE(rc))
	1550	return rc;
	1551
	1552	if (pApic->fRZEnabled)
	1553	{
	1554	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTRCPTR /pvUser/,
[61794]	1555	"apicWriteMmio", "apicReadMmio");
[60307]	1556	if (RT_FAILURE(rc))
	1557	return rc;
	1558
	1559	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTR0PTR /pvUser/,
[61794]	1560	"apicWriteMmio", "apicReadMmio");
[60307]	1561	if (RT_FAILURE(rc))
	1562	return rc;
	1563	}
	1564
	1565	/*
	1566	* Create the APIC timers.
	1567	*/
	1568	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
	1569	{
	1570	PVMCPU pVCpu = &pVM->aCpus[idCpu];
	1571	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
[60398]	1572	RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
[60307]	1573	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
	1574	pApicCpu->szTimerDesc, &pApicCpu->pTimerR3);
	1575	if (RT_SUCCESS(rc))
	1576	{
	1577	pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
	1578	pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
	1579	}
	1580	else
	1581	return rc;
	1582	}
	1583
	1584	/*
	1585	* Register saved state callbacks.
	1586	*/
	1587	rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(pApicDev), NULL /pfnLiveExec*/, apicR3SaveExec,
	1588	apicR3LoadExec);
	1589	if (RT_FAILURE(rc))
	1590	return rc;
	1591
	1592	/*
[61566]	1593	* Register debugger info callbacks.
	1594	*
	1595	* We use separate callbacks rather than arguments so they can also be
	1596	* dumped in an automated fashion while collecting crash diagnostics and
	1597	* not just used during live debugging via the VM debugger.
[60307]	1598	*/
[61575]	1599	rc = DBGFR3InfoRegisterInternalEx(pVM, "apic", "Dumps APIC basic information.", apicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
	1600	rc \|= DBGFR3InfoRegisterInternalEx(pVM, "apiclvt", "Dumps APIC LVT information.", apicR3InfoLvt, DBGFINFO_FLAGS_ALL_EMTS);
	1601	rc \|= DBGFR3InfoRegisterInternalEx(pVM, "apictimer", "Dumps APIC timer information.", apicR3InfoTimer, DBGFINFO_FLAGS_ALL_EMTS);
[60469]	1602	AssertRCReturn(rc, rc);
[60307]	1603
[60469]	1604	#ifdef VBOX_WITH_STATISTICS
	1605	/*
	1606	* Statistics.
	1607	*/
	1608	#define APIC_REG_COUNTER(a_Reg, a_Desc, a_Key) \
	1609	do { \
	1610	rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, a_Desc, a_Key, idCpu); \
	1611	AssertRCReturn(rc, rc); \
	1612	} while(0)
	1613
[60516]	1614	#define APIC_PROF_COUNTER(a_Reg, a_Desc, a_Key) \
	1615	do { \
	1616	rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, a_Desc, a_Key, \
	1617	idCpu); \
	1618	AssertRCReturn(rc, rc); \
	1619	} while(0)
	1620
[60469]	1621	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
	1622	{
	1623	PVMCPU pVCpu = &pVM->aCpus[idCpu];
	1624	PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
	1625
[61848]	1626	APIC_REG_COUNTER(&pApicCpu->StatMmioReadRZ, "Number of APIC MMIO reads in RZ.", "/Devices/APIC/%u/RZ/MmioRead");
	1627	APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRZ, "Number of APIC MMIO writes in RZ.", "/Devices/APIC/%u/RZ/MmioWrite");
	1628	APIC_REG_COUNTER(&pApicCpu->StatMsrReadRZ, "Number of APIC MSR reads in RZ.", "/Devices/APIC/%u/RZ/MsrRead");
	1629	APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRZ, "Number of APIC MSR writes in RZ.", "/Devices/APIC/%u/RZ/MsrWrite");
[60469]	1630
	1631	APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "Number of APIC MMIO reads in R3.", "/Devices/APIC/%u/R3/MmioReadR3");
	1632	APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "Number of APIC MMIO writes in R3.", "/Devices/APIC/%u/R3/MmioWriteR3");
	1633	APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "Number of APIC MSR reads in R3.", "/Devices/APIC/%u/R3/MsrReadR3");
	1634	APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "Number of APIC MSR writes in R3.", "/Devices/APIC/%u/R3/MsrWriteR3");
	1635
[60516]	1636	APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
	1637	"/PROF/CPU%d/APIC/UpdatePendingInterrupts");
[60593]	1638	APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
	1639
	1640	APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending, "Number of times an interrupt is already pending.",
	1641	"/Devices/APIC/%u/PostInterruptAlreadyPending");
[60632]	1642	APIC_REG_COUNTER(&pApicCpu->StatTimerCallback, "Number of times the timer callback is invoked.",
	1643	"/Devices/APIC/%u/TimerCallback");
[60752]	1644
[60804]	1645	APIC_REG_COUNTER(&pApicCpu->StatTprWrite, "Number of TPR writes.", "/Devices/APIC/%u/TprWrite");
	1646	APIC_REG_COUNTER(&pApicCpu->StatTprRead, "Number of TPR reads.", "/Devices/APIC/%u/TprRead");
	1647	APIC_REG_COUNTER(&pApicCpu->StatEoiWrite, "Number of EOI writes.", "/Devices/APIC/%u/EoiWrite");
[61795]	1648	APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr, "Number of times TPR masks an interrupt in apicGetInterrupt.",
[60804]	1649	"/Devices/APIC/%u/MaskedByTpr");
[61795]	1650	APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr, "Number of times PPR masks an interrupt in apicGetInterrupt.",
[60804]	1651	"/Devices/APIC/%u/MaskedByPpr");
[61150]	1652	APIC_REG_COUNTER(&pApicCpu->StatTimerIcrWrite, "Number of times the timer ICR is written.",
	1653	"/Devices/APIC/%u/TimerIcrWrite");
	1654	APIC_REG_COUNTER(&pApicCpu->StatIcrLoWrite, "Number of times the ICR Lo (send IPI) is written.",
	1655	"/Devices/APIC/%u/IcrLoWrite");
[63632]	1656	APIC_REG_COUNTER(&pApicCpu->StatIcrHiWrite, "Number of times the ICR Hi is written.",
	1657	"/Devices/APIC/%u/IcrHiWrite");
	1658	APIC_REG_COUNTER(&pApicCpu->StatIcrFullWrite, "Number of times the ICR full (send IPI, x2APIC) is written.",
	1659	"/Devices/APIC/%u/IcrFullWrite");
[60469]	1660	}
[60593]	1661	# undef APIC_PROF_COUNTER
[60469]	1662	# undef APIC_REG_ACCESS_COUNTER
	1663	#endif
	1664
[60307]	1665	return VINF_SUCCESS;
	1666	}
	1667
	1668
	1669	/**
	1670	* APIC device registration structure.
	1671	*/
[76402]	1672	static const PDMDEVREG g_DeviceAPIC =
[60307]	1673	{
	1674	/* u32Version */
	1675	PDM_DEVREG_VERSION,
	1676	/* szName */
	1677	"apic",
	1678	/* szRCMod */
	1679	"VMMRC.rc",
	1680	/* szR0Mod */
	1681	"VMMR0.r0",
	1682	/* pszDescription */
	1683	"Advanced Programmable Interrupt Controller",
	1684	/* fFlags */
	1685	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36
	1686	\| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
	1687	/* fClass */
	1688	PDM_DEVREG_CLASS_PIC,
	1689	/* cMaxInstances */
	1690	1,
	1691	/* cbInstance */
	1692	sizeof(APICDEV),
	1693	/* pfnConstruct */
	1694	apicR3Construct,
	1695	/* pfnDestruct */
[60398]	1696	apicR3Destruct,
[60307]	1697	/* pfnRelocate */
	1698	apicR3Relocate,
	1699	/* pfnMemSetup */
	1700	NULL,
	1701	/* pfnPowerOn */
	1702	NULL,
	1703	/* pfnReset */
	1704	apicR3Reset,
	1705	/* pfnSuspend */
	1706	NULL,
	1707	/* pfnResume */
	1708	NULL,
	1709	/* pfnAttach */
	1710	NULL,
	1711	/* pfnDetach */
	1712	NULL,
	1713	/* pfnQueryInterface. */
	1714	NULL,
	1715	/* pfnInitComplete */
[60398]	1716	apicR3InitComplete,
[60307]	1717	/* pfnPowerOff */
	1718	NULL,
	1719	/* pfnSoftReset */
	1720	NULL,
	1721	/* u32VersionEnd */
	1722	PDM_DEVREG_VERSION
	1723	};
	1724
[76402]	1725
	1726	/**
	1727	* Called by PDM to register the APIC device.
	1728	*/
	1729	VMMR3_INT_DECL(int) APICR3RegisterDevice(PPDMDEVREGCB pCallbacks)
	1730	{
	1731	return pCallbacks->pfnRegister(pCallbacks, &g_DeviceAPIC);
	1732	}
	1733
[60307]	1734	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
	1735

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