VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 26066

Last change on this file since 26066 was 26066, checked in by vboxsync, 15 years ago

Guest SMP: force all VCPUs to go back to ring 3 when a pgm pool flush is pending. Not doing so might cause trouble on a loaded host.
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1/* $Id: HWSVMR0.cpp 26066 2010-01-27 12:59:32Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/cpuset.h>
45#include <iprt/mp.h>
46#include <iprt/time.h>
47#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
48# include <iprt/thread.h>
49#endif
50#include "HWSVMR0.h"
51
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
56static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
57static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62
63/**
64 * Sets up and activates AMD-V on the current CPU
65 *
66 * @returns VBox status code.
67 * @param pCpu CPU info struct
68 * @param pVM The VM to operate on. (can be NULL after a resume!!)
69 * @param pvPageCpu Pointer to the global cpu page
70 * @param pPageCpuPhys Physical address of the global cpu page
71 */
72VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
73{
74 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
75 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
76
77 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
78 uint64_t val = ASMRdMsr(MSR_K6_EFER);
79 if (val & MSR_K6_EFER_SVME)
80 {
81 /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we blindly use AMD-V. */
82 if ( pVM
83 && pVM->hwaccm.s.svm.fIgnoreInUseError)
84 {
85 pCpu->fIgnoreAMDVInUseError = true;
86 }
87
88 if (!pCpu->fIgnoreAMDVInUseError)
89 return VERR_SVM_IN_USE;
90 }
91
92 /* Turn on AMD-V in the EFER MSR. */
93 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
94
95 /* Write the physical page address where the CPU will store the host state while executing the VM. */
96 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
97
98 return VINF_SUCCESS;
99}
100
101/**
102 * Deactivates AMD-V on the current CPU
103 *
104 * @returns VBox status code.
105 * @param pCpu CPU info struct
106 * @param pvPageCpu Pointer to the global cpu page
107 * @param pPageCpuPhys Physical address of the global cpu page
108 */
109VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
110{
111 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
112 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
113
114 /* Turn off AMD-V in the EFER MSR. */
115 uint64_t val = ASMRdMsr(MSR_K6_EFER);
116 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
117
118 /* Invalidate host state physical address. */
119 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
120
121 return VINF_SUCCESS;
122}
123
124/**
125 * Does Ring-0 per VM AMD-V init.
126 *
127 * @returns VBox status code.
128 * @param pVM The VM to operate on.
129 */
130VMMR0DECL(int) SVMR0InitVM(PVM pVM)
131{
132 int rc;
133
134 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
135
136 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
137 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
138 if (RT_FAILURE(rc))
139 return rc;
140
141 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
142 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
143 /* Set all bits to intercept all IO accesses. */
144 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
145
146 /* Erratum 170 which requires a forced TLB flush for each world switch:
147 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
148 *
149 * All BH-G1/2 and DH-G1/2 models include a fix:
150 * Athlon X2: 0x6b 1/2
151 * 0x68 1/2
152 * Athlon 64: 0x7f 1
153 * 0x6f 2
154 * Sempron: 0x7f 1/2
155 * 0x6f 2
156 * 0x6c 2
157 * 0x7c 2
158 * Turion 64: 0x68 2
159 *
160 */
161 uint32_t u32Dummy;
162 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
163 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
164 u32BaseFamily= (u32Version >> 8) & 0xf;
165 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
166 u32Model = ((u32Version >> 4) & 0xf);
167 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
168 u32Stepping = u32Version & 0xf;
169 if ( u32Family == 0xf
170 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
171 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
172 {
173 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
174 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
175 }
176
177 /* Allocate VMCBs for all guest CPUs. */
178 for (VMCPUID i = 0; i < pVM->cCpus; i++)
179 {
180 PVMCPU pVCpu = &pVM->aCpus[i];
181
182 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
183 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
184 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
185
186 /* Allocate one page for the host context */
187 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
188 if (RT_FAILURE(rc))
189 return rc;
190
191 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
192 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
193 Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);
194 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
195
196 /* Allocate one page for the VM control block (VMCB). */
197 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
198 if (RT_FAILURE(rc))
199 return rc;
200
201 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
202 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
203 Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);
204 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
205
206 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
207 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
208 if (RT_FAILURE(rc))
209 return rc;
210
211 pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
212 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
213 /* Set all bits to intercept all MSR accesses. */
214 ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
215 }
216
217 return VINF_SUCCESS;
218}
219
220/**
221 * Does Ring-0 per VM AMD-V termination.
222 *
223 * @returns VBox status code.
224 * @param pVM The VM to operate on.
225 */
226VMMR0DECL(int) SVMR0TermVM(PVM pVM)
227{
228 for (VMCPUID i = 0; i < pVM->cCpus; i++)
229 {
230 PVMCPU pVCpu = &pVM->aCpus[i];
231
232 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
233 {
234 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
235 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
236 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
237 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
238 }
239
240 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
241 {
242 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
243 pVCpu->hwaccm.s.svm.pVMCB = 0;
244 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
245 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
246 }
247 if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
248 {
249 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
250 pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
251 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
252 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
253 }
254 }
255 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
256 {
257 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
258 pVM->hwaccm.s.svm.pIOBitmap = 0;
259 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
260 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
261 }
262 return VINF_SUCCESS;
263}
264
265/**
266 * Sets up AMD-V for the specified VM
267 *
268 * @returns VBox status code.
269 * @param pVM The VM to operate on.
270 */
271VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
272{
273 int rc = VINF_SUCCESS;
274
275 AssertReturn(pVM, VERR_INVALID_PARAMETER);
276
277 Assert(pVM->hwaccm.s.svm.fSupported);
278
279 for (VMCPUID i = 0; i < pVM->cCpus; i++)
280 {
281 PVMCPU pVCpu = &pVM->aCpus[i];
282 SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
283
284 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
285
286 /* Program the control fields. Most of them never have to be changed again. */
287 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
288 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
289 if (!pVM->hwaccm.s.fNestedPaging)
290 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
291 else
292 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
293
294 /*
295 * CR0/3/4 writes must be intercepted for obvious reasons.
296 */
297 if (!pVM->hwaccm.s.fNestedPaging)
298 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
299 else
300 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
301
302 /* Intercept all DRx reads and writes by default. Changed later on. */
303 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
304 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
305
306 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
307 * All breakpoints are automatically cleared when the VM exits.
308 */
309
310 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
311#ifndef DEBUG
312 if (pVM->hwaccm.s.fNestedPaging)
313 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
314#endif
315
316 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
317 | SVM_CTRL1_INTERCEPT_VINTR
318 | SVM_CTRL1_INTERCEPT_NMI
319 | SVM_CTRL1_INTERCEPT_SMI
320 | SVM_CTRL1_INTERCEPT_INIT
321 | SVM_CTRL1_INTERCEPT_RDPMC
322 | SVM_CTRL1_INTERCEPT_CPUID
323 | SVM_CTRL1_INTERCEPT_RSM
324 | SVM_CTRL1_INTERCEPT_HLT
325 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
326 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
327 | SVM_CTRL1_INTERCEPT_INVLPG
328 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
329 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
330 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
331 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
332 ;
333 /* With nested paging we don't care about invlpg anymore. */
334 if (pVM->hwaccm.s.fNestedPaging)
335 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
336
337 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
338 | SVM_CTRL2_INTERCEPT_VMMCALL
339 | SVM_CTRL2_INTERCEPT_VMLOAD
340 | SVM_CTRL2_INTERCEPT_VMSAVE
341 | SVM_CTRL2_INTERCEPT_STGI
342 | SVM_CTRL2_INTERCEPT_CLGI
343 | SVM_CTRL2_INTERCEPT_SKINIT
344 | SVM_CTRL2_INTERCEPT_WBINVD
345 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
346 ;
347 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
348 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
349 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
350
351 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
352 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
353 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
354 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
355
356 /* Set IO and MSR bitmap addresses. */
357 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
358 pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
359
360 /* No LBR virtualization. */
361 pVMCB->ctrl.u64LBRVirt = 0;
362
363 /** The ASID must start at 1; the host uses 0. */
364 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
365
366 /** Setup the PAT msr (nested paging only) */
367 pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
368
369 /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
370 * to modify them directly.
371 */
372 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
373 svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
374 svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
375 svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
376 svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
377 svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
378 svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
379 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
380 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
381 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
382 }
383
384 return rc;
385}
386
387
388/**
389 * Sets the permission bits for the specified MSR
390 *
391 * @param pVCpu The VMCPU to operate on.
392 * @param ulMSR MSR value
393 * @param fRead Reading allowed/disallowed
394 * @param fWrite Writing allowed/disallowed
395 */
396static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
397{
398 unsigned ulBit;
399 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
400
401 if (ulMSR <= 0x00001FFF)
402 {
403 /* Pentium-compatible MSRs */
404 ulBit = ulMSR * 2;
405 }
406 else
407 if ( ulMSR >= 0xC0000000
408 && ulMSR <= 0xC0001FFF)
409 {
410 /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
411 ulBit = (ulMSR - 0xC0000000) * 2;
412 pMSRBitmap += 0x800;
413 }
414 else
415 if ( ulMSR >= 0xC0010000
416 && ulMSR <= 0xC0011FFF)
417 {
418 /* AMD Seventh and Eighth Generation Processor MSRs */
419 ulBit = (ulMSR - 0xC0001000) * 2;
420 pMSRBitmap += 0x1000;
421 }
422 else
423 {
424 AssertFailed();
425 return;
426 }
427 Assert(ulBit < 16 * 1024 - 1);
428 if (fRead)
429 ASMBitClear(pMSRBitmap, ulBit);
430 else
431 ASMBitSet(pMSRBitmap, ulBit);
432
433 if (fWrite)
434 ASMBitClear(pMSRBitmap, ulBit + 1);
435 else
436 ASMBitSet(pMSRBitmap, ulBit + 1);
437}
438
439/**
440 * Injects an event (trap or external interrupt)
441 *
442 * @param pVCpu The VMCPU to operate on.
443 * @param pVMCB SVM control block
444 * @param pCtx CPU Context
445 * @param pIntInfo SVM interrupt info
446 */
447inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
448{
449#ifdef VBOX_WITH_STATISTICS
450 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
451#endif
452
453#ifdef VBOX_STRICT
454 if (pEvent->n.u8Vector == 0xE)
455 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
456 else
457 if (pEvent->n.u8Vector < 0x20)
458 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
459 else
460 {
461 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
462 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
463 Assert(pCtx->eflags.u32 & X86_EFL_IF);
464 }
465#endif
466
467 /* Set event injection state. */
468 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
469}
470
471
472/**
473 * Checks for pending guest interrupts and injects them
474 *
475 * @returns VBox status code.
476 * @param pVM The VM to operate on.
477 * @param pVCpu The VM CPU to operate on.
478 * @param pVMCB SVM control block
479 * @param pCtx CPU Context
480 */
481static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
482{
483 int rc;
484
485 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
486 if (pVCpu->hwaccm.s.Event.fPending)
487 {
488 SVM_EVENT Event;
489
490 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
491 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
492 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
493 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
494
495 pVCpu->hwaccm.s.Event.fPending = false;
496 return VINF_SUCCESS;
497 }
498
499 /* If an active trap is already pending, then we must forward it first! */
500 if (!TRPMHasTrap(pVCpu))
501 {
502 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
503 {
504 SVM_EVENT Event;
505
506 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
507 Event.n.u8Vector = X86_XCPT_NMI;
508 Event.n.u1Valid = 1;
509 Event.n.u32ErrorCode = 0;
510 Event.n.u3Type = SVM_EVENT_NMI;
511
512 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
513 return VINF_SUCCESS;
514 }
515
516 /* @todo SMI interrupts. */
517
518 /* When external interrupts are pending, we should exit the VM when IF is set. */
519 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
520 {
521 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
522 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
523 {
524 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
525 {
526 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
527 LogFlow(("Enable irq window exit!\n"));
528 else
529 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
530
531 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
532 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
533 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
534 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
535 }
536 }
537 else
538 {
539 uint8_t u8Interrupt;
540
541 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
542 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
543 if (RT_SUCCESS(rc))
544 {
545 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
546 AssertRC(rc);
547 }
548 else
549 {
550 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
551 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
552 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
553 /* Just continue */
554 }
555 }
556 }
557 }
558
559#ifdef VBOX_STRICT
560 if (TRPMHasTrap(pVCpu))
561 {
562 uint8_t u8Vector;
563 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
564 AssertRC(rc);
565 }
566#endif
567
568 if ( (pCtx->eflags.u32 & X86_EFL_IF)
569 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
570 && TRPMHasTrap(pVCpu)
571 )
572 {
573 uint8_t u8Vector;
574 TRPMEVENT enmType;
575 SVM_EVENT Event;
576 RTGCUINT u32ErrorCode;
577
578 Event.au64[0] = 0;
579
580 /* If a new event is pending, then dispatch it now. */
581 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
582 AssertRC(rc);
583 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
584 Assert(enmType != TRPM_SOFTWARE_INT);
585
586 /* Clear the pending trap. */
587 rc = TRPMResetTrap(pVCpu);
588 AssertRC(rc);
589
590 Event.n.u8Vector = u8Vector;
591 Event.n.u1Valid = 1;
592 Event.n.u32ErrorCode = u32ErrorCode;
593
594 if (enmType == TRPM_TRAP)
595 {
596 switch (u8Vector) {
597 case 8:
598 case 10:
599 case 11:
600 case 12:
601 case 13:
602 case 14:
603 case 17:
604 /* Valid error codes. */
605 Event.n.u1ErrorCodeValid = 1;
606 break;
607 default:
608 break;
609 }
610 if (u8Vector == X86_XCPT_NMI)
611 Event.n.u3Type = SVM_EVENT_NMI;
612 else
613 Event.n.u3Type = SVM_EVENT_EXCEPTION;
614 }
615 else
616 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
617
618 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
619 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
620 } /* if (interrupts can be dispatched) */
621
622 return VINF_SUCCESS;
623}
624
625/**
626 * Save the host state
627 *
628 * @returns VBox status code.
629 * @param pVM The VM to operate on.
630 * @param pVCpu The VM CPU to operate on.
631 */
632VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
633{
634 NOREF(pVM);
635 NOREF(pVCpu);
636 /* Nothing to do here. */
637 return VINF_SUCCESS;
638}
639
640/**
641 * Loads the guest state
642 *
643 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
644 *
645 * @returns VBox status code.
646 * @param pVM The VM to operate on.
647 * @param pVCpu The VM CPU to operate on.
648 * @param pCtx Guest context
649 */
650VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
651{
652 RTGCUINTPTR val;
653 SVM_VMCB *pVMCB;
654
655 if (pVM == NULL)
656 return VERR_INVALID_PARAMETER;
657
658 /* Setup AMD SVM. */
659 Assert(pVM->hwaccm.s.svm.fSupported);
660
661 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
662 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
663
664 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
665 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
666 {
667 SVM_WRITE_SELREG(CS, cs);
668 SVM_WRITE_SELREG(SS, ss);
669 SVM_WRITE_SELREG(DS, ds);
670 SVM_WRITE_SELREG(ES, es);
671 SVM_WRITE_SELREG(FS, fs);
672 SVM_WRITE_SELREG(GS, gs);
673 }
674
675 /* Guest CPU context: LDTR. */
676 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
677 {
678 SVM_WRITE_SELREG(LDTR, ldtr);
679 }
680
681 /* Guest CPU context: TR. */
682 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
683 {
684 SVM_WRITE_SELREG(TR, tr);
685 }
686
687 /* Guest CPU context: GDTR. */
688 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
689 {
690 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
691 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
692 }
693
694 /* Guest CPU context: IDTR. */
695 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
696 {
697 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
698 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
699 }
700
701 /*
702 * Sysenter MSRs (unconditional)
703 */
704 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
705 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
706 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
707
708 /* Control registers */
709 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
710 {
711 val = pCtx->cr0;
712 if (!CPUMIsGuestFPUStateActive(pVCpu))
713 {
714 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
715 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
716 }
717 else
718 {
719 /** @todo check if we support the old style mess correctly. */
720 if (!(val & X86_CR0_NE))
721 {
722 Log(("Forcing X86_CR0_NE!!!\n"));
723
724 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
725 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
726 {
727 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
728 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
729 }
730 }
731 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
732 }
733 /* Always enable caching. */
734 val &= ~(X86_CR0_CD|X86_CR0_NW);
735
736 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
737 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
738 if (!pVM->hwaccm.s.fNestedPaging)
739 {
740 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
741 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
742 }
743 pVMCB->guest.u64CR0 = val;
744 }
745 /* CR2 as well */
746 pVMCB->guest.u64CR2 = pCtx->cr2;
747
748 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
749 {
750 /* Save our shadow CR3 register. */
751 if (pVM->hwaccm.s.fNestedPaging)
752 {
753 PGMMODE enmShwPagingMode;
754
755#if HC_ARCH_BITS == 32
756 if (CPUMIsGuestInLongModeEx(pCtx))
757 enmShwPagingMode = PGMMODE_AMD64_NX;
758 else
759#endif
760 enmShwPagingMode = PGMGetHostMode(pVM);
761
762 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
763 Assert(pVMCB->ctrl.u64NestedPagingCR3);
764 pVMCB->guest.u64CR3 = pCtx->cr3;
765 }
766 else
767 {
768 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
769 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
770 }
771 }
772
773 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
774 {
775 val = pCtx->cr4;
776 if (!pVM->hwaccm.s.fNestedPaging)
777 {
778 switch(pVCpu->hwaccm.s.enmShadowMode)
779 {
780 case PGMMODE_REAL:
781 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
782 AssertFailed();
783 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
784
785 case PGMMODE_32_BIT: /* 32-bit paging. */
786 val &= ~X86_CR4_PAE;
787 break;
788
789 case PGMMODE_PAE: /* PAE paging. */
790 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
791 /** @todo use normal 32 bits paging */
792 val |= X86_CR4_PAE;
793 break;
794
795 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
796 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
797#ifdef VBOX_ENABLE_64_BITS_GUESTS
798 break;
799#else
800 AssertFailed();
801 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
802#endif
803
804 default: /* shut up gcc */
805 AssertFailed();
806 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
807 }
808 }
809 pVMCB->guest.u64CR4 = val;
810 }
811
812 /* Debug registers. */
813 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
814 {
815 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
816 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
817
818 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
819 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
820 pCtx->dr[7] |= 0x400; /* must be one */
821
822 pVMCB->guest.u64DR7 = pCtx->dr[7];
823 pVMCB->guest.u64DR6 = pCtx->dr[6];
824
825#ifdef DEBUG
826 /* Sync the hypervisor debug state now if any breakpoint is armed. */
827 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
828 && !CPUMIsHyperDebugStateActive(pVCpu)
829 && !DBGFIsStepping(pVCpu))
830 {
831 /* Save the host and load the hypervisor debug state. */
832 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
833 AssertRC(rc);
834
835 /* DRx intercepts remain enabled. */
836
837 /* Override dr6 & dr7 with the hypervisor values. */
838 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
839 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
840 }
841 else
842#endif
843 /* Sync the debug state now if any breakpoint is armed. */
844 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
845 && !CPUMIsGuestDebugStateActive(pVCpu)
846 && !DBGFIsStepping(pVCpu))
847 {
848 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
849
850 /* Disable drx move intercepts. */
851 pVMCB->ctrl.u16InterceptRdDRx = 0;
852 pVMCB->ctrl.u16InterceptWrDRx = 0;
853
854 /* Save the host and load the guest debug state. */
855 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
856 AssertRC(rc);
857 }
858 }
859
860 /* EIP, ESP and EFLAGS */
861 pVMCB->guest.u64RIP = pCtx->rip;
862 pVMCB->guest.u64RSP = pCtx->rsp;
863 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
864
865 /* Set CPL */
866 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
867
868 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
869 pVMCB->guest.u64RAX = pCtx->rax;
870
871 /* vmrun will fail without MSR_K6_EFER_SVME. */
872 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
873
874 /* 64 bits guest mode? */
875 if (CPUMIsGuestInLongModeEx(pCtx))
876 {
877#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
878 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
879#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
880 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
881#else
882# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
883 if (!pVM->hwaccm.s.fAllow64BitGuests)
884 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
885# endif
886 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
887#endif
888 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
889 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
890 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
891 }
892 else
893 {
894 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
895 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
896
897 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
898 }
899
900 /* TSC offset. */
901 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
902 {
903 uint64_t u64CurTSC = ASMReadTSC();
904 if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
905 {
906 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
907 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
908 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
909 }
910 else
911 {
912 /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
913 LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
914 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
915 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
916 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
917 }
918 }
919 else
920 {
921 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
922 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
923 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
924 }
925
926 /* Sync the various msrs for 64 bits mode. */
927 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
928 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
929 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
930 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
931 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
932
933#ifdef DEBUG
934 /* Intercept X86_XCPT_DB if stepping is enabled */
935 if ( DBGFIsStepping(pVCpu)
936 || CPUMIsHyperDebugStateActive(pVCpu))
937 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
938 else
939 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
940#endif
941
942 /* Done. */
943 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
944
945 return VINF_SUCCESS;
946}
947
948
949/**
950 * Runs guest code in an AMD-V VM.
951 *
952 * @returns VBox status code.
953 * @param pVM The VM to operate on.
954 * @param pVCpu The VM CPU to operate on.
955 * @param pCtx Guest context
956 */
957VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
958{
959 int rc = VINF_SUCCESS;
960 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
961 SVM_VMCB *pVMCB;
962 bool fSyncTPR = false;
963 unsigned cResume = 0;
964 uint8_t u8LastTPR;
965 PHWACCM_CPUINFO pCpu = 0;
966 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
967#ifdef VBOX_STRICT
968 RTCPUID idCpuCheck;
969#endif
970#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
971 uint64_t u64LastTime = RTTimeMilliTS();
972#endif
973
974 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
975
976 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
977 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
978
979 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
980 */
981ResumeExecution:
982 Assert(!HWACCMR0SuspendPending());
983
984 /* Safety precaution; looping for too long here can have a very bad effect on the host */
985 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
986 {
987 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
988 rc = VINF_EM_RAW_INTERRUPT;
989 goto end;
990 }
991
992 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
993 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
994 {
995 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
996 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
997 {
998 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
999 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1000 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1001 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1002 */
1003 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1004 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1005 pVMCB->ctrl.u64IntShadow = 0;
1006 }
1007 }
1008 else
1009 {
1010 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1011 pVMCB->ctrl.u64IntShadow = 0;
1012 }
1013
1014#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1015 if (RT_UNLIKELY(cResume & 0xf) == 0)
1016 {
1017 uint64_t u64CurTime = RTTimeMilliTS();
1018
1019 if (RT_UNLIKELY(u64CurTime > u64LastTime))
1020 {
1021 u64LastTime = u64CurTime;
1022 TMTimerPollVoid(pVM, pVCpu);
1023 }
1024 }
1025#endif
1026
1027 /* Check for pending actions that force us to go back to ring 3. */
1028 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING)
1029 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST))
1030 {
1031 /* Check if a sync operation is pending. */
1032 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1033 {
1034 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1035 AssertRC(rc);
1036 if (rc != VINF_SUCCESS)
1037 {
1038 Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", rc));
1039 goto end;
1040 }
1041 }
1042
1043#ifdef DEBUG
1044 /* Intercept X86_XCPT_DB if stepping is enabled */
1045 if (!DBGFIsStepping(pVCpu))
1046#endif
1047 {
1048 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1049 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1050 {
1051 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1052 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1053 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1054 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1055 goto end;
1056 }
1057 }
1058
1059 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1060 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1061 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1062 {
1063 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1064 rc = VINF_EM_PENDING_REQUEST;
1065 goto end;
1066 }
1067
1068 /* Check if a pgm pool flush is in progress. */
1069 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
1070 {
1071 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1072 rc = VINF_PGM_POOL_FLUSH_PENDING;
1073 goto end;
1074 }
1075 }
1076
1077#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1078 /*
1079 * Exit to ring-3 preemption/work is pending.
1080 *
1081 * Interrupts are disabled before the call to make sure we don't miss any interrupt
1082 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1083 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
1084 *
1085 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
1086 * shootdowns rely on this.
1087 */
1088 uOldEFlags = ASMIntDisableFlags();
1089 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1090 {
1091 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1092 rc = VINF_EM_RAW_INTERRUPT;
1093 goto end;
1094 }
1095 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1096#endif
1097
1098 /* When external interrupts are pending, we should exit the VM when IF is set. */
1099 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1100 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1101 if (RT_FAILURE(rc))
1102 {
1103 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1104 goto end;
1105 }
1106
1107 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1108 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1109 * @todo query and update the TPR only when it could have been changed (mmio access)
1110 */
1111 if (pVM->hwaccm.s.fHasIoApic)
1112 {
1113 bool fPending;
1114
1115 /* TPR caching in CR8 */
1116 int rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1117 AssertRC(rc2);
1118
1119 if (pVM->hwaccm.s.fTPRPatchingActive)
1120 {
1121 /* Our patch code uses LSTAR for TPR caching. */
1122 pCtx->msrLSTAR = u8LastTPR;
1123
1124 if (fPending)
1125 {
1126 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
1127 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1128 }
1129 else
1130 /* No interrupts are pending, so we don't need to be explicitely notified.
1131 * There are enough world switches for detecting pending interrupts.
1132 */
1133 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1134 }
1135 else
1136 {
1137 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1138
1139 if (fPending)
1140 {
1141 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1142 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1143 }
1144 else
1145 /* No interrupts are pending, so we don't need to be explicitely notified.
1146 * There are enough world switches for detecting pending interrupts.
1147 */
1148 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1149 }
1150 fSyncTPR = !fPending;
1151 }
1152
1153 /* All done! Let's start VM execution. */
1154 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1155
1156 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1157 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1158
1159#ifdef LOG_ENABLED
1160 pCpu = HWACCMR0GetCurrentCpu();
1161 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1162 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1163 {
1164 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1165 LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1166 else
1167 LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1168 }
1169 if (pCpu->fFlushTLB)
1170 LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1171#endif
1172
1173 /*
1174 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1175 * (until the actual world switch)
1176 */
1177#ifdef VBOX_STRICT
1178 idCpuCheck = RTMpCpuId();
1179#endif
1180 VMMR0LogFlushDisable(pVCpu);
1181
1182 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1183 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1184 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1185 {
1186 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1187 VMMR0LogFlushEnable(pVCpu);
1188 goto end;
1189 }
1190
1191#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1192 /* Disable interrupts to make sure a poke will interrupt execution.
1193 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1194 */
1195 uOldEFlags = ASMIntDisableFlags();
1196 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1197#endif
1198
1199 pCpu = HWACCMR0GetCurrentCpu();
1200 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1201 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1202 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1203 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1204 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1205 {
1206 /* Force a TLB flush on VM entry. */
1207 pVCpu->hwaccm.s.fForceTLBFlush = true;
1208 }
1209 else
1210 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1211
1212 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1213
1214 /** Set TLB flush state as checked until we return from the world switch. */
1215 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
1216
1217 /* Check for tlb shootdown flushes. */
1218 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1219 pVCpu->hwaccm.s.fForceTLBFlush = true;
1220
1221 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1222 if ( pVCpu->hwaccm.s.fForceTLBFlush
1223 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1224 {
1225 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1226 || pCpu->fFlushTLB)
1227 {
1228 pCpu->fFlushTLB = false;
1229 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1230 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1231 pCpu->cTLBFlushes++;
1232 }
1233 else
1234 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1235
1236 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1237 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1238 }
1239 else
1240 {
1241 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1242
1243 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1244 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1245 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1246
1247 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1248 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1249
1250 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1251 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1252 {
1253 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1254 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1255 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1256 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1257 }
1258 }
1259 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1260 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1261
1262 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1263 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1264 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1265 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1266
1267#ifdef VBOX_WITH_STATISTICS
1268 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1269 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1270 else
1271 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1272#endif
1273
1274 /* In case we execute a goto ResumeExecution later on. */
1275 pVCpu->hwaccm.s.fResumeVM = true;
1276 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1277
1278 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1279 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1280 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1281 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1282 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1283
1284#ifdef VBOX_STRICT
1285 Assert(idCpuCheck == RTMpCpuId());
1286#endif
1287 TMNotifyStartOfExecution(pVCpu);
1288#ifdef VBOX_WITH_KERNEL_USING_XMM
1289 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1290#else
1291 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1292#endif
1293 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
1294 ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExit);
1295 /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
1296 if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1297 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1298 TMNotifyEndOfExecution(pVCpu);
1299 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1300 ASMSetFlags(uOldEFlags);
1301#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1302 uOldEFlags = ~(RTCCUINTREG)0;
1303#endif
1304 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1305
1306 /*
1307 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1308 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1309 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1310 */
1311
1312 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1313
1314 /* Reason for the VM exit */
1315 exitCode = pVMCB->ctrl.u64ExitCode;
1316
1317 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1318 {
1319 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1320#ifdef DEBUG
1321 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1322 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1323 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1324 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1325 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1326 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1327 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1328 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1329 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1330 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1331
1332 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1333 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1334 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1335 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1336
1337 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1338 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1339 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1340 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1341 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1342 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1343 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1344 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1345 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1346 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1347
1348 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1349 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1350 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1351 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1352 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1353 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1354 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1355 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1356 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1357 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1358 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1359 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1360 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1361 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1362 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1363 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1364 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1365
1366 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1367 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1368
1369 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1370 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1371 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1372 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1373 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1374 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1375 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1376 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1377 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1378 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1379 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1380 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1381 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1382 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1383 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1384 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1385 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1386 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1387 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1388 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1389
1390 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1391 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1392
1393 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1394 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1395 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1396 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1397
1398 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1399 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1400
1401 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1402 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1403 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1404 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1405
1406 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1407 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1408 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1409 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1410 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1411 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1412 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1413
1414 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1415 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1416 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1417 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1418
1419 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1420 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1421 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1422
1423 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1424 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1425 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1426 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1427 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1428 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1429 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1430 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1431 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1432 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1433 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1434 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1435
1436#endif
1437 rc = VERR_SVM_UNABLE_TO_START_VM;
1438 VMMR0LogFlushEnable(pVCpu);
1439 goto end;
1440 }
1441
1442 /* Let's first sync back eip, esp, and eflags. */
1443 pCtx->rip = pVMCB->guest.u64RIP;
1444 pCtx->rsp = pVMCB->guest.u64RSP;
1445 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1446 /* eax is saved/restore across the vmrun instruction */
1447 pCtx->rax = pVMCB->guest.u64RAX;
1448
1449 /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1450 pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1451 pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1452 pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1453 pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1454 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1455 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1456 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1457 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1458
1459 /* Can be updated behind our back in the nested paging case. */
1460 pCtx->cr2 = pVMCB->guest.u64CR2;
1461
1462 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1463 SVM_READ_SELREG(SS, ss);
1464 SVM_READ_SELREG(CS, cs);
1465 SVM_READ_SELREG(DS, ds);
1466 SVM_READ_SELREG(ES, es);
1467 SVM_READ_SELREG(FS, fs);
1468 SVM_READ_SELREG(GS, gs);
1469
1470 /* Correct the hidden CS granularity flag. Haven't seen it being wrong in
1471 any other register (yet). */
1472 if ( !pCtx->csHid.Attr.n.u1Granularity
1473 && pCtx->csHid.Attr.n.u1Present
1474 && pCtx->csHid.u32Limit > UINT32_C(0xfffff))
1475 {
1476 Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
1477 pCtx->csHid.Attr.n.u1Granularity = 1;
1478 }
1479#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1480 AssertMsg( !pCtx->reg##Hid.Attr.n.u1Present \
1481 || ( pCtx->reg##Hid.Attr.n.u1Granularity \
1482 ? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
1483 : pCtx->reg##Hid.u32Limit <= 0xfffff), \
1484 ("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
1485 SVM_ASSERT_SEL_GRANULARITY(ss);
1486 SVM_ASSERT_SEL_GRANULARITY(cs);
1487 SVM_ASSERT_SEL_GRANULARITY(ds);
1488 SVM_ASSERT_SEL_GRANULARITY(es);
1489 SVM_ASSERT_SEL_GRANULARITY(fs);
1490 SVM_ASSERT_SEL_GRANULARITY(gs);
1491#undef SVM_ASSERT_SEL_GRANULARITY
1492
1493 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1494 SVM_READ_SELREG(LDTR, ldtr);
1495 SVM_READ_SELREG(TR, tr);
1496
1497 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1498 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1499
1500 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1501 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1502
1503 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1504 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1505 if ( pVM->hwaccm.s.fNestedPaging
1506 && pCtx->cr3 != pVMCB->guest.u64CR3)
1507 {
1508 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1509 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1510 }
1511
1512 /* Note! NOW IT'S SAFE FOR LOGGING! */
1513 VMMR0LogFlushEnable(pVCpu);
1514
1515 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1516 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1517 {
1518 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1519 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1520 }
1521 else
1522 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1523
1524 Log2(("exitCode = %x\n", exitCode));
1525
1526 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1527 pCtx->dr[6] = pVMCB->guest.u64DR6;
1528 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1529 pCtx->dr[7] = pVMCB->guest.u64DR7;
1530
1531 /* Check if an injected event was interrupted prematurely. */
1532 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1533 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1534 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1535 {
1536 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1537
1538#ifdef LOG_ENABLED
1539 SVM_EVENT Event;
1540 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1541
1542 if ( exitCode == SVM_EXIT_EXCEPTION_E
1543 && Event.n.u8Vector == 0xE)
1544 {
1545 Log(("Double fault!\n"));
1546 }
1547#endif
1548
1549 pVCpu->hwaccm.s.Event.fPending = true;
1550 /* Error code present? (redundant) */
1551 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1552 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1553 else
1554 pVCpu->hwaccm.s.Event.errCode = 0;
1555 }
1556#ifdef VBOX_WITH_STATISTICS
1557 if (exitCode == SVM_EXIT_NPF)
1558 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1559 else
1560 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1561#endif
1562
1563 /* Sync back the TPR if it was changed. */
1564 if (fSyncTPR)
1565 {
1566 if (pVM->hwaccm.s.fTPRPatchingActive)
1567 {
1568 if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1569 {
1570 /* Our patch code uses LSTAR for TPR caching. */
1571 rc = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1572 AssertRC(rc);
1573 }
1574 }
1575 else
1576 {
1577 if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1578 {
1579 rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1580 AssertRC(rc);
1581 }
1582 }
1583 }
1584
1585 /* Deal with the reason of the VM-exit. */
1586 switch (exitCode)
1587 {
1588 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1589 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1590 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1591 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1592 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1593 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1594 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1595 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1596 {
1597 /* Pending trap. */
1598 SVM_EVENT Event;
1599 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1600
1601 Log2(("Hardware/software interrupt %d\n", vector));
1602 switch (vector)
1603 {
1604 case X86_XCPT_DB:
1605 {
1606 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1607
1608 /* Note that we don't support guest and host-initiated debugging at the same time. */
1609 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1610
1611 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1612 if (rc == VINF_EM_RAW_GUEST_TRAP)
1613 {
1614 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1615
1616 /* Reinject the exception. */
1617 Event.au64[0] = 0;
1618 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1619 Event.n.u1Valid = 1;
1620 Event.n.u8Vector = X86_XCPT_DB;
1621
1622 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1623
1624 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1625 goto ResumeExecution;
1626 }
1627 /* Return to ring 3 to deal with the debug exit code. */
1628 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
1629 break;
1630 }
1631
1632 case X86_XCPT_NM:
1633 {
1634 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1635
1636 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1637 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1638 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1639 if (rc == VINF_SUCCESS)
1640 {
1641 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1642 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1643
1644 /* Continue execution. */
1645 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1646 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1647
1648 goto ResumeExecution;
1649 }
1650
1651 Log(("Forward #NM fault to the guest\n"));
1652 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1653
1654 Event.au64[0] = 0;
1655 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1656 Event.n.u1Valid = 1;
1657 Event.n.u8Vector = X86_XCPT_NM;
1658
1659 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1660 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1661 goto ResumeExecution;
1662 }
1663
1664 case X86_XCPT_PF: /* Page fault */
1665 {
1666 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1667 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1668
1669#ifdef DEBUG
1670 if (pVM->hwaccm.s.fNestedPaging)
1671 { /* A genuine pagefault.
1672 * Forward the trap to the guest by injecting the exception and resuming execution.
1673 */
1674 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1675 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1676
1677 /* Now we must update CR2. */
1678 pCtx->cr2 = uFaultAddress;
1679
1680 Event.au64[0] = 0;
1681 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1682 Event.n.u1Valid = 1;
1683 Event.n.u8Vector = X86_XCPT_PF;
1684 Event.n.u1ErrorCodeValid = 1;
1685 Event.n.u32ErrorCode = errCode;
1686
1687 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1688
1689 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1690 goto ResumeExecution;
1691 }
1692#endif
1693 Assert(!pVM->hwaccm.s.fNestedPaging);
1694
1695#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1696 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1697 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1698 && (uFaultAddress & 0xfff) == 0x080
1699 && !(errCode & X86_TRAP_PF_P) /* not present */
1700 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1701 && !CPUMIsGuestInLongModeEx(pCtx)
1702 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1703 {
1704 RTGCPHYS GCPhysApicBase, GCPhys;
1705 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1706 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1707
1708 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1709 if ( rc == VINF_SUCCESS
1710 && GCPhys == GCPhysApicBase)
1711 {
1712 /* Only attempt to patch the instruction once. */
1713 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1714 if (!pPatch)
1715 {
1716 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1717 break;
1718 }
1719 }
1720 }
1721#endif
1722
1723 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1724 /* Exit qualification contains the linear address of the page fault. */
1725 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1726 TRPMSetErrorCode(pVCpu, errCode);
1727 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1728
1729 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1730 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1731 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1732 if (rc == VINF_SUCCESS)
1733 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1734 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1735 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1736
1737 TRPMResetTrap(pVCpu);
1738 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1739 goto ResumeExecution;
1740 }
1741 else
1742 if (rc == VINF_EM_RAW_GUEST_TRAP)
1743 { /* A genuine pagefault.
1744 * Forward the trap to the guest by injecting the exception and resuming execution.
1745 */
1746 Log2(("Forward page fault to the guest\n"));
1747 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1748 /* The error code might have been changed. */
1749 errCode = TRPMGetErrorCode(pVCpu);
1750
1751 TRPMResetTrap(pVCpu);
1752
1753 /* Now we must update CR2. */
1754 pCtx->cr2 = uFaultAddress;
1755
1756 Event.au64[0] = 0;
1757 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1758 Event.n.u1Valid = 1;
1759 Event.n.u8Vector = X86_XCPT_PF;
1760 Event.n.u1ErrorCodeValid = 1;
1761 Event.n.u32ErrorCode = errCode;
1762
1763 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1764
1765 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1766 goto ResumeExecution;
1767 }
1768#ifdef VBOX_STRICT
1769 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1770 LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1771#endif
1772 /* Need to go back to the recompiler to emulate the instruction. */
1773 TRPMResetTrap(pVCpu);
1774 break;
1775 }
1776
1777 case X86_XCPT_MF: /* Floating point exception. */
1778 {
1779 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1780 if (!(pCtx->cr0 & X86_CR0_NE))
1781 {
1782 /* old style FPU error reporting needs some extra work. */
1783 /** @todo don't fall back to the recompiler, but do it manually. */
1784 rc = VINF_EM_RAW_EMULATE_INSTR;
1785 break;
1786 }
1787 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1788
1789 Event.au64[0] = 0;
1790 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1791 Event.n.u1Valid = 1;
1792 Event.n.u8Vector = X86_XCPT_MF;
1793
1794 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1795
1796 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1797 goto ResumeExecution;
1798 }
1799
1800#ifdef VBOX_STRICT
1801 case X86_XCPT_GP: /* General protection failure exception.*/
1802 case X86_XCPT_UD: /* Unknown opcode exception. */
1803 case X86_XCPT_DE: /* Divide error. */
1804 case X86_XCPT_SS: /* Stack segment exception. */
1805 case X86_XCPT_NP: /* Segment not present exception. */
1806 {
1807 Event.au64[0] = 0;
1808 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1809 Event.n.u1Valid = 1;
1810 Event.n.u8Vector = vector;
1811
1812 switch(vector)
1813 {
1814 case X86_XCPT_GP:
1815 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1816 Event.n.u1ErrorCodeValid = 1;
1817 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1818 break;
1819 case X86_XCPT_DE:
1820 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1821 break;
1822 case X86_XCPT_UD:
1823 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1824 break;
1825 case X86_XCPT_SS:
1826 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1827 Event.n.u1ErrorCodeValid = 1;
1828 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1829 break;
1830 case X86_XCPT_NP:
1831 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1832 Event.n.u1ErrorCodeValid = 1;
1833 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1834 break;
1835 }
1836 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1837 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1838
1839 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1840 goto ResumeExecution;
1841 }
1842#endif
1843 default:
1844 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1845 rc = VERR_EM_INTERNAL_ERROR;
1846 break;
1847
1848 } /* switch (vector) */
1849 break;
1850 }
1851
1852 case SVM_EXIT_NPF:
1853 {
1854 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1855 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1856 RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1857 PGMMODE enmShwPagingMode;
1858
1859 Assert(pVM->hwaccm.s.fNestedPaging);
1860 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1861
1862#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1863 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1864 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1865 && (uFaultAddress & 0xfff) == 0x080
1866 && !(errCode & X86_TRAP_PF_P) /* not present */
1867 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1868 && !CPUMIsGuestInLongModeEx(pCtx)
1869 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1870 {
1871 RTGCPHYS GCPhysApicBase;
1872 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1873 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1874
1875 if (uFaultAddress == GCPhysApicBase + 0x80)
1876 {
1877 /* Only attempt to patch the instruction once. */
1878 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1879 if (!pPatch)
1880 {
1881 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1882 break;
1883 }
1884 }
1885 }
1886#endif
1887
1888 /* Exit qualification contains the linear address of the page fault. */
1889 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1890 TRPMSetErrorCode(pVCpu, errCode);
1891 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1892
1893 /* Handle the pagefault trap for the nested shadow table. */
1894#if HC_ARCH_BITS == 32
1895 if (CPUMIsGuestInLongModeEx(pCtx))
1896 enmShwPagingMode = PGMMODE_AMD64_NX;
1897 else
1898#endif
1899 enmShwPagingMode = PGMGetHostMode(pVM);
1900
1901 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1902 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1903 if (rc == VINF_SUCCESS)
1904 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1905 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1906 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1907
1908 TRPMResetTrap(pVCpu);
1909
1910 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1911 goto ResumeExecution;
1912 }
1913
1914#ifdef VBOX_STRICT
1915 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1916 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1917#endif
1918 /* Need to go back to the recompiler to emulate the instruction. */
1919 TRPMResetTrap(pVCpu);
1920 break;
1921 }
1922
1923 case SVM_EXIT_VINTR:
1924 /* A virtual interrupt is about to be delivered, which means IF=1. */
1925 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1926 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1927 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1928 goto ResumeExecution;
1929
1930 case SVM_EXIT_FERR_FREEZE:
1931 case SVM_EXIT_INTR:
1932 case SVM_EXIT_NMI:
1933 case SVM_EXIT_SMI:
1934 case SVM_EXIT_INIT:
1935 /* External interrupt; leave to allow it to be dispatched again. */
1936 rc = VINF_EM_RAW_INTERRUPT;
1937 break;
1938
1939 case SVM_EXIT_WBINVD:
1940 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1941 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1942 /* Skip instruction and continue directly. */
1943 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1944 /* Continue execution.*/
1945 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1946 goto ResumeExecution;
1947
1948 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1949 {
1950 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1951 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1952 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1953 if (rc == VINF_SUCCESS)
1954 {
1955 /* Update EIP and continue execution. */
1956 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1957 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1958 goto ResumeExecution;
1959 }
1960 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1961 rc = VINF_EM_RAW_EMULATE_INSTR;
1962 break;
1963 }
1964
1965 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1966 {
1967 Log2(("SVM: Rdtsc\n"));
1968 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1969 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1970 if (rc == VINF_SUCCESS)
1971 {
1972 /* Update EIP and continue execution. */
1973 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1974 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1975 goto ResumeExecution;
1976 }
1977 rc = VINF_EM_RAW_EMULATE_INSTR;
1978 break;
1979 }
1980
1981 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1982 {
1983 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1984 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1985 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1986 if (rc == VINF_SUCCESS)
1987 {
1988 /* Update EIP and continue execution. */
1989 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1990 goto ResumeExecution;
1991 }
1992 rc = VINF_EM_RAW_EMULATE_INSTR;
1993 break;
1994 }
1995
1996 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1997 {
1998 Log2(("SVM: Rdtscp\n"));
1999 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2000 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
2001 if (rc == VINF_SUCCESS)
2002 {
2003 /* Update EIP and continue execution. */
2004 pCtx->rip += 3; /* Note! hardcoded opcode size! */
2005 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2006 goto ResumeExecution;
2007 }
2008 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
2009 rc = VINF_EM_RAW_EMULATE_INSTR;
2010 break;
2011 }
2012
2013 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
2014 {
2015 Log2(("SVM: invlpg\n"));
2016 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2017
2018 Assert(!pVM->hwaccm.s.fNestedPaging);
2019
2020 /* Truly a pita. Why can't SVM give the same information as VT-x? */
2021 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
2022 if (rc == VINF_SUCCESS)
2023 {
2024 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
2025 goto ResumeExecution; /* eip already updated */
2026 }
2027 break;
2028 }
2029
2030 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2031 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2032 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2033 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2034 {
2035 uint32_t cbSize;
2036
2037 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2038 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2039 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2040
2041 switch (exitCode - SVM_EXIT_WRITE_CR0)
2042 {
2043 case 0:
2044 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2045 break;
2046 case 2:
2047 break;
2048 case 3:
2049 Assert(!pVM->hwaccm.s.fNestedPaging);
2050 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2051 break;
2052 case 4:
2053 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2054 break;
2055 case 8:
2056 break;
2057 default:
2058 AssertFailed();
2059 }
2060 if (rc == VINF_SUCCESS)
2061 {
2062 /* EIP has been updated already. */
2063
2064 /* Only resume if successful. */
2065 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2066 goto ResumeExecution;
2067 }
2068 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2069 break;
2070 }
2071
2072 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2073 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2074 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2075 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2076 {
2077 uint32_t cbSize;
2078
2079 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2080 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2081 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2082 if (rc == VINF_SUCCESS)
2083 {
2084 /* EIP has been updated already. */
2085
2086 /* Only resume if successful. */
2087 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2088 goto ResumeExecution;
2089 }
2090 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2091 break;
2092 }
2093
2094 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2095 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2096 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2097 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2098 {
2099 uint32_t cbSize;
2100
2101 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2102 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2103
2104 if ( !DBGFIsStepping(pVCpu)
2105 && !CPUMIsHyperDebugStateActive(pVCpu))
2106 {
2107 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2108
2109 /* Disable drx move intercepts. */
2110 pVMCB->ctrl.u16InterceptRdDRx = 0;
2111 pVMCB->ctrl.u16InterceptWrDRx = 0;
2112
2113 /* Save the host and load the guest debug state. */
2114 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2115 AssertRC(rc);
2116
2117 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2118 goto ResumeExecution;
2119 }
2120
2121 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2122 if (rc == VINF_SUCCESS)
2123 {
2124 /* EIP has been updated already. */
2125 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2126
2127 /* Only resume if successful. */
2128 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2129 goto ResumeExecution;
2130 }
2131 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2132 break;
2133 }
2134
2135 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2136 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2137 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2138 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2139 {
2140 uint32_t cbSize;
2141
2142 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2143 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2144
2145 if (!DBGFIsStepping(pVCpu))
2146 {
2147 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2148
2149 /* Disable drx move intercepts. */
2150 pVMCB->ctrl.u16InterceptRdDRx = 0;
2151 pVMCB->ctrl.u16InterceptWrDRx = 0;
2152
2153 /* Save the host and load the guest debug state. */
2154 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2155 AssertRC(rc);
2156
2157 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2158 goto ResumeExecution;
2159 }
2160
2161 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2162 if (rc == VINF_SUCCESS)
2163 {
2164 /* EIP has been updated already. */
2165
2166 /* Only resume if successful. */
2167 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2168 goto ResumeExecution;
2169 }
2170 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2171 break;
2172 }
2173
2174 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2175 case SVM_EXIT_IOIO: /* I/O instruction. */
2176 {
2177 SVM_IOIO_EXIT IoExitInfo;
2178 uint32_t uIOSize, uAndVal;
2179
2180 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2181
2182 /** @todo could use a lookup table here */
2183 if (IoExitInfo.n.u1OP8)
2184 {
2185 uIOSize = 1;
2186 uAndVal = 0xff;
2187 }
2188 else
2189 if (IoExitInfo.n.u1OP16)
2190 {
2191 uIOSize = 2;
2192 uAndVal = 0xffff;
2193 }
2194 else
2195 if (IoExitInfo.n.u1OP32)
2196 {
2197 uIOSize = 4;
2198 uAndVal = 0xffffffff;
2199 }
2200 else
2201 {
2202 AssertFailed(); /* should be fatal. */
2203 rc = VINF_EM_RAW_EMULATE_INSTR;
2204 break;
2205 }
2206
2207 if (IoExitInfo.n.u1STR)
2208 {
2209 /* ins/outs */
2210 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2211
2212 /* Disassemble manually to deal with segment prefixes. */
2213 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2214 if (rc == VINF_SUCCESS)
2215 {
2216 if (IoExitInfo.n.u1Type == 0)
2217 {
2218 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2219 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2220 rc = VBOXSTRICTRC_TODO(IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2221 }
2222 else
2223 {
2224 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2225 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2226 rc = VBOXSTRICTRC_TODO(IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2227 }
2228 }
2229 else
2230 rc = VINF_EM_RAW_EMULATE_INSTR;
2231 }
2232 else
2233 {
2234 /* normal in/out */
2235 Assert(!IoExitInfo.n.u1REP);
2236
2237 if (IoExitInfo.n.u1Type == 0)
2238 {
2239 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2240 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2241 rc = VBOXSTRICTRC_TODO(IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2242 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2243 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2244 }
2245 else
2246 {
2247 uint32_t u32Val = 0;
2248
2249 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2250 rc = VBOXSTRICTRC_TODO(IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize));
2251 if (IOM_SUCCESS(rc))
2252 {
2253 /* Write back to the EAX register. */
2254 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2255 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2256 }
2257 else
2258 if (rc == VINF_IOM_HC_IOPORT_READ)
2259 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2260 }
2261 }
2262 /*
2263 * Handled the I/O return codes.
2264 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2265 */
2266 if (IOM_SUCCESS(rc))
2267 {
2268 /* Update EIP and continue execution. */
2269 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2270 if (RT_LIKELY(rc == VINF_SUCCESS))
2271 {
2272 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2273 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2274 {
2275 /* IO operation lookup arrays. */
2276 static uint32_t const aIOSize[4] = {1, 2, 0, 4};
2277
2278 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2279 for (unsigned i=0;i<4;i++)
2280 {
2281 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2282
2283 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2284 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2285 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2286 {
2287 SVM_EVENT Event;
2288
2289 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2290
2291 /* Clear all breakpoint status flags and set the one we just hit. */
2292 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2293 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2294
2295 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2296 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2297 * the contents have been read.
2298 */
2299 pVMCB->guest.u64DR6 = pCtx->dr[6];
2300
2301 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2302 pCtx->dr[7] &= ~X86_DR7_GD;
2303
2304 /* Paranoia. */
2305 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2306 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2307 pCtx->dr[7] |= 0x400; /* must be one */
2308
2309 pVMCB->guest.u64DR7 = pCtx->dr[7];
2310
2311 /* Inject the exception. */
2312 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2313
2314 Event.au64[0] = 0;
2315 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2316 Event.n.u1Valid = 1;
2317 Event.n.u8Vector = X86_XCPT_DB;
2318
2319 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2320
2321 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2322 goto ResumeExecution;
2323 }
2324 }
2325 }
2326
2327 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2328 goto ResumeExecution;
2329 }
2330 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2331 break;
2332 }
2333
2334#ifdef VBOX_STRICT
2335 if (rc == VINF_IOM_HC_IOPORT_READ)
2336 Assert(IoExitInfo.n.u1Type != 0);
2337 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2338 Assert(IoExitInfo.n.u1Type == 0);
2339 else
2340 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2341#endif
2342 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2343 break;
2344 }
2345
2346 case SVM_EXIT_HLT:
2347 /** Check if external interrupts are pending; if so, don't switch back. */
2348 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2349 pCtx->rip++; /* skip hlt */
2350 if ( pCtx->eflags.Bits.u1IF
2351 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2352 goto ResumeExecution;
2353
2354 rc = VINF_EM_HALT;
2355 break;
2356
2357 case SVM_EXIT_MWAIT_UNCOND:
2358 Log2(("SVM: mwait\n"));
2359 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2360 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2361 if ( rc == VINF_EM_HALT
2362 || rc == VINF_SUCCESS)
2363 {
2364 /* Update EIP and continue execution. */
2365 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2366
2367 /** Check if external interrupts are pending; if so, don't switch back. */
2368 if ( rc == VINF_SUCCESS
2369 || ( rc == VINF_EM_HALT
2370 && pCtx->eflags.Bits.u1IF
2371 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2372 )
2373 goto ResumeExecution;
2374 }
2375 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2376 break;
2377
2378 case SVM_EXIT_VMMCALL:
2379 rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2380 if (rc == VINF_SUCCESS)
2381 {
2382 goto ResumeExecution; /* rip already updated. */
2383 }
2384 /* no break */
2385
2386 case SVM_EXIT_RSM:
2387 case SVM_EXIT_INVLPGA:
2388 case SVM_EXIT_VMRUN:
2389 case SVM_EXIT_VMLOAD:
2390 case SVM_EXIT_VMSAVE:
2391 case SVM_EXIT_STGI:
2392 case SVM_EXIT_CLGI:
2393 case SVM_EXIT_SKINIT:
2394 {
2395 /* Unsupported instructions. */
2396 SVM_EVENT Event;
2397
2398 Event.au64[0] = 0;
2399 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2400 Event.n.u1Valid = 1;
2401 Event.n.u8Vector = X86_XCPT_UD;
2402
2403 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2404 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2405
2406 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2407 goto ResumeExecution;
2408 }
2409
2410 /* Emulate in ring 3. */
2411 case SVM_EXIT_MSR:
2412 {
2413 uint32_t cbSize;
2414
2415 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2416 if ( pVM->hwaccm.s.fTPRPatchingActive
2417 && pCtx->ecx == MSR_K8_LSTAR
2418 && pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2419 {
2420 if ((pCtx->eax & 0xff) != u8LastTPR)
2421 {
2422 Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2423
2424 /* Our patch code uses LSTAR for TPR caching. */
2425 rc = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2426 AssertRC(rc);
2427 }
2428
2429 /* Skip the instruction and continue. */
2430 pCtx->rip += 2; /* wrmsr = [0F 30] */
2431
2432 /* Only resume if successful. */
2433 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2434 goto ResumeExecution;
2435 }
2436
2437 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2438 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2439 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2440 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2441 if (rc == VINF_SUCCESS)
2442 {
2443 /* EIP has been updated already. */
2444
2445 /* Only resume if successful. */
2446 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2447 goto ResumeExecution;
2448 }
2449 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2450 break;
2451 }
2452
2453 case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler*/
2454 Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVMCB->ctrl.u64ExitInfo2));
2455 if ( !(pVMCB->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET | SVM_EXIT2_TASK_SWITCH_JMP))
2456 && pVCpu->hwaccm.s.Event.fPending)
2457 {
2458 SVM_EVENT Event;
2459
2460 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
2461
2462 /* Caused by an injected interrupt. */
2463 pVCpu->hwaccm.s.Event.fPending = false;
2464
2465 switch (Event.n.u3Type)
2466 {
2467 case SVM_EVENT_EXTERNAL_IRQ:
2468 case SVM_EVENT_NMI:
2469 Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2470 Assert(!Event.n.u1ErrorCodeValid);
2471 rc = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2472 AssertRC(rc);
2473 break;
2474
2475 default:
2476 /* Exceptions and software interrupts can just be restarted. */
2477 break;
2478 }
2479 }
2480 rc = VERR_EM_INTERPRETER;
2481 break;
2482
2483 case SVM_EXIT_MONITOR:
2484 case SVM_EXIT_PAUSE:
2485 case SVM_EXIT_MWAIT_ARMED:
2486 rc = VERR_EM_INTERPRETER;
2487 break;
2488
2489 case SVM_EXIT_SHUTDOWN:
2490 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2491 break;
2492
2493 case SVM_EXIT_IDTR_READ:
2494 case SVM_EXIT_GDTR_READ:
2495 case SVM_EXIT_LDTR_READ:
2496 case SVM_EXIT_TR_READ:
2497 case SVM_EXIT_IDTR_WRITE:
2498 case SVM_EXIT_GDTR_WRITE:
2499 case SVM_EXIT_LDTR_WRITE:
2500 case SVM_EXIT_TR_WRITE:
2501 case SVM_EXIT_CR0_SEL_WRITE:
2502 default:
2503 /* Unexpected exit codes. */
2504 rc = VERR_EM_INTERNAL_ERROR;
2505 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2506 break;
2507 }
2508
2509end:
2510
2511 /* Signal changes for the recompiler. */
2512 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2513
2514 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2515 if (exitCode == SVM_EXIT_INTR)
2516 {
2517 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2518 /* On the next entry we'll only sync the host context. */
2519 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2520 }
2521 else
2522 {
2523 /* On the next entry we'll sync everything. */
2524 /** @todo we can do better than this */
2525 /* Not in the VINF_PGM_CHANGE_MODE though! */
2526 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2527 }
2528
2529 /* translate into a less severe return code */
2530 if (rc == VERR_EM_INTERPRETER)
2531 rc = VINF_EM_RAW_EMULATE_INSTR;
2532
2533 /* Just set the correct state here instead of trying to catch every goto above. */
2534 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2535
2536#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2537 /* Restore interrupts if we exitted after disabling them. */
2538 if (uOldEFlags != ~(RTCCUINTREG)0)
2539 ASMSetFlags(uOldEFlags);
2540#endif
2541
2542 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2543 return rc;
2544}
2545
2546/**
2547 * Emulate simple mov tpr instruction
2548 *
2549 * @returns VBox status code.
2550 * @param pVM The VM to operate on.
2551 * @param pVCpu The VM CPU to operate on.
2552 * @param pCtx CPU context
2553 */
2554static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2555{
2556 int rc;
2557
2558 LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2559
2560 while (true)
2561 {
2562 bool fPending;
2563 uint8_t u8Tpr;
2564
2565 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2566 if (!pPatch)
2567 break;
2568
2569 switch(pPatch->enmType)
2570 {
2571 case HWACCMTPRINSTR_READ:
2572 /* TPR caching in CR8 */
2573 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2574 AssertRC(rc);
2575
2576 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2577 AssertRC(rc);
2578
2579 LogFlow(("Emulated read successfully\n"));
2580 pCtx->rip += pPatch->cbOp;
2581 break;
2582
2583 case HWACCMTPRINSTR_WRITE_REG:
2584 case HWACCMTPRINSTR_WRITE_IMM:
2585 /* Fetch the new TPR value */
2586 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2587 {
2588 uint32_t val;
2589
2590 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2591 AssertRC(rc);
2592 u8Tpr = val;
2593 }
2594 else
2595 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2596
2597 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2598 AssertRC(rc);
2599 LogFlow(("Emulated write successfully\n"));
2600 pCtx->rip += pPatch->cbOp;
2601 break;
2602 default:
2603 AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_INTERNAL_ERROR);
2604 }
2605 }
2606 return VINF_SUCCESS;
2607}
2608
2609
2610/**
2611 * Enters the AMD-V session
2612 *
2613 * @returns VBox status code.
2614 * @param pVM The VM to operate on.
2615 * @param pVCpu The VM CPU to operate on.
2616 * @param pCpu CPU info struct
2617 */
2618VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2619{
2620 Assert(pVM->hwaccm.s.svm.fSupported);
2621
2622 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2623 pVCpu->hwaccm.s.fResumeVM = false;
2624
2625 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2626 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2627
2628 return VINF_SUCCESS;
2629}
2630
2631
2632/**
2633 * Leaves the AMD-V session
2634 *
2635 * @returns VBox status code.
2636 * @param pVM The VM to operate on.
2637 * @param pVCpu The VM CPU to operate on.
2638 * @param pCtx CPU context
2639 */
2640VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2641{
2642 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2643
2644 Assert(pVM->hwaccm.s.svm.fSupported);
2645
2646#ifdef DEBUG
2647 if (CPUMIsHyperDebugStateActive(pVCpu))
2648 {
2649 CPUMR0LoadHostDebugState(pVM, pVCpu);
2650 }
2651 else
2652#endif
2653 /* Save the guest debug state if necessary. */
2654 if (CPUMIsGuestDebugStateActive(pVCpu))
2655 {
2656 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2657
2658 /* Intercept all DRx reads and writes again. Changed later on. */
2659 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2660 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2661
2662 /* Resync the debug registers the next time. */
2663 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2664 }
2665 else
2666 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2667
2668 return VINF_SUCCESS;
2669}
2670
2671
2672static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2673{
2674 OP_PARAMVAL param1;
2675 RTGCPTR addr;
2676
2677 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2678 if(RT_FAILURE(rc))
2679 return VERR_EM_INTERPRETER;
2680
2681 switch(param1.type)
2682 {
2683 case PARMTYPE_IMMEDIATE:
2684 case PARMTYPE_ADDRESS:
2685 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2686 return VERR_EM_INTERPRETER;
2687 addr = param1.val.val64;
2688 break;
2689
2690 default:
2691 return VERR_EM_INTERPRETER;
2692 }
2693
2694 /** @todo is addr always a flat linear address or ds based
2695 * (in absence of segment override prefixes)????
2696 */
2697 rc = PGMInvalidatePage(pVCpu, addr);
2698 if (RT_SUCCESS(rc))
2699 return VINF_SUCCESS;
2700
2701 AssertRC(rc);
2702 return rc;
2703}
2704
2705/**
2706 * Interprets INVLPG
2707 *
2708 * @returns VBox status code.
2709 * @retval VINF_* Scheduling instructions.
2710 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2711 * @retval VERR_* Fatal errors.
2712 *
2713 * @param pVM The VM handle.
2714 * @param pRegFrame The register frame.
2715 * @param ASID Tagged TLB id for the guest
2716 *
2717 * Updates the EIP if an instruction was executed successfully.
2718 */
2719static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2720{
2721 /*
2722 * Only allow 32 & 64 bits code.
2723 */
2724 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2725 if (enmMode != CPUMODE_16BIT)
2726 {
2727 RTGCPTR pbCode;
2728 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2729 if (RT_SUCCESS(rc))
2730 {
2731 uint32_t cbOp;
2732 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2733
2734 pDis->mode = enmMode;
2735 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2736 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2737 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2738 {
2739 Assert(cbOp == pDis->opsize);
2740 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2741 if (RT_SUCCESS(rc))
2742 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2743
2744 return rc;
2745 }
2746 }
2747 }
2748 return VERR_EM_INTERPRETER;
2749}
2750
2751
2752/**
2753 * Invalidates a guest page
2754 *
2755 * @returns VBox status code.
2756 * @param pVM The VM to operate on.
2757 * @param pVCpu The VM CPU to operate on.
2758 * @param GCVirt Page to invalidate
2759 */
2760VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2761{
2762 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2763
2764 /* Skip it if a TLB flush is already pending. */
2765 if (!fFlushPending)
2766 {
2767 SVM_VMCB *pVMCB;
2768
2769 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2770 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2771 Assert(pVM->hwaccm.s.svm.fSupported);
2772
2773 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2774 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2775
2776#if HC_ARCH_BITS == 32
2777 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2778 if (CPUMIsGuestInLongMode(pVCpu))
2779 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2780 else
2781#endif
2782 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2783 }
2784 return VINF_SUCCESS;
2785}
2786
2787
2788#if 0 /* obsolete, but left here for clarification. */
2789/**
2790 * Invalidates a guest page by physical address
2791 *
2792 * @returns VBox status code.
2793 * @param pVM The VM to operate on.
2794 * @param pVCpu The VM CPU to operate on.
2795 * @param GCPhys Page to invalidate
2796 */
2797VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2798{
2799 Assert(pVM->hwaccm.s.fNestedPaging);
2800 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2801 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2802 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2803 return VINF_SUCCESS;
2804}
2805#endif
2806
2807#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2808/**
2809 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2810 *
2811 * @returns VBox status code.
2812 * @param pVMCBHostPhys Physical address of host VMCB.
2813 * @param pVMCBPhys Physical address of the VMCB.
2814 * @param pCtx Guest context.
2815 * @param pVM The VM to operate on.
2816 * @param pVCpu The VMCPU to operate on.
2817 */
2818DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2819{
2820 uint32_t aParam[4];
2821
2822 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2823 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2824 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2825 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2826
2827 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2828}
2829
2830/**
2831 * Executes the specified handler in 64 mode
2832 *
2833 * @returns VBox status code.
2834 * @param pVM The VM to operate on.
2835 * @param pVCpu The VMCPU to operate on.
2836 * @param pCtx Guest context
2837 * @param pfnHandler RC handler
2838 * @param cbParam Number of parameters
2839 * @param paParam Array of 32 bits parameters
2840 */
2841VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2842{
2843 int rc;
2844 RTHCUINTREG uOldEFlags;
2845
2846 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
2847 AssertReturn(pVM->cCpus == 1, VERR_TOO_MANY_CPUS);
2848 Assert(pfnHandler);
2849
2850 /* Disable interrupts. */
2851 uOldEFlags = ASMIntDisableFlags();
2852
2853 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
2854 CPUMSetHyperEIP(pVCpu, pfnHandler);
2855 for (int i=(int)cbParam-1;i>=0;i--)
2856 CPUMPushHyper(pVCpu, paParam[i]);
2857
2858 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2859 /* Call switcher. */
2860 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2861 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2862
2863 ASMSetFlags(uOldEFlags);
2864 return rc;
2865}
2866
2867#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
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