VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 26044

Last change on this file since 26044 was 26018, checked in by vboxsync, 15 years ago

Missing pending pgm sync handling in VT-x and AMD-V page fault handling. Cause of win2k3 smp guest instability and possibly many others.
Cleaned up InvalidatePage (removed obsolete code).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 114.8 KB
Line 
1/* $Id: HWSVMR0.cpp 26018 2010-01-25 16:06:26Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/cpuset.h>
45#include <iprt/mp.h>
46#include <iprt/time.h>
47#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
48# include <iprt/thread.h>
49#endif
50#include "HWSVMR0.h"
51
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
56static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
57static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62
63/**
64 * Sets up and activates AMD-V on the current CPU
65 *
66 * @returns VBox status code.
67 * @param pCpu CPU info struct
68 * @param pVM The VM to operate on. (can be NULL after a resume!!)
69 * @param pvPageCpu Pointer to the global cpu page
70 * @param pPageCpuPhys Physical address of the global cpu page
71 */
72VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
73{
74 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
75 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
76
77 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
78 uint64_t val = ASMRdMsr(MSR_K6_EFER);
79 if (val & MSR_K6_EFER_SVME)
80 {
81 /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we blindly use AMD-V. */
82 if ( pVM
83 && pVM->hwaccm.s.svm.fIgnoreInUseError)
84 {
85 pCpu->fIgnoreAMDVInUseError = true;
86 }
87
88 if (!pCpu->fIgnoreAMDVInUseError)
89 return VERR_SVM_IN_USE;
90 }
91
92 /* Turn on AMD-V in the EFER MSR. */
93 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
94
95 /* Write the physical page address where the CPU will store the host state while executing the VM. */
96 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
97
98 return VINF_SUCCESS;
99}
100
101/**
102 * Deactivates AMD-V on the current CPU
103 *
104 * @returns VBox status code.
105 * @param pCpu CPU info struct
106 * @param pvPageCpu Pointer to the global cpu page
107 * @param pPageCpuPhys Physical address of the global cpu page
108 */
109VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
110{
111 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
112 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
113
114 /* Turn off AMD-V in the EFER MSR. */
115 uint64_t val = ASMRdMsr(MSR_K6_EFER);
116 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
117
118 /* Invalidate host state physical address. */
119 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
120
121 return VINF_SUCCESS;
122}
123
124/**
125 * Does Ring-0 per VM AMD-V init.
126 *
127 * @returns VBox status code.
128 * @param pVM The VM to operate on.
129 */
130VMMR0DECL(int) SVMR0InitVM(PVM pVM)
131{
132 int rc;
133
134 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
135
136 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
137 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
138 if (RT_FAILURE(rc))
139 return rc;
140
141 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
142 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
143 /* Set all bits to intercept all IO accesses. */
144 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
145
146 /* Erratum 170 which requires a forced TLB flush for each world switch:
147 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
148 *
149 * All BH-G1/2 and DH-G1/2 models include a fix:
150 * Athlon X2: 0x6b 1/2
151 * 0x68 1/2
152 * Athlon 64: 0x7f 1
153 * 0x6f 2
154 * Sempron: 0x7f 1/2
155 * 0x6f 2
156 * 0x6c 2
157 * 0x7c 2
158 * Turion 64: 0x68 2
159 *
160 */
161 uint32_t u32Dummy;
162 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
163 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
164 u32BaseFamily= (u32Version >> 8) & 0xf;
165 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
166 u32Model = ((u32Version >> 4) & 0xf);
167 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
168 u32Stepping = u32Version & 0xf;
169 if ( u32Family == 0xf
170 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
171 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
172 {
173 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
174 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
175 }
176
177 /* Allocate VMCBs for all guest CPUs. */
178 for (VMCPUID i = 0; i < pVM->cCpus; i++)
179 {
180 PVMCPU pVCpu = &pVM->aCpus[i];
181
182 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
183 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
184 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
185
186 /* Allocate one page for the host context */
187 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
188 if (RT_FAILURE(rc))
189 return rc;
190
191 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
192 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
193 Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);
194 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
195
196 /* Allocate one page for the VM control block (VMCB). */
197 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
198 if (RT_FAILURE(rc))
199 return rc;
200
201 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
202 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
203 Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);
204 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
205
206 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
207 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
208 if (RT_FAILURE(rc))
209 return rc;
210
211 pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
212 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
213 /* Set all bits to intercept all MSR accesses. */
214 ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
215 }
216
217 return VINF_SUCCESS;
218}
219
220/**
221 * Does Ring-0 per VM AMD-V termination.
222 *
223 * @returns VBox status code.
224 * @param pVM The VM to operate on.
225 */
226VMMR0DECL(int) SVMR0TermVM(PVM pVM)
227{
228 for (VMCPUID i = 0; i < pVM->cCpus; i++)
229 {
230 PVMCPU pVCpu = &pVM->aCpus[i];
231
232 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
233 {
234 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
235 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
236 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
237 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
238 }
239
240 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
241 {
242 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
243 pVCpu->hwaccm.s.svm.pVMCB = 0;
244 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
245 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
246 }
247 if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
248 {
249 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
250 pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
251 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
252 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
253 }
254 }
255 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
256 {
257 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
258 pVM->hwaccm.s.svm.pIOBitmap = 0;
259 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
260 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
261 }
262 return VINF_SUCCESS;
263}
264
265/**
266 * Sets up AMD-V for the specified VM
267 *
268 * @returns VBox status code.
269 * @param pVM The VM to operate on.
270 */
271VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
272{
273 int rc = VINF_SUCCESS;
274
275 AssertReturn(pVM, VERR_INVALID_PARAMETER);
276
277 Assert(pVM->hwaccm.s.svm.fSupported);
278
279 for (VMCPUID i = 0; i < pVM->cCpus; i++)
280 {
281 PVMCPU pVCpu = &pVM->aCpus[i];
282 SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
283
284 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
285
286 /* Program the control fields. Most of them never have to be changed again. */
287 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
288 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
289 if (!pVM->hwaccm.s.fNestedPaging)
290 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
291 else
292 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
293
294 /*
295 * CR0/3/4 writes must be intercepted for obvious reasons.
296 */
297 if (!pVM->hwaccm.s.fNestedPaging)
298 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
299 else
300 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
301
302 /* Intercept all DRx reads and writes by default. Changed later on. */
303 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
304 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
305
306 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
307 * All breakpoints are automatically cleared when the VM exits.
308 */
309
310 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
311#ifndef DEBUG
312 if (pVM->hwaccm.s.fNestedPaging)
313 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
314#endif
315
316 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
317 | SVM_CTRL1_INTERCEPT_VINTR
318 | SVM_CTRL1_INTERCEPT_NMI
319 | SVM_CTRL1_INTERCEPT_SMI
320 | SVM_CTRL1_INTERCEPT_INIT
321 | SVM_CTRL1_INTERCEPT_RDPMC
322 | SVM_CTRL1_INTERCEPT_CPUID
323 | SVM_CTRL1_INTERCEPT_RSM
324 | SVM_CTRL1_INTERCEPT_HLT
325 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
326 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
327 | SVM_CTRL1_INTERCEPT_INVLPG
328 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
329 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
330 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
331 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
332 ;
333 /* With nested paging we don't care about invlpg anymore. */
334 if (pVM->hwaccm.s.fNestedPaging)
335 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
336
337 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
338 | SVM_CTRL2_INTERCEPT_VMMCALL
339 | SVM_CTRL2_INTERCEPT_VMLOAD
340 | SVM_CTRL2_INTERCEPT_VMSAVE
341 | SVM_CTRL2_INTERCEPT_STGI
342 | SVM_CTRL2_INTERCEPT_CLGI
343 | SVM_CTRL2_INTERCEPT_SKINIT
344 | SVM_CTRL2_INTERCEPT_WBINVD
345 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
346 ;
347 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
348 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
349 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
350
351 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
352 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
353 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
354 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
355
356 /* Set IO and MSR bitmap addresses. */
357 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
358 pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
359
360 /* No LBR virtualization. */
361 pVMCB->ctrl.u64LBRVirt = 0;
362
363 /** The ASID must start at 1; the host uses 0. */
364 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
365
366 /** Setup the PAT msr (nested paging only) */
367 pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
368
369 /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
370 * to modify them directly.
371 */
372 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
373 svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
374 svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
375 svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
376 svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
377 svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
378 svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
379 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
380 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
381 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
382 }
383
384 return rc;
385}
386
387
388/**
389 * Sets the permission bits for the specified MSR
390 *
391 * @param pVCpu The VMCPU to operate on.
392 * @param ulMSR MSR value
393 * @param fRead Reading allowed/disallowed
394 * @param fWrite Writing allowed/disallowed
395 */
396static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
397{
398 unsigned ulBit;
399 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
400
401 if (ulMSR <= 0x00001FFF)
402 {
403 /* Pentium-compatible MSRs */
404 ulBit = ulMSR * 2;
405 }
406 else
407 if ( ulMSR >= 0xC0000000
408 && ulMSR <= 0xC0001FFF)
409 {
410 /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
411 ulBit = (ulMSR - 0xC0000000) * 2;
412 pMSRBitmap += 0x800;
413 }
414 else
415 if ( ulMSR >= 0xC0010000
416 && ulMSR <= 0xC0011FFF)
417 {
418 /* AMD Seventh and Eighth Generation Processor MSRs */
419 ulBit = (ulMSR - 0xC0001000) * 2;
420 pMSRBitmap += 0x1000;
421 }
422 else
423 {
424 AssertFailed();
425 return;
426 }
427 Assert(ulBit < 16 * 1024 - 1);
428 if (fRead)
429 ASMBitClear(pMSRBitmap, ulBit);
430 else
431 ASMBitSet(pMSRBitmap, ulBit);
432
433 if (fWrite)
434 ASMBitClear(pMSRBitmap, ulBit + 1);
435 else
436 ASMBitSet(pMSRBitmap, ulBit + 1);
437}
438
439/**
440 * Injects an event (trap or external interrupt)
441 *
442 * @param pVCpu The VMCPU to operate on.
443 * @param pVMCB SVM control block
444 * @param pCtx CPU Context
445 * @param pIntInfo SVM interrupt info
446 */
447inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
448{
449#ifdef VBOX_WITH_STATISTICS
450 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
451#endif
452
453#ifdef VBOX_STRICT
454 if (pEvent->n.u8Vector == 0xE)
455 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
456 else
457 if (pEvent->n.u8Vector < 0x20)
458 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
459 else
460 {
461 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
462 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
463 Assert(pCtx->eflags.u32 & X86_EFL_IF);
464 }
465#endif
466
467 /* Set event injection state. */
468 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
469}
470
471
472/**
473 * Checks for pending guest interrupts and injects them
474 *
475 * @returns VBox status code.
476 * @param pVM The VM to operate on.
477 * @param pVCpu The VM CPU to operate on.
478 * @param pVMCB SVM control block
479 * @param pCtx CPU Context
480 */
481static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
482{
483 int rc;
484
485 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
486 if (pVCpu->hwaccm.s.Event.fPending)
487 {
488 SVM_EVENT Event;
489
490 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
491 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
492 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
493 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
494
495 pVCpu->hwaccm.s.Event.fPending = false;
496 return VINF_SUCCESS;
497 }
498
499 /* If an active trap is already pending, then we must forward it first! */
500 if (!TRPMHasTrap(pVCpu))
501 {
502 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
503 {
504 SVM_EVENT Event;
505
506 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
507 Event.n.u8Vector = X86_XCPT_NMI;
508 Event.n.u1Valid = 1;
509 Event.n.u32ErrorCode = 0;
510 Event.n.u3Type = SVM_EVENT_NMI;
511
512 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
513 return VINF_SUCCESS;
514 }
515
516 /* @todo SMI interrupts. */
517
518 /* When external interrupts are pending, we should exit the VM when IF is set. */
519 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
520 {
521 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
522 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
523 {
524 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
525 {
526 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
527 LogFlow(("Enable irq window exit!\n"));
528 else
529 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
530
531 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
532 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
533 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
534 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
535 }
536 }
537 else
538 {
539 uint8_t u8Interrupt;
540
541 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
542 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
543 if (RT_SUCCESS(rc))
544 {
545 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
546 AssertRC(rc);
547 }
548 else
549 {
550 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
551 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
552 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
553 /* Just continue */
554 }
555 }
556 }
557 }
558
559#ifdef VBOX_STRICT
560 if (TRPMHasTrap(pVCpu))
561 {
562 uint8_t u8Vector;
563 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
564 AssertRC(rc);
565 }
566#endif
567
568 if ( (pCtx->eflags.u32 & X86_EFL_IF)
569 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
570 && TRPMHasTrap(pVCpu)
571 )
572 {
573 uint8_t u8Vector;
574 TRPMEVENT enmType;
575 SVM_EVENT Event;
576 RTGCUINT u32ErrorCode;
577
578 Event.au64[0] = 0;
579
580 /* If a new event is pending, then dispatch it now. */
581 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
582 AssertRC(rc);
583 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
584 Assert(enmType != TRPM_SOFTWARE_INT);
585
586 /* Clear the pending trap. */
587 rc = TRPMResetTrap(pVCpu);
588 AssertRC(rc);
589
590 Event.n.u8Vector = u8Vector;
591 Event.n.u1Valid = 1;
592 Event.n.u32ErrorCode = u32ErrorCode;
593
594 if (enmType == TRPM_TRAP)
595 {
596 switch (u8Vector) {
597 case 8:
598 case 10:
599 case 11:
600 case 12:
601 case 13:
602 case 14:
603 case 17:
604 /* Valid error codes. */
605 Event.n.u1ErrorCodeValid = 1;
606 break;
607 default:
608 break;
609 }
610 if (u8Vector == X86_XCPT_NMI)
611 Event.n.u3Type = SVM_EVENT_NMI;
612 else
613 Event.n.u3Type = SVM_EVENT_EXCEPTION;
614 }
615 else
616 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
617
618 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
619 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
620 } /* if (interrupts can be dispatched) */
621
622 return VINF_SUCCESS;
623}
624
625/**
626 * Save the host state
627 *
628 * @returns VBox status code.
629 * @param pVM The VM to operate on.
630 * @param pVCpu The VM CPU to operate on.
631 */
632VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
633{
634 NOREF(pVM);
635 NOREF(pVCpu);
636 /* Nothing to do here. */
637 return VINF_SUCCESS;
638}
639
640/**
641 * Loads the guest state
642 *
643 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
644 *
645 * @returns VBox status code.
646 * @param pVM The VM to operate on.
647 * @param pVCpu The VM CPU to operate on.
648 * @param pCtx Guest context
649 */
650VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
651{
652 RTGCUINTPTR val;
653 SVM_VMCB *pVMCB;
654
655 if (pVM == NULL)
656 return VERR_INVALID_PARAMETER;
657
658 /* Setup AMD SVM. */
659 Assert(pVM->hwaccm.s.svm.fSupported);
660
661 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
662 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
663
664 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
665 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
666 {
667 SVM_WRITE_SELREG(CS, cs);
668 SVM_WRITE_SELREG(SS, ss);
669 SVM_WRITE_SELREG(DS, ds);
670 SVM_WRITE_SELREG(ES, es);
671 SVM_WRITE_SELREG(FS, fs);
672 SVM_WRITE_SELREG(GS, gs);
673 }
674
675 /* Guest CPU context: LDTR. */
676 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
677 {
678 SVM_WRITE_SELREG(LDTR, ldtr);
679 }
680
681 /* Guest CPU context: TR. */
682 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
683 {
684 SVM_WRITE_SELREG(TR, tr);
685 }
686
687 /* Guest CPU context: GDTR. */
688 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
689 {
690 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
691 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
692 }
693
694 /* Guest CPU context: IDTR. */
695 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
696 {
697 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
698 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
699 }
700
701 /*
702 * Sysenter MSRs (unconditional)
703 */
704 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
705 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
706 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
707
708 /* Control registers */
709 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
710 {
711 val = pCtx->cr0;
712 if (!CPUMIsGuestFPUStateActive(pVCpu))
713 {
714 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
715 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
716 }
717 else
718 {
719 /** @todo check if we support the old style mess correctly. */
720 if (!(val & X86_CR0_NE))
721 {
722 Log(("Forcing X86_CR0_NE!!!\n"));
723
724 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
725 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
726 {
727 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
728 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
729 }
730 }
731 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
732 }
733 /* Always enable caching. */
734 val &= ~(X86_CR0_CD|X86_CR0_NW);
735
736 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
737 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
738 if (!pVM->hwaccm.s.fNestedPaging)
739 {
740 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
741 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
742 }
743 pVMCB->guest.u64CR0 = val;
744 }
745 /* CR2 as well */
746 pVMCB->guest.u64CR2 = pCtx->cr2;
747
748 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
749 {
750 /* Save our shadow CR3 register. */
751 if (pVM->hwaccm.s.fNestedPaging)
752 {
753 PGMMODE enmShwPagingMode;
754
755#if HC_ARCH_BITS == 32
756 if (CPUMIsGuestInLongModeEx(pCtx))
757 enmShwPagingMode = PGMMODE_AMD64_NX;
758 else
759#endif
760 enmShwPagingMode = PGMGetHostMode(pVM);
761
762 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
763 Assert(pVMCB->ctrl.u64NestedPagingCR3);
764 pVMCB->guest.u64CR3 = pCtx->cr3;
765 }
766 else
767 {
768 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
769 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
770 }
771 }
772
773 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
774 {
775 val = pCtx->cr4;
776 if (!pVM->hwaccm.s.fNestedPaging)
777 {
778 switch(pVCpu->hwaccm.s.enmShadowMode)
779 {
780 case PGMMODE_REAL:
781 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
782 AssertFailed();
783 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
784
785 case PGMMODE_32_BIT: /* 32-bit paging. */
786 val &= ~X86_CR4_PAE;
787 break;
788
789 case PGMMODE_PAE: /* PAE paging. */
790 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
791 /** @todo use normal 32 bits paging */
792 val |= X86_CR4_PAE;
793 break;
794
795 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
796 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
797#ifdef VBOX_ENABLE_64_BITS_GUESTS
798 break;
799#else
800 AssertFailed();
801 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
802#endif
803
804 default: /* shut up gcc */
805 AssertFailed();
806 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
807 }
808 }
809 pVMCB->guest.u64CR4 = val;
810 }
811
812 /* Debug registers. */
813 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
814 {
815 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
816 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
817
818 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
819 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
820 pCtx->dr[7] |= 0x400; /* must be one */
821
822 pVMCB->guest.u64DR7 = pCtx->dr[7];
823 pVMCB->guest.u64DR6 = pCtx->dr[6];
824
825#ifdef DEBUG
826 /* Sync the hypervisor debug state now if any breakpoint is armed. */
827 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
828 && !CPUMIsHyperDebugStateActive(pVCpu)
829 && !DBGFIsStepping(pVCpu))
830 {
831 /* Save the host and load the hypervisor debug state. */
832 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
833 AssertRC(rc);
834
835 /* DRx intercepts remain enabled. */
836
837 /* Override dr6 & dr7 with the hypervisor values. */
838 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
839 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
840 }
841 else
842#endif
843 /* Sync the debug state now if any breakpoint is armed. */
844 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
845 && !CPUMIsGuestDebugStateActive(pVCpu)
846 && !DBGFIsStepping(pVCpu))
847 {
848 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
849
850 /* Disable drx move intercepts. */
851 pVMCB->ctrl.u16InterceptRdDRx = 0;
852 pVMCB->ctrl.u16InterceptWrDRx = 0;
853
854 /* Save the host and load the guest debug state. */
855 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
856 AssertRC(rc);
857 }
858 }
859
860 /* EIP, ESP and EFLAGS */
861 pVMCB->guest.u64RIP = pCtx->rip;
862 pVMCB->guest.u64RSP = pCtx->rsp;
863 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
864
865 /* Set CPL */
866 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
867
868 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
869 pVMCB->guest.u64RAX = pCtx->rax;
870
871 /* vmrun will fail without MSR_K6_EFER_SVME. */
872 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
873
874 /* 64 bits guest mode? */
875 if (CPUMIsGuestInLongModeEx(pCtx))
876 {
877#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
878 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
879#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
880 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
881#else
882# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
883 if (!pVM->hwaccm.s.fAllow64BitGuests)
884 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
885# endif
886 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
887#endif
888 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
889 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
890 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
891 }
892 else
893 {
894 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
895 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
896
897 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
898 }
899
900 /* TSC offset. */
901 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
902 {
903 uint64_t u64CurTSC = ASMReadTSC();
904 if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
905 {
906 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
907 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
908 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
909 }
910 else
911 {
912 /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
913 LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
914 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
915 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
916 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
917 }
918 }
919 else
920 {
921 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
922 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
923 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
924 }
925
926 /* Sync the various msrs for 64 bits mode. */
927 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
928 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
929 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
930 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
931 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
932
933#ifdef DEBUG
934 /* Intercept X86_XCPT_DB if stepping is enabled */
935 if ( DBGFIsStepping(pVCpu)
936 || CPUMIsHyperDebugStateActive(pVCpu))
937 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
938 else
939 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
940#endif
941
942 /* Done. */
943 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
944
945 return VINF_SUCCESS;
946}
947
948
949/**
950 * Runs guest code in an AMD-V VM.
951 *
952 * @returns VBox status code.
953 * @param pVM The VM to operate on.
954 * @param pVCpu The VM CPU to operate on.
955 * @param pCtx Guest context
956 */
957VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
958{
959 int rc = VINF_SUCCESS;
960 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
961 SVM_VMCB *pVMCB;
962 bool fSyncTPR = false;
963 unsigned cResume = 0;
964 uint8_t u8LastTPR;
965 PHWACCM_CPUINFO pCpu = 0;
966 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
967#ifdef VBOX_STRICT
968 RTCPUID idCpuCheck;
969#endif
970#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
971 uint64_t u64LastTime = RTTimeMilliTS();
972#endif
973
974 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
975
976 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
977 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
978
979 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
980 */
981ResumeExecution:
982 Assert(!HWACCMR0SuspendPending());
983
984 /* Safety precaution; looping for too long here can have a very bad effect on the host */
985 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
986 {
987 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
988 rc = VINF_EM_RAW_INTERRUPT;
989 goto end;
990 }
991
992 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
993 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
994 {
995 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
996 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
997 {
998 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
999 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1000 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1001 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1002 */
1003 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1004 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1005 pVMCB->ctrl.u64IntShadow = 0;
1006 }
1007 }
1008 else
1009 {
1010 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1011 pVMCB->ctrl.u64IntShadow = 0;
1012 }
1013
1014#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1015 if (RT_UNLIKELY(cResume & 0xf) == 0)
1016 {
1017 uint64_t u64CurTime = RTTimeMilliTS();
1018
1019 if (RT_UNLIKELY(u64CurTime > u64LastTime))
1020 {
1021 u64LastTime = u64CurTime;
1022 TMTimerPollVoid(pVM, pVCpu);
1023 }
1024 }
1025#endif
1026
1027 /* Check for pending actions that force us to go back to ring 3. */
1028#ifdef DEBUG
1029 /* Intercept X86_XCPT_DB if stepping is enabled */
1030 if (!DBGFIsStepping(pVCpu))
1031#endif
1032 {
1033 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1034 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1035 {
1036 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1037 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1038 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1039 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1040 goto end;
1041 }
1042 }
1043
1044 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1045 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1046 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1047 {
1048 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1049 rc = VINF_EM_PENDING_REQUEST;
1050 goto end;
1051 }
1052
1053#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1054 /*
1055 * Exit to ring-3 preemption/work is pending.
1056 *
1057 * Interrupts are disabled before the call to make sure we don't miss any interrupt
1058 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1059 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
1060 *
1061 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
1062 * shootdowns rely on this.
1063 */
1064 uOldEFlags = ASMIntDisableFlags();
1065 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1066 {
1067 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1068 rc = VINF_EM_RAW_INTERRUPT;
1069 goto end;
1070 }
1071 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1072#endif
1073
1074 /* When external interrupts are pending, we should exit the VM when IF is set. */
1075 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1076 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1077 if (RT_FAILURE(rc))
1078 {
1079 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1080 goto end;
1081 }
1082
1083 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1084 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1085 * @todo query and update the TPR only when it could have been changed (mmio access)
1086 */
1087 if (pVM->hwaccm.s.fHasIoApic)
1088 {
1089 bool fPending;
1090
1091 /* TPR caching in CR8 */
1092 int rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1093 AssertRC(rc2);
1094
1095 if (pVM->hwaccm.s.fTPRPatchingActive)
1096 {
1097 /* Our patch code uses LSTAR for TPR caching. */
1098 pCtx->msrLSTAR = u8LastTPR;
1099
1100 if (fPending)
1101 {
1102 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
1103 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1104 }
1105 else
1106 /* No interrupts are pending, so we don't need to be explicitely notified.
1107 * There are enough world switches for detecting pending interrupts.
1108 */
1109 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1110 }
1111 else
1112 {
1113 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1114
1115 if (fPending)
1116 {
1117 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1118 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1119 }
1120 else
1121 /* No interrupts are pending, so we don't need to be explicitely notified.
1122 * There are enough world switches for detecting pending interrupts.
1123 */
1124 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1125 }
1126 fSyncTPR = !fPending;
1127 }
1128
1129 /* All done! Let's start VM execution. */
1130 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1131
1132 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1133 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1134
1135#ifdef LOG_ENABLED
1136 pCpu = HWACCMR0GetCurrentCpu();
1137 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1138 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1139 {
1140 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1141 LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1142 else
1143 LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1144 }
1145 if (pCpu->fFlushTLB)
1146 LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1147#endif
1148
1149 /*
1150 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1151 * (until the actual world switch)
1152 */
1153#ifdef VBOX_STRICT
1154 idCpuCheck = RTMpCpuId();
1155#endif
1156 VMMR0LogFlushDisable(pVCpu);
1157
1158 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1159 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1160 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1161 {
1162 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1163 VMMR0LogFlushEnable(pVCpu);
1164 goto end;
1165 }
1166
1167#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1168 /* Disable interrupts to make sure a poke will interrupt execution.
1169 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1170 */
1171 uOldEFlags = ASMIntDisableFlags();
1172 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1173#endif
1174
1175 pCpu = HWACCMR0GetCurrentCpu();
1176 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1177 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1178 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1179 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1180 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1181 {
1182 /* Force a TLB flush on VM entry. */
1183 pVCpu->hwaccm.s.fForceTLBFlush = true;
1184 }
1185 else
1186 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1187
1188 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1189
1190 /** Set TLB flush state as checked until we return from the world switch. */
1191 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
1192
1193 /* Check for tlb shootdown flushes. */
1194 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1195 pVCpu->hwaccm.s.fForceTLBFlush = true;
1196
1197 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1198 if ( pVCpu->hwaccm.s.fForceTLBFlush
1199 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1200 {
1201 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1202 || pCpu->fFlushTLB)
1203 {
1204 pCpu->fFlushTLB = false;
1205 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1206 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1207 pCpu->cTLBFlushes++;
1208 }
1209 else
1210 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1211
1212 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1213 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1214 }
1215 else
1216 {
1217 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1218
1219 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1220 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1221 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1222
1223 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1224 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1225
1226 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1227 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1228 {
1229 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1230 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1231 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1232 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1233 }
1234 }
1235 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1236 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1237
1238 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1239 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1240 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1241 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1242
1243#ifdef VBOX_WITH_STATISTICS
1244 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1245 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1246 else
1247 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1248#endif
1249
1250 /* In case we execute a goto ResumeExecution later on. */
1251 pVCpu->hwaccm.s.fResumeVM = true;
1252 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1253
1254 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1255 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1256 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1257 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1258 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1259
1260#ifdef VBOX_STRICT
1261 Assert(idCpuCheck == RTMpCpuId());
1262#endif
1263 TMNotifyStartOfExecution(pVCpu);
1264#ifdef VBOX_WITH_KERNEL_USING_XMM
1265 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1266#else
1267 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1268#endif
1269 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
1270 ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExit);
1271 /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
1272 if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1273 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1274 TMNotifyEndOfExecution(pVCpu);
1275 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1276 ASMSetFlags(uOldEFlags);
1277#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1278 uOldEFlags = ~(RTCCUINTREG)0;
1279#endif
1280 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1281
1282 /*
1283 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1284 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1285 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1286 */
1287
1288 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1289
1290 /* Reason for the VM exit */
1291 exitCode = pVMCB->ctrl.u64ExitCode;
1292
1293 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1294 {
1295 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1296#ifdef DEBUG
1297 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1298 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1299 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1300 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1301 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1302 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1303 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1304 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1305 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1306 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1307
1308 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1309 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1310 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1311 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1312
1313 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1314 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1315 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1316 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1317 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1318 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1319 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1320 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1321 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1322 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1323
1324 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1325 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1326 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1327 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1328 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1329 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1330 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1331 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1332 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1333 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1334 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1335 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1336 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1337 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1338 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1339 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1340 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1341
1342 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1343 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1344
1345 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1346 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1347 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1348 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1349 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1350 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1351 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1352 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1353 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1354 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1355 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1356 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1357 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1358 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1359 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1360 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1361 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1362 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1363 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1364 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1365
1366 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1367 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1368
1369 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1370 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1371 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1372 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1373
1374 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1375 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1376
1377 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1378 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1379 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1380 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1381
1382 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1383 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1384 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1385 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1386 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1387 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1388 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1389
1390 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1391 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1392 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1393 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1394
1395 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1396 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1397 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1398
1399 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1400 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1401 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1402 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1403 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1404 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1405 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1406 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1407 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1408 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1409 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1410 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1411
1412#endif
1413 rc = VERR_SVM_UNABLE_TO_START_VM;
1414 VMMR0LogFlushEnable(pVCpu);
1415 goto end;
1416 }
1417
1418 /* Let's first sync back eip, esp, and eflags. */
1419 pCtx->rip = pVMCB->guest.u64RIP;
1420 pCtx->rsp = pVMCB->guest.u64RSP;
1421 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1422 /* eax is saved/restore across the vmrun instruction */
1423 pCtx->rax = pVMCB->guest.u64RAX;
1424
1425 /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1426 pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1427 pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1428 pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1429 pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1430 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1431 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1432 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1433 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1434
1435 /* Can be updated behind our back in the nested paging case. */
1436 pCtx->cr2 = pVMCB->guest.u64CR2;
1437
1438 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1439 SVM_READ_SELREG(SS, ss);
1440 SVM_READ_SELREG(CS, cs);
1441 SVM_READ_SELREG(DS, ds);
1442 SVM_READ_SELREG(ES, es);
1443 SVM_READ_SELREG(FS, fs);
1444 SVM_READ_SELREG(GS, gs);
1445
1446 /* Correct the hidden CS granularity flag. Haven't seen it being wrong in
1447 any other register (yet). */
1448 if ( !pCtx->csHid.Attr.n.u1Granularity
1449 && pCtx->csHid.Attr.n.u1Present
1450 && pCtx->csHid.u32Limit > UINT32_C(0xfffff))
1451 {
1452 Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
1453 pCtx->csHid.Attr.n.u1Granularity = 1;
1454 }
1455#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1456 AssertMsg( !pCtx->reg##Hid.Attr.n.u1Present \
1457 || ( pCtx->reg##Hid.Attr.n.u1Granularity \
1458 ? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
1459 : pCtx->reg##Hid.u32Limit <= 0xfffff), \
1460 ("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
1461 SVM_ASSERT_SEL_GRANULARITY(ss);
1462 SVM_ASSERT_SEL_GRANULARITY(cs);
1463 SVM_ASSERT_SEL_GRANULARITY(ds);
1464 SVM_ASSERT_SEL_GRANULARITY(es);
1465 SVM_ASSERT_SEL_GRANULARITY(fs);
1466 SVM_ASSERT_SEL_GRANULARITY(gs);
1467#undef SVM_ASSERT_SEL_GRANULARITY
1468
1469 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1470 SVM_READ_SELREG(LDTR, ldtr);
1471 SVM_READ_SELREG(TR, tr);
1472
1473 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1474 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1475
1476 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1477 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1478
1479 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1480 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1481 if ( pVM->hwaccm.s.fNestedPaging
1482 && pCtx->cr3 != pVMCB->guest.u64CR3)
1483 {
1484 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1485 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1486 }
1487
1488 /* Note! NOW IT'S SAFE FOR LOGGING! */
1489 VMMR0LogFlushEnable(pVCpu);
1490
1491 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1492 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1493 {
1494 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1495 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1496 }
1497 else
1498 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1499
1500 Log2(("exitCode = %x\n", exitCode));
1501
1502 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1503 pCtx->dr[6] = pVMCB->guest.u64DR6;
1504 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1505 pCtx->dr[7] = pVMCB->guest.u64DR7;
1506
1507 /* Check if an injected event was interrupted prematurely. */
1508 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1509 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1510 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1511 {
1512 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1513
1514#ifdef LOG_ENABLED
1515 SVM_EVENT Event;
1516 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1517
1518 if ( exitCode == SVM_EXIT_EXCEPTION_E
1519 && Event.n.u8Vector == 0xE)
1520 {
1521 Log(("Double fault!\n"));
1522 }
1523#endif
1524
1525 pVCpu->hwaccm.s.Event.fPending = true;
1526 /* Error code present? (redundant) */
1527 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1528 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1529 else
1530 pVCpu->hwaccm.s.Event.errCode = 0;
1531 }
1532#ifdef VBOX_WITH_STATISTICS
1533 if (exitCode == SVM_EXIT_NPF)
1534 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1535 else
1536 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1537#endif
1538
1539 /* Sync back the TPR if it was changed. */
1540 if (fSyncTPR)
1541 {
1542 if (pVM->hwaccm.s.fTPRPatchingActive)
1543 {
1544 if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1545 {
1546 /* Our patch code uses LSTAR for TPR caching. */
1547 rc = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1548 AssertRC(rc);
1549 }
1550 }
1551 else
1552 {
1553 if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1554 {
1555 rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1556 AssertRC(rc);
1557 }
1558 }
1559 }
1560
1561 /* Deal with the reason of the VM-exit. */
1562 switch (exitCode)
1563 {
1564 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1565 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1566 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1567 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1568 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1569 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1570 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1571 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1572 {
1573 /* Pending trap. */
1574 SVM_EVENT Event;
1575 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1576
1577 Log2(("Hardware/software interrupt %d\n", vector));
1578 switch (vector)
1579 {
1580 case X86_XCPT_DB:
1581 {
1582 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1583
1584 /* Note that we don't support guest and host-initiated debugging at the same time. */
1585 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1586
1587 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1588 if (rc == VINF_EM_RAW_GUEST_TRAP)
1589 {
1590 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1591
1592 /* Reinject the exception. */
1593 Event.au64[0] = 0;
1594 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1595 Event.n.u1Valid = 1;
1596 Event.n.u8Vector = X86_XCPT_DB;
1597
1598 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1599
1600 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1601 goto ResumeExecution;
1602 }
1603 /* Return to ring 3 to deal with the debug exit code. */
1604 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
1605 break;
1606 }
1607
1608 case X86_XCPT_NM:
1609 {
1610 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1611
1612 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1613 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1614 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1615 if (rc == VINF_SUCCESS)
1616 {
1617 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1618 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1619
1620 /* Continue execution. */
1621 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1622 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1623
1624 goto ResumeExecution;
1625 }
1626
1627 Log(("Forward #NM fault to the guest\n"));
1628 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1629
1630 Event.au64[0] = 0;
1631 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1632 Event.n.u1Valid = 1;
1633 Event.n.u8Vector = X86_XCPT_NM;
1634
1635 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1636 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1637 goto ResumeExecution;
1638 }
1639
1640 case X86_XCPT_PF: /* Page fault */
1641 {
1642 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1643 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1644
1645#ifdef DEBUG
1646 if (pVM->hwaccm.s.fNestedPaging)
1647 { /* A genuine pagefault.
1648 * Forward the trap to the guest by injecting the exception and resuming execution.
1649 */
1650 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1651 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1652
1653 /* Now we must update CR2. */
1654 pCtx->cr2 = uFaultAddress;
1655
1656 Event.au64[0] = 0;
1657 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1658 Event.n.u1Valid = 1;
1659 Event.n.u8Vector = X86_XCPT_PF;
1660 Event.n.u1ErrorCodeValid = 1;
1661 Event.n.u32ErrorCode = errCode;
1662
1663 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1664
1665 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1666 goto ResumeExecution;
1667 }
1668#endif
1669 Assert(!pVM->hwaccm.s.fNestedPaging);
1670
1671#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1672 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1673 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1674 && (uFaultAddress & 0xfff) == 0x080
1675 && !(errCode & X86_TRAP_PF_P) /* not present */
1676 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1677 && !CPUMIsGuestInLongModeEx(pCtx)
1678 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1679 {
1680 RTGCPHYS GCPhysApicBase, GCPhys;
1681 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1682 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1683
1684 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1685 if ( rc == VINF_SUCCESS
1686 && GCPhys == GCPhysApicBase)
1687 {
1688 /* Only attempt to patch the instruction once. */
1689 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1690 if (!pPatch)
1691 {
1692 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1693 break;
1694 }
1695 }
1696 }
1697#endif
1698
1699 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1700 /* Exit qualification contains the linear address of the page fault. */
1701 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1702 TRPMSetErrorCode(pVCpu, errCode);
1703 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1704
1705 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1706 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1707 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1708 if (rc == VINF_SUCCESS)
1709 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1710 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1711 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1712
1713 TRPMResetTrap(pVCpu);
1714 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1715
1716 /* Check if a sync operation is pending. */
1717 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1718 {
1719 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1720 AssertRC(rc);
1721 if (rc != VINF_SUCCESS)
1722 {
1723 Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", rc));
1724 break;
1725 }
1726 }
1727
1728 goto ResumeExecution;
1729 }
1730 else
1731 if (rc == VINF_EM_RAW_GUEST_TRAP)
1732 { /* A genuine pagefault.
1733 * Forward the trap to the guest by injecting the exception and resuming execution.
1734 */
1735 Log2(("Forward page fault to the guest\n"));
1736 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1737 /* The error code might have been changed. */
1738 errCode = TRPMGetErrorCode(pVCpu);
1739
1740 TRPMResetTrap(pVCpu);
1741
1742 /* Now we must update CR2. */
1743 pCtx->cr2 = uFaultAddress;
1744
1745 Event.au64[0] = 0;
1746 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1747 Event.n.u1Valid = 1;
1748 Event.n.u8Vector = X86_XCPT_PF;
1749 Event.n.u1ErrorCodeValid = 1;
1750 Event.n.u32ErrorCode = errCode;
1751
1752 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1753
1754 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1755 goto ResumeExecution;
1756 }
1757#ifdef VBOX_STRICT
1758 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1759 LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1760#endif
1761 /* Need to go back to the recompiler to emulate the instruction. */
1762 TRPMResetTrap(pVCpu);
1763 break;
1764 }
1765
1766 case X86_XCPT_MF: /* Floating point exception. */
1767 {
1768 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1769 if (!(pCtx->cr0 & X86_CR0_NE))
1770 {
1771 /* old style FPU error reporting needs some extra work. */
1772 /** @todo don't fall back to the recompiler, but do it manually. */
1773 rc = VINF_EM_RAW_EMULATE_INSTR;
1774 break;
1775 }
1776 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1777
1778 Event.au64[0] = 0;
1779 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1780 Event.n.u1Valid = 1;
1781 Event.n.u8Vector = X86_XCPT_MF;
1782
1783 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1784
1785 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1786 goto ResumeExecution;
1787 }
1788
1789#ifdef VBOX_STRICT
1790 case X86_XCPT_GP: /* General protection failure exception.*/
1791 case X86_XCPT_UD: /* Unknown opcode exception. */
1792 case X86_XCPT_DE: /* Divide error. */
1793 case X86_XCPT_SS: /* Stack segment exception. */
1794 case X86_XCPT_NP: /* Segment not present exception. */
1795 {
1796 Event.au64[0] = 0;
1797 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1798 Event.n.u1Valid = 1;
1799 Event.n.u8Vector = vector;
1800
1801 switch(vector)
1802 {
1803 case X86_XCPT_GP:
1804 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1805 Event.n.u1ErrorCodeValid = 1;
1806 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1807 break;
1808 case X86_XCPT_DE:
1809 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1810 break;
1811 case X86_XCPT_UD:
1812 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1813 break;
1814 case X86_XCPT_SS:
1815 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1816 Event.n.u1ErrorCodeValid = 1;
1817 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1818 break;
1819 case X86_XCPT_NP:
1820 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1821 Event.n.u1ErrorCodeValid = 1;
1822 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1823 break;
1824 }
1825 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1826 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1827
1828 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1829 goto ResumeExecution;
1830 }
1831#endif
1832 default:
1833 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1834 rc = VERR_EM_INTERNAL_ERROR;
1835 break;
1836
1837 } /* switch (vector) */
1838 break;
1839 }
1840
1841 case SVM_EXIT_NPF:
1842 {
1843 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1844 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1845 RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1846 PGMMODE enmShwPagingMode;
1847
1848 Assert(pVM->hwaccm.s.fNestedPaging);
1849 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1850
1851#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1852 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1853 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1854 && (uFaultAddress & 0xfff) == 0x080
1855 && !(errCode & X86_TRAP_PF_P) /* not present */
1856 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1857 && !CPUMIsGuestInLongModeEx(pCtx)
1858 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1859 {
1860 RTGCPHYS GCPhysApicBase;
1861 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1862 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1863
1864 if (uFaultAddress == GCPhysApicBase + 0x80)
1865 {
1866 /* Only attempt to patch the instruction once. */
1867 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1868 if (!pPatch)
1869 {
1870 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1871 break;
1872 }
1873 }
1874 }
1875#endif
1876
1877 /* Exit qualification contains the linear address of the page fault. */
1878 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1879 TRPMSetErrorCode(pVCpu, errCode);
1880 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1881
1882 /* Handle the pagefault trap for the nested shadow table. */
1883#if HC_ARCH_BITS == 32
1884 if (CPUMIsGuestInLongModeEx(pCtx))
1885 enmShwPagingMode = PGMMODE_AMD64_NX;
1886 else
1887#endif
1888 enmShwPagingMode = PGMGetHostMode(pVM);
1889
1890 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1891 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1892 if (rc == VINF_SUCCESS)
1893 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1894 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1895 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1896
1897 TRPMResetTrap(pVCpu);
1898
1899 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1900
1901 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1902 goto ResumeExecution;
1903 }
1904
1905#ifdef VBOX_STRICT
1906 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1907 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1908#endif
1909 /* Need to go back to the recompiler to emulate the instruction. */
1910 TRPMResetTrap(pVCpu);
1911 break;
1912 }
1913
1914 case SVM_EXIT_VINTR:
1915 /* A virtual interrupt is about to be delivered, which means IF=1. */
1916 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1917 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1918 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1919 goto ResumeExecution;
1920
1921 case SVM_EXIT_FERR_FREEZE:
1922 case SVM_EXIT_INTR:
1923 case SVM_EXIT_NMI:
1924 case SVM_EXIT_SMI:
1925 case SVM_EXIT_INIT:
1926 /* External interrupt; leave to allow it to be dispatched again. */
1927 rc = VINF_EM_RAW_INTERRUPT;
1928 break;
1929
1930 case SVM_EXIT_WBINVD:
1931 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1932 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1933 /* Skip instruction and continue directly. */
1934 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1935 /* Continue execution.*/
1936 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1937 goto ResumeExecution;
1938
1939 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1940 {
1941 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1942 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1943 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1944 if (rc == VINF_SUCCESS)
1945 {
1946 /* Update EIP and continue execution. */
1947 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1948 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1949 goto ResumeExecution;
1950 }
1951 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1952 rc = VINF_EM_RAW_EMULATE_INSTR;
1953 break;
1954 }
1955
1956 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1957 {
1958 Log2(("SVM: Rdtsc\n"));
1959 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1960 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1961 if (rc == VINF_SUCCESS)
1962 {
1963 /* Update EIP and continue execution. */
1964 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1965 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1966 goto ResumeExecution;
1967 }
1968 rc = VINF_EM_RAW_EMULATE_INSTR;
1969 break;
1970 }
1971
1972 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1973 {
1974 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1975 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1976 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1977 if (rc == VINF_SUCCESS)
1978 {
1979 /* Update EIP and continue execution. */
1980 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1981 goto ResumeExecution;
1982 }
1983 rc = VINF_EM_RAW_EMULATE_INSTR;
1984 break;
1985 }
1986
1987 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1988 {
1989 Log2(("SVM: Rdtscp\n"));
1990 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1991 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1992 if (rc == VINF_SUCCESS)
1993 {
1994 /* Update EIP and continue execution. */
1995 pCtx->rip += 3; /* Note! hardcoded opcode size! */
1996 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1997 goto ResumeExecution;
1998 }
1999 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
2000 rc = VINF_EM_RAW_EMULATE_INSTR;
2001 break;
2002 }
2003
2004 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
2005 {
2006 Log2(("SVM: invlpg\n"));
2007 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2008
2009 Assert(!pVM->hwaccm.s.fNestedPaging);
2010
2011 /* Truly a pita. Why can't SVM give the same information as VT-x? */
2012 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
2013 if (rc == VINF_SUCCESS)
2014 {
2015 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
2016 goto ResumeExecution; /* eip already updated */
2017 }
2018 break;
2019 }
2020
2021 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2022 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2023 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2024 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2025 {
2026 uint32_t cbSize;
2027
2028 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2029 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2030 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2031
2032 switch (exitCode - SVM_EXIT_WRITE_CR0)
2033 {
2034 case 0:
2035 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2036 break;
2037 case 2:
2038 break;
2039 case 3:
2040 Assert(!pVM->hwaccm.s.fNestedPaging);
2041 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2042 break;
2043 case 4:
2044 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2045 break;
2046 case 8:
2047 break;
2048 default:
2049 AssertFailed();
2050 }
2051 /* Check if a sync operation is pending. */
2052 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2053 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2054 {
2055 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2056 AssertRC(rc);
2057
2058 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
2059
2060 /* Must be set by PGMSyncCR3 */
2061 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || PGMGetGuestMode(pVCpu) <= PGMMODE_PROTECTED || pVCpu->hwaccm.s.fForceTLBFlush,
2062 ("rc=%Rrc mode=%d fForceTLBFlush=%RTbool\n", rc, PGMGetGuestMode(pVCpu), pVCpu->hwaccm.s.fForceTLBFlush));
2063 }
2064 if (rc == VINF_SUCCESS)
2065 {
2066 /* EIP has been updated already. */
2067
2068 /* Only resume if successful. */
2069 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2070 goto ResumeExecution;
2071 }
2072 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2073 break;
2074 }
2075
2076 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2077 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2078 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2079 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2080 {
2081 uint32_t cbSize;
2082
2083 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2084 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2085 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2086 if (rc == VINF_SUCCESS)
2087 {
2088 /* EIP has been updated already. */
2089
2090 /* Only resume if successful. */
2091 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2092 goto ResumeExecution;
2093 }
2094 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2095 break;
2096 }
2097
2098 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2099 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2100 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2101 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2102 {
2103 uint32_t cbSize;
2104
2105 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2106 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2107
2108 if ( !DBGFIsStepping(pVCpu)
2109 && !CPUMIsHyperDebugStateActive(pVCpu))
2110 {
2111 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2112
2113 /* Disable drx move intercepts. */
2114 pVMCB->ctrl.u16InterceptRdDRx = 0;
2115 pVMCB->ctrl.u16InterceptWrDRx = 0;
2116
2117 /* Save the host and load the guest debug state. */
2118 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2119 AssertRC(rc);
2120
2121 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2122 goto ResumeExecution;
2123 }
2124
2125 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2126 if (rc == VINF_SUCCESS)
2127 {
2128 /* EIP has been updated already. */
2129 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2130
2131 /* Only resume if successful. */
2132 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2133 goto ResumeExecution;
2134 }
2135 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2136 break;
2137 }
2138
2139 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2140 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2141 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2142 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2143 {
2144 uint32_t cbSize;
2145
2146 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2147 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2148
2149 if (!DBGFIsStepping(pVCpu))
2150 {
2151 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2152
2153 /* Disable drx move intercepts. */
2154 pVMCB->ctrl.u16InterceptRdDRx = 0;
2155 pVMCB->ctrl.u16InterceptWrDRx = 0;
2156
2157 /* Save the host and load the guest debug state. */
2158 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2159 AssertRC(rc);
2160
2161 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2162 goto ResumeExecution;
2163 }
2164
2165 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2166 if (rc == VINF_SUCCESS)
2167 {
2168 /* EIP has been updated already. */
2169
2170 /* Only resume if successful. */
2171 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2172 goto ResumeExecution;
2173 }
2174 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2175 break;
2176 }
2177
2178 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2179 case SVM_EXIT_IOIO: /* I/O instruction. */
2180 {
2181 SVM_IOIO_EXIT IoExitInfo;
2182 uint32_t uIOSize, uAndVal;
2183
2184 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2185
2186 /** @todo could use a lookup table here */
2187 if (IoExitInfo.n.u1OP8)
2188 {
2189 uIOSize = 1;
2190 uAndVal = 0xff;
2191 }
2192 else
2193 if (IoExitInfo.n.u1OP16)
2194 {
2195 uIOSize = 2;
2196 uAndVal = 0xffff;
2197 }
2198 else
2199 if (IoExitInfo.n.u1OP32)
2200 {
2201 uIOSize = 4;
2202 uAndVal = 0xffffffff;
2203 }
2204 else
2205 {
2206 AssertFailed(); /* should be fatal. */
2207 rc = VINF_EM_RAW_EMULATE_INSTR;
2208 break;
2209 }
2210
2211 if (IoExitInfo.n.u1STR)
2212 {
2213 /* ins/outs */
2214 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2215
2216 /* Disassemble manually to deal with segment prefixes. */
2217 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2218 if (rc == VINF_SUCCESS)
2219 {
2220 if (IoExitInfo.n.u1Type == 0)
2221 {
2222 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2223 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2224 rc = VBOXSTRICTRC_TODO(IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2225 }
2226 else
2227 {
2228 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2229 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2230 rc = VBOXSTRICTRC_TODO(IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2231 }
2232 }
2233 else
2234 rc = VINF_EM_RAW_EMULATE_INSTR;
2235 }
2236 else
2237 {
2238 /* normal in/out */
2239 Assert(!IoExitInfo.n.u1REP);
2240
2241 if (IoExitInfo.n.u1Type == 0)
2242 {
2243 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2244 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2245 rc = VBOXSTRICTRC_TODO(IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2246 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2247 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2248 }
2249 else
2250 {
2251 uint32_t u32Val = 0;
2252
2253 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2254 rc = VBOXSTRICTRC_TODO(IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize));
2255 if (IOM_SUCCESS(rc))
2256 {
2257 /* Write back to the EAX register. */
2258 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2259 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2260 }
2261 else
2262 if (rc == VINF_IOM_HC_IOPORT_READ)
2263 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2264 }
2265 }
2266 /*
2267 * Handled the I/O return codes.
2268 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2269 */
2270 if (IOM_SUCCESS(rc))
2271 {
2272 /* Update EIP and continue execution. */
2273 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2274 if (RT_LIKELY(rc == VINF_SUCCESS))
2275 {
2276 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2277 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2278 {
2279 /* IO operation lookup arrays. */
2280 static uint32_t const aIOSize[4] = {1, 2, 0, 4};
2281
2282 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2283 for (unsigned i=0;i<4;i++)
2284 {
2285 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2286
2287 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2288 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2289 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2290 {
2291 SVM_EVENT Event;
2292
2293 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2294
2295 /* Clear all breakpoint status flags and set the one we just hit. */
2296 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2297 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2298
2299 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2300 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2301 * the contents have been read.
2302 */
2303 pVMCB->guest.u64DR6 = pCtx->dr[6];
2304
2305 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2306 pCtx->dr[7] &= ~X86_DR7_GD;
2307
2308 /* Paranoia. */
2309 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2310 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2311 pCtx->dr[7] |= 0x400; /* must be one */
2312
2313 pVMCB->guest.u64DR7 = pCtx->dr[7];
2314
2315 /* Inject the exception. */
2316 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2317
2318 Event.au64[0] = 0;
2319 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2320 Event.n.u1Valid = 1;
2321 Event.n.u8Vector = X86_XCPT_DB;
2322
2323 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2324
2325 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2326 goto ResumeExecution;
2327 }
2328 }
2329 }
2330
2331 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2332 goto ResumeExecution;
2333 }
2334 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2335 break;
2336 }
2337
2338#ifdef VBOX_STRICT
2339 if (rc == VINF_IOM_HC_IOPORT_READ)
2340 Assert(IoExitInfo.n.u1Type != 0);
2341 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2342 Assert(IoExitInfo.n.u1Type == 0);
2343 else
2344 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2345#endif
2346 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2347 break;
2348 }
2349
2350 case SVM_EXIT_HLT:
2351 /** Check if external interrupts are pending; if so, don't switch back. */
2352 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2353 pCtx->rip++; /* skip hlt */
2354 if ( pCtx->eflags.Bits.u1IF
2355 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2356 goto ResumeExecution;
2357
2358 rc = VINF_EM_HALT;
2359 break;
2360
2361 case SVM_EXIT_MWAIT_UNCOND:
2362 Log2(("SVM: mwait\n"));
2363 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2364 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2365 if ( rc == VINF_EM_HALT
2366 || rc == VINF_SUCCESS)
2367 {
2368 /* Update EIP and continue execution. */
2369 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2370
2371 /** Check if external interrupts are pending; if so, don't switch back. */
2372 if ( rc == VINF_SUCCESS
2373 || ( rc == VINF_EM_HALT
2374 && pCtx->eflags.Bits.u1IF
2375 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2376 )
2377 goto ResumeExecution;
2378 }
2379 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2380 break;
2381
2382 case SVM_EXIT_VMMCALL:
2383 rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2384 if (rc == VINF_SUCCESS)
2385 {
2386 goto ResumeExecution; /* rip already updated. */
2387 }
2388 /* no break */
2389
2390 case SVM_EXIT_RSM:
2391 case SVM_EXIT_INVLPGA:
2392 case SVM_EXIT_VMRUN:
2393 case SVM_EXIT_VMLOAD:
2394 case SVM_EXIT_VMSAVE:
2395 case SVM_EXIT_STGI:
2396 case SVM_EXIT_CLGI:
2397 case SVM_EXIT_SKINIT:
2398 {
2399 /* Unsupported instructions. */
2400 SVM_EVENT Event;
2401
2402 Event.au64[0] = 0;
2403 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2404 Event.n.u1Valid = 1;
2405 Event.n.u8Vector = X86_XCPT_UD;
2406
2407 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2408 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2409
2410 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2411 goto ResumeExecution;
2412 }
2413
2414 /* Emulate in ring 3. */
2415 case SVM_EXIT_MSR:
2416 {
2417 uint32_t cbSize;
2418
2419 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2420 if ( pVM->hwaccm.s.fTPRPatchingActive
2421 && pCtx->ecx == MSR_K8_LSTAR
2422 && pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2423 {
2424 if ((pCtx->eax & 0xff) != u8LastTPR)
2425 {
2426 Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2427
2428 /* Our patch code uses LSTAR for TPR caching. */
2429 rc = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2430 AssertRC(rc);
2431 }
2432
2433 /* Skip the instruction and continue. */
2434 pCtx->rip += 2; /* wrmsr = [0F 30] */
2435
2436 /* Only resume if successful. */
2437 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2438 goto ResumeExecution;
2439 }
2440
2441 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2442 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2443 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2444 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2445 if (rc == VINF_SUCCESS)
2446 {
2447 /* EIP has been updated already. */
2448
2449 /* Only resume if successful. */
2450 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2451 goto ResumeExecution;
2452 }
2453 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2454 break;
2455 }
2456
2457 case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler*/
2458 Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVMCB->ctrl.u64ExitInfo2));
2459 if ( !(pVMCB->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET | SVM_EXIT2_TASK_SWITCH_JMP))
2460 && pVCpu->hwaccm.s.Event.fPending)
2461 {
2462 SVM_EVENT Event;
2463
2464 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
2465
2466 /* Caused by an injected interrupt. */
2467 pVCpu->hwaccm.s.Event.fPending = false;
2468
2469 switch (Event.n.u3Type)
2470 {
2471 case SVM_EVENT_EXTERNAL_IRQ:
2472 case SVM_EVENT_NMI:
2473 Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2474 Assert(!Event.n.u1ErrorCodeValid);
2475 rc = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2476 AssertRC(rc);
2477 break;
2478
2479 default:
2480 /* Exceptions and software interrupts can just be restarted. */
2481 break;
2482 }
2483 }
2484 rc = VERR_EM_INTERPRETER;
2485 break;
2486
2487 case SVM_EXIT_MONITOR:
2488 case SVM_EXIT_PAUSE:
2489 case SVM_EXIT_MWAIT_ARMED:
2490 rc = VERR_EM_INTERPRETER;
2491 break;
2492
2493 case SVM_EXIT_SHUTDOWN:
2494 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2495 break;
2496
2497 case SVM_EXIT_IDTR_READ:
2498 case SVM_EXIT_GDTR_READ:
2499 case SVM_EXIT_LDTR_READ:
2500 case SVM_EXIT_TR_READ:
2501 case SVM_EXIT_IDTR_WRITE:
2502 case SVM_EXIT_GDTR_WRITE:
2503 case SVM_EXIT_LDTR_WRITE:
2504 case SVM_EXIT_TR_WRITE:
2505 case SVM_EXIT_CR0_SEL_WRITE:
2506 default:
2507 /* Unexpected exit codes. */
2508 rc = VERR_EM_INTERNAL_ERROR;
2509 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2510 break;
2511 }
2512
2513end:
2514
2515 /* Signal changes for the recompiler. */
2516 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2517
2518 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2519 if (exitCode == SVM_EXIT_INTR)
2520 {
2521 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2522 /* On the next entry we'll only sync the host context. */
2523 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2524 }
2525 else
2526 {
2527 /* On the next entry we'll sync everything. */
2528 /** @todo we can do better than this */
2529 /* Not in the VINF_PGM_CHANGE_MODE though! */
2530 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2531 }
2532
2533 /* translate into a less severe return code */
2534 if (rc == VERR_EM_INTERPRETER)
2535 rc = VINF_EM_RAW_EMULATE_INSTR;
2536
2537 /* Just set the correct state here instead of trying to catch every goto above. */
2538 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2539
2540#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2541 /* Restore interrupts if we exitted after disabling them. */
2542 if (uOldEFlags != ~(RTCCUINTREG)0)
2543 ASMSetFlags(uOldEFlags);
2544#endif
2545
2546 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2547 return rc;
2548}
2549
2550/**
2551 * Emulate simple mov tpr instruction
2552 *
2553 * @returns VBox status code.
2554 * @param pVM The VM to operate on.
2555 * @param pVCpu The VM CPU to operate on.
2556 * @param pCtx CPU context
2557 */
2558static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2559{
2560 int rc;
2561
2562 LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2563
2564 while (true)
2565 {
2566 bool fPending;
2567 uint8_t u8Tpr;
2568
2569 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2570 if (!pPatch)
2571 break;
2572
2573 switch(pPatch->enmType)
2574 {
2575 case HWACCMTPRINSTR_READ:
2576 /* TPR caching in CR8 */
2577 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2578 AssertRC(rc);
2579
2580 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2581 AssertRC(rc);
2582
2583 LogFlow(("Emulated read successfully\n"));
2584 pCtx->rip += pPatch->cbOp;
2585 break;
2586
2587 case HWACCMTPRINSTR_WRITE_REG:
2588 case HWACCMTPRINSTR_WRITE_IMM:
2589 /* Fetch the new TPR value */
2590 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2591 {
2592 uint32_t val;
2593
2594 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2595 AssertRC(rc);
2596 u8Tpr = val;
2597 }
2598 else
2599 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2600
2601 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2602 AssertRC(rc);
2603 LogFlow(("Emulated write successfully\n"));
2604 pCtx->rip += pPatch->cbOp;
2605 break;
2606 default:
2607 AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_INTERNAL_ERROR);
2608 }
2609 }
2610 return VINF_SUCCESS;
2611}
2612
2613
2614/**
2615 * Enters the AMD-V session
2616 *
2617 * @returns VBox status code.
2618 * @param pVM The VM to operate on.
2619 * @param pVCpu The VM CPU to operate on.
2620 * @param pCpu CPU info struct
2621 */
2622VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2623{
2624 Assert(pVM->hwaccm.s.svm.fSupported);
2625
2626 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2627 pVCpu->hwaccm.s.fResumeVM = false;
2628
2629 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2630 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2631
2632 return VINF_SUCCESS;
2633}
2634
2635
2636/**
2637 * Leaves the AMD-V session
2638 *
2639 * @returns VBox status code.
2640 * @param pVM The VM to operate on.
2641 * @param pVCpu The VM CPU to operate on.
2642 * @param pCtx CPU context
2643 */
2644VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2645{
2646 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2647
2648 Assert(pVM->hwaccm.s.svm.fSupported);
2649
2650#ifdef DEBUG
2651 if (CPUMIsHyperDebugStateActive(pVCpu))
2652 {
2653 CPUMR0LoadHostDebugState(pVM, pVCpu);
2654 }
2655 else
2656#endif
2657 /* Save the guest debug state if necessary. */
2658 if (CPUMIsGuestDebugStateActive(pVCpu))
2659 {
2660 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2661
2662 /* Intercept all DRx reads and writes again. Changed later on. */
2663 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2664 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2665
2666 /* Resync the debug registers the next time. */
2667 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2668 }
2669 else
2670 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2671
2672 return VINF_SUCCESS;
2673}
2674
2675
2676static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2677{
2678 OP_PARAMVAL param1;
2679 RTGCPTR addr;
2680
2681 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2682 if(RT_FAILURE(rc))
2683 return VERR_EM_INTERPRETER;
2684
2685 switch(param1.type)
2686 {
2687 case PARMTYPE_IMMEDIATE:
2688 case PARMTYPE_ADDRESS:
2689 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2690 return VERR_EM_INTERPRETER;
2691 addr = param1.val.val64;
2692 break;
2693
2694 default:
2695 return VERR_EM_INTERPRETER;
2696 }
2697
2698 /** @todo is addr always a flat linear address or ds based
2699 * (in absence of segment override prefixes)????
2700 */
2701 rc = PGMInvalidatePage(pVCpu, addr);
2702 if (RT_SUCCESS(rc))
2703 return VINF_SUCCESS;
2704
2705 AssertRC(rc);
2706 return rc;
2707}
2708
2709/**
2710 * Interprets INVLPG
2711 *
2712 * @returns VBox status code.
2713 * @retval VINF_* Scheduling instructions.
2714 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2715 * @retval VERR_* Fatal errors.
2716 *
2717 * @param pVM The VM handle.
2718 * @param pRegFrame The register frame.
2719 * @param ASID Tagged TLB id for the guest
2720 *
2721 * Updates the EIP if an instruction was executed successfully.
2722 */
2723static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2724{
2725 /*
2726 * Only allow 32 & 64 bits code.
2727 */
2728 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2729 if (enmMode != CPUMODE_16BIT)
2730 {
2731 RTGCPTR pbCode;
2732 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2733 if (RT_SUCCESS(rc))
2734 {
2735 uint32_t cbOp;
2736 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2737
2738 pDis->mode = enmMode;
2739 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2740 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2741 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2742 {
2743 Assert(cbOp == pDis->opsize);
2744 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2745 if (RT_SUCCESS(rc))
2746 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2747
2748 return rc;
2749 }
2750 }
2751 }
2752 return VERR_EM_INTERPRETER;
2753}
2754
2755
2756/**
2757 * Invalidates a guest page
2758 *
2759 * @returns VBox status code.
2760 * @param pVM The VM to operate on.
2761 * @param pVCpu The VM CPU to operate on.
2762 * @param GCVirt Page to invalidate
2763 */
2764VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2765{
2766 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2767
2768 /* Skip it if a TLB flush is already pending. */
2769 if (!fFlushPending)
2770 {
2771 SVM_VMCB *pVMCB;
2772
2773 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2774 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2775 Assert(pVM->hwaccm.s.svm.fSupported);
2776
2777 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2778 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2779
2780#if HC_ARCH_BITS == 32
2781 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2782 if (CPUMIsGuestInLongMode(pVCpu))
2783 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2784 else
2785#endif
2786 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2787 }
2788 return VINF_SUCCESS;
2789}
2790
2791
2792#if 0 /* obsolete, but left here for clarification. */
2793/**
2794 * Invalidates a guest page by physical address
2795 *
2796 * @returns VBox status code.
2797 * @param pVM The VM to operate on.
2798 * @param pVCpu The VM CPU to operate on.
2799 * @param GCPhys Page to invalidate
2800 */
2801VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2802{
2803 Assert(pVM->hwaccm.s.fNestedPaging);
2804 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2805 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2806 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2807 return VINF_SUCCESS;
2808}
2809#endif
2810
2811#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2812/**
2813 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2814 *
2815 * @returns VBox status code.
2816 * @param pVMCBHostPhys Physical address of host VMCB.
2817 * @param pVMCBPhys Physical address of the VMCB.
2818 * @param pCtx Guest context.
2819 * @param pVM The VM to operate on.
2820 * @param pVCpu The VMCPU to operate on.
2821 */
2822DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2823{
2824 uint32_t aParam[4];
2825
2826 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2827 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2828 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2829 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2830
2831 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2832}
2833
2834/**
2835 * Executes the specified handler in 64 mode
2836 *
2837 * @returns VBox status code.
2838 * @param pVM The VM to operate on.
2839 * @param pVCpu The VMCPU to operate on.
2840 * @param pCtx Guest context
2841 * @param pfnHandler RC handler
2842 * @param cbParam Number of parameters
2843 * @param paParam Array of 32 bits parameters
2844 */
2845VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2846{
2847 int rc;
2848 RTHCUINTREG uOldEFlags;
2849
2850 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
2851 AssertReturn(pVM->cCpus == 1, VERR_TOO_MANY_CPUS);
2852 Assert(pfnHandler);
2853
2854 /* Disable interrupts. */
2855 uOldEFlags = ASMIntDisableFlags();
2856
2857 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
2858 CPUMSetHyperEIP(pVCpu, pfnHandler);
2859 for (int i=(int)cbParam-1;i>=0;i--)
2860 CPUMPushHyper(pVCpu, paParam[i]);
2861
2862 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2863 /* Call switcher. */
2864 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2865 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2866
2867 ASMSetFlags(uOldEFlags);
2868 return rc;
2869}
2870
2871#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette