HWACCMR0.cpp@ 8873

Last change on this file since 8873 was 8873, checked in by vboxsync, 17 years ago
Fetch the SVM features too and write them to the release log
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File size: 37.2 KB

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1	/* $Id: HWACCMR0.cpp 8873 2008-05-16 08:55:47Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/param.h>
40	#include <iprt/assert.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43	#include <iprt/memobj.h>
44	#include <iprt/cpuset.h>
45	#include "HWVMXR0.h"
46	#include "HWSVMR0.h"
47
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static int hwaccmr0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
55
56	/*******************************************************************************
57	* Local Variables *
58	*******************************************************************************/
59	static struct
60	{
61	struct
62	{
63	RTR0MEMOBJ pMemObj;
64	bool fVMXConfigured;
65	bool fSVMConfigured;
66	} aCpuInfo[RTCPUSET_MAX_CPUS];
67
68	struct
69	{
70	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
71	bool fSupported;
72
73	/** Host CR4 value (set by ring-0 VMX init) */
74	uint64_t hostCR4;
75
76	/** VMX MSR values */
77	struct
78	{
79	uint64_t feature_ctrl;
80	uint64_t vmx_basic_info;
81	uint64_t vmx_pin_ctls;
82	uint64_t vmx_proc_ctls;
83	uint64_t vmx_exit;
84	uint64_t vmx_entry;
85	uint64_t vmx_misc;
86	uint64_t vmx_cr0_fixed0;
87	uint64_t vmx_cr0_fixed1;
88	uint64_t vmx_cr4_fixed0;
89	uint64_t vmx_cr4_fixed1;
90	uint64_t vmx_vmcs_enum;
91	} msr;
92	/* Last instruction error */
93	uint32_t ulLastInstrError;
94	} vmx;
95	struct
96	{
97	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
98	bool fSupported;
99
100	/** SVM revision. */
101	uint32_t u32Rev;
102
103	/** Maximum ASID allowed. */
104	uint32_t u32MaxASID;
105
106	/** SVM feature bits from cpuid 0x8000000a */
107	uint32_t u32Features;
108	} svm;
109	/** Saved error from detection */
110	int32_t lLastError;
111
112	struct
113	{
114	uint32_t u32AMDFeatureECX;
115	uint32_t u32AMDFeatureEDX;
116	} cpuid;
117
118	HWACCMSTATE enmHwAccmState;
119	} HWACCMR0Globals;
120
121
122
123	/**
124	* Does global Ring-0 HWACCM initialization.
125	*
126	* @returns VBox status code.
127	*/
128	HWACCMR0DECL(int) HWACCMR0Init()
129	{
130	int rc;
131
132	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
133	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
134
135	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL /* paranoia */
136
137	/*
138	* Check for VT-x and AMD-V capabilities
139	*/
140	if (ASMHasCpuId())
141	{
142	uint32_t u32FeaturesECX;
143	uint32_t u32Dummy;
144	uint32_t u32FeaturesEDX;
145	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
146
147	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
148	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
149	/* Query AMD features. */
150	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
151
152	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
153	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
154	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
155	)
156	{
157	/*
158	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
159	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
160	*/
161	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
162	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
163	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
164	)
165	{
166	int aRc[RTCPUSET_MAX_CPUS];
167	RTCPUID idCpu = 0;
168
169	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
170
171	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
172	memset(aRc, 0, sizeof(aRc));
173	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
174
175	/* Check the return code of all invocations. */
176	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
177	HWACCMR0Globals.lLastError = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
178
179	if (VBOX_SUCCESS(HWACCMR0Globals.lLastError))
180	{
181	/* Reread in case we've changed it. */
182	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
183
184	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
185	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
186	{
187	RTR0MEMOBJ pScatchMemObj;
188	void *pvScatchPage;
189	RTHCPHYS pScatchPagePhys;
190
191	HWACCMR0Globals.vmx.fSupported = true;
192	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
193	HWACCMR0Globals.vmx.msr.vmx_pin_ctls = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
194	HWACCMR0Globals.vmx.msr.vmx_proc_ctls = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
195	HWACCMR0Globals.vmx.msr.vmx_exit = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
196	HWACCMR0Globals.vmx.msr.vmx_entry = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
197	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
198	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
199	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
200	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
201	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
202	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
203	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
204
205	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
206	if (RT_FAILURE(rc))
207	return rc;
208
209	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
210	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
211	memset(pvScatchPage, 0, PAGE_SIZE);
212
213	/* Set revision dword at the beginning of the structure. */
214	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
215
216	/* Make sure we don't get rescheduled to another cpu during this probe. */
217	RTCCUINTREG fFlags = ASMIntDisableFlags();
218
219	/*
220	* Check CR4.VMXE
221	*/
222	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
223	{
224	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
225	* try to execute the VMX instructions...
226	*/
227	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
228	}
229
230	/* Enter VMX Root Mode */
231	rc = VMXEnable(pScatchPagePhys);
232	if (VBOX_FAILURE(rc))
233	{
234	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
235	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
236	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
237	*
238	* They should fix their code, but until they do we simply refuse to run.
239	*/
240	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
241	HWACCMR0Globals.vmx.fSupported = false;
242	}
243	else
244	VMXDisable();
245
246	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
247	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
248	ASMSetFlags(fFlags);
249
250	RTR0MemObjFree(pScatchMemObj, false);
251	if (VBOX_FAILURE(HWACCMR0Globals.lLastError))
252	return HWACCMR0Globals.lLastError ;
253	}
254	else
255	{
256	AssertFailed(); /* can't hit this case anymore */
257	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
258	}
259	}
260	#ifdef LOG_ENABLED
261	else
262	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
263	#endif
264	}
265	else
266	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
267	}
268	else
269	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
270	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
271	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
272	)
273	{
274	/*
275	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
276	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
277	*/
278	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
279	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
280	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
281	)
282	{
283	int aRc[RTCPUSET_MAX_CPUS];
284	RTCPUID idCpu = 0;
285
286	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
287	memset(aRc, 0, sizeof(aRc));
288	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
289	AssertRC(rc);
290
291	/* Check the return code of all invocations. */
292	if (VBOX_SUCCESS(rc))
293	rc = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
294
295	AssertMsg(VBOX_SUCCESS(rc), ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
296
297	if (VBOX_SUCCESS(rc))
298	{
299	/* Query AMD features. */
300	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.svm.u32MaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
301
302	HWACCMR0Globals.svm.fSupported = true;
303	}
304	else
305	HWACCMR0Globals.lLastError = rc;
306	}
307	else
308	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
309	}
310	else
311	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
312	}
313	else
314	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
315
316	#endif /* !VBOX_WITH_HYBIRD_32BIT_KERNEL */
317
318	return VINF_SUCCESS;
319	}
320
321
322	/**
323	* Checks the error code array filled in for each cpu in the system.
324	*
325	* @returns VBox status code.
326	* @param paRc Error code array
327	* @param cErrorCodes Array size
328	* @param pidCpu Value of the first cpu that set an error (out)
329	*/
330	static int hwaccmr0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
331	{
332	int rc = VINF_SUCCESS;
333
334	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
335
336	for (unsigned i=0;i<cErrorCodes;i++)
337	{
338	if (RTMpIsCpuOnline(i))
339	{
340	if (VBOX_FAILURE(paRc[i]))
341	{
342	rc = paRc[i];
343	*pidCpu = i;
344	break;
345	}
346	}
347	}
348	return rc;
349	}
350
351	/**
352	* Does global Ring-0 HWACCM termination.
353	*
354	* @returns VBox status code.
355	*/
356	HWACCMR0DECL(int) HWACCMR0Term()
357	{
358	int aRc[RTCPUSET_MAX_CPUS];
359
360	memset(aRc, 0, sizeof(aRc));
361	int rc = RTMpOnAll(HWACCMR0DisableCPU, aRc, NULL);
362	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
363
364	/* Free the per-cpu pages used for VT-x and AMD-V */
365	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
366	{
367	AssertMsg(VBOX_SUCCESS(aRc[i]), ("HWACCMR0DisableCPU failed for cpu %d with rc=%d\n", i, aRc[i]));
368	if (HWACCMR0Globals.aCpuInfo[i].pMemObj)
369	{
370	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
371	HWACCMR0Globals.aCpuInfo[i].pMemObj = NULL;
372	}
373	}
374	return rc;
375	}
376
377
378	/**
379	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
380	* is to be called on the target cpus.
381	*
382	* @param idCpu The identifier for the CPU the function is called on.
383	* @param pvUser1 The 1st user argument.
384	* @param pvUser2 The 2nd user argument.
385	*/
386	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
387	{
388	unsigned u32VendorEBX = (uintptr_t)pvUser1;
389	int paRc = (int )pvUser2;
390	uint64_t val;
391
392	#ifdef LOG_ENABLED
393	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
394	#endif
395	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
396
397	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
398	{
399	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
400
401	/*
402	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
403	* Once the lock bit is set, this MSR can no longer be modified.
404	*/
405	if (!(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)))
406	{
407	/* MSR is not yet locked; we can change it ourselves here */
408	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
409	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
410	}
411	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
412	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
413	paRc[idCpu] = VINF_SUCCESS;
414	else
415	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
416	}
417	else
418	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
419	{
420	/* Check if SVM is disabled */
421	val = ASMRdMsr(MSR_K8_VM_CR);
422	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
423	{
424	/* Turn on SVM in the EFER MSR. */
425	val = ASMRdMsr(MSR_K6_EFER);
426	if (!(val & MSR_K6_EFER_SVME))
427	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
428
429	/* Paranoia. */
430	val = ASMRdMsr(MSR_K6_EFER);
431	if (val & MSR_K6_EFER_SVME)
432	paRc[idCpu] = VINF_SUCCESS;
433	else
434	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
435	}
436	else
437	paRc[idCpu] = HWACCMR0Globals.lLastError = VERR_SVM_DISABLED;
438	}
439	else
440	AssertFailed(); /* can't happen */
441	return;
442	}
443
444
445	/**
446	* Sets up HWACCM on all cpus.
447	*
448	* @returns VBox status code.
449	* @param pVM The VM to operate on.
450	* @param enmNewHwAccmState New hwaccm state
451	*
452	*/
453	HWACCMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
454	{
455	Assert(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
456	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, enmNewHwAccmState, HWACCMSTATE_UNINITIALIZED))
457	{
458	int aRc[RTCPUSET_MAX_CPUS];
459	RTCPUID idCpu = 0;
460
461	/* Don't setup hwaccm as that might not work (vt-x & 64 bits raw mode) */
462	if (enmNewHwAccmState == HWACCMSTATE_DISABLED)
463	return VINF_SUCCESS;
464
465	memset(aRc, 0, sizeof(aRc));
466
467	/* Allocate one page per cpu for the global vt-x and amd-v pages */
468	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
469	{
470	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
471
472	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
473	if (RTMpIsCpuOnline(i))
474	{
475	int rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
476	AssertRC(rc);
477	if (RT_FAILURE(rc))
478	return rc;
479
480	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
481	Assert(pvR0);
482	memset(pvR0, 0, PAGE_SIZE);
483
484	#ifdef LOG_ENABLED
485	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
486	#endif
487	}
488	}
489	/* First time, so initialize each cpu/core */
490	int rc = RTMpOnAll(HWACCMR0EnableCPU, (void *)pVM, aRc);
491
492	/* Check the return code of all invocations. */
493	if (VBOX_SUCCESS(rc))
494	rc = hwaccmr0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
495
496	AssertMsg(VBOX_SUCCESS(rc), ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
497	return rc;
498	}
499
500	if (HWACCMR0Globals.enmHwAccmState == enmNewHwAccmState)
501	return VINF_SUCCESS;
502
503	/* Request to change the mode is not allowed */
504	return VERR_ACCESS_DENIED;
505	}
506
507	/**
508	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
509	* is to be called on the target cpus.
510	*
511	* @param idCpu The identifier for the CPU the function is called on.
512	* @param pvUser1 The 1st user argument.
513	* @param pvUser2 The 2nd user argument.
514	*/
515	static DECLCALLBACK(void) HWACCMR0EnableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
516	{
517	PVM pVM = (PVM)pvUser1;
518	int paRc = (int )pvUser2;
519	void *pvPageCpu;
520	RTHCPHYS pPageCpuPhys;
521
522	Assert(pVM);
523	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
524	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
525
526	/* Should never happen */
527	if (!HWACCMR0Globals.aCpuInfo[idCpu].pMemObj)
528	{
529	AssertFailed();
530	return;
531	}
532
533	pvPageCpu = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj);
534	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj, 0);
535
536	if (pVM->hwaccm.s.vmx.fSupported)
537	{
538	paRc[idCpu] = VMXR0EnableCpu(idCpu, pVM, pvPageCpu, pPageCpuPhys);
539	AssertRC(paRc[idCpu]);
540	if (VBOX_SUCCESS(paRc[idCpu]))
541	HWACCMR0Globals.aCpuInfo[idCpu].fVMXConfigured = true;
542	}
543	else
544	if (pVM->hwaccm.s.svm.fSupported)
545	{
546	paRc[idCpu] = SVMR0EnableCpu(idCpu, pVM, pvPageCpu, pPageCpuPhys);
547	AssertRC(paRc[idCpu]);
548	if (VBOX_SUCCESS(paRc[idCpu]))
549	HWACCMR0Globals.aCpuInfo[idCpu].fSVMConfigured = true;
550	}
551	return;
552	}
553
554	/**
555	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
556	* is to be called on the target cpus.
557	*
558	* @param idCpu The identifier for the CPU the function is called on.
559	* @param pvUser1 The 1st user argument.
560	* @param pvUser2 The 2nd user argument.
561	*/
562	static DECLCALLBACK(void) HWACCMR0DisableCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
563	{
564	void *pvPageCpu;
565	RTHCPHYS pPageCpuPhys;
566	int paRc = (int )pvUser1;
567
568	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
569	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
570
571	if (!HWACCMR0Globals.aCpuInfo[idCpu].pMemObj)
572	return;
573
574	pvPageCpu = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj);
575	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[idCpu].pMemObj, 0);
576
577	if (HWACCMR0Globals.aCpuInfo[idCpu].fVMXConfigured)
578	{
579	paRc[idCpu] = VMXR0DisableCpu(idCpu, pvPageCpu, pPageCpuPhys);
580	AssertRC(paRc[idCpu]);
581	HWACCMR0Globals.aCpuInfo[idCpu].fVMXConfigured = false;
582	}
583	else
584	if (HWACCMR0Globals.aCpuInfo[idCpu].fSVMConfigured)
585	{
586	paRc[idCpu] = SVMR0DisableCpu(idCpu, pvPageCpu, pPageCpuPhys);
587	AssertRC(paRc[idCpu]);
588	HWACCMR0Globals.aCpuInfo[idCpu].fSVMConfigured = false;
589	}
590	return;
591	}
592
593
594	/**
595	* Does Ring-0 per VM HWACCM initialization.
596	*
597	* This is mainly to check that the Host CPU mode is compatible
598	* with VMX.
599	*
600	* @returns VBox status code.
601	* @param pVM The VM to operate on.
602	*/
603	HWACCMR0DECL(int) HWACCMR0InitVM(PVM pVM)
604	{
605	int rc = VINF_SUCCESS;
606
607	AssertReturn(pVM, VERR_INVALID_PARAMETER);
608
609	#ifdef LOG_ENABLED
610	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
611	#endif
612
613	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
614	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
615
616	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
617	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
618	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
619	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
620	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
621	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
622	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
623	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
624	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
625	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
626	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
627	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
628	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
629	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
630	pVM->hwaccm.s.svm.u32MaxASID = HWACCMR0Globals.svm.u32MaxASID;
631	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
632	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
633	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
634	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
635
636	/* Init a VT-x or AMD-V VM. */
637	if (pVM->hwaccm.s.vmx.fSupported)
638	rc = VMXR0InitVM(pVM);
639	else
640	if (pVM->hwaccm.s.svm.fSupported)
641	rc = SVMR0InitVM(pVM);
642
643	return rc;
644	}
645
646
647	/**
648	* Does Ring-0 per VM HWACCM termination.
649	*
650	* @returns VBox status code.
651	* @param pVM The VM to operate on.
652	*/
653	HWACCMR0DECL(int) HWACCMR0TermVM(PVM pVM)
654	{
655	int rc = VINF_SUCCESS;
656
657	AssertReturn(pVM, VERR_INVALID_PARAMETER);
658
659	#ifdef LOG_ENABLED
660	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
661	#endif
662
663	/* Terminate a VT-x or AMD-V VM. */
664	if (pVM->hwaccm.s.vmx.fSupported)
665	rc = VMXR0TermVM(pVM);
666	else
667	if (pVM->hwaccm.s.svm.fSupported)
668	rc = SVMR0TermVM(pVM);
669
670	return rc;
671	}
672
673
674	/**
675	* Sets up a VT-x or AMD-V session
676	*
677	* @returns VBox status code.
678	* @param pVM The VM to operate on.
679	*/
680	HWACCMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
681	{
682	int rc = VINF_SUCCESS;
683
684	AssertReturn(pVM, VERR_INVALID_PARAMETER);
685
686	#ifdef LOG_ENABLED
687	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
688	#endif
689
690	/* Setup VT-x or AMD-V. */
691	if (pVM->hwaccm.s.vmx.fSupported)
692	rc = VMXR0SetupVM(pVM);
693	else
694	if (pVM->hwaccm.s.svm.fSupported)
695	rc = SVMR0SetupVM(pVM);
696
697	return rc;
698	}
699
700
701	/**
702	* Enters the VT-x or AMD-V session
703	*
704	* @returns VBox status code.
705	* @param pVM The VM to operate on.
706	*/
707	HWACCMR0DECL(int) HWACCMR0Enter(PVM pVM)
708	{
709	CPUMCTX *pCtx;
710	int rc;
711
712	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
713	if (VBOX_FAILURE(rc))
714	return rc;
715
716	/* Always load the guest's FPU/XMM state on-demand. */
717	CPUMDeactivateGuestFPUState(pVM);
718
719	/* Always reload the host context and the guest's CR0 register. (!!!!) */
720	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
721
722	if (pVM->hwaccm.s.vmx.fSupported)
723	{
724	rc = VMXR0Enter(pVM);
725	AssertRC(rc);
726	rc \|= VMXR0SaveHostState(pVM);
727	AssertRC(rc);
728	rc \|= VMXR0LoadGuestState(pVM, pCtx);
729	AssertRC(rc);
730	if (rc != VINF_SUCCESS)
731	return rc;
732	}
733	else
734	{
735	Assert(pVM->hwaccm.s.svm.fSupported);
736	rc = SVMR0Enter(pVM);
737	AssertRC(rc);
738	rc \|= SVMR0LoadGuestState(pVM, pCtx);
739	AssertRC(rc);
740	if (rc != VINF_SUCCESS)
741	return rc;
742
743	}
744	return VINF_SUCCESS;
745	}
746
747
748	/**
749	* Leaves the VT-x or AMD-V session
750	*
751	* @returns VBox status code.
752	* @param pVM The VM to operate on.
753	*/
754	HWACCMR0DECL(int) HWACCMR0Leave(PVM pVM)
755	{
756	CPUMCTX *pCtx;
757	int rc;
758
759	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
760	if (VBOX_FAILURE(rc))
761	return rc;
762
763	/** @note It's rather tricky with longjmps done by e.g. Log statements or the page fault handler. */
764	/* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
765	* or trash somebody else's FPU state.
766	*/
767
768	/* Restore host FPU and XMM state if necessary. */
769	if (CPUMIsGuestFPUStateActive(pVM))
770	{
771	Log2(("CPUMRestoreHostFPUState\n"));
772	/** @note CPUMRestoreHostFPUState keeps the current CR0 intact. */
773	CPUMRestoreHostFPUState(pVM);
774
775	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
776	}
777
778	if (pVM->hwaccm.s.vmx.fSupported)
779	{
780	return VMXR0Leave(pVM);
781	}
782	else
783	{
784	Assert(pVM->hwaccm.s.svm.fSupported);
785	return SVMR0Leave(pVM);
786	}
787	}
788
789	/**
790	* Runs guest code in a hardware accelerated VM.
791	*
792	* @returns VBox status code.
793	* @param pVM The VM to operate on.
794	*/
795	HWACCMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM)
796	{
797	CPUMCTX *pCtx;
798	int rc;
799
800	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
801	if (VBOX_FAILURE(rc))
802	return rc;
803
804	if (pVM->hwaccm.s.vmx.fSupported)
805	{
806	return VMXR0RunGuestCode(pVM, pCtx);
807	}
808	else
809	{
810	Assert(pVM->hwaccm.s.svm.fSupported);
811	return SVMR0RunGuestCode(pVM, pCtx);
812	}
813	}
814
815	/**
816	* Invalidates a guest page
817	*
818	* @returns VBox status code.
819	* @param pVM The VM to operate on.
820	* @param GCVirt Page to invalidate
821	*/
822	HWACCMR0DECL(int) HWACCMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
823	{
824	if (pVM->hwaccm.s.svm.fSupported)
825	return SVMR0InvalidatePage(pVM, GCVirt);
826
827	return VINF_SUCCESS;
828	}
829
830	/**
831	* Flushes the guest TLB
832	*
833	* @returns VBox status code.
834	* @param pVM The VM to operate on.
835	*/
836	HWACCMR0DECL(int) HWACCMR0FlushTLB(PVM pVM)
837	{
838	if (pVM->hwaccm.s.svm.fSupported)
839	return SVMR0FlushTLB(pVM);
840
841	return VINF_SUCCESS;
842	}
843
844
845	#ifdef VBOX_STRICT
846	#include <iprt/string.h>
847	/**
848	* Dumps a descriptor.
849	*
850	* @param Desc Descriptor to dump.
851	* @param Sel Selector number.
852	* @param pszMsg Message to prepend the log entry with.
853	*/
854	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg)
855	{
856	/*
857	* Make variable description string.
858	*/
859	static struct
860	{
861	unsigned cch;
862	const char *psz;
863	} const aTypes[32] =
864	{
865	#define STRENTRY(str) { sizeof(str) - 1, str }
866
867	/* system */
868	#if HC_ARCH_BITS == 64
869	STRENTRY("Reserved0 "), /* 0x00 */
870	STRENTRY("Reserved1 "), /* 0x01 */
871	STRENTRY("LDT "), /* 0x02 */
872	STRENTRY("Reserved3 "), /* 0x03 */
873	STRENTRY("Reserved4 "), /* 0x04 */
874	STRENTRY("Reserved5 "), /* 0x05 */
875	STRENTRY("Reserved6 "), /* 0x06 */
876	STRENTRY("Reserved7 "), /* 0x07 */
877	STRENTRY("Reserved8 "), /* 0x08 */
878	STRENTRY("TSS64Avail "), /* 0x09 */
879	STRENTRY("ReservedA "), /* 0x0a */
880	STRENTRY("TSS64Busy "), /* 0x0b */
881	STRENTRY("Call64 "), /* 0x0c */
882	STRENTRY("ReservedD "), /* 0x0d */
883	STRENTRY("Int64 "), /* 0x0e */
884	STRENTRY("Trap64 "), /* 0x0f */
885	#else
886	STRENTRY("Reserved0 "), /* 0x00 */
887	STRENTRY("TSS16Avail "), /* 0x01 */
888	STRENTRY("LDT "), /* 0x02 */
889	STRENTRY("TSS16Busy "), /* 0x03 */
890	STRENTRY("Call16 "), /* 0x04 */
891	STRENTRY("Task "), /* 0x05 */
892	STRENTRY("Int16 "), /* 0x06 */
893	STRENTRY("Trap16 "), /* 0x07 */
894	STRENTRY("Reserved8 "), /* 0x08 */
895	STRENTRY("TSS32Avail "), /* 0x09 */
896	STRENTRY("ReservedA "), /* 0x0a */
897	STRENTRY("TSS32Busy "), /* 0x0b */
898	STRENTRY("Call32 "), /* 0x0c */
899	STRENTRY("ReservedD "), /* 0x0d */
900	STRENTRY("Int32 "), /* 0x0e */
901	STRENTRY("Trap32 "), /* 0x0f */
902	#endif
903	/* non system */
904	STRENTRY("DataRO "), /* 0x10 */
905	STRENTRY("DataRO Accessed "), /* 0x11 */
906	STRENTRY("DataRW "), /* 0x12 */
907	STRENTRY("DataRW Accessed "), /* 0x13 */
908	STRENTRY("DataDownRO "), /* 0x14 */
909	STRENTRY("DataDownRO Accessed "), /* 0x15 */
910	STRENTRY("DataDownRW "), /* 0x16 */
911	STRENTRY("DataDownRW Accessed "), /* 0x17 */
912	STRENTRY("CodeEO "), /* 0x18 */
913	STRENTRY("CodeEO Accessed "), /* 0x19 */
914	STRENTRY("CodeER "), /* 0x1a */
915	STRENTRY("CodeER Accessed "), /* 0x1b */
916	STRENTRY("CodeConfEO "), /* 0x1c */
917	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
918	STRENTRY("CodeConfER "), /* 0x1e */
919	STRENTRY("CodeConfER Accessed ") /* 0x1f */
920	#undef SYSENTRY
921	};
922	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
923	char szMsg[128];
924	char *psz = &szMsg[0];
925	unsigned i = Desc->Gen.u1DescType << 4 \| Desc->Gen.u4Type;
926	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
927	psz += aTypes[i].cch;
928
929	if (Desc->Gen.u1Present)
930	ADD_STR(psz, "Present ");
931	else
932	ADD_STR(psz, "Not-Present ");
933	#if HC_ARCH_BITS == 64
934	if (Desc->Gen.u1Long)
935	ADD_STR(psz, "64-bit ");
936	else
937	ADD_STR(psz, "Comp ");
938	#else
939	if (Desc->Gen.u1Granularity)
940	ADD_STR(psz, "Page ");
941	if (Desc->Gen.u1DefBig)
942	ADD_STR(psz, "32-bit ");
943	else
944	ADD_STR(psz, "16-bit ");
945	#endif
946	#undef ADD_STR
947	*psz = '\0';
948
949	/*
950	* Limit and Base and format the output.
951	*/
952	uint32_t u32Limit = Desc->Gen.u4LimitHigh << 16 \| Desc->Gen.u16LimitLow;
953	if (Desc->Gen.u1Granularity)
954	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
955
956	#if HC_ARCH_BITS == 64
957	uint64_t u32Base = ((uintptr_t)Desc->Gen.u32BaseHigh3 << 32ULL) \| Desc->Gen.u8BaseHigh2 << 24ULL \| Desc->Gen.u8BaseHigh1 << 16ULL \| Desc->Gen.u16BaseLow;
958
959	Log(("%s %04x - %VX64 %VX64 - base=%VX64 limit=%08x dpl=%d %s\n", pszMsg,
960	Sel, Desc->au64[0], Desc->au64[1], u32Base, u32Limit, Desc->Gen.u2Dpl, szMsg));
961	#else
962	uint32_t u32Base = Desc->Gen.u8BaseHigh2 << 24 \| Desc->Gen.u8BaseHigh1 << 16 \| Desc->Gen.u16BaseLow;
963
964	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
965	Sel, Desc->au32[0], Desc->au32[1], u32Base, u32Limit, Desc->Gen.u2Dpl, szMsg));
966	#endif
967	}
968
969	/**
970	* Formats a full register dump.
971	*
972	* @param pCtx The context to format.
973	*/
974	HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx)
975	{
976	/*
977	* Format the flags.
978	*/
979	static struct
980	{
981	const char pszSet; const char pszClear; uint32_t fFlag;
982	} aFlags[] =
983	{
984	{ "vip",NULL, X86_EFL_VIP },
985	{ "vif",NULL, X86_EFL_VIF },
986	{ "ac", NULL, X86_EFL_AC },
987	{ "vm", NULL, X86_EFL_VM },
988	{ "rf", NULL, X86_EFL_RF },
989	{ "nt", NULL, X86_EFL_NT },
990	{ "ov", "nv", X86_EFL_OF },
991	{ "dn", "up", X86_EFL_DF },
992	{ "ei", "di", X86_EFL_IF },
993	{ "tf", NULL, X86_EFL_TF },
994	{ "nt", "pl", X86_EFL_SF },
995	{ "nz", "zr", X86_EFL_ZF },
996	{ "ac", "na", X86_EFL_AF },
997	{ "po", "pe", X86_EFL_PF },
998	{ "cy", "nc", X86_EFL_CF },
999	};
1000	char szEFlags[80];
1001	char *psz = szEFlags;
1002	uint32_t efl = pCtx->eflags.u32;
1003	for (unsigned i = 0; i < ELEMENTS(aFlags); i++)
1004	{
1005	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1006	if (pszAdd)
1007	{
1008	strcpy(psz, pszAdd);
1009	psz += strlen(pszAdd);
1010	*psz++ = ' ';
1011	}
1012	}
1013	psz[-1] = '\0';
1014
1015
1016	/*
1017	* Format the registers.
1018	*/
1019	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1020	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1021	"cs={%04x base=%08x limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1022	"ds={%04x base=%08x limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1023	"es={%04x base=%08x limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1024	"fs={%04x base=%08x limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1025	,
1026	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1027	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1028	(RTSEL)pCtx->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr0, pCtx->dr1,
1029	(RTSEL)pCtx->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr2, pCtx->dr3,
1030	(RTSEL)pCtx->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr4, pCtx->dr5,
1031	(RTSEL)pCtx->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr6, pCtx->dr7));
1032
1033	Log(("gs={%04x base=%08x limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1034	"ss={%04x base=%08x limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1035	"gdtr=%08x:%04x idtr=%08x:%04x eflags=%08x\n"
1036	"ldtr={%04x base=%08x limit=%08x flags=%08x}\n"
1037	"tr ={%04x base=%08x limit=%08x flags=%08x}\n"
1038	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1039	"FCW=%04x FSW=%04x FTW=%04x\n",
1040	(RTSEL)pCtx->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1041	(RTSEL)pCtx->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1042	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1043	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1044	(RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1045	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1046	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW));
1047
1048
1049	}
1050	#endif

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 8873

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