HMSVMR0.cpp@ 80274

Last change on this file since 80274 was 80274, checked in by vboxsync, 6 years ago
VMM: Refactoring VMMR0/* and VMMRZ/* to use VMCC & VMMCPUCC. bugref:9217
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1	/* $Id: HMSVMR0.cpp 80274 2019-08-14 14:34:38Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define VBOX_BUGREF_9217_PART_I
23	#define LOG_GROUP LOG_GROUP_HM
24	#define VMCPU_INCL_CPUM_GST_CTX
25	#include <iprt/asm-amd64-x86.h>
26	#include <iprt/thread.h>
27
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iem.h>
31	#include <VBox/vmm/iom.h>
32	#include <VBox/vmm/tm.h>
33	#include <VBox/vmm/em.h>
34	#include <VBox/vmm/gim.h>
35	#include <VBox/vmm/apic.h>
36	#include "HMInternal.h"
37	#include <VBox/vmm/vmcc.h>
38	#include <VBox/err.h>
39	#include "HMSVMR0.h"
40	#include "dtrace/VBoxVMM.h"
41
42	#ifdef DEBUG_ramshankar
43	# define HMSVM_SYNC_FULL_GUEST_STATE
44	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
45	# define HMSVM_ALWAYS_TRAP_PF
46	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
47	#endif
48
49
50	/*********************************************************************************************************************************
51	* Defined Constants And Macros *
52	*********************************************************************************************************************************/
53	#ifdef VBOX_WITH_STATISTICS
54	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
55	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
56	if ((u64ExitCode) == SVM_EXIT_NPF) \
57	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
58	else \
59	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
60	} while (0)
61
62	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
63	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
64	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
65	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitAll); \
66	if ((u64ExitCode) == SVM_EXIT_NPF) \
67	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
68	else \
69	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
70	} while (0)
71	# endif
72	#else
73	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
74	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
75	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
76	# endif
77	#endif /* !VBOX_WITH_STATISTICS */
78
79	/** If we decide to use a function table approach this can be useful to
80	* switch to a "static DECLCALLBACK(int)". */
81	#define HMSVM_EXIT_DECL static int
82
83	/**
84	* Subset of the guest-CPU state that is kept by SVM R0 code while executing the
85	* guest using hardware-assisted SVM.
86	*
87	* This excludes state like TSC AUX, GPRs (other than RSP, RAX) which are always
88	* are swapped and restored across the world-switch and also registers like
89	* EFER, PAT MSR etc. which cannot be modified by the guest without causing a
90	* \#VMEXIT.
91	*/
92	#define HMSVM_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
93	\| CPUMCTX_EXTRN_RFLAGS \
94	\| CPUMCTX_EXTRN_RAX \
95	\| CPUMCTX_EXTRN_RSP \
96	\| CPUMCTX_EXTRN_SREG_MASK \
97	\| CPUMCTX_EXTRN_CR0 \
98	\| CPUMCTX_EXTRN_CR2 \
99	\| CPUMCTX_EXTRN_CR3 \
100	\| CPUMCTX_EXTRN_TABLE_MASK \
101	\| CPUMCTX_EXTRN_DR6 \
102	\| CPUMCTX_EXTRN_DR7 \
103	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
104	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
105	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
106	\| CPUMCTX_EXTRN_HWVIRT \
107	\| CPUMCTX_EXTRN_HM_SVM_MASK)
108
109	/**
110	* Subset of the guest-CPU state that is shared between the guest and host.
111	*/
112	#define HMSVM_CPUMCTX_SHARED_STATE CPUMCTX_EXTRN_DR_MASK
113
114	/** Macro for importing guest state from the VMCB back into CPUMCTX. */
115	#define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) \
116	do { \
117	if ((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fWhat)) \
118	hmR0SvmImportGuestState((a_pVCpu), (a_fWhat)); \
119	} while (0)
120
121	/** Assert that the required state bits are fetched. */
122	#define HMSVM_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
123	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
124	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
125
126	/** Assert that preemption is disabled or covered by thread-context hooks. */
127	#define HMSVM_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
128	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
129
130	/** Assert that we haven't migrated CPUs when thread-context hooks are not
131	* used. */
132	#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
133	\|\| (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
134	("Illegal migration! Entered on CPU %u Current %u\n", \
135	(a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()));
136
137	/** Assert that we're not executing a nested-guest. */
138	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
139	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
140	#else
141	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
142	#endif
143
144	/** Assert that we're executing a nested-guest. */
145	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
146	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
147	#else
148	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
149	#endif
150
151	/** Macro for checking and returning from the using function for
152	* \#VMEXIT intercepts that maybe caused during delivering of another
153	* event in the guest. */
154	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
155	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
156	do \
157	{ \
158	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
159	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
160	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
161	else if ( rc == VINF_EM_RESET \
162	&& CPUMIsGuestSvmCtrlInterceptSet((a_pVCpu), &(a_pVCpu)->cpum.GstCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
163	{ \
164	HMSVM_CPUMCTX_IMPORT_STATE((a_pVCpu), HMSVM_CPUMCTX_EXTRN_ALL); \
165	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), SVM_EXIT_SHUTDOWN, 0, 0)); \
166	} \
167	else \
168	return rc; \
169	} while (0)
170	#else
171	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
172	do \
173	{ \
174	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
175	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
176	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
177	else \
178	return rc; \
179	} while (0)
180	#endif
181
182	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
183	* instruction that exited. */
184	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
185	do { \
186	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
187	(a_rc) = VINF_EM_DBG_STEPPED; \
188	} while (0)
189
190	/** Validate segment descriptor granularity bit. */
191	#ifdef VBOX_STRICT
192	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) \
193	AssertMsg( !(a_pCtx)->reg.Attr.n.u1Present \
194	\|\| ( (a_pCtx)->reg.Attr.n.u1Granularity \
195	? ((a_pCtx)->reg.u32Limit & 0xfff) == 0xfff \
196	: (a_pCtx)->reg.u32Limit <= UINT32_C(0xfffff)), \
197	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", (a_pCtx)->reg.u32Limit, \
198	(a_pCtx)->reg.Attr.u, (a_pCtx)->reg.u64Base))
199	#else
200	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) do { } while (0)
201	#endif
202
203	/**
204	* Exception bitmap mask for all contributory exceptions.
205	*
206	* Page fault is deliberately excluded here as it's conditional as to whether
207	* it's contributory or benign. Page faults are handled separately.
208	*/
209	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
210	\| RT_BIT(X86_XCPT_DE))
211
212	/**
213	* Mandatory/unconditional guest control intercepts.
214	*
215	* SMIs can and do happen in normal operation. We need not intercept them
216	* while executing the guest (or nested-guest).
217	*/
218	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
219	\| SVM_CTRL_INTERCEPT_NMI \
220	\| SVM_CTRL_INTERCEPT_INIT \
221	\| SVM_CTRL_INTERCEPT_RDPMC \
222	\| SVM_CTRL_INTERCEPT_CPUID \
223	\| SVM_CTRL_INTERCEPT_RSM \
224	\| SVM_CTRL_INTERCEPT_HLT \
225	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
226	\| SVM_CTRL_INTERCEPT_MSR_PROT \
227	\| SVM_CTRL_INTERCEPT_INVLPGA \
228	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
229	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
230	\| SVM_CTRL_INTERCEPT_VMRUN \
231	\| SVM_CTRL_INTERCEPT_SKINIT \
232	\| SVM_CTRL_INTERCEPT_WBINVD \
233	\| SVM_CTRL_INTERCEPT_MONITOR \
234	\| SVM_CTRL_INTERCEPT_MWAIT \
235	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
236	\| SVM_CTRL_INTERCEPT_XSETBV)
237
238	/** @name VMCB Clean Bits.
239	*
240	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
241	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
242	* memory.
243	*
244	* @{ */
245	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
246	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
247	/** I/O permission bitmap, MSR permission bitmap. */
248	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
249	/** ASID. */
250	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
251	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
252	V_INTR_VECTOR. */
253	#define HMSVM_VMCB_CLEAN_INT_CTRL RT_BIT(3)
254	/** Nested Paging: Nested CR3 (nCR3), PAT. */
255	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
256	/** Control registers (CR0, CR3, CR4, EFER). */
257	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
258	/** Debug registers (DR6, DR7). */
259	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
260	/** GDT, IDT limit and base. */
261	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
262	/** Segment register: CS, SS, DS, ES limit and base. */
263	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
264	/** CR2.*/
265	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
266	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
267	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
268	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
269	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
270	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
271	/** Mask of all valid VMCB Clean bits. */
272	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
273	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
274	\| HMSVM_VMCB_CLEAN_ASID \
275	\| HMSVM_VMCB_CLEAN_INT_CTRL \
276	\| HMSVM_VMCB_CLEAN_NP \
277	\| HMSVM_VMCB_CLEAN_CRX_EFER \
278	\| HMSVM_VMCB_CLEAN_DRX \
279	\| HMSVM_VMCB_CLEAN_DT \
280	\| HMSVM_VMCB_CLEAN_SEG \
281	\| HMSVM_VMCB_CLEAN_CR2 \
282	\| HMSVM_VMCB_CLEAN_LBR \
283	\| HMSVM_VMCB_CLEAN_AVIC)
284	/** @} */
285
286	/** @name SVM transient.
287	*
288	* A state structure for holding miscellaneous information across AMD-V
289	* VMRUN/\#VMEXIT operation, restored after the transition.
290	*
291	* @{ */
292	typedef struct SVMTRANSIENT
293	{
294	/** The host's rflags/eflags. */
295	RTCCUINTREG fEFlags;
296
297	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
298	uint64_t u64ExitCode;
299	/** The guest's TPR value used for TPR shadowing. */
300	uint8_t u8GuestTpr;
301	/** Alignment. */
302	uint8_t abAlignment0[7];
303
304	/** Pointer to the currently executing VMCB. */
305	PSVMVMCB pVmcb;
306	/** Whether we are currently executing a nested-guest. */
307	bool fIsNestedGuest;
308
309	/** Whether the guest debug state was active at the time of \#VMEXIT. */
310	bool fWasGuestDebugStateActive;
311	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
312	bool fWasHyperDebugStateActive;
313	/** Whether the TSC offset mode needs to be updated. */
314	bool fUpdateTscOffsetting;
315	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
316	bool fRestoreTscAuxMsr;
317	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
318	* contributary exception or a page-fault. */
319	bool fVectoringDoublePF;
320	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
321	* external interrupt or NMI. */
322	bool fVectoringPF;
323	} SVMTRANSIENT, *PSVMTRANSIENT;
324	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
325	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
326	/** @} */
327
328	/**
329	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
330	*/
331	typedef enum SVMMSREXITREAD
332	{
333	/** Reading this MSR causes a \#VMEXIT. */
334	SVMMSREXIT_INTERCEPT_READ = 0xb,
335	/** Reading this MSR does not cause a \#VMEXIT. */
336	SVMMSREXIT_PASSTHRU_READ
337	} SVMMSREXITREAD;
338
339	/**
340	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
341	*/
342	typedef enum SVMMSREXITWRITE
343	{
344	/** Writing to this MSR causes a \#VMEXIT. */
345	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
346	/** Writing to this MSR does not cause a \#VMEXIT. */
347	SVMMSREXIT_PASSTHRU_WRITE
348	} SVMMSREXITWRITE;
349
350	/**
351	* SVM \#VMEXIT handler.
352	*
353	* @returns VBox status code.
354	* @param pVCpu The cross context virtual CPU structure.
355	* @param pSvmTransient Pointer to the SVM-transient structure.
356	*/
357	typedef int FNSVMEXITHANDLER(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
358
359
360	/*********************************************************************************************************************************
361	* Internal Functions *
362	*********************************************************************************************************************************/
363	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu);
364	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState);
365
366
367	/** @name \#VMEXIT handlers.
368	* @{
369	*/
370	static FNSVMEXITHANDLER hmR0SvmExitIntr;
371	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
372	static FNSVMEXITHANDLER hmR0SvmExitInvd;
373	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
374	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
375	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
376	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
377	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
378	static FNSVMEXITHANDLER hmR0SvmExitHlt;
379	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
380	static FNSVMEXITHANDLER hmR0SvmExitMwait;
381	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
382	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
383	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
384	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
385	static FNSVMEXITHANDLER hmR0SvmExitMsr;
386	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
387	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
388	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
389	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
390	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
391	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
392	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
393	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
394	static FNSVMEXITHANDLER hmR0SvmExitPause;
395	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
396	static FNSVMEXITHANDLER hmR0SvmExitIret;
397	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
398	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
399	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
400	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
401	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
402	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
403	static FNSVMEXITHANDLER hmR0SvmExitXcptGP;
404	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
405	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
406	#endif
407	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
408	static FNSVMEXITHANDLER hmR0SvmExitClgi;
409	static FNSVMEXITHANDLER hmR0SvmExitStgi;
410	static FNSVMEXITHANDLER hmR0SvmExitVmload;
411	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
412	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
413	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
414	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
415	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
416	#endif
417	/** @} */
418
419	static int hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
420	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
421	static int hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
422	#endif
423
424
425	/*********************************************************************************************************************************
426	* Global Variables *
427	*********************************************************************************************************************************/
428	/** Ring-0 memory object for the IO bitmap. */
429	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
430	/** Physical address of the IO bitmap. */
431	static RTHCPHYS g_HCPhysIOBitmap;
432	/** Pointer to the IO bitmap. */
433	static R0PTRTYPE(void *) g_pvIOBitmap;
434
435	#ifdef VBOX_STRICT
436	# define HMSVM_LOG_RBP_RSP RT_BIT_32(0)
437	# define HMSVM_LOG_CR_REGS RT_BIT_32(1)
438	# define HMSVM_LOG_CS RT_BIT_32(2)
439	# define HMSVM_LOG_SS RT_BIT_32(3)
440	# define HMSVM_LOG_FS RT_BIT_32(4)
441	# define HMSVM_LOG_GS RT_BIT_32(5)
442	# define HMSVM_LOG_LBR RT_BIT_32(6)
443	# define HMSVM_LOG_ALL ( HMSVM_LOG_RBP_RSP \
444	\| HMSVM_LOG_CR_REGS \
445	\| HMSVM_LOG_CS \
446	\| HMSVM_LOG_SS \
447	\| HMSVM_LOG_FS \
448	\| HMSVM_LOG_GS \
449	\| HMSVM_LOG_LBR)
450
451	/**
452	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
453	*
454	* @param pVCpu The cross context virtual CPU structure.
455	* @param pVmcb Pointer to the VM control block.
456	* @param pszPrefix Log prefix.
457	* @param fFlags Log flags, see HMSVM_LOG_XXX.
458	* @param uVerbose The verbosity level, currently unused.
459	*/
460	static void hmR0SvmLogState(PVMCPUCC pVCpu, PCSVMVMCB pVmcb, const char *pszPrefix, uint32_t fFlags, uint8_t uVerbose)
461	{
462	RT_NOREF2(pVCpu, uVerbose);
463	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
464
465	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
466	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip, pCtx->rflags.u));
467
468	if (fFlags & HMSVM_LOG_RBP_RSP)
469	{
470	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP);
471	Log4(("%s: rsp=%#RX64 rbp=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp));
472	}
473
474	if (fFlags & HMSVM_LOG_CR_REGS)
475	{
476	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4);
477	Log4(("%s: cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cr0, pCtx->cr3, pCtx->cr4));
478	}
479
480	if (fFlags & HMSVM_LOG_CS)
481	{
482	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
483	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
484	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
485	}
486	if (fFlags & HMSVM_LOG_SS)
487	{
488	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
489	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
490	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
491	}
492	if (fFlags & HMSVM_LOG_FS)
493	{
494	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
495	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
496	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
497	}
498	if (fFlags & HMSVM_LOG_GS)
499	{
500	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
501	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
502	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
503	}
504
505	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
506	if (fFlags & HMSVM_LOG_LBR)
507	{
508	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
509	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
510	}
511	NOREF(pszPrefix); NOREF(pVmcbGuest); NOREF(pCtx);
512	}
513	#endif /* VBOX_STRICT */
514
515
516	/**
517	* Sets up and activates AMD-V on the current CPU.
518	*
519	* @returns VBox status code.
520	* @param pHostCpu The HM physical-CPU structure.
521	* @param pVM The cross context VM structure. Can be
522	* NULL after a resume!
523	* @param pvCpuPage Pointer to the global CPU page.
524	* @param HCPhysCpuPage Physical address of the global CPU page.
525	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
526	* @param pHwvirtMsrs Pointer to the hardware-virtualization MSRs (currently
527	* unused).
528	*/
529	VMMR0DECL(int) SVMR0EnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
530	PCSUPHWVIRTMSRS pHwvirtMsrs)
531	{
532	Assert(!fEnabledByHost);
533	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
534	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
535	Assert(pvCpuPage); NOREF(pvCpuPage);
536	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
537
538	RT_NOREF2(fEnabledByHost, pHwvirtMsrs);
539
540	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
541	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
542
543	/*
544	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
545	*/
546	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
547	if (u64HostEfer & MSR_K6_EFER_SVME)
548	{
549	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
550	if ( pVM
551	&& pVM->hm.s.svm.fIgnoreInUseError)
552	pHostCpu->fIgnoreAMDVInUseError = true;
553
554	if (!pHostCpu->fIgnoreAMDVInUseError)
555	{
556	ASMSetFlags(fEFlags);
557	return VERR_SVM_IN_USE;
558	}
559	}
560
561	/* Turn on AMD-V in the EFER MSR. */
562	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
563
564	/* Write the physical page address where the CPU will store the host state while executing the VM. */
565	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
566
567	/* Restore interrupts. */
568	ASMSetFlags(fEFlags);
569
570	/*
571	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all
572	* non-zero ASIDs when enabling SVM. AMD doesn't have an SVM instruction to flush all
573	* ASIDs (flushing is done upon VMRUN). Therefore, flag that we need to flush the TLB
574	* entirely with before executing any guest code.
575	*/
576	pHostCpu->fFlushAsidBeforeUse = true;
577
578	/*
579	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
580	*/
581	++pHostCpu->cTlbFlushes;
582
583	return VINF_SUCCESS;
584	}
585
586
587	/**
588	* Deactivates AMD-V on the current CPU.
589	*
590	* @returns VBox status code.
591	* @param pvCpuPage Pointer to the global CPU page.
592	* @param HCPhysCpuPage Physical address of the global CPU page.
593	*/
594	VMMR0DECL(int) SVMR0DisableCpu(void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
595	{
596	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
597	AssertReturn( HCPhysCpuPage
598	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
599	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
600
601	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
602	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
603
604	/* Turn off AMD-V in the EFER MSR. */
605	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
606	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
607
608	/* Invalidate host state physical address. */
609	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
610
611	/* Restore interrupts. */
612	ASMSetFlags(fEFlags);
613
614	return VINF_SUCCESS;
615	}
616
617
618	/**
619	* Does global AMD-V initialization (called during module initialization).
620	*
621	* @returns VBox status code.
622	*/
623	VMMR0DECL(int) SVMR0GlobalInit(void)
624	{
625	/*
626	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
627	* intercept all IO accesses, it's done once globally here instead of per-VM.
628	*/
629	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
630	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
631	if (RT_FAILURE(rc))
632	return rc;
633
634	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
635	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
636
637	/* Set all bits to intercept all IO accesses. */
638	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
639
640	return VINF_SUCCESS;
641	}
642
643
644	/**
645	* Does global AMD-V termination (called during module termination).
646	*/
647	VMMR0DECL(void) SVMR0GlobalTerm(void)
648	{
649	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
650	{
651	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
652	g_pvIOBitmap = NULL;
653	g_HCPhysIOBitmap = 0;
654	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
655	}
656	}
657
658
659	/**
660	* Frees any allocated per-VCPU structures for a VM.
661	*
662	* @param pVM The cross context VM structure.
663	*/
664	DECLINLINE(void) hmR0SvmFreeStructs(PVMCC pVM)
665	{
666	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
667	{
668	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
669	AssertPtr(pVCpu);
670
671	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
672	{
673	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
674	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
675	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
676	}
677
678	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
679	{
680	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
681	pVCpu->hm.s.svm.pVmcb = NULL;
682	pVCpu->hm.s.svm.HCPhysVmcb = 0;
683	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
684	}
685
686	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
687	{
688	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
689	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
690	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
691	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
692	}
693	}
694	}
695
696
697	/**
698	* Does per-VM AMD-V initialization.
699	*
700	* @returns VBox status code.
701	* @param pVM The cross context VM structure.
702	*/
703	VMMR0DECL(int) SVMR0InitVM(PVMCC pVM)
704	{
705	int rc = VERR_INTERNAL_ERROR_5;
706
707	/*
708	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
709	*/
710	uint32_t u32Family;
711	uint32_t u32Model;
712	uint32_t u32Stepping;
713	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
714	{
715	Log4Func(("AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
716	pVM->hm.s.svm.fAlwaysFlushTLB = true;
717	}
718
719	/*
720	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
721	*/
722	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
723	{
724	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
725	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
726	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
727	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
728	}
729
730	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
731	{
732	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
733
734	/*
735	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
736	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
737	*/
738	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
739	if (RT_FAILURE(rc))
740	goto failure_cleanup;
741
742	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
743	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
744	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
745	ASMMemZeroPage(pvVmcbHost);
746
747	/*
748	* Allocate one page for the guest-state VMCB.
749	*/
750	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
751	if (RT_FAILURE(rc))
752	goto failure_cleanup;
753
754	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
755	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
756	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
757	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
758
759	/*
760	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
761	* SVM to not require one.
762	*/
763	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
764	false /* fExecutable */);
765	if (RT_FAILURE(rc))
766	goto failure_cleanup;
767
768	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
769	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
770	/* Set all bits to intercept all MSR accesses (changed later on). */
771	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
772	}
773
774	return VINF_SUCCESS;
775
776	failure_cleanup:
777	hmR0SvmFreeStructs(pVM);
778	return rc;
779	}
780
781
782	/**
783	* Does per-VM AMD-V termination.
784	*
785	* @returns VBox status code.
786	* @param pVM The cross context VM structure.
787	*/
788	VMMR0DECL(int) SVMR0TermVM(PVMCC pVM)
789	{
790	hmR0SvmFreeStructs(pVM);
791	return VINF_SUCCESS;
792	}
793
794
795	/**
796	* Returns whether the VMCB Clean Bits feature is supported.
797	*
798	* @returns @c true if supported, @c false otherwise.
799	* @param pVCpu The cross context virtual CPU structure.
800	*/
801	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPUCC pVCpu)
802	{
803	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
804	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
805	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
806	{
807	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
808	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
809	}
810	#endif
811	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
812	}
813
814
815	/**
816	* Returns whether the decode assists feature is supported.
817	*
818	* @returns @c true if supported, @c false otherwise.
819	* @param pVCpu The cross context virtual CPU structure.
820	*/
821	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPUCC pVCpu)
822	{
823	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
824	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
825	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
826	{
827	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
828	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
829	}
830	#endif
831	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
832	}
833
834
835	/**
836	* Returns whether the NRIP_SAVE feature is supported.
837	*
838	* @returns @c true if supported, @c false otherwise.
839	* @param pVCpu The cross context virtual CPU structure.
840	*/
841	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPUCC pVCpu)
842	{
843	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
844	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
845	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
846	{
847	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
848	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
849	}
850	#endif
851	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
852	}
853
854
855	/**
856	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
857	*
858	* @param pVCpu The cross context virtual CPU structure.
859	* @param pbMsrBitmap Pointer to the MSR bitmap.
860	* @param idMsr The MSR for which the permissions are being set.
861	* @param enmRead MSR read permissions.
862	* @param enmWrite MSR write permissions.
863	*
864	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
865	* caller needs to take care of this.
866	*/
867	static void hmR0SvmSetMsrPermission(PVMCPUCC pVCpu, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
868	SVMMSREXITWRITE enmWrite)
869	{
870	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
871	uint16_t offMsrpm;
872	uint8_t uMsrpmBit;
873	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
874	AssertRC(rc);
875
876	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
877	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
878
879	pbMsrBitmap += offMsrpm;
880	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
881	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
882	else
883	{
884	if (!fInNestedGuestMode)
885	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
886	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
887	else
888	{
889	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
890	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
891	pbNstGstMsrBitmap += offMsrpm;
892	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
893	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
894	else
895	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
896	}
897	#endif
898	}
899
900	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
901	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
902	else
903	{
904	if (!fInNestedGuestMode)
905	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
906	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
907	else
908	{
909	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
910	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
911	pbNstGstMsrBitmap += offMsrpm;
912	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
913	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
914	else
915	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
916	}
917	#endif
918	}
919	}
920
921
922	/**
923	* Sets up AMD-V for the specified VM.
924	* This function is only called once per-VM during initalization.
925	*
926	* @returns VBox status code.
927	* @param pVM The cross context VM structure.
928	*/
929	VMMR0DECL(int) SVMR0SetupVM(PVMCC pVM)
930	{
931	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
932	AssertReturn(pVM, VERR_INVALID_PARAMETER);
933	Assert(pVM->hm.s.svm.fSupported);
934
935	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
936	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
937	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
938
939	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
940	bool const fUseLbrVirt = fLbrVirt; /** @todo CFGM, IEM implementation etc. */
941
942	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
943	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
944	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
945
946	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
947	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
948	#endif
949
950	PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
951	PSVMVMCB pVmcb0 = pVCpu0->hm.s.svm.pVmcb;
952	AssertMsgReturn(RT_VALID_PTR(pVmcb0), ("Invalid pVmcb (%p) for vcpu[0]\n", pVmcb0), VERR_SVM_INVALID_PVMCB);
953	PSVMVMCBCTRL pVmcbCtrl0 = &pVmcb0->ctrl;
954
955	/* Always trap #AC for reasons of security. */
956	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
957
958	/* Always trap #DB for reasons of security. */
959	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
960
961	/* Trap exceptions unconditionally (debug purposes). */
962	#ifdef HMSVM_ALWAYS_TRAP_PF
963	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_PF);
964	#endif
965	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
966	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
967	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_BP)
968	\| RT_BIT_32(X86_XCPT_DE)
969	\| RT_BIT_32(X86_XCPT_NM)
970	\| RT_BIT_32(X86_XCPT_UD)
971	\| RT_BIT_32(X86_XCPT_NP)
972	\| RT_BIT_32(X86_XCPT_SS)
973	\| RT_BIT_32(X86_XCPT_GP)
974	\| RT_BIT_32(X86_XCPT_PF)
975	\| RT_BIT_32(X86_XCPT_MF)
976	;
977	#endif
978
979	/* Apply the exceptions intercepts needed by the GIM provider. */
980	if (pVCpu0->hm.s.fGIMTrapXcptUD)
981	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
982
983	/* The mesa 3d driver hack needs #GP. */
984	if (pVCpu0->hm.s.fTrapXcptGpForLovelyMesaDrv)
985	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_GP);
986
987	/* Set up unconditional intercepts and conditions. */
988	pVmcbCtrl0->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
989	\| SVM_CTRL_INTERCEPT_VMMCALL;
990
991	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
992	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
993	#endif
994
995	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
996	/* Virtualized VMSAVE/VMLOAD. */
997	pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
998	if (!fUseVirtVmsaveVmload)
999	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
1000	\| SVM_CTRL_INTERCEPT_VMLOAD;
1001
1002	/* Virtual GIF. */
1003	pVmcbCtrl0->IntCtrl.n.u1VGifEnable = fUseVGif;
1004	if (!fUseVGif)
1005	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
1006	\| SVM_CTRL_INTERCEPT_STGI;
1007	#endif
1008
1009	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
1010	pVmcbCtrl0->u16InterceptWrCRx = RT_BIT(4);
1011
1012	/* Intercept all DRx reads and writes by default. Changed later on. */
1013	pVmcbCtrl0->u16InterceptRdDRx = 0xffff;
1014	pVmcbCtrl0->u16InterceptWrDRx = 0xffff;
1015
1016	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
1017	pVmcbCtrl0->IntCtrl.n.u1VIntrMasking = 1;
1018
1019	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
1020	and we currently deliver both PIC and APIC interrupts alike, see hmR0SvmEvaluatePendingEvent() */
1021	pVmcbCtrl0->IntCtrl.n.u1IgnoreTPR = 1;
1022
1023	/* Set the IO permission bitmap physical addresses. */
1024	pVmcbCtrl0->u64IOPMPhysAddr = g_HCPhysIOBitmap;
1025
1026	/* LBR virtualization. */
1027	pVmcbCtrl0->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
1028
1029	/* The host ASID MBZ, for the guest start with 1. */
1030	pVmcbCtrl0->TLBCtrl.n.u32ASID = 1;
1031
1032	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1033	pVmcbCtrl0->NestedPagingCtrl.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1034
1035	/* Without Nested Paging, we need additionally intercepts. */
1036	if (!pVM->hm.s.fNestedPaging)
1037	{
1038	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1039	pVmcbCtrl0->u16InterceptRdCRx \|= RT_BIT(3);
1040	pVmcbCtrl0->u16InterceptWrCRx \|= RT_BIT(3);
1041
1042	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1043	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1044	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1045
1046	/* Page faults must be intercepted to implement shadow paging. */
1047	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1048	}
1049
1050	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1051	if (fUsePauseFilter)
1052	{
1053	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1054	pVmcbCtrl0->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1055	if (fPauseFilterThreshold)
1056	pVmcbCtrl0->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1057	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1058	}
1059
1060	/*
1061	* Setup the MSR permission bitmap.
1062	* The following MSRs are saved/restored automatically during the world-switch.
1063	* Don't intercept guest read/write accesses to these MSRs.
1064	*/
1065	uint8_t pbMsrBitmap0 = (uint8_t )pVCpu0->hm.s.svm.pvMsrBitmap;
1066	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1067	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1068	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1069	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1070	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1071	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1072	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1073	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1074	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1075	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1076	pVmcbCtrl0->u64MSRPMPhysAddr = pVCpu0->hm.s.svm.HCPhysMsrBitmap;
1077
1078	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1079	Assert(pVmcbCtrl0->u32VmcbCleanBits == 0);
1080
1081	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
1082	{
1083	PVMCPUCC pVCpuCur = VMCC_GET_CPU(pVM, idCpu);
1084	PSVMVMCB pVmcbCur = pVCpuCur->hm.s.svm.pVmcb;
1085	AssertMsgReturn(RT_VALID_PTR(pVmcbCur), ("Invalid pVmcb (%p) for vcpu[%u]\n", pVmcbCur, idCpu), VERR_SVM_INVALID_PVMCB);
1086	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1087
1088	/* Copy the VMCB control area. */
1089	memcpy(pVmcbCtrlCur, pVmcbCtrl0, sizeof(*pVmcbCtrlCur));
1090
1091	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1092	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hm.s.svm.pvMsrBitmap;
1093	memcpy(pbMsrBitmapCur, pbMsrBitmap0, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1094	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hm.s.svm.HCPhysMsrBitmap;
1095
1096	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1097	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1098
1099	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs initially. */
1100	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu0->hm.s.fGIMTrapXcptUD);
1101	}
1102
1103	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1104	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool fUseVGif=%RTbool fUseVirtVmsaveVmload=%RTbool\n", fUsePauseFilter,
1105	fUseLbrVirt, fUseVGif, fUseVirtVmsaveVmload));
1106	#else
1107	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool\n", fUsePauseFilter, fUseLbrVirt));
1108	#endif
1109	return VINF_SUCCESS;
1110	}
1111
1112
1113	/**
1114	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1115	*
1116	* @returns Pointer to the current context VMCB.
1117	* @param pVCpu The cross context virtual CPU structure.
1118	*/
1119	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPUCC pVCpu)
1120	{
1121	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1122	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1123	return pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
1124	#endif
1125	return pVCpu->hm.s.svm.pVmcb;
1126	}
1127
1128
1129	/**
1130	* Gets a pointer to the nested-guest VMCB cache.
1131	*
1132	* @returns Pointer to the nested-guest VMCB cache.
1133	* @param pVCpu The cross context virtual CPU structure.
1134	*/
1135	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPUCC pVCpu)
1136	{
1137	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1138	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
1139	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1140	#else
1141	RT_NOREF(pVCpu);
1142	return NULL;
1143	#endif
1144	}
1145
1146
1147	/**
1148	* Invalidates a guest page by guest virtual address.
1149	*
1150	* @returns VBox status code.
1151	* @param pVCpu The cross context virtual CPU structure.
1152	* @param GCVirt Guest virtual address of the page to invalidate.
1153	*/
1154	VMMR0DECL(int) SVMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1155	{
1156	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
1157
1158	bool const fFlushPending = pVCpu->CTX_SUFF(pVM)->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1159
1160	/* Skip it if a TLB flush is already pending. */
1161	if (!fFlushPending)
1162	{
1163	Log4Func(("%#RGv\n", GCVirt));
1164
1165	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
1166	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1167
1168	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1169	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1170	}
1171	return VINF_SUCCESS;
1172	}
1173
1174
1175	/**
1176	* Flushes the appropriate tagged-TLB entries.
1177	*
1178	* @param pHostCpu The HM physical-CPU structure.
1179	* @param pVCpu The cross context virtual CPU structure.
1180	* @param pVmcb Pointer to the VM control block.
1181	*/
1182	static void hmR0SvmFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1183	{
1184	/*
1185	* Force a TLB flush for the first world switch if the current CPU differs from the one
1186	* we ran on last. This can happen both for start & resume due to long jumps back to
1187	* ring-3.
1188	*
1189	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no
1190	* correlation between it and the physical CPU.
1191	*
1192	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while
1193	* flushing the TLB, so we cannot reuse the ASIDs without flushing.
1194	*/
1195	bool fNewAsid = false;
1196	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1197	if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
1198	\|\| pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
1199	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1200	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
1201	#endif
1202	)
1203	{
1204	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1205	pVCpu->hm.s.fForceTLBFlush = true;
1206	fNewAsid = true;
1207	}
1208
1209	/* Set TLB flush state as checked until we return from the world switch. */
1210	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1211
1212	/* Check for explicit TLB flushes. */
1213	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1214	{
1215	pVCpu->hm.s.fForceTLBFlush = true;
1216	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1217	}
1218
1219	/*
1220	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1221	* This Host CPU requirement takes precedence.
1222	*/
1223	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1224	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1225	{
1226	pHostCpu->uCurrentAsid = 1;
1227	pVCpu->hm.s.uCurrentAsid = 1;
1228	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1229	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1230	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1231
1232	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1233	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1234	}
1235	else
1236	{
1237	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1238	if (pVCpu->hm.s.fForceTLBFlush)
1239	{
1240	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1241	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1242
1243	if (fNewAsid)
1244	{
1245	++pHostCpu->uCurrentAsid;
1246
1247	bool fHitASIDLimit = false;
1248	if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1249	{
1250	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1251	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1252	fHitASIDLimit = true;
1253	}
1254
1255	if ( fHitASIDLimit
1256	\|\| pHostCpu->fFlushAsidBeforeUse)
1257	{
1258	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1259	pHostCpu->fFlushAsidBeforeUse = false;
1260	}
1261
1262	pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1263	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1264	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1265	}
1266	else
1267	{
1268	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1269	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1270	else
1271	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1272	}
1273
1274	pVCpu->hm.s.fForceTLBFlush = false;
1275	}
1276	}
1277
1278	/* Update VMCB with the ASID. */
1279	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1280	{
1281	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1282	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1283	}
1284
1285	AssertMsg(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu,
1286	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pHostCpu->idCpu));
1287	AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1288	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1289	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1290	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1291	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1292	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1293
1294	#ifdef VBOX_WITH_STATISTICS
1295	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1296	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1297	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1298	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1299	{
1300	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1301	}
1302	else
1303	{
1304	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1305	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1306	}
1307	#endif
1308	}
1309
1310
1311	/**
1312	* Sets an exception intercept in the specified VMCB.
1313	*
1314	* @param pVmcb Pointer to the VM control block.
1315	* @param uXcpt The exception (X86_XCPT_*).
1316	*/
1317	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1318	{
1319	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1320	{
1321	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1322	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1323	}
1324	}
1325
1326
1327	/**
1328	* Clears an exception intercept in the specified VMCB.
1329	*
1330	* @param pVCpu The cross context virtual CPU structure.
1331	* @param pVmcb Pointer to the VM control block.
1332	* @param uXcpt The exception (X86_XCPT_*).
1333	*
1334	* @remarks This takes into account if we're executing a nested-guest and only
1335	* removes the exception intercept if both the guest -and- nested-guest
1336	* are not intercepting it.
1337	*/
1338	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint8_t uXcpt)
1339	{
1340	Assert(uXcpt != X86_XCPT_DB);
1341	Assert(uXcpt != X86_XCPT_AC);
1342	Assert(uXcpt != X86_XCPT_GP);
1343	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1344	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1345	{
1346	bool fRemove = true;
1347	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1348	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1349	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1350	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1351	{
1352	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1353	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1354	}
1355	# else
1356	RT_NOREF(pVCpu);
1357	# endif
1358	if (fRemove)
1359	{
1360	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1361	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1362	}
1363	}
1364	#else
1365	RT_NOREF3(pVCpu, pVmcb, uXcpt);
1366	#endif
1367	}
1368
1369
1370	/**
1371	* Sets a control intercept in the specified VMCB.
1372	*
1373	* @param pVmcb Pointer to the VM control block.
1374	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1375	*/
1376	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1377	{
1378	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1379	{
1380	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1381	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1382	}
1383	}
1384
1385
1386	/**
1387	* Clears a control intercept in the specified VMCB.
1388	*
1389	* @returns @c true if the intercept is still set, @c false otherwise.
1390	* @param pVCpu The cross context virtual CPU structure.
1391	* @param pVmcb Pointer to the VM control block.
1392	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1393	*
1394	* @remarks This takes into account if we're executing a nested-guest and only
1395	* removes the control intercept if both the guest -and- nested-guest
1396	* are not intercepting it.
1397	*/
1398	static bool hmR0SvmClearCtrlIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1399	{
1400	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1401	{
1402	bool fRemove = true;
1403	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1404	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1405	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1406	{
1407	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1408	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1409	}
1410	#else
1411	RT_NOREF(pVCpu);
1412	#endif
1413	if (fRemove)
1414	{
1415	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1416	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1417	}
1418	}
1419
1420	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1421	}
1422
1423
1424	/**
1425	* Exports the guest (or nested-guest) CR0 into the VMCB.
1426	*
1427	* @param pVCpu The cross context virtual CPU structure.
1428	* @param pVmcb Pointer to the VM control block.
1429	*
1430	* @remarks This assumes we always pre-load the guest FPU.
1431	* @remarks No-long-jump zone!!!
1432	*/
1433	static void hmR0SvmExportGuestCR0(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1434	{
1435	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1436
1437	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1438	uint64_t const uGuestCr0 = pCtx->cr0;
1439	uint64_t uShadowCr0 = uGuestCr0;
1440
1441	/* Always enable caching. */
1442	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1443
1444	/* When Nested Paging is not available use shadow page tables and intercept #PFs (latter done in SVMR0SetupVM()). */
1445	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1446	{
1447	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1448	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1449	}
1450
1451	/*
1452	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that
1453	* lets us isolate the host from it, IEM/REM still needs work to emulate it properly,
1454	* see @bugref{7243#c103}.
1455	*/
1456	if (!(uGuestCr0 & X86_CR0_NE))
1457	{
1458	uShadowCr0 \|= X86_CR0_NE;
1459	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1460	}
1461	else
1462	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_MF);
1463
1464	/*
1465	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1466	*
1467	* CR0 writes still needs interception as PGM requires tracking paging mode changes,
1468	* see @bugref{6944}.
1469	*
1470	* We also don't ever want to honor weird things like cache disable from the guest.
1471	* However, we can avoid intercepting changes to the TS & MP bits by clearing the CR0
1472	* write intercept below and keeping SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1473	*/
1474	if (uShadowCr0 == uGuestCr0)
1475	{
1476	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1477	{
1478	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1479	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1480	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1481	}
1482	else
1483	{
1484	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1485	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1486	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1487	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1488	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1489	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1490	}
1491	}
1492	else
1493	{
1494	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1495	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1496	}
1497	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1498
1499	Assert(!RT_HI_U32(uShadowCr0));
1500	if (pVmcb->guest.u64CR0 != uShadowCr0)
1501	{
1502	pVmcb->guest.u64CR0 = uShadowCr0;
1503	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1504	}
1505	}
1506
1507
1508	/**
1509	* Exports the guest (or nested-guest) CR3 into the VMCB.
1510	*
1511	* @param pVCpu The cross context virtual CPU structure.
1512	* @param pVmcb Pointer to the VM control block.
1513	*
1514	* @remarks No-long-jump zone!!!
1515	*/
1516	static void hmR0SvmExportGuestCR3(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1517	{
1518	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1519
1520	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1521	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1522	if (pVM->hm.s.fNestedPaging)
1523	{
1524	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetHyperCR3(pVCpu);
1525	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1526	pVmcb->guest.u64CR3 = pCtx->cr3;
1527	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1528	}
1529	else
1530	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1531
1532	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1533	}
1534
1535
1536	/**
1537	* Exports the guest (or nested-guest) CR4 into the VMCB.
1538	*
1539	* @param pVCpu The cross context virtual CPU structure.
1540	* @param pVmcb Pointer to the VM control block.
1541	*
1542	* @remarks No-long-jump zone!!!
1543	*/
1544	static int hmR0SvmExportGuestCR4(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1545	{
1546	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1547
1548	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1549	uint64_t uShadowCr4 = pCtx->cr4;
1550	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1551	{
1552	switch (pVCpu->hm.s.enmShadowMode)
1553	{
1554	case PGMMODE_REAL:
1555	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1556	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1557
1558	case PGMMODE_32_BIT: /* 32-bit paging. */
1559	uShadowCr4 &= ~X86_CR4_PAE;
1560	break;
1561
1562	case PGMMODE_PAE: /* PAE paging. */
1563	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1564	/** Must use PAE paging as we could use physical memory > 4 GB */
1565	uShadowCr4 \|= X86_CR4_PAE;
1566	break;
1567
1568	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1569	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1570	#ifdef VBOX_WITH_64_BITS_GUESTS
1571	break;
1572	#else
1573	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1574	#endif
1575
1576	default: /* shut up gcc */
1577	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1578	}
1579	}
1580
1581	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1582	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1583
1584	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1585	if (uShadowCr4 == pCtx->cr4)
1586	{
1587	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1588	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1589	else
1590	{
1591	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1592	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1593	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1594	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1595	}
1596	}
1597	else
1598	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1599
1600	/* CR4 writes are always intercepted (both guest, nested-guest) for tracking PGM mode changes. */
1601	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1602
1603	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1604	Assert(!RT_HI_U32(uShadowCr4));
1605	pVmcb->guest.u64CR4 = uShadowCr4;
1606	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1607
1608	return VINF_SUCCESS;
1609	}
1610
1611
1612	/**
1613	* Exports the guest (or nested-guest) control registers into the VMCB.
1614	*
1615	* @returns VBox status code.
1616	* @param pVCpu The cross context virtual CPU structure.
1617	* @param pVmcb Pointer to the VM control block.
1618	*
1619	* @remarks No-long-jump zone!!!
1620	*/
1621	static int hmR0SvmExportGuestControlRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1622	{
1623	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1624
1625	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR_MASK)
1626	{
1627	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR0)
1628	hmR0SvmExportGuestCR0(pVCpu, pVmcb);
1629
1630	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR2)
1631	{
1632	pVmcb->guest.u64CR2 = pVCpu->cpum.GstCtx.cr2;
1633	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1634	}
1635
1636	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR3)
1637	hmR0SvmExportGuestCR3(pVCpu, pVmcb);
1638
1639	/* CR4 re-loading is ASSUMED to be done everytime we get in from ring-3! (XCR0) */
1640	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR4)
1641	{
1642	int rc = hmR0SvmExportGuestCR4(pVCpu, pVmcb);
1643	if (RT_FAILURE(rc))
1644	return rc;
1645	}
1646
1647	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_CR_MASK;
1648	}
1649	return VINF_SUCCESS;
1650	}
1651
1652
1653	/**
1654	* Exports the guest (or nested-guest) segment registers into the VMCB.
1655	*
1656	* @returns VBox status code.
1657	* @param pVCpu The cross context virtual CPU structure.
1658	* @param pVmcb Pointer to the VM control block.
1659	*
1660	* @remarks No-long-jump zone!!!
1661	*/
1662	static void hmR0SvmExportGuestSegmentRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1663	{
1664	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1665	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1666
1667	/* Guest segment registers. */
1668	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SREG_MASK)
1669	{
1670	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CS)
1671	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1672
1673	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SS)
1674	{
1675	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1676	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1677	}
1678
1679	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DS)
1680	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1681
1682	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_ES)
1683	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1684
1685	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_FS)
1686	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1687
1688	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GS)
1689	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1690
1691	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1692	}
1693
1694	/* Guest TR. */
1695	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_TR)
1696	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1697
1698	/* Guest LDTR. */
1699	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_LDTR)
1700	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1701
1702	/* Guest GDTR. */
1703	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GDTR)
1704	{
1705	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1706	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1707	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1708	}
1709
1710	/* Guest IDTR. */
1711	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_IDTR)
1712	{
1713	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1714	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1715	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1716	}
1717
1718	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SREG_MASK
1719	\| HM_CHANGED_GUEST_TABLE_MASK);
1720	}
1721
1722
1723	/**
1724	* Exports the guest (or nested-guest) MSRs into the VMCB.
1725	*
1726	* @param pVCpu The cross context virtual CPU structure.
1727	* @param pVmcb Pointer to the VM control block.
1728	*
1729	* @remarks No-long-jump zone!!!
1730	*/
1731	static void hmR0SvmExportGuestMsrs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1732	{
1733	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1734	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1735
1736	/* Guest Sysenter MSRs. */
1737	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
1738	{
1739	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
1740	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1741
1742	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
1743	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1744
1745	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
1746	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1747	}
1748
1749	/*
1750	* Guest EFER MSR.
1751	* AMD-V requires guest EFER.SVME to be set. Weird.
1752	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1753	*/
1754	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_EFER_MSR)
1755	{
1756	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1757	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1758	}
1759
1760	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit, otherwise SVM expects amd64 shadow paging. */
1761	if ( !CPUMIsGuestInLongModeEx(pCtx)
1762	&& (pCtx->msrEFER & MSR_K6_EFER_LME))
1763	{
1764	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1765	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1766	}
1767
1768	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSCALL_MSRS)
1769	{
1770	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1771	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1772	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1773	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1774	}
1775
1776	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_KERNEL_GS_BASE)
1777	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1778
1779	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SYSENTER_MSR_MASK
1780	\| HM_CHANGED_GUEST_EFER_MSR
1781	\| HM_CHANGED_GUEST_SYSCALL_MSRS
1782	\| HM_CHANGED_GUEST_KERNEL_GS_BASE);
1783
1784	/*
1785	* Setup the PAT MSR (applicable for Nested Paging only).
1786	*
1787	* While guests can modify and see the modified values through the shadow values,
1788	* we shall not honor any guest modifications of this MSR to ensure caching is always
1789	* enabled similar to how we clear CR0.CD and NW bits.
1790	*
1791	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1792	*/
1793	pVmcb->guest.u64PAT = MSR_IA32_CR_PAT_INIT_VAL;
1794
1795	/* Enable the last branch record bit if LBR virtualization is enabled. */
1796	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1797	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1798	}
1799
1800
1801	/**
1802	* Exports the guest (or nested-guest) debug state into the VMCB and programs
1803	* the necessary intercepts accordingly.
1804	*
1805	* @param pVCpu The cross context virtual CPU structure.
1806	* @param pVmcb Pointer to the VM control block.
1807	*
1808	* @remarks No-long-jump zone!!!
1809	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1810	*/
1811	static void hmR0SvmExportSharedDebugState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1812	{
1813	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1814
1815	/*
1816	* Anyone single stepping on the host side? If so, we'll have to use the
1817	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1818	* the VMM level like the VT-x implementations does.
1819	*/
1820	bool fInterceptMovDRx = false;
1821	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1822	if (fStepping)
1823	{
1824	pVCpu->hm.s.fClearTrapFlag = true;
1825	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1826	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1827	}
1828
1829	if ( fStepping
1830	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1831	{
1832	/*
1833	* Use the combined guest and host DRx values found in the hypervisor
1834	* register set because the debugger has breakpoints active or someone
1835	* is single stepping on the host side.
1836	*
1837	* Note! DBGF expects a clean DR6 state before executing guest code.
1838	*/
1839	if (!CPUMIsHyperDebugStateActive(pVCpu))
1840	{
1841	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1842	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1843	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1844	}
1845
1846	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1847	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1848	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1849	{
1850	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1851	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1852	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1853	}
1854
1855	/** @todo If we cared, we could optimize to allow the guest to read registers
1856	* with the same values. */
1857	fInterceptMovDRx = true;
1858	pVCpu->hm.s.fUsingHyperDR7 = true;
1859	Log5(("hmR0SvmExportSharedDebugState: Loaded hyper DRx\n"));
1860	}
1861	else
1862	{
1863	/*
1864	* Update DR6, DR7 with the guest values if necessary.
1865	*/
1866	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1867	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1868	{
1869	pVmcb->guest.u64DR7 = pCtx->dr[7];
1870	pVmcb->guest.u64DR6 = pCtx->dr[6];
1871	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1872	}
1873	pVCpu->hm.s.fUsingHyperDR7 = false;
1874
1875	/*
1876	* If the guest has enabled debug registers, we need to load them prior to
1877	* executing guest code so they'll trigger at the right time.
1878	*/
1879	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1880	{
1881	if (!CPUMIsGuestDebugStateActive(pVCpu))
1882	{
1883	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1884	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1885	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1886	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1887	}
1888	Log5(("hmR0SvmExportSharedDebugState: Loaded guest DRx\n"));
1889	}
1890	/*
1891	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1892	* intercept #DB as DR6 is updated in the VMCB.
1893	*
1894	* Note! If we cared and dared, we could skip intercepting \#DB here.
1895	* However, \#DB shouldn't be performance critical, so we'll play safe
1896	* and keep the code similar to the VT-x code and always intercept it.
1897	*/
1898	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1899	fInterceptMovDRx = true;
1900	}
1901
1902	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1903	if (fInterceptMovDRx)
1904	{
1905	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1906	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1907	{
1908	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1909	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1910	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1911	}
1912	}
1913	else
1914	{
1915	if ( pVmcb->ctrl.u16InterceptRdDRx
1916	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1917	{
1918	pVmcb->ctrl.u16InterceptRdDRx = 0;
1919	pVmcb->ctrl.u16InterceptWrDRx = 0;
1920	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1921	}
1922	}
1923	Log4Func(("DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1924	}
1925
1926	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1927	/**
1928	* Exports the nested-guest hardware virtualization state into the nested-guest
1929	* VMCB.
1930	*
1931	* @param pVCpu The cross context virtual CPU structure.
1932	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1933	*
1934	* @remarks No-long-jump zone!!!
1935	*/
1936	static void hmR0SvmExportGuestHwvirtStateNested(PVMCPUCC pVCpu, PSVMVMCB pVmcbNstGst)
1937	{
1938	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1939
1940	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_HWVIRT)
1941	{
1942	/*
1943	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
1944	* since SVM doesn't have a preemption timer.
1945	*
1946	* We do this here rather than in hmR0SvmSetupVmcbNested() as we may have been executing the
1947	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
1948	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
1949	*/
1950	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1951	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
1952	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1953	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1954	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_PAUSE))
1955	{
1956	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1957	pVmcbNstGstCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
1958	pVmcbNstGstCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
1959	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1960	}
1961	else
1962	{
1963	pVmcbNstGstCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
1964	pVmcbNstGstCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
1965	}
1966
1967	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_HWVIRT;
1968	}
1969	}
1970	#endif
1971
1972	/**
1973	* Exports the guest APIC TPR state into the VMCB.
1974	*
1975	* @returns VBox status code.
1976	* @param pVCpu The cross context virtual CPU structure.
1977	* @param pVmcb Pointer to the VM control block.
1978	*/
1979	static int hmR0SvmExportGuestApicTpr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1980	{
1981	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
1982	{
1983	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1984	if ( PDMHasApic(pVM)
1985	&& APICIsEnabled(pVCpu))
1986	{
1987	bool fPendingIntr;
1988	uint8_t u8Tpr;
1989	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1990	AssertRCReturn(rc, rc);
1991
1992	/* Assume that we need to trap all TPR accesses and thus need not check on
1993	every #VMEXIT if we should update the TPR. */
1994	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1995	pVCpu->hm.s.svm.fSyncVTpr = false;
1996
1997	if (!pVM->hm.s.fTPRPatchingActive)
1998	{
1999	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2000	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2001
2002	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we
2003	can deliver the interrupt to the guest. */
2004	if (fPendingIntr)
2005	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2006	else
2007	{
2008	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2009	pVCpu->hm.s.svm.fSyncVTpr = true;
2010	}
2011
2012	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_INT_CTRL);
2013	}
2014	else
2015	{
2016	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2017	pVmcb->guest.u64LSTAR = u8Tpr;
2018	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
2019
2020	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2021	if (fPendingIntr)
2022	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2023	else
2024	{
2025	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2026	pVCpu->hm.s.svm.fSyncVTpr = true;
2027	}
2028	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2029	}
2030	}
2031	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
2032	}
2033	return VINF_SUCCESS;
2034	}
2035
2036
2037	/**
2038	* Sets up the exception interrupts required for guest (or nested-guest)
2039	* execution in the VMCB.
2040	*
2041	* @param pVCpu The cross context virtual CPU structure.
2042	* @param pVmcb Pointer to the VM control block.
2043	*
2044	* @remarks No-long-jump zone!!!
2045	*/
2046	static void hmR0SvmExportGuestXcptIntercepts(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2047	{
2048	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2049
2050	/* If we modify intercepts from here, please check & adjust hmR0SvmMergeVmcbCtrlsNested() if required. */
2051	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_XCPT_INTERCEPTS)
2052	{
2053	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2054	if (pVCpu->hm.s.fGIMTrapXcptUD)
2055	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2056	else
2057	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_UD);
2058
2059	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2060	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2061	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2062	else
2063	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_BP);
2064
2065	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmExportGuestCR0(). */
2066	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_SVM_XCPT_INTERCEPTS;
2067	}
2068	}
2069
2070
2071	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2072	/**
2073	* Merges guest and nested-guest intercepts for executing the nested-guest using
2074	* hardware-assisted SVM.
2075	*
2076	* This merges the guest and nested-guest intercepts in a way that if the outer
2077	* guest intercept is set we need to intercept it in the nested-guest as
2078	* well.
2079	*
2080	* @param pVCpu The cross context virtual CPU structure.
2081	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2082	*/
2083	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPUCC pVCpu)
2084	{
2085	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2086	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2087	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2088	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2089
2090	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2091	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2092	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2093
2094	/* Always intercept CR4 writes for tracking PGM mode changes. */
2095	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2096
2097	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2098	if (!pVM->hm.s.fNestedPaging)
2099	{
2100	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2101	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2102	}
2103
2104	/** @todo Figure out debugging with nested-guests, till then just intercept
2105	* all DR[0-15] accesses. */
2106	pVmcbNstGstCtrl->u16InterceptRdDRx \|= 0xffff;
2107	pVmcbNstGstCtrl->u16InterceptWrDRx \|= 0xffff;
2108
2109	/*
2110	* Merge the guest's exception intercepts into the nested-guest VMCB.
2111	*
2112	* - #UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2113	* while executing the nested-guest.
2114	*
2115	* - #BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2116	* be tweaked later depending on how we wish to implement breakpoints.
2117	*
2118	* - #GP: Exclude these as it's the inner VMMs problem to get vmsvga 3d drivers
2119	* loaded into their guests, not ours.
2120	*
2121	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2122	* for VM debugger breakpoints, see hmR0SvmExportGuestXcptIntercepts().
2123	*/
2124	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2125	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt
2126	& ~( RT_BIT(X86_XCPT_UD)
2127	\| RT_BIT(X86_XCPT_BP)
2128	\| (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv ? RT_BIT(X86_XCPT_GP) : 0));
2129	#else
2130	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2131	#endif
2132
2133	/*
2134	* Adjust intercepts while executing the nested-guest that differ from the
2135	* outer guest intercepts.
2136	*
2137	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2138	* that belong to the nested-guest to the outer guest.
2139	*
2140	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2141	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2142	*/
2143	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2144	\| SVM_CTRL_INTERCEPT_VMMCALL))
2145	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2146
2147	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2148	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2149
2150	/* Finally, update the VMCB clean bits. */
2151	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2152	}
2153	#endif
2154
2155
2156	/**
2157	* Selects the appropriate function to run guest code.
2158	*
2159	* @returns VBox status code.
2160	* @param pVCpu The cross context virtual CPU structure.
2161	*
2162	* @remarks No-long-jump zone!!!
2163	*/
2164	static int hmR0SvmSelectVMRunHandler(PVMCPUCC pVCpu)
2165	{
2166	if (CPUMIsGuestInLongMode(pVCpu))
2167	{
2168	#ifndef VBOX_WITH_64_BITS_GUESTS
2169	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
2170	#else
2171	# if HC_ARCH_BITS != 64 \|\| ARCH_BITS != 64
2172	# error "Only 64-bit hosts are supported!"
2173	# endif
2174	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
2175	/* Guest in long mode, use 64-bit handler (host is 64-bit). */
2176	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
2177	#endif
2178	}
2179	else
2180	{
2181	/* Guest is not in long mode, use the 32-bit handler. */
2182	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2183	}
2184	return VINF_SUCCESS;
2185	}
2186
2187
2188	/**
2189	* Enters the AMD-V session.
2190	*
2191	* @returns VBox status code.
2192	* @param pVCpu The cross context virtual CPU structure.
2193	*/
2194	VMMR0DECL(int) SVMR0Enter(PVMCPUCC pVCpu)
2195	{
2196	AssertPtr(pVCpu);
2197	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
2198	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2199
2200	LogFlowFunc(("pVCpu=%p\n", pVCpu));
2201	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2202	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2203
2204	pVCpu->hm.s.fLeaveDone = false;
2205	return VINF_SUCCESS;
2206	}
2207
2208
2209	/**
2210	* Thread-context callback for AMD-V.
2211	*
2212	* @param enmEvent The thread-context event.
2213	* @param pVCpu The cross context virtual CPU structure.
2214	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2215	* @thread EMT(pVCpu)
2216	*/
2217	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
2218	{
2219	NOREF(fGlobalInit);
2220
2221	switch (enmEvent)
2222	{
2223	case RTTHREADCTXEVENT_OUT:
2224	{
2225	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2226	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2227	VMCPU_ASSERT_EMT(pVCpu);
2228
2229	/* No longjmps (log-flush, locks) in this fragile context. */
2230	VMMRZCallRing3Disable(pVCpu);
2231
2232	if (!pVCpu->hm.s.fLeaveDone)
2233	{
2234	hmR0SvmLeave(pVCpu, false /* fImportState */);
2235	pVCpu->hm.s.fLeaveDone = true;
2236	}
2237
2238	/* Leave HM context, takes care of local init (term). */
2239	int rc = HMR0LeaveCpu(pVCpu);
2240	AssertRC(rc); NOREF(rc);
2241
2242	/* Restore longjmp state. */
2243	VMMRZCallRing3Enable(pVCpu);
2244	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2245	break;
2246	}
2247
2248	case RTTHREADCTXEVENT_IN:
2249	{
2250	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2251	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2252	VMCPU_ASSERT_EMT(pVCpu);
2253
2254	/* No longjmps (log-flush, locks) in this fragile context. */
2255	VMMRZCallRing3Disable(pVCpu);
2256
2257	/*
2258	* Initialize the bare minimum state required for HM. This takes care of
2259	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2260	*/
2261	int rc = hmR0EnterCpu(pVCpu);
2262	AssertRC(rc); NOREF(rc);
2263	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2264	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2265
2266	pVCpu->hm.s.fLeaveDone = false;
2267
2268	/* Restore longjmp state. */
2269	VMMRZCallRing3Enable(pVCpu);
2270	break;
2271	}
2272
2273	default:
2274	break;
2275	}
2276	}
2277
2278
2279	/**
2280	* Saves the host state.
2281	*
2282	* @returns VBox status code.
2283	* @param pVCpu The cross context virtual CPU structure.
2284	*
2285	* @remarks No-long-jump zone!!!
2286	*/
2287	VMMR0DECL(int) SVMR0ExportHostState(PVMCPUCC pVCpu)
2288	{
2289	NOREF(pVCpu);
2290
2291	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2292	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_HOST_CONTEXT);
2293	return VINF_SUCCESS;
2294	}
2295
2296
2297	/**
2298	* Exports the guest state from the guest-CPU context into the VMCB.
2299	*
2300	* The CPU state will be loaded from these fields on every successful VM-entry.
2301	* Also sets up the appropriate VMRUN function to execute guest code based on
2302	* the guest CPU mode.
2303	*
2304	* @returns VBox status code.
2305	* @param pVCpu The cross context virtual CPU structure.
2306	*
2307	* @remarks No-long-jump zone!!!
2308	*/
2309	static int hmR0SvmExportGuestState(PVMCPUCC pVCpu)
2310	{
2311	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2312
2313	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2314	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2315
2316	Assert(pVmcb);
2317	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2318
2319	pVmcb->guest.u64RIP = pCtx->rip;
2320	pVmcb->guest.u64RSP = pCtx->rsp;
2321	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2322	pVmcb->guest.u64RAX = pCtx->rax;
2323	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2324	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
2325	{
2326	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF); /* Hardware supports it. */
2327	Assert(HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2328	pVmcb->ctrl.IntCtrl.n.u1VGif = CPUMGetGuestGif(pCtx);
2329	}
2330	#endif
2331
2332	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2333
2334	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcb);
2335	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2336
2337	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcb);
2338	hmR0SvmExportGuestMsrs(pVCpu, pVmcb);
2339	hmR0SvmExportGuestXcptIntercepts(pVCpu, pVmcb);
2340
2341	ASMSetFlags(fEFlags);
2342
2343	/* hmR0SvmExportGuestApicTpr() must be called -after- hmR0SvmExportGuestMsrs() as we
2344	otherwise we would overwrite the LSTAR MSR that we use for TPR patching. */
2345	hmR0SvmExportGuestApicTpr(pVCpu, pVmcb);
2346
2347	rc = hmR0SvmSelectVMRunHandler(pVCpu);
2348	AssertRCReturn(rc, rc);
2349
2350	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2351	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( HM_CHANGED_GUEST_RIP
2352	\| HM_CHANGED_GUEST_RFLAGS
2353	\| HM_CHANGED_GUEST_GPRS_MASK
2354	\| HM_CHANGED_GUEST_X87
2355	\| HM_CHANGED_GUEST_SSE_AVX
2356	\| HM_CHANGED_GUEST_OTHER_XSAVE
2357	\| HM_CHANGED_GUEST_XCRx
2358	\| HM_CHANGED_GUEST_TSC_AUX
2359	\| HM_CHANGED_GUEST_OTHER_MSRS
2360	\| HM_CHANGED_GUEST_HWVIRT
2361	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_XCPT_INTERCEPTS)));
2362
2363	#ifdef VBOX_STRICT
2364	/*
2365	* All of the guest-CPU state and SVM keeper bits should be exported here by now,
2366	* except for the host-context and/or shared host-guest context bits.
2367	*/
2368	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2369	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
2370	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2371	("fCtxChanged=%#RX64\n", fCtxChanged));
2372
2373	/*
2374	* If we need to log state that isn't always imported, we'll need to import them here.
2375	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2376	*/
2377	hmR0SvmLogState(pVCpu, pVmcb, "hmR0SvmExportGuestState", 0 /* fFlags /, 0 / uVerbose */);
2378	#endif
2379
2380	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2381	return VINF_SUCCESS;
2382	}
2383
2384
2385	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2386	/**
2387	* Merges the guest and nested-guest MSR permission bitmap.
2388	*
2389	* If the guest is intercepting an MSR we need to intercept it regardless of
2390	* whether the nested-guest is intercepting it or not.
2391	*
2392	* @param pHostCpu The HM physical-CPU structure.
2393	* @param pVCpu The cross context virtual CPU structure.
2394	*
2395	* @remarks No-long-jmp zone!!!
2396	*/
2397	DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu)
2398	{
2399	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hm.s.svm.pvMsrBitmap;
2400	uint64_t const pu64NstGstMsrpm = (uint64_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2401	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2402
2403	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2404	uint32_t const offRsvdQwords = 0x1800 >> 3;
2405	for (uint32_t i = 0; i < offRsvdQwords; i++)
2406	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2407	}
2408
2409
2410	/**
2411	* Caches the nested-guest VMCB fields before we modify them for execution using
2412	* hardware-assisted SVM.
2413	*
2414	* @returns true if the VMCB was previously already cached, false otherwise.
2415	* @param pVCpu The cross context virtual CPU structure.
2416	*
2417	* @sa HMNotifySvmNstGstVmexit.
2418	*/
2419	static bool hmR0SvmCacheVmcbNested(PVMCPUCC pVCpu)
2420	{
2421	/*
2422	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2423	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2424	*
2425	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2426	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2427	*/
2428	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2429	bool const fWasCached = pVmcbNstGstCache->fCacheValid;
2430	if (!fWasCached)
2431	{
2432	PCSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2433	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2434	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2435	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2436	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2437	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2438	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2439	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2440	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2441	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2442	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2443	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2444	pVmcbNstGstCache->fNestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2445	pVmcbNstGstCache->fLbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2446	pVmcbNstGstCache->fCacheValid = true;
2447	Log4Func(("Cached VMCB fields\n"));
2448	}
2449
2450	return fWasCached;
2451	}
2452
2453
2454	/**
2455	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2456	*
2457	* This is done the first time we enter nested-guest execution using SVM R0
2458	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2459	* \#VMEXITs which may or may not cause a corresponding nested-guest \#VMEXIT).
2460	*
2461	* @param pVCpu The cross context virtual CPU structure.
2462	*/
2463	static void hmR0SvmSetupVmcbNested(PVMCPUCC pVCpu)
2464	{
2465	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2466	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2467
2468	/*
2469	* First cache the nested-guest VMCB fields we may potentially modify.
2470	*/
2471	bool const fVmcbCached = hmR0SvmCacheVmcbNested(pVCpu);
2472	if (!fVmcbCached)
2473	{
2474	/*
2475	* The IOPM of the nested-guest can be ignored because the the guest always
2476	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2477	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2478	*/
2479	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2480
2481	/*
2482	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2483	* nested-paging suddenly while executing a VM (see assertion at the end of
2484	* Trap0eHandler() in PGMAllBth.h).
2485	*/
2486	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2487
2488	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2489	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2490
2491	/*
2492	* Turn off TPR syncing on #VMEXIT for nested-guests as CR8 intercepts are subject
2493	* to the nested-guest intercepts and we always run with V_INTR_MASKING.
2494	*/
2495	pVCpu->hm.s.svm.fSyncVTpr = false;
2496
2497	#ifdef DEBUG_ramshankar
2498	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2499	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2500	#endif
2501
2502	/*
2503	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2504	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2505	*/
2506	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2507	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2508	\| SVM_CTRL_INTERCEPT_VMLOAD;
2509
2510	/*
2511	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2512	* CLGI/STGI instructions executed by the nested-guest.
2513	*/
2514	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2515	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2516	\| SVM_CTRL_INTERCEPT_STGI;
2517
2518	/* Merge the guest and nested-guest intercepts. */
2519	hmR0SvmMergeVmcbCtrlsNested(pVCpu);
2520
2521	/* Update the VMCB clean bits. */
2522	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2523	}
2524	else
2525	{
2526	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
2527	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2528	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2529	}
2530	}
2531
2532
2533	/**
2534	* Exports the nested-guest state into the VMCB.
2535	*
2536	* We need to export the entire state as we could be continuing nested-guest
2537	* execution at any point (not just immediately after VMRUN) and thus the VMCB
2538	* can be out-of-sync with the nested-guest state if it was executed in IEM.
2539	*
2540	* @returns VBox status code.
2541	* @param pVCpu The cross context virtual CPU structure.
2542	* @param pCtx Pointer to the guest-CPU context.
2543	*
2544	* @remarks No-long-jump zone!!!
2545	*/
2546	static int hmR0SvmExportGuestStateNested(PVMCPUCC pVCpu)
2547	{
2548	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2549
2550	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2551	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2552	Assert(pVmcbNstGst);
2553
2554	hmR0SvmSetupVmcbNested(pVCpu);
2555
2556	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2557	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2558	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2559	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2560
2561	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2562
2563	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcbNstGst);
2564	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2565
2566	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcbNstGst);
2567	hmR0SvmExportGuestMsrs(pVCpu, pVmcbNstGst);
2568	hmR0SvmExportGuestHwvirtStateNested(pVCpu, pVmcbNstGst);
2569
2570	ASMSetFlags(fEFlags);
2571
2572	/* Nested VGIF not supported yet. */
2573	Assert(!pVmcbNstGst->ctrl.IntCtrl.n.u1VGifEnable);
2574
2575	rc = hmR0SvmSelectVMRunHandler(pVCpu);
2576	AssertRCReturn(rc, rc);
2577
2578	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2579	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( HM_CHANGED_GUEST_RIP
2580	\| HM_CHANGED_GUEST_RFLAGS
2581	\| HM_CHANGED_GUEST_GPRS_MASK
2582	\| HM_CHANGED_GUEST_APIC_TPR
2583	\| HM_CHANGED_GUEST_X87
2584	\| HM_CHANGED_GUEST_SSE_AVX
2585	\| HM_CHANGED_GUEST_OTHER_XSAVE
2586	\| HM_CHANGED_GUEST_XCRx
2587	\| HM_CHANGED_GUEST_TSC_AUX
2588	\| HM_CHANGED_GUEST_OTHER_MSRS
2589	\| HM_CHANGED_SVM_XCPT_INTERCEPTS
2590	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_MASK)));
2591
2592	#ifdef VBOX_STRICT
2593	/*
2594	* All of the guest-CPU state and SVM keeper bits should be exported here by now, except
2595	* for the host-context and/or shared host-guest context bits.
2596	*/
2597	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2598	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
2599	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2600	("fCtxChanged=%#RX64\n", fCtxChanged));
2601
2602	/*
2603	* If we need to log state that isn't always imported, we'll need to import them here.
2604	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2605	*/
2606	hmR0SvmLogState(pVCpu, pVmcbNstGst, "hmR0SvmExportGuestStateNested", 0 /* fFlags /, 0 / uVerbose */);
2607	#endif
2608
2609	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2610	return rc;
2611	}
2612	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
2613
2614
2615	/**
2616	* Exports the state shared between the host and guest (or nested-guest) into
2617	* the VMCB.
2618	*
2619	* @param pVCpu The cross context virtual CPU structure.
2620	* @param pVmcb Pointer to the VM control block.
2621	*
2622	* @remarks No-long-jump zone!!!
2623	*/
2624	static void hmR0SvmExportSharedState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2625	{
2626	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2627	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2628
2629	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
2630	{
2631	/** @todo Figure out stepping with nested-guest. */
2632	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2633	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2634	hmR0SvmExportSharedDebugState(pVCpu, pVmcb);
2635	else
2636	{
2637	pVmcb->guest.u64DR6 = pCtx->dr[6];
2638	pVmcb->guest.u64DR7 = pCtx->dr[7];
2639	}
2640	}
2641
2642	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
2643	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE),
2644	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
2645	}
2646
2647
2648	/**
2649	* Worker for SVMR0ImportStateOnDemand.
2650	*
2651	* @param pVCpu The cross context virtual CPU structure.
2652	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2653	*/
2654	static void hmR0SvmImportGuestState(PVMCPUCC pVCpu, uint64_t fWhat)
2655	{
2656	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
2657
2658	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2659	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2660	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
2661	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2662
2663	Log4Func(("fExtrn=%#RX64 fWhat=%#RX64\n", pCtx->fExtrn, fWhat));
2664
2665	/*
2666	* We disable interrupts to make the updating of the state and in particular
2667	* the fExtrn modification atomic wrt to preemption hooks.
2668	*/
2669	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2670
2671	fWhat &= pCtx->fExtrn;
2672	if (fWhat)
2673	{
2674	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2675	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
2676	{
2677	if (pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2678	{
2679	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); /* We don't yet support passing VGIF feature to the guest. */
2680	Assert(HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2681	CPUMSetGuestGif(pCtx, pVmcbCtrl->IntCtrl.n.u1VGif);
2682	}
2683	}
2684
2685	if (fWhat & CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
2686	{
2687	if ( !pVmcbCtrl->IntCtrl.n.u1VIrqPending
2688	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2689	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2690	}
2691	#endif
2692
2693	if (fWhat & CPUMCTX_EXTRN_HM_SVM_INT_SHADOW)
2694	{
2695	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2696	EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
2697	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2698	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2699	}
2700
2701	if (fWhat & CPUMCTX_EXTRN_RIP)
2702	pCtx->rip = pVmcbGuest->u64RIP;
2703
2704	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
2705	pCtx->eflags.u32 = pVmcbGuest->u64RFlags;
2706
2707	if (fWhat & CPUMCTX_EXTRN_RSP)
2708	pCtx->rsp = pVmcbGuest->u64RSP;
2709
2710	if (fWhat & CPUMCTX_EXTRN_RAX)
2711	pCtx->rax = pVmcbGuest->u64RAX;
2712
2713	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
2714	{
2715	if (fWhat & CPUMCTX_EXTRN_CS)
2716	{
2717	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, CS, cs);
2718	/* Correct the CS granularity bit. Haven't seen it being wrong in any other register (yet). */
2719	/** @todo SELM might need to be fixed as it too should not care about the
2720	* granularity bit. See @bugref{6785}. */
2721	if ( !pCtx->cs.Attr.n.u1Granularity
2722	&& pCtx->cs.Attr.n.u1Present
2723	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
2724	{
2725	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
2726	pCtx->cs.Attr.n.u1Granularity = 1;
2727	}
2728	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, cs);
2729	}
2730	if (fWhat & CPUMCTX_EXTRN_SS)
2731	{
2732	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, SS, ss);
2733	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ss);
2734	/*
2735	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the
2736	* VMCB and uses that and thus it's possible that when the CPL changes during
2737	* guest execution that the SS DPL isn't updated by AMD-V. Observed on some
2738	* AMD Fusion CPUs with 64-bit guests.
2739	*
2740	* See AMD spec. 15.5.1 "Basic operation".
2741	*/
2742	Assert(!(pVmcbGuest->u8CPL & ~0x3));
2743	uint8_t const uCpl = pVmcbGuest->u8CPL;
2744	if (pCtx->ss.Attr.n.u2Dpl != uCpl)
2745	pCtx->ss.Attr.n.u2Dpl = uCpl & 0x3;
2746	}
2747	if (fWhat & CPUMCTX_EXTRN_DS)
2748	{
2749	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, DS, ds);
2750	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ds);
2751	}
2752	if (fWhat & CPUMCTX_EXTRN_ES)
2753	{
2754	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, ES, es);
2755	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, es);
2756	}
2757	if (fWhat & CPUMCTX_EXTRN_FS)
2758	{
2759	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, FS, fs);
2760	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, fs);
2761	}
2762	if (fWhat & CPUMCTX_EXTRN_GS)
2763	{
2764	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, GS, gs);
2765	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, gs);
2766	}
2767	}
2768
2769	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
2770	{
2771	if (fWhat & CPUMCTX_EXTRN_TR)
2772	{
2773	/*
2774	* Fixup TR attributes so it's compatible with Intel. Important when saved-states
2775	* are used between Intel and AMD, see @bugref{6208#c39}.
2776	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2777	*/
2778	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, TR, tr);
2779	if (pCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2780	{
2781	if ( pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2782	\|\| CPUMIsGuestInLongModeEx(pCtx))
2783	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2784	else if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2785	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2786	}
2787	}
2788
2789	if (fWhat & CPUMCTX_EXTRN_LDTR)
2790	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, LDTR, ldtr);
2791
2792	if (fWhat & CPUMCTX_EXTRN_GDTR)
2793	{
2794	pCtx->gdtr.cbGdt = pVmcbGuest->GDTR.u32Limit;
2795	pCtx->gdtr.pGdt = pVmcbGuest->GDTR.u64Base;
2796	}
2797
2798	if (fWhat & CPUMCTX_EXTRN_IDTR)
2799	{
2800	pCtx->idtr.cbIdt = pVmcbGuest->IDTR.u32Limit;
2801	pCtx->idtr.pIdt = pVmcbGuest->IDTR.u64Base;
2802	}
2803	}
2804
2805	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
2806	{
2807	pCtx->msrSTAR = pVmcbGuest->u64STAR;
2808	pCtx->msrLSTAR = pVmcbGuest->u64LSTAR;
2809	pCtx->msrCSTAR = pVmcbGuest->u64CSTAR;
2810	pCtx->msrSFMASK = pVmcbGuest->u64SFMASK;
2811	}
2812
2813	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
2814	{
2815	pCtx->SysEnter.cs = pVmcbGuest->u64SysEnterCS;
2816	pCtx->SysEnter.eip = pVmcbGuest->u64SysEnterEIP;
2817	pCtx->SysEnter.esp = pVmcbGuest->u64SysEnterESP;
2818	}
2819
2820	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
2821	pCtx->msrKERNELGSBASE = pVmcbGuest->u64KernelGSBase;
2822
2823	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
2824	{
2825	if (fWhat & CPUMCTX_EXTRN_DR6)
2826	{
2827	if (!pVCpu->hm.s.fUsingHyperDR7)
2828	pCtx->dr[6] = pVmcbGuest->u64DR6;
2829	else
2830	CPUMSetHyperDR6(pVCpu, pVmcbGuest->u64DR6);
2831	}
2832
2833	if (fWhat & CPUMCTX_EXTRN_DR7)
2834	{
2835	if (!pVCpu->hm.s.fUsingHyperDR7)
2836	pCtx->dr[7] = pVmcbGuest->u64DR7;
2837	else
2838	Assert(pVmcbGuest->u64DR7 == CPUMGetHyperDR7(pVCpu));
2839	}
2840	}
2841
2842	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
2843	{
2844	if (fWhat & CPUMCTX_EXTRN_CR0)
2845	{
2846	/* We intercept changes to all CR0 bits except maybe TS & MP bits. */
2847	uint64_t const uCr0 = (pCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2848	\| (pVmcbGuest->u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2849	VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
2850	CPUMSetGuestCR0(pVCpu, uCr0);
2851	VMMRZCallRing3Enable(pVCpu);
2852	}
2853
2854	if (fWhat & CPUMCTX_EXTRN_CR2)
2855	pCtx->cr2 = pVmcbGuest->u64CR2;
2856
2857	if (fWhat & CPUMCTX_EXTRN_CR3)
2858	{
2859	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2860	&& pCtx->cr3 != pVmcbGuest->u64CR3)
2861	{
2862	CPUMSetGuestCR3(pVCpu, pVmcbGuest->u64CR3);
2863	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2864	}
2865	}
2866
2867	/* Changes to CR4 are always intercepted. */
2868	}
2869
2870	/* Update fExtrn. */
2871	pCtx->fExtrn &= ~fWhat;
2872
2873	/* If everything has been imported, clear the HM keeper bit. */
2874	if (!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL))
2875	{
2876	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
2877	Assert(!pCtx->fExtrn);
2878	}
2879	}
2880	else
2881	Assert(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
2882
2883	ASMSetFlags(fEFlags);
2884
2885	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
2886
2887	/*
2888	* Honor any pending CR3 updates.
2889	*
2890	* Consider this scenario: #VMEXIT -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp
2891	* -> hmR0SvmCallRing3Callback() -> VMMRZCallRing3Disable() -> hmR0SvmImportGuestState()
2892	* -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp -> continue with #VMEXIT
2893	* handling -> hmR0SvmImportGuestState() and here we are.
2894	*
2895	* The reason for such complicated handling is because VM-exits that call into PGM expect
2896	* CR3 to be up-to-date and thus any CR3-saves -before- the VM-exit (longjmp) would've
2897	* postponed the CR3 update via the force-flag and cleared CR3 from fExtrn. Any SVM R0
2898	* VM-exit handler that requests CR3 to be saved will end up here and we call PGMUpdateCR3().
2899	*
2900	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again,
2901	* and does not process force-flag like regular exits to ring-3 either, we cover for it here.
2902	*/
2903	if ( VMMRZCallRing3IsEnabled(pVCpu)
2904	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
2905	{
2906	Assert(pCtx->cr3 == pVmcbGuest->u64CR3);
2907	PGMUpdateCR3(pVCpu, pCtx->cr3);
2908	}
2909	}
2910
2911
2912	/**
2913	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2914	* context.
2915	*
2916	* Currently there is no residual state left in the CPU that is not updated in the
2917	* VMCB.
2918	*
2919	* @returns VBox status code.
2920	* @param pVCpu The cross context virtual CPU structure.
2921	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2922	*/
2923	VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2924	{
2925	hmR0SvmImportGuestState(pVCpu, fWhat);
2926	return VINF_SUCCESS;
2927	}
2928
2929
2930	/**
2931	* Does the necessary state syncing before returning to ring-3 for any reason
2932	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2933	*
2934	* @param pVCpu The cross context virtual CPU structure.
2935	* @param fImportState Whether to import the guest state from the VMCB back
2936	* to the guest-CPU context.
2937	*
2938	* @remarks No-long-jmp zone!!!
2939	*/
2940	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState)
2941	{
2942	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2943	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2944	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2945
2946	/*
2947	* !!! IMPORTANT !!!
2948	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2949	*/
2950
2951	/* Save the guest state if necessary. */
2952	if (fImportState)
2953	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
2954
2955	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2956	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2957	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
2958
2959	/*
2960	* Restore host debug registers if necessary and resync on next R0 reentry.
2961	*/
2962	#ifdef VBOX_STRICT
2963	if (CPUMIsHyperDebugStateActive(pVCpu))
2964	{
2965	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
2966	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2967	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2968	}
2969	#endif
2970	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2971	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2972	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2973
2974	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2975	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
2976	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
2977	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
2978	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
2979	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitVmentry);
2980	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2981
2982	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2983	}
2984
2985
2986	/**
2987	* Leaves the AMD-V session.
2988	*
2989	* Only used while returning to ring-3 either due to longjump or exits to
2990	* ring-3.
2991	*
2992	* @returns VBox status code.
2993	* @param pVCpu The cross context virtual CPU structure.
2994	*/
2995	static int hmR0SvmLeaveSession(PVMCPUCC pVCpu)
2996	{
2997	HM_DISABLE_PREEMPT(pVCpu);
2998	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2999	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3000
3001	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
3002	and done this from the SVMR0ThreadCtxCallback(). */
3003	if (!pVCpu->hm.s.fLeaveDone)
3004	{
3005	hmR0SvmLeave(pVCpu, true /* fImportState */);
3006	pVCpu->hm.s.fLeaveDone = true;
3007	}
3008
3009	/*
3010	* !!! IMPORTANT !!!
3011	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
3012	*/
3013
3014	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3015	/* Deregister hook now that we've left HM context before re-enabling preemption. */
3016	VMMR0ThreadCtxHookDisable(pVCpu);
3017
3018	/* Leave HM context. This takes care of local init (term). */
3019	int rc = HMR0LeaveCpu(pVCpu);
3020
3021	HM_RESTORE_PREEMPT();
3022	return rc;
3023	}
3024
3025
3026	/**
3027	* Does the necessary state syncing before doing a longjmp to ring-3.
3028	*
3029	* @returns VBox status code.
3030	* @param pVCpu The cross context virtual CPU structure.
3031	*
3032	* @remarks No-long-jmp zone!!!
3033	*/
3034	static int hmR0SvmLongJmpToRing3(PVMCPUCC pVCpu)
3035	{
3036	return hmR0SvmLeaveSession(pVCpu);
3037	}
3038
3039
3040	/**
3041	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
3042	* any remaining host state) before we longjump to ring-3 and possibly get
3043	* preempted.
3044	*
3045	* @param pVCpu The cross context virtual CPU structure.
3046	* @param enmOperation The operation causing the ring-3 longjump.
3047	* @param pvUser The user argument, NULL (currently unused).
3048	*/
3049	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
3050	{
3051	RT_NOREF_PV(pvUser);
3052
3053	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
3054	{
3055	/*
3056	* !!! IMPORTANT !!!
3057	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
3058	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
3059	*/
3060	VMMRZCallRing3RemoveNotification(pVCpu);
3061	VMMRZCallRing3Disable(pVCpu);
3062	HM_DISABLE_PREEMPT(pVCpu);
3063
3064	/* Import the entire guest state. */
3065	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3066
3067	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3068	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3069
3070	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3071	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3072
3073	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3074	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3075	VMMR0ThreadCtxHookDisable(pVCpu);
3076
3077	/* Leave HM context. This takes care of local init (term). */
3078	HMR0LeaveCpu(pVCpu);
3079
3080	HM_RESTORE_PREEMPT();
3081	return VINF_SUCCESS;
3082	}
3083
3084	Assert(pVCpu);
3085	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3086	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3087
3088	VMMRZCallRing3Disable(pVCpu);
3089	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3090
3091	Log4Func(("Calling hmR0SvmLongJmpToRing3\n"));
3092	int rc = hmR0SvmLongJmpToRing3(pVCpu);
3093	AssertRCReturn(rc, rc);
3094
3095	VMMRZCallRing3Enable(pVCpu);
3096	return VINF_SUCCESS;
3097	}
3098
3099
3100	/**
3101	* Take necessary actions before going back to ring-3.
3102	*
3103	* An action requires us to go back to ring-3. This function does the necessary
3104	* steps before we can safely return to ring-3. This is not the same as longjmps
3105	* to ring-3, this is voluntary.
3106	*
3107	* @returns VBox status code.
3108	* @param pVCpu The cross context virtual CPU structure.
3109	* @param rcExit The reason for exiting to ring-3. Can be
3110	* VINF_VMM_UNKNOWN_RING3_CALL.
3111	*/
3112	static int hmR0SvmExitToRing3(PVMCPUCC pVCpu, int rcExit)
3113	{
3114	Assert(pVCpu);
3115	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3116
3117	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3118	VMMRZCallRing3Disable(pVCpu);
3119	Log4Func(("rcExit=%d LocalFF=%#RX64 GlobalFF=%#RX32\n", rcExit, (uint64_t)pVCpu->fLocalForcedActions,
3120	pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
3121
3122	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3123	if (pVCpu->hm.s.Event.fPending)
3124	{
3125	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3126	Assert(!pVCpu->hm.s.Event.fPending);
3127	}
3128
3129	/* Sync. the necessary state for going back to ring-3. */
3130	hmR0SvmLeaveSession(pVCpu);
3131	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3132
3133	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3134	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3135	\| CPUM_CHANGED_LDTR
3136	\| CPUM_CHANGED_GDTR
3137	\| CPUM_CHANGED_IDTR
3138	\| CPUM_CHANGED_TR
3139	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3140	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
3141	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
3142	{
3143	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3144	}
3145
3146	/* Update the exit-to-ring 3 reason. */
3147	pVCpu->hm.s.rcLastExitToR3 = rcExit;
3148
3149	/* On our way back from ring-3, reload the guest-CPU state if it may change while in ring-3. */
3150	if ( rcExit != VINF_EM_RAW_INTERRUPT
3151	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3152	{
3153	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3154	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3155	}
3156
3157	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3158
3159	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
3160	VMMRZCallRing3RemoveNotification(pVCpu);
3161	VMMRZCallRing3Enable(pVCpu);
3162
3163	/*
3164	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3165	* and if we're injecting an event we should have a TRPM trap pending.
3166	*/
3167	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3168	pVCpu->hm.s.u32HMError = rcExit,
3169	VERR_SVM_IPE_5);
3170	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3171	pVCpu->hm.s.u32HMError = rcExit,
3172	VERR_SVM_IPE_4);
3173
3174	return rcExit;
3175	}
3176
3177
3178	/**
3179	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3180	* intercepts.
3181	*
3182	* @param pVCpu The cross context virtual CPU structure.
3183	* @param pVmcb Pointer to the VM control block.
3184	*
3185	* @remarks No-long-jump zone!!!
3186	*/
3187	static void hmR0SvmUpdateTscOffsetting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3188	{
3189	/*
3190	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3191	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3192	* RDTSC/RDTSCP as well.
3193	*/
3194	bool fParavirtTsc;
3195	uint64_t uTscOffset;
3196	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
3197
3198	bool fIntercept;
3199	if (fCanUseRealTsc)
3200	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3201	else
3202	{
3203	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3204	fIntercept = true;
3205	}
3206
3207	if (!fIntercept)
3208	{
3209	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3210	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3211	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3212	uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset);
3213	#endif
3214
3215	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3216	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3217	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3218	}
3219
3220	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3221	information before every VM-entry, hence we have nothing to do here at the moment. */
3222	if (fParavirtTsc)
3223	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3224	}
3225
3226
3227	/**
3228	* Sets an event as a pending event to be injected into the guest.
3229	*
3230	* @param pVCpu The cross context virtual CPU structure.
3231	* @param pEvent Pointer to the SVM event.
3232	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3233	* page-fault.
3234	*
3235	* @remarks Statistics counter assumes this is a guest event being reflected to
3236	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3237	*/
3238	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPUCC pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3239	{
3240	Assert(!pVCpu->hm.s.Event.fPending);
3241	Assert(pEvent->n.u1Valid);
3242
3243	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3244	pVCpu->hm.s.Event.fPending = true;
3245	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3246
3247	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3248	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3249	}
3250
3251
3252	/**
3253	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3254	*
3255	* @param pVCpu The cross context virtual CPU structure.
3256	*/
3257	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPUCC pVCpu)
3258	{
3259	SVMEVENT Event;
3260	Event.u = 0;
3261	Event.n.u1Valid = 1;
3262	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3263	Event.n.u8Vector = X86_XCPT_UD;
3264	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3265	}
3266
3267
3268	/**
3269	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3270	*
3271	* @param pVCpu The cross context virtual CPU structure.
3272	*/
3273	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPUCC pVCpu)
3274	{
3275	SVMEVENT Event;
3276	Event.u = 0;
3277	Event.n.u1Valid = 1;
3278	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3279	Event.n.u8Vector = X86_XCPT_DB;
3280	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3281	}
3282
3283
3284	/**
3285	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3286	*
3287	* @param pVCpu The cross context virtual CPU structure.
3288	* @param u32ErrCode The error-code for the page-fault.
3289	* @param uFaultAddress The page fault address (CR2).
3290	*
3291	* @remarks This updates the guest CR2 with @a uFaultAddress!
3292	*/
3293	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPUCC pVCpu, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3294	{
3295	SVMEVENT Event;
3296	Event.u = 0;
3297	Event.n.u1Valid = 1;
3298	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3299	Event.n.u8Vector = X86_XCPT_PF;
3300	Event.n.u1ErrorCodeValid = 1;
3301	Event.n.u32ErrorCode = u32ErrCode;
3302
3303	/* Update CR2 of the guest. */
3304	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR2);
3305	if (pVCpu->cpum.GstCtx.cr2 != uFaultAddress)
3306	{
3307	pVCpu->cpum.GstCtx.cr2 = uFaultAddress;
3308	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3309	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
3310	}
3311
3312	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3313	}
3314
3315
3316	/**
3317	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3318	*
3319	* @param pVCpu The cross context virtual CPU structure.
3320	*/
3321	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPUCC pVCpu)
3322	{
3323	SVMEVENT Event;
3324	Event.u = 0;
3325	Event.n.u1Valid = 1;
3326	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3327	Event.n.u8Vector = X86_XCPT_MF;
3328	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3329	}
3330
3331
3332	/**
3333	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3334	*
3335	* @param pVCpu The cross context virtual CPU structure.
3336	*/
3337	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPUCC pVCpu)
3338	{
3339	SVMEVENT Event;
3340	Event.u = 0;
3341	Event.n.u1Valid = 1;
3342	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3343	Event.n.u8Vector = X86_XCPT_DF;
3344	Event.n.u1ErrorCodeValid = 1;
3345	Event.n.u32ErrorCode = 0;
3346	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3347	}
3348
3349
3350	/**
3351	* Injects an event into the guest upon VMRUN by updating the relevant field
3352	* in the VMCB.
3353	*
3354	* @param pVCpu The cross context virtual CPU structure.
3355	* @param pVmcb Pointer to the guest VM control block.
3356	* @param pEvent Pointer to the event.
3357	*
3358	* @remarks No-long-jump zone!!!
3359	* @remarks Requires CR0!
3360	*/
3361	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMEVENT pEvent)
3362	{
3363	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3364	pVmcb->ctrl.EventInject.u = pEvent->u;
3365	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3366	RT_NOREF(pVCpu);
3367
3368	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3369	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3370	}
3371
3372
3373
3374	/**
3375	* Converts any TRPM trap into a pending HM event. This is typically used when
3376	* entering from ring-3 (not longjmp returns).
3377	*
3378	* @param pVCpu The cross context virtual CPU structure.
3379	*/
3380	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPUCC pVCpu)
3381	{
3382	Assert(TRPMHasTrap(pVCpu));
3383	Assert(!pVCpu->hm.s.Event.fPending);
3384
3385	uint8_t uVector;
3386	TRPMEVENT enmTrpmEvent;
3387	RTGCUINT uErrCode;
3388	RTGCUINTPTR GCPtrFaultAddress;
3389	uint8_t cbInstr;
3390
3391	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
3392	AssertRC(rc);
3393
3394	SVMEVENT Event;
3395	Event.u = 0;
3396	Event.n.u1Valid = 1;
3397	Event.n.u8Vector = uVector;
3398
3399	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3400	if (enmTrpmEvent == TRPM_TRAP)
3401	{
3402	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3403	switch (uVector)
3404	{
3405	case X86_XCPT_NMI:
3406	{
3407	Event.n.u3Type = SVM_EVENT_NMI;
3408	break;
3409	}
3410
3411	case X86_XCPT_BP:
3412	case X86_XCPT_OF:
3413	AssertMsgFailed(("Invalid TRPM vector %d for event type %d\n", uVector, enmTrpmEvent));
3414	RT_FALL_THRU();
3415
3416	case X86_XCPT_PF:
3417	case X86_XCPT_DF:
3418	case X86_XCPT_TS:
3419	case X86_XCPT_NP:
3420	case X86_XCPT_SS:
3421	case X86_XCPT_GP:
3422	case X86_XCPT_AC:
3423	{
3424	Event.n.u1ErrorCodeValid = 1;
3425	Event.n.u32ErrorCode = uErrCode;
3426	break;
3427	}
3428	}
3429	}
3430	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3431	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3432	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3433	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3434	else
3435	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3436
3437	rc = TRPMResetTrap(pVCpu);
3438	AssertRC(rc);
3439
3440	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3441	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3442
3443	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3444	}
3445
3446
3447	/**
3448	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3449	* AMD-V to execute any instruction.
3450	*
3451	* @param pVCpu The cross context virtual CPU structure.
3452	*/
3453	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu)
3454	{
3455	Assert(pVCpu->hm.s.Event.fPending);
3456	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3457
3458	SVMEVENT Event;
3459	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3460
3461	uint8_t uVector = Event.n.u8Vector;
3462	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event, uVector);
3463
3464	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, Event.n.u3Type));
3465
3466	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3467	AssertRC(rc);
3468
3469	if (Event.n.u1ErrorCodeValid)
3470	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3471
3472	if ( enmTrapType == TRPM_TRAP
3473	&& uVector == X86_XCPT_PF)
3474	{
3475	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3476	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3477	}
3478	else if (enmTrapType == TRPM_SOFTWARE_INT)
3479	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3480	pVCpu->hm.s.Event.fPending = false;
3481	}
3482
3483
3484	/**
3485	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3486	* now.
3487	*
3488	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3489	* @param pVCpu The cross context virtual CPU structure.
3490	*
3491	* @remarks No-long-jump zone!!!
3492	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3493	*/
3494	static bool hmR0SvmIsIntrShadowActive(PVMCPUCC pVCpu)
3495	{
3496	/*
3497	* Instructions like STI and MOV SS inhibit interrupts till the next instruction
3498	* completes. Check if we should inhibit interrupts or clear any existing
3499	* interrupt inhibition.
3500	*/
3501	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3502	{
3503	if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
3504	{
3505	/*
3506	* We can clear the inhibit force flag as even if we go back to the recompiler
3507	* without executing guest code in AMD-V, the flag's condition to be cleared is
3508	* met and thus the cleared state is correct.
3509	*/
3510	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3511	return false;
3512	}
3513	return true;
3514	}
3515	return false;
3516	}
3517
3518
3519	/**
3520	* Sets the virtual interrupt intercept control in the VMCB.
3521	*
3522	* @param pVCpu The cross context virtual CPU structure.
3523	* @param pVmcb Pointer to the VM control block.
3524	*/
3525	static void hmR0SvmSetIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3526	{
3527	/*
3528	* When AVIC isn't supported, set up an interrupt window to cause a #VMEXIT when the guest
3529	* is ready to accept interrupts. At #VMEXIT, we then get the interrupt from the APIC
3530	* (updating ISR at the right time) and inject the interrupt.
3531	*
3532	* With AVIC is supported, we could make use of the asynchronously delivery without
3533	* #VMEXIT and we would be passing the AVIC page to SVM.
3534	*
3535	* In AMD-V, an interrupt window is achieved using a combination of V_IRQ (an interrupt
3536	* is pending), V_IGN_TPR (ignore TPR priorities) and the VINTR intercept all being set.
3537	*/
3538	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3539	/*
3540	* Currently we don't overlay interupt windows and if there's any V_IRQ pending in the
3541	* nested-guest VMCB, we avoid setting up any interrupt window on behalf of the outer
3542	* guest.
3543	*/
3544	/** @todo Does this mean we end up prioritizing virtual interrupt
3545	* delivery/window over a physical interrupt (from the outer guest)
3546	* might be pending? */
3547	bool const fEnableIntWindow = !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
3548	if (!fEnableIntWindow)
3549	{
3550	Assert(CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx));
3551	Log4(("Nested-guest V_IRQ already pending\n"));
3552	}
3553	#else
3554	bool const fEnableIntWindow = true;
3555	RT_NOREF(pVCpu);
3556	#endif
3557	if (fEnableIntWindow)
3558	{
3559	Assert(pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR);
3560	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3561	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3562	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3563	Log4(("Set VINTR intercept\n"));
3564	}
3565	}
3566
3567
3568	/**
3569	* Clears the virtual interrupt intercept control in the VMCB as
3570	* we are figured the guest is unable process any interrupts
3571	* at this point of time.
3572	*
3573	* @param pVCpu The cross context virtual CPU structure.
3574	* @param pVmcb Pointer to the VM control block.
3575	*/
3576	static void hmR0SvmClearIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3577	{
3578	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
3579	if ( pVmcbCtrl->IntCtrl.n.u1VIrqPending
3580	\|\| (pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3581	{
3582	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
3583	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3584	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3585	Log4(("Cleared VINTR intercept\n"));
3586	}
3587	}
3588
3589	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3590	/**
3591	* Evaluates the event to be delivered to the nested-guest and sets it as the
3592	* pending event.
3593	*
3594	* @returns VBox strict status code.
3595	* @param pVCpu The cross context virtual CPU structure.
3596	*/
3597	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPUCC pVCpu)
3598	{
3599	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3600	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
3601	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3602	\| CPUMCTX_EXTRN_RFLAGS
3603	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
3604	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ);
3605
3606	Assert(!pVCpu->hm.s.Event.fPending);
3607	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3608	Assert(pVmcb);
3609
3610	bool const fGif = CPUMGetGuestGif(pCtx);
3611	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3612	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3613
3614	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
3615	fGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3616	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3617
3618	/** @todo SMI. SMIs take priority over NMIs. */
3619
3620	/*
3621	* Check if the guest can receive NMIs.
3622	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3623	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3624	*/
3625	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3626	&& !fBlockNmi)
3627	{
3628	if ( fGif
3629	&& !fIntShadow)
3630	{
3631	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3632	{
3633	Log4(("Intercepting NMI -> #VMEXIT\n"));
3634	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3635	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3636	}
3637
3638	Log4(("Setting NMI pending for injection\n"));
3639	SVMEVENT Event;
3640	Event.u = 0;
3641	Event.n.u1Valid = 1;
3642	Event.n.u8Vector = X86_XCPT_NMI;
3643	Event.n.u3Type = SVM_EVENT_NMI;
3644	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3645	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3646	}
3647	else if (!fGif)
3648	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3649	else
3650	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3651	}
3652	/*
3653	* Check if the nested-guest can receive external interrupts (generated by the guest's
3654	* PIC/APIC).
3655	*
3656	* External intercepts, NMI, SMI etc. from the physical CPU are -always- intercepted
3657	* when executing using hardware-assisted SVM, see HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS.
3658	*
3659	* External interrupts that are generated for the outer guest may be intercepted
3660	* depending on how the nested-guest VMCB was programmed by guest software.
3661	*
3662	* Physical interrupts always take priority over virtual interrupts,
3663	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3664	*
3665	* We don't need to inject nested-guest virtual interrupts here, we can let the hardware
3666	* do that work when we execute nested guest code esp. since all the required information
3667	* is in the VMCB, unlike physical interrupts where we need to fetch the interrupt from
3668	* the virtual interrupt controller.
3669	*/
3670	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3671	&& !pVCpu->hm.s.fSingleInstruction)
3672	{
3673	if ( fGif
3674	&& !fIntShadow
3675	&& CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx))
3676	{
3677	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3678	{
3679	Log4(("Intercepting INTR -> #VMEXIT\n"));
3680	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3681	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3682	}
3683
3684	uint8_t u8Interrupt;
3685	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3686	if (RT_SUCCESS(rc))
3687	{
3688	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3689	SVMEVENT Event;
3690	Event.u = 0;
3691	Event.n.u1Valid = 1;
3692	Event.n.u8Vector = u8Interrupt;
3693	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3694	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3695	}
3696	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3697	{
3698	/*
3699	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3700	* updated eventually when the TPR is written by the guest.
3701	*/
3702	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3703	}
3704	else
3705	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3706	}
3707	else if (!fGif)
3708	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3709	else
3710	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3711	}
3712
3713	return VINF_SUCCESS;
3714	}
3715	#endif
3716
3717	/**
3718	* Evaluates the event to be delivered to the guest and sets it as the pending
3719	* event.
3720	*
3721	* @param pVCpu The cross context virtual CPU structure.
3722	*/
3723	static void hmR0SvmEvaluatePendingEvent(PVMCPUCC pVCpu)
3724	{
3725	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3726	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3727	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3728	\| CPUMCTX_EXTRN_RFLAGS
3729	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW);
3730
3731	Assert(!pVCpu->hm.s.Event.fPending);
3732	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3733	Assert(pVmcb);
3734
3735	bool const fGif = CPUMGetGuestGif(pCtx);
3736	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3737	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3738	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3739
3740	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool fIntPending=%RTbool NMI pending=%RTbool\n",
3741	fGif, fBlockNmi, fBlockInt, fIntShadow,
3742	VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3743	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3744
3745	/** @todo SMI. SMIs take priority over NMIs. */
3746
3747	/*
3748	* Check if the guest can receive NMIs.
3749	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3750	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3751	*/
3752	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3753	&& !fBlockNmi)
3754	{
3755	if ( fGif
3756	&& !fIntShadow)
3757	{
3758	Log4(("Setting NMI pending for injection\n"));
3759	SVMEVENT Event;
3760	Event.u = 0;
3761	Event.n.u1Valid = 1;
3762	Event.n.u8Vector = X86_XCPT_NMI;
3763	Event.n.u3Type = SVM_EVENT_NMI;
3764	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3765	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3766	}
3767	else if (!fGif)
3768	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3769	else
3770	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3771	}
3772	/*
3773	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt()
3774	* returns a valid interrupt we -must- deliver the interrupt. We can no longer re-request
3775	* it from the APIC device.
3776	*/
3777	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3778	&& !pVCpu->hm.s.fSingleInstruction)
3779	{
3780	if ( fGif
3781	&& !fBlockInt
3782	&& !fIntShadow)
3783	{
3784	uint8_t u8Interrupt;
3785	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3786	if (RT_SUCCESS(rc))
3787	{
3788	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3789	SVMEVENT Event;
3790	Event.u = 0;
3791	Event.n.u1Valid = 1;
3792	Event.n.u8Vector = u8Interrupt;
3793	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3794	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3795	}
3796	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3797	{
3798	/*
3799	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3800	* updated eventually when the TPR is written by the guest.
3801	*/
3802	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3803	}
3804	else
3805	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3806	}
3807	else if (!fGif)
3808	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3809	else
3810	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3811	}
3812	}
3813
3814
3815	/**
3816	* Injects any pending events into the guest (or nested-guest).
3817	*
3818	* @param pVCpu The cross context virtual CPU structure.
3819	* @param pVmcb Pointer to the VM control block.
3820	*
3821	* @remarks Must only be called when we are guaranteed to enter
3822	* hardware-assisted SVM execution and not return to ring-3
3823	* prematurely.
3824	*/
3825	static void hmR0SvmInjectPendingEvent(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3826	{
3827	Assert(!TRPMHasTrap(pVCpu));
3828	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3829
3830	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3831	#ifdef VBOX_STRICT
3832	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3833	bool const fGif = CPUMGetGuestGif(pCtx);
3834	bool fAllowInt = fGif;
3835	if (fGif)
3836	{
3837	/*
3838	* For nested-guests we have no way to determine if we're injecting a physical or
3839	* virtual interrupt at this point. Hence the partial verification below.
3840	*/
3841	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3842	fAllowInt = CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx) \|\| CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
3843	else
3844	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3845	}
3846	#endif
3847
3848	if (pVCpu->hm.s.Event.fPending)
3849	{
3850	SVMEVENT Event;
3851	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3852	Assert(Event.n.u1Valid);
3853
3854	/*
3855	* Validate event injection pre-conditions.
3856	*/
3857	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3858	{
3859	Assert(fAllowInt);
3860	Assert(!fIntShadow);
3861	}
3862	else if (Event.n.u3Type == SVM_EVENT_NMI)
3863	{
3864	Assert(fGif);
3865	Assert(!fIntShadow);
3866	}
3867
3868	/*
3869	* Before injecting an NMI we must set VMCPU_FF_BLOCK_NMIS to prevent nested NMIs. We
3870	* do this only when we are surely going to inject the NMI as otherwise if we return
3871	* to ring-3 prematurely we could leave NMIs blocked indefinitely upon re-entry into
3872	* SVM R0.
3873	*
3874	* With VT-x, this is handled by the Guest interruptibility information VMCS field
3875	* which will set the VMCS field after actually delivering the NMI which we read on
3876	* VM-exit to determine the state.
3877	*/
3878	if ( Event.n.u3Type == SVM_EVENT_NMI
3879	&& Event.n.u8Vector == X86_XCPT_NMI
3880	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3881	{
3882	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3883	}
3884
3885	/*
3886	* Inject it (update VMCB for injection by the hardware).
3887	*/
3888	Log4(("Injecting pending HM event\n"));
3889	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, &Event);
3890	pVCpu->hm.s.Event.fPending = false;
3891
3892	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3893	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3894	else
3895	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3896	}
3897	else
3898	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3899
3900	/*
3901	* We could have injected an NMI through IEM and continue guest execution using
3902	* hardware-assisted SVM. In which case, we would not have any events pending (above)
3903	* but we still need to intercept IRET in order to eventually clear NMI inhibition.
3904	*/
3905	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3906	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
3907
3908	/*
3909	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
3910	*
3911	* For nested-guests: We need to update it too for the scenario where IEM executes
3912	* the nested-guest but execution later continues here with an interrupt shadow active.
3913	*/
3914	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3915	}
3916
3917
3918	/**
3919	* Reports world-switch error and dumps some useful debug info.
3920	*
3921	* @param pVCpu The cross context virtual CPU structure.
3922	* @param rcVMRun The return code from VMRUN (or
3923	* VERR_SVM_INVALID_GUEST_STATE for invalid
3924	* guest-state).
3925	*/
3926	static void hmR0SvmReportWorldSwitchError(PVMCPUCC pVCpu, int rcVMRun)
3927	{
3928	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3929	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
3930	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3931
3932	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3933	{
3934	#ifdef VBOX_STRICT
3935	hmR0DumpRegs(pVCpu, HM_DUMP_REG_FLAGS_ALL);
3936	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3937	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3938	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3939	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3940	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3941	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3942	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3943	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3944	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3945	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3946	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3947
3948	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3949	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3950	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3951
3952	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3953	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3954	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3955	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3956	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3957	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3958	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3959	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3960	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3961	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
3962	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3963	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3964
3965	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3966	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3967	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3968	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3969	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3970	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3971	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3972	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3973	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3974	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3975	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3976	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
3977	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
3978	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
3979	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3980	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3981	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3982	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3983	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3984	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3985
3986	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3987
3988	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3989	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3990
3991	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3992	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3993	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3994	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3995	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3996	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3997	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3998	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3999	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
4000	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
4001	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
4002	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
4003	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
4004	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
4005	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
4006	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
4007	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
4008	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
4009	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
4010	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
4011
4012	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
4013	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
4014
4015	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
4016	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
4017	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
4018	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
4019
4020	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
4021	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
4022
4023	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
4024	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
4025	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
4026	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
4027
4028	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
4029	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
4030	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
4031	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
4032	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
4033	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
4034	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
4035
4036	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
4037	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
4038	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
4039	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
4040
4041	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
4042	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
4043	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
4044
4045	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
4046	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
4047	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
4048	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
4049	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
4050	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
4051	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
4052	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
4053	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
4054	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
4055	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
4056	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
4057
4058	NOREF(pVmcb);
4059	#endif /* VBOX_STRICT */
4060	}
4061	else
4062	Log4Func(("rcVMRun=%d\n", rcVMRun));
4063	}
4064
4065
4066	/**
4067	* Check per-VM and per-VCPU force flag actions that require us to go back to
4068	* ring-3 for one reason or another.
4069	*
4070	* @returns VBox status code (information status code included).
4071	* @retval VINF_SUCCESS if we don't have any actions that require going back to
4072	* ring-3.
4073	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
4074	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
4075	* interrupts)
4076	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
4077	* all EMTs to be in ring-3.
4078	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
4079	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
4080	* to the EM loop.
4081	*
4082	* @param pVCpu The cross context virtual CPU structure.
4083	*/
4084	static int hmR0SvmCheckForceFlags(PVMCPUCC pVCpu)
4085	{
4086	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4087	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
4088
4089	/* Could happen as a result of longjump. */
4090	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
4091	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
4092
4093	/* Update pending interrupts into the APIC's IRR. */
4094	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
4095	APICUpdatePendingInterrupts(pVCpu);
4096
4097	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4098	if ( VM_FF_IS_ANY_SET(pVM, !pVCpu->hm.s.fSingleInstruction
4099	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
4100	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, !pVCpu->hm.s.fSingleInstruction
4101	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
4102	{
4103	/* Pending PGM C3 sync. */
4104	if (VMCPU_FF_IS_ANY_SET(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
4105	{
4106	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
4107	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4108	if (rc != VINF_SUCCESS)
4109	{
4110	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
4111	return rc;
4112	}
4113	}
4114
4115	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
4116	/* -XXX- what was that about single stepping? */
4117	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
4118	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4119	{
4120	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4121	int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
4122	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
4123	return rc;
4124	}
4125
4126	/* Pending VM request packets, such as hardware interrupts. */
4127	if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
4128	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
4129	{
4130	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchVmReq);
4131	Log4Func(("Pending VM request forcing us back to ring-3\n"));
4132	return VINF_EM_PENDING_REQUEST;
4133	}
4134
4135	/* Pending PGM pool flushes. */
4136	if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
4137	{
4138	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPgmPoolFlush);
4139	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
4140	return VINF_PGM_POOL_FLUSH_PENDING;
4141	}
4142
4143	/* Pending DMA requests. */
4144	if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
4145	{
4146	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchDma);
4147	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
4148	return VINF_EM_RAW_TO_R3;
4149	}
4150	}
4151
4152	return VINF_SUCCESS;
4153	}
4154
4155
4156	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4157	/**
4158	* Does the preparations before executing nested-guest code in AMD-V.
4159	*
4160	* @returns VBox status code (informational status codes included).
4161	* @retval VINF_SUCCESS if we can proceed with running the guest.
4162	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4163	*
4164	* @param pVCpu The cross context virtual CPU structure.
4165	* @param pSvmTransient Pointer to the SVM transient structure.
4166	*
4167	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
4168	* @sa hmR0SvmPreRunGuest.
4169	*/
4170	static int hmR0SvmPreRunGuestNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4171	{
4172	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4173	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4174	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4175
4176	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
4177	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx)) /* Redundant check to avoid unreachable code warning. */
4178	{
4179	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4180	return VINF_EM_RESCHEDULE_REM;
4181	}
4182	#endif
4183
4184	/* Check force flag actions that might require us to go back to ring-3. */
4185	int rc = hmR0SvmCheckForceFlags(pVCpu);
4186	if (rc != VINF_SUCCESS)
4187	return rc;
4188
4189	if (TRPMHasTrap(pVCpu))
4190	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4191	else if (!pVCpu->hm.s.Event.fPending)
4192	{
4193	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu);
4194	if ( rcStrict != VINF_SUCCESS
4195	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4196	return VBOXSTRICTRC_VAL(rcStrict);
4197	}
4198
4199	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4200
4201	/*
4202	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4203	* Just do it in software, see @bugref{8411}.
4204	* NB: If we could continue a task switch exit we wouldn't need to do this.
4205	*/
4206	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4207	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
4208	&& pVCpu->hm.s.Event.fPending
4209	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4210	{
4211	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4212	}
4213
4214	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4215	Assert(!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4216	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4217	#endif
4218
4219	/*
4220	* Export the nested-guest state bits that are not shared with the host in any way as we
4221	* can longjmp or get preempted in the midst of exporting some of the state.
4222	*/
4223	rc = hmR0SvmExportGuestStateNested(pVCpu);
4224	AssertRCReturn(rc, rc);
4225	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4226
4227	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware-assisted SVM. */
4228	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
4229
4230	/*
4231	* No longjmps to ring-3 from this point on!!!
4232	*
4233	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4234	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4235	*/
4236	VMMRZCallRing3Disable(pVCpu);
4237
4238	/*
4239	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4240	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4241	* preemption disabled for a while. Since this is purly to aid the
4242	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4243	* disable interrupt on NT.
4244	*
4245	* We need to check for force-flags that could've possible been altered since we last
4246	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4247	* see @bugref{6398}).
4248	*
4249	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4250	* to ring-3 before executing guest code.
4251	*/
4252	pSvmTransient->fEFlags = ASMIntDisableFlags();
4253	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4254	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4255	{
4256	ASMSetFlags(pSvmTransient->fEFlags);
4257	VMMRZCallRing3Enable(pVCpu);
4258	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4259	return VINF_EM_RAW_TO_R3;
4260	}
4261	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4262	{
4263	ASMSetFlags(pSvmTransient->fEFlags);
4264	VMMRZCallRing3Enable(pVCpu);
4265	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4266	return VINF_EM_RAW_INTERRUPT;
4267	}
4268	return VINF_SUCCESS;
4269	}
4270	#endif
4271
4272
4273	/**
4274	* Does the preparations before executing guest code in AMD-V.
4275	*
4276	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4277	* recompiler. We must be cautious what we do here regarding committing
4278	* guest-state information into the VMCB assuming we assuredly execute the guest
4279	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4280	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4281	* that the recompiler can (and should) use them when it resumes guest
4282	* execution. Otherwise such operations must be done when we can no longer
4283	* exit to ring-3.
4284	*
4285	* @returns VBox status code (informational status codes included).
4286	* @retval VINF_SUCCESS if we can proceed with running the guest.
4287	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4288	*
4289	* @param pVCpu The cross context virtual CPU structure.
4290	* @param pSvmTransient Pointer to the SVM transient structure.
4291	*/
4292	static int hmR0SvmPreRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4293	{
4294	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4295	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4296
4297	/* Check force flag actions that might require us to go back to ring-3. */
4298	int rc = hmR0SvmCheckForceFlags(pVCpu);
4299	if (rc != VINF_SUCCESS)
4300	return rc;
4301
4302	if (TRPMHasTrap(pVCpu))
4303	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4304	else if (!pVCpu->hm.s.Event.fPending)
4305	hmR0SvmEvaluatePendingEvent(pVCpu);
4306
4307	/*
4308	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4309	* Just do it in software, see @bugref{8411}.
4310	* NB: If we could continue a task switch exit we wouldn't need to do this.
4311	*/
4312	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4313	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
4314	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
4315	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4316
4317	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4318	Assert(!(pVCpu->cpum.GstCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4319	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4320	#endif
4321
4322	/*
4323	* Export the guest state bits that are not shared with the host in any way as we can
4324	* longjmp or get preempted in the midst of exporting some of the state.
4325	*/
4326	rc = hmR0SvmExportGuestState(pVCpu);
4327	AssertRCReturn(rc, rc);
4328	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4329
4330	/*
4331	* If we're not intercepting TPR changes in the guest, save the guest TPR before the
4332	* world-switch so we can update it on the way back if the guest changed the TPR.
4333	*/
4334	if (pVCpu->hm.s.svm.fSyncVTpr)
4335	{
4336	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4337	if (pVM->hm.s.fTPRPatchingActive)
4338	pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
4339	else
4340	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4341	}
4342
4343	/*
4344	* No longjmps to ring-3 from this point on!!!
4345	*
4346	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4347	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4348	*/
4349	VMMRZCallRing3Disable(pVCpu);
4350
4351	/*
4352	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4353	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4354	* preemption disabled for a while. Since this is purly to aid the
4355	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4356	* disable interrupt on NT.
4357	*
4358	* We need to check for force-flags that could've possible been altered since we last
4359	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4360	* see @bugref{6398}).
4361	*
4362	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4363	* to ring-3 before executing guest code.
4364	*/
4365	pSvmTransient->fEFlags = ASMIntDisableFlags();
4366	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4367	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4368	{
4369	ASMSetFlags(pSvmTransient->fEFlags);
4370	VMMRZCallRing3Enable(pVCpu);
4371	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4372	return VINF_EM_RAW_TO_R3;
4373	}
4374	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4375	{
4376	ASMSetFlags(pSvmTransient->fEFlags);
4377	VMMRZCallRing3Enable(pVCpu);
4378	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4379	return VINF_EM_RAW_INTERRUPT;
4380	}
4381
4382	return VINF_SUCCESS;
4383	}
4384
4385
4386	/**
4387	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4388	* doing so.
4389	*
4390	* This means there is no backing out to ring-3 or anywhere else at this point.
4391	*
4392	* @param pVCpu The cross context virtual CPU structure.
4393	* @param pSvmTransient Pointer to the SVM transient structure.
4394	*
4395	* @remarks Called with preemption disabled.
4396	* @remarks No-long-jump zone!!!
4397	*/
4398	static void hmR0SvmPreRunGuestCommitted(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4399	{
4400	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4401	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4402	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4403
4404	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4405	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4406
4407	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4408	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4409
4410	hmR0SvmInjectPendingEvent(pVCpu, pVmcb);
4411
4412	if (!CPUMIsGuestFPUStateActive(pVCpu))
4413	{
4414	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4415	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4416	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4417	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4418	}
4419
4420	/* Load the state shared between host and guest (FPU, debug). */
4421	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)
4422	hmR0SvmExportSharedState(pVCpu, pVmcb);
4423
4424	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
4425	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
4426
4427	PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
4428	RTCPUID const idHostCpu = pHostCpu->idCpu;
4429	bool const fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
4430
4431	/* Setup TSC offsetting. */
4432	if ( pSvmTransient->fUpdateTscOffsetting
4433	\|\| fMigratedHostCpu)
4434	{
4435	hmR0SvmUpdateTscOffsetting(pVCpu, pVmcb);
4436	pSvmTransient->fUpdateTscOffsetting = false;
4437	}
4438
4439	/* Record statistics of how often we use TSC offsetting as opposed to intercepting RDTSC/P. */
4440	if (!(pVmcb->ctrl.u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
4441	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
4442	else
4443	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
4444
4445	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4446	if (fMigratedHostCpu)
4447	pVmcb->ctrl.u32VmcbCleanBits = 0;
4448
4449	/* Store status of the shared guest-host state at the time of VMRUN. */
4450	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4451	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4452
4453	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4454	uint8_t *pbMsrBitmap;
4455	if (!pSvmTransient->fIsNestedGuest)
4456	pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
4457	else
4458	{
4459	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu);
4460
4461	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4462	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4463	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4464	}
4465	#else
4466	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4467	#endif
4468
4469	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4470	/* Flush the appropriate tagged-TLB entries. */
4471	hmR0SvmFlushTaggedTlb(pHostCpu, pVCpu, pVmcb);
4472	Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
4473
4474	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4475
4476	TMNotifyStartOfExecution(pVM, pVCpu); /* Finally, notify TM to resume its clocks as we're about
4477	to start executing. */
4478
4479	/*
4480	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that RDTSCPs
4481	* (that don't cause exits) reads the guest MSR, see @bugref{3324}.
4482	*
4483	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4484	*/
4485	if ( pVM->cpum.ro.HostFeatures.fRdTscP
4486	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4487	{
4488	uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
4489	pVCpu->hm.s.svm.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4490	if (uGuestTscAux != pVCpu->hm.s.svm.u64HostTscAux)
4491	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4492	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4493	pSvmTransient->fRestoreTscAuxMsr = true;
4494	}
4495	else
4496	{
4497	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4498	pSvmTransient->fRestoreTscAuxMsr = false;
4499	}
4500	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4501
4502	/*
4503	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the nested
4504	* virtualization case, mark all state-bits as dirty indicating to the CPU to re-load
4505	* from the VMCB.
4506	*/
4507	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu);
4508	if (!fSupportsVmcbCleanBits)
4509	pVmcb->ctrl.u32VmcbCleanBits = 0;
4510	}
4511
4512
4513	/**
4514	* Wrapper for running the guest (or nested-guest) code in AMD-V.
4515	*
4516	* @returns VBox strict status code.
4517	* @param pVCpu The cross context virtual CPU structure.
4518	* @param HCPhysVmcb The host physical address of the VMCB.
4519	*
4520	* @remarks No-long-jump zone!!!
4521	*/
4522	DECLINLINE(int) hmR0SvmRunGuest(PVMCPUCC pVCpu, RTHCPHYS HCPhysVmcb)
4523	{
4524	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4525	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4526	pCtx->fExtrn \|= HMSVM_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
4527
4528	/*
4529	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses
4530	* floating-point operations using SSE instructions. Some XMM registers (XMM6-XMM15) are
4531	* callee-saved and thus the need for this XMM wrapper.
4532	*
4533	* Refer MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
4534	*/
4535	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4536	#ifdef VBOX_WITH_KERNEL_USING_XMM
4537	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu, pVCpu->hm.s.svm.pfnVMRun);
4538	#else
4539	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu);
4540	#endif
4541	}
4542
4543
4544	/**
4545	* Performs some essential restoration of state after running guest (or
4546	* nested-guest) code in AMD-V.
4547	*
4548	* @param pVCpu The cross context virtual CPU structure.
4549	* @param pSvmTransient Pointer to the SVM transient structure.
4550	* @param rcVMRun Return code of VMRUN.
4551	*
4552	* @remarks Called with interrupts disabled.
4553	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4554	* unconditionally when it is safe to do so.
4555	*/
4556	static void hmR0SvmPostRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4557	{
4558	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4559
4560	uint64_t const uHostTsc = ASMReadTSC(); /* Read the TSC as soon as possible. */
4561	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4562	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4563
4564	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4565	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4566
4567	/* TSC read must be done early for maximum accuracy. */
4568	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4569	{
4570	if (!pSvmTransient->fIsNestedGuest)
4571	TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4572	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4573	else
4574	{
4575	/* The nested-guest VMCB TSC offset shall eventually be restored on #VMEXIT via HMNotifySvmNstGstVmexit(). */
4576	uint64_t const uGstTsc = CPUMRemoveNestedGuestTscOffset(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4577	TMCpuTickSetLastSeen(pVCpu, uGstTsc);
4578	}
4579	#endif
4580	}
4581
4582	if (pSvmTransient->fRestoreTscAuxMsr)
4583	{
4584	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4585	CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4586	if (u64GuestTscAuxMsr != pVCpu->hm.s.svm.u64HostTscAux)
4587	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.svm.u64HostTscAux);
4588	}
4589
4590	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
4591	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4592	TMNotifyEndOfExecution(pVM, pVCpu); /* Notify TM that the guest is no longer running. */
4593	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4594
4595	Assert(!(ASMGetFlags() & X86_EFL_IF));
4596	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4597	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4598
4599	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4600	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4601	{
4602	Log4Func(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4603	return;
4604	}
4605
4606	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4607	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4608	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4609	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4610
4611	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4612	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4613	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4614	#else
4615	/*
4616	* Always import the following:
4617	*
4618	* - RIP for exit optimizations and evaluating event injection on re-entry.
4619	* - RFLAGS for evaluating event injection on VM re-entry and for exporting shared debug
4620	* state on preemption.
4621	* - Interrupt shadow, GIF for evaluating event injection on VM re-entry.
4622	* - CS for exit optimizations.
4623	* - RAX, RSP for simplifying assumptions on GPRs. All other GPRs are swapped by the
4624	* assembly switcher code.
4625	* - Shared state (only DR7 currently) for exporting shared debug state on preemption.
4626	*/
4627	hmR0SvmImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP
4628	\| CPUMCTX_EXTRN_RFLAGS
4629	\| CPUMCTX_EXTRN_RAX
4630	\| CPUMCTX_EXTRN_RSP
4631	\| CPUMCTX_EXTRN_CS
4632	\| CPUMCTX_EXTRN_HWVIRT
4633	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
4634	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ
4635	\| HMSVM_CPUMCTX_SHARED_STATE);
4636	#endif
4637
4638	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4639	&& pVCpu->hm.s.svm.fSyncVTpr)
4640	{
4641	Assert(!pSvmTransient->fIsNestedGuest);
4642	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4643	if ( pVM->hm.s.fTPRPatchingActive
4644	&& (pVmcb->guest.u64LSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4645	{
4646	int rc = APICSetTpr(pVCpu, pVmcb->guest.u64LSTAR & 0xff);
4647	AssertRC(rc);
4648	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4649	}
4650	/* Sync TPR when we aren't intercepting CR8 writes. */
4651	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4652	{
4653	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4654	AssertRC(rc);
4655	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4656	}
4657	}
4658
4659	#ifdef DEBUG_ramshankar
4660	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4661	{
4662	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4663	hmR0SvmLogState(pVCpu, pVmcb, pVCpu->cpum.GstCtx, "hmR0SvmPostRunGuestNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR,
4664	0 /* uVerbose */);
4665	}
4666	#endif
4667
4668	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
4669	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
4670	pVCpu->cpum.GstCtx.cs.u64Base + pVCpu->cpum.GstCtx.rip, uHostTsc);
4671	}
4672
4673
4674	/**
4675	* Runs the guest code using AMD-V.
4676	*
4677	* @returns VBox status code.
4678	* @param pVCpu The cross context virtual CPU structure.
4679	* @param pcLoops Pointer to the number of executed loops.
4680	*/
4681	static int hmR0SvmRunGuestCodeNormal(PVMCPUCC pVCpu, uint32_t *pcLoops)
4682	{
4683	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4684	Assert(pcLoops);
4685	Assert(*pcLoops <= cMaxResumeLoops);
4686
4687	SVMTRANSIENT SvmTransient;
4688	RT_ZERO(SvmTransient);
4689	SvmTransient.fUpdateTscOffsetting = true;
4690	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4691
4692	int rc = VERR_INTERNAL_ERROR_5;
4693	for (;;)
4694	{
4695	Assert(!HMR0SuspendPending());
4696	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4697
4698	/* Preparatory work for running nested-guest code, this may force us to return to
4699	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4700	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4701	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4702	if (rc != VINF_SUCCESS)
4703	break;
4704
4705	/*
4706	* No longjmps to ring-3 from this point on!!!
4707	*
4708	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4709	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4710	*/
4711	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4712	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4713
4714	/* Restore any residual host-state and save any bits shared between host and guest
4715	into the guest-CPU state. Re-enables interrupts! */
4716	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4717
4718	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4719	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4720	{
4721	if (rc == VINF_SUCCESS)
4722	rc = VERR_SVM_INVALID_GUEST_STATE;
4723	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4724	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4725	break;
4726	}
4727
4728	/* Handle the #VMEXIT. */
4729	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4730	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4731	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4732	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4733	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4734	if (rc != VINF_SUCCESS)
4735	break;
4736	if (++(*pcLoops) >= cMaxResumeLoops)
4737	{
4738	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4739	rc = VINF_EM_RAW_INTERRUPT;
4740	break;
4741	}
4742	}
4743
4744	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4745	return rc;
4746	}
4747
4748
4749	/**
4750	* Runs the guest code using AMD-V in single step mode.
4751	*
4752	* @returns VBox status code.
4753	* @param pVCpu The cross context virtual CPU structure.
4754	* @param pcLoops Pointer to the number of executed loops.
4755	*/
4756	static int hmR0SvmRunGuestCodeStep(PVMCPUCC pVCpu, uint32_t *pcLoops)
4757	{
4758	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4759	Assert(pcLoops);
4760	Assert(*pcLoops <= cMaxResumeLoops);
4761
4762	SVMTRANSIENT SvmTransient;
4763	RT_ZERO(SvmTransient);
4764	SvmTransient.fUpdateTscOffsetting = true;
4765	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4766
4767	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4768	uint16_t uCsStart = pCtx->cs.Sel;
4769	uint64_t uRipStart = pCtx->rip;
4770
4771	int rc = VERR_INTERNAL_ERROR_5;
4772	for (;;)
4773	{
4774	Assert(!HMR0SuspendPending());
4775	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4776	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4777	(unsigned)RTMpCpuId(), *pcLoops));
4778
4779	/* Preparatory work for running nested-guest code, this may force us to return to
4780	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4781	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4782	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4783	if (rc != VINF_SUCCESS)
4784	break;
4785
4786	/*
4787	* No longjmps to ring-3 from this point on!!!
4788	*
4789	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4790	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4791	*/
4792	VMMRZCallRing3Disable(pVCpu);
4793	VMMRZCallRing3RemoveNotification(pVCpu);
4794	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4795
4796	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4797
4798	/* Restore any residual host-state and save any bits shared between host and guest
4799	into the guest-CPU state. Re-enables interrupts! */
4800	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4801
4802	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4803	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4804	{
4805	if (rc == VINF_SUCCESS)
4806	rc = VERR_SVM_INVALID_GUEST_STATE;
4807	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4808	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4809	return rc;
4810	}
4811
4812	/* Handle the #VMEXIT. */
4813	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4814	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4815	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4816	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4817	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4818	if (rc != VINF_SUCCESS)
4819	break;
4820	if (++(*pcLoops) >= cMaxResumeLoops)
4821	{
4822	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4823	rc = VINF_EM_RAW_INTERRUPT;
4824	break;
4825	}
4826
4827	/*
4828	* Did the RIP change, if so, consider it a single step.
4829	* Otherwise, make sure one of the TFs gets set.
4830	*/
4831	if ( pCtx->rip != uRipStart
4832	\|\| pCtx->cs.Sel != uCsStart)
4833	{
4834	rc = VINF_EM_DBG_STEPPED;
4835	break;
4836	}
4837	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR_MASK;
4838	}
4839
4840	/*
4841	* Clear the X86_EFL_TF if necessary.
4842	*/
4843	if (pVCpu->hm.s.fClearTrapFlag)
4844	{
4845	pVCpu->hm.s.fClearTrapFlag = false;
4846	pCtx->eflags.Bits.u1TF = 0;
4847	}
4848
4849	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4850	return rc;
4851	}
4852
4853	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4854	/**
4855	* Runs the nested-guest code using AMD-V.
4856	*
4857	* @returns VBox status code.
4858	* @param pVCpu The cross context virtual CPU structure.
4859	* @param pcLoops Pointer to the number of executed loops. If we're switching
4860	* from the guest-code execution loop to this nested-guest
4861	* execution loop pass the remainder value, else pass 0.
4862	*/
4863	static int hmR0SvmRunGuestCodeNested(PVMCPUCC pVCpu, uint32_t *pcLoops)
4864	{
4865	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4866	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4867	Assert(pcLoops);
4868	Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops);
4869
4870	SVMTRANSIENT SvmTransient;
4871	RT_ZERO(SvmTransient);
4872	SvmTransient.fUpdateTscOffsetting = true;
4873	SvmTransient.pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4874	SvmTransient.fIsNestedGuest = true;
4875
4876	int rc = VERR_INTERNAL_ERROR_4;
4877	for (;;)
4878	{
4879	Assert(!HMR0SuspendPending());
4880	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4881
4882	/* Preparatory work for running nested-guest code, this may force us to return to
4883	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4884	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4885	rc = hmR0SvmPreRunGuestNested(pVCpu, &SvmTransient);
4886	if ( rc != VINF_SUCCESS
4887	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4888	{
4889	break;
4890	}
4891
4892	/*
4893	* No longjmps to ring-3 from this point on!!!
4894	*
4895	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4896	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4897	*/
4898	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4899
4900	rc = hmR0SvmRunGuest(pVCpu, pCtx->hwvirt.svm.HCPhysVmcb);
4901
4902	/* Restore any residual host-state and save any bits shared between host and guest
4903	into the guest-CPU state. Re-enables interrupts! */
4904	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4905
4906	if (RT_LIKELY( rc == VINF_SUCCESS
4907	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4908	{ /* extremely likely */ }
4909	else
4910	{
4911	/* VMRUN failed, shouldn't really happen, Guru. */
4912	if (rc != VINF_SUCCESS)
4913	break;
4914
4915	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4916	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4917	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4918	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
4919	break;
4920	}
4921
4922	/* Handle the #VMEXIT. */
4923	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4924	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4925	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4926	rc = hmR0SvmHandleExitNested(pVCpu, &SvmTransient);
4927	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4928	if ( rc != VINF_SUCCESS
4929	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4930	break;
4931	if (++(*pcLoops) >= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
4932	{
4933	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4934	rc = VINF_EM_RAW_INTERRUPT;
4935	break;
4936	}
4937	/** @todo NSTSVM: Add stat for StatSwitchNstGstVmexit. Re-arrange the above code to
4938	* be accurate when doing so, see the corresponding VT-x code. */
4939
4940	/** @todo handle single-stepping */
4941	}
4942
4943	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4944	return rc;
4945	}
4946	#endif
4947
4948
4949	/**
4950	* Runs the guest code using AMD-V.
4951	*
4952	* @returns Strict VBox status code.
4953	* @param pVCpu The cross context virtual CPU structure.
4954	*/
4955	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPUCC pVCpu)
4956	{
4957	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4958	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4959	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, NULL /* pvUser */);
4960
4961	uint32_t cLoops = 0;
4962	int rc;
4963	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4964	if (!CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4965	#endif
4966	{
4967	if (!pVCpu->hm.s.fSingleInstruction)
4968	rc = hmR0SvmRunGuestCodeNormal(pVCpu, &cLoops);
4969	else
4970	rc = hmR0SvmRunGuestCodeStep(pVCpu, &cLoops);
4971	}
4972	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4973	else
4974	{
4975	rc = VINF_SVM_VMRUN;
4976	}
4977
4978	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4979	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4980	if (rc == VINF_SVM_VMRUN)
4981	{
4982	rc = hmR0SvmRunGuestCodeNested(pVCpu, &cLoops);
4983	if (rc == VINF_SVM_VMEXIT)
4984	rc = VINF_SUCCESS;
4985	}
4986	#endif
4987
4988	/** @todo NSTSVM: Continue in ring-0 after nested-guest \#VMEXIT. See VT-x code for
4989	* reference. */
4990
4991	/* Fixup error codes. */
4992	if (rc == VERR_EM_INTERPRETER)
4993	rc = VINF_EM_RAW_EMULATE_INSTR;
4994	else if (rc == VINF_EM_RESET)
4995	rc = VINF_EM_TRIPLE_FAULT;
4996
4997	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4998	rc = hmR0SvmExitToRing3(pVCpu, rc);
4999	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
5000	return rc;
5001	}
5002
5003
5004	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5005	/**
5006	* Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
5007	*
5008	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
5009	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
5010	*/
5011	static bool hmR0SvmIsIoInterceptSet(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
5012	{
5013	const uint16_t u16Port = pIoExitInfo->n.u16Port;
5014	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
5015	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
5016	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
5017	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
5018	const bool fRep = pIoExitInfo->n.u1Rep;
5019	const bool fStrIo = pIoExitInfo->n.u1Str;
5020
5021	return CPUMIsSvmIoInterceptSet(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
5022	NULL /* pIoExitInfo */);
5023	}
5024
5025
5026	/**
5027	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
5028	* SVM_EXIT_INVALID).
5029	*
5030	* @returns VBox status code (informational status codes included).
5031	* @param pVCpu The cross context virtual CPU structure.
5032	* @param pSvmTransient Pointer to the SVM transient structure.
5033	*/
5034	static int hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5035	{
5036	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
5037	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5038	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5039
5040	/*
5041	* We import the complete state here because we use separate VMCBs for the guest and the
5042	* nested-guest, and the guest's VMCB is used after the #VMEXIT. We can only save/restore
5043	* the #VMEXIT specific state if we used the same VMCB for both guest and nested-guest.
5044	*/
5045	#define NST_GST_VMEXIT_CALL_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5046	do { \
5047	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5048	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2))); \
5049	} while (0)
5050
5051	/*
5052	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected by the
5053	* nested-guest. If it isn't, it should be handled by the (outer) guest.
5054	*/
5055	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
5056	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5057	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
5058	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
5059	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
5060	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
5061
5062	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
5063	switch (uExitCode)
5064	{
5065	case SVM_EXIT_CPUID:
5066	{
5067	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
5068	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5069	return hmR0SvmExitCpuid(pVCpu, pSvmTransient);
5070	}
5071
5072	case SVM_EXIT_RDTSC:
5073	{
5074	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
5075	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5076	return hmR0SvmExitRdtsc(pVCpu, pSvmTransient);
5077	}
5078
5079	case SVM_EXIT_RDTSCP:
5080	{
5081	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
5082	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5083	return hmR0SvmExitRdtscp(pVCpu, pSvmTransient);
5084	}
5085
5086	case SVM_EXIT_MONITOR:
5087	{
5088	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
5089	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5090	return hmR0SvmExitMonitor(pVCpu, pSvmTransient);
5091	}
5092
5093	case SVM_EXIT_MWAIT:
5094	{
5095	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
5096	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5097	return hmR0SvmExitMwait(pVCpu, pSvmTransient);
5098	}
5099
5100	case SVM_EXIT_HLT:
5101	{
5102	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
5103	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5104	return hmR0SvmExitHlt(pVCpu, pSvmTransient);
5105	}
5106
5107	case SVM_EXIT_MSR:
5108	{
5109	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
5110	{
5111	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
5112	uint16_t offMsrpm;
5113	uint8_t uMsrpmBit;
5114	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
5115	if (RT_SUCCESS(rc))
5116	{
5117	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
5118	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
5119
5120	uint8_t const pbMsrBitmap = (uint8_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
5121	pbMsrBitmap += offMsrpm;
5122	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
5123	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
5124
5125	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
5126	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
5127	{
5128	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5129	}
5130	}
5131	else
5132	{
5133	/*
5134	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
5135	* See AMD-V spec. "15.11 MSR Intercepts".
5136	*/
5137	Assert(rc == VERR_OUT_OF_RANGE);
5138	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5139	}
5140	}
5141	return hmR0SvmExitMsr(pVCpu, pSvmTransient);
5142	}
5143
5144	case SVM_EXIT_IOIO:
5145	{
5146	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
5147	{
5148	void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
5149	SVMIOIOEXITINFO IoExitInfo;
5150	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
5151	bool const fIntercept = hmR0SvmIsIoInterceptSet(pvIoBitmap, &IoExitInfo);
5152	if (fIntercept)
5153	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5154	}
5155	return hmR0SvmExitIOInstr(pVCpu, pSvmTransient);
5156	}
5157
5158	case SVM_EXIT_XCPT_PF:
5159	{
5160	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
5161	if (pVM->hm.s.fNestedPaging)
5162	{
5163	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
5164	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
5165
5166	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
5167	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
5168	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
5169
5170	/* If the nested-guest is not intercepting #PFs, forward the #PF to the guest. */
5171	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5172	hmR0SvmSetPendingXcptPF(pVCpu, u32ErrCode, uFaultAddress);
5173	return VINF_SUCCESS;
5174	}
5175	return hmR0SvmExitXcptPF(pVCpu, pSvmTransient);
5176	}
5177
5178	case SVM_EXIT_XCPT_UD:
5179	{
5180	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
5181	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5182	hmR0SvmSetPendingXcptUD(pVCpu);
5183	return VINF_SUCCESS;
5184	}
5185
5186	case SVM_EXIT_XCPT_MF:
5187	{
5188	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
5189	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5190	return hmR0SvmExitXcptMF(pVCpu, pSvmTransient);
5191	}
5192
5193	case SVM_EXIT_XCPT_DB:
5194	{
5195	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
5196	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5197	return hmR0SvmNestedExitXcptDB(pVCpu, pSvmTransient);
5198	}
5199
5200	case SVM_EXIT_XCPT_AC:
5201	{
5202	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
5203	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5204	return hmR0SvmExitXcptAC(pVCpu, pSvmTransient);
5205	}
5206
5207	case SVM_EXIT_XCPT_BP:
5208	{
5209	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
5210	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5211	return hmR0SvmNestedExitXcptBP(pVCpu, pSvmTransient);
5212	}
5213
5214	case SVM_EXIT_READ_CR0:
5215	case SVM_EXIT_READ_CR3:
5216	case SVM_EXIT_READ_CR4:
5217	{
5218	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5219	if (CPUMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5220	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5221	return hmR0SvmExitReadCRx(pVCpu, pSvmTransient);
5222	}
5223
5224	case SVM_EXIT_CR0_SEL_WRITE:
5225	{
5226	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5227	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5228	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5229	}
5230
5231	case SVM_EXIT_WRITE_CR0:
5232	case SVM_EXIT_WRITE_CR3:
5233	case SVM_EXIT_WRITE_CR4:
5234	case SVM_EXIT_WRITE_CR8: /* CR8 writes would go to the V_TPR rather than here, since we run with V_INTR_MASKING. */
5235	{
5236	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5237	Log4Func(("Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5238
5239	if (CPUMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5240	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5241	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5242	}
5243
5244	case SVM_EXIT_PAUSE:
5245	{
5246	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5247	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5248	return hmR0SvmExitPause(pVCpu, pSvmTransient);
5249	}
5250
5251	case SVM_EXIT_VINTR:
5252	{
5253	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5254	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5255	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5256	}
5257
5258	case SVM_EXIT_INTR:
5259	case SVM_EXIT_NMI:
5260	case SVM_EXIT_SMI:
5261	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5262	{
5263	/*
5264	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5265	*
5266	* Although we don't intercept SMIs, the nested-guest might. Therefore, we might
5267	* get an SMI #VMEXIT here so simply ignore rather than causing a corresponding
5268	* nested-guest #VMEXIT.
5269	*
5270	* We shall import the complete state here as we may cause #VMEXITs from ring-3
5271	* while trying to inject interrupts, see comment at the top of this function.
5272	*/
5273	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_ALL);
5274	return hmR0SvmExitIntr(pVCpu, pSvmTransient);
5275	}
5276
5277	case SVM_EXIT_FERR_FREEZE:
5278	{
5279	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5280	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5281	return hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient);
5282	}
5283
5284	case SVM_EXIT_INVLPG:
5285	{
5286	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5287	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5288	return hmR0SvmExitInvlpg(pVCpu, pSvmTransient);
5289	}
5290
5291	case SVM_EXIT_WBINVD:
5292	{
5293	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5294	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5295	return hmR0SvmExitWbinvd(pVCpu, pSvmTransient);
5296	}
5297
5298	case SVM_EXIT_INVD:
5299	{
5300	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5301	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5302	return hmR0SvmExitInvd(pVCpu, pSvmTransient);
5303	}
5304
5305	case SVM_EXIT_RDPMC:
5306	{
5307	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5308	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5309	return hmR0SvmExitRdpmc(pVCpu, pSvmTransient);
5310	}
5311
5312	default:
5313	{
5314	switch (uExitCode)
5315	{
5316	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5317	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5318	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5319	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5320	{
5321	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5322	if (CPUMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5323	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5324	return hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
5325	}
5326
5327	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5328	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5329	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5330	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5331	{
5332	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5333	if (CPUMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5334	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5335	return hmR0SvmExitWriteDRx(pVCpu, pSvmTransient);
5336	}
5337
5338	case SVM_EXIT_XCPT_DE:
5339	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5340	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5341	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5342	case SVM_EXIT_XCPT_OF:
5343	case SVM_EXIT_XCPT_BR:
5344	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5345	case SVM_EXIT_XCPT_NM:
5346	case SVM_EXIT_XCPT_DF:
5347	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5348	case SVM_EXIT_XCPT_TS:
5349	case SVM_EXIT_XCPT_NP:
5350	case SVM_EXIT_XCPT_SS:
5351	case SVM_EXIT_XCPT_GP:
5352	/* SVM_EXIT_XCPT_PF: / / Handled above. */
5353	case SVM_EXIT_XCPT_15: /* Reserved. */
5354	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5355	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5356	case SVM_EXIT_XCPT_MC:
5357	case SVM_EXIT_XCPT_XF:
5358	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5359	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5360	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5361	{
5362	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5363	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5364	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5365	return hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient);
5366	}
5367
5368	case SVM_EXIT_XSETBV:
5369	{
5370	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5371	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5372	return hmR0SvmExitXsetbv(pVCpu, pSvmTransient);
5373	}
5374
5375	case SVM_EXIT_TASK_SWITCH:
5376	{
5377	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5378	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5379	return hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient);
5380	}
5381
5382	case SVM_EXIT_IRET:
5383	{
5384	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5385	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5386	return hmR0SvmExitIret(pVCpu, pSvmTransient);
5387	}
5388
5389	case SVM_EXIT_SHUTDOWN:
5390	{
5391	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5392	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5393	return hmR0SvmExitShutdown(pVCpu, pSvmTransient);
5394	}
5395
5396	case SVM_EXIT_VMMCALL:
5397	{
5398	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5399	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5400	return hmR0SvmExitVmmCall(pVCpu, pSvmTransient);
5401	}
5402
5403	case SVM_EXIT_CLGI:
5404	{
5405	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5406	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5407	return hmR0SvmExitClgi(pVCpu, pSvmTransient);
5408	}
5409
5410	case SVM_EXIT_STGI:
5411	{
5412	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5413	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5414	return hmR0SvmExitStgi(pVCpu, pSvmTransient);
5415	}
5416
5417	case SVM_EXIT_VMLOAD:
5418	{
5419	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5420	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5421	return hmR0SvmExitVmload(pVCpu, pSvmTransient);
5422	}
5423
5424	case SVM_EXIT_VMSAVE:
5425	{
5426	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5427	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5428	return hmR0SvmExitVmsave(pVCpu, pSvmTransient);
5429	}
5430
5431	case SVM_EXIT_INVLPGA:
5432	{
5433	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5434	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5435	return hmR0SvmExitInvlpga(pVCpu, pSvmTransient);
5436	}
5437
5438	case SVM_EXIT_VMRUN:
5439	{
5440	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5441	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5442	return hmR0SvmExitVmrun(pVCpu, pSvmTransient);
5443	}
5444
5445	case SVM_EXIT_RSM:
5446	{
5447	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5448	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5449	hmR0SvmSetPendingXcptUD(pVCpu);
5450	return VINF_SUCCESS;
5451	}
5452
5453	case SVM_EXIT_SKINIT:
5454	{
5455	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5456	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5457	hmR0SvmSetPendingXcptUD(pVCpu);
5458	return VINF_SUCCESS;
5459	}
5460
5461	case SVM_EXIT_NPF:
5462	{
5463	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5464	return hmR0SvmExitNestedPF(pVCpu, pSvmTransient);
5465	}
5466
5467	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5468	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5469
5470	default:
5471	{
5472	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5473	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5474	return VERR_SVM_UNKNOWN_EXIT;
5475	}
5476	}
5477	}
5478	}
5479	/* not reached */
5480
5481	#undef NST_GST_VMEXIT_CALL_RET
5482	}
5483	#endif
5484
5485
5486	/**
5487	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5488	*
5489	* @returns VBox status code (informational status codes included).
5490	* @param pVCpu The cross context virtual CPU structure.
5491	* @param pSvmTransient Pointer to the SVM transient structure.
5492	*/
5493	static int hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5494	{
5495	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5496	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5497
5498	#ifdef DEBUG_ramshankar
5499	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) \
5500	do { \
5501	if ((a_fDbg) == 1) \
5502	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5503	int rc = a_CallExpr; \
5504	if ((a_fDbg) == 1) \
5505	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
5506	return rc; \
5507	} while (0)
5508	#else
5509	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) return a_CallExpr
5510	#endif
5511
5512	/*
5513	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs
5514	* for most guests under normal workloads (for some definition of "normal").
5515	*/
5516	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5517	switch (uExitCode)
5518	{
5519	case SVM_EXIT_NPF: VMEXIT_CALL_RET(0, hmR0SvmExitNestedPF(pVCpu, pSvmTransient));
5520	case SVM_EXIT_IOIO: VMEXIT_CALL_RET(0, hmR0SvmExitIOInstr(pVCpu, pSvmTransient));
5521	case SVM_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0SvmExitRdtsc(pVCpu, pSvmTransient));
5522	case SVM_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0SvmExitRdtscp(pVCpu, pSvmTransient));
5523	case SVM_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0SvmExitCpuid(pVCpu, pSvmTransient));
5524	case SVM_EXIT_XCPT_PF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptPF(pVCpu, pSvmTransient));
5525	case SVM_EXIT_MSR: VMEXIT_CALL_RET(0, hmR0SvmExitMsr(pVCpu, pSvmTransient));
5526	case SVM_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0SvmExitMonitor(pVCpu, pSvmTransient));
5527	case SVM_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0SvmExitMwait(pVCpu, pSvmTransient));
5528	case SVM_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0SvmExitHlt(pVCpu, pSvmTransient));
5529
5530	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5531	case SVM_EXIT_INTR:
5532	case SVM_EXIT_NMI: VMEXIT_CALL_RET(0, hmR0SvmExitIntr(pVCpu, pSvmTransient));
5533
5534	case SVM_EXIT_READ_CR0:
5535	case SVM_EXIT_READ_CR3:
5536	case SVM_EXIT_READ_CR4: VMEXIT_CALL_RET(0, hmR0SvmExitReadCRx(pVCpu, pSvmTransient));
5537
5538	case SVM_EXIT_CR0_SEL_WRITE:
5539	case SVM_EXIT_WRITE_CR0:
5540	case SVM_EXIT_WRITE_CR3:
5541	case SVM_EXIT_WRITE_CR4:
5542	case SVM_EXIT_WRITE_CR8: VMEXIT_CALL_RET(0, hmR0SvmExitWriteCRx(pVCpu, pSvmTransient));
5543
5544	case SVM_EXIT_VINTR: VMEXIT_CALL_RET(0, hmR0SvmExitVIntr(pVCpu, pSvmTransient));
5545	case SVM_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0SvmExitPause(pVCpu, pSvmTransient));
5546	case SVM_EXIT_VMMCALL: VMEXIT_CALL_RET(0, hmR0SvmExitVmmCall(pVCpu, pSvmTransient));
5547	case SVM_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpg(pVCpu, pSvmTransient));
5548	case SVM_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0SvmExitWbinvd(pVCpu, pSvmTransient));
5549	case SVM_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0SvmExitInvd(pVCpu, pSvmTransient));
5550	case SVM_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0SvmExitRdpmc(pVCpu, pSvmTransient));
5551	case SVM_EXIT_IRET: VMEXIT_CALL_RET(0, hmR0SvmExitIret(pVCpu, pSvmTransient));
5552	case SVM_EXIT_XCPT_UD: VMEXIT_CALL_RET(0, hmR0SvmExitXcptUD(pVCpu, pSvmTransient));
5553	case SVM_EXIT_XCPT_MF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptMF(pVCpu, pSvmTransient));
5554	case SVM_EXIT_XCPT_DB: VMEXIT_CALL_RET(0, hmR0SvmExitXcptDB(pVCpu, pSvmTransient));
5555	case SVM_EXIT_XCPT_AC: VMEXIT_CALL_RET(0, hmR0SvmExitXcptAC(pVCpu, pSvmTransient));
5556	case SVM_EXIT_XCPT_BP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptBP(pVCpu, pSvmTransient));
5557	case SVM_EXIT_XCPT_GP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptGP(pVCpu, pSvmTransient));
5558	case SVM_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0SvmExitXsetbv(pVCpu, pSvmTransient));
5559	case SVM_EXIT_FERR_FREEZE: VMEXIT_CALL_RET(0, hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient));
5560
5561	default:
5562	{
5563	switch (pSvmTransient->u64ExitCode)
5564	{
5565	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5566	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5567	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5568	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5569	VMEXIT_CALL_RET(0, hmR0SvmExitReadDRx(pVCpu, pSvmTransient));
5570
5571	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5572	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5573	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5574	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5575	VMEXIT_CALL_RET(0, hmR0SvmExitWriteDRx(pVCpu, pSvmTransient));
5576
5577	case SVM_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient));
5578	case SVM_EXIT_SHUTDOWN: VMEXIT_CALL_RET(0, hmR0SvmExitShutdown(pVCpu, pSvmTransient));
5579
5580	case SVM_EXIT_SMI:
5581	case SVM_EXIT_INIT:
5582	{
5583	/*
5584	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5585	* If it ever does, we want to know about it so log the exit code and bail.
5586	*/
5587	VMEXIT_CALL_RET(0, hmR0SvmExitUnexpected(pVCpu, pSvmTransient));
5588	}
5589
5590	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5591	case SVM_EXIT_CLGI: VMEXIT_CALL_RET(0, hmR0SvmExitClgi(pVCpu, pSvmTransient));
5592	case SVM_EXIT_STGI: VMEXIT_CALL_RET(0, hmR0SvmExitStgi(pVCpu, pSvmTransient));
5593	case SVM_EXIT_VMLOAD: VMEXIT_CALL_RET(0, hmR0SvmExitVmload(pVCpu, pSvmTransient));
5594	case SVM_EXIT_VMSAVE: VMEXIT_CALL_RET(0, hmR0SvmExitVmsave(pVCpu, pSvmTransient));
5595	case SVM_EXIT_INVLPGA: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpga(pVCpu, pSvmTransient));
5596	case SVM_EXIT_VMRUN: VMEXIT_CALL_RET(0, hmR0SvmExitVmrun(pVCpu, pSvmTransient));
5597	#else
5598	case SVM_EXIT_CLGI:
5599	case SVM_EXIT_STGI:
5600	case SVM_EXIT_VMLOAD:
5601	case SVM_EXIT_VMSAVE:
5602	case SVM_EXIT_INVLPGA:
5603	case SVM_EXIT_VMRUN:
5604	#endif
5605	case SVM_EXIT_RSM:
5606	case SVM_EXIT_SKINIT:
5607	{
5608	hmR0SvmSetPendingXcptUD(pVCpu);
5609	return VINF_SUCCESS;
5610	}
5611
5612	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5613	case SVM_EXIT_XCPT_DE:
5614	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5615	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5616	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5617	case SVM_EXIT_XCPT_OF:
5618	case SVM_EXIT_XCPT_BR:
5619	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5620	case SVM_EXIT_XCPT_NM:
5621	case SVM_EXIT_XCPT_DF:
5622	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5623	case SVM_EXIT_XCPT_TS:
5624	case SVM_EXIT_XCPT_NP:
5625	case SVM_EXIT_XCPT_SS:
5626	/* SVM_EXIT_XCPT_GP: / / Handled above. */
5627	/* SVM_EXIT_XCPT_PF: */
5628	case SVM_EXIT_XCPT_15: /* Reserved. */
5629	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5630	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5631	case SVM_EXIT_XCPT_MC:
5632	case SVM_EXIT_XCPT_XF:
5633	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5634	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5635	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5636	VMEXIT_CALL_RET(0, hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient));
5637	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5638
5639	default:
5640	{
5641	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5642	pVCpu->hm.s.u32HMError = uExitCode;
5643	return VERR_SVM_UNKNOWN_EXIT;
5644	}
5645	}
5646	}
5647	}
5648	/* not reached */
5649	#undef VMEXIT_CALL_RET
5650	}
5651
5652
5653	#ifdef VBOX_STRICT
5654	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5655	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5656	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5657
5658	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5659	do \
5660	{ \
5661	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5662	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5663	} while (0)
5664
5665	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5666	do { \
5667	AssertPtr((a_pVCpu)); \
5668	AssertPtr((a_pSvmTransient)); \
5669	Assert(ASMIntAreEnabled()); \
5670	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5671	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5672	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu)); \
5673	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5674	if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
5675	HMSVM_ASSERT_PREEMPT_CPUID(); \
5676	} while (0)
5677	#else
5678	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5679	do { \
5680	RT_NOREF2(a_pVCpu, a_pSvmTransient); \
5681	} while (0)
5682	#endif
5683
5684
5685	/**
5686	* Gets the IEM exception flags for the specified SVM event.
5687	*
5688	* @returns The IEM exception flags.
5689	* @param pEvent Pointer to the SVM event.
5690	*
5691	* @remarks This function currently only constructs flags required for
5692	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5693	* and CR2 aspects of an exception are not included).
5694	*/
5695	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5696	{
5697	uint8_t const uEventType = pEvent->n.u3Type;
5698	uint32_t fIemXcptFlags;
5699	switch (uEventType)
5700	{
5701	case SVM_EVENT_EXCEPTION:
5702	/*
5703	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5704	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5705	*/
5706	if (pEvent->n.u8Vector == X86_XCPT_BP)
5707	{
5708	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5709	break;
5710	}
5711	if (pEvent->n.u8Vector == X86_XCPT_OF)
5712	{
5713	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5714	break;
5715	}
5716	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5717	RT_FALL_THRU();
5718	case SVM_EVENT_NMI:
5719	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5720	break;
5721
5722	case SVM_EVENT_EXTERNAL_IRQ:
5723	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5724	break;
5725
5726	case SVM_EVENT_SOFTWARE_INT:
5727	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5728	break;
5729
5730	default:
5731	fIemXcptFlags = 0;
5732	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5733	break;
5734	}
5735	return fIemXcptFlags;
5736	}
5737
5738
5739	/**
5740	* Handle a condition that occurred while delivering an event through the guest
5741	* IDT.
5742	*
5743	* @returns VBox status code (informational error codes included).
5744	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5745	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5746	* continue execution of the guest which will delivery the \#DF.
5747	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5748	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5749	*
5750	* @param pVCpu The cross context virtual CPU structure.
5751	* @param pSvmTransient Pointer to the SVM transient structure.
5752	*
5753	* @remarks No-long-jump zone!!!
5754	*/
5755	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5756	{
5757	int rc = VINF_SUCCESS;
5758	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5759	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5760
5761	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5762	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5763	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5764
5765	/*
5766	* The EXITINTINFO (if valid) contains the prior exception (IDT vector) that was trying to
5767	* be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector).
5768	*
5769	* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code".
5770	*/
5771	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5772	{
5773	IEMXCPTRAISE enmRaise;
5774	IEMXCPTRAISEINFO fRaiseInfo;
5775	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5776	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5777	if (fExitIsHwXcpt)
5778	{
5779	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5780	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5781	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5782	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5783	}
5784	else
5785	{
5786	/*
5787	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF)
5788	* then we end up here.
5789	*
5790	* If the event was:
5791	* - a software interrupt, we can re-execute the instruction which will
5792	* regenerate the event.
5793	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5794	* - a hardware exception or external interrupt, we re-inject it.
5795	*/
5796	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5797	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5798	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5799	else
5800	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5801	}
5802
5803	switch (enmRaise)
5804	{
5805	case IEMXCPTRAISE_CURRENT_XCPT:
5806	case IEMXCPTRAISE_PREV_EVENT:
5807	{
5808	/* For software interrupts, we shall re-execute the instruction. */
5809	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5810	{
5811	RTGCUINTPTR GCPtrFaultAddress = 0;
5812
5813	/* If we are re-injecting an NMI, clear NMI blocking. */
5814	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5815	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5816
5817	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5818	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5819	{
5820	pSvmTransient->fVectoringPF = true;
5821	Log4Func(("IDT: Pending vectoring #PF due to delivery of Ext-Int/NMI. uCR2=%#RX64\n",
5822	pVCpu->cpum.GstCtx.cr2));
5823	}
5824	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5825	&& uIdtVector == X86_XCPT_PF)
5826	{
5827	/*
5828	* If the previous exception was a #PF, we need to recover the CR2 value.
5829	* This can't happen with shadow paging.
5830	*/
5831	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
5832	}
5833
5834	/*
5835	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5836	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5837	*/
5838	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5839	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflect);
5840	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5841
5842	Log4Func(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5843	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5844	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5845	}
5846	break;
5847	}
5848
5849	case IEMXCPTRAISE_REEXEC_INSTR:
5850	{
5851	Assert(rc == VINF_SUCCESS);
5852	break;
5853	}
5854
5855	case IEMXCPTRAISE_DOUBLE_FAULT:
5856	{
5857	/*
5858	* Determing a vectoring double #PF condition. Used later, when PGM evaluates
5859	* the second #PF as a guest #PF (and not a shadow #PF) and needs to be
5860	* converted into a #DF.
5861	*/
5862	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5863	{
5864	Log4Func(("IDT: Pending vectoring double #PF uCR2=%#RX64\n", pVCpu->cpum.GstCtx.cr2));
5865	pSvmTransient->fVectoringDoublePF = true;
5866	Assert(rc == VINF_SUCCESS);
5867	}
5868	else
5869	{
5870	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectConvertDF);
5871	hmR0SvmSetPendingXcptDF(pVCpu);
5872	rc = VINF_HM_DOUBLE_FAULT;
5873	}
5874	break;
5875	}
5876
5877	case IEMXCPTRAISE_TRIPLE_FAULT:
5878	{
5879	rc = VINF_EM_RESET;
5880	break;
5881	}
5882
5883	case IEMXCPTRAISE_CPU_HANG:
5884	{
5885	rc = VERR_EM_GUEST_CPU_HANG;
5886	break;
5887	}
5888
5889	default:
5890	AssertMsgFailedBreakStmt(("Bogus enmRaise value: %d (%#x)\n", enmRaise, enmRaise), rc = VERR_SVM_IPE_2);
5891	}
5892	}
5893	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5894	return rc;
5895	}
5896
5897
5898	/**
5899	* Advances the guest RIP by the number of bytes specified in @a cb.
5900	*
5901	* @param pVCpu The cross context virtual CPU structure.
5902	* @param cb RIP increment value in bytes.
5903	*/
5904	DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPUCC pVCpu, uint32_t cb)
5905	{
5906	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5907	pCtx->rip += cb;
5908
5909	/* Update interrupt shadow. */
5910	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
5911	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
5912	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
5913	}
5914
5915
5916	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5917	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5918	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5919
5920	/** @name \#VMEXIT handlers.
5921	* @{
5922	*/
5923
5924	/**
5925	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5926	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5927	*/
5928	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5929	{
5930	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5931
5932	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5933	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5934	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5935	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5936
5937	/*
5938	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to
5939	* signal -before- the timer fires if the current interrupt is our own timer or a some
5940	* other host interrupt. We also cannot examine what interrupt it is until the host
5941	* actually take the interrupt.
5942	*
5943	* Going back to executing guest code here unconditionally causes random scheduling
5944	* problems (observed on an AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5945	*/
5946	return VINF_EM_RAW_INTERRUPT;
5947	}
5948
5949
5950	/**
5951	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5952	*/
5953	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5954	{
5955	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5956
5957	VBOXSTRICTRC rcStrict;
5958	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5959	if (fSupportsNextRipSave)
5960	{
5961	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5962	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5963	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5964	rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
5965	}
5966	else
5967	{
5968	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5969	rcStrict = IEMExecOne(pVCpu);
5970	}
5971
5972	if (rcStrict == VINF_IEM_RAISED_XCPT)
5973	{
5974	rcStrict = VINF_SUCCESS;
5975	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5976	}
5977	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5978	return VBOXSTRICTRC_TODO(rcStrict);
5979	}
5980
5981
5982	/**
5983	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5984	*/
5985	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5986	{
5987	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5988
5989	VBOXSTRICTRC rcStrict;
5990	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5991	if (fSupportsNextRipSave)
5992	{
5993	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5994	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5995	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5996	rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
5997	}
5998	else
5999	{
6000	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6001	rcStrict = IEMExecOne(pVCpu);
6002	}
6003
6004	if (rcStrict == VINF_IEM_RAISED_XCPT)
6005	{
6006	rcStrict = VINF_SUCCESS;
6007	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6008	}
6009	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6010	return VBOXSTRICTRC_TODO(rcStrict);
6011	}
6012
6013
6014	/**
6015	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6016	*/
6017	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6018	{
6019	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6020
6021	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX);
6022	VBOXSTRICTRC rcStrict;
6023	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6024	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
6025	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6026	if (!pExitRec)
6027	{
6028	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6029	if (fSupportsNextRipSave)
6030	{
6031	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6032	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6033	rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
6034	}
6035	else
6036	{
6037	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6038	rcStrict = IEMExecOne(pVCpu);
6039	}
6040
6041	if (rcStrict == VINF_IEM_RAISED_XCPT)
6042	{
6043	rcStrict = VINF_SUCCESS;
6044	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6045	}
6046	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6047	}
6048	else
6049	{
6050	/*
6051	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6052	*/
6053	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6054
6055	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
6056	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
6057
6058	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6059
6060	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6061	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6062	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6063	}
6064	return VBOXSTRICTRC_TODO(rcStrict);
6065	}
6066
6067
6068	/**
6069	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6070	*/
6071	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6072	{
6073	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6074
6075	VBOXSTRICTRC rcStrict;
6076	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6077	if (fSupportsNextRipSave)
6078	{
6079	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
6080	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6081	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6082	rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
6083	}
6084	else
6085	{
6086	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6087	rcStrict = IEMExecOne(pVCpu);
6088	}
6089
6090	if (rcStrict == VINF_SUCCESS)
6091	pSvmTransient->fUpdateTscOffsetting = true;
6092	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6093	{
6094	rcStrict = VINF_SUCCESS;
6095	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6096	}
6097	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6098	return VBOXSTRICTRC_TODO(rcStrict);
6099	}
6100
6101
6102	/**
6103	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6104	*/
6105	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6106	{
6107	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6108
6109	VBOXSTRICTRC rcStrict;
6110	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6111	if (fSupportsNextRipSave)
6112	{
6113	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_TSC_AUX);
6114	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6115	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6116	rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
6117	}
6118	else
6119	{
6120	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6121	rcStrict = IEMExecOne(pVCpu);
6122	}
6123
6124	if (rcStrict == VINF_SUCCESS)
6125	pSvmTransient->fUpdateTscOffsetting = true;
6126	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6127	{
6128	rcStrict = VINF_SUCCESS;
6129	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6130	}
6131	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6132	return VBOXSTRICTRC_TODO(rcStrict);
6133	}
6134
6135
6136	/**
6137	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6138	*/
6139	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6140	{
6141	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6142
6143	VBOXSTRICTRC rcStrict;
6144	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6145	if (fSupportsNextRipSave)
6146	{
6147	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
6148	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6149	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6150	rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
6151	}
6152	else
6153	{
6154	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6155	rcStrict = IEMExecOne(pVCpu);
6156	}
6157
6158	if (rcStrict == VINF_IEM_RAISED_XCPT)
6159	{
6160	rcStrict = VINF_SUCCESS;
6161	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6162	}
6163	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6164	return VBOXSTRICTRC_TODO(rcStrict);
6165	}
6166
6167
6168	/**
6169	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6170	*/
6171	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6172	{
6173	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6174	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6175
6176	VBOXSTRICTRC rcStrict;
6177	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6178	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6179	if ( fSupportsDecodeAssists
6180	&& fSupportsNextRipSave)
6181	{
6182	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
6183	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6184	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6185	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6186	rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6187	}
6188	else
6189	{
6190	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6191	rcStrict = IEMExecOne(pVCpu);
6192	}
6193
6194	if (rcStrict == VINF_IEM_RAISED_XCPT)
6195	{
6196	rcStrict = VINF_SUCCESS;
6197	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6198	}
6199	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6200	return VBOXSTRICTRC_VAL(rcStrict);
6201	}
6202
6203
6204	/**
6205	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6206	*/
6207	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6208	{
6209	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6210
6211	VBOXSTRICTRC rcStrict;
6212	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6213	if (fSupportsNextRipSave)
6214	{
6215	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6216	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6217	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6218	rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
6219	}
6220	else
6221	{
6222	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6223	rcStrict = IEMExecOne(pVCpu);
6224	}
6225
6226	if ( rcStrict == VINF_EM_HALT
6227	\|\| rcStrict == VINF_SUCCESS)
6228	rcStrict = EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6229	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6230	{
6231	rcStrict = VINF_SUCCESS;
6232	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6233	}
6234	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6235	if (rcStrict != VINF_SUCCESS)
6236	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6237	return VBOXSTRICTRC_VAL(rcStrict);;
6238	}
6239
6240
6241	/**
6242	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6243	*/
6244	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6245	{
6246	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6247
6248	/*
6249	* If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
6250	* segment override prefix is present (and thus use the default segment DS). Otherwise, a
6251	* segment override prefix or other prefixes might be used, in which case we fallback to
6252	* IEMExecOne() to figure out.
6253	*/
6254	VBOXSTRICTRC rcStrict;
6255	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6256	uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
6257	if (cbInstr)
6258	{
6259	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
6260	rcStrict = IEMExecDecodedMonitor(pVCpu, cbInstr);
6261	}
6262	else
6263	{
6264	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6265	rcStrict = IEMExecOne(pVCpu);
6266	}
6267
6268	if (rcStrict == VINF_IEM_RAISED_XCPT)
6269	{
6270	rcStrict = VINF_SUCCESS;
6271	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6272	}
6273	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6274	return VBOXSTRICTRC_TODO(rcStrict);
6275	}
6276
6277
6278	/**
6279	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6280	*/
6281	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6282	{
6283	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6284
6285	VBOXSTRICTRC rcStrict;
6286	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6287	if (fSupportsNextRipSave)
6288	{
6289	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6290	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6291	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6292	rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
6293	}
6294	else
6295	{
6296	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6297	rcStrict = IEMExecOne(pVCpu);
6298	}
6299
6300	if ( rcStrict == VINF_EM_HALT
6301	&& EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
6302	rcStrict = VINF_SUCCESS;
6303	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6304	{
6305	rcStrict = VINF_SUCCESS;
6306	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6307	}
6308	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6309	return VBOXSTRICTRC_TODO(rcStrict);
6310	}
6311
6312
6313	/**
6314	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6315	* \#VMEXIT.
6316	*/
6317	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6318	{
6319	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6320	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6321	return VINF_EM_RESET;
6322	}
6323
6324
6325	/**
6326	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6327	*/
6328	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6329	{
6330	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6331	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6332	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6333	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6334	RT_NOREF(pVmcb);
6335	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6336	return VERR_SVM_UNEXPECTED_EXIT;
6337	}
6338
6339
6340	/**
6341	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6342	*/
6343	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6344	{
6345	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6346
6347	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6348	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6349	#ifdef VBOX_WITH_STATISTICS
6350	switch (pSvmTransient->u64ExitCode)
6351	{
6352	case SVM_EXIT_READ_CR0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
6353	case SVM_EXIT_READ_CR2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
6354	case SVM_EXIT_READ_CR3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
6355	case SVM_EXIT_READ_CR4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
6356	case SVM_EXIT_READ_CR8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
6357	}
6358	#endif
6359
6360	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6361	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6362	if ( fSupportsDecodeAssists
6363	&& fSupportsNextRipSave)
6364	{
6365	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6366	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6367	if (fMovCRx)
6368	{
6369	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR_MASK
6370	\| CPUMCTX_EXTRN_APIC_TPR);
6371	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6372	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6373	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6374	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6375	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6376	return VBOXSTRICTRC_VAL(rcStrict);
6377	}
6378	/* else: SMSW instruction, fall back below to IEM for this. */
6379	}
6380
6381	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6382	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6383	AssertMsg( rcStrict == VINF_SUCCESS
6384	\|\| rcStrict == VINF_PGM_SYNC_CR3
6385	\|\| rcStrict == VINF_IEM_RAISED_XCPT,
6386	("hmR0SvmExitReadCRx: IEMExecOne failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6387	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6388	if (rcStrict == VINF_IEM_RAISED_XCPT)
6389	{
6390	rcStrict = VINF_SUCCESS;
6391	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6392	}
6393	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6394	return VBOXSTRICTRC_TODO(rcStrict);
6395	}
6396
6397
6398	/**
6399	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6400	*/
6401	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6402	{
6403	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6404
6405	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6406	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6407	Assert(iCrReg <= 15);
6408
6409	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6410	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6411	bool fDecodedInstr = false;
6412	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6413	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6414	if ( fSupportsDecodeAssists
6415	&& fSupportsNextRipSave)
6416	{
6417	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6418	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6419	if (fMovCRx)
6420	{
6421	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4
6422	\| CPUMCTX_EXTRN_APIC_TPR);
6423	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6424	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6425	Log4Func(("Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6426	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6427	fDecodedInstr = true;
6428	}
6429	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6430	}
6431
6432	if (!fDecodedInstr)
6433	{
6434	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6435	Log4Func(("iCrReg=%#x\n", iCrReg));
6436	rcStrict = IEMExecOne(pVCpu);
6437	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6438	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6439	rcStrict = VERR_EM_INTERPRETER;
6440	}
6441
6442	if (rcStrict == VINF_SUCCESS)
6443	{
6444	switch (iCrReg)
6445	{
6446	case 0:
6447	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
6448	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
6449	break;
6450
6451	case 2:
6452	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
6453	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
6454	break;
6455
6456	case 3:
6457	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR3);
6458	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
6459	break;
6460
6461	case 4:
6462	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
6463	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
6464	break;
6465
6466	case 8:
6467	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6468	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
6469	break;
6470
6471	default:
6472	{
6473	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6474	pSvmTransient->u64ExitCode, iCrReg));
6475	break;
6476	}
6477	}
6478	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6479	}
6480	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6481	{
6482	rcStrict = VINF_SUCCESS;
6483	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6484	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6485	}
6486	else
6487	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_SYNC_CR3);
6488	return VBOXSTRICTRC_TODO(rcStrict);
6489	}
6490
6491
6492	/**
6493	* \#VMEXIT helper for read MSRs, see hmR0SvmExitMsr.
6494	*
6495	* @returns Strict VBox status code.
6496	* @param pVCpu The cross context virtual CPU structure.
6497	* @param pVmcb Pointer to the VM control block.
6498	*/
6499	static VBOXSTRICTRC hmR0SvmExitReadMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
6500	{
6501	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6502	Log4Func(("idMsr=%#RX32\n", pVCpu->cpum.GstCtx.ecx));
6503
6504	VBOXSTRICTRC rcStrict;
6505	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6506	if (fSupportsNextRipSave)
6507	{
6508	/** @todo Optimize this: Only retrieve the MSR bits we need here. CPUMAllMsrs.cpp
6509	* can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
6510	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6511	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6512	rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
6513	}
6514	else
6515	{
6516	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6517	rcStrict = IEMExecOne(pVCpu);
6518	}
6519
6520	AssertMsg( rcStrict == VINF_SUCCESS
6521	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6522	\|\| rcStrict == VINF_CPUM_R3_MSR_READ,
6523	("hmR0SvmExitReadMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6524
6525	if (rcStrict == VINF_IEM_RAISED_XCPT)
6526	{
6527	rcStrict = VINF_SUCCESS;
6528	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6529	}
6530	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6531	return rcStrict;
6532	}
6533
6534
6535	/**
6536	* \#VMEXIT helper for write MSRs, see hmR0SvmExitMsr.
6537	*
6538	* @returns Strict VBox status code.
6539	* @param pVCpu The cross context virtual CPU structure.
6540	* @param pVmcb Pointer to the VM control block.
6541	* @param pSvmTransient Pointer to the SVM-transient structure.
6542	*/
6543	static VBOXSTRICTRC hmR0SvmExitWriteMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMTRANSIENT pSvmTransient)
6544	{
6545	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6546	uint32_t const idMsr = pCtx->ecx;
6547	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6548	Log4Func(("idMsr=%#RX32\n", idMsr));
6549
6550	/*
6551	* Handle TPR patching MSR writes.
6552	* We utilitize the LSTAR MSR for patching.
6553	*/
6554	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6555	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
6556	&& idMsr == MSR_K8_LSTAR)
6557	{
6558	unsigned cbInstr;
6559	if (fSupportsNextRipSave)
6560	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6561	else
6562	{
6563	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6564	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6565	if ( rc == VINF_SUCCESS
6566	&& pDis->pCurInstr->uOpcode == OP_WRMSR)
6567	Assert(cbInstr > 0);
6568	else
6569	cbInstr = 0;
6570	}
6571
6572	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6573	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6574	{
6575	int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6576	AssertRCReturn(rc, rc);
6577	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6578	}
6579
6580	int rc = VINF_SUCCESS;
6581	hmR0SvmAdvanceRip(pVCpu, cbInstr);
6582	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6583	return rc;
6584	}
6585
6586	/*
6587	* Handle regular MSR writes.
6588	*/
6589	VBOXSTRICTRC rcStrict;
6590	if (fSupportsNextRipSave)
6591	{
6592	/** @todo Optimize this: We don't need to get much of the MSR state here
6593	* since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and
6594	* clear the applicable extern flags. */
6595	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6596	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6597	rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
6598	}
6599	else
6600	{
6601	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6602	rcStrict = IEMExecOne(pVCpu);
6603	}
6604
6605	AssertMsg( rcStrict == VINF_SUCCESS
6606	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6607	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE,
6608	("hmR0SvmExitWriteMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6609
6610	if (rcStrict == VINF_SUCCESS)
6611	{
6612	/* If this is an X2APIC WRMSR access, update the APIC TPR state. */
6613	if ( idMsr >= MSR_IA32_X2APIC_START
6614	&& idMsr <= MSR_IA32_X2APIC_END)
6615	{
6616	/*
6617	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest().
6618	* When full APIC register virtualization is implemented we'll have to make sure
6619	* APIC state is saved from the VMCB before IEM changes it.
6620	*/
6621	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6622	}
6623	else
6624	{
6625	switch (idMsr)
6626	{
6627	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6628	case MSR_K6_EFER: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR); break;
6629	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
6630	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
6631	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6632	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6633	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6634	}
6635	}
6636	}
6637	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6638	{
6639	rcStrict = VINF_SUCCESS;
6640	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6641	}
6642	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6643	return rcStrict;
6644	}
6645
6646
6647	/**
6648	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6649	* \#VMEXIT.
6650	*/
6651	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6652	{
6653	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6654
6655	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6656	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ)
6657	return VBOXSTRICTRC_TODO(hmR0SvmExitReadMsr(pVCpu, pVmcb));
6658
6659	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE);
6660	return VBOXSTRICTRC_TODO(hmR0SvmExitWriteMsr(pVCpu, pVmcb, pSvmTransient));
6661	}
6662
6663
6664	/**
6665	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6666	*/
6667	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6668	{
6669	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6670	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6671
6672	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6673
6674	/** @todo Stepping with nested-guest. */
6675	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6676	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6677	{
6678	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6679	if (pSvmTransient->fWasGuestDebugStateActive)
6680	{
6681	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6682	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6683	return VERR_SVM_UNEXPECTED_EXIT;
6684	}
6685
6686	/*
6687	* Lazy DR0-3 loading.
6688	*/
6689	if (!pSvmTransient->fWasHyperDebugStateActive)
6690	{
6691	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6692	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6693
6694	/* Don't intercept DRx read and writes. */
6695	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6696	pVmcb->ctrl.u16InterceptRdDRx = 0;
6697	pVmcb->ctrl.u16InterceptWrDRx = 0;
6698	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6699
6700	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6701	VMMRZCallRing3Disable(pVCpu);
6702	HM_DISABLE_PREEMPT(pVCpu);
6703
6704	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6705	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6706	Assert(CPUMIsGuestDebugStateActive(pVCpu));
6707
6708	HM_RESTORE_PREEMPT();
6709	VMMRZCallRing3Enable(pVCpu);
6710
6711	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6712	return VINF_SUCCESS;
6713	}
6714	}
6715
6716	/*
6717	* Interpret the read/writing of DRx.
6718	*/
6719	/** @todo Decode assist. */
6720	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6721	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6722	if (RT_LIKELY(rc == VINF_SUCCESS))
6723	{
6724	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6725	/** @todo CPUM should set this flag! */
6726	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
6727	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6728	}
6729	else
6730	Assert(rc == VERR_EM_INTERPRETER);
6731	return VBOXSTRICTRC_TODO(rc);
6732	}
6733
6734
6735	/**
6736	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6737	*/
6738	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6739	{
6740	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6741	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6742	int rc = hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
6743	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6744	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6745	return rc;
6746	}
6747
6748
6749	/**
6750	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6751	*/
6752	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6753	{
6754	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6755	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6756
6757	/** @todo decode assists... */
6758	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6759	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6760	{
6761	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6762	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6763	Log4Func(("New XCR0=%#RX64 fLoadSaveGuestXcr0=%RTbool (cr4=%#RX64)\n", pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0,
6764	pCtx->cr4));
6765	}
6766	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6767	{
6768	rcStrict = VINF_SUCCESS;
6769	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6770	}
6771	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6772	return VBOXSTRICTRC_TODO(rcStrict);
6773	}
6774
6775
6776	/**
6777	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6778	*/
6779	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6780	{
6781	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6782	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK);
6783
6784	/* I/O operation lookup arrays. */
6785	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6786	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6787	the result (in AL/AX/EAX). */
6788	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6789	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6790	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6791
6792	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6793
6794	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6795	SVMIOIOEXITINFO IoExitInfo;
6796	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6797	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6798	uint32_t cbValue = s_aIOSize[uIOWidth];
6799	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6800
6801	if (RT_UNLIKELY(!cbValue))
6802	{
6803	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6804	return VERR_EM_INTERPRETER;
6805	}
6806
6807	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
6808	VBOXSTRICTRC rcStrict;
6809	PCEMEXITREC pExitRec = NULL;
6810	if ( !pVCpu->hm.s.fSingleInstruction
6811	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
6812	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6813	!IoExitInfo.n.u1Str
6814	? IoExitInfo.n.u1Type == SVM_IOIO_READ
6815	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
6816	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
6817	: IoExitInfo.n.u1Type == SVM_IOIO_READ
6818	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
6819	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
6820	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6821	if (!pExitRec)
6822	{
6823	bool fUpdateRipAlready = false;
6824	if (IoExitInfo.n.u1Str)
6825	{
6826	/* INS/OUTS - I/O String instruction. */
6827	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6828	* in EXITINFO1? Investigate once this thing is up and running. */
6829	Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6830	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6831	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6832	static IEMMODE const s_aenmAddrMode[8] =
6833	{
6834	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6835	};
6836	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6837	if (enmAddrMode != (IEMMODE)-1)
6838	{
6839	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6840	if (cbInstr <= 15 && cbInstr >= 1)
6841	{
6842	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6843	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6844	{
6845	/* Don't know exactly how to detect whether u3Seg is valid, currently
6846	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6847	2384 Opterons when only checking NRIP. */
6848	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6849	if ( fSupportsNextRipSave
6850	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6851	{
6852	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
6853	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
6854	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6855	IoExitInfo.n.u3Seg, true /fIoChecked/);
6856	}
6857	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
6858	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6859	X86_SREG_DS, true /fIoChecked/);
6860	else
6861	rcStrict = IEMExecOne(pVCpu);
6862	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6863	}
6864	else
6865	{
6866	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
6867	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6868	true /fIoChecked/);
6869	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6870	}
6871	}
6872	else
6873	{
6874	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6875	rcStrict = IEMExecOne(pVCpu);
6876	}
6877	}
6878	else
6879	{
6880	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6881	rcStrict = IEMExecOne(pVCpu);
6882	}
6883	fUpdateRipAlready = true;
6884	}
6885	else
6886	{
6887	/* IN/OUT - I/O instruction. */
6888	Assert(!IoExitInfo.n.u1Rep);
6889
6890	uint8_t const cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6891	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6892	{
6893	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6894	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6895	&& !pCtx->eflags.Bits.u1TF)
6896	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue, pCtx->eax & uAndVal);
6897	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6898	}
6899	else
6900	{
6901	uint32_t u32Val = 0;
6902	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6903	if (IOM_SUCCESS(rcStrict))
6904	{
6905	/* Save result of I/O IN instr. in AL/AX/EAX. */
6906	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6907	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6908	}
6909	else if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6910	&& !pCtx->eflags.Bits.u1TF)
6911	rcStrict = EMRZSetPendingIoPortRead(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue);
6912
6913	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6914	}
6915	}
6916
6917	if (IOM_SUCCESS(rcStrict))
6918	{
6919	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6920	if (!fUpdateRipAlready)
6921	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6922
6923	/*
6924	* If any I/O breakpoints are armed, we need to check if one triggered
6925	* and take appropriate action.
6926	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6927	*/
6928	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6929	* execution engines about whether hyper BPs and such are pending. */
6930	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
6931	uint32_t const uDr7 = pCtx->dr[7];
6932	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6933	&& X86_DR7_ANY_RW_IO(uDr7)
6934	&& (pCtx->cr4 & X86_CR4_DE))
6935	\|\| DBGFBpIsHwIoArmed(pVM)))
6936	{
6937	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6938	VMMRZCallRing3Disable(pVCpu);
6939	HM_DISABLE_PREEMPT(pVCpu);
6940
6941	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6942	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6943
6944	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, &pVCpu->cpum.GstCtx, IoExitInfo.n.u16Port, cbValue);
6945	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6946	{
6947	/* Raise #DB. */
6948	pVmcb->guest.u64DR6 = pCtx->dr[6];
6949	pVmcb->guest.u64DR7 = pCtx->dr[7];
6950	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6951	hmR0SvmSetPendingXcptDB(pVCpu);
6952	}
6953	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6954	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6955	else if ( rcStrict2 != VINF_SUCCESS
6956	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6957	rcStrict = rcStrict2;
6958	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6959
6960	HM_RESTORE_PREEMPT();
6961	VMMRZCallRing3Enable(pVCpu);
6962	}
6963
6964	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6965	}
6966
6967	#ifdef VBOX_STRICT
6968	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6969	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
6970	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6971	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6972	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
6973	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
6974	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6975	else
6976	{
6977	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6978	* statuses, that the VMM device and some others may return. See
6979	* IOM_SUCCESS() for guidance. */
6980	AssertMsg( RT_FAILURE(rcStrict)
6981	\|\| rcStrict == VINF_SUCCESS
6982	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6983	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6984	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6985	\|\| rcStrict == VINF_EM_RAW_TO_R3
6986	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6987	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6988	}
6989	#endif
6990	}
6991	else
6992	{
6993	/*
6994	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6995	*/
6996	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6997	STAM_COUNTER_INC(!IoExitInfo.n.u1Str
6998	? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
6999	: IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
7000	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
7001	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "",
7002	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth));
7003
7004	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
7005	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7006
7007	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
7008	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
7009	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7010	}
7011	return VBOXSTRICTRC_TODO(rcStrict);
7012	}
7013
7014
7015	/**
7016	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
7017	*/
7018	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7019	{
7020	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7021	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7022	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7023
7024	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7025	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7026	Assert(pVM->hm.s.fNestedPaging);
7027
7028	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
7029	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7030	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
7031	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /* Note! High bits in EXITINFO1 may contain additional info and are
7032	thus intentionally not copied into u32ErrCode. */
7033
7034	Log4Func(("#NPF at CS:RIP=%04x:%#RX64 GCPhysFaultAddr=%RGp ErrCode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr,
7035	u32ErrCode));
7036
7037	/*
7038	* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
7039	*/
7040	if ( pVM->hm.s.fTprPatchingAllowed
7041	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
7042	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
7043	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
7044	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7045	&& !CPUMIsGuestInLongModeEx(pCtx)
7046	&& !CPUMGetGuestCPL(pVCpu)
7047	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7048	{
7049	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7050	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7051
7052	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
7053	{
7054	/* Only attempt to patch the instruction once. */
7055	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7056	if (!pPatch)
7057	return VINF_EM_HM_PATCH_TPR_INSTR;
7058	}
7059	}
7060
7061	/*
7062	* Determine the nested paging mode.
7063	*/
7064	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
7065	PGMMODE const enmNestedPagingMode = PGMGetHostMode(pVM);
7066
7067	/*
7068	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
7069	*/
7070	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
7071	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
7072	{
7073	/*
7074	* If event delivery causes an MMIO #NPF, go back to instruction emulation as otherwise
7075	* injecting the original pending event would most likely cause the same MMIO #NPF.
7076	*/
7077	if (pVCpu->hm.s.Event.fPending)
7078	{
7079	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7080	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7081	}
7082
7083	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
7084	VBOXSTRICTRC rcStrict;
7085	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
7086	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
7087	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
7088	if (!pExitRec)
7089	{
7090
7091	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
7092	u32ErrCode);
7093
7094	/*
7095	* If we succeed, resume guest execution.
7096	*
7097	* If we fail in interpreting the instruction because we couldn't get the guest
7098	* physical address of the page containing the instruction via the guest's page
7099	* tables (we would invalidate the guest page in the host TLB), resume execution
7100	* which would cause a guest page fault to let the guest handle this weird case.
7101	*
7102	* See @bugref{6043}.
7103	*/
7104	if ( rcStrict == VINF_SUCCESS
7105	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
7106	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
7107	{
7108	/* Successfully handled MMIO operation. */
7109	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
7110	rcStrict = VINF_SUCCESS;
7111	}
7112	}
7113	else
7114	{
7115	/*
7116	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
7117	*/
7118	Assert(pCtx == &pVCpu->cpum.GstCtx);
7119	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7120	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
7121	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr));
7122
7123	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
7124	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7125
7126	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
7127	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
7128	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7129	}
7130	return VBOXSTRICTRC_TODO(rcStrict);
7131	}
7132
7133	/*
7134	* Nested page-fault.
7135	*/
7136	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
7137	int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
7138	TRPMResetTrap(pVCpu);
7139
7140	Log4Func(("#NPF: PGMR0Trap0eHandlerNestedPaging returns %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
7141
7142	/*
7143	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
7144	*/
7145	if ( rc == VINF_SUCCESS
7146	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7147	\|\| rc == VERR_PAGE_NOT_PRESENT)
7148	{
7149	/* We've successfully synced our shadow page tables. */
7150	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7151	rc = VINF_SUCCESS;
7152	}
7153
7154	/*
7155	* If delivering an event causes an #NPF (and not MMIO), we shall resolve the fault and
7156	* re-inject the original event.
7157	*/
7158	if (pVCpu->hm.s.Event.fPending)
7159	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflectNPF);
7160
7161	return rc;
7162	}
7163
7164
7165	/**
7166	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
7167	* \#VMEXIT.
7168	*/
7169	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7170	{
7171	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7172	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7173
7174	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7175	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7176	hmR0SvmClearIntWindowExiting(pVCpu, pVmcb);
7177
7178	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7179	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7180	return VINF_SUCCESS;
7181	}
7182
7183
7184	/**
7185	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7186	* \#VMEXIT.
7187	*/
7188	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7189	{
7190	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7191	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7192
7193	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7194	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7195	#endif
7196
7197	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7198	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7199	{
7200	/*
7201	* AMD-V provides us with the exception which caused the TS; we collect
7202	* the information in the call to hmR0SvmCheckExitDueToEventDelivery().
7203	*/
7204	Log4Func(("TS occurred during event delivery\n"));
7205	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7206	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7207	}
7208
7209	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7210	* emulation. */
7211	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7212	return VERR_EM_INTERPRETER;
7213	}
7214
7215
7216	/**
7217	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7218	*/
7219	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7220	{
7221	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7222	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7223
7224	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7225	if (pVM->hm.s.fTprPatchingAllowed)
7226	{
7227	int rc = hmEmulateSvmMovTpr(pVM, pVCpu);
7228	if (rc != VERR_NOT_FOUND)
7229	{
7230	Log4Func(("hmEmulateSvmMovTpr returns %Rrc\n", rc));
7231	return rc;
7232	}
7233	}
7234
7235	if (EMAreHypercallInstructionsEnabled(pVCpu))
7236	{
7237	unsigned cbInstr;
7238	if (hmR0SvmSupportsNextRipSave(pVCpu))
7239	{
7240	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7241	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7242	}
7243	else
7244	{
7245	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
7246	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7247	if ( rc == VINF_SUCCESS
7248	&& pDis->pCurInstr->uOpcode == OP_VMMCALL)
7249	Assert(cbInstr > 0);
7250	else
7251	cbInstr = 0;
7252	}
7253
7254	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
7255	if (RT_SUCCESS(rcStrict))
7256	{
7257	/* Only update the RIP if we're continuing guest execution and not in the case
7258	of say VINF_GIM_R3_HYPERCALL. */
7259	if (rcStrict == VINF_SUCCESS)
7260	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7261
7262	return VBOXSTRICTRC_VAL(rcStrict);
7263	}
7264	else
7265	Log4Func(("GIMHypercall returns %Rrc -> #UD\n", VBOXSTRICTRC_VAL(rcStrict)));
7266	}
7267
7268	hmR0SvmSetPendingXcptUD(pVCpu);
7269	return VINF_SUCCESS;
7270	}
7271
7272
7273	/**
7274	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7275	*/
7276	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7277	{
7278	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7279
7280	unsigned cbInstr;
7281	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7282	if (fSupportsNextRipSave)
7283	{
7284	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7285	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7286	}
7287	else
7288	{
7289	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
7290	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7291	if ( rc == VINF_SUCCESS
7292	&& pDis->pCurInstr->uOpcode == OP_PAUSE)
7293	Assert(cbInstr > 0);
7294	else
7295	cbInstr = 0;
7296	}
7297
7298	/** @todo The guest has likely hit a contended spinlock. We might want to
7299	* poke a schedule different guest VCPU. */
7300	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7301	return VINF_EM_RAW_INTERRUPT;
7302	}
7303
7304
7305	/**
7306	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7307	* \#VMEXIT.
7308	*/
7309	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7310	{
7311	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7312	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
7313	Assert(!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE));
7314
7315	Log4Func(("Raising IRQ 13 in response to #FERR\n"));
7316	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7317	}
7318
7319
7320	/**
7321	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7322	*/
7323	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7324	{
7325	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7326
7327	/* Clear NMI blocking. */
7328	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7329	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7330
7331	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7332	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7333	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_IRET);
7334
7335	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7336	return VINF_SUCCESS;
7337	}
7338
7339
7340	/**
7341	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7342	* Conditional \#VMEXIT.
7343	*/
7344	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7345	{
7346	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7347	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7348	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7349
7350	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7351	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7352	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7353	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7354	uint32_t uErrCode = pVmcb->ctrl.u64ExitInfo1;
7355	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7356
7357	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7358	if (pVM->hm.s.fNestedPaging)
7359	{
7360	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7361	if ( !pSvmTransient->fVectoringDoublePF
7362	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7363	{
7364	/* A genuine guest #PF, reflect it to the guest. */
7365	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7366	Log4Func(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RX64 ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7367	uFaultAddress, uErrCode));
7368	}
7369	else
7370	{
7371	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7372	hmR0SvmSetPendingXcptDF(pVCpu);
7373	Log4Func(("Pending #DF due to vectoring #PF. NP\n"));
7374	}
7375	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7376	return VINF_SUCCESS;
7377	}
7378	#endif
7379
7380	Assert(!pVM->hm.s.fNestedPaging);
7381
7382	/*
7383	* TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
7384	*/
7385	if ( pVM->hm.s.fTprPatchingAllowed
7386	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7387	&& !(uErrCode & X86_TRAP_PF_P) /* Not present. */
7388	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7389	&& !CPUMIsGuestInLongModeEx(pCtx)
7390	&& !CPUMGetGuestCPL(pVCpu)
7391	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7392	{
7393	RTGCPHYS GCPhysApicBase;
7394	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7395	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7396
7397	/* Check if the page at the fault-address is the APIC base. */
7398	RTGCPHYS GCPhysPage;
7399	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7400	if ( rc2 == VINF_SUCCESS
7401	&& GCPhysPage == GCPhysApicBase)
7402	{
7403	/* Only attempt to patch the instruction once. */
7404	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7405	if (!pPatch)
7406	return VINF_EM_HM_PATCH_TPR_INSTR;
7407	}
7408	}
7409
7410	Log4Func(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7411	pCtx->rip, uErrCode, pCtx->cr3));
7412
7413	/*
7414	* If it's a vectoring #PF, emulate injecting the original event injection as
7415	* PGMTrap0eHandler() is incapable of differentiating between instruction emulation and
7416	* event injection that caused a #PF. See @bugref{6607}.
7417	*/
7418	if (pSvmTransient->fVectoringPF)
7419	{
7420	Assert(pVCpu->hm.s.Event.fPending);
7421	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7422	}
7423
7424	TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
7425	int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7426
7427	Log4Func(("#PF: rc=%Rrc\n", rc));
7428
7429	if (rc == VINF_SUCCESS)
7430	{
7431	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7432	TRPMResetTrap(pVCpu);
7433	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7434	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7435	return rc;
7436	}
7437
7438	if (rc == VINF_EM_RAW_GUEST_TRAP)
7439	{
7440	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7441
7442	/*
7443	* If a nested-guest delivers a #PF and that causes a #PF which is -not- a shadow #PF,
7444	* we should simply forward the #PF to the guest and is up to the nested-hypervisor to
7445	* determine whether it is a nested-shadow #PF or a #DF, see @bugref{7243#c121}.
7446	*/
7447	if ( !pSvmTransient->fVectoringDoublePF
7448	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7449	{
7450	/* It's a guest (or nested-guest) page fault and needs to be reflected. */
7451	uErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7452	TRPMResetTrap(pVCpu);
7453
7454	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7455	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
7456	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7457	&& CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
7458	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_XCPT_PF, uErrCode, uFaultAddress));
7459	#endif
7460
7461	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7462	}
7463	else
7464	{
7465	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7466	TRPMResetTrap(pVCpu);
7467	hmR0SvmSetPendingXcptDF(pVCpu);
7468	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
7469	}
7470
7471	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7472	return VINF_SUCCESS;
7473	}
7474
7475	TRPMResetTrap(pVCpu);
7476	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7477	return rc;
7478	}
7479
7480
7481	/**
7482	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7483	* Conditional \#VMEXIT.
7484	*/
7485	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7486	{
7487	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7488	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7489	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7490
7491	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7492	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7493	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7494
7495	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7496	if (pVCpu->hm.s.fGIMTrapXcptUD)
7497	{
7498	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7499	uint8_t cbInstr = 0;
7500	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, &pVCpu->cpum.GstCtx, NULL /* pDis */, &cbInstr);
7501	if (rcStrict == VINF_SUCCESS)
7502	{
7503	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7504	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7505	rc = VINF_SUCCESS;
7506	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7507	}
7508	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7509	rc = VINF_SUCCESS;
7510	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7511	rc = VINF_GIM_R3_HYPERCALL;
7512	else
7513	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7514	}
7515
7516	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7517	if (RT_FAILURE(rc))
7518	{
7519	hmR0SvmSetPendingXcptUD(pVCpu);
7520	rc = VINF_SUCCESS;
7521	}
7522
7523	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7524	return rc;
7525	}
7526
7527
7528	/**
7529	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7530	* Conditional \#VMEXIT.
7531	*/
7532	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7533	{
7534	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7535	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7536	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7537
7538	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7539	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7540
7541	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7542	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7543
7544	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7545
7546	if (!(pCtx->cr0 & X86_CR0_NE))
7547	{
7548	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7549	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7550	unsigned cbInstr;
7551	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
7552	if (RT_SUCCESS(rc))
7553	{
7554	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7555	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7556	if (RT_SUCCESS(rc))
7557	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7558	}
7559	else
7560	Log4Func(("EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7561	return rc;
7562	}
7563
7564	hmR0SvmSetPendingXcptMF(pVCpu);
7565	return VINF_SUCCESS;
7566	}
7567
7568
7569	/**
7570	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7571	* \#VMEXIT.
7572	*/
7573	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7574	{
7575	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7576	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7577	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7578	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7579
7580	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7581	{
7582	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7583	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7584	}
7585
7586	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7587
7588	/*
7589	* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data
7590	* breakpoint). However, for both cases DR6 and DR7 are updated to what the exception
7591	* handler expects. See AMD spec. 15.12.2 "#DB (Debug)".
7592	*/
7593	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7594	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7595	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7596	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7597	if (rc == VINF_EM_RAW_GUEST_TRAP)
7598	{
7599	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7600	if (CPUMIsHyperDebugStateActive(pVCpu))
7601	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7602
7603	/* Reflect the exception back to the guest. */
7604	hmR0SvmSetPendingXcptDB(pVCpu);
7605	rc = VINF_SUCCESS;
7606	}
7607
7608	/*
7609	* Update DR6.
7610	*/
7611	if (CPUMIsHyperDebugStateActive(pVCpu))
7612	{
7613	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7614	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7615	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7616	}
7617	else
7618	{
7619	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7620	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7621	}
7622
7623	return rc;
7624	}
7625
7626
7627	/**
7628	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7629	* Conditional \#VMEXIT.
7630	*/
7631	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7632	{
7633	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7634	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7635	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC);
7636
7637	SVMEVENT Event;
7638	Event.u = 0;
7639	Event.n.u1Valid = 1;
7640	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7641	Event.n.u8Vector = X86_XCPT_AC;
7642	Event.n.u1ErrorCodeValid = 1;
7643	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7644	return VINF_SUCCESS;
7645	}
7646
7647
7648	/**
7649	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7650	* Conditional \#VMEXIT.
7651	*/
7652	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7653	{
7654	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7655	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7656	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7657	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
7658
7659	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7660	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7661	if (rc == VINF_EM_RAW_GUEST_TRAP)
7662	{
7663	SVMEVENT Event;
7664	Event.u = 0;
7665	Event.n.u1Valid = 1;
7666	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7667	Event.n.u8Vector = X86_XCPT_BP;
7668	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7669	}
7670
7671	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7672	return rc;
7673	}
7674
7675
7676	/**
7677	* Hacks its way around the lovely mesa driver's backdoor accesses.
7678	*
7679	* @sa hmR0VmxHandleMesaDrvGp
7680	*/
7681	static int hmR0SvmHandleMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7682	{
7683	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK);
7684	Log(("hmR0SvmHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n",
7685	pVmcb->guest.CS.u16Sel, pVmcb->guest.u64RIP, pCtx->rcx, pCtx->rbx));
7686	RT_NOREF(pCtx, pVmcb);
7687
7688	/* For now we'll just skip the instruction. */
7689	hmR0SvmAdvanceRip(pVCpu, 1);
7690	return VINF_SUCCESS;
7691	}
7692
7693
7694	/**
7695	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
7696	* backdoor logging w/o checking what it is running inside.
7697	*
7698	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
7699	* backdoor port and magic numbers loaded in registers.
7700	*
7701	* @returns true if it is, false if it isn't.
7702	* @sa hmR0VmxIsMesaDrvGp
7703	*/
7704	DECLINLINE(bool) hmR0SvmIsMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7705	{
7706	/* Check magic and port. */
7707	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RCX)));
7708	/Log8(("hmR0SvmIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax, pCtx->rdx));/
7709	if (pCtx->dx != UINT32_C(0x5658))
7710	return false;
7711	if ((pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax) != UINT32_C(0x564d5868))
7712	return false;
7713
7714	/* Check that it is #GP(0). */
7715	if (pVmcb->ctrl.u64ExitInfo1 != 0)
7716	return false;
7717
7718	/* Flat ring-3 CS. */
7719	/Log8(("hmR0SvmIsMesaDrvGp: u8CPL=%d base=%RX64\n", pVmcb->guest.u8CPL, pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base));/
7720	if (pVmcb->guest.u8CPL != 3)
7721	return false;
7722	if ((pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base) != 0)
7723	return false;
7724
7725	/* 0xed: IN eAX,dx */
7726	if (pVmcb->ctrl.cbInstrFetched < 1) /* unlikely, it turns out. */
7727	{
7728	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_GPRS_MASK
7729	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7730	uint8_t abInstr[1];
7731	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
7732	/Log8(("hmR0SvmIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0])); /
7733	if (RT_FAILURE(rc))
7734	return false;
7735	if (abInstr[0] != 0xed)
7736	return false;
7737	}
7738	else
7739	{
7740	/Log8(("hmR0SvmIsMesaDrvGp: %#x\n", pVmcb->ctrl.abInstr));/
7741	if (pVmcb->ctrl.abInstr[0] != 0xed)
7742	return false;
7743	}
7744	return true;
7745	}
7746
7747
7748	/**
7749	* \#VMEXIT handler for general protection faults (SVM_EXIT_XCPT_BP).
7750	* Conditional \#VMEXIT.
7751	*/
7752	HMSVM_EXIT_DECL hmR0SvmExitXcptGP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7753	{
7754	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7755	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7756	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
7757
7758	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7759	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7760
7761	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7762	if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
7763	\|\| !hmR0SvmIsMesaDrvGp(pVCpu, pCtx, pVmcb))
7764	{
7765	SVMEVENT Event;
7766	Event.u = 0;
7767	Event.n.u1Valid = 1;
7768	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7769	Event.n.u8Vector = X86_XCPT_GP;
7770	Event.n.u1ErrorCodeValid = 1;
7771	Event.n.u32ErrorCode = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
7772	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7773	return VINF_SUCCESS;
7774	}
7775	return hmR0SvmHandleMesaDrvGp(pVCpu, pCtx, pVmcb);
7776	}
7777
7778
7779	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
7780	/**
7781	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7782	*/
7783	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7784	{
7785	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7786	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7787
7788	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7789	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7790	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7791	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7792	Assert(uVector <= X86_XCPT_LAST);
7793	Log4Func(("uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7794
7795	SVMEVENT Event;
7796	Event.u = 0;
7797	Event.n.u1Valid = 1;
7798	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7799	Event.n.u8Vector = uVector;
7800	switch (uVector)
7801	{
7802	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7803	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7804	case X86_XCPT_DF:
7805	case X86_XCPT_TS:
7806	case X86_XCPT_NP:
7807	case X86_XCPT_SS:
7808	case X86_XCPT_GP:
7809	case X86_XCPT_AC:
7810	{
7811	Event.n.u1ErrorCodeValid = 1;
7812	Event.n.u32ErrorCode = uErrCode;
7813	break;
7814	}
7815	}
7816
7817	#ifdef VBOX_WITH_STATISTICS
7818	switch (uVector)
7819	{
7820	case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE); break;
7821	case X86_XCPT_DB: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB); break;
7822	case X86_XCPT_BP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); break;
7823	case X86_XCPT_OF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7824	case X86_XCPT_BR: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBR); break;
7825	case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD); break;
7826	case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7827	case X86_XCPT_DF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDF); break;
7828	case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS); break;
7829	case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP); break;
7830	case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS); break;
7831	case X86_XCPT_GP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP); break;
7832	case X86_XCPT_PF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF); break;
7833	case X86_XCPT_MF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); break;
7834	case X86_XCPT_AC: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC); break;
7835	case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF); break;
7836	default:
7837	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
7838	break;
7839	}
7840	#endif
7841
7842	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7843	return VINF_SUCCESS;
7844	}
7845	#endif
7846
7847	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7848	/**
7849	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7850	*/
7851	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7852	{
7853	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7854
7855	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7856	Assert(pVmcb);
7857	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7858
7859	VBOXSTRICTRC rcStrict;
7860	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7861	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7862	if (fSupportsNextRipSave)
7863	{
7864	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7865	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7866	rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7867	}
7868	else
7869	{
7870	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7871	rcStrict = IEMExecOne(pVCpu);
7872	}
7873
7874	if (rcStrict == VINF_SUCCESS)
7875	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7876	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7877	{
7878	rcStrict = VINF_SUCCESS;
7879	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7880	}
7881	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7882	return VBOXSTRICTRC_TODO(rcStrict);
7883	}
7884
7885
7886	/**
7887	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7888	*/
7889	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7890	{
7891	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7892
7893	/*
7894	* When VGIF is not used we always intercept STGI instructions. When VGIF is used,
7895	* we only intercept STGI when events are pending for GIF to become 1.
7896	*/
7897	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7898	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
7899	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_STGI);
7900
7901	VBOXSTRICTRC rcStrict;
7902	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7903	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7904	if (fSupportsNextRipSave)
7905	{
7906	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7907	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7908	rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7909	}
7910	else
7911	{
7912	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7913	rcStrict = IEMExecOne(pVCpu);
7914	}
7915
7916	if (rcStrict == VINF_SUCCESS)
7917	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7918	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7919	{
7920	rcStrict = VINF_SUCCESS;
7921	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7922	}
7923	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7924	return VBOXSTRICTRC_TODO(rcStrict);
7925	}
7926
7927
7928	/**
7929	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7930	*/
7931	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7932	{
7933	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7934
7935	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7936	Assert(pVmcb);
7937	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7938
7939	VBOXSTRICTRC rcStrict;
7940	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7941	uint64_t const fImport = CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_KERNEL_GS_BASE
7942	\| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR \| CPUMCTX_EXTRN_SYSCALL_MSRS
7943	\| CPUMCTX_EXTRN_SYSENTER_MSRS;
7944	if (fSupportsNextRipSave)
7945	{
7946	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7947	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7948	rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7949	}
7950	else
7951	{
7952	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7953	rcStrict = IEMExecOne(pVCpu);
7954	}
7955
7956	if (rcStrict == VINF_SUCCESS)
7957	{
7958	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS \| HM_CHANGED_GUEST_GS
7959	\| HM_CHANGED_GUEST_TR \| HM_CHANGED_GUEST_LDTR
7960	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \| HM_CHANGED_GUEST_SYSCALL_MSRS
7961	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
7962	}
7963	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7964	{
7965	rcStrict = VINF_SUCCESS;
7966	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7967	}
7968	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7969	return VBOXSTRICTRC_TODO(rcStrict);
7970	}
7971
7972
7973	/**
7974	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7975	*/
7976	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7977	{
7978	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7979
7980	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7981	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7982
7983	VBOXSTRICTRC rcStrict;
7984	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7985	if (fSupportsNextRipSave)
7986	{
7987	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7988	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7989	rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7990	}
7991	else
7992	{
7993	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7994	rcStrict = IEMExecOne(pVCpu);
7995	}
7996
7997	if (rcStrict == VINF_IEM_RAISED_XCPT)
7998	{
7999	rcStrict = VINF_SUCCESS;
8000	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8001	}
8002	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8003	return VBOXSTRICTRC_TODO(rcStrict);
8004	}
8005
8006
8007	/**
8008	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
8009	*/
8010	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
8011	{
8012	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8013
8014	VBOXSTRICTRC rcStrict;
8015	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8016	if (fSupportsNextRipSave)
8017	{
8018	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
8019	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8020	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8021	rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
8022	}
8023	else
8024	{
8025	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
8026	rcStrict = IEMExecOne(pVCpu);
8027	}
8028
8029	if (rcStrict == VINF_IEM_RAISED_XCPT)
8030	{
8031	rcStrict = VINF_SUCCESS;
8032	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8033	}
8034	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8035	return VBOXSTRICTRC_TODO(rcStrict);
8036	}
8037
8038
8039	/**
8040	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
8041	*/
8042	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
8043	{
8044	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8045	/* We shall import the entire state here, just in case we enter and continue execution of
8046	the nested-guest with hardware-assisted SVM in ring-0, we would be switching VMCBs and
8047	could lose lose part of CPU state. */
8048	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
8049
8050	VBOXSTRICTRC rcStrict;
8051	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8052	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitVmentry, z);
8053	if (fSupportsNextRipSave)
8054	{
8055	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8056	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8057	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
8058	}
8059	else
8060	{
8061	/* We use IEMExecOneBypassEx() here as it supresses attempt to continue emulating any
8062	instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
8063	instruction itself, see @bugref{7243#c126} */
8064	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
8065	}
8066	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);
8067
8068	if (rcStrict == VINF_SUCCESS)
8069	{
8070	rcStrict = VINF_SVM_VMRUN;
8071	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_SVM_VMRUN_MASK);
8072	}
8073	else if (rcStrict == VINF_IEM_RAISED_XCPT)
8074	{
8075	rcStrict = VINF_SUCCESS;
8076	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8077	}
8078	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8079	return VBOXSTRICTRC_TODO(rcStrict);
8080	}
8081
8082
8083	/**
8084	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
8085	* Unconditional \#VMEXIT.
8086	*/
8087	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
8088	{
8089	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8090	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
8091
8092	if (pVCpu->hm.s.Event.fPending)
8093	{
8094	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
8095	return VINF_EM_RAW_INJECT_TRPM_EVENT;
8096	}
8097
8098	hmR0SvmSetPendingXcptDB(pVCpu);
8099	return VINF_SUCCESS;
8100	}
8101
8102
8103	/**
8104	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
8105	* Conditional \#VMEXIT.
8106	*/
8107	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
8108	{
8109	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8110	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
8111
8112	SVMEVENT Event;
8113	Event.u = 0;
8114	Event.n.u1Valid = 1;
8115	Event.n.u3Type = SVM_EVENT_EXCEPTION;
8116	Event.n.u8Vector = X86_XCPT_BP;
8117	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
8118	return VINF_SUCCESS;
8119	}
8120	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
8121
8122	/** @} */
8123

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 80274

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