HMR0.cpp@ 47826

Last change on this file since 47826 was 47803, checked in by vboxsync, 12 years ago
VMM/HM: Preemption hoooks, work in progress.
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1	/* $Id: HMR0.cpp 47803 2013-08-16 11:58:57Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
90	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
91	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
92	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
94	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
95	bool fEnabledByHost));
96	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
97	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
99	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
100	/** @} */
101
102	/** Maximum ASID allowed. */
103	uint32_t uMaxAsid;
104
105	/** VT-x data. */
106	struct
107	{
108	/** Set to by us to indicate VMX is supported by the CPU. */
109	bool fSupported;
110	/** Whether we're using SUPR0EnableVTx or not. */
111	bool fUsingSUPR0EnableVTx;
112	/** Whether we're using the preemption timer or not. */
113	bool fUsePreemptTimer;
114	/** The shift mask employed by the VMX-Preemption timer. */
115	uint8_t cPreemptTimerShift;
116
117	/** Host CR4 value (set by ring-0 VMX init) */
118	uint64_t hostCR4;
119
120	/** Host EFER value (set by ring-0 VMX init) */
121	uint64_t hostEFER;
122
123	/** VMX MSR values */
124	struct
125	{
126	uint64_t feature_ctrl;
127	uint64_t vmx_basic_info;
128	VMX_CAPABILITY vmx_pin_ctls;
129	VMX_CAPABILITY vmx_proc_ctls;
130	VMX_CAPABILITY vmx_proc_ctls2;
131	VMX_CAPABILITY vmx_exit;
132	VMX_CAPABILITY vmx_entry;
133	uint64_t vmx_misc;
134	uint64_t vmx_cr0_fixed0;
135	uint64_t vmx_cr0_fixed1;
136	uint64_t vmx_cr4_fixed0;
137	uint64_t vmx_cr4_fixed1;
138	uint64_t vmx_vmcs_enum;
139	uint64_t vmx_vmfunc;
140	uint64_t vmx_ept_vpid_caps;
141	} msr;
142	/* Last instruction error */
143	uint32_t ulLastInstrError;
144	} vmx;
145
146	/** AMD-V information. */
147	struct
148	{
149	/* HWCR MSR (for diagnostics) */
150	uint64_t msrHwcr;
151
152	/** SVM revision. */
153	uint32_t u32Rev;
154
155	/** SVM feature bits from cpuid 0x8000000a */
156	uint32_t u32Features;
157
158	/** Set by us to indicate SVM is supported by the CPU. */
159	bool fSupported;
160	} svm;
161	/** Saved error from detection */
162	int32_t lLastError;
163
164	struct
165	{
166	uint32_t u32AMDFeatureECX;
167	uint32_t u32AMDFeatureEDX;
168	} cpuid;
169
170	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
171	* enabled and disabled each time it's used to execute guest code. */
172	bool fGlobalInit;
173	/** Indicates whether the host is suspending or not. We'll refuse a few
174	* actions when the host is being suspended to speed up the suspending and
175	* avoid trouble. */
176	volatile bool fSuspended;
177
178	/** Whether we've already initialized all CPUs.
179	* @remarks We could check the EnableAllCpusOnce state, but this is
180	* simpler and hopefully easier to understand. */
181	bool fEnabled;
182	/** Serialize initialization in HMR0EnableAllCpus. */
183	RTONCE EnableAllCpusOnce;
184	} g_HvmR0;
185
186
187
188	/**
189	* Initializes a first return code structure.
190	*
191	* @param pFirstRc The structure to init.
192	*/
193	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
194	{
195	pFirstRc->rc = VINF_SUCCESS;
196	pFirstRc->idCpu = NIL_RTCPUID;
197	}
198
199
200	/**
201	* Try set the status code (success ignored).
202	*
203	* @param pFirstRc The first return code structure.
204	* @param rc The status code.
205	*/
206	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
207	{
208	if ( RT_FAILURE(rc)
209	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
210	pFirstRc->idCpu = RTMpCpuId();
211	}
212
213
214	/**
215	* Get the status code of a first return code structure.
216	*
217	* @returns The status code; VINF_SUCCESS or error status, no informational or
218	* warning errors.
219	* @param pFirstRc The first return code structure.
220	*/
221	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
222	{
223	return pFirstRc->rc;
224	}
225
226
227	#ifdef VBOX_STRICT
228	/**
229	* Get the CPU ID on which the failure status code was reported.
230	*
231	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
232	* @param pFirstRc The first return code structure.
233	*/
234	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
235	{
236	return pFirstRc->idCpu;
237	}
238	#endif /* VBOX_STRICT */
239
240
241	/** @name Dummy callback handlers.
242	* @{ */
243
244	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
245	{
246	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
247	return VINF_SUCCESS;
248	}
249
250	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
251	{
252	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
253	return VINF_SUCCESS;
254	}
255
256	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
257	{
258	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
259	}
260
261	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
262	bool fEnabledBySystem)
263	{
264	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem);
265	return VINF_SUCCESS;
266	}
267
268	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
269	{
270	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
271	return VINF_SUCCESS;
272	}
273
274	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
275	{
276	NOREF(pVM);
277	return VINF_SUCCESS;
278	}
279
280	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
281	{
282	NOREF(pVM);
283	return VINF_SUCCESS;
284	}
285
286	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
287	{
288	NOREF(pVM);
289	return VINF_SUCCESS;
290	}
291
292	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
293	{
294	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
295	return VINF_SUCCESS;
296	}
297
298	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
299	{
300	NOREF(pVM); NOREF(pVCpu);
301	return VINF_SUCCESS;
302	}
303
304	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
305	{
306	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
307	return VINF_SUCCESS;
308	}
309
310	/** @} */
311
312
313	/**
314	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
315	* Down at the Rate Specified" erratum.
316	*
317	* Errata names and related steppings:
318	* - BA86 - D0.
319	* - AAX65 - C2.
320	* - AAU65 - C2, K0.
321	* - AAO95 - B1.
322	* - AAT59 - C2.
323	* - AAK139 - D0.
324	* - AAM126 - C0, C1, D0.
325	* - AAN92 - B1.
326	* - AAJ124 - C0, D0.
327	*
328	* - AAP86 - B1.
329	*
330	* Steppings: B1, C0, C1, C2, D0, K0.
331	*
332	* @returns true if subject to it, false if not.
333	*/
334	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
335	{
336	uint32_t u = ASMCpuId_EAX(1);
337	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
338	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
339	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
340	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
341	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
342	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
343	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
344	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
345	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
346	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
347	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
348	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
349	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
350	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
351	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
352	)
353	return true;
354	return false;
355	}
356
357
358	/**
359	* Intel specific initialization code.
360	*
361	* @returns VBox status code (will only fail if out of memory).
362	*/
363	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
364	{
365	/*
366	* Check that all the required VT-x features are present.
367	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
368	*/
369	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
370	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
371	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
372	)
373	{
374	/** @todo move this into a separate function. */
375	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
376
377	/*
378	* First try use native kernel API for controlling VT-x.
379	* (This is only supported by some Mac OS X kernels atm.)
380	*/
381	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
382	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
383	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
384	{
385	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
386	if (RT_SUCCESS(rc))
387	{
388	g_HvmR0.vmx.fSupported = true;
389	rc = SUPR0EnableVTx(false /* fEnable */);
390	AssertLogRelRC(rc);
391	}
392	}
393	else
394	{
395	/* We need to check if VT-x has been properly initialized on all
396	CPUs. Some BIOSes do a lousy job. */
397	HMR0FIRSTRC FirstRc;
398	hmR0FirstRcInit(&FirstRc);
399	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
400	if (RT_SUCCESS(g_HvmR0.lLastError))
401	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
402	}
403	if (RT_SUCCESS(g_HvmR0.lLastError))
404	{
405	/* Reread in case we've changed it. */
406	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
407
408	if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
409	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
410	{
411	/*
412	* Read all relevant MSR.
413	*/
414	g_HvmR0.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
415	g_HvmR0.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
416	g_HvmR0.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
417	g_HvmR0.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
418	g_HvmR0.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
419	g_HvmR0.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
420	g_HvmR0.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
421	g_HvmR0.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
422	g_HvmR0.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
423	g_HvmR0.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
424	g_HvmR0.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
425	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
426	g_HvmR0.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
427	/* VPID 16 bits ASID. */
428	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
429
430	if (g_HvmR0.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
431	{
432	g_HvmR0.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
433	if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1
434	& (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
435	{
436	g_HvmR0.vmx.msr.vmx_ept_vpid_caps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
437	}
438
439	if (g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
440	g_HvmR0.vmx.msr.vmx_vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
441	}
442
443	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
444	{
445	/*
446	* Enter root mode
447	*/
448	RTR0MEMOBJ hScatchMemObj;
449	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
450	if (RT_FAILURE(rc))
451	{
452	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
453	return rc;
454	}
455
456	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
457	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
458	ASMMemZeroPage(pvScatchPage);
459
460	/* Set revision dword at the beginning of the structure. */
461	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.vmx_basic_info);
462
463	/* Make sure we don't get rescheduled to another cpu during this probe. */
464	RTCCUINTREG fFlags = ASMIntDisableFlags();
465
466	/*
467	* Check CR4.VMXE
468	*/
469	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
470	if (!(g_HvmR0.vmx.hostCR4 & X86_CR4_VMXE))
471	{
472	/* In theory this bit could be cleared behind our back. Which would cause
473	#UD faults when we try to execute the VMX instructions... */
474	ASMSetCR4(g_HvmR0.vmx.hostCR4 \| X86_CR4_VMXE);
475	}
476
477	/* Enter VMX Root Mode */
478	rc = VMXEnable(HCPhysScratchPage);
479	if (RT_SUCCESS(rc))
480	{
481	g_HvmR0.vmx.fSupported = true;
482	VMXDisable();
483	}
484	else
485	{
486	/*
487	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
488	* it will crash the host when we enter raw mode, because:
489	*
490	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
491	* this bit), and
492	* (b) turning off paging causes a #GP (unavoidable when switching
493	* from long to 32 bits mode or 32 bits to PAE).
494	*
495	* They should fix their code, but until they do we simply refuse to run.
496	*/
497	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
498	}
499
500	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
501	if it wasn't so before (some software could incorrectly
502	think it's in VMX mode). */
503	ASMSetCR4(g_HvmR0.vmx.hostCR4);
504	ASMSetFlags(fFlags);
505
506	RTR0MemObjFree(hScatchMemObj, false);
507	}
508	}
509	else
510	{
511	AssertFailed(); /* can't hit this case anymore */
512	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
513	}
514
515	if (g_HvmR0.vmx.fSupported)
516	{
517	/* Call the global VT-x initialization routine. */
518	rc = VMXR0GlobalInit();
519	if (RT_FAILURE(rc))
520	g_HvmR0.lLastError = rc;
521
522	/*
523	* Install the VT-x methods.
524	*/
525	g_HvmR0.pfnEnterSession = VMXR0Enter;
526	g_HvmR0.pfnLeaveSession = VMXR0Leave;
527	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
528	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
529	g_HvmR0.pfnLoadGuestState = VMXR0LoadGuestState;
530	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
531	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
532	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
533	g_HvmR0.pfnInitVM = VMXR0InitVM;
534	g_HvmR0.pfnTermVM = VMXR0TermVM;
535	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
536
537	/*
538	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
539	* Timer Does Not Count Down at the Rate Specified" erratum.
540	*/
541	if (g_HvmR0.vmx.msr.vmx_pin_ctls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
542	{
543	g_HvmR0.vmx.fUsePreemptTimer = true;
544	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.vmx_misc);
545	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
546	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
547	}
548	}
549	}
550	#ifdef LOG_ENABLED
551	else
552	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
553	#endif
554	}
555	else
556	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
557	return VINF_SUCCESS;
558	}
559
560
561	/**
562	* AMD-specific initialization code.
563	*
564	* @returns VBox status code.
565	*/
566	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
567	{
568	/*
569	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
570	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
571	*/
572	int rc;
573	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
574	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
575	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
576	&& ASMIsValidExtRange(uMaxExtLeaf)
577	&& uMaxExtLeaf >= 0x8000000a
578	)
579	{
580	/* Call the global AMD-V initialization routine. */
581	rc = SVMR0GlobalInit();
582	if (RT_FAILURE(rc))
583	{
584	g_HvmR0.lLastError = rc;
585	return rc;
586	}
587
588	/*
589	* Install the AMD-V methods.
590	*/
591	g_HvmR0.pfnEnterSession = SVMR0Enter;
592	g_HvmR0.pfnLeaveSession = SVMR0Leave;
593	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
594	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
595	g_HvmR0.pfnLoadGuestState = SVMR0LoadGuestState;
596	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
597	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
598	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
599	g_HvmR0.pfnInitVM = SVMR0InitVM;
600	g_HvmR0.pfnTermVM = SVMR0TermVM;
601	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
602
603	/* Query AMD features. */
604	uint32_t u32Dummy;
605	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
606
607	/*
608	* We need to check if AMD-V has been properly initialized on all CPUs.
609	* Some BIOSes might do a poor job.
610	*/
611	HMR0FIRSTRC FirstRc;
612	hmR0FirstRcInit(&FirstRc);
613	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
614	AssertRC(rc);
615	if (RT_SUCCESS(rc))
616	rc = hmR0FirstRcGetStatus(&FirstRc);
617	#ifndef DEBUG_bird
618	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
619	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
620	#endif
621	if (RT_SUCCESS(rc))
622	{
623	/* Read the HWCR MSR for diagnostics. */
624	g_HvmR0.svm.msrHwcr = ASMRdMsr(MSR_K8_HWCR);
625	g_HvmR0.svm.fSupported = true;
626	}
627	else
628	g_HvmR0.lLastError = rc;
629	}
630	else
631	{
632	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
633	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
634	}
635	return rc;
636	}
637
638
639	/**
640	* Does global Ring-0 HM initialization (at module init).
641	*
642	* @returns VBox status code.
643	*/
644	VMMR0_INT_DECL(int) HMR0Init(void)
645	{
646	/*
647	* Initialize the globals.
648	*/
649	g_HvmR0.fEnabled = false;
650	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
651	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
652	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
653	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
654
655	/* Fill in all callbacks with placeholders. */
656	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
657	g_HvmR0.pfnLeaveSession = hmR0DummyLeave;
658	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
659	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
660	g_HvmR0.pfnLoadGuestState = hmR0DummyLoadGuestState;
661	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
662	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
663	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
664	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
665	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
666	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
667
668	/* Default is global VT-x/AMD-V init. */
669	g_HvmR0.fGlobalInit = true;
670
671	/*
672	* Make sure aCpuInfo is big enough for all the CPUs on this system.
673	*/
674	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
675	{
676	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
677	return VERR_TOO_MANY_CPUS;
678	}
679
680	/*
681	* Check for VT-x and AMD-V capabilities.
682	*/
683	int rc;
684	if (ASMHasCpuId())
685	{
686	/* Standard features. */
687	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
688	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
689	if (ASMIsValidStdRange(uMaxLeaf))
690	{
691	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
692	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
693
694	/* Query AMD features. */
695	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
696	if (ASMIsValidExtRange(uMaxExtLeaf))
697	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
698	&g_HvmR0.cpuid.u32AMDFeatureECX,
699	&g_HvmR0.cpuid.u32AMDFeatureEDX);
700	else
701	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
702
703	/* Go to CPU specific initialization code. */
704	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
705	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
706	{
707	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
708	if (RT_FAILURE(rc))
709	return rc;
710	}
711	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
712	{
713	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
714	if (RT_FAILURE(rc))
715	return rc;
716	}
717	else
718	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
719	}
720	else
721	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
722	}
723	else
724	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
725
726	/*
727	* Register notification callbacks that we can use to disable/enable CPUs
728	* when brought offline/online or suspending/resuming.
729	*/
730	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
731	{
732	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
733	AssertRC(rc);
734
735	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
736	AssertRC(rc);
737	}
738
739	/* We return success here because module init shall not fail if HM
740	fails to initialize. */
741	return VINF_SUCCESS;
742	}
743
744
745	/**
746	* Does global Ring-0 HM termination (at module termination).
747	*
748	* @returns VBox status code.
749	*/
750	VMMR0_INT_DECL(int) HMR0Term(void)
751	{
752	int rc;
753	if ( g_HvmR0.vmx.fSupported
754	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
755	{
756	/*
757	* Simple if the host OS manages VT-x.
758	*/
759	Assert(g_HvmR0.fGlobalInit);
760	rc = SUPR0EnableVTx(false /* fEnable */);
761
762	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
763	{
764	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
765	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
766	}
767	}
768	else
769	{
770	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
771	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
772	{
773	/* Doesn't really matter if this fails. */
774	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
775	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
776	}
777	else
778	rc = VINF_SUCCESS;
779
780	/*
781	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
782	*/
783	if (g_HvmR0.fGlobalInit)
784	{
785	HMR0FIRSTRC FirstRc;
786	hmR0FirstRcInit(&FirstRc);
787	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
788	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
789	if (RT_SUCCESS(rc))
790	{
791	rc = hmR0FirstRcGetStatus(&FirstRc);
792	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
793	}
794	}
795
796	/*
797	* Free the per-cpu pages used for VT-x and AMD-V.
798	*/
799	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
800	{
801	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
802	{
803	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
804	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
805	}
806	}
807	}
808
809	/** @todo This needs cleaning up. There's no matching
810	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
811	* should move into their respective modules. */
812	/* Finally, call global VT-x/AMD-V termination. */
813	if (g_HvmR0.vmx.fSupported)
814	VMXR0GlobalTerm();
815	else if (g_HvmR0.svm.fSupported)
816	SVMR0GlobalTerm();
817
818	return rc;
819	}
820
821
822	/**
823	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
824	* VT-x on a CPU.
825	*
826	* @param idCpu The identifier for the CPU the function is called on.
827	* @param pvUser1 Pointer to the first RC structure.
828	* @param pvUser2 Ignored.
829	*/
830	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
831	{
832	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
833	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
834	NOREF(pvUser2);
835
836	/*
837	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
838	* Once the lock bit is set, this MSR can no longer be modified.
839	*/
840	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
841	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
842	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
843	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
844	)
845	{
846	/* MSR is not yet locked; we can change it ourselves here. */
847	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
848	g_HvmR0.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
849	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
850	}
851
852	int rc;
853	if ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
854	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
855	rc = VINF_SUCCESS;
856	else
857	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
858
859	hmR0FirstRcSetStatus(pFirstRc, rc);
860	}
861
862
863	/**
864	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
865	* on a CPU.
866	*
867	* @param idCpu The identifier for the CPU the function is called on.
868	* @param pvUser1 Pointer to the first RC structure.
869	* @param pvUser2 Ignored.
870	*/
871	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
872	{
873	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
874	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
875	NOREF(pvUser2);
876
877	/* Check if SVM is disabled. */
878	int rc;
879	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
880	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
881	{
882	/* Turn on SVM in the EFER MSR. */
883	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
884	if (fEfer & MSR_K6_EFER_SVME)
885	rc = VERR_SVM_IN_USE;
886	else
887	{
888	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
889
890	/* Paranoia. */
891	fEfer = ASMRdMsr(MSR_K6_EFER);
892	if (fEfer & MSR_K6_EFER_SVME)
893	{
894	/* Restore previous value. */
895	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
896	rc = VINF_SUCCESS;
897	}
898	else
899	rc = VERR_SVM_ILLEGAL_EFER_MSR;
900	}
901	}
902	else
903	rc = VERR_SVM_DISABLED;
904
905	hmR0FirstRcSetStatus(pFirstRc, rc);
906	}
907
908
909	/**
910	* Enable VT-x or AMD-V on the current CPU
911	*
912	* @returns VBox status code.
913	* @param pVM Pointer to the VM (can be 0).
914	* @param idCpu The identifier for the CPU the function is called on.
915	*/
916	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
917	{
918	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
919
920	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
921	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
922	Assert(!pCpu->fConfigured);
923
924	pCpu->idCpu = idCpu;
925	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
926	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
927
928	int rc;
929	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
930	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL, NIL_RTHCPHYS, true);
931	else
932	{
933	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
934	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
935	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
936	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
937	}
938	AssertRC(rc);
939	if (RT_SUCCESS(rc))
940	pCpu->fConfigured = true;
941
942	return rc;
943	}
944
945
946	/**
947	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
948	* is to be called on the target cpus.
949	*
950	* @param idCpu The identifier for the CPU the function is called on.
951	* @param pvUser1 The 1st user argument.
952	* @param pvUser2 The 2nd user argument.
953	*/
954	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
955	{
956	PVM pVM = (PVM)pvUser1; /* can be NULL! */
957	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
958	AssertReturnVoid(g_HvmR0.fGlobalInit);
959	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
960	}
961
962
963	/**
964	* RTOnce callback employed by HMR0EnableAllCpus.
965	*
966	* @returns VBox status code.
967	* @param pvUser Pointer to the VM.
968	* @param pvUserIgnore NULL, ignored.
969	*/
970	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
971	{
972	PVM pVM = (PVM)pvUser;
973
974	/*
975	* Indicate that we've initialized.
976	*
977	* Note! There is a potential race between this function and the suspend
978	* notification. Kind of unlikely though, so ignored for now.
979	*/
980	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
981	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
982
983	/*
984	* The global init variable is set by the first VM.
985	*/
986	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
987
988	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
989	{
990	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
991	g_HvmR0.aCpuInfo[i].fConfigured = false;
992	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
993	}
994
995	int rc;
996	if ( g_HvmR0.vmx.fSupported
997	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
998	{
999	/*
1000	* Global VT-x initialization API (only darwin for now).
1001	*/
1002	rc = SUPR0EnableVTx(true /* fEnable */);
1003	if (RT_SUCCESS(rc))
1004	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
1005	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
1006	else
1007	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1008	}
1009	else
1010	{
1011	/*
1012	* We're doing the job ourselves.
1013	*/
1014	/* Allocate one page per cpu for the global vt-x and amd-v pages */
1015	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1016	{
1017	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1018
1019	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1020	{
1021	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1022	AssertLogRelRCReturn(rc, rc);
1023
1024	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1025	ASMMemZeroPage(pvR0);
1026	}
1027	}
1028
1029	rc = VINF_SUCCESS;
1030	}
1031
1032	if (RT_SUCCESS(rc) && g_HvmR0.fGlobalInit)
1033	{
1034	/* First time, so initialize each cpu/core. */
1035	HMR0FIRSTRC FirstRc;
1036	hmR0FirstRcInit(&FirstRc);
1037	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1038	if (RT_SUCCESS(rc))
1039	rc = hmR0FirstRcGetStatus(&FirstRc);
1040	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1041	}
1042
1043	return rc;
1044	}
1045
1046
1047	/**
1048	* Sets up HM on all cpus.
1049	*
1050	* @returns VBox status code.
1051	* @param pVM Pointer to the VM.
1052	*/
1053	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1054	{
1055	/* Make sure we don't touch HM after we've disabled HM in
1056	preparation of a suspend. */
1057	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1058	return VERR_HM_SUSPEND_PENDING;
1059
1060	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1061	}
1062
1063
1064	/**
1065	* Disable VT-x or AMD-V on the current CPU.
1066	*
1067	* @returns VBox status code.
1068	* @param idCpu The identifier for the CPU the function is called on.
1069	*/
1070	static int hmR0DisableCpu(RTCPUID idCpu)
1071	{
1072	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1073
1074	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1075	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1076	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1077	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1078
1079	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1080	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1081
1082	int rc;
1083	if (pCpu->fConfigured)
1084	{
1085	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1086	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1087	if (idCpu == RTMpCpuId())
1088	{
1089	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1090	AssertRC(rc);
1091	}
1092	else
1093	{
1094	pCpu->fIgnoreAMDVInUseError = true;
1095	rc = VINF_SUCCESS;
1096	}
1097
1098	pCpu->fConfigured = false;
1099	}
1100	else
1101	rc = VINF_SUCCESS; /* nothing to do */
1102
1103	pCpu->uCurrentAsid = 0;
1104	return rc;
1105	}
1106
1107
1108	/**
1109	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1110	* is to be called on the target cpus.
1111	*
1112	* @param idCpu The identifier for the CPU the function is called on.
1113	* @param pvUser1 The 1st user argument.
1114	* @param pvUser2 The 2nd user argument.
1115	*/
1116	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1117	{
1118	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1119	AssertReturnVoid(g_HvmR0.fGlobalInit);
1120	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1121	}
1122
1123
1124	/**
1125	* Callback function invoked when a cpu goes online or offline.
1126	*
1127	* @param enmEvent The Mp event.
1128	* @param idCpu The identifier for the CPU the function is called on.
1129	* @param pvData Opaque data (PVM pointer).
1130	*/
1131	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1132	{
1133	NOREF(pvData);
1134
1135	/*
1136	* We only care about uninitializing a CPU that is going offline. When a
1137	* CPU comes online, the initialization is done lazily in HMR0Enter().
1138	*/
1139	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1140	switch (enmEvent)
1141	{
1142	case RTMPEVENT_OFFLINE:
1143	{
1144	int rc = hmR0DisableCpu(idCpu);
1145	AssertRC(rc);
1146	break;
1147	}
1148
1149	default:
1150	break;
1151	}
1152	}
1153
1154
1155	/**
1156	* Called whenever a system power state change occurs.
1157	*
1158	* @param enmEvent The Power event.
1159	* @param pvUser User argument.
1160	*/
1161	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1162	{
1163	NOREF(pvUser);
1164	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1165
1166	#ifdef LOG_ENABLED
1167	if (enmEvent == RTPOWEREVENT_SUSPEND)
1168	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1169	else
1170	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1171	#endif
1172
1173	if (enmEvent == RTPOWEREVENT_SUSPEND)
1174	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1175
1176	if (g_HvmR0.fEnabled)
1177	{
1178	int rc;
1179	HMR0FIRSTRC FirstRc;
1180	hmR0FirstRcInit(&FirstRc);
1181
1182	if (enmEvent == RTPOWEREVENT_SUSPEND)
1183	{
1184	if (g_HvmR0.fGlobalInit)
1185	{
1186	/* Turn off VT-x or AMD-V on all CPUs. */
1187	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
1188	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1189	}
1190	/* else nothing to do here for the local init case */
1191	}
1192	else
1193	{
1194	/* Reinit the CPUs from scratch as the suspend state might have
1195	messed with the MSRs. (lousy BIOSes as usual) */
1196	if (g_HvmR0.vmx.fSupported)
1197	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1198	else
1199	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1200	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1201	if (RT_SUCCESS(rc))
1202	rc = hmR0FirstRcGetStatus(&FirstRc);
1203	#ifdef LOG_ENABLED
1204	if (RT_FAILURE(rc))
1205	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1206	#endif
1207	if (g_HvmR0.fGlobalInit)
1208	{
1209	/* Turn VT-x or AMD-V back on on all CPUs. */
1210	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
1211	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1212	}
1213	/* else nothing to do here for the local init case */
1214	}
1215	}
1216
1217	if (enmEvent == RTPOWEREVENT_RESUME)
1218	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1219	}
1220
1221
1222	/**
1223	* Does Ring-0 per VM HM initialization.
1224	*
1225	* This will copy HM global into the VM structure and call the CPU specific
1226	* init routine which will allocate resources for each virtual CPU and such.
1227	*
1228	* @returns VBox status code.
1229	* @param pVM Pointer to the VM.
1230	*/
1231	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1232	{
1233	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1234
1235	#ifdef LOG_ENABLED
1236	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1237	#endif
1238
1239	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1240	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1241	return VERR_HM_SUSPEND_PENDING;
1242
1243	/*
1244	* Copy globals to the VM structure.
1245	*/
1246	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1247	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1248
1249	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1250	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1251	pVM->hm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.feature_ctrl;
1252	pVM->hm.s.vmx.hostCR4 = g_HvmR0.vmx.hostCR4;
1253	pVM->hm.s.vmx.hostEFER = g_HvmR0.vmx.hostEFER;
1254	pVM->hm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.vmx_basic_info;
1255	pVM->hm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmx_pin_ctls;
1256	pVM->hm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmx_proc_ctls;
1257	pVM->hm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmx_proc_ctls2;
1258	pVM->hm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmx_exit;
1259	pVM->hm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmx_entry;
1260	pVM->hm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.vmx_misc;
1261	pVM->hm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.vmx_cr0_fixed0;
1262	pVM->hm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.vmx_cr0_fixed1;
1263	pVM->hm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.vmx_cr4_fixed0;
1264	pVM->hm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1;
1265	pVM->hm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum;
1266	pVM->hm.s.vmx.msr.vmx_vmfunc = g_HvmR0.vmx.msr.vmx_vmfunc;
1267	pVM->hm.s.vmx.msr.vmx_ept_vpid_caps = g_HvmR0.vmx.msr.vmx_ept_vpid_caps;
1268	pVM->hm.s.svm.msrHwcr = g_HvmR0.svm.msrHwcr;
1269	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1270	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1271	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1272	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1273	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1274
1275	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1276
1277
1278	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1279	{
1280	pVM->hm.s.cMaxResumeLoops = 1024;
1281	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1282	if (RTThreadPreemptIsPendingTrusty())
1283	pVM->hm.s.cMaxResumeLoops = 8192;
1284	#endif
1285	}
1286
1287	/*
1288	* Initialize some per CPU fields.
1289	*/
1290	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1291	{
1292	PVMCPU pVCpu = &pVM->aCpus[i];
1293
1294	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1295
1296	/* Invalidate the last cpu we were running on. */
1297	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1298
1299	/* We'll aways increment this the first time (host uses ASID 0) */
1300	pVCpu->hm.s.uCurrentAsid = 0;
1301	}
1302
1303	/*
1304	* Call the hardware specific initialization method.
1305	*/
1306	RTCCUINTREG fFlags = ASMIntDisableFlags();
1307	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1308	ASMSetFlags(fFlags);
1309
1310	int rc = g_HvmR0.pfnInitVM(pVM);
1311	return rc;
1312	}
1313
1314
1315	/**
1316	* Does Ring-0 per VM HM termination.
1317	*
1318	* @returns VBox status code.
1319	* @param pVM Pointer to the VM.
1320	*/
1321	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1322	{
1323	Log(("HMR0TermVM: %p\n", pVM));
1324	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1325
1326	/* Make sure we don't touch HM after we've disabled HM in preparation
1327	of a suspend. */
1328	/** @todo r=bird: This cannot be right, the termination functions are
1329	* just freeing memory and resetting pVM/pVCpu members...
1330	* ==> memory leak. */
1331	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1332
1333	/*
1334	* Call the hardware specific method.
1335	*/
1336	RTCCUINTREG fFlags = ASMIntDisableFlags();
1337	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1338	ASMSetFlags(fFlags);
1339
1340	int rc = g_HvmR0.pfnTermVM(pVM);
1341	return rc;
1342	}
1343
1344
1345	/**
1346	* Sets up a VT-x or AMD-V session.
1347	*
1348	* This is mostly about setting up the hardware VM state.
1349	*
1350	* @returns VBox status code.
1351	* @param pVM Pointer to the VM.
1352	*/
1353	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1354	{
1355	Log(("HMR0SetupVM: %p\n", pVM));
1356	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1357
1358	/* Make sure we don't touch HM after we've disabled HM in
1359	preparation of a suspend. */
1360	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1361
1362	/*
1363	* Call the hardware specific setup VM method. This requires the CPU to be
1364	* enabled for AMD-V/VT-x and preemption to be prevented.
1365	*/
1366	RTCCUINTREG fFlags = ASMIntDisableFlags();
1367	RTCPUID idCpu = RTMpCpuId();
1368	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1369
1370	/* On first entry we'll sync everything. */
1371	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1372	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1373
1374	/* Enable VT-x or AMD-V if local init is required. */
1375	int rc;
1376	if (!g_HvmR0.fGlobalInit)
1377	{
1378	rc = hmR0EnableCpu(pVM, idCpu);
1379	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1380	}
1381
1382	/* Setup VT-x or AMD-V. */
1383	rc = g_HvmR0.pfnSetupVM(pVM);
1384
1385	/* Disable VT-x or AMD-V if local init was done before. */
1386	if (!g_HvmR0.fGlobalInit)
1387	{
1388	int rc2 = hmR0DisableCpu(idCpu);
1389	AssertRC(rc2);
1390	}
1391
1392	ASMSetFlags(fFlags);
1393	return rc;
1394	}
1395
1396
1397	/**
1398	* Initializes the bare minimum state required for entering HM context.
1399	*
1400	* @param pvCpu Pointer to the VMCPU.
1401	*/
1402	VMMR0_INT_DECL(void) HMR0EnterEx(PVMCPU pVCpu)
1403	{
1404	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1405
1406	RTCPUID idCpu = RTMpCpuId();
1407	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1408	AssertPtr(pCpu);
1409
1410	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1411	if ( !pCpu->fConfigured
1412	\|\| !g_HvmR0.fGlobalInit)
1413	{
1414	hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1415	}
1416
1417	/* Reload host-context (back from ring-3/migrated CPUs), reload guest CR0 (for FPU bits). */
1418	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_GUEST_CR0;
1419	pVCpu->hm.s.idEnteredCpu = idCpu;
1420	}
1421
1422
1423	/**
1424	* Enters the VT-x or AMD-V session.
1425	*
1426	* @returns VBox status code.
1427	* @param pVM Pointer to the VM.
1428	* @param pVCpu Pointer to the VMCPU.
1429	*
1430	* @remarks This is called with preemption disabled.
1431	*/
1432	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1433	{
1434	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1435
1436	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1437	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1438
1439	/* Load the bare minimum state required for entering HM. */
1440	HMR0EnterEx(pVCpu);
1441
1442	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1443	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1444	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1445	#endif
1446
1447	RTCPUID idCpu = RTMpCpuId();
1448	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1449	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1450	Assert(pCpu);
1451	Assert(pCtx);
1452	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_GUEST_CR0));
1453
1454	int rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1455	AssertRC(rc);
1456
1457	/* We must save the host context here (VT-x) as we might be rescheduled on
1458	a different cpu after a long jump back to ring 3. */
1459	/** @todo This will change with preemption hooks. */
1460	rc \|= g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1461	AssertRC(rc);
1462
1463	rc \|= g_HvmR0.pfnLoadGuestState(pVM, pVCpu, pCtx);
1464	AssertRC(rc);
1465
1466	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1467	if (fStartedSet)
1468	PGMRZDynMapReleaseAutoSet(pVCpu);
1469	#endif
1470
1471	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1472	and ring-3 calls. */
1473	if (RT_FAILURE(rc))
1474	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1475	return rc;
1476	}
1477
1478
1479	/**
1480	* Deinitializes the bare minimum state used for HM context.
1481	*
1482	* @returns VBox status code.
1483	* @param pVCpu Pointer to the VMCPU.
1484	*/
1485	VMMR0_INT_DECL(int) HMR0LeaveEx(PVMCPU pVCpu)
1486	{
1487	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1488
1489	if (!g_HvmR0.fGlobalInit)
1490	{
1491	RTCPUID idCpu = RTMpCpuId();
1492	int rc = hmR0DisableCpu(idCpu);
1493	AssertRCReturn(rc, rc);
1494	}
1495
1496	/* Reset these to force a TLB flush for the next entry. */
1497	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1498	pVCpu->hm.s.uCurrentAsid = 0;
1499	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1500
1501	return VINF_SUCCESS;
1502	}
1503
1504
1505	/**
1506	* Leaves the VT-x or AMD-V session.
1507	*
1508	* @returns VBox status code.
1509	* @param pVM Pointer to the VM.
1510	* @param pVCpu Pointer to the VMCPU.
1511	*
1512	* @remarks Called with preemption disabled just like HMR0Enter, our
1513	* counterpart.
1514	*/
1515	VMMR0_INT_DECL(int) HMR0Leave(PVM pVM, PVMCPU pVCpu)
1516	{
1517	/** @todo r=bird: This can't be entirely right? */
1518	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1519
1520	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1521	AssertPtr(pCtx);
1522
1523	int rc = g_HvmR0.pfnLeaveSession(pVM, pVCpu, pCtx);
1524
1525	/*
1526	* When thread-context hooks are not used, leave HM context and if necessary disable HM on the CPU.
1527	* When thread-context hooks -are- used, this work would be done in the VT-x and AMD-V thread-context callback.
1528	*/
1529	if (!VMMR0ThreadCtxHooksAreRegistered(pVCpu))
1530	{
1531	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1532	RTCPUID idCpu = RTMpCpuId();
1533
1534	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1535	and ring-3 calls when thread-context hooks are not supported. */
1536	AssertMsgStmt( pVCpu->hm.s.idEnteredCpu == idCpu
1537	\|\| RT_FAILURE_NP(rc), ("Owner is %u, I'm %u", pVCpu->hm.s.idEnteredCpu, idCpu),
1538	rc = VERR_HM_WRONG_CPU_1);
1539
1540	rc = HMR0LeaveEx(pVCpu);
1541	AssertRCReturn(rc, rc);
1542	}
1543
1544	/* Guest FPU and debug state shouldn't be active now, it's likely that we're going back to ring-3. */
1545	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1546	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1547
1548	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1549	return rc;
1550	}
1551
1552
1553	/**
1554	* Thread-context hook for HM.
1555	*
1556	* @param enmEvent The thread-context event.
1557	* @param pvUser Opaque pointer to the VMCPU.
1558	*/
1559	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1560	{
1561	PVMCPU pVCpu = (PVMCPU)pvUser;
1562	Assert(pVCpu);
1563	Assert(g_HvmR0.pfnThreadCtxCallback);
1564
1565	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1566	}
1567
1568
1569	/**
1570	* Runs guest code in a hardware accelerated VM.
1571	*
1572	* @returns VBox status code.
1573	* @param pVM Pointer to the VM.
1574	* @param pVCpu Pointer to the VMCPU.
1575	*
1576	* @remarks Called with preemption disabled and after first having called
1577	* HMR0Enter.
1578	*/
1579	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1580	{
1581	#ifdef VBOX_STRICT
1582	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1583	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1584	Assert(pCpu->fConfigured);
1585	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1586	#endif
1587
1588	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1589	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1590	PGMRZDynMapStartAutoSet(pVCpu);
1591	#endif
1592
1593	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1594
1595	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1596	PGMRZDynMapReleaseAutoSet(pVCpu);
1597	#endif
1598	return rc;
1599	}
1600
1601	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1602
1603	/**
1604	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1605	*
1606	* @returns VBox status code.
1607	* @param pVM Pointer to the VM.
1608	* @param pVCpu Pointer to the VMCPU.
1609	* @param pCtx Pointer to the guest CPU context.
1610	*/
1611	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1612	{
1613	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1614	if (pVM->hm.s.vmx.fSupported)
1615	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1616	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1617	}
1618
1619
1620	/**
1621	* Save guest debug state (64 bits guest mode & 32 bits host only)
1622	*
1623	* @returns VBox status code.
1624	* @param pVM Pointer to the VM.
1625	* @param pVCpu Pointer to the VMCPU.
1626	* @param pCtx Pointer to the guest CPU context.
1627	*/
1628	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1629	{
1630	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1631	if (pVM->hm.s.vmx.fSupported)
1632	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1633	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1634	}
1635
1636
1637	/**
1638	* Test the 32->64 bits switcher.
1639	*
1640	* @returns VBox status code.
1641	* @param pVM Pointer to the VM.
1642	*/
1643	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1644	{
1645	PVMCPU pVCpu = &pVM->aCpus[0];
1646	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1647	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1648	int rc;
1649
1650	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1651	if (pVM->hm.s.vmx.fSupported)
1652	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1653	else
1654	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1655	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1656
1657	return rc;
1658	}
1659
1660	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1661
1662	/**
1663	* Returns suspend status of the host.
1664	*
1665	* @returns Suspend pending or not.
1666	*/
1667	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1668	{
1669	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1670	}
1671
1672
1673	/**
1674	* Returns the cpu structure for the current cpu.
1675	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1676	*
1677	* @returns The cpu structure pointer.
1678	*/
1679	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1680	{
1681	RTCPUID idCpu = RTMpCpuId();
1682	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1683	return &g_HvmR0.aCpuInfo[idCpu];
1684	}
1685
1686
1687	/**
1688	* Returns the cpu structure for the current cpu.
1689	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1690	*
1691	* @returns The cpu structure pointer.
1692	* @param idCpu id of the VCPU.
1693	*/
1694	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1695	{
1696	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1697	return &g_HvmR0.aCpuInfo[idCpu];
1698	}
1699
1700
1701	/**
1702	* Save a pending IO read.
1703	*
1704	* @param pVCpu Pointer to the VMCPU.
1705	* @param GCPtrRip Address of IO instruction.
1706	* @param GCPtrRipNext Address of the next instruction.
1707	* @param uPort Port address.
1708	* @param uAndVal AND mask for saving the result in eax.
1709	* @param cbSize Read size.
1710	*/
1711	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1712	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1713	{
1714	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1715	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1716	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1717	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1718	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1719	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1720	return;
1721	}
1722
1723
1724	/**
1725	* Save a pending IO write.
1726	*
1727	* @param pVCpu Pointer to the VMCPU.
1728	* @param GCPtrRIP Address of IO instruction.
1729	* @param uPort Port address.
1730	* @param uAndVal AND mask for fetching the result from eax.
1731	* @param cbSize Read size.
1732	*/
1733	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1734	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1735	{
1736	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1737	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1738	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1739	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1740	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1741	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1742	return;
1743	}
1744
1745
1746	/**
1747	* Raw-mode switcher hook - disable VT-x if it's active and the current
1748	* switcher turns off paging.
1749	*
1750	* @returns VBox status code.
1751	* @param pVM Pointer to the VM.
1752	* @param enmSwitcher The switcher we're about to use.
1753	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1754	*/
1755	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1756	{
1757	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1758
1759	*pfVTxDisabled = false;
1760
1761	/* No such issues with AMD-V */
1762	if (!g_HvmR0.vmx.fSupported)
1763	return VINF_SUCCESS;
1764
1765	/* Check if the swithcing we're up to is safe. */
1766	switch (enmSwitcher)
1767	{
1768	case VMMSWITCHER_32_TO_32:
1769	case VMMSWITCHER_PAE_TO_PAE:
1770	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1771
1772	case VMMSWITCHER_32_TO_PAE:
1773	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1774	case VMMSWITCHER_AMD64_TO_32:
1775	case VMMSWITCHER_AMD64_TO_PAE:
1776	break; /* unsafe switchers */
1777
1778	default:
1779	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1780	}
1781
1782	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1783	regardless of whether we're currently using VT-x or not. */
1784	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1785	{
1786	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1787	return VINF_SUCCESS;
1788	}
1789
1790	/** @todo Check if this code is presumtive wrt other VT-x users on the
1791	* system... */
1792
1793	/* Nothing to do if we haven't enabled VT-x. */
1794	if (!g_HvmR0.fEnabled)
1795	return VINF_SUCCESS;
1796
1797	/* Local init implies the CPU is currently not in VMX root mode. */
1798	if (!g_HvmR0.fGlobalInit)
1799	return VINF_SUCCESS;
1800
1801	/* Ok, disable VT-x. */
1802	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1803	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1804
1805	*pfVTxDisabled = true;
1806	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1807	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1808	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1809	}
1810
1811
1812	/**
1813	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1814	* switcher turned off paging.
1815	*
1816	* @param pVM Pointer to the VM.
1817	* @param fVTxDisabled Whether VT-x was disabled or not.
1818	*/
1819	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1820	{
1821	Assert(!(ASMGetFlags() & X86_EFL_IF));
1822
1823	if (!fVTxDisabled)
1824	return; /* nothing to do */
1825
1826	Assert(g_HvmR0.vmx.fSupported);
1827	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1828	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1829	else
1830	{
1831	Assert(g_HvmR0.fEnabled);
1832	Assert(g_HvmR0.fGlobalInit);
1833
1834	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1835	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1836
1837	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1838	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1839	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
1840	}
1841	}
1842
1843	#ifdef VBOX_STRICT
1844
1845	/**
1846	* Dumps a descriptor.
1847	*
1848	* @param pDesc Descriptor to dump.
1849	* @param Sel Selector number.
1850	* @param pszMsg Message to prepend the log entry with.
1851	*/
1852	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1853	{
1854	/*
1855	* Make variable description string.
1856	*/
1857	static struct
1858	{
1859	unsigned cch;
1860	const char *psz;
1861	} const s_aTypes[32] =
1862	{
1863	# define STRENTRY(str) { sizeof(str) - 1, str }
1864
1865	/* system */
1866	# if HC_ARCH_BITS == 64
1867	STRENTRY("Reserved0 "), /* 0x00 */
1868	STRENTRY("Reserved1 "), /* 0x01 */
1869	STRENTRY("LDT "), /* 0x02 */
1870	STRENTRY("Reserved3 "), /* 0x03 */
1871	STRENTRY("Reserved4 "), /* 0x04 */
1872	STRENTRY("Reserved5 "), /* 0x05 */
1873	STRENTRY("Reserved6 "), /* 0x06 */
1874	STRENTRY("Reserved7 "), /* 0x07 */
1875	STRENTRY("Reserved8 "), /* 0x08 */
1876	STRENTRY("TSS64Avail "), /* 0x09 */
1877	STRENTRY("ReservedA "), /* 0x0a */
1878	STRENTRY("TSS64Busy "), /* 0x0b */
1879	STRENTRY("Call64 "), /* 0x0c */
1880	STRENTRY("ReservedD "), /* 0x0d */
1881	STRENTRY("Int64 "), /* 0x0e */
1882	STRENTRY("Trap64 "), /* 0x0f */
1883	# else
1884	STRENTRY("Reserved0 "), /* 0x00 */
1885	STRENTRY("TSS16Avail "), /* 0x01 */
1886	STRENTRY("LDT "), /* 0x02 */
1887	STRENTRY("TSS16Busy "), /* 0x03 */
1888	STRENTRY("Call16 "), /* 0x04 */
1889	STRENTRY("Task "), /* 0x05 */
1890	STRENTRY("Int16 "), /* 0x06 */
1891	STRENTRY("Trap16 "), /* 0x07 */
1892	STRENTRY("Reserved8 "), /* 0x08 */
1893	STRENTRY("TSS32Avail "), /* 0x09 */
1894	STRENTRY("ReservedA "), /* 0x0a */
1895	STRENTRY("TSS32Busy "), /* 0x0b */
1896	STRENTRY("Call32 "), /* 0x0c */
1897	STRENTRY("ReservedD "), /* 0x0d */
1898	STRENTRY("Int32 "), /* 0x0e */
1899	STRENTRY("Trap32 "), /* 0x0f */
1900	# endif
1901	/* non system */
1902	STRENTRY("DataRO "), /* 0x10 */
1903	STRENTRY("DataRO Accessed "), /* 0x11 */
1904	STRENTRY("DataRW "), /* 0x12 */
1905	STRENTRY("DataRW Accessed "), /* 0x13 */
1906	STRENTRY("DataDownRO "), /* 0x14 */
1907	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1908	STRENTRY("DataDownRW "), /* 0x16 */
1909	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1910	STRENTRY("CodeEO "), /* 0x18 */
1911	STRENTRY("CodeEO Accessed "), /* 0x19 */
1912	STRENTRY("CodeER "), /* 0x1a */
1913	STRENTRY("CodeER Accessed "), /* 0x1b */
1914	STRENTRY("CodeConfEO "), /* 0x1c */
1915	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1916	STRENTRY("CodeConfER "), /* 0x1e */
1917	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1918	# undef SYSENTRY
1919	};
1920	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1921	char szMsg[128];
1922	char *psz = &szMsg[0];
1923	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1924	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1925	psz += s_aTypes[i].cch;
1926
1927	if (pDesc->Gen.u1Present)
1928	ADD_STR(psz, "Present ");
1929	else
1930	ADD_STR(psz, "Not-Present ");
1931	# if HC_ARCH_BITS == 64
1932	if (pDesc->Gen.u1Long)
1933	ADD_STR(psz, "64-bit ");
1934	else
1935	ADD_STR(psz, "Comp ");
1936	# else
1937	if (pDesc->Gen.u1Granularity)
1938	ADD_STR(psz, "Page ");
1939	if (pDesc->Gen.u1DefBig)
1940	ADD_STR(psz, "32-bit ");
1941	else
1942	ADD_STR(psz, "16-bit ");
1943	# endif
1944	# undef ADD_STR
1945	*psz = '\0';
1946
1947	/*
1948	* Limit and Base and format the output.
1949	*/
1950	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1951
1952	# if HC_ARCH_BITS == 64
1953	uint64_t u32Base = X86DESC64_BASE(pDesc);
1954
1955	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1956	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1957	# else
1958	uint32_t u32Base = X86DESC_BASE(pDesc);
1959
1960	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1961	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1962	# endif
1963	}
1964
1965
1966	/**
1967	* Formats a full register dump.
1968	*
1969	* @param pVM Pointer to the VM.
1970	* @param pVCpu Pointer to the VMCPU.
1971	* @param pCtx Pointer to the CPU context.
1972	*/
1973	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1974	{
1975	NOREF(pVM);
1976
1977	/*
1978	* Format the flags.
1979	*/
1980	static struct
1981	{
1982	const char pszSet; const char pszClear; uint32_t fFlag;
1983	} const s_aFlags[] =
1984	{
1985	{ "vip",NULL, X86_EFL_VIP },
1986	{ "vif",NULL, X86_EFL_VIF },
1987	{ "ac", NULL, X86_EFL_AC },
1988	{ "vm", NULL, X86_EFL_VM },
1989	{ "rf", NULL, X86_EFL_RF },
1990	{ "nt", NULL, X86_EFL_NT },
1991	{ "ov", "nv", X86_EFL_OF },
1992	{ "dn", "up", X86_EFL_DF },
1993	{ "ei", "di", X86_EFL_IF },
1994	{ "tf", NULL, X86_EFL_TF },
1995	{ "nt", "pl", X86_EFL_SF },
1996	{ "nz", "zr", X86_EFL_ZF },
1997	{ "ac", "na", X86_EFL_AF },
1998	{ "po", "pe", X86_EFL_PF },
1999	{ "cy", "nc", X86_EFL_CF },
2000	};
2001	char szEFlags[80];
2002	char *psz = szEFlags;
2003	uint32_t efl = pCtx->eflags.u32;
2004	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2005	{
2006	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2007	if (pszAdd)
2008	{
2009	strcpy(psz, pszAdd);
2010	psz += strlen(pszAdd);
2011	*psz++ = ' ';
2012	}
2013	}
2014	psz[-1] = '\0';
2015
2016
2017	/*
2018	* Format the registers.
2019	*/
2020	if (CPUMIsGuestIn64BitCode(pVCpu))
2021	{
2022	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
2023	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
2024	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2025	"r14=%016RX64 r15=%016RX64\n"
2026	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
2027	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2028	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2029	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2030	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2031	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2032	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2033	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
2034	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
2035	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
2036	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2037	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2038	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2039	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2040	,
2041	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2042	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2043	pCtx->r14, pCtx->r15,
2044	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2045	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2046	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2047	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2048	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2049	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2050	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2051	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2052	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2053	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2054	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2055	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2056	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2057	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2058	}
2059	else
2060	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2061	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2062	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2063	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2064	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2065	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2066	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2067	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2068	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2069	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2070	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2071	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2072	,
2073	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2074	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2075	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2076	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2077	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2078	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2079	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2080	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2081	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2082	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2083	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2084	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2085
2086	Log(("FPU:\n"
2087	"FCW=%04x FSW=%04x FTW=%02x\n"
2088	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2089	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2090	,
2091	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2092	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2093	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2094	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2095
2096
2097	Log(("MSR:\n"
2098	"EFER =%016RX64\n"
2099	"PAT =%016RX64\n"
2100	"STAR =%016RX64\n"
2101	"CSTAR =%016RX64\n"
2102	"LSTAR =%016RX64\n"
2103	"SFMASK =%016RX64\n"
2104	"KERNELGSBASE =%016RX64\n",
2105	pCtx->msrEFER,
2106	pCtx->msrPAT,
2107	pCtx->msrSTAR,
2108	pCtx->msrCSTAR,
2109	pCtx->msrLSTAR,
2110	pCtx->msrSFMASK,
2111	pCtx->msrKERNELGSBASE));
2112
2113	}
2114
2115	#endif /* VBOX_STRICT */
2116

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 47826

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