| 1 | /* $Id: SELMAll.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
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| 2 | /** @file
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| 3 | * SELM All contexts.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2022 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 |
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| 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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| 32 | #define LOG_GROUP LOG_GROUP_SELM
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| 33 | #include <VBox/vmm/selm.h>
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| 34 | #include <VBox/vmm/stam.h>
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| 35 | #include <VBox/vmm/em.h>
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| 36 | #include <VBox/vmm/mm.h>
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| 37 | #include <VBox/vmm/hm.h>
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| 38 | #include <VBox/vmm/pgm.h>
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| 39 | #include <VBox/vmm/hm.h>
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| 40 | #include "SELMInternal.h"
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| 41 | #include <VBox/vmm/vmcc.h>
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| 42 | #include <VBox/err.h>
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| 43 | #include <VBox/param.h>
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| 44 | #include <iprt/assert.h>
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| 45 | #include <VBox/vmm/vmm.h>
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| 46 | #include <iprt/x86.h>
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| 47 | #include <iprt/string.h>
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| 48 |
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| 49 |
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| 50 |
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| 51 | /**
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| 52 | * Converts a GC selector based address to a flat address.
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| 53 | *
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| 54 | * No limit checks are done. Use the SELMToFlat*() or SELMValidate*() functions
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| 55 | * for that.
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| 56 | *
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| 57 | * @returns Flat address.
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| 58 | * @param pVM The cross context VM structure.
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| 59 | * @param SelReg Selector register
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| 60 | * @param pCtxCore CPU context
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| 61 | * @param Addr Address part.
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| 62 | */
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| 63 | VMMDECL(RTGCPTR) SELMToFlat(PVMCC pVM, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr)
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| 64 | {
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| 65 | PCPUMSELREG pSReg;
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| 66 | PVMCPUCC pVCpu = VMMGetCpu(pVM);
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| 67 |
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| 68 | int rc = DISFetchRegSegEx(pCtxCore, SelReg, &pSReg); AssertRC(rc);
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| 69 |
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| 70 | /*
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| 71 | * Deal with real & v86 mode first.
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| 72 | */
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| 73 | if ( pCtxCore->eflags.Bits.u1VM
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| 74 | || CPUMIsGuestInRealMode(pVCpu))
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| 75 | {
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| 76 | uint32_t uFlat = (uint32_t)Addr & 0xffff;
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| 77 | if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
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| 78 | uFlat += (uint32_t)pSReg->u64Base;
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| 79 | else
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| 80 | uFlat += (uint32_t)pSReg->Sel << 4;
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| 81 | return (RTGCPTR)uFlat;
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| 82 | }
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| 83 |
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| 84 | Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
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| 85 | Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtxCore->cs));
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| 86 |
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| 87 | /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0
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| 88 | (Intel(r) 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
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| 89 | if ( pCtxCore->cs.Attr.n.u1Long
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| 90 | && CPUMIsGuestInLongMode(pVCpu))
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| 91 | {
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| 92 | switch (SelReg)
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| 93 | {
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| 94 | case DISSELREG_FS:
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| 95 | case DISSELREG_GS:
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| 96 | return (RTGCPTR)(pSReg->u64Base + Addr);
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| 97 |
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| 98 | default:
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| 99 | return Addr; /* base 0 */
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| 100 | }
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| 101 | }
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| 102 |
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| 103 | /* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
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| 104 | Assert(pSReg->u64Base <= 0xffffffff);
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| 105 | return (uint32_t)pSReg->u64Base + (uint32_t)Addr;
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| 106 | }
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| 107 |
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| 108 |
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| 109 | /**
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| 110 | * Converts a GC selector based address to a flat address.
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| 111 | *
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| 112 | * Some basic checking is done, but not all kinds yet.
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| 113 | *
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| 114 | * @returns VBox status
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| 115 | * @param pVCpu The cross context virtual CPU structure.
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| 116 | * @param SelReg Selector register.
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| 117 | * @param pCtxCore CPU context.
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| 118 | * @param Addr Address part.
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| 119 | * @param fFlags SELMTOFLAT_FLAGS_*
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| 120 | * GDT entires are valid.
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| 121 | * @param ppvGC Where to store the GC flat address.
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| 122 | */
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| 123 | VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr, uint32_t fFlags, PRTGCPTR ppvGC)
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| 124 | {
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| 125 | /*
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| 126 | * Fetch the selector first.
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| 127 | */
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| 128 | PCPUMSELREG pSReg;
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| 129 | int rc = DISFetchRegSegEx(pCtxCore, SelReg, &pSReg);
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| 130 | AssertRCReturn(rc, rc); AssertPtr(pSReg);
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| 131 |
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| 132 | /*
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| 133 | * Deal with real & v86 mode first.
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| 134 | */
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| 135 | if ( pCtxCore->eflags.Bits.u1VM
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| 136 | || CPUMIsGuestInRealMode(pVCpu))
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| 137 | {
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| 138 | if (ppvGC)
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| 139 | {
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| 140 | uint32_t uFlat = (uint32_t)Addr & 0xffff;
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| 141 | if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
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| 142 | *ppvGC = (uint32_t)pSReg->u64Base + uFlat;
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| 143 | else
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| 144 | *ppvGC = ((uint32_t)pSReg->Sel << 4) + uFlat;
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| 145 | }
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| 146 | return VINF_SUCCESS;
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| 147 | }
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| 148 |
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| 149 | Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
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| 150 | Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtxCore->cs));
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| 151 |
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| 152 | /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0
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| 153 | (Intel(r) 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
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| 154 | RTGCPTR pvFlat;
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| 155 | bool fCheckLimit = true;
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| 156 | if ( pCtxCore->cs.Attr.n.u1Long
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| 157 | && CPUMIsGuestInLongMode(pVCpu))
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| 158 | {
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| 159 | fCheckLimit = false;
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| 160 | switch (SelReg)
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| 161 | {
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| 162 | case DISSELREG_FS:
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| 163 | case DISSELREG_GS:
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| 164 | pvFlat = pSReg->u64Base + Addr;
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| 165 | break;
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| 166 |
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| 167 | default:
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| 168 | pvFlat = Addr;
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| 169 | break;
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| 170 | }
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| 171 | }
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| 172 | else
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| 173 | {
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| 174 | /* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
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| 175 | Assert(pSReg->u64Base <= UINT32_C(0xffffffff));
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| 176 | pvFlat = (uint32_t)pSReg->u64Base + (uint32_t)Addr;
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| 177 | Assert(pvFlat <= UINT32_MAX);
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| 178 | }
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| 179 |
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| 180 | /*
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| 181 | * Check type if present.
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| 182 | */
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| 183 | if (pSReg->Attr.n.u1Present)
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| 184 | {
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| 185 | switch (pSReg->Attr.n.u4Type)
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| 186 | {
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| 187 | /* Read only selector type. */
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| 188 | case X86_SEL_TYPE_RO:
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| 189 | case X86_SEL_TYPE_RO_ACC:
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| 190 | case X86_SEL_TYPE_RW:
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| 191 | case X86_SEL_TYPE_RW_ACC:
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| 192 | case X86_SEL_TYPE_EO:
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| 193 | case X86_SEL_TYPE_EO_ACC:
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| 194 | case X86_SEL_TYPE_ER:
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| 195 | case X86_SEL_TYPE_ER_ACC:
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| 196 | if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
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| 197 | {
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| 198 | /** @todo fix this mess */
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| 199 | }
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| 200 | /* check limit. */
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| 201 | if (fCheckLimit && Addr > pSReg->u32Limit)
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| 202 | return VERR_OUT_OF_SELECTOR_BOUNDS;
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| 203 | /* ok */
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| 204 | if (ppvGC)
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| 205 | *ppvGC = pvFlat;
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| 206 | return VINF_SUCCESS;
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| 207 |
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| 208 | case X86_SEL_TYPE_EO_CONF:
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| 209 | case X86_SEL_TYPE_EO_CONF_ACC:
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| 210 | case X86_SEL_TYPE_ER_CONF:
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| 211 | case X86_SEL_TYPE_ER_CONF_ACC:
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| 212 | if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
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| 213 | {
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| 214 | /** @todo fix this mess */
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| 215 | }
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| 216 | /* check limit. */
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| 217 | if (fCheckLimit && Addr > pSReg->u32Limit)
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| 218 | return VERR_OUT_OF_SELECTOR_BOUNDS;
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| 219 | /* ok */
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| 220 | if (ppvGC)
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| 221 | *ppvGC = pvFlat;
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| 222 | return VINF_SUCCESS;
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| 223 |
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| 224 | case X86_SEL_TYPE_RO_DOWN:
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| 225 | case X86_SEL_TYPE_RO_DOWN_ACC:
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| 226 | case X86_SEL_TYPE_RW_DOWN:
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| 227 | case X86_SEL_TYPE_RW_DOWN_ACC:
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| 228 | if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
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| 229 | {
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| 230 | /** @todo fix this mess */
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| 231 | }
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| 232 | /* check limit. */
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| 233 | if (fCheckLimit)
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| 234 | {
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| 235 | if (!pSReg->Attr.n.u1Granularity && Addr > UINT32_C(0xffff))
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| 236 | return VERR_OUT_OF_SELECTOR_BOUNDS;
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| 237 | if (Addr <= pSReg->u32Limit)
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| 238 | return VERR_OUT_OF_SELECTOR_BOUNDS;
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| 239 | }
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| 240 | /* ok */
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| 241 | if (ppvGC)
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| 242 | *ppvGC = pvFlat;
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| 243 | return VINF_SUCCESS;
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| 244 |
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| 245 | default:
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| 246 | return VERR_INVALID_SELECTOR;
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| 247 |
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| 248 | }
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| 249 | }
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| 250 | return VERR_SELECTOR_NOT_PRESENT;
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| 251 | }
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| 252 |
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| 253 |
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| 254 |
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| 255 | /**
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| 256 | * Validates and converts a GC selector based code address to a flat
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| 257 | * address when in real or v8086 mode.
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| 258 | *
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| 259 | * @returns VINF_SUCCESS.
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| 260 | * @param pVCpu The cross context virtual CPU structure.
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| 261 | * @param SelCS Selector part.
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| 262 | * @param pSReg The hidden CS register part. Optional.
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| 263 | * @param Addr Address part.
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| 264 | * @param ppvFlat Where to store the flat address.
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| 265 | */
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| 266 | DECLINLINE(int) selmValidateAndConvertCSAddrRealMode(PVMCPU pVCpu, RTSEL SelCS, PCCPUMSELREGHID pSReg, RTGCPTR Addr,
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| 267 | PRTGCPTR ppvFlat)
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| 268 | {
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| 269 | NOREF(pVCpu);
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| 270 | uint32_t uFlat = Addr & 0xffff;
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| 271 | if (!pSReg || !CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
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| 272 | uFlat += (uint32_t)SelCS << 4;
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| 273 | else
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| 274 | uFlat += (uint32_t)pSReg->u64Base;
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| 275 | *ppvFlat = uFlat;
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| 276 | return VINF_SUCCESS;
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| 277 | }
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| 278 |
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| 279 |
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| 280 | /**
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| 281 | * Validates and converts a GC selector based code address to a flat address
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| 282 | * when in protected/long mode using the standard hidden selector registers
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| 283 | *
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| 284 | * @returns VBox status code.
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| 285 | * @param pVCpu The cross context virtual CPU structure.
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| 286 | * @param SelCPL Current privilege level. Get this from SS - CS might be
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| 287 | * conforming! A full selector can be passed, we'll only
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| 288 | * use the RPL part.
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| 289 | * @param SelCS Selector part.
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| 290 | * @param pSRegCS The full CS selector register.
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| 291 | * @param Addr The address (think IP/EIP/RIP).
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| 292 | * @param ppvFlat Where to store the flat address upon successful return.
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| 293 | */
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| 294 | DECLINLINE(int) selmValidateAndConvertCSAddrHidden(PVMCPU pVCpu, RTSEL SelCPL, RTSEL SelCS, PCCPUMSELREGHID pSRegCS,
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| 295 | RTGCPTR Addr, PRTGCPTR ppvFlat)
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| 296 | {
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| 297 | NOREF(SelCPL); NOREF(SelCS);
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| 298 |
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| 299 | /*
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| 300 | * Check if present.
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| 301 | */
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| 302 | if (pSRegCS->Attr.n.u1Present)
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| 303 | {
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| 304 | /*
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| 305 | * Type check.
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| 306 | */
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| 307 | if ( pSRegCS->Attr.n.u1DescType == 1
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| 308 | && (pSRegCS->Attr.n.u4Type & X86_SEL_TYPE_CODE))
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| 309 | {
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| 310 | /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0
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| 311 | (Intel(r) 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
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| 312 | if ( pSRegCS->Attr.n.u1Long
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| 313 | && CPUMIsGuestInLongMode(pVCpu))
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| 314 | {
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| 315 | *ppvFlat = Addr;
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| 316 | return VINF_SUCCESS;
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| 317 | }
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| 318 |
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| 319 | /*
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| 320 | * Limit check. Note that the limit in the hidden register is the
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| 321 | * final value. The granularity bit was included in its calculation.
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| 322 | */
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| 323 | uint32_t u32Limit = pSRegCS->u32Limit;
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| 324 | if ((uint32_t)Addr <= u32Limit)
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| 325 | {
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| 326 | *ppvFlat = (uint32_t)Addr + (uint32_t)pSRegCS->u64Base;
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| 327 | return VINF_SUCCESS;
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| 328 | }
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| 329 |
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| 330 | return VERR_OUT_OF_SELECTOR_BOUNDS;
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| 331 | }
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| 332 | return VERR_NOT_CODE_SELECTOR;
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| 333 | }
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| 334 | return VERR_SELECTOR_NOT_PRESENT;
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| 335 | }
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| 336 |
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| 337 |
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| 338 | /**
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| 339 | * Validates and converts a GC selector based code address to a flat address.
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| 340 | *
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| 341 | * @returns VBox status code.
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| 342 | * @param pVCpu The cross context virtual CPU structure.
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| 343 | * @param Efl Current EFLAGS.
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| 344 | * @param SelCPL Current privilege level. Get this from SS - CS might be
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| 345 | * conforming! A full selector can be passed, we'll only
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| 346 | * use the RPL part.
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| 347 | * @param SelCS Selector part.
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| 348 | * @param pSRegCS The full CS selector register.
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| 349 | * @param Addr The address (think IP/EIP/RIP).
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| 350 | * @param ppvFlat Where to store the flat address upon successful return.
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| 351 | */
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| 352 | VMMDECL(int) SELMValidateAndConvertCSAddr(PVMCPU pVCpu, X86EFLAGS Efl, RTSEL SelCPL, RTSEL SelCS, PCPUMSELREG pSRegCS,
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| 353 | RTGCPTR Addr, PRTGCPTR ppvFlat)
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| 354 | {
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| 355 | if ( Efl.Bits.u1VM
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| 356 | || CPUMIsGuestInRealMode(pVCpu))
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| 357 | return selmValidateAndConvertCSAddrRealMode(pVCpu, SelCS, pSRegCS, Addr, ppvFlat);
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| 358 |
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| 359 | Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS));
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| 360 | Assert(pSRegCS->Sel == SelCS);
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| 361 |
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| 362 | return selmValidateAndConvertCSAddrHidden(pVCpu, SelCPL, SelCS, pSRegCS, Addr, ppvFlat);
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| 363 | }
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| 364 |
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| 365 |
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| 366 | /**
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| 367 | * Gets info about the current TSS.
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| 368 | *
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| 369 | * @returns VBox status code.
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| 370 | * @retval VINF_SUCCESS if we've got a TSS loaded.
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| 371 | * @retval VERR_SELM_NO_TSS if we haven't got a TSS (rather unlikely).
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| 372 | *
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| 373 | * @param pVM The cross context VM structure.
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| 374 | * @param pVCpu The cross context virtual CPU structure.
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| 375 | * @param pGCPtrTss Where to store the TSS address.
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| 376 | * @param pcbTss Where to store the TSS size limit.
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| 377 | * @param pfCanHaveIOBitmap Where to store the can-have-I/O-bitmap indicator. (optional)
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| 378 | */
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| 379 | VMMDECL(int) SELMGetTSSInfo(PVM pVM, PVMCPU pVCpu, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap)
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| 380 | {
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| 381 | NOREF(pVM);
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| 382 |
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| 383 | /*
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| 384 | * The TR hidden register is always valid.
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| 385 | */
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| 386 | CPUMSELREGHID trHid;
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| 387 | RTSEL tr = CPUMGetGuestTR(pVCpu, &trHid);
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| 388 | if (!(tr & X86_SEL_MASK_OFF_RPL))
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| 389 | return VERR_SELM_NO_TSS;
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| 390 |
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| 391 | *pGCPtrTss = trHid.u64Base;
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| 392 | *pcbTss = trHid.u32Limit + (trHid.u32Limit != UINT32_MAX); /* be careful. */
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| 393 | if (pfCanHaveIOBitmap)
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| 394 | *pfCanHaveIOBitmap = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
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| 395 | || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
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| 396 | return VINF_SUCCESS;
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| 397 | }
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| 398 |
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