VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 96879

Last change on this file since 96879 was 96879, checked in by vboxsync, 20 months ago

VMM/PGM: Nested VMX: bugref:10092 Nested EPT shadow page-pool handling.
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1/* $Id: PGMAllShw.h 96879 2022-09-26 17:43:43Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Shadow Paging Template - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Defined Constants And Macros *
31*********************************************************************************************************************************/
32#undef SHWUINT
33#undef SHWPT
34#undef PSHWPT
35#undef SHWPTE
36#undef PSHWPTE
37#undef SHWPD
38#undef PSHWPD
39#undef SHWPDE
40#undef PSHWPDE
41#undef SHW_PDE_PG_MASK
42#undef SHW_PD_SHIFT
43#undef SHW_PD_MASK
44#undef SHW_PDE_ATOMIC_SET
45#undef SHW_PDE_ATOMIC_SET2
46#undef SHW_PDE_IS_P
47#undef SHW_PDE_IS_A
48#undef SHW_PDE_IS_BIG
49#undef SHW_PTE_PG_MASK
50#undef SHW_PTE_IS_P
51#undef SHW_PTE_IS_RW
52#undef SHW_PTE_IS_US
53#undef SHW_PTE_IS_A
54#undef SHW_PTE_IS_D
55#undef SHW_PTE_IS_P_RW
56#undef SHW_PTE_IS_TRACK_DIRTY
57#undef SHW_PTE_GET_HCPHYS
58#undef SHW_PTE_GET_U
59#undef SHW_PTE_LOG64
60#undef SHW_PTE_SET
61#undef SHW_PTE_ATOMIC_SET
62#undef SHW_PTE_ATOMIC_SET2
63#undef SHW_PTE_SET_RO
64#undef SHW_PTE_SET_RW
65#undef SHW_PT_SHIFT
66#undef SHW_PT_MASK
67#undef SHW_TOTAL_PD_ENTRIES
68#undef SHW_PDPT_SHIFT
69#undef SHW_PDPT_MASK
70#undef SHW_PDPE_PG_MASK
71
72#if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
73# define SHWUINT uint32_t
74# define SHWPT X86PT
75# define PSHWPT PX86PT
76# define SHWPTE X86PTE
77# define PSHWPTE PX86PTE
78# define SHWPD X86PD
79# define PSHWPD PX86PD
80# define SHWPDE X86PDE
81# define PSHWPDE PX86PDE
82# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
83# define SHW_PD_SHIFT X86_PD_SHIFT
84# define SHW_PD_MASK X86_PD_MASK
85# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
86# define SHW_PDE_IS_P(Pde) ( (Pde).u & X86_PDE_P )
87# define SHW_PDE_IS_A(Pde) ( (Pde).u & X86_PDE_A )
88# define SHW_PDE_IS_BIG(Pde) ( (Pde).u & X86_PDE_PS )
89# define SHW_PDE_ATOMIC_SET(Pde, uNew) do { ASMAtomicWriteU32(&(Pde).u, (uNew)); } while (0)
90# define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU32(&(Pde).u, (Pde2).u); } while (0)
91# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
92# define SHW_PTE_IS_P(Pte) ( (Pte).u & X86_PTE_P )
93# define SHW_PTE_IS_RW(Pte) ( (Pte).u & X86_PTE_RW )
94# define SHW_PTE_IS_US(Pte) ( (Pte).u & X86_PTE_US )
95# define SHW_PTE_IS_A(Pte) ( (Pte).u & X86_PTE_A )
96# define SHW_PTE_IS_D(Pte) ( (Pte).u & X86_PTE_D )
97# define SHW_PTE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
98# define SHW_PTE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
99# define SHW_PTE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PG_MASK )
100# define SHW_PTE_LOG64(Pte) ( (uint64_t)(Pte).u )
101# define SHW_PTE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
102# define SHW_PTE_SET(Pte, uNew) do { (Pte).u = (uNew); } while (0)
103# define SHW_PTE_ATOMIC_SET(Pte, uNew) do { ASMAtomicWriteU32(&(Pte).u, (uNew)); } while (0)
104# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU32(&(Pte).u, (Pte2).u); } while (0)
105# define SHW_PTE_SET_RO(Pte) do { (Pte).u &= ~(X86PGUINT)X86_PTE_RW; } while (0)
106# define SHW_PTE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
107# define SHW_PT_SHIFT X86_PT_SHIFT
108# define SHW_PT_MASK X86_PT_MASK
109
110#elif PGM_SHW_TYPE == PGM_TYPE_EPT
111# define SHWUINT uint64_t
112# define SHWPT EPTPT
113# define PSHWPT PEPTPT
114# define SHWPTE EPTPTE
115# define PSHWPTE PEPTPTE
116# define SHWPD EPTPD
117# define PSHWPD PEPTPD
118# define SHWPDE EPTPDE
119# define PSHWPDE PEPTPDE
120# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
121# define SHW_PD_SHIFT EPT_PD_SHIFT
122# define SHW_PD_MASK EPT_PD_MASK
123# define SHW_PDE_IS_P(Pde) ( (Pde).u & EPT_E_READ /* always set*/ )
124# define SHW_PDE_IS_A(Pde) ( 1 ) /* We don't use EPT_E_ACCESSED, use with care! */
125# define SHW_PDE_IS_BIG(Pde) ( (Pde).u & EPT_E_LEAF )
126# define SHW_PDE_ATOMIC_SET(Pde, uNew) do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
127# define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU64(&(Pde).u, (Pde2).u); } while (0)
128# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
129# define SHW_PTE_IS_P(Pte) ( (Pte).u & EPT_E_READ ) /* Approximation, works for us. */
130# define SHW_PTE_IS_RW(Pte) ( (Pte).u & EPT_E_WRITE )
131# define SHW_PTE_IS_US(Pte) ( true )
132# define SHW_PTE_IS_A(Pte) ( true )
133# define SHW_PTE_IS_D(Pte) ( true )
134# define SHW_PTE_IS_P_RW(Pte) ( ((Pte).u & (EPT_E_READ | EPT_E_WRITE)) == (EPT_E_READ | EPT_E_WRITE) )
135# define SHW_PTE_IS_TRACK_DIRTY(Pte) ( false )
136# define SHW_PTE_GET_HCPHYS(Pte) ( (Pte).u & EPT_PTE_PG_MASK )
137# define SHW_PTE_LOG64(Pte) ( (Pte).u )
138# define SHW_PTE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
139# define SHW_PTE_SET(Pte, uNew) do { (Pte).u = (uNew); } while (0)
140# define SHW_PTE_ATOMIC_SET(Pte, uNew) do { ASMAtomicWriteU64(&(Pte).u, (uNew)); } while (0)
141# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
142# define SHW_PTE_SET_RO(Pte) do { (Pte).u &= ~(uint64_t)EPT_E_WRITE; } while (0)
143# define SHW_PTE_SET_RW(Pte) do { (Pte).u |= EPT_E_WRITE; } while (0)
144# define SHW_PT_SHIFT EPT_PT_SHIFT
145# define SHW_PT_MASK EPT_PT_MASK
146# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
147# define SHW_PDPT_MASK EPT_PDPT_MASK
148# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
149# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES * EPT_PG_AMD64_PDPE_ENTRIES)
150
151#else
152# define SHWUINT uint64_t
153# define SHWPT PGMSHWPTPAE
154# define PSHWPT PPGMSHWPTPAE
155# define SHWPTE PGMSHWPTEPAE
156# define PSHWPTE PPGMSHWPTEPAE
157# define SHWPD X86PDPAE
158# define PSHWPD PX86PDPAE
159# define SHWPDE X86PDEPAE
160# define PSHWPDE PX86PDEPAE
161# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
162# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
163# define SHW_PD_MASK X86_PD_PAE_MASK
164# define SHW_PDE_IS_P(Pde) ( (Pde).u & X86_PDE_P )
165# define SHW_PDE_IS_A(Pde) ( (Pde).u & X86_PDE_A )
166# define SHW_PDE_IS_BIG(Pde) ( (Pde).u & X86_PDE_PS )
167# define SHW_PDE_ATOMIC_SET(Pde, uNew) do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
168# define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU64(&(Pde).u, (Pde2).u); } while (0)
169# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
170# define SHW_PTE_IS_P(Pte) PGMSHWPTEPAE_IS_P(Pte)
171# define SHW_PTE_IS_RW(Pte) PGMSHWPTEPAE_IS_RW(Pte)
172# define SHW_PTE_IS_US(Pte) PGMSHWPTEPAE_IS_US(Pte)
173# define SHW_PTE_IS_A(Pte) PGMSHWPTEPAE_IS_A(Pte)
174# define SHW_PTE_IS_D(Pte) PGMSHWPTEPAE_IS_D(Pte)
175# define SHW_PTE_IS_P_RW(Pte) PGMSHWPTEPAE_IS_P_RW(Pte)
176# define SHW_PTE_IS_TRACK_DIRTY(Pte) PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte)
177# define SHW_PTE_GET_HCPHYS(Pte) PGMSHWPTEPAE_GET_HCPHYS(Pte)
178# define SHW_PTE_LOG64(Pte) PGMSHWPTEPAE_GET_LOG(Pte)
179# define SHW_PTE_GET_U(Pte) PGMSHWPTEPAE_GET_U(Pte) /**< Use with care. */
180# define SHW_PTE_SET(Pte, uNew) PGMSHWPTEPAE_SET(Pte, uNew)
181# define SHW_PTE_ATOMIC_SET(Pte, uNew) PGMSHWPTEPAE_ATOMIC_SET(Pte, uNew)
182# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2)
183# define SHW_PTE_SET_RO(Pte) PGMSHWPTEPAE_SET_RO(Pte)
184# define SHW_PTE_SET_RW(Pte) PGMSHWPTEPAE_SET_RW(Pte)
185# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
186# define SHW_PT_MASK X86_PT_PAE_MASK
187
188# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64 || /* whatever: */ PGM_SHW_TYPE == PGM_TYPE_NONE
189# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
190# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
191# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
192# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
193
194# elif PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
195# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
196# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
197# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
198# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
199
200# else
201# error "Misconfigured PGM_SHW_TYPE or something..."
202# endif
203#endif
204
205#if PGM_SHW_TYPE == PGM_TYPE_NONE && PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
206# error "PGM_TYPE_IS_NESTED_OR_EPT is true for PGM_TYPE_NONE!"
207#endif
208
209
210
211/*********************************************************************************************************************************
212* Internal Functions *
213*********************************************************************************************************************************/
214RT_C_DECLS_BEGIN
215PGM_SHW_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
216PGM_SHW_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
217PGM_SHW_DECL(int, Enter)(PVMCPUCC pVCpu, bool fIs64BitsPagingMode);
218PGM_SHW_DECL(int, Exit)(PVMCPUCC pVCpu);
219#ifdef IN_RING3
220PGM_SHW_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
221#endif
222RT_C_DECLS_END
223
224
225/**
226 * Enters the shadow mode.
227 *
228 * @returns VBox status code.
229 * @param pVCpu The cross context virtual CPU structure.
230 * @param fIs64BitsPagingMode New shadow paging mode is for 64 bits? (only relevant for 64 bits guests on a 32 bits AMD-V nested paging host)
231 */
232PGM_SHW_DECL(int, Enter)(PVMCPUCC pVCpu, bool fIs64BitsPagingMode)
233{
234#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
235
236# if PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && HC_ARCH_BITS == 32
237 /* Must distinguish between 32 and 64 bits guest paging modes as we'll use
238 a different shadow paging root/mode in both cases. */
239 RTGCPHYS GCPhysCR3 = (fIs64BitsPagingMode) ? RT_BIT_64(63) : RT_BIT_64(62);
240 PGMPOOLKIND enmKind = PGMPOOLKIND_ROOT_NESTED;
241# elif defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT)
242 RTGCPHYS GCPhysCR3;
243 PGMPOOLKIND enmKind;
244 if (pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_EPT)
245 {
246 GCPhysCR3 = RT_BIT_64(63); NOREF(fIs64BitsPagingMode);
247 enmKind = PGMPOOLKIND_ROOT_NESTED;
248 }
249 else
250 {
251 GCPhysCR3 = pVCpu->pgm.s.uEptPtr & EPT_EPTP_PG_MASK;
252 enmKind = PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4;
253 }
254# else
255 RTGCPHYS GCPhysCR3 = RT_BIT_64(63); NOREF(fIs64BitsPagingMode);
256 PGMPOOLKIND const enmKind = PGMPOOLKIND_ROOT_NESTED;
257# endif
258 PPGMPOOLPAGE pNewShwPageCR3;
259 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
260
261 Assert(HMIsNestedPagingActive(pVM));
262 Assert(pVM->pgm.s.fNestedPaging);
263 Assert(!pVCpu->pgm.s.pShwPageCR3R3);
264
265 PGM_LOCK_VOID(pVM);
266
267 int rc = pgmPoolAlloc(pVM, GCPhysCR3, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
268 NIL_PGMPOOL_IDX, UINT32_MAX, true /*fLockPage*/,
269 &pNewShwPageCR3);
270 AssertLogRelRCReturnStmt(rc, PGM_UNLOCK(pVM), rc);
271
272 pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pVM->pgm.s.CTX_SUFF(pPool), pNewShwPageCR3);
273 pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pVM->pgm.s.CTX_SUFF(pPool), pNewShwPageCR3);
274
275 PGM_UNLOCK(pVM);
276
277 Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
278#else
279 NOREF(pVCpu); NOREF(fIs64BitsPagingMode);
280#endif
281 return VINF_SUCCESS;
282}
283
284
285/**
286 * Exits the shadow mode.
287 *
288 * @returns VBox status code.
289 * @param pVCpu The cross context virtual CPU structure.
290 */
291PGM_SHW_DECL(int, Exit)(PVMCPUCC pVCpu)
292{
293#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
294 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
295 if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
296 {
297 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
298
299 PGM_LOCK_VOID(pVM);
300
301# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
302 if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
303 pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
304# endif
305
306 /* Do *not* unlock this page as we have two of them floating around in the 32-bit host & 64-bit guest case.
307 * We currently assert when you try to free one of them; don't bother to really allow this.
308 *
309 * Note that this is two nested paging root pages max. This isn't a leak. They are reused.
310 */
311 /* pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)); */
312
313 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
314 pVCpu->pgm.s.pShwPageCR3R3 = 0;
315 pVCpu->pgm.s.pShwPageCR3R0 = 0;
316
317 PGM_UNLOCK(pVM);
318
319 Log(("Leave nested shadow paging mode\n"));
320 }
321#else
322 RT_NOREF_PV(pVCpu);
323#endif
324 return VINF_SUCCESS;
325}
326
327
328/**
329 * Gets effective page information (from the VMM page directory).
330 *
331 * @returns VBox status code.
332 * @param pVCpu The cross context virtual CPU structure.
333 * @param GCPtr Guest Context virtual address of the page.
334 * @param pfFlags Where to store the flags. These are X86_PTE_*.
335 * @param pHCPhys Where to store the HC physical address of the page.
336 * This is page aligned.
337 * @remark You should use PGMMapGetPage() for pages in a mapping.
338 */
339PGM_SHW_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
340{
341#if PGM_SHW_TYPE == PGM_TYPE_NONE
342 RT_NOREF(pVCpu, GCPtr);
343 AssertFailed();
344 *pfFlags = 0;
345 *pHCPhys = NIL_RTHCPHYS;
346 return VERR_PGM_SHW_NONE_IPE;
347
348#else /* PGM_SHW_TYPE != PGM_TYPE_NONE */
349 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
350
351 PGM_LOCK_ASSERT_OWNER(pVM);
352
353 /*
354 * Get the PDE.
355 */
356# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
357 X86PDEPAE Pde;
358
359 /* PML4 */
360 X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
361 if (!(Pml4e.u & X86_PML4E_P))
362 return VERR_PAGE_TABLE_NOT_PRESENT;
363
364 /* PDPT */
365 PX86PDPT pPDPT;
366 int rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
367 if (RT_FAILURE(rc))
368 return rc;
369 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
370 X86PDPE Pdpe = pPDPT->a[iPDPT];
371 if (!(Pdpe.u & X86_PDPE_P))
372 return VERR_PAGE_TABLE_NOT_PRESENT;
373
374 /* PD */
375 PX86PDPAE pPd;
376 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
377 if (RT_FAILURE(rc))
378 return rc;
379 const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
380 Pde = pPd->a[iPd];
381
382 /* Merge accessed, write, user and no-execute bits into the PDE. */
383 AssertCompile(X86_PML4E_A == X86_PDPE_A && X86_PML4E_A == X86_PDE_A);
384 AssertCompile(X86_PML4E_RW == X86_PDPE_RW && X86_PML4E_RW == X86_PDE_RW);
385 AssertCompile(X86_PML4E_US == X86_PDPE_US && X86_PML4E_US == X86_PDE_US);
386 AssertCompile(X86_PML4E_NX == X86_PDPE_LM_NX && X86_PML4E_NX == X86_PDE_PAE_NX);
387 Pde.u &= (Pml4e.u & Pdpe.u) | ~(X86PGPAEUINT)(X86_PML4E_A | X86_PML4E_RW | X86_PML4E_US);
388 Pde.u |= (Pml4e.u | Pdpe.u) & X86_PML4E_NX;
389
390# elif PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
391 X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
392
393# elif PGM_SHW_TYPE == PGM_TYPE_EPT
394 Assert(pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_DIRECT);
395 PEPTPD pPDDst;
396 int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
397 if (rc == VINF_SUCCESS) /** @todo this function isn't expected to return informational status codes. Check callers / fix. */
398 { /* likely */ }
399 else
400 {
401 AssertRC(rc);
402 return rc;
403 }
404 Assert(pPDDst);
405
406 const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
407 EPTPDE Pde = pPDDst->a[iPd];
408
409# elif PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
410 X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
411
412# else
413# error "Misconfigured PGM_SHW_TYPE or something..."
414# endif
415 if (!SHW_PDE_IS_P(Pde))
416 return VERR_PAGE_TABLE_NOT_PRESENT;
417
418 /* Deal with large pages. */
419 if (SHW_PDE_IS_BIG(Pde))
420 {
421 /*
422 * Store the results.
423 * RW and US flags depend on the entire page translation hierarchy - except for
424 * legacy PAE which has a simplified PDPE.
425 */
426 if (pfFlags)
427 {
428 *pfFlags = (Pde.u & ~SHW_PDE_PG_MASK);
429# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
430 if ( (Pde.u & X86_PTE_PAE_NX)
431# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
432 && CPUMIsGuestNXEnabled(pVCpu) /** @todo why do we have to check the guest state here? */
433# endif
434 )
435 *pfFlags |= X86_PTE_PAE_NX;
436# endif
437 }
438
439 if (pHCPhys)
440 *pHCPhys = (Pde.u & SHW_PDE_PG_MASK) + (GCPtr & (RT_BIT(SHW_PD_SHIFT) - 1) & X86_PAGE_4K_BASE_MASK);
441
442 return VINF_SUCCESS;
443 }
444
445 /*
446 * Get PT entry.
447 */
448 PSHWPT pPT;
449 int rc2 = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
450 if (RT_FAILURE(rc2))
451 return rc2;
452 const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
453 SHWPTE Pte = pPT->a[iPt];
454 if (!SHW_PTE_IS_P(Pte))
455 return VERR_PAGE_NOT_PRESENT;
456
457 /*
458 * Store the results.
459 * RW and US flags depend on the entire page translation hierarchy - except for
460 * legacy PAE which has a simplified PDPE.
461 */
462 if (pfFlags)
463 {
464 *pfFlags = (SHW_PTE_GET_U(Pte) & ~SHW_PTE_PG_MASK)
465 & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
466
467# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
468 /* The NX bit is determined by a bitwise OR between the PT and PD */
469 if ( ((SHW_PTE_GET_U(Pte) | Pde.u) & X86_PTE_PAE_NX)
470# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
471 && CPUMIsGuestNXEnabled(pVCpu) /** @todo why do we have to check the guest state here? */
472# endif
473 )
474 *pfFlags |= X86_PTE_PAE_NX;
475# endif
476 }
477
478 if (pHCPhys)
479 *pHCPhys = SHW_PTE_GET_HCPHYS(Pte);
480
481 return VINF_SUCCESS;
482#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
483}
484
485
486/**
487 * Modify page flags for a range of pages in the shadow context.
488 *
489 * The existing flags are ANDed with the fMask and ORed with the fFlags.
490 *
491 * @returns VBox status code.
492 * @param pVCpu The cross context virtual CPU structure.
493 * @param GCPtr Virtual address of the first page in the range. Page aligned!
494 * @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
495 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
496 * @param fMask The AND mask - page flags X86_PTE_*.
497 * Be extremely CAREFUL with ~'ing values because they can be 32-bit!
498 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
499 * @remark You must use PGMMapModifyPage() for pages in a mapping.
500 */
501PGM_SHW_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
502{
503#if PGM_SHW_TYPE == PGM_TYPE_NONE
504 RT_NOREF(pVCpu, GCPtr, cb, fFlags, fMask, fOpFlags);
505 AssertFailed();
506 return VERR_PGM_SHW_NONE_IPE;
507
508#else /* PGM_SHW_TYPE != PGM_TYPE_NONE */
509 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
510 PGM_LOCK_ASSERT_OWNER(pVM);
511
512 /*
513 * Walk page tables and pages till we're done.
514 */
515 int rc;
516 for (;;)
517 {
518 /*
519 * Get the PDE.
520 */
521# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
522 X86PDEPAE Pde;
523 /* PML4 */
524 X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
525 if (!(Pml4e.u & X86_PML4E_P))
526 return VERR_PAGE_TABLE_NOT_PRESENT;
527
528 /* PDPT */
529 PX86PDPT pPDPT;
530 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
531 if (RT_FAILURE(rc))
532 return rc;
533 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
534 X86PDPE Pdpe = pPDPT->a[iPDPT];
535 if (!(Pdpe.u & X86_PDPE_P))
536 return VERR_PAGE_TABLE_NOT_PRESENT;
537
538 /* PD */
539 PX86PDPAE pPd;
540 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
541 if (RT_FAILURE(rc))
542 return rc;
543 const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
544 Pde = pPd->a[iPd];
545
546# elif PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
547 X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
548
549# elif PGM_SHW_TYPE == PGM_TYPE_EPT
550 Assert(pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_DIRECT);
551 const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
552 PEPTPD pPDDst;
553 EPTPDE Pde;
554
555 rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
556 if (rc != VINF_SUCCESS)
557 {
558 AssertRC(rc);
559 return rc;
560 }
561 Assert(pPDDst);
562 Pde = pPDDst->a[iPd];
563
564# else /* PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT */
565 X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
566# endif
567 if (!SHW_PDE_IS_P(Pde))
568 return VERR_PAGE_TABLE_NOT_PRESENT;
569
570 AssertFatalMsg(!SHW_PDE_IS_BIG(Pde), ("Pde=%#RX64\n", (uint64_t)Pde.u));
571
572 /*
573 * Map the page table.
574 */
575 PSHWPT pPT;
576 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
577 if (RT_FAILURE(rc))
578 return rc;
579
580 unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
581 while (iPTE < RT_ELEMENTS(pPT->a))
582 {
583 if (SHW_PTE_IS_P(pPT->a[iPTE]))
584 {
585 SHWPTE const OrgPte = pPT->a[iPTE];
586 SHWPTE NewPte;
587
588 SHW_PTE_SET(NewPte, (SHW_PTE_GET_U(OrgPte) & (fMask | SHW_PTE_PG_MASK)) | (fFlags & ~SHW_PTE_PG_MASK));
589 if (!SHW_PTE_IS_P(NewPte))
590 {
591 /** @todo Some CSAM code path might end up here and upset
592 * the page pool. */
593 AssertMsgFailed(("NewPte=%#RX64 OrgPte=%#RX64 GCPtr=%#RGv\n", SHW_PTE_LOG64(NewPte), SHW_PTE_LOG64(OrgPte), GCPtr));
594 }
595 else if ( SHW_PTE_IS_RW(NewPte)
596 && !SHW_PTE_IS_RW(OrgPte)
597 && !(fOpFlags & PGM_MK_PG_IS_MMIO2) )
598 {
599 /** @todo Optimize \#PF handling by caching data. We can
600 * then use this when PGM_MK_PG_IS_WRITE_FAULT is
601 * set instead of resolving the guest physical
602 * address yet again. */
603 PGMPTWALK GstWalk;
604 rc = PGMGstGetPage(pVCpu, GCPtr, &GstWalk);
605 AssertRC(rc);
606 if (RT_SUCCESS(rc))
607 {
608 Assert((GstWalk.fEffective & X86_PTE_RW) || !(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP /* allow netware hack */));
609 PPGMPAGE pPage = pgmPhysGetPage(pVM, GstWalk.GCPhys);
610 Assert(pPage);
611 if (pPage)
612 {
613 rc = pgmPhysPageMakeWritable(pVM, pPage, GstWalk.GCPhys);
614 AssertRCReturn(rc, rc);
615 Log(("%s: pgmPhysPageMakeWritable on %RGv / %RGp %R[pgmpage]\n", __PRETTY_FUNCTION__, GCPtr, GstWalk.GCPhys, pPage));
616 }
617 }
618 }
619
620 SHW_PTE_ATOMIC_SET2(pPT->a[iPTE], NewPte);
621# if PGM_SHW_TYPE == PGM_TYPE_EPT
622 HMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
623# else
624 PGM_INVL_PG_ALL_VCPU(pVM, GCPtr);
625# endif
626 }
627
628 /* next page */
629 cb -= HOST_PAGE_SIZE;
630 if (!cb)
631 return VINF_SUCCESS;
632 GCPtr += HOST_PAGE_SIZE;
633 iPTE++;
634 }
635 }
636#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
637}
638
639
640#ifdef IN_RING3
641/**
642 * Relocate any GC pointers related to shadow mode paging.
643 *
644 * @returns VBox status code.
645 * @param pVCpu The cross context virtual CPU structure.
646 * @param offDelta The relocation offset.
647 */
648PGM_SHW_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta)
649{
650 RT_NOREF(pVCpu, offDelta);
651 return VINF_SUCCESS;
652}
653#endif
654
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