VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 74795

Last change on this file since 74795 was 73324, checked in by vboxsync, 6 years ago

PGM: Introduced a special shadow paging mode for NEM that translates to minimal unnecessary work. bugref:9044
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1/* $Id: PGMAllShw.h 73324 2018-07-23 14:06:55Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Shadow Paging Template - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#undef SHWPT
23#undef PSHWPT
24#undef SHWPTE
25#undef PSHWPTE
26#undef SHWPD
27#undef PSHWPD
28#undef SHWPDE
29#undef PSHWPDE
30#undef SHW_PDE_PG_MASK
31#undef SHW_PD_SHIFT
32#undef SHW_PD_MASK
33#undef SHW_PTE_PG_MASK
34#undef SHW_PTE_IS_P
35#undef SHW_PTE_IS_RW
36#undef SHW_PTE_IS_US
37#undef SHW_PTE_IS_A
38#undef SHW_PTE_IS_D
39#undef SHW_PTE_IS_P_RW
40#undef SHW_PTE_IS_TRACK_DIRTY
41#undef SHW_PTE_GET_HCPHYS
42#undef SHW_PTE_GET_U
43#undef SHW_PTE_LOG64
44#undef SHW_PTE_SET
45#undef SHW_PTE_ATOMIC_SET
46#undef SHW_PTE_ATOMIC_SET2
47#undef SHW_PTE_SET_RO
48#undef SHW_PTE_SET_RW
49#undef SHW_PT_SHIFT
50#undef SHW_PT_MASK
51#undef SHW_TOTAL_PD_ENTRIES
52#undef SHW_PDPT_SHIFT
53#undef SHW_PDPT_MASK
54#undef SHW_PDPE_PG_MASK
55
56#if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
57# define SHWPT X86PT
58# define PSHWPT PX86PT
59# define SHWPTE X86PTE
60# define PSHWPTE PX86PTE
61# define SHWPD X86PD
62# define PSHWPD PX86PD
63# define SHWPDE X86PDE
64# define PSHWPDE PX86PDE
65# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
66# define SHW_PD_SHIFT X86_PD_SHIFT
67# define SHW_PD_MASK X86_PD_MASK
68# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
69# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
70# define SHW_PTE_IS_P(Pte) ( (Pte).n.u1Present )
71# define SHW_PTE_IS_RW(Pte) ( (Pte).n.u1Write )
72# define SHW_PTE_IS_US(Pte) ( (Pte).n.u1User )
73# define SHW_PTE_IS_A(Pte) ( (Pte).n.u1Accessed )
74# define SHW_PTE_IS_D(Pte) ( (Pte).n.u1Dirty )
75# define SHW_PTE_IS_P_RW(Pte) ( (Pte).n.u1Present && (Pte).n.u1Write )
76# define SHW_PTE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
77# define SHW_PTE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PG_MASK )
78# define SHW_PTE_LOG64(Pte) ( (uint64_t)(Pte).u )
79# define SHW_PTE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
80# define SHW_PTE_SET(Pte, uNew) do { (Pte).u = (uNew); } while (0)
81# define SHW_PTE_ATOMIC_SET(Pte, uNew) do { ASMAtomicWriteU32(&(Pte).u, (uNew)); } while (0)
82# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU32(&(Pte).u, (Pte2).u); } while (0)
83# define SHW_PTE_SET_RO(Pte) do { (Pte).n.u1Write = 0; } while (0)
84# define SHW_PTE_SET_RW(Pte) do { (Pte).n.u1Write = 1; } while (0)
85# define SHW_PT_SHIFT X86_PT_SHIFT
86# define SHW_PT_MASK X86_PT_MASK
87
88#elif PGM_SHW_TYPE == PGM_TYPE_EPT
89# define SHWPT EPTPT
90# define PSHWPT PEPTPT
91# define SHWPTE EPTPTE
92# define PSHWPTE PEPTPTE
93# define SHWPD EPTPD
94# define PSHWPD PEPTPD
95# define SHWPDE EPTPDE
96# define PSHWPDE PEPTPDE
97# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
98# define SHW_PD_SHIFT EPT_PD_SHIFT
99# define SHW_PD_MASK EPT_PD_MASK
100# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
101# define SHW_PTE_IS_P(Pte) ( (Pte).n.u1Present ) /* Approximation, works for us. */
102# define SHW_PTE_IS_RW(Pte) ( (Pte).n.u1Write )
103# define SHW_PTE_IS_US(Pte) ( true )
104# define SHW_PTE_IS_A(Pte) ( true )
105# define SHW_PTE_IS_D(Pte) ( true )
106# define SHW_PTE_IS_P_RW(Pte) ( (Pte).n.u1Present && (Pte).n.u1Write )
107# define SHW_PTE_IS_TRACK_DIRTY(Pte) ( false )
108# define SHW_PTE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PG_MASK )
109# define SHW_PTE_LOG64(Pte) ( (Pte).u )
110# define SHW_PTE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
111# define SHW_PTE_SET(Pte, uNew) do { (Pte).u = (uNew); } while (0)
112# define SHW_PTE_ATOMIC_SET(Pte, uNew) do { ASMAtomicWriteU64(&(Pte).u, (uNew)); } while (0)
113# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
114# define SHW_PTE_SET_RO(Pte) do { (Pte).n.u1Write = 0; } while (0)
115# define SHW_PTE_SET_RW(Pte) do { (Pte).n.u1Write = 1; } while (0)
116# define SHW_PT_SHIFT EPT_PT_SHIFT
117# define SHW_PT_MASK EPT_PT_MASK
118# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
119# define SHW_PDPT_MASK EPT_PDPT_MASK
120# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
121# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
122
123#else
124# define SHWPT PGMSHWPTPAE
125# define PSHWPT PPGMSHWPTPAE
126# define SHWPTE PGMSHWPTEPAE
127# define PSHWPTE PPGMSHWPTEPAE
128# define SHWPD X86PDPAE
129# define PSHWPD PX86PDPAE
130# define SHWPDE X86PDEPAE
131# define PSHWPDE PX86PDEPAE
132# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
133# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
134# define SHW_PD_MASK X86_PD_PAE_MASK
135# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
136# define SHW_PTE_IS_P(Pte) PGMSHWPTEPAE_IS_P(Pte)
137# define SHW_PTE_IS_RW(Pte) PGMSHWPTEPAE_IS_RW(Pte)
138# define SHW_PTE_IS_US(Pte) PGMSHWPTEPAE_IS_US(Pte)
139# define SHW_PTE_IS_A(Pte) PGMSHWPTEPAE_IS_A(Pte)
140# define SHW_PTE_IS_D(Pte) PGMSHWPTEPAE_IS_D(Pte)
141# define SHW_PTE_IS_P_RW(Pte) PGMSHWPTEPAE_IS_P_RW(Pte)
142# define SHW_PTE_IS_TRACK_DIRTY(Pte) PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte)
143# define SHW_PTE_GET_HCPHYS(Pte) PGMSHWPTEPAE_GET_HCPHYS(Pte)
144# define SHW_PTE_LOG64(Pte) PGMSHWPTEPAE_GET_LOG(Pte)
145# define SHW_PTE_GET_U(Pte) PGMSHWPTEPAE_GET_U(Pte) /**< Use with care. */
146# define SHW_PTE_SET(Pte, uNew) PGMSHWPTEPAE_SET(Pte, uNew)
147# define SHW_PTE_ATOMIC_SET(Pte, uNew) PGMSHWPTEPAE_ATOMIC_SET(Pte, uNew)
148# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2)
149# define SHW_PTE_SET_RO(Pte) PGMSHWPTEPAE_SET_RO(Pte)
150# define SHW_PTE_SET_RW(Pte) PGMSHWPTEPAE_SET_RW(Pte)
151# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
152# define SHW_PT_MASK X86_PT_PAE_MASK
153
154# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64 || /* whatever: */ PGM_SHW_TYPE == PGM_TYPE_NONE
155# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
156# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
157# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
158# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
159
160# elif PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
161# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
162# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
163# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
164# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
165
166# else
167# error "Misconfigured PGM_SHW_TYPE or something..."
168# endif
169#endif
170
171#if PGM_SHW_TYPE == PGM_TYPE_NONE && PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
172# error "PGM_TYPE_IS_NESTED_OR_EPT is true for PGM_TYPE_NONE!"
173#endif
174
175
176
177/*********************************************************************************************************************************
178* Internal Functions *
179*********************************************************************************************************************************/
180RT_C_DECLS_BEGIN
181PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
182PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
183PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
184PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu);
185#ifdef IN_RING3
186PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
187#endif
188RT_C_DECLS_END
189
190
191/**
192 * Enters the shadow mode.
193 *
194 * @returns VBox status code.
195 * @param pVCpu The cross context virtual CPU structure.
196 * @param fIs64BitsPagingMode New shadow paging mode is for 64 bits? (only relevant for 64 bits guests on a 32 bits AMD-V nested paging host)
197 */
198PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode)
199{
200#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
201
202# if PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && HC_ARCH_BITS == 32
203 /* Must distinguish between 32 and 64 bits guest paging modes as we'll use
204 a different shadow paging root/mode in both cases. */
205 RTGCPHYS GCPhysCR3 = (fIs64BitsPagingMode) ? RT_BIT_64(63) : RT_BIT_64(62);
206# else
207 RTGCPHYS GCPhysCR3 = RT_BIT_64(63); NOREF(fIs64BitsPagingMode);
208# endif
209 PPGMPOOLPAGE pNewShwPageCR3;
210 PVM pVM = pVCpu->CTX_SUFF(pVM);
211
212 Assert((HMIsNestedPagingActive(pVM) || VM_IS_NEM_ENABLED(pVM)) == pVM->pgm.s.fNestedPaging);
213 Assert(pVM->pgm.s.fNestedPaging);
214 Assert(!pVCpu->pgm.s.pShwPageCR3R3);
215
216 pgmLock(pVM);
217
218 int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
219 NIL_PGMPOOL_IDX, UINT32_MAX, true /*fLockPage*/,
220 &pNewShwPageCR3);
221 AssertLogRelRCReturnStmt(rc, pgmUnlock(pVM), rc);
222
223 pVCpu->pgm.s.pShwPageCR3R3 = (R3PTRTYPE(PPGMPOOLPAGE))MMHyperCCToR3(pVM, pNewShwPageCR3);
224 pVCpu->pgm.s.pShwPageCR3RC = (RCPTRTYPE(PPGMPOOLPAGE))MMHyperCCToRC(pVM, pNewShwPageCR3);
225 pVCpu->pgm.s.pShwPageCR3R0 = (R0PTRTYPE(PPGMPOOLPAGE))MMHyperCCToR0(pVM, pNewShwPageCR3);
226
227 pgmUnlock(pVM);
228
229 Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
230#else
231 NOREF(pVCpu); NOREF(fIs64BitsPagingMode);
232#endif
233 return VINF_SUCCESS;
234}
235
236
237/**
238 * Exits the shadow mode.
239 *
240 * @returns VBox status code.
241 * @param pVCpu The cross context virtual CPU structure.
242 */
243PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu)
244{
245#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
246 PVM pVM = pVCpu->CTX_SUFF(pVM);
247 if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
248 {
249 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
250
251 pgmLock(pVM);
252
253 /* Do *not* unlock this page as we have two of them floating around in the 32-bit host & 64-bit guest case.
254 * We currently assert when you try to free one of them; don't bother to really allow this.
255 *
256 * Note that this is two nested paging root pages max. This isn't a leak. They are reused.
257 */
258 /* pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)); */
259
260 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
261 pVCpu->pgm.s.pShwPageCR3R3 = 0;
262 pVCpu->pgm.s.pShwPageCR3R0 = 0;
263 pVCpu->pgm.s.pShwPageCR3RC = 0;
264
265 pgmUnlock(pVM);
266
267 Log(("Leave nested shadow paging mode\n"));
268 }
269#else
270 RT_NOREF_PV(pVCpu);
271#endif
272 return VINF_SUCCESS;
273}
274
275
276/**
277 * Gets effective page information (from the VMM page directory).
278 *
279 * @returns VBox status code.
280 * @param pVCpu The cross context virtual CPU structure.
281 * @param GCPtr Guest Context virtual address of the page.
282 * @param pfFlags Where to store the flags. These are X86_PTE_*.
283 * @param pHCPhys Where to store the HC physical address of the page.
284 * This is page aligned.
285 * @remark You should use PGMMapGetPage() for pages in a mapping.
286 */
287PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
288{
289#if PGM_SHW_TYPE == PGM_TYPE_NONE
290 RT_NOREF(pVCpu, GCPtr);
291 AssertFailed();
292 *pfFlags = 0;
293 *pHCPhys = NIL_RTHCPHYS;
294 return VERR_PGM_SHW_NONE_IPE;
295
296#else /* PGM_SHW_TYPE != PGM_TYPE_NONE */
297 PVM pVM = pVCpu->CTX_SUFF(pVM);
298
299 PGM_LOCK_ASSERT_OWNER(pVM);
300
301 /*
302 * Get the PDE.
303 */
304# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
305 X86PDEPAE Pde;
306
307 /* PML4 */
308 X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
309 if (!Pml4e.n.u1Present)
310 return VERR_PAGE_TABLE_NOT_PRESENT;
311
312 /* PDPT */
313 PX86PDPT pPDPT;
314 int rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
315 if (RT_FAILURE(rc))
316 return rc;
317 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
318 X86PDPE Pdpe = pPDPT->a[iPDPT];
319 if (!Pdpe.n.u1Present)
320 return VERR_PAGE_TABLE_NOT_PRESENT;
321
322 /* PD */
323 PX86PDPAE pPd;
324 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
325 if (RT_FAILURE(rc))
326 return rc;
327 const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
328 Pde = pPd->a[iPd];
329
330 /* Merge accessed, write, user and no-execute bits into the PDE. */
331 Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
332 Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
333 Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
334 Pde.n.u1NoExecute |= Pml4e.n.u1NoExecute | Pdpe.lm.u1NoExecute;
335
336# elif PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
337 X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
338
339# elif PGM_SHW_TYPE == PGM_TYPE_EPT
340 const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
341 PEPTPD pPDDst;
342 EPTPDE Pde;
343
344 int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
345 if (rc != VINF_SUCCESS) /** @todo this function isn't expected to return informational status codes. Check callers / fix. */
346 {
347 AssertRC(rc);
348 return rc;
349 }
350 Assert(pPDDst);
351 Pde = pPDDst->a[iPd];
352
353# elif PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
354 X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
355# else
356# error "Misconfigured PGM_SHW_TYPE or something..."
357# endif
358 if (!Pde.n.u1Present)
359 return VERR_PAGE_TABLE_NOT_PRESENT;
360
361 /* Deal with large pages. */
362 if (Pde.b.u1Size)
363 {
364 /*
365 * Store the results.
366 * RW and US flags depend on the entire page translation hierarchy - except for
367 * legacy PAE which has a simplified PDPE.
368 */
369 if (pfFlags)
370 {
371 *pfFlags = (Pde.u & ~SHW_PDE_PG_MASK);
372# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
373 if ( (Pde.u & X86_PTE_PAE_NX)
374# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
375 && CPUMIsGuestNXEnabled(pVCpu) /** @todo why do we have to check the guest state here? */
376# endif
377 )
378 *pfFlags |= X86_PTE_PAE_NX;
379# endif
380 }
381
382 if (pHCPhys)
383 *pHCPhys = (Pde.u & SHW_PDE_PG_MASK) + (GCPtr & (RT_BIT(SHW_PD_SHIFT) - 1) & X86_PAGE_4K_BASE_MASK);
384
385 return VINF_SUCCESS;
386 }
387
388 /*
389 * Get PT entry.
390 */
391 PSHWPT pPT;
392 if (!(Pde.u & PGM_PDFLAGS_MAPPING))
393 {
394 int rc2 = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
395 if (RT_FAILURE(rc2))
396 return rc2;
397 }
398 else /* mapping: */
399 {
400# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \
401 || PGM_SHW_TYPE == PGM_TYPE_EPT \
402 || defined(PGM_WITHOUT_MAPPINGS)
403 AssertFailed(); /* can't happen */
404 pPT = NULL; /* shut up MSC */
405# else
406 Assert(pgmMapAreMappingsEnabled(pVM));
407
408 PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
409 AssertMsgReturn(pMap, ("GCPtr=%RGv\n", GCPtr), VERR_PGM_MAPPING_IPE);
410# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
411 pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
412# else /* PAE */
413 pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
414# endif
415# endif
416 }
417 const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
418 SHWPTE Pte = pPT->a[iPt];
419 if (!SHW_PTE_IS_P(Pte))
420 return VERR_PAGE_NOT_PRESENT;
421
422 /*
423 * Store the results.
424 * RW and US flags depend on the entire page translation hierarchy - except for
425 * legacy PAE which has a simplified PDPE.
426 */
427 if (pfFlags)
428 {
429 *pfFlags = (SHW_PTE_GET_U(Pte) & ~SHW_PTE_PG_MASK)
430 & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
431
432# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
433 /* The NX bit is determined by a bitwise OR between the PT and PD */
434 if ( ((SHW_PTE_GET_U(Pte) | Pde.u) & X86_PTE_PAE_NX)
435# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
436 && CPUMIsGuestNXEnabled(pVCpu) /** @todo why do we have to check the guest state here? */
437# endif
438 )
439 *pfFlags |= X86_PTE_PAE_NX;
440# endif
441 }
442
443 if (pHCPhys)
444 *pHCPhys = SHW_PTE_GET_HCPHYS(Pte);
445
446 return VINF_SUCCESS;
447#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
448}
449
450
451/**
452 * Modify page flags for a range of pages in the shadow context.
453 *
454 * The existing flags are ANDed with the fMask and ORed with the fFlags.
455 *
456 * @returns VBox status code.
457 * @param pVCpu The cross context virtual CPU structure.
458 * @param GCPtr Virtual address of the first page in the range. Page aligned!
459 * @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
460 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
461 * @param fMask The AND mask - page flags X86_PTE_*.
462 * Be extremely CAREFUL with ~'ing values because they can be 32-bit!
463 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
464 * @remark You must use PGMMapModifyPage() for pages in a mapping.
465 */
466PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
467{
468#if PGM_SHW_TYPE == PGM_TYPE_NONE
469 RT_NOREF(pVCpu, GCPtr, cb, fFlags, fMask, fOpFlags);
470 AssertFailed();
471 return VERR_PGM_SHW_NONE_IPE;
472
473#else /* PGM_SHW_TYPE != PGM_TYPE_NONE */
474 PVM pVM = pVCpu->CTX_SUFF(pVM);
475 PGM_LOCK_ASSERT_OWNER(pVM);
476
477 /*
478 * Walk page tables and pages till we're done.
479 */
480 int rc;
481 for (;;)
482 {
483 /*
484 * Get the PDE.
485 */
486# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
487 X86PDEPAE Pde;
488 /* PML4 */
489 X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
490 if (!Pml4e.n.u1Present)
491 return VERR_PAGE_TABLE_NOT_PRESENT;
492
493 /* PDPT */
494 PX86PDPT pPDPT;
495 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
496 if (RT_FAILURE(rc))
497 return rc;
498 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
499 X86PDPE Pdpe = pPDPT->a[iPDPT];
500 if (!Pdpe.n.u1Present)
501 return VERR_PAGE_TABLE_NOT_PRESENT;
502
503 /* PD */
504 PX86PDPAE pPd;
505 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
506 if (RT_FAILURE(rc))
507 return rc;
508 const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
509 Pde = pPd->a[iPd];
510
511# elif PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
512 X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
513
514# elif PGM_SHW_TYPE == PGM_TYPE_EPT
515 const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
516 PEPTPD pPDDst;
517 EPTPDE Pde;
518
519 rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
520 if (rc != VINF_SUCCESS)
521 {
522 AssertRC(rc);
523 return rc;
524 }
525 Assert(pPDDst);
526 Pde = pPDDst->a[iPd];
527
528# else /* PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT */
529 X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
530# endif
531 if (!Pde.n.u1Present)
532 return VERR_PAGE_TABLE_NOT_PRESENT;
533
534 AssertFatal(!Pde.b.u1Size);
535
536 /*
537 * Map the page table.
538 */
539 PSHWPT pPT;
540 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
541 if (RT_FAILURE(rc))
542 return rc;
543
544 unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
545 while (iPTE < RT_ELEMENTS(pPT->a))
546 {
547 if (SHW_PTE_IS_P(pPT->a[iPTE]))
548 {
549 SHWPTE const OrgPte = pPT->a[iPTE];
550 SHWPTE NewPte;
551
552 SHW_PTE_SET(NewPte, (SHW_PTE_GET_U(OrgPte) & (fMask | SHW_PTE_PG_MASK)) | (fFlags & ~SHW_PTE_PG_MASK));
553 if (!SHW_PTE_IS_P(NewPte))
554 {
555 /** @todo Some CSAM code path might end up here and upset
556 * the page pool. */
557 AssertFailed();
558 }
559 else if ( SHW_PTE_IS_RW(NewPte)
560 && !SHW_PTE_IS_RW(OrgPte)
561 && !(fOpFlags & PGM_MK_PG_IS_MMIO2) )
562 {
563 /** @todo Optimize \#PF handling by caching data. We can
564 * then use this when PGM_MK_PG_IS_WRITE_FAULT is
565 * set instead of resolving the guest physical
566 * address yet again. */
567 RTGCPHYS GCPhys;
568 uint64_t fGstPte;
569 rc = PGMGstGetPage(pVCpu, GCPtr, &fGstPte, &GCPhys);
570 AssertRC(rc);
571 if (RT_SUCCESS(rc))
572 {
573 Assert((fGstPte & X86_PTE_RW) || !(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP /* allow netware hack */));
574 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
575 Assert(pPage);
576 if (pPage)
577 {
578 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
579 AssertRCReturn(rc, rc);
580 Log(("%s: pgmPhysPageMakeWritable on %RGv / %RGp %R[pgmpage]\n", __PRETTY_FUNCTION__, GCPtr, GCPhys, pPage));
581 }
582 }
583 }
584
585 SHW_PTE_ATOMIC_SET2(pPT->a[iPTE], NewPte);
586# if PGM_SHW_TYPE == PGM_TYPE_EPT
587 HMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
588# else
589 PGM_INVL_PG_ALL_VCPU(pVM, GCPtr);
590# endif
591 }
592
593 /* next page */
594 cb -= PAGE_SIZE;
595 if (!cb)
596 return VINF_SUCCESS;
597 GCPtr += PAGE_SIZE;
598 iPTE++;
599 }
600 }
601#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
602}
603
604
605#ifdef IN_RING3
606/**
607 * Relocate any GC pointers related to shadow mode paging.
608 *
609 * @returns VBox status code.
610 * @param pVCpu The cross context virtual CPU structure.
611 * @param offDelta The relocation offset.
612 */
613PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
614{
615# if PGM_SHW_TYPE != PGM_TYPE_NONE
616 pVCpu->pgm.s.pShwPageCR3RC += offDelta;
617# else
618 RT_NOREF(pVCpu, offDelta);
619# endif
620 return VINF_SUCCESS;
621}
622#endif
623
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