VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 50653

Last change on this file since 50653 was 45798, checked in by vboxsync, 11 years ago

Fixed up and enabled Netware WP0+RO+US hack.
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File size: 18.9 KB
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1/* $Id: PGMAllShw.h 45798 2013-04-29 03:40:54Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Shadow Paging Template - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Defined Constants And Macros *
20*******************************************************************************/
21#undef SHWPT
22#undef PSHWPT
23#undef SHWPTE
24#undef PSHWPTE
25#undef SHWPD
26#undef PSHWPD
27#undef SHWPDE
28#undef PSHWPDE
29#undef SHW_PDE_PG_MASK
30#undef SHW_PD_SHIFT
31#undef SHW_PD_MASK
32#undef SHW_PTE_PG_MASK
33#undef SHW_PTE_IS_P
34#undef SHW_PTE_IS_RW
35#undef SHW_PTE_IS_US
36#undef SHW_PTE_IS_A
37#undef SHW_PTE_IS_D
38#undef SHW_PTE_IS_P_RW
39#undef SHW_PTE_IS_TRACK_DIRTY
40#undef SHW_PTE_GET_HCPHYS
41#undef SHW_PTE_GET_U
42#undef SHW_PTE_LOG64
43#undef SHW_PTE_SET
44#undef SHW_PTE_ATOMIC_SET
45#undef SHW_PTE_ATOMIC_SET2
46#undef SHW_PTE_SET_RO
47#undef SHW_PTE_SET_RW
48#undef SHW_PT_SHIFT
49#undef SHW_PT_MASK
50#undef SHW_TOTAL_PD_ENTRIES
51#undef SHW_PDPT_SHIFT
52#undef SHW_PDPT_MASK
53#undef SHW_PDPE_PG_MASK
54
55#if PGM_SHW_TYPE == PGM_TYPE_32BIT
56# define SHWPT X86PT
57# define PSHWPT PX86PT
58# define SHWPTE X86PTE
59# define PSHWPTE PX86PTE
60# define SHWPD X86PD
61# define PSHWPD PX86PD
62# define SHWPDE X86PDE
63# define PSHWPDE PX86PDE
64# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
65# define SHW_PD_SHIFT X86_PD_SHIFT
66# define SHW_PD_MASK X86_PD_MASK
67# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
68# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
69# define SHW_PTE_IS_P(Pte) ( (Pte).n.u1Present )
70# define SHW_PTE_IS_RW(Pte) ( (Pte).n.u1Write )
71# define SHW_PTE_IS_US(Pte) ( (Pte).n.u1User )
72# define SHW_PTE_IS_A(Pte) ( (Pte).n.u1Accessed )
73# define SHW_PTE_IS_D(Pte) ( (Pte).n.u1Dirty )
74# define SHW_PTE_IS_P_RW(Pte) ( (Pte).n.u1Present && (Pte).n.u1Write )
75# define SHW_PTE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
76# define SHW_PTE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PG_MASK )
77# define SHW_PTE_LOG64(Pte) ( (uint64_t)(Pte).u )
78# define SHW_PTE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
79# define SHW_PTE_SET(Pte, uNew) do { (Pte).u = (uNew); } while (0)
80# define SHW_PTE_ATOMIC_SET(Pte, uNew) do { ASMAtomicWriteU32(&(Pte).u, (uNew)); } while (0)
81# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU32(&(Pte).u, (Pte2).u); } while (0)
82# define SHW_PTE_SET_RO(Pte) do { (Pte).n.u1Write = 0; } while (0)
83# define SHW_PTE_SET_RW(Pte) do { (Pte).n.u1Write = 1; } while (0)
84# define SHW_PT_SHIFT X86_PT_SHIFT
85# define SHW_PT_MASK X86_PT_MASK
86
87#elif PGM_SHW_TYPE == PGM_TYPE_EPT
88# define SHWPT EPTPT
89# define PSHWPT PEPTPT
90# define SHWPTE EPTPTE
91# define PSHWPTE PEPTPTE
92# define SHWPD EPTPD
93# define PSHWPD PEPTPD
94# define SHWPDE EPTPDE
95# define PSHWPDE PEPTPDE
96# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
97# define SHW_PD_SHIFT EPT_PD_SHIFT
98# define SHW_PD_MASK EPT_PD_MASK
99# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
100# define SHW_PTE_IS_P(Pte) ( (Pte).n.u1Present ) /* Approximation, works for us. */
101# define SHW_PTE_IS_RW(Pte) ( (Pte).n.u1Write )
102# define SHW_PTE_IS_US(Pte) ( true )
103# define SHW_PTE_IS_A(Pte) ( true )
104# define SHW_PTE_IS_D(Pte) ( true )
105# define SHW_PTE_IS_P_RW(Pte) ( (Pte).n.u1Present && (Pte).n.u1Write )
106# define SHW_PTE_IS_TRACK_DIRTY(Pte) ( false )
107# define SHW_PTE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PG_MASK )
108# define SHW_PTE_LOG64(Pte) ( (Pte).u )
109# define SHW_PTE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
110# define SHW_PTE_SET(Pte, uNew) do { (Pte).u = (uNew); } while (0)
111# define SHW_PTE_ATOMIC_SET(Pte, uNew) do { ASMAtomicWriteU64(&(Pte).u, (uNew)); } while (0)
112# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
113# define SHW_PTE_SET_RO(Pte) do { (Pte).n.u1Write = 0; } while (0)
114# define SHW_PTE_SET_RW(Pte) do { (Pte).n.u1Write = 1; } while (0)
115# define SHW_PT_SHIFT EPT_PT_SHIFT
116# define SHW_PT_MASK EPT_PT_MASK
117# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
118# define SHW_PDPT_MASK EPT_PDPT_MASK
119# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
120# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
121
122#else
123# define SHWPT PGMSHWPTPAE
124# define PSHWPT PPGMSHWPTPAE
125# define SHWPTE PGMSHWPTEPAE
126# define PSHWPTE PPGMSHWPTEPAE
127# define SHWPD X86PDPAE
128# define PSHWPD PX86PDPAE
129# define SHWPDE X86PDEPAE
130# define PSHWPDE PX86PDEPAE
131# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
132# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
133# define SHW_PD_MASK X86_PD_PAE_MASK
134# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
135# define SHW_PTE_IS_P(Pte) PGMSHWPTEPAE_IS_P(Pte)
136# define SHW_PTE_IS_RW(Pte) PGMSHWPTEPAE_IS_RW(Pte)
137# define SHW_PTE_IS_US(Pte) PGMSHWPTEPAE_IS_US(Pte)
138# define SHW_PTE_IS_A(Pte) PGMSHWPTEPAE_IS_A(Pte)
139# define SHW_PTE_IS_D(Pte) PGMSHWPTEPAE_IS_D(Pte)
140# define SHW_PTE_IS_P_RW(Pte) PGMSHWPTEPAE_IS_P_RW(Pte)
141# define SHW_PTE_IS_TRACK_DIRTY(Pte) PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte)
142# define SHW_PTE_GET_HCPHYS(Pte) PGMSHWPTEPAE_GET_HCPHYS(Pte)
143# define SHW_PTE_LOG64(Pte) PGMSHWPTEPAE_GET_LOG(Pte)
144# define SHW_PTE_GET_U(Pte) PGMSHWPTEPAE_GET_U(Pte) /**< Use with care. */
145# define SHW_PTE_SET(Pte, uNew) PGMSHWPTEPAE_SET(Pte, uNew)
146# define SHW_PTE_ATOMIC_SET(Pte, uNew) PGMSHWPTEPAE_ATOMIC_SET(Pte, uNew)
147# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2)
148# define SHW_PTE_SET_RO(Pte) PGMSHWPTEPAE_SET_RO(Pte)
149# define SHW_PTE_SET_RW(Pte) PGMSHWPTEPAE_SET_RW(Pte)
150# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
151# define SHW_PT_MASK X86_PT_PAE_MASK
152
153# if PGM_SHW_TYPE == PGM_TYPE_AMD64
154# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
155# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
156# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
157# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
158
159# else /* 32 bits PAE mode */
160# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
161# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
162# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
163# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
164
165# endif
166#endif
167
168
169
170/*******************************************************************************
171* Internal Functions *
172*******************************************************************************/
173RT_C_DECLS_BEGIN
174PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
175PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
176RT_C_DECLS_END
177
178
179
180/**
181 * Gets effective page information (from the VMM page directory).
182 *
183 * @returns VBox status.
184 * @param pVCpu Pointer to the VMCPU.
185 * @param GCPtr Guest Context virtual address of the page.
186 * @param pfFlags Where to store the flags. These are X86_PTE_*.
187 * @param pHCPhys Where to store the HC physical address of the page.
188 * This is page aligned.
189 * @remark You should use PGMMapGetPage() for pages in a mapping.
190 */
191PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
192{
193#if PGM_SHW_TYPE == PGM_TYPE_NESTED
194 NOREF(pVCpu); NOREF(GCPtr); NOREF(pfFlags); NOREF(pHCPhys);
195 return VERR_PAGE_TABLE_NOT_PRESENT;
196
197#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
198 PVM pVM = pVCpu->CTX_SUFF(pVM);
199
200 PGM_LOCK_ASSERT_OWNER(pVM);
201
202 /*
203 * Get the PDE.
204 */
205# if PGM_SHW_TYPE == PGM_TYPE_AMD64
206 X86PDEPAE Pde;
207
208 /* PML4 */
209 X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
210 if (!Pml4e.n.u1Present)
211 return VERR_PAGE_TABLE_NOT_PRESENT;
212
213 /* PDPT */
214 PX86PDPT pPDPT;
215 int rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
216 if (RT_FAILURE(rc))
217 return rc;
218 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
219 X86PDPE Pdpe = pPDPT->a[iPDPT];
220 if (!Pdpe.n.u1Present)
221 return VERR_PAGE_TABLE_NOT_PRESENT;
222
223 /* PD */
224 PX86PDPAE pPd;
225 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
226 if (RT_FAILURE(rc))
227 return rc;
228 const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
229 Pde = pPd->a[iPd];
230
231 /* Merge accessed, write, user and no-execute bits into the PDE. */
232 Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
233 Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
234 Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
235 Pde.n.u1NoExecute |= Pml4e.n.u1NoExecute | Pdpe.lm.u1NoExecute;
236
237# elif PGM_SHW_TYPE == PGM_TYPE_PAE
238 X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
239
240# elif PGM_SHW_TYPE == PGM_TYPE_EPT
241 const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
242 PEPTPD pPDDst;
243 EPTPDE Pde;
244
245 int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
246 if (rc != VINF_SUCCESS) /** @todo this function isn't expected to return informational status codes. Check callers / fix. */
247 {
248 AssertRC(rc);
249 return rc;
250 }
251 Assert(pPDDst);
252 Pde = pPDDst->a[iPd];
253
254# else /* PGM_TYPE_32BIT */
255 X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
256# endif
257 if (!Pde.n.u1Present)
258 return VERR_PAGE_TABLE_NOT_PRESENT;
259
260 /** Deal with large pages. */
261 if (Pde.b.u1Size)
262 {
263 /*
264 * Store the results.
265 * RW and US flags depend on the entire page translation hierarchy - except for
266 * legacy PAE which has a simplified PDPE.
267 */
268 if (pfFlags)
269 {
270 *pfFlags = (Pde.u & ~SHW_PDE_PG_MASK);
271# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) /** @todo why do we have to check the guest state here? */
272 if ((Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu))
273 *pfFlags |= X86_PTE_PAE_NX;
274# endif
275 }
276
277 if (pHCPhys)
278 *pHCPhys = (Pde.u & SHW_PDE_PG_MASK) + (GCPtr & (RT_BIT(SHW_PD_SHIFT) - 1) & X86_PAGE_4K_BASE_MASK);
279
280 return VINF_SUCCESS;
281 }
282
283 /*
284 * Get PT entry.
285 */
286 PSHWPT pPT;
287 if (!(Pde.u & PGM_PDFLAGS_MAPPING))
288 {
289 int rc2 = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
290 if (RT_FAILURE(rc2))
291 return rc2;
292 }
293 else /* mapping: */
294 {
295# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \
296 || PGM_SHW_TYPE == PGM_TYPE_EPT \
297 || defined(PGM_WITHOUT_MAPPINGS)
298 AssertFailed(); /* can't happen */
299 pPT = NULL; /* shut up MSC */
300# else
301 Assert(pgmMapAreMappingsEnabled(pVM));
302
303 PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
304 AssertMsgReturn(pMap, ("GCPtr=%RGv\n", GCPtr), VERR_PGM_MAPPING_IPE);
305# if PGM_SHW_TYPE == PGM_TYPE_32BIT
306 pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
307# else /* PAE */
308 pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
309# endif
310# endif
311 }
312 const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
313 SHWPTE Pte = pPT->a[iPt];
314 if (!SHW_PTE_IS_P(Pte))
315 return VERR_PAGE_NOT_PRESENT;
316
317 /*
318 * Store the results.
319 * RW and US flags depend on the entire page translation hierarchy - except for
320 * legacy PAE which has a simplified PDPE.
321 */
322 if (pfFlags)
323 {
324 *pfFlags = (SHW_PTE_GET_U(Pte) & ~SHW_PTE_PG_MASK)
325 & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
326# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) /** @todo why do we have to check the guest state here? */
327 /* The NX bit is determined by a bitwise OR between the PT and PD */
328 if (((SHW_PTE_GET_U(Pte) | Pde.u) & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu))
329 *pfFlags |= X86_PTE_PAE_NX;
330# endif
331 }
332
333 if (pHCPhys)
334 *pHCPhys = SHW_PTE_GET_HCPHYS(Pte);
335
336 return VINF_SUCCESS;
337#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
338}
339
340
341/**
342 * Modify page flags for a range of pages in the shadow context.
343 *
344 * The existing flags are ANDed with the fMask and ORed with the fFlags.
345 *
346 * @returns VBox status code.
347 * @param pVCpu Pointer to the VMCPU.
348 * @param GCPtr Virtual address of the first page in the range. Page aligned!
349 * @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
350 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
351 * @param fMask The AND mask - page flags X86_PTE_*.
352 * Be extremely CAREFUL with ~'ing values because they can be 32-bit!
353 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
354 * @remark You must use PGMMapModifyPage() for pages in a mapping.
355 */
356PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
357{
358# if PGM_SHW_TYPE == PGM_TYPE_NESTED
359 NOREF(pVCpu); NOREF(GCPtr); NOREF(cb); NOREF(fFlags); NOREF(fMask); NOREF(fOpFlags);
360 return VERR_PAGE_TABLE_NOT_PRESENT;
361
362# else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
363 PVM pVM = pVCpu->CTX_SUFF(pVM);
364 int rc;
365
366 PGM_LOCK_ASSERT_OWNER(pVM);
367
368 /*
369 * Walk page tables and pages till we're done.
370 */
371 for (;;)
372 {
373 /*
374 * Get the PDE.
375 */
376# if PGM_SHW_TYPE == PGM_TYPE_AMD64
377 X86PDEPAE Pde;
378 /* PML4 */
379 X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
380 if (!Pml4e.n.u1Present)
381 return VERR_PAGE_TABLE_NOT_PRESENT;
382
383 /* PDPT */
384 PX86PDPT pPDPT;
385 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
386 if (RT_FAILURE(rc))
387 return rc;
388 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
389 X86PDPE Pdpe = pPDPT->a[iPDPT];
390 if (!Pdpe.n.u1Present)
391 return VERR_PAGE_TABLE_NOT_PRESENT;
392
393 /* PD */
394 PX86PDPAE pPd;
395 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
396 if (RT_FAILURE(rc))
397 return rc;
398 const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
399 Pde = pPd->a[iPd];
400
401# elif PGM_SHW_TYPE == PGM_TYPE_PAE
402 X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
403
404# elif PGM_SHW_TYPE == PGM_TYPE_EPT
405 const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
406 PEPTPD pPDDst;
407 EPTPDE Pde;
408
409 rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
410 if (rc != VINF_SUCCESS)
411 {
412 AssertRC(rc);
413 return rc;
414 }
415 Assert(pPDDst);
416 Pde = pPDDst->a[iPd];
417
418# else /* PGM_TYPE_32BIT */
419 X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
420# endif
421 if (!Pde.n.u1Present)
422 return VERR_PAGE_TABLE_NOT_PRESENT;
423
424 AssertFatal(!Pde.b.u1Size);
425
426 /*
427 * Map the page table.
428 */
429 PSHWPT pPT;
430 rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
431 if (RT_FAILURE(rc))
432 return rc;
433
434 unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
435 while (iPTE < RT_ELEMENTS(pPT->a))
436 {
437 if (SHW_PTE_IS_P(pPT->a[iPTE]))
438 {
439 SHWPTE const OrgPte = pPT->a[iPTE];
440 SHWPTE NewPte;
441
442 SHW_PTE_SET(NewPte, (SHW_PTE_GET_U(OrgPte) & (fMask | SHW_PTE_PG_MASK)) | (fFlags & ~SHW_PTE_PG_MASK));
443 if (!SHW_PTE_IS_P(NewPte))
444 {
445 /** @todo Some CSAM code path might end up here and upset
446 * the page pool. */
447 AssertFailed();
448 }
449 else if ( SHW_PTE_IS_RW(NewPte)
450 && !SHW_PTE_IS_RW(OrgPte)
451 && !(fOpFlags & PGM_MK_PG_IS_MMIO2) )
452 {
453 /** @todo Optimize \#PF handling by caching data. We can
454 * then use this when PGM_MK_PG_IS_WRITE_FAULT is
455 * set instead of resolving the guest physical
456 * address yet again. */
457 RTGCPHYS GCPhys;
458 uint64_t fGstPte;
459 rc = PGMGstGetPage(pVCpu, GCPtr, &fGstPte, &GCPhys);
460 AssertRC(rc);
461 if (RT_SUCCESS(rc))
462 {
463 Assert((fGstPte & X86_PTE_RW) || !(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP /* allow netware hack */));
464 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
465 Assert(pPage);
466 if (pPage)
467 {
468 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
469 AssertRCReturn(rc, rc);
470 Log(("%s: pgmPhysPageMakeWritable on %RGv / %RGp %R[pgmpage]\n", __PRETTY_FUNCTION__, GCPtr, GCPhys, pPage));
471 }
472 }
473 }
474
475 SHW_PTE_ATOMIC_SET2(pPT->a[iPTE], NewPte);
476# if PGM_SHW_TYPE == PGM_TYPE_EPT
477 HMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
478# else
479 PGM_INVL_PG_ALL_VCPU(pVM, GCPtr);
480# endif
481 }
482
483 /* next page */
484 cb -= PAGE_SIZE;
485 if (!cb)
486 return VINF_SUCCESS;
487 GCPtr += PAGE_SIZE;
488 iPTE++;
489 }
490 }
491# endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
492}
493
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