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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 50653

Last change on this file since 50653 was 49482, checked in by vboxsync, 11 years ago
VMM: Warnings.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 210.6 KB

Line
1	/* $Id: PGMAllPool.cpp 49482 2013-11-14 15:43:58Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_POOL
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/em.h>
26	#include <VBox/vmm/cpum.h>
27	#ifdef IN_RC
28	# include <VBox/vmm/patm.h>
29	#endif
30	#include "PGMInternal.h"
31	#include <VBox/vmm/vm.h>
32	#include "PGMInline.h"
33	#include <VBox/disopcode.h>
34	#include <VBox/vmm/hm_vmx.h>
35
36	#include <VBox/log.h>
37	#include <VBox/err.h>
38	#include <iprt/asm.h>
39	#include <iprt/asm-amd64-x86.h>
40	#include <iprt/string.h>
41
42
43	/*******************************************************************************
44	* Internal Functions *
45	*******************************************************************************/
46	RT_C_DECLS_BEGIN
47	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
48	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
49	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
50	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
51	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
52	#ifndef IN_RING3
53	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
54	#endif
55	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
56	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
57	#endif
58	#if 0 /defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)/
59	static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT);
60	#endif
61
62	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
63	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
64	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
65	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
66
67	RT_C_DECLS_END
68
69
70	/**
71	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
72	*
73	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
74	* @param enmKind The page kind.
75	*/
76	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
77	{
78	switch (enmKind)
79	{
80	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
81	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
82	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
83	return true;
84	default:
85	return false;
86	}
87	}
88
89
90	/**
91	* Flushes a chain of pages sharing the same access monitor.
92	*
93	* @returns VBox status code suitable for scheduling.
94	* @param pPool The pool.
95	* @param pPage A page in the chain.
96	* @todo VBOXSTRICTRC
97	*/
98	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
99	{
100	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
101
102	/*
103	* Find the list head.
104	*/
105	uint16_t idx = pPage->idx;
106	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
107	{
108	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
109	{
110	idx = pPage->iMonitoredPrev;
111	Assert(idx != pPage->idx);
112	pPage = &pPool->aPages[idx];
113	}
114	}
115
116	/*
117	* Iterate the list flushing each shadow page.
118	*/
119	int rc = VINF_SUCCESS;
120	for (;;)
121	{
122	idx = pPage->iMonitoredNext;
123	Assert(idx != pPage->idx);
124	if (pPage->idx >= PGMPOOL_IDX_FIRST)
125	{
126	int rc2 = pgmPoolFlushPage(pPool, pPage);
127	AssertRC(rc2);
128	}
129	/* next */
130	if (idx == NIL_PGMPOOL_IDX)
131	break;
132	pPage = &pPool->aPages[idx];
133	}
134	return rc;
135	}
136
137
138	/**
139	* Wrapper for getting the current context pointer to the entry being modified.
140	*
141	* @returns VBox status code suitable for scheduling.
142	* @param pVM Pointer to the VM.
143	* @param pvDst Destination address
144	* @param pvSrc Source guest virtual address.
145	* @param GCPhysSrc The source guest physical address.
146	* @param cb Size of data to read
147	*/
148	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc,
149	RTGCPHYS GCPhysSrc, size_t cb)
150	{
151	#if defined(IN_RING3)
152	NOREF(pVM); NOREF(GCPhysSrc);
153	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
154	return VINF_SUCCESS;
155	#else
156	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
157	NOREF(pvSrc);
158	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
159	#endif
160	}
161
162
163	/**
164	* Process shadow entries before they are changed by the guest.
165	*
166	* For PT entries we will clear them. For PD entries, we'll simply check
167	* for mapping conflicts and set the SyncCR3 FF if found.
168	*
169	* @param pVCpu Pointer to the VMCPU.
170	* @param pPool The pool.
171	* @param pPage The head page.
172	* @param GCPhysFault The guest physical fault address.
173	* @param uAddress In R0 and GC this is the guest context fault address (flat).
174	* In R3 this is the host context 'fault' address.
175	* @param cbWrite Write size; might be zero if the caller knows we're not crossing entry boundaries
176	*/
177	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault,
178	CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite)
179	{
180	AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%u (idx=%u)\n", pPage->iMonitoredPrev, pPage->idx));
181	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
182	PVM pVM = pPool->CTX_SUFF(pVM);
183	NOREF(pVCpu);
184
185	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)(CTXTYPE(RTGCPTR, uintptr_t, RTGCPTR))pvAddress, GCPhysFault, cbWrite));
186
187	for (;;)
188	{
189	union
190	{
191	void *pv;
192	PX86PT pPT;
193	PPGMSHWPTPAE pPTPae;
194	PX86PD pPD;
195	PX86PDPAE pPDPae;
196	PX86PDPT pPDPT;
197	PX86PML4 pPML4;
198	} uShw;
199
200	LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
201
202	uShw.pv = NULL;
203	switch (pPage->enmKind)
204	{
205	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
206	{
207	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
208	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
209	const unsigned iShw = off / sizeof(X86PTE);
210	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
211	if (uShw.pPT->a[iShw].n.u1Present)
212	{
213	X86PTE GstPte;
214
215	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
216	AssertRC(rc);
217	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
218	pgmPoolTracDerefGCPhysHint(pPool, pPage,
219	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
220	GstPte.u & X86_PTE_PG_MASK,
221	iShw);
222	ASMAtomicWriteU32(&uShw.pPT->a[iShw].u, 0);
223	}
224	break;
225	}
226
227	/* page/2 sized */
228	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
229	{
230	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
231	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
232	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
233	{
234	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
235	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
236	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
237	{
238	X86PTE GstPte;
239	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
240	AssertRC(rc);
241
242	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
243	pgmPoolTracDerefGCPhysHint(pPool, pPage,
244	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
245	GstPte.u & X86_PTE_PG_MASK,
246	iShw);
247	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
248	}
249	}
250	break;
251	}
252
253	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
254	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
255	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
256	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
257	{
258	unsigned iGst = off / sizeof(X86PDE);
259	unsigned iShwPdpt = iGst / 256;
260	unsigned iShw = (iGst % 256) * 2;
261	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
262
263	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
264	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
265	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
266	{
267	for (unsigned i = 0; i < 2; i++)
268	{
269	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
270	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
271	{
272	Assert(pgmMapAreMappingsEnabled(pVM));
273	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
274	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
275	break;
276	}
277	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
278	if (uShw.pPDPae->a[iShw+i].n.u1Present)
279	{
280	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
281	pgmPoolFree(pVM,
282	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
283	pPage->idx,
284	iShw + i);
285	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw+i].u, 0);
286	}
287
288	/* paranoia / a bit assumptive. */
289	if ( (off & 3)
290	&& (off & 3) + cbWrite > 4)
291	{
292	const unsigned iShw2 = iShw + 2 + i;
293	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
294	{
295	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
296	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
297	{
298	Assert(pgmMapAreMappingsEnabled(pVM));
299	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
300	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
301	break;
302	}
303	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
304	if (uShw.pPDPae->a[iShw2].n.u1Present)
305	{
306	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
307	pgmPoolFree(pVM,
308	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
309	pPage->idx,
310	iShw2);
311	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
312	}
313	}
314	}
315	}
316	}
317	break;
318	}
319
320	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
321	{
322	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
323	const unsigned iShw = off / sizeof(X86PTEPAE);
324	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
325	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
326	{
327	X86PTEPAE GstPte;
328	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
329	AssertRC(rc);
330
331	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK));
332	pgmPoolTracDerefGCPhysHint(pPool, pPage,
333	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
334	GstPte.u & X86_PTE_PAE_PG_MASK,
335	iShw);
336	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
337	}
338
339	/* paranoia / a bit assumptive. */
340	if ( (off & 7)
341	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
342	{
343	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
344	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
345
346	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw2]))
347	{
348	X86PTEPAE GstPte;
349	# ifdef IN_RING3
350	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
351	# else
352	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
353	# endif
354	AssertRC(rc);
355	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK));
356	pgmPoolTracDerefGCPhysHint(pPool, pPage,
357	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]),
358	GstPte.u & X86_PTE_PAE_PG_MASK,
359	iShw2);
360	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw2], 0);
361	}
362	}
363	break;
364	}
365
366	case PGMPOOLKIND_32BIT_PD:
367	{
368	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
369	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
370
371	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
372	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
373	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
374	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
375	{
376	Assert(pgmMapAreMappingsEnabled(pVM));
377	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
378	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
379	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
380	break;
381	}
382	else
383	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
384	{
385	if (uShw.pPD->a[iShw].n.u1Present)
386	{
387	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
388	pgmPoolFree(pVM,
389	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
390	pPage->idx,
391	iShw);
392	ASMAtomicWriteU32(&uShw.pPD->a[iShw].u, 0);
393	}
394	}
395	/* paranoia / a bit assumptive. */
396	if ( (off & 3)
397	&& (off & 3) + cbWrite > sizeof(X86PTE))
398	{
399	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
400	if ( iShw2 != iShw
401	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
402	{
403	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
404	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
405	{
406	Assert(pgmMapAreMappingsEnabled(pVM));
407	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
408	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
409	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
410	break;
411	}
412	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
413	if (uShw.pPD->a[iShw2].n.u1Present)
414	{
415	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
416	pgmPoolFree(pVM,
417	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
418	pPage->idx,
419	iShw2);
420	ASMAtomicWriteU32(&uShw.pPD->a[iShw2].u, 0);
421	}
422	}
423	}
424	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
425	if ( uShw.pPD->a[iShw].n.u1Present
426	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
427	{
428	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
429	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
430	ASMProbeReadByte(pvAddress);
431	# endif
432	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
433	ASMAtomicWriteU32(&uShw.pPD->a[iShw].u, 0);
434	}
435	#endif
436	break;
437	}
438
439	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
440	{
441	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
442	const unsigned iShw = off / sizeof(X86PDEPAE);
443	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
444	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
445	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
446	{
447	Assert(pgmMapAreMappingsEnabled(pVM));
448	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
449	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
450	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
451	break;
452	}
453	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
454	/*
455	* Causes trouble when the guest uses a PDE to refer to the whole page table level
456	* structure. (Invalidate here; faults later on when it tries to change the page
457	* table entries -> recheck; probably only applies to the RC case.)
458	*/
459	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
460	else
461	#endif
462	{
463	if (uShw.pPDPae->a[iShw].n.u1Present)
464	{
465	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
466	pgmPoolFree(pVM,
467	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
468	pPage->idx,
469	iShw);
470	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw].u, 0);
471	}
472	}
473	/* paranoia / a bit assumptive. */
474	if ( (off & 7)
475	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
476	{
477	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
478	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
479
480	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
481	if ( iShw2 != iShw
482	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
483	{
484	Assert(pgmMapAreMappingsEnabled(pVM));
485	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
486	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
487	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
488	break;
489	}
490	else
491	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
492	if (uShw.pPDPae->a[iShw2].n.u1Present)
493	{
494	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
495	pgmPoolFree(pVM,
496	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
497	pPage->idx,
498	iShw2);
499	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
500	}
501	}
502	break;
503	}
504
505	case PGMPOOLKIND_PAE_PDPT:
506	{
507	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
508	/*
509	* Hopefully this doesn't happen very often:
510	* - touching unused parts of the page
511	* - messing with the bits of pd pointers without changing the physical address
512	*/
513	/* PDPT roots are not page aligned; 32 byte only! */
514	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
515
516	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
517	const unsigned iShw = offPdpt / sizeof(X86PDPE);
518	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
519	{
520	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
521	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
522	{
523	Assert(pgmMapAreMappingsEnabled(pVM));
524	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
525	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
527	break;
528	}
529	else
530	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
531	if (uShw.pPDPT->a[iShw].n.u1Present)
532	{
533	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
534	pgmPoolFree(pVM,
535	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
536	pPage->idx,
537	iShw);
538	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw].u, 0);
539	}
540
541	/* paranoia / a bit assumptive. */
542	if ( (offPdpt & 7)
543	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
544	{
545	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
546	if ( iShw2 != iShw
547	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
548	{
549	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
550	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
551	{
552	Assert(pgmMapAreMappingsEnabled(pVM));
553	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
554	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
555	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
556	break;
557	}
558	else
559	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
560	if (uShw.pPDPT->a[iShw2].n.u1Present)
561	{
562	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
563	pgmPoolFree(pVM,
564	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
565	pPage->idx,
566	iShw2);
567	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw2].u, 0);
568	}
569	}
570	}
571	}
572	break;
573	}
574
575	#ifndef IN_RC
576	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
577	{
578	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
579	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
580	const unsigned iShw = off / sizeof(X86PDEPAE);
581	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
582	if (uShw.pPDPae->a[iShw].n.u1Present)
583	{
584	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
585	pgmPoolFree(pVM,
586	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
587	pPage->idx,
588	iShw);
589	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw].u, 0);
590	}
591	/* paranoia / a bit assumptive. */
592	if ( (off & 7)
593	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
594	{
595	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
596	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
597
598	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
599	if (uShw.pPDPae->a[iShw2].n.u1Present)
600	{
601	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
602	pgmPoolFree(pVM,
603	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
604	pPage->idx,
605	iShw2);
606	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
607	}
608	}
609	break;
610	}
611
612	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
613	{
614	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
615	/*
616	* Hopefully this doesn't happen very often:
617	* - messing with the bits of pd pointers without changing the physical address
618	*/
619	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
620	const unsigned iShw = off / sizeof(X86PDPE);
621	if (uShw.pPDPT->a[iShw].n.u1Present)
622	{
623	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
624	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
625	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw].u, 0);
626	}
627	/* paranoia / a bit assumptive. */
628	if ( (off & 7)
629	&& (off & 7) + cbWrite > sizeof(X86PDPE))
630	{
631	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
632	if (uShw.pPDPT->a[iShw2].n.u1Present)
633	{
634	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
635	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
636	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw2].u, 0);
637	}
638	}
639	break;
640	}
641
642	case PGMPOOLKIND_64BIT_PML4:
643	{
644	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
645	/*
646	* Hopefully this doesn't happen very often:
647	* - messing with the bits of pd pointers without changing the physical address
648	*/
649	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
650	const unsigned iShw = off / sizeof(X86PDPE);
651	if (uShw.pPML4->a[iShw].n.u1Present)
652	{
653	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
654	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
655	ASMAtomicWriteU64(&uShw.pPML4->a[iShw].u, 0);
656	}
657	/* paranoia / a bit assumptive. */
658	if ( (off & 7)
659	&& (off & 7) + cbWrite > sizeof(X86PDPE))
660	{
661	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
662	if (uShw.pPML4->a[iShw2].n.u1Present)
663	{
664	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
665	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
666	ASMAtomicWriteU64(&uShw.pPML4->a[iShw2].u, 0);
667	}
668	}
669	break;
670	}
671	#endif /* IN_RING0 */
672
673	default:
674	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
675	}
676	PGM_DYNMAP_UNUSED_HINT_VM(pVM, uShw.pv);
677
678	/* next */
679	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
680	return;
681	pPage = &pPool->aPages[pPage->iMonitoredNext];
682	}
683	}
684
685	# ifndef IN_RING3
686
687	/**
688	* Checks if a access could be a fork operation in progress.
689	*
690	* Meaning, that the guest is setting up the parent process for Copy-On-Write.
691	*
692	* @returns true if it's likely that we're forking, otherwise false.
693	* @param pPool The pool.
694	* @param pDis The disassembled instruction.
695	* @param offFault The access offset.
696	*/
697	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
698	{
699	/*
700	* i386 linux is using btr to clear X86_PTE_RW.
701	* The functions involved are (2.6.16 source inspection):
702	* clear_bit
703	* ptep_set_wrprotect
704	* copy_one_pte
705	* copy_pte_range
706	* copy_pmd_range
707	* copy_pud_range
708	* copy_page_range
709	* dup_mmap
710	* dup_mm
711	* copy_mm
712	* copy_process
713	* do_fork
714	*/
715	if ( pDis->pCurInstr->uOpcode == OP_BTR
716	&& !(offFault & 4)
717	/** @todo Validate that the bit index is X86_PTE_RW. */
718	)
719	{
720	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
721	return true;
722	}
723	return false;
724	}
725
726
727	/**
728	* Determine whether the page is likely to have been reused.
729	*
730	* @returns true if we consider the page as being reused for a different purpose.
731	* @returns false if we consider it to still be a paging page.
732	* @param pVM Pointer to the VM.
733	* @param pVCpu Pointer to the VMCPU.
734	* @param pRegFrame Trap register frame.
735	* @param pDis The disassembly info for the faulting instruction.
736	* @param pvFault The fault address.
737	*
738	* @remark The REP prefix check is left to the caller because of STOSD/W.
739	*/
740	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
741	{
742	#ifndef IN_RC
743	/** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
744	if ( HMHasPendingIrq(pVM)
745	&& (pRegFrame->rsp - pvFault) < 32)
746	{
747	/* Fault caused by stack writes while trying to inject an interrupt event. */
748	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
749	return true;
750	}
751	#else
752	NOREF(pVM); NOREF(pvFault);
753	#endif
754
755	LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->Param1.fUse, pDis->Param1.Base.idxGenReg));
756
757	/* Non-supervisor mode write means it's used for something else. */
758	if (CPUMGetGuestCPL(pVCpu) == 3)
759	return true;
760
761	switch (pDis->pCurInstr->uOpcode)
762	{
763	/* call implies the actual push of the return address faulted */
764	case OP_CALL:
765	Log4(("pgmPoolMonitorIsReused: CALL\n"));
766	return true;
767	case OP_PUSH:
768	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
769	return true;
770	case OP_PUSHF:
771	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
772	return true;
773	case OP_PUSHA:
774	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
775	return true;
776	case OP_FXSAVE:
777	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
778	return true;
779	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
780	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
781	return true;
782	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
783	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
784	return true;
785	case OP_MOVSWD:
786	case OP_STOSWD:
787	if ( pDis->fPrefix == (DISPREFIX_REP\|DISPREFIX_REX)
788	&& pRegFrame->rcx >= 0x40
789	)
790	{
791	Assert(pDis->uCpuMode == DISCPUMODE_64BIT);
792
793	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
794	return true;
795	}
796	return false;
797	}
798	if ( ( (pDis->Param1.fUse & DISUSE_REG_GEN32)
799	\|\| (pDis->Param1.fUse & DISUSE_REG_GEN64))
800	&& (pDis->Param1.Base.idxGenReg == DISGREG_ESP))
801	{
802	Log4(("pgmPoolMonitorIsReused: ESP\n"));
803	return true;
804	}
805
806	return false;
807	}
808
809
810	/**
811	* Flushes the page being accessed.
812	*
813	* @returns VBox status code suitable for scheduling.
814	* @param pVM Pointer to the VM.
815	* @param pVCpu Pointer to the VMCPU.
816	* @param pPool The pool.
817	* @param pPage The pool page (head).
818	* @param pDis The disassembly of the write instruction.
819	* @param pRegFrame The trap register frame.
820	* @param GCPhysFault The fault address as guest physical address.
821	* @param pvFault The fault address.
822	* @todo VBOXSTRICTRC
823	*/
824	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
825	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
826	{
827	NOREF(pVM); NOREF(GCPhysFault);
828
829	/*
830	* First, do the flushing.
831	*/
832	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
833
834	/*
835	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
836	* Must do this in raw mode (!); XP boot will fail otherwise.
837	*/
838	VBOXSTRICTRC rc2 = EMInterpretInstructionDisasState(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL);
839	if (rc2 == VINF_SUCCESS)
840	{ /* do nothing */ }
841	#ifdef VBOX_WITH_IEM
842	else if (rc2 == VINF_EM_RESCHEDULE)
843	{
844	if (rc == VINF_SUCCESS)
845	rc = VBOXSTRICTRC_VAL(rc2);
846	# ifndef IN_RING3
847	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
848	# endif
849	}
850	#endif
851	else if (rc2 == VERR_EM_INTERPRETER)
852	{
853	#ifdef IN_RC
854	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
855	{
856	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
857	pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->eip));
858	rc = VINF_SUCCESS;
859	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
860	}
861	else
862	#endif
863	{
864	rc = VINF_EM_RAW_EMULATE_INSTR;
865	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
866	}
867	}
868	else if (RT_FAILURE_NP(rc2))
869	rc = VBOXSTRICTRC_VAL(rc2);
870	else
871	AssertMsgFailed(("%Rrc\n", VBOXSTRICTRC_VAL(rc2))); /* ASSUMES no complicated stuff here. */
872
873	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
874	return rc;
875	}
876
877
878	/**
879	* Handles the STOSD write accesses.
880	*
881	* @returns VBox status code suitable for scheduling.
882	* @param pVM Pointer to the VM.
883	* @param pPool The pool.
884	* @param pPage The pool page (head).
885	* @param pDis The disassembly of the write instruction.
886	* @param pRegFrame The trap register frame.
887	* @param GCPhysFault The fault address as guest physical address.
888	* @param pvFault The fault address.
889	*/
890	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
891	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
892	{
893	unsigned uIncrement = pDis->Param1.cb;
894	NOREF(pVM);
895
896	Assert(pDis->uCpuMode == DISCPUMODE_32BIT \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
897	Assert(pRegFrame->rcx <= 0x20);
898
899	#ifdef VBOX_STRICT
900	if (pDis->uOpMode == DISCPUMODE_32BIT)
901	Assert(uIncrement == 4);
902	else
903	Assert(uIncrement == 8);
904	#endif
905
906	Log3(("pgmPoolAccessHandlerSTOSD\n"));
907
908	/*
909	* Increment the modification counter and insert it into the list
910	* of modified pages the first time.
911	*/
912	if (!pPage->cModifications++)
913	pgmPoolMonitorModifiedInsert(pPool, pPage);
914
915	/*
916	* Execute REP STOSD.
917	*
918	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
919	* write situation, meaning that it's safe to write here.
920	*/
921	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
922	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
923	while (pRegFrame->rcx)
924	{
925	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
926	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
927	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
928	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
929	#else
930	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
931	#endif
932	#ifdef IN_RC
933	(uint32_t )(uintptr_t)pu32 = pRegFrame->eax;
934	#else
935	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
936	#endif
937	pu32 += uIncrement;
938	GCPhysFault += uIncrement;
939	pRegFrame->rdi += uIncrement;
940	pRegFrame->rcx--;
941	}
942	pRegFrame->rip += pDis->cbInstr;
943
944	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
945	return VINF_SUCCESS;
946	}
947
948
949	/**
950	* Handles the simple write accesses.
951	*
952	* @returns VBox status code suitable for scheduling.
953	* @param pVM Pointer to the VM.
954	* @param pVCpu Pointer to the VMCPU.
955	* @param pPool The pool.
956	* @param pPage The pool page (head).
957	* @param pDis The disassembly of the write instruction.
958	* @param pRegFrame The trap register frame.
959	* @param GCPhysFault The fault address as guest physical address.
960	* @param pvFault The fault address.
961	* @param pfReused Reused state (in/out)
962	*/
963	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
964	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
965	{
966	Log3(("pgmPoolAccessHandlerSimple\n"));
967	NOREF(pVM);
968	NOREF(pfReused); /* initialized by caller */
969
970	/*
971	* Increment the modification counter and insert it into the list
972	* of modified pages the first time.
973	*/
974	if (!pPage->cModifications++)
975	pgmPoolMonitorModifiedInsert(pPool, pPage);
976
977	/*
978	* Clear all the pages. ASSUMES that pvFault is readable.
979	*/
980	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
981	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
982	#endif
983
984	uint32_t cbWrite = DISGetParamSize(pDis, &pDis->Param1);
985	if (cbWrite <= 8)
986	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, cbWrite);
987	else
988	{
989	Assert(cbWrite <= 16);
990	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, 8);
991	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault + 8, pvFault + 8, cbWrite - 8);
992	}
993
994	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
995	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
996	#endif
997
998	/*
999	* Interpret the instruction.
1000	*/
1001	VBOXSTRICTRC rc = EMInterpretInstructionDisasState(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL);
1002	if (RT_SUCCESS(rc))
1003	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc))); /* ASSUMES no complicated stuff here. */
1004	else if (rc == VERR_EM_INTERPRETER)
1005	{
1006	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1007	pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode));
1008	rc = VINF_EM_RAW_EMULATE_INSTR;
1009	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1010	}
1011
1012	#if 0 /* experimental code */
1013	if (rc == VINF_SUCCESS)
1014	{
1015	switch (pPage->enmKind)
1016	{
1017	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1018	{
1019	X86PTEPAE GstPte;
1020	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
1021	AssertRC(rc);
1022
1023	/* Check the new value written by the guest. If present and with a bogus physical address, then
1024	* it's fairly safe to assume the guest is reusing the PT.
1025	*/
1026	if (GstPte.n.u1Present)
1027	{
1028	RTHCPHYS HCPhys = -1;
1029	int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1030	if (rc != VINF_SUCCESS)
1031	{
1032	*pfReused = true;
1033	STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1034	}
1035	}
1036	break;
1037	}
1038	}
1039	}
1040	#endif
1041
1042	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1043	return VBOXSTRICTRC_VAL(rc);
1044	}
1045
1046
1047	/**
1048	* \#PF Handler callback for PT write accesses.
1049	*
1050	* @returns VBox status code (appropriate for GC return).
1051	* @param pVM Pointer to the VM.
1052	* @param uErrorCode CPU Error code.
1053	* @param pRegFrame Trap register frame.
1054	* NULL on DMA and other non CPU access.
1055	* @param pvFault The fault address (cr2).
1056	* @param GCPhysFault The GC physical address corresponding to pvFault.
1057	* @param pvUser User argument.
1058	*/
1059	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1060	RTGCPHYS GCPhysFault, void *pvUser)
1061	{
1062	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1063	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1064	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1065	PVMCPU pVCpu = VMMGetCpu(pVM);
1066	unsigned cMaxModifications;
1067	bool fForcedFlush = false;
1068	NOREF(uErrorCode);
1069
1070	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1071
1072	pgmLock(pVM);
1073	if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1074	{
1075	/* Pool page changed while we were waiting for the lock; ignore. */
1076	Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1077	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1078	pgmUnlock(pVM);
1079	return VINF_SUCCESS;
1080	}
1081	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1082	if (pPage->fDirty)
1083	{
1084	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH));
1085	pgmUnlock(pVM);
1086	return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
1087	}
1088	#endif
1089
1090	#if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
1091	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1092	{
1093	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1094	void *pvGst;
1095	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1096	pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
1097	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1098	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1099	}
1100	#endif
1101
1102	/*
1103	* Disassemble the faulting instruction.
1104	*/
1105	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1106	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
1107	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1108	{
1109	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("Unexpected rc %d\n", rc));
1110	pgmUnlock(pVM);
1111	return rc;
1112	}
1113
1114	Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1115
1116	/*
1117	* We should ALWAYS have the list head as user parameter. This
1118	* is because we use that page to record the changes.
1119	*/
1120	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1121
1122	#ifdef IN_RING0
1123	/* Maximum nr of modifications depends on the page type. */
1124	if ( pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1125	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1126	cMaxModifications = 4;
1127	else
1128	cMaxModifications = 24;
1129	#else
1130	cMaxModifications = 48;
1131	#endif
1132
1133	/*
1134	* Incremental page table updates should weigh more than random ones.
1135	* (Only applies when started from offset 0)
1136	*/
1137	pVCpu->pgm.s.cPoolAccessHandler++;
1138	if ( pPage->GCPtrLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1139	&& pPage->GCPtrLastAccessHandlerRip < pRegFrame->rip + 0x40
1140	&& pvFault == (pPage->GCPtrLastAccessHandlerFault + pDis->Param1.cb)
1141	&& pVCpu->pgm.s.cPoolAccessHandler == pPage->cLastAccessHandler + 1)
1142	{
1143	Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1144	Assert(pPage->cModifications < 32000);
1145	pPage->cModifications = pPage->cModifications * 2;
1146	pPage->GCPtrLastAccessHandlerFault = pvFault;
1147	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1148	if (pPage->cModifications >= cMaxModifications)
1149	{
1150	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1151	fForcedFlush = true;
1152	}
1153	}
1154
1155	if (pPage->cModifications >= cMaxModifications)
1156	Log(("Mod overflow %RGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1157
1158	/*
1159	* Check if it's worth dealing with.
1160	*/
1161	bool fReused = false;
1162	bool fNotReusedNotForking = false;
1163	if ( ( pPage->cModifications < cMaxModifications /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1164	\|\| pgmPoolIsPageLocked(pPage)
1165	)
1166	&& !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1167	&& !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1168	{
1169	/*
1170	* Simple instructions, no REP prefix.
1171	*/
1172	if (!(pDis->fPrefix & (DISPREFIX_REP \| DISPREFIX_REPNE)))
1173	{
1174	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1175	if (fReused)
1176	goto flushPage;
1177
1178	/* A mov instruction to change the first page table entry will be remembered so we can detect
1179	* full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1180	*/
1181	if ( rc == VINF_SUCCESS
1182	&& !pPage->cLocked /* only applies to unlocked pages as we can't free locked ones (e.g. cr3 root). */
1183	&& pDis->pCurInstr->uOpcode == OP_MOV
1184	&& (pvFault & PAGE_OFFSET_MASK) == 0)
1185	{
1186	pPage->GCPtrLastAccessHandlerFault = pvFault;
1187	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1188	pPage->GCPtrLastAccessHandlerRip = pRegFrame->rip;
1189	/* Make sure we don't kick out a page too quickly. */
1190	if (pPage->cModifications > 8)
1191	pPage->cModifications = 2;
1192	}
1193	else if (pPage->GCPtrLastAccessHandlerFault == pvFault)
1194	{
1195	/* ignore the 2nd write to this page table entry. */
1196	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1197	}
1198	else
1199	{
1200	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
1201	pPage->GCPtrLastAccessHandlerRip = 0;
1202	}
1203
1204	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1205	pgmUnlock(pVM);
1206	return rc;
1207	}
1208
1209	/*
1210	* Windows is frequently doing small memset() operations (netio test 4k+).
1211	* We have to deal with these or we'll kill the cache and performance.
1212	*/
1213	if ( pDis->pCurInstr->uOpcode == OP_STOSWD
1214	&& !pRegFrame->eflags.Bits.u1DF
1215	&& pDis->uOpMode == pDis->uCpuMode
1216	&& pDis->uAddrMode == pDis->uCpuMode)
1217	{
1218	bool fValidStosd = false;
1219
1220	if ( pDis->uCpuMode == DISCPUMODE_32BIT
1221	&& pDis->fPrefix == DISPREFIX_REP
1222	&& pRegFrame->ecx <= 0x20
1223	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1224	&& !((uintptr_t)pvFault & 3)
1225	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1226	)
1227	{
1228	fValidStosd = true;
1229	pRegFrame->rcx &= 0xffffffff; /* paranoia */
1230	}
1231	else
1232	if ( pDis->uCpuMode == DISCPUMODE_64BIT
1233	&& pDis->fPrefix == (DISPREFIX_REP \| DISPREFIX_REX)
1234	&& pRegFrame->rcx <= 0x20
1235	&& pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1236	&& !((uintptr_t)pvFault & 7)
1237	&& (pRegFrame->rax == 0 \|\| pRegFrame->rax == 0x80) /* the two values observed. */
1238	)
1239	{
1240	fValidStosd = true;
1241	}
1242
1243	if (fValidStosd)
1244	{
1245	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1246	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1247	pgmUnlock(pVM);
1248	return rc;
1249	}
1250	}
1251
1252	/* REP prefix, don't bother. */
1253	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1254	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1255	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode, pDis->fPrefix));
1256	fNotReusedNotForking = true;
1257	}
1258
1259	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1260	/* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1261	* leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1262	*/
1263	if ( pPage->cModifications >= cMaxModifications
1264	&& !fForcedFlush
1265	&& (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT \|\| pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1266	&& ( fNotReusedNotForking
1267	\|\| ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1268	&& !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1269	)
1270	)
1271	{
1272	Assert(!pgmPoolIsPageLocked(pPage));
1273	Assert(pPage->fDirty == false);
1274
1275	/* Flush any monitored duplicates as we will disable write protection. */
1276	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1277	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1278	{
1279	PPGMPOOLPAGE pPageHead = pPage;
1280
1281	/* Find the monitor head. */
1282	while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1283	pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1284
1285	while (pPageHead)
1286	{
1287	unsigned idxNext = pPageHead->iMonitoredNext;
1288
1289	if (pPageHead != pPage)
1290	{
1291	STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1292	Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1293	int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1294	AssertRC(rc2);
1295	}
1296
1297	if (idxNext == NIL_PGMPOOL_IDX)
1298	break;
1299
1300	pPageHead = &pPool->aPages[idxNext];
1301	}
1302	}
1303
1304	/* The flushing above might fail for locked pages, so double check. */
1305	if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1306	&& pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1307	{
1308	pgmPoolAddDirtyPage(pVM, pPool, pPage);
1309
1310	/* Temporarily allow write access to the page table again. */
1311	rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK, pPage->GCPhys & PAGE_BASE_GC_MASK);
1312	if (rc == VINF_SUCCESS)
1313	{
1314	rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
1315	AssertMsg(rc == VINF_SUCCESS
1316	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1317	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1318	\|\| rc == VERR_PAGE_NOT_PRESENT,
1319	("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1320	# ifdef VBOX_STRICT
1321	pPage->GCPtrDirtyFault = pvFault;
1322	# endif
1323
1324	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1325	pgmUnlock(pVM);
1326	return rc;
1327	}
1328	}
1329	}
1330	#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1331
1332	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushModOverflow));
1333	flushPage:
1334	/*
1335	* Not worth it, so flush it.
1336	*
1337	* If we considered it to be reused, don't go back to ring-3
1338	* to emulate failed instructions since we usually cannot
1339	* interpret then. This may be a bit risky, in which case
1340	* the reuse detection must be fixed.
1341	*/
1342	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1343	if ( rc == VINF_EM_RAW_EMULATE_INSTR
1344	&& fReused)
1345	{
1346	/* Make sure that the current instruction still has shadow page backing, otherwise we'll end up in a loop. */
1347	if (PGMShwGetPage(pVCpu, pRegFrame->rip, NULL, NULL) == VINF_SUCCESS)
1348	rc = VINF_SUCCESS; /* safe to restart the instruction. */
1349	}
1350	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1351	pgmUnlock(pVM);
1352	return rc;
1353	}
1354
1355	# endif /* !IN_RING3 */
1356
1357	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1358
1359	# if defined(VBOX_STRICT) && !defined(IN_RING3)
1360
1361	/**
1362	* Check references to guest physical memory in a PAE / PAE page table.
1363	*
1364	* @param pPool The pool.
1365	* @param pPage The page.
1366	* @param pShwPT The shadow page table (mapping of the page).
1367	* @param pGstPT The guest page table.
1368	*/
1369	static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
1370	{
1371	unsigned cErrors = 0;
1372	int LastRc = -1; /* initialized to shut up gcc */
1373	unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1374	RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1375	PVM pVM = pPool->CTX_SUFF(pVM);
1376
1377	#ifdef VBOX_STRICT
1378	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1379	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1380	#endif
1381	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1382	{
1383	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1384	{
1385	RTHCPHYS HCPhys = NIL_RTHCPHYS;
1386	int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1387	if ( rc != VINF_SUCCESS
1388	\|\| PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
1389	{
1390	Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1391	LastPTE = i;
1392	LastRc = rc;
1393	LastHCPhys = HCPhys;
1394	cErrors++;
1395
1396	RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1397	rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1398	AssertRC(rc);
1399
1400	for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1401	{
1402	PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1403
1404	if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1405	{
1406	PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1407
1408	for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1409	{
1410	if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
1411	&& PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[j]) == HCPhysPT)
1412	{
1413	Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
1414	}
1415	}
1416
1417	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1418	}
1419	}
1420	}
1421	}
1422	}
1423	AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
1424	}
1425
1426
1427	/**
1428	* Check references to guest physical memory in a PAE / 32-bit page table.
1429	*
1430	* @param pPool The pool.
1431	* @param pPage The page.
1432	* @param pShwPT The shadow page table (mapping of the page).
1433	* @param pGstPT The guest page table.
1434	*/
1435	static void pgmPoolTrackCheckPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
1436	{
1437	unsigned cErrors = 0;
1438	int LastRc = -1; /* initialized to shut up gcc */
1439	unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1440	RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1441	PVM pVM = pPool->CTX_SUFF(pVM);
1442
1443	#ifdef VBOX_STRICT
1444	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1445	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1446	#endif
1447	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1448	{
1449	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1450	{
1451	RTHCPHYS HCPhys = NIL_RTHCPHYS;
1452	int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PG_MASK, &HCPhys);
1453	if ( rc != VINF_SUCCESS
1454	\|\| PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
1455	{
1456	Log(("rc=%d idx=%d guest %x shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1457	LastPTE = i;
1458	LastRc = rc;
1459	LastHCPhys = HCPhys;
1460	cErrors++;
1461
1462	RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1463	rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1464	AssertRC(rc);
1465
1466	for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1467	{
1468	PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1469
1470	if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1471	{
1472	PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1473
1474	for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1475	{
1476	if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
1477	&& PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[j]) == HCPhysPT)
1478	{
1479	Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
1480	}
1481	}
1482
1483	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1484	}
1485	}
1486	}
1487	}
1488	}
1489	AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %x shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
1490	}
1491
1492	# endif /* VBOX_STRICT && !IN_RING3 */
1493
1494	/**
1495	* Clear references to guest physical memory in a PAE / PAE page table.
1496	*
1497	* @returns nr of changed PTEs
1498	* @param pPool The pool.
1499	* @param pPage The page.
1500	* @param pShwPT The shadow page table (mapping of the page).
1501	* @param pGstPT The guest page table.
1502	* @param pOldGstPT The old cached guest page table.
1503	* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1504	* @param pfFlush Flush reused page table (out)
1505	*/
1506	DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT,
1507	PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1508	{
1509	unsigned cChanged = 0;
1510
1511	#ifdef VBOX_STRICT
1512	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1513	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1514	#endif
1515	*pfFlush = false;
1516
1517	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1518	{
1519	/* Check the new value written by the guest. If present and with a bogus physical address, then
1520	* it's fairly safe to assume the guest is reusing the PT.
1521	*/
1522	if ( fAllowRemoval
1523	&& pGstPT->a[i].n.u1Present)
1524	{
1525	if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1526	{
1527	*pfFlush = true;
1528	return ++cChanged;
1529	}
1530	}
1531	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1532	{
1533	/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1534	if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1535	{
1536	#ifdef VBOX_STRICT
1537	RTHCPHYS HCPhys = NIL_RTGCPHYS;
1538	int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1539	AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1540	#endif
1541	uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G \| X86_PTE_PAE_NX);
1542	bool fHostRW = !!(PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & X86_PTE_RW);
1543	uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G \| X86_PTE_PAE_NX);
1544	bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1545
1546	if ( uHostAttr == uGuestAttr
1547	&& fHostRW <= fGuestRW)
1548	continue;
1549	}
1550	cChanged++;
1551	/* Something was changed, so flush it. */
1552	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1553	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1554	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
1555	PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
1556	}
1557	}
1558	return cChanged;
1559	}
1560
1561
1562	/**
1563	* Clear references to guest physical memory in a PAE / PAE page table.
1564	*
1565	* @returns nr of changed PTEs
1566	* @param pPool The pool.
1567	* @param pPage The page.
1568	* @param pShwPT The shadow page table (mapping of the page).
1569	* @param pGstPT The guest page table.
1570	* @param pOldGstPT The old cached guest page table.
1571	* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1572	* @param pfFlush Flush reused page table (out)
1573	*/
1574	DECLINLINE(unsigned) pgmPoolTrackFlushPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT,
1575	PCX86PT pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1576	{
1577	unsigned cChanged = 0;
1578
1579	#ifdef VBOX_STRICT
1580	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1581	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1582	#endif
1583	*pfFlush = false;
1584
1585	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1586	{
1587	/* Check the new value written by the guest. If present and with a bogus physical address, then
1588	* it's fairly safe to assume the guest is reusing the PT.
1589	*/
1590	if ( fAllowRemoval
1591	&& pGstPT->a[i].n.u1Present)
1592	{
1593	if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PG_MASK))
1594	{
1595	*pfFlush = true;
1596	return ++cChanged;
1597	}
1598	}
1599	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1600	{
1601	/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1602	if ((pGstPT->a[i].u & X86_PTE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PG_MASK))
1603	{
1604	#ifdef VBOX_STRICT
1605	RTHCPHYS HCPhys = NIL_RTGCPHYS;
1606	int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PG_MASK, &HCPhys);
1607	AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %x old %x shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1608	#endif
1609	uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G);
1610	bool fHostRW = !!(PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & X86_PTE_RW);
1611	uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G);
1612	bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1613
1614	if ( uHostAttr == uGuestAttr
1615	&& fHostRW <= fGuestRW)
1616	continue;
1617	}
1618	cChanged++;
1619	/* Something was changed, so flush it. */
1620	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%x\n",
1621	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PG_MASK));
1622	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PG_MASK, i);
1623	PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
1624	}
1625	}
1626	return cChanged;
1627	}
1628
1629
1630	/**
1631	* Flush a dirty page
1632	*
1633	* @param pVM Pointer to the VM.
1634	* @param pPool The pool.
1635	* @param idxSlot Dirty array slot index
1636	* @param fAllowRemoval Allow a reused page table to be removed
1637	*/
1638	static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1639	{
1640	PPGMPOOLPAGE pPage;
1641	unsigned idxPage;
1642
1643	Assert(idxSlot < RT_ELEMENTS(pPool->aDirtyPages));
1644	if (pPool->aDirtyPages[idxSlot].uIdx == NIL_PGMPOOL_IDX)
1645	return;
1646
1647	idxPage = pPool->aDirtyPages[idxSlot].uIdx;
1648	AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1649	pPage = &pPool->aPages[idxPage];
1650	Assert(pPage->idx == idxPage);
1651	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1652
1653	AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1654	Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1655
1656	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
1657	PVMCPU pVCpu = VMMGetCpu(pVM);
1658	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
1659	#endif
1660
1661	/* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1662	int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK);
1663	Assert(rc == VINF_SUCCESS);
1664	pPage->fDirty = false;
1665
1666	#ifdef VBOX_STRICT
1667	uint64_t fFlags = 0;
1668	RTHCPHYS HCPhys;
1669	rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->GCPtrDirtyFault, &fFlags, &HCPhys);
1670	AssertMsg( ( rc == VINF_SUCCESS
1671	&& (!(fFlags & X86_PTE_RW) \|\| HCPhys != pPage->Core.Key))
1672	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1673	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1674	\|\| rc == VERR_PAGE_NOT_PRESENT,
1675	("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->GCPtrDirtyFault, rc, fFlags));
1676	#endif
1677
1678	/* Flush those PTEs that have changed. */
1679	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1680	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1681	void *pvGst;
1682	rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1683	bool fFlush;
1684	unsigned cChanges;
1685
1686	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1687	cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst,
1688	(PCX86PTPAE)&pPool->aDirtyPages[idxSlot].aPage[0], fAllowRemoval, &fFlush);
1689	else
1690	cChanges = pgmPoolTrackFlushPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst,
1691	(PCX86PT)&pPool->aDirtyPages[idxSlot].aPage[0], fAllowRemoval, &fFlush);
1692
1693	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1694	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1695	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1696	/* Note: we might want to consider keeping the dirty page active in case there were many changes. */
1697
1698	/* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1699	Assert(pPage->cModifications);
1700	if (cChanges < 4)
1701	pPage->cModifications = 1; /* must use > 0 here */
1702	else
1703	pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1704
1705	STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1706	if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages))
1707	pPool->idxFreeDirtyPage = idxSlot;
1708
1709	pPool->cDirtyPages--;
1710	pPool->aDirtyPages[idxSlot].uIdx = NIL_PGMPOOL_IDX;
1711	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1712	if (fFlush)
1713	{
1714	Assert(fAllowRemoval);
1715	Log(("Flush reused page table!\n"));
1716	pgmPoolFlushPage(pPool, pPage);
1717	STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1718	}
1719	else
1720	Log(("Removed dirty page %RGp cMods=%d cChanges=%d\n", pPage->GCPhys, pPage->cModifications, cChanges));
1721
1722	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
1723	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
1724	#endif
1725	}
1726
1727
1728	# ifndef IN_RING3
1729	/**
1730	* Add a new dirty page
1731	*
1732	* @param pVM Pointer to the VM.
1733	* @param pPool The pool.
1734	* @param pPage The page.
1735	*/
1736	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1737	{
1738	unsigned idxFree;
1739
1740	PGM_LOCK_ASSERT_OWNER(pVM);
1741	AssertCompile(RT_ELEMENTS(pPool->aDirtyPages) == 8 \|\| RT_ELEMENTS(pPool->aDirtyPages) == 16);
1742	Assert(!pPage->fDirty);
1743
1744	idxFree = pPool->idxFreeDirtyPage;
1745	Assert(idxFree < RT_ELEMENTS(pPool->aDirtyPages));
1746	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1747
1748	if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aDirtyPages))
1749	{
1750	STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1751	pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1752	}
1753	Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aDirtyPages));
1754	AssertMsg(pPool->aDirtyPages[idxFree].uIdx == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1755
1756	Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1757
1758	/*
1759	* Make a copy of the guest page table as we require valid GCPhys addresses
1760	* when removing references to physical pages.
1761	* (The HCPhys linear lookup is extremely expensive!)
1762	*/
1763	void *pvGst;
1764	int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1765	memcpy(&pPool->aDirtyPages[idxFree].aPage[0], pvGst, (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT) ? PAGE_SIZE : PAGE_SIZE/2);
1766	# ifdef VBOX_STRICT
1767	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1768	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1769	pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
1770	else
1771	pgmPoolTrackCheckPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst);
1772	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1773	# endif
1774	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1775
1776	STAM_COUNTER_INC(&pPool->StatDirtyPage);
1777	pPage->fDirty = true;
1778	pPage->idxDirtyEntry = (uint8_t)idxFree; Assert(pPage->idxDirtyEntry == idxFree);
1779	pPool->aDirtyPages[idxFree].uIdx = pPage->idx;
1780	pPool->cDirtyPages++;
1781
1782	pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aDirtyPages) - 1);
1783	if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aDirtyPages)
1784	&& pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1785	{
1786	unsigned i;
1787	for (i = 1; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1788	{
1789	idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aDirtyPages) - 1);
1790	if (pPool->aDirtyPages[idxFree].uIdx == NIL_PGMPOOL_IDX)
1791	{
1792	pPool->idxFreeDirtyPage = idxFree;
1793	break;
1794	}
1795	}
1796	Assert(i != RT_ELEMENTS(pPool->aDirtyPages));
1797	}
1798
1799	Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages) \|\| pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx == NIL_PGMPOOL_IDX);
1800	return;
1801	}
1802	# endif /* !IN_RING3 */
1803
1804
1805	/**
1806	* Check if the specified page is dirty (not write monitored)
1807	*
1808	* @return dirty or not
1809	* @param pVM Pointer to the VM.
1810	* @param GCPhys Guest physical address
1811	*/
1812	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1813	{
1814	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1815	PGM_LOCK_ASSERT_OWNER(pVM);
1816	if (!pPool->cDirtyPages)
1817	return false;
1818
1819	GCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
1820
1821	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1822	{
1823	if (pPool->aDirtyPages[i].uIdx != NIL_PGMPOOL_IDX)
1824	{
1825	PPGMPOOLPAGE pPage;
1826	unsigned idxPage = pPool->aDirtyPages[i].uIdx;
1827
1828	pPage = &pPool->aPages[idxPage];
1829	if (pPage->GCPhys == GCPhys)
1830	return true;
1831	}
1832	}
1833	return false;
1834	}
1835
1836
1837	/**
1838	* Reset all dirty pages by reinstating page monitoring.
1839	*
1840	* @param pVM Pointer to the VM.
1841	*/
1842	void pgmPoolResetDirtyPages(PVM pVM)
1843	{
1844	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1845	PGM_LOCK_ASSERT_OWNER(pVM);
1846	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1847
1848	if (!pPool->cDirtyPages)
1849	return;
1850
1851	Log(("pgmPoolResetDirtyPages\n"));
1852	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1853	pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1854
1855	pPool->idxFreeDirtyPage = 0;
1856	if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aDirtyPages)
1857	&& pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1858	{
1859	unsigned i;
1860	for (i = 1; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1861	{
1862	if (pPool->aDirtyPages[i].uIdx == NIL_PGMPOOL_IDX)
1863	{
1864	pPool->idxFreeDirtyPage = i;
1865	break;
1866	}
1867	}
1868	AssertMsg(i != RT_ELEMENTS(pPool->aDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1869	}
1870
1871	Assert(pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx == NIL_PGMPOOL_IDX \|\| pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages));
1872	return;
1873	}
1874
1875
1876	/**
1877	* Invalidate the PT entry for the specified page
1878	*
1879	* @param pVM Pointer to the VM.
1880	* @param GCPtrPage Guest page to invalidate
1881	*/
1882	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage)
1883	{
1884	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1885	PGM_LOCK_ASSERT_OWNER(pVM);
1886	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1887
1888	if (!pPool->cDirtyPages)
1889	return;
1890
1891	Log(("pgmPoolResetDirtyPage %RGv\n", GCPtrPage));
1892	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1893	{
1894	}
1895	}
1896
1897
1898	/**
1899	* Reset all dirty pages by reinstating page monitoring.
1900	*
1901	* @param pVM Pointer to the VM.
1902	* @param GCPhysPT Physical address of the page table
1903	*/
1904	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT)
1905	{
1906	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1907	PGM_LOCK_ASSERT_OWNER(pVM);
1908	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1909	unsigned idxDirtyPage = RT_ELEMENTS(pPool->aDirtyPages);
1910
1911	if (!pPool->cDirtyPages)
1912	return;
1913
1914	GCPhysPT = GCPhysPT & ~(RTGCPHYS)PAGE_OFFSET_MASK;
1915
1916	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1917	{
1918	if (pPool->aDirtyPages[i].uIdx != NIL_PGMPOOL_IDX)
1919	{
1920	unsigned idxPage = pPool->aDirtyPages[i].uIdx;
1921
1922	PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1923	if (pPage->GCPhys == GCPhysPT)
1924	{
1925	idxDirtyPage = i;
1926	break;
1927	}
1928	}
1929	}
1930
1931	if (idxDirtyPage != RT_ELEMENTS(pPool->aDirtyPages))
1932	{
1933	pgmPoolFlushDirtyPage(pVM, pPool, idxDirtyPage, true /* allow removal of reused page tables*/);
1934	if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aDirtyPages)
1935	&& pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1936	{
1937	unsigned i;
1938	for (i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1939	{
1940	if (pPool->aDirtyPages[i].uIdx == NIL_PGMPOOL_IDX)
1941	{
1942	pPool->idxFreeDirtyPage = i;
1943	break;
1944	}
1945	}
1946	AssertMsg(i != RT_ELEMENTS(pPool->aDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1947	}
1948	}
1949	}
1950
1951	# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1952
1953	/**
1954	* Inserts a page into the GCPhys hash table.
1955	*
1956	* @param pPool The pool.
1957	* @param pPage The page.
1958	*/
1959	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1960	{
1961	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1962	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1963	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1964	pPage->iNext = pPool->aiHash[iHash];
1965	pPool->aiHash[iHash] = pPage->idx;
1966	}
1967
1968
1969	/**
1970	* Removes a page from the GCPhys hash table.
1971	*
1972	* @param pPool The pool.
1973	* @param pPage The page.
1974	*/
1975	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1976	{
1977	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1978	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1979	if (pPool->aiHash[iHash] == pPage->idx)
1980	pPool->aiHash[iHash] = pPage->iNext;
1981	else
1982	{
1983	uint16_t iPrev = pPool->aiHash[iHash];
1984	for (;;)
1985	{
1986	const int16_t i = pPool->aPages[iPrev].iNext;
1987	if (i == pPage->idx)
1988	{
1989	pPool->aPages[iPrev].iNext = pPage->iNext;
1990	break;
1991	}
1992	if (i == NIL_PGMPOOL_IDX)
1993	{
1994	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%d\n", pPage->GCPhys, pPage->idx));
1995	break;
1996	}
1997	iPrev = i;
1998	}
1999	}
2000	pPage->iNext = NIL_PGMPOOL_IDX;
2001	}
2002
2003
2004	/**
2005	* Frees up one cache page.
2006	*
2007	* @returns VBox status code.
2008	* @retval VINF_SUCCESS on success.
2009	* @param pPool The pool.
2010	* @param iUser The user index.
2011	*/
2012	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
2013	{
2014	#ifndef IN_RC
2015	const PVM pVM = pPool->CTX_SUFF(pVM);
2016	#endif
2017	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
2018	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
2019
2020	/*
2021	* Select one page from the tail of the age list.
2022	*/
2023	PPGMPOOLPAGE pPage;
2024	for (unsigned iLoop = 0; ; iLoop++)
2025	{
2026	uint16_t iToFree = pPool->iAgeTail;
2027	if (iToFree == iUser && iUser != NIL_PGMPOOL_IDX)
2028	iToFree = pPool->aPages[iToFree].iAgePrev;
2029	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
2030	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
2031	{
2032	uint16_t i = pPool->aPages[iToFree].iAgePrev;
2033	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
2034	{
2035	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
2036	continue;
2037	iToFree = i;
2038	break;
2039	}
2040	}
2041	*/
2042	Assert(iToFree != iUser);
2043	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
2044	pPage = &pPool->aPages[iToFree];
2045
2046	/*
2047	* Reject any attempts at flushing the currently active shadow CR3 mapping.
2048	* Call pgmPoolCacheUsed to move the page to the head of the age list.
2049	*/
2050	if ( !pgmPoolIsPageLocked(pPage)
2051	&& pPage->idx >= PGMPOOL_IDX_FIRST /* paranoia (#6349) */)
2052	break;
2053	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
2054	pgmPoolCacheUsed(pPool, pPage);
2055	AssertLogRelReturn(iLoop < 8192, VERR_PGM_POOL_TOO_MANY_LOOPS);
2056	}
2057
2058	/*
2059	* Found a usable page, flush it and return.
2060	*/
2061	int rc = pgmPoolFlushPage(pPool, pPage);
2062	/* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
2063	/* todo: find out why this is necessary; pgmPoolFlushPage should trigger a flush if one is really needed. */
2064	if (rc == VINF_SUCCESS)
2065	PGM_INVL_ALL_VCPU_TLBS(pVM);
2066	return rc;
2067	}
2068
2069
2070	/**
2071	* Checks if a kind mismatch is really a page being reused
2072	* or if it's just normal remappings.
2073	*
2074	* @returns true if reused and the cached page (enmKind1) should be flushed
2075	* @returns false if not reused.
2076	* @param enmKind1 The kind of the cached page.
2077	* @param enmKind2 The kind of the requested page.
2078	*/
2079	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
2080	{
2081	switch (enmKind1)
2082	{
2083	/*
2084	* Never reuse them. There is no remapping in non-paging mode.
2085	*/
2086	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2087	case PGMPOOLKIND_32BIT_PD_PHYS:
2088	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2089	case PGMPOOLKIND_PAE_PD_PHYS:
2090	case PGMPOOLKIND_PAE_PDPT_PHYS:
2091	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2092	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2093	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2094	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2095	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2096	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
2097	return false;
2098
2099	/*
2100	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
2101	*/
2102	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2103	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2104	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2105	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2106	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2107	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2108	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2109	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2110	case PGMPOOLKIND_32BIT_PD:
2111	case PGMPOOLKIND_PAE_PDPT:
2112	switch (enmKind2)
2113	{
2114	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2115	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2116	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2117	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2118	case PGMPOOLKIND_64BIT_PML4:
2119	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2120	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2121	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2122	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2123	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2124	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2125	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2126	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2127	return true;
2128	default:
2129	return false;
2130	}
2131
2132	/*
2133	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
2134	*/
2135	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2136	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2137	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2138	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2139	case PGMPOOLKIND_64BIT_PML4:
2140	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2141	switch (enmKind2)
2142	{
2143	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2144	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2145	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2146	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2147	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2148	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2149	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2150	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2151	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2152	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2153	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2154	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2155	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2156	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2157	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2158	return true;
2159	default:
2160	return false;
2161	}
2162
2163	/*
2164	* These cannot be flushed, and it's common to reuse the PDs as PTs.
2165	*/
2166	case PGMPOOLKIND_ROOT_NESTED:
2167	return false;
2168
2169	default:
2170	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
2171	}
2172	}
2173
2174
2175	/**
2176	* Attempts to satisfy a pgmPoolAlloc request from the cache.
2177	*
2178	* @returns VBox status code.
2179	* @retval VINF_PGM_CACHED_PAGE on success.
2180	* @retval VERR_FILE_NOT_FOUND if not found.
2181	* @param pPool The pool.
2182	* @param GCPhys The GC physical address of the page we're gonna shadow.
2183	* @param enmKind The kind of mapping.
2184	* @param enmAccess Access type for the mapping (only relevant for big pages)
2185	* @param fA20Enabled Whether the CPU has the A20 gate enabled.
2186	* @param iUser The shadow page pool index of the user table. This is
2187	* NIL_PGMPOOL_IDX for root pages.
2188	* @param iUserTable The index into the user table (shadowed). Ignored if
2189	* root page
2190	* @param ppPage Where to store the pointer to the page.
2191	*/
2192	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
2193	uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
2194	{
2195	/*
2196	* Look up the GCPhys in the hash.
2197	*/
2198	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2199	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%d iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2200	if (i != NIL_PGMPOOL_IDX)
2201	{
2202	do
2203	{
2204	PPGMPOOLPAGE pPage = &pPool->aPages[i];
2205	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2206	if (pPage->GCPhys == GCPhys)
2207	{
2208	if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2209	&& (PGMPOOLACCESS)pPage->enmAccess == enmAccess
2210	&& pPage->fA20Enabled == fA20Enabled)
2211	{
2212	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2213	* doesn't flush it in case there are no more free use records.
2214	*/
2215	pgmPoolCacheUsed(pPool, pPage);
2216
2217	int rc = VINF_SUCCESS;
2218	if (iUser != NIL_PGMPOOL_IDX)
2219	rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2220	if (RT_SUCCESS(rc))
2221	{
2222	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2223	*ppPage = pPage;
2224	if (pPage->cModifications)
2225	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2226	STAM_COUNTER_INC(&pPool->StatCacheHits);
2227	return VINF_PGM_CACHED_PAGE;
2228	}
2229	return rc;
2230	}
2231
2232	if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2233	{
2234	/*
2235	* The kind is different. In some cases we should now flush the page
2236	* as it has been reused, but in most cases this is normal remapping
2237	* of PDs as PT or big pages using the GCPhys field in a slightly
2238	* different way than the other kinds.
2239	*/
2240	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2241	{
2242	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2243	pgmPoolFlushPage(pPool, pPage);
2244	break;
2245	}
2246	}
2247	}
2248
2249	/* next */
2250	i = pPage->iNext;
2251	} while (i != NIL_PGMPOOL_IDX);
2252	}
2253
2254	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2255	STAM_COUNTER_INC(&pPool->StatCacheMisses);
2256	return VERR_FILE_NOT_FOUND;
2257	}
2258
2259
2260	/**
2261	* Inserts a page into the cache.
2262	*
2263	* @param pPool The pool.
2264	* @param pPage The cached page.
2265	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2266	*/
2267	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2268	{
2269	/*
2270	* Insert into the GCPhys hash if the page is fit for that.
2271	*/
2272	Assert(!pPage->fCached);
2273	if (fCanBeCached)
2274	{
2275	pPage->fCached = true;
2276	pgmPoolHashInsert(pPool, pPage);
2277	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2278	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2279	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2280	}
2281	else
2282	{
2283	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2284	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2285	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2286	}
2287
2288	/*
2289	* Insert at the head of the age list.
2290	*/
2291	pPage->iAgePrev = NIL_PGMPOOL_IDX;
2292	pPage->iAgeNext = pPool->iAgeHead;
2293	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2294	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2295	else
2296	pPool->iAgeTail = pPage->idx;
2297	pPool->iAgeHead = pPage->idx;
2298	}
2299
2300
2301	/**
2302	* Flushes a cached page.
2303	*
2304	* @param pPool The pool.
2305	* @param pPage The cached page.
2306	*/
2307	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2308	{
2309	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2310
2311	/*
2312	* Remove the page from the hash.
2313	*/
2314	if (pPage->fCached)
2315	{
2316	pPage->fCached = false;
2317	pgmPoolHashRemove(pPool, pPage);
2318	}
2319	else
2320	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2321
2322	/*
2323	* Remove it from the age list.
2324	*/
2325	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2326	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2327	else
2328	pPool->iAgeTail = pPage->iAgePrev;
2329	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2330	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2331	else
2332	pPool->iAgeHead = pPage->iAgeNext;
2333	pPage->iAgeNext = NIL_PGMPOOL_IDX;
2334	pPage->iAgePrev = NIL_PGMPOOL_IDX;
2335	}
2336
2337
2338	/**
2339	* Looks for pages sharing the monitor.
2340	*
2341	* @returns Pointer to the head page.
2342	* @returns NULL if not found.
2343	* @param pPool The Pool
2344	* @param pNewPage The page which is going to be monitored.
2345	*/
2346	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2347	{
2348	/*
2349	* Look up the GCPhys in the hash.
2350	*/
2351	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
2352	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2353	if (i == NIL_PGMPOOL_IDX)
2354	return NULL;
2355	do
2356	{
2357	PPGMPOOLPAGE pPage = &pPool->aPages[i];
2358	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2359	&& pPage != pNewPage)
2360	{
2361	switch (pPage->enmKind)
2362	{
2363	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2364	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2365	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2366	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2367	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2368	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2369	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2370	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2371	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2372	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2373	case PGMPOOLKIND_64BIT_PML4:
2374	case PGMPOOLKIND_32BIT_PD:
2375	case PGMPOOLKIND_PAE_PDPT:
2376	{
2377	/* find the head */
2378	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2379	{
2380	Assert(pPage->iMonitoredPrev != pPage->idx);
2381	pPage = &pPool->aPages[pPage->iMonitoredPrev];
2382	}
2383	return pPage;
2384	}
2385
2386	/* ignore, no monitoring. */
2387	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2388	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2389	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2390	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2391	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2392	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2393	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2394	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2395	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2396	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2397	case PGMPOOLKIND_ROOT_NESTED:
2398	case PGMPOOLKIND_PAE_PD_PHYS:
2399	case PGMPOOLKIND_PAE_PDPT_PHYS:
2400	case PGMPOOLKIND_32BIT_PD_PHYS:
2401	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2402	break;
2403	default:
2404	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2405	}
2406	}
2407
2408	/* next */
2409	i = pPage->iNext;
2410	} while (i != NIL_PGMPOOL_IDX);
2411	return NULL;
2412	}
2413
2414
2415	/**
2416	* Enabled write monitoring of a guest page.
2417	*
2418	* @returns VBox status code.
2419	* @retval VINF_SUCCESS on success.
2420	* @param pPool The pool.
2421	* @param pPage The cached page.
2422	*/
2423	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2424	{
2425	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK));
2426
2427	/*
2428	* Filter out the relevant kinds.
2429	*/
2430	switch (pPage->enmKind)
2431	{
2432	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2433	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2434	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2435	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2436	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2437	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2438	case PGMPOOLKIND_64BIT_PML4:
2439	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2440	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2441	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2442	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2443	case PGMPOOLKIND_32BIT_PD:
2444	case PGMPOOLKIND_PAE_PDPT:
2445	break;
2446
2447	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2448	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2449	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2450	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2451	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2452	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2453	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2454	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2455	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2456	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2457	case PGMPOOLKIND_ROOT_NESTED:
2458	/* Nothing to monitor here. */
2459	return VINF_SUCCESS;
2460
2461	case PGMPOOLKIND_32BIT_PD_PHYS:
2462	case PGMPOOLKIND_PAE_PDPT_PHYS:
2463	case PGMPOOLKIND_PAE_PD_PHYS:
2464	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2465	/* Nothing to monitor here. */
2466	return VINF_SUCCESS;
2467	default:
2468	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2469	}
2470
2471	/*
2472	* Install handler.
2473	*/
2474	int rc;
2475	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2476	if (pPageHead)
2477	{
2478	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2479	Assert(pPageHead->iMonitoredPrev != pPage->idx);
2480
2481	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2482	if (pPageHead->fDirty)
2483	pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirtyEntry, false /* do not remove */);
2484	#endif
2485
2486	pPage->iMonitoredPrev = pPageHead->idx;
2487	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2488	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2489	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2490	pPageHead->iMonitoredNext = pPage->idx;
2491	rc = VINF_SUCCESS;
2492	}
2493	else
2494	{
2495	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2496	PVM pVM = pPool->CTX_SUFF(pVM);
2497	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
2498	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2499	GCPhysPage, GCPhysPage + PAGE_OFFSET_MASK,
2500	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
2501	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
2502	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
2503	pPool->pszAccessHandler);
2504	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2505	* the heap size should suffice. */
2506	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2507	PVMCPU pVCpu = VMMGetCpu(pVM);
2508	AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), ("fSyncFlags=%x syncff=%d\n", pVCpu->pgm.s.fSyncFlags, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
2509	}
2510	pPage->fMonitored = true;
2511	return rc;
2512	}
2513
2514
2515	/**
2516	* Disables write monitoring of a guest page.
2517	*
2518	* @returns VBox status code.
2519	* @retval VINF_SUCCESS on success.
2520	* @param pPool The pool.
2521	* @param pPage The cached page.
2522	*/
2523	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2524	{
2525	/*
2526	* Filter out the relevant kinds.
2527	*/
2528	switch (pPage->enmKind)
2529	{
2530	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2531	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2532	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2533	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2534	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2535	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2536	case PGMPOOLKIND_64BIT_PML4:
2537	case PGMPOOLKIND_32BIT_PD:
2538	case PGMPOOLKIND_PAE_PDPT:
2539	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2540	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2541	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2542	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2543	break;
2544
2545	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2546	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2547	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2548	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2549	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2550	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2551	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2552	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2553	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2554	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2555	case PGMPOOLKIND_ROOT_NESTED:
2556	case PGMPOOLKIND_PAE_PD_PHYS:
2557	case PGMPOOLKIND_PAE_PDPT_PHYS:
2558	case PGMPOOLKIND_32BIT_PD_PHYS:
2559	/* Nothing to monitor here. */
2560	Assert(!pPage->fMonitored);
2561	return VINF_SUCCESS;
2562
2563	default:
2564	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2565	}
2566	Assert(pPage->fMonitored);
2567
2568	/*
2569	* Remove the page from the monitored list or uninstall it if last.
2570	*/
2571	const PVM pVM = pPool->CTX_SUFF(pVM);
2572	int rc;
2573	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2574	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2575	{
2576	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2577	{
2578	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2579	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2580	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK,
2581	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
2582	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
2583	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
2584	pPool->pszAccessHandler);
2585	AssertFatalRCSuccess(rc);
2586	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2587	}
2588	else
2589	{
2590	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2591	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2592	{
2593	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2594	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2595	}
2596	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2597	rc = VINF_SUCCESS;
2598	}
2599	}
2600	else
2601	{
2602	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
2603	AssertFatalRC(rc);
2604	PVMCPU pVCpu = VMMGetCpu(pVM);
2605	AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2606	("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2607	}
2608	pPage->fMonitored = false;
2609
2610	/*
2611	* Remove it from the list of modified pages (if in it).
2612	*/
2613	pgmPoolMonitorModifiedRemove(pPool, pPage);
2614
2615	return rc;
2616	}
2617
2618
2619	/**
2620	* Inserts the page into the list of modified pages.
2621	*
2622	* @param pPool The pool.
2623	* @param pPage The page.
2624	*/
2625	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2626	{
2627	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2628	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2629	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2630	&& pPool->iModifiedHead != pPage->idx,
2631	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2632	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2633	pPool->iModifiedHead, pPool->cModifiedPages));
2634
2635	pPage->iModifiedNext = pPool->iModifiedHead;
2636	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2637	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2638	pPool->iModifiedHead = pPage->idx;
2639	pPool->cModifiedPages++;
2640	#ifdef VBOX_WITH_STATISTICS
2641	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2642	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2643	#endif
2644	}
2645
2646
2647	/**
2648	* Removes the page from the list of modified pages and resets the
2649	* modification counter.
2650	*
2651	* @param pPool The pool.
2652	* @param pPage The page which is believed to be in the list of modified pages.
2653	*/
2654	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2655	{
2656	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2657	if (pPool->iModifiedHead == pPage->idx)
2658	{
2659	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2660	pPool->iModifiedHead = pPage->iModifiedNext;
2661	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2662	{
2663	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2664	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2665	}
2666	pPool->cModifiedPages--;
2667	}
2668	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2669	{
2670	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2671	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2672	{
2673	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2674	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2675	}
2676	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2677	pPool->cModifiedPages--;
2678	}
2679	else
2680	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2681	pPage->cModifications = 0;
2682	}
2683
2684
2685	/**
2686	* Zaps the list of modified pages, resetting their modification counters in the process.
2687	*
2688	* @param pVM Pointer to the VM.
2689	*/
2690	static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2691	{
2692	pgmLock(pVM);
2693	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2694	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2695
2696	unsigned cPages = 0; NOREF(cPages);
2697
2698	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2699	pgmPoolResetDirtyPages(pVM);
2700	#endif
2701
2702	uint16_t idx = pPool->iModifiedHead;
2703	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2704	while (idx != NIL_PGMPOOL_IDX)
2705	{
2706	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2707	idx = pPage->iModifiedNext;
2708	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2709	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2710	pPage->cModifications = 0;
2711	Assert(++cPages);
2712	}
2713	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2714	pPool->cModifiedPages = 0;
2715	pgmUnlock(pVM);
2716	}
2717
2718
2719	/**
2720	* Handle SyncCR3 pool tasks
2721	*
2722	* @returns VBox status code.
2723	* @retval VINF_SUCCESS if successfully added.
2724	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2725	* @param pVCpu Pointer to the VMCPU.
2726	* @remark Should only be used when monitoring is available, thus placed in
2727	* the PGMPOOL_WITH_MONITORING #ifdef.
2728	*/
2729	int pgmPoolSyncCR3(PVMCPU pVCpu)
2730	{
2731	PVM pVM = pVCpu->CTX_SUFF(pVM);
2732	LogFlow(("pgmPoolSyncCR3 fSyncFlags=%x\n", pVCpu->pgm.s.fSyncFlags));
2733
2734	/*
2735	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2736	* Occasionally we will have to clear all the shadow page tables because we wanted
2737	* to monitor a page which was mapped by too many shadowed page tables. This operation
2738	* sometimes referred to as a 'lightweight flush'.
2739	*/
2740	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2741	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2742	pgmR3PoolClearAll(pVM, false /fFlushRemTlb/);
2743	# else /* !IN_RING3 */
2744	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2745	{
2746	Log(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2747	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2748
2749	/* Make sure all other VCPUs return to ring 3. */
2750	if (pVM->cCpus > 1)
2751	{
2752	VM_FF_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING);
2753	PGM_INVL_ALL_VCPU_TLBS(pVM);
2754	}
2755	return VINF_PGM_SYNC_CR3;
2756	}
2757	# endif /* !IN_RING3 */
2758	else
2759	{
2760	pgmPoolMonitorModifiedClearAll(pVM);
2761
2762	/* pgmPoolMonitorModifiedClearAll can cause a pgm pool flush (dirty page clearing), so make sure we handle this! */
2763	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2764	{
2765	Log(("pgmPoolMonitorModifiedClearAll caused a pgm flush -> call pgmPoolSyncCR3 again!\n"));
2766	return pgmPoolSyncCR3(pVCpu);
2767	}
2768	}
2769	return VINF_SUCCESS;
2770	}
2771
2772
2773	/**
2774	* Frees up at least one user entry.
2775	*
2776	* @returns VBox status code.
2777	* @retval VINF_SUCCESS if successfully added.
2778	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2779	* @param pPool The pool.
2780	* @param iUser The user index.
2781	*/
2782	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2783	{
2784	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2785	/*
2786	* Just free cached pages in a braindead fashion.
2787	*/
2788	/** @todo walk the age list backwards and free the first with usage. */
2789	int rc = VINF_SUCCESS;
2790	do
2791	{
2792	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2793	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2794	rc = rc2;
2795	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2796	return rc;
2797	}
2798
2799
2800	/**
2801	* Inserts a page into the cache.
2802	*
2803	* This will create user node for the page, insert it into the GCPhys
2804	* hash, and insert it into the age list.
2805	*
2806	* @returns VBox status code.
2807	* @retval VINF_SUCCESS if successfully added.
2808	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2809	* @param pPool The pool.
2810	* @param pPage The cached page.
2811	* @param GCPhys The GC physical address of the page we're gonna shadow.
2812	* @param iUser The user index.
2813	* @param iUserTable The user table index.
2814	*/
2815	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2816	{
2817	int rc = VINF_SUCCESS;
2818	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2819
2820	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser=%d iUserTable=%x\n", GCPhys, iUser, iUserTable));
2821
2822	if (iUser != NIL_PGMPOOL_IDX)
2823	{
2824	#ifdef VBOX_STRICT
2825	/*
2826	* Check that the entry doesn't already exists.
2827	*/
2828	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2829	{
2830	uint16_t i = pPage->iUserHead;
2831	do
2832	{
2833	Assert(i < pPool->cMaxUsers);
2834	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2835	i = paUsers[i].iNext;
2836	} while (i != NIL_PGMPOOL_USER_INDEX);
2837	}
2838	#endif
2839
2840	/*
2841	* Find free a user node.
2842	*/
2843	uint16_t i = pPool->iUserFreeHead;
2844	if (i == NIL_PGMPOOL_USER_INDEX)
2845	{
2846	rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2847	if (RT_FAILURE(rc))
2848	return rc;
2849	i = pPool->iUserFreeHead;
2850	}
2851
2852	/*
2853	* Unlink the user node from the free list,
2854	* initialize and insert it into the user list.
2855	*/
2856	pPool->iUserFreeHead = paUsers[i].iNext;
2857	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2858	paUsers[i].iUser = iUser;
2859	paUsers[i].iUserTable = iUserTable;
2860	pPage->iUserHead = i;
2861	}
2862	else
2863	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
2864
2865
2866	/*
2867	* Insert into cache and enable monitoring of the guest page if enabled.
2868	*
2869	* Until we implement caching of all levels, including the CR3 one, we'll
2870	* have to make sure we don't try monitor & cache any recursive reuse of
2871	* a monitored CR3 page. Because all windows versions are doing this we'll
2872	* have to be able to do combined access monitoring, CR3 + PT and
2873	* PD + PT (guest PAE).
2874	*
2875	* Update:
2876	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2877	*/
2878	const bool fCanBeMonitored = true;
2879	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2880	if (fCanBeMonitored)
2881	{
2882	rc = pgmPoolMonitorInsert(pPool, pPage);
2883	AssertRC(rc);
2884	}
2885	return rc;
2886	}
2887
2888
2889	/**
2890	* Adds a user reference to a page.
2891	*
2892	* This will move the page to the head of the
2893	*
2894	* @returns VBox status code.
2895	* @retval VINF_SUCCESS if successfully added.
2896	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2897	* @param pPool The pool.
2898	* @param pPage The cached page.
2899	* @param iUser The user index.
2900	* @param iUserTable The user table.
2901	*/
2902	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2903	{
2904	Log3(("pgmPoolTrackAddUser: GCPhys=%RGp iUser=%%x iUserTable=%x\n", pPage->GCPhys, iUser, iUserTable));
2905	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2906	Assert(iUser != NIL_PGMPOOL_IDX);
2907
2908	# ifdef VBOX_STRICT
2909	/*
2910	* Check that the entry doesn't already exists. We only allow multiple
2911	* users of top-level paging structures (SHW_POOL_ROOT_IDX).
2912	*/
2913	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2914	{
2915	uint16_t i = pPage->iUserHead;
2916	do
2917	{
2918	Assert(i < pPool->cMaxUsers);
2919	/** @todo this assertion looks odd... Shouldn't it be && here? */
2920	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2921	i = paUsers[i].iNext;
2922	} while (i != NIL_PGMPOOL_USER_INDEX);
2923	}
2924	# endif
2925
2926	/*
2927	* Allocate a user node.
2928	*/
2929	uint16_t i = pPool->iUserFreeHead;
2930	if (i == NIL_PGMPOOL_USER_INDEX)
2931	{
2932	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2933	if (RT_FAILURE(rc))
2934	return rc;
2935	i = pPool->iUserFreeHead;
2936	}
2937	pPool->iUserFreeHead = paUsers[i].iNext;
2938
2939	/*
2940	* Initialize the user node and insert it.
2941	*/
2942	paUsers[i].iNext = pPage->iUserHead;
2943	paUsers[i].iUser = iUser;
2944	paUsers[i].iUserTable = iUserTable;
2945	pPage->iUserHead = i;
2946
2947	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2948	if (pPage->fDirty)
2949	pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirtyEntry, false /* do not remove */);
2950	# endif
2951
2952	/*
2953	* Tell the cache to update its replacement stats for this page.
2954	*/
2955	pgmPoolCacheUsed(pPool, pPage);
2956	return VINF_SUCCESS;
2957	}
2958
2959
2960	/**
2961	* Frees a user record associated with a page.
2962	*
2963	* This does not clear the entry in the user table, it simply replaces the
2964	* user record to the chain of free records.
2965	*
2966	* @param pPool The pool.
2967	* @param HCPhys The HC physical address of the shadow page.
2968	* @param iUser The shadow page pool index of the user table.
2969	* @param iUserTable The index into the user table (shadowed).
2970	*
2971	* @remarks Don't call this for root pages.
2972	*/
2973	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2974	{
2975	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2976	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2977	Assert(iUser != NIL_PGMPOOL_IDX);
2978
2979	/*
2980	* Unlink and free the specified user entry.
2981	*/
2982
2983	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2984	uint16_t i = pPage->iUserHead;
2985	if ( i != NIL_PGMPOOL_USER_INDEX
2986	&& paUsers[i].iUser == iUser
2987	&& paUsers[i].iUserTable == iUserTable)
2988	{
2989	pPage->iUserHead = paUsers[i].iNext;
2990
2991	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2992	paUsers[i].iNext = pPool->iUserFreeHead;
2993	pPool->iUserFreeHead = i;
2994	return;
2995	}
2996
2997	/* General: Linear search. */
2998	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2999	while (i != NIL_PGMPOOL_USER_INDEX)
3000	{
3001	if ( paUsers[i].iUser == iUser
3002	&& paUsers[i].iUserTable == iUserTable)
3003	{
3004	if (iPrev != NIL_PGMPOOL_USER_INDEX)
3005	paUsers[iPrev].iNext = paUsers[i].iNext;
3006	else
3007	pPage->iUserHead = paUsers[i].iNext;
3008
3009	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3010	paUsers[i].iNext = pPool->iUserFreeHead;
3011	pPool->iUserFreeHead = i;
3012	return;
3013	}
3014	iPrev = i;
3015	i = paUsers[i].iNext;
3016	}
3017
3018	/* Fatal: didn't find it */
3019	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%d iUserTable=%#x GCPhys=%RGp\n",
3020	iUser, iUserTable, pPage->GCPhys));
3021	}
3022
3023
3024	/**
3025	* Gets the entry size of a shadow table.
3026	*
3027	* @param enmKind The kind of page.
3028	*
3029	* @returns The size of the entry in bytes. That is, 4 or 8.
3030	* @returns If the kind is not for a table, an assertion is raised and 0 is
3031	* returned.
3032	*/
3033	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
3034	{
3035	switch (enmKind)
3036	{
3037	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3038	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3039	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3040	case PGMPOOLKIND_32BIT_PD:
3041	case PGMPOOLKIND_32BIT_PD_PHYS:
3042	return 4;
3043
3044	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3045	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3046	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3047	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3048	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3049	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3050	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3051	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3052	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3053	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3054	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3055	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3056	case PGMPOOLKIND_64BIT_PML4:
3057	case PGMPOOLKIND_PAE_PDPT:
3058	case PGMPOOLKIND_ROOT_NESTED:
3059	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3060	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3061	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3062	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3063	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3064	case PGMPOOLKIND_PAE_PD_PHYS:
3065	case PGMPOOLKIND_PAE_PDPT_PHYS:
3066	return 8;
3067
3068	default:
3069	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3070	}
3071	}
3072
3073
3074	/**
3075	* Gets the entry size of a guest table.
3076	*
3077	* @param enmKind The kind of page.
3078	*
3079	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
3080	* @returns If the kind is not for a table, an assertion is raised and 0 is
3081	* returned.
3082	*/
3083	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
3084	{
3085	switch (enmKind)
3086	{
3087	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3088	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3089	case PGMPOOLKIND_32BIT_PD:
3090	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3091	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3092	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3093	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3094	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3095	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3096	return 4;
3097
3098	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3099	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3100	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3101	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3102	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3103	case PGMPOOLKIND_64BIT_PML4:
3104	case PGMPOOLKIND_PAE_PDPT:
3105	return 8;
3106
3107	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3108	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3109	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3110	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3111	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3112	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3113	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3114	case PGMPOOLKIND_ROOT_NESTED:
3115	case PGMPOOLKIND_PAE_PD_PHYS:
3116	case PGMPOOLKIND_PAE_PDPT_PHYS:
3117	case PGMPOOLKIND_32BIT_PD_PHYS:
3118	/** @todo can we return 0? (nobody is calling this...) */
3119	AssertFailed();
3120	return 0;
3121
3122	default:
3123	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3124	}
3125	}
3126
3127
3128	/**
3129	* Checks one shadow page table entry for a mapping of a physical page.
3130	*
3131	* @returns true / false indicating removal of all relevant PTEs
3132	*
3133	* @param pVM Pointer to the VM.
3134	* @param pPhysPage The guest page in question.
3135	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3136	* @param iShw The shadow page table.
3137	* @param iPte Page table entry or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown
3138	*/
3139	static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t iPte)
3140	{
3141	LogFlow(("pgmPoolTrackFlushGCPhysPTInt: pPhysPage=%RHp iShw=%d iPte=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, iPte));
3142	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3143	bool fRet = false;
3144
3145	/*
3146	* Assert sanity.
3147	*/
3148	Assert(iPte != NIL_PGMPOOL_PHYSEXT_IDX_PTE);
3149	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
3150	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
3151
3152	/*
3153	* Then, clear the actual mappings to the page in the shadow PT.
3154	*/
3155	switch (pPage->enmKind)
3156	{
3157	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3158	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3159	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3160	{
3161	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
3162	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3163	uint32_t u32AndMask = 0;
3164	uint32_t u32OrMask = 0;
3165
3166	if (!fFlushPTEs)
3167	{
3168	switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3169	{
3170	case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3171	case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3172	u32OrMask = X86_PTE_RW;
3173	u32AndMask = UINT32_MAX;
3174	fRet = true;
3175	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3176	break;
3177
3178	case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3179	u32OrMask = 0;
3180	u32AndMask = ~X86_PTE_RW;
3181	fRet = true;
3182	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3183	break;
3184	default:
3185	/* (shouldn't be here, will assert below) */
3186	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3187	break;
3188	}
3189	}
3190	else
3191	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3192
3193	/* Update the counter if we're removing references. */
3194	if (!u32AndMask)
3195	{
3196	Assert(pPage->cPresent);
3197	Assert(pPool->cPresent);
3198	pPage->cPresent--;
3199	pPool->cPresent--;
3200	}
3201
3202	if ((pPT->a[iPte].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3203	{
3204	X86PTE Pte;
3205
3206	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32\n", iPte, pPT->a[iPte]));
3207	Pte.u = (pPT->a[iPte].u & u32AndMask) \| u32OrMask;
3208	if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3209	Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3210
3211	ASMAtomicWriteU32(&pPT->a[iPte].u, Pte.u);
3212	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3213	return fRet;
3214	}
3215	#ifdef LOG_ENABLED
3216	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3217	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
3218	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3219	{
3220	Log(("i=%d cFound=%d\n", i, ++cFound));
3221	}
3222	#endif
3223	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u32=%RX32 poolkind=%x\n", pPage->iFirstPresent, pPage->cPresent, u32, pPage->enmKind));
3224	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);/
3225	break;
3226	}
3227
3228	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3229	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3230	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3231	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3232	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3233	case PGMPOOLKIND_EPT_PT_FOR_PHYS: /* physical mask the same as PAE; RW bit as well; be careful! */
3234	{
3235	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
3236	PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3237	uint64_t u64OrMask = 0;
3238	uint64_t u64AndMask = 0;
3239
3240	if (!fFlushPTEs)
3241	{
3242	switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3243	{
3244	case PGM_PAGE_HNDL_PHYS_STATE_NONE: /* No handler installed. */
3245	case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /* Monitoring is temporarily disabled. */
3246	u64OrMask = X86_PTE_RW;
3247	u64AndMask = UINT64_MAX;
3248	fRet = true;
3249	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3250	break;
3251
3252	case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /* Write access is monitored. */
3253	u64OrMask = 0;
3254	u64AndMask = ~(uint64_t)X86_PTE_RW;
3255	fRet = true;
3256	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3257	break;
3258
3259	default:
3260	/* (shouldn't be here, will assert below) */
3261	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3262	break;
3263	}
3264	}
3265	else
3266	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3267
3268	/* Update the counter if we're removing references. */
3269	if (!u64AndMask)
3270	{
3271	Assert(pPage->cPresent);
3272	Assert(pPool->cPresent);
3273	pPage->cPresent--;
3274	pPool->cPresent--;
3275	}
3276
3277	if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3278	{
3279	X86PTEPAE Pte;
3280
3281	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64\n", iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
3282	Pte.u = (PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & u64AndMask) \| u64OrMask;
3283	if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3284	Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3285
3286	PGMSHWPTEPAE_ATOMIC_SET(pPT->a[iPte], Pte.u);
3287	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3288	return fRet;
3289	}
3290	#ifdef LOG_ENABLED
3291	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3292	Log(("Found %RX64 expected %RX64\n", PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX), u64));
3293	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
3294	if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3295	Log(("i=%d cFound=%d\n", i, ++cFound));
3296	#endif
3297	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x iPte=%d PT=%RX64\n", pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind, iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
3298	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);/
3299	break;
3300	}
3301
3302	#ifdef PGM_WITH_LARGE_PAGES
3303	/* Large page case only. */
3304	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3305	{
3306	Assert(pVM->pgm.s.fNestedPaging);
3307
3308	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PDE4M_P \| X86_PDE4M_PS;
3309	PEPTPD pPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3310
3311	if ((pPD->a[iPte].u & (EPT_PDE2M_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3312	{
3313	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64\n", iPte, pPD->a[iPte]));
3314	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3315	pPD->a[iPte].u = 0;
3316	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3317
3318	/* Update the counter as we're removing references. */
3319	Assert(pPage->cPresent);
3320	Assert(pPool->cPresent);
3321	pPage->cPresent--;
3322	pPool->cPresent--;
3323
3324	return fRet;
3325	}
3326	# ifdef LOG_ENABLED
3327	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3328	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPD->a); i++)
3329	if ((pPD->a[i].u & (EPT_PDE2M_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3330	Log(("i=%d cFound=%d\n", i, ++cFound));
3331	# endif
3332	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3333	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);/
3334	break;
3335	}
3336
3337	/* AMD-V nested paging / /* @todo merge with EPT as we only check the parts that are identical. */
3338	case PGMPOOLKIND_PAE_PD_PHYS:
3339	{
3340	Assert(pVM->pgm.s.fNestedPaging);
3341
3342	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PDE4M_P \| X86_PDE4M_PS;
3343	PX86PD pPD = (PX86PD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3344
3345	if ((pPD->a[iPte].u & (X86_PDE2M_PAE_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3346	{
3347	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64\n", iPte, pPD->a[iPte]));
3348	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3349	pPD->a[iPte].u = 0;
3350	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3351
3352	/* Update the counter as we're removing references. */
3353	Assert(pPage->cPresent);
3354	Assert(pPool->cPresent);
3355	pPage->cPresent--;
3356	pPool->cPresent--;
3357	return fRet;
3358	}
3359	# ifdef LOG_ENABLED
3360	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3361	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPD->a); i++)
3362	if ((pPD->a[i].u & (X86_PDE2M_PAE_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3363	Log(("i=%d cFound=%d\n", i, ++cFound));
3364	# endif
3365	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3366	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);/
3367	break;
3368	}
3369	#endif /* PGM_WITH_LARGE_PAGES */
3370
3371	default:
3372	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3373	}
3374
3375	/* not reached. */
3376	#ifndef _MSC_VER
3377	return fRet;
3378	#endif
3379	}
3380
3381
3382	/**
3383	* Scans one shadow page table for mappings of a physical page.
3384	*
3385	* @param pVM Pointer to the VM.
3386	* @param pPhysPage The guest page in question.
3387	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3388	* @param iShw The shadow page table.
3389	*/
3390	static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw)
3391	{
3392	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3393
3394	/* We should only come here with when there's only one reference to this physical page. */
3395	Assert(PGMPOOL_TD_GET_CREFS(PGM_PAGE_GET_TRACKING(pPhysPage)) == 1);
3396
3397	Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw));
3398	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3399	bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, PGM_PAGE_GET_PTE_INDEX(pPhysPage));
3400	if (!fKeptPTEs)
3401	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3402	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3403	}
3404
3405
3406	/**
3407	* Flushes a list of shadow page tables mapping the same physical page.
3408	*
3409	* @param pVM Pointer to the VM.
3410	* @param pPhysPage The guest page in question.
3411	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3412	* @param iPhysExt The physical cross reference extent list to flush.
3413	*/
3414	static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3415	{
3416	PGM_LOCK_ASSERT_OWNER(pVM);
3417	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3418	bool fKeepList = false;
3419
3420	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3421	Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3422
3423	const uint16_t iPhysExtStart = iPhysExt;
3424	PPGMPOOLPHYSEXT pPhysExt;
3425	do
3426	{
3427	Assert(iPhysExt < pPool->cMaxPhysExts);
3428	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3429	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3430	{
3431	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3432	{
3433	bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], pPhysExt->apte[i]);
3434	if (!fKeptPTEs)
3435	{
3436	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3437	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3438	}
3439	else
3440	fKeepList = true;
3441	}
3442	}
3443	/* next */
3444	iPhysExt = pPhysExt->iNext;
3445	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3446
3447	if (!fKeepList)
3448	{
3449	/* insert the list into the free list and clear the ram range entry. */
3450	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3451	pPool->iPhysExtFreeHead = iPhysExtStart;
3452	/* Invalidate the tracking data. */
3453	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3454	}
3455
3456	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3457	}
3458
3459
3460	/**
3461	* Flushes all shadow page table mappings of the given guest page.
3462	*
3463	* This is typically called when the host page backing the guest one has been
3464	* replaced or when the page protection was changed due to a guest access
3465	* caught by the monitoring.
3466	*
3467	* @returns VBox status code.
3468	* @retval VINF_SUCCESS if all references has been successfully cleared.
3469	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3470	* pool cleaning. FF and sync flags are set.
3471	*
3472	* @param pVM Pointer to the VM.
3473	* @param GCPhysPage GC physical address of the page in question
3474	* @param pPhysPage The guest page in question.
3475	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3476	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3477	* flushed, it is NOT touched if this isn't necessary.
3478	* The caller MUST initialized this to @a false.
3479	*/
3480	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3481	{
3482	PVMCPU pVCpu = VMMGetCpu(pVM);
3483	pgmLock(pVM);
3484	int rc = VINF_SUCCESS;
3485
3486	#ifdef PGM_WITH_LARGE_PAGES
3487	/* Is this page part of a large page? */
3488	if (PGM_PAGE_GET_PDE_TYPE(pPhysPage) == PGM_PAGE_PDE_TYPE_PDE)
3489	{
3490	RTGCPHYS GCPhysBase = GCPhysPage & X86_PDE2M_PAE_PG_MASK;
3491	GCPhysPage &= X86_PDE_PAE_PG_MASK;
3492
3493	/* Fetch the large page base. */
3494	PPGMPAGE pLargePage;
3495	if (GCPhysBase != GCPhysPage)
3496	{
3497	pLargePage = pgmPhysGetPage(pVM, GCPhysBase);
3498	AssertFatal(pLargePage);
3499	}
3500	else
3501	pLargePage = pPhysPage;
3502
3503	Log(("pgmPoolTrackUpdateGCPhys: update large page PDE for %RGp (%RGp)\n", GCPhysBase, GCPhysPage));
3504
3505	if (PGM_PAGE_GET_PDE_TYPE(pLargePage) == PGM_PAGE_PDE_TYPE_PDE)
3506	{
3507	/* Mark the large page as disabled as we need to break it up to change a single page in the 2 MB range. */
3508	PGM_PAGE_SET_PDE_TYPE(pVM, pLargePage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3509	pVM->pgm.s.cLargePagesDisabled++;
3510
3511	/* Update the base as that only that one has a reference and there's only one PDE to clear. */
3512	rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhysBase, pLargePage, fFlushPTEs, pfFlushTLBs);
3513
3514	*pfFlushTLBs = true;
3515	pgmUnlock(pVM);
3516	return rc;
3517	}
3518	}
3519	#else
3520	NOREF(GCPhysPage);
3521	#endif /* PGM_WITH_LARGE_PAGES */
3522
3523	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3524	if (u16)
3525	{
3526	/*
3527	* The zero page is currently screwing up the tracking and we'll
3528	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3529	* is defined, zero pages won't normally be mapped. Some kind of solution
3530	* will be needed for this problem of course, but it will have to wait...
3531	*/
3532	if ( PGM_PAGE_IS_ZERO(pPhysPage)
3533	\|\| PGM_PAGE_IS_BALLOONED(pPhysPage))
3534	rc = VINF_PGM_GCPHYS_ALIASED;
3535	else
3536	{
3537	# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC) /** @todo we can drop this now. */
3538	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3539	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3540	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
3541	# endif
3542
3543	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3544	{
3545	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3546	pgmPoolTrackFlushGCPhysPT(pVM,
3547	pPhysPage,
3548	fFlushPTEs,
3549	PGMPOOL_TD_GET_IDX(u16));
3550	}
3551	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3552	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3553	else
3554	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3555	*pfFlushTLBs = true;
3556
3557	# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
3558	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
3559	# endif
3560	}
3561	}
3562
3563	if (rc == VINF_PGM_GCPHYS_ALIASED)
3564	{
3565	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3566	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3567	rc = VINF_PGM_SYNC_CR3;
3568	}
3569	pgmUnlock(pVM);
3570	return rc;
3571	}
3572
3573
3574	/**
3575	* Scans all shadow page tables for mappings of a physical page.
3576	*
3577	* This may be slow, but it's most likely more efficient than cleaning
3578	* out the entire page pool / cache.
3579	*
3580	* @returns VBox status code.
3581	* @retval VINF_SUCCESS if all references has been successfully cleared.
3582	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3583	* a page pool cleaning.
3584	*
3585	* @param pVM Pointer to the VM.
3586	* @param pPhysPage The guest page in question.
3587	*/
3588	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3589	{
3590	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3591	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3592	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3593	pPool->cUsedPages, pPool->cPresent, pPhysPage));
3594
3595	/*
3596	* There is a limit to what makes sense.
3597	*/
3598	if ( pPool->cPresent > 1024
3599	&& pVM->cCpus == 1)
3600	{
3601	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3602	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3603	return VINF_PGM_GCPHYS_ALIASED;
3604	}
3605
3606	/*
3607	* Iterate all the pages until we've encountered all that in use.
3608	* This is simple but not quite optimal solution.
3609	*/
3610	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P; /** @todo drop X86_PTE_P here as we always test if present separately, anyway. */
3611	const uint32_t u32 = u64; /** @todo move into the 32BIT_PT_xx case */
3612	unsigned cLeft = pPool->cUsedPages;
3613	unsigned iPage = pPool->cCurPages;
3614	while (--iPage >= PGMPOOL_IDX_FIRST)
3615	{
3616	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3617	if ( pPage->GCPhys != NIL_RTGCPHYS
3618	&& pPage->cPresent)
3619	{
3620	switch (pPage->enmKind)
3621	{
3622	/*
3623	* We only care about shadow page tables.
3624	*/
3625	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3626	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3627	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3628	{
3629	unsigned cPresent = pPage->cPresent;
3630	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3631	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3632	if (pPT->a[i].n.u1Present)
3633	{
3634	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3635	{
3636	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3637	pPT->a[i].u = 0;
3638
3639	/* Update the counter as we're removing references. */
3640	Assert(pPage->cPresent);
3641	Assert(pPool->cPresent);
3642	pPage->cPresent--;
3643	pPool->cPresent--;
3644	}
3645	if (!--cPresent)
3646	break;
3647	}
3648	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3649	break;
3650	}
3651
3652	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3653	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3654	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3655	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3656	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3657	{
3658	unsigned cPresent = pPage->cPresent;
3659	PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3660	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3661	if (PGMSHWPTEPAE_IS_P(pPT->a[i]))
3662	{
3663	if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
3664	{
3665	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3666	PGMSHWPTEPAE_SET(pPT->a[i], 0); /// @todo why not atomic?
3667
3668	/* Update the counter as we're removing references. */
3669	Assert(pPage->cPresent);
3670	Assert(pPool->cPresent);
3671	pPage->cPresent--;
3672	pPool->cPresent--;
3673	}
3674	if (!--cPresent)
3675	break;
3676	}
3677	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3678	break;
3679	}
3680	#ifndef IN_RC
3681	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3682	{
3683	unsigned cPresent = pPage->cPresent;
3684	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3685	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3686	if (pPT->a[i].n.u1Present)
3687	{
3688	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
3689	{
3690	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3691	pPT->a[i].u = 0;
3692
3693	/* Update the counter as we're removing references. */
3694	Assert(pPage->cPresent);
3695	Assert(pPool->cPresent);
3696	pPage->cPresent--;
3697	pPool->cPresent--;
3698	}
3699	if (!--cPresent)
3700	break;
3701	}
3702	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3703	break;
3704	}
3705	#endif
3706	}
3707	if (!--cLeft)
3708	break;
3709	}
3710	}
3711
3712	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3713	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3714
3715	/*
3716	* There is a limit to what makes sense. The above search is very expensive, so force a pgm pool flush.
3717	*/
3718	if (pPool->cPresent > 1024)
3719	{
3720	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3721	return VINF_PGM_GCPHYS_ALIASED;
3722	}
3723
3724	return VINF_SUCCESS;
3725	}
3726
3727
3728	/**
3729	* Clears the user entry in a user table.
3730	*
3731	* This is used to remove all references to a page when flushing it.
3732	*/
3733	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3734	{
3735	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3736	Assert(pUser->iUser < pPool->cCurPages);
3737	uint32_t iUserTable = pUser->iUserTable;
3738
3739	/*
3740	* Map the user page. Ignore references made by fictitious pages.
3741	*/
3742	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3743	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3744	union
3745	{
3746	uint64_t *pau64;
3747	uint32_t *pau32;
3748	} u;
3749	if (pUserPage->idx < PGMPOOL_IDX_FIRST)
3750	{
3751	Assert(!pUserPage->pvPageR3);
3752	return;
3753	}
3754	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3755
3756
3757	/* Safety precaution in case we change the paging for other modes too in the future. */
3758	Assert(!pgmPoolIsPageLocked(pPage));
3759
3760	#ifdef VBOX_STRICT
3761	/*
3762	* Some sanity checks.
3763	*/
3764	switch (pUserPage->enmKind)
3765	{
3766	case PGMPOOLKIND_32BIT_PD:
3767	case PGMPOOLKIND_32BIT_PD_PHYS:
3768	Assert(iUserTable < X86_PG_ENTRIES);
3769	break;
3770	case PGMPOOLKIND_PAE_PDPT:
3771	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3772	case PGMPOOLKIND_PAE_PDPT_PHYS:
3773	Assert(iUserTable < 4);
3774	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3775	break;
3776	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3777	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3778	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3779	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3780	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3781	case PGMPOOLKIND_PAE_PD_PHYS:
3782	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3783	break;
3784	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3785	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3786	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3787	break;
3788	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3789	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3790	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3791	break;
3792	case PGMPOOLKIND_64BIT_PML4:
3793	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3794	/* GCPhys >> PAGE_SHIFT is the index here */
3795	break;
3796	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3797	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3798	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3799	break;
3800
3801	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3802	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3803	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3804	break;
3805
3806	case PGMPOOLKIND_ROOT_NESTED:
3807	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3808	break;
3809
3810	default:
3811	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3812	break;
3813	}
3814	#endif /* VBOX_STRICT */
3815
3816	/*
3817	* Clear the entry in the user page.
3818	*/
3819	switch (pUserPage->enmKind)
3820	{
3821	/* 32-bit entries */
3822	case PGMPOOLKIND_32BIT_PD:
3823	case PGMPOOLKIND_32BIT_PD_PHYS:
3824	ASMAtomicWriteU32(&u.pau32[iUserTable], 0);
3825	break;
3826
3827	/* 64-bit entries */
3828	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3829	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3830	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3831	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3832	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3833	#ifdef IN_RC
3834	/*
3835	* In 32 bits PAE mode we must invalidate the TLB when changing a
3836	* PDPT entry; the CPU fetches them only during cr3 load, so any
3837	* non-present PDPT will continue to cause page faults.
3838	*/
3839	ASMReloadCR3();
3840	/* no break */
3841	#endif
3842	case PGMPOOLKIND_PAE_PD_PHYS:
3843	case PGMPOOLKIND_PAE_PDPT_PHYS:
3844	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3845	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3846	case PGMPOOLKIND_64BIT_PML4:
3847	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3848	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3849	case PGMPOOLKIND_PAE_PDPT:
3850	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3851	case PGMPOOLKIND_ROOT_NESTED:
3852	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3853	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3854	ASMAtomicWriteU64(&u.pau64[iUserTable], 0);
3855	break;
3856
3857	default:
3858	AssertFatalMsgFailed(("enmKind=%d iUser=%d iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3859	}
3860	PGM_DYNMAP_UNUSED_HINT_VM(pPool->CTX_SUFF(pVM), u.pau64);
3861	}
3862
3863
3864	/**
3865	* Clears all users of a page.
3866	*/
3867	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3868	{
3869	/*
3870	* Free all the user records.
3871	*/
3872	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3873
3874	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3875	uint16_t i = pPage->iUserHead;
3876	while (i != NIL_PGMPOOL_USER_INDEX)
3877	{
3878	/* Clear enter in user table. */
3879	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3880
3881	/* Free it. */
3882	const uint16_t iNext = paUsers[i].iNext;
3883	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3884	paUsers[i].iNext = pPool->iUserFreeHead;
3885	pPool->iUserFreeHead = i;
3886
3887	/* Next. */
3888	i = iNext;
3889	}
3890	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3891	}
3892
3893
3894	/**
3895	* Allocates a new physical cross reference extent.
3896	*
3897	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3898	* @param pVM Pointer to the VM.
3899	* @param piPhysExt Where to store the phys ext index.
3900	*/
3901	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3902	{
3903	PGM_LOCK_ASSERT_OWNER(pVM);
3904	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3905	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3906	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3907	{
3908	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3909	return NULL;
3910	}
3911	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3912	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3913	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3914	*piPhysExt = iPhysExt;
3915	return pPhysExt;
3916	}
3917
3918
3919	/**
3920	* Frees a physical cross reference extent.
3921	*
3922	* @param pVM Pointer to the VM.
3923	* @param iPhysExt The extent to free.
3924	*/
3925	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3926	{
3927	PGM_LOCK_ASSERT_OWNER(pVM);
3928	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3929	Assert(iPhysExt < pPool->cMaxPhysExts);
3930	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3931	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3932	{
3933	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3934	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3935	}
3936	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3937	pPool->iPhysExtFreeHead = iPhysExt;
3938	}
3939
3940
3941	/**
3942	* Frees a physical cross reference extent.
3943	*
3944	* @param pVM Pointer to the VM.
3945	* @param iPhysExt The extent to free.
3946	*/
3947	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3948	{
3949	PGM_LOCK_ASSERT_OWNER(pVM);
3950	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3951
3952	const uint16_t iPhysExtStart = iPhysExt;
3953	PPGMPOOLPHYSEXT pPhysExt;
3954	do
3955	{
3956	Assert(iPhysExt < pPool->cMaxPhysExts);
3957	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3958	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3959	{
3960	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3961	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3962	}
3963
3964	/* next */
3965	iPhysExt = pPhysExt->iNext;
3966	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3967
3968	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3969	pPool->iPhysExtFreeHead = iPhysExtStart;
3970	}
3971
3972
3973	/**
3974	* Insert a reference into a list of physical cross reference extents.
3975	*
3976	* @returns The new tracking data for PGMPAGE.
3977	*
3978	* @param pVM Pointer to the VM.
3979	* @param iPhysExt The physical extent index of the list head.
3980	* @param iShwPT The shadow page table index.
3981	* @param iPte Page table entry
3982	*
3983	*/
3984	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT, uint16_t iPte)
3985	{
3986	PGM_LOCK_ASSERT_OWNER(pVM);
3987	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3988	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3989
3990	/*
3991	* Special common cases.
3992	*/
3993	if (paPhysExts[iPhysExt].aidx[1] == NIL_PGMPOOL_IDX)
3994	{
3995	paPhysExts[iPhysExt].aidx[1] = iShwPT;
3996	paPhysExts[iPhysExt].apte[1] = iPte;
3997	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
3998	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,%d pte %d,}\n", iPhysExt, iShwPT, iPte));
3999	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4000	}
4001	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
4002	{
4003	paPhysExts[iPhysExt].aidx[2] = iShwPT;
4004	paPhysExts[iPhysExt].apte[2] = iPte;
4005	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
4006	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d pte %d}\n", iPhysExt, iShwPT, iPte));
4007	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4008	}
4009	AssertCompile(RT_ELEMENTS(paPhysExts[iPhysExt].aidx) == 3);
4010
4011	/*
4012	* General treatment.
4013	*/
4014	const uint16_t iPhysExtStart = iPhysExt;
4015	unsigned cMax = 15;
4016	for (;;)
4017	{
4018	Assert(iPhysExt < pPool->cMaxPhysExts);
4019	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4020	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
4021	{
4022	paPhysExts[iPhysExt].aidx[i] = iShwPT;
4023	paPhysExts[iPhysExt].apte[i] = iPte;
4024	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
4025	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d pte %d} i=%d cMax=%d\n", iPhysExt, iShwPT, iPte, i, cMax));
4026	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
4027	}
4028	if (!--cMax)
4029	{
4030	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackOverflows);
4031	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
4032	LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
4033	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4034	}
4035
4036	/* advance */
4037	iPhysExt = paPhysExts[iPhysExt].iNext;
4038	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
4039	break;
4040	}
4041
4042	/*
4043	* Add another extent to the list.
4044	*/
4045	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
4046	if (!pNew)
4047	{
4048	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackNoExtentsLeft);
4049	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
4050	LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
4051	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4052	}
4053	pNew->iNext = iPhysExtStart;
4054	pNew->aidx[0] = iShwPT;
4055	pNew->apte[0] = iPte;
4056	LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d pte %d}->%d\n", iPhysExt, iShwPT, iPte, iPhysExtStart));
4057	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4058	}
4059
4060
4061	/**
4062	* Add a reference to guest physical page where extents are in use.
4063	*
4064	* @returns The new tracking data for PGMPAGE.
4065	*
4066	* @param pVM Pointer to the VM.
4067	* @param pPhysPage Pointer to the aPages entry in the ram range.
4068	* @param u16 The ram range flags (top 16-bits).
4069	* @param iShwPT The shadow page table index.
4070	* @param iPte Page table entry
4071	*/
4072	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte)
4073	{
4074	pgmLock(pVM);
4075	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
4076	{
4077	/*
4078	* Convert to extent list.
4079	*/
4080	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
4081	uint16_t iPhysExt;
4082	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
4083	if (pPhysExt)
4084	{
4085	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
4086	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliased);
4087	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
4088	pPhysExt->apte[0] = PGM_PAGE_GET_PTE_INDEX(pPhysPage);
4089	pPhysExt->aidx[1] = iShwPT;
4090	pPhysExt->apte[1] = iPte;
4091	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4092	}
4093	else
4094	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4095	}
4096	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
4097	{
4098	/*
4099	* Insert into the extent list.
4100	*/
4101	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT, iPte);
4102	}
4103	else
4104	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedLots);
4105	pgmUnlock(pVM);
4106	return u16;
4107	}
4108
4109
4110	/**
4111	* Clear references to guest physical memory.
4112	*
4113	* @param pPool The pool.
4114	* @param pPage The page.
4115	* @param pPhysPage Pointer to the aPages entry in the ram range.
4116	* @param iPte Shadow PTE index
4117	*/
4118	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage, uint16_t iPte)
4119	{
4120	PVM pVM = pPool->CTX_SUFF(pVM);
4121	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4122	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
4123
4124	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
4125	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
4126	{
4127	pgmLock(pVM);
4128
4129	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
4130	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4131	do
4132	{
4133	Assert(iPhysExt < pPool->cMaxPhysExts);
4134
4135	/*
4136	* Look for the shadow page and check if it's all freed.
4137	*/
4138	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4139	{
4140	if ( paPhysExts[iPhysExt].aidx[i] == pPage->idx
4141	&& paPhysExts[iPhysExt].apte[i] == iPte)
4142	{
4143	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
4144	paPhysExts[iPhysExt].apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
4145
4146	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4147	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
4148	{
4149	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
4150	pgmUnlock(pVM);
4151	return;
4152	}
4153
4154	/* we can free the node. */
4155	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
4156	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
4157	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
4158	{
4159	/* lonely node */
4160	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4161	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
4162	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
4163	}
4164	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
4165	{
4166	/* head */
4167	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
4168	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
4169	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4170	}
4171	else
4172	{
4173	/* in list */
4174	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d in list\n", pPhysPage, pPage->idx));
4175	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
4176	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4177	}
4178	iPhysExt = iPhysExtNext;
4179	pgmUnlock(pVM);
4180	return;
4181	}
4182	}
4183
4184	/* next */
4185	iPhysExtPrev = iPhysExt;
4186	iPhysExt = paPhysExts[iPhysExt].iNext;
4187	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
4188
4189	pgmUnlock(pVM);
4190	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
4191	}
4192	else /* nothing to do */
4193	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
4194	}
4195
4196	/**
4197	* Clear references to guest physical memory.
4198	*
4199	* This is the same as pgmPoolTracDerefGCPhysHint except that the guest
4200	* physical address is assumed to be correct, so the linear search can be
4201	* skipped and we can assert at an earlier point.
4202	*
4203	* @param pPool The pool.
4204	* @param pPage The page.
4205	* @param HCPhys The host physical address corresponding to the guest page.
4206	* @param GCPhys The guest physical address corresponding to HCPhys.
4207	* @param iPte Shadow PTE index
4208	*/
4209	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys, uint16_t iPte)
4210	{
4211	/*
4212	* Lookup the page and check if it checks out before derefing it.
4213	*/
4214	PVM pVM = pPool->CTX_SUFF(pVM);
4215	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhys);
4216	if (pPhysPage)
4217	{
4218	Assert(PGM_PAGE_GET_HCPHYS(pPhysPage));
4219	#ifdef LOG_ENABLED
4220	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(pPhysPage);
4221	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
4222	#endif
4223	if (PGM_PAGE_GET_HCPHYS(pPhysPage) == HCPhys)
4224	{
4225	Assert(pPage->cPresent);
4226	Assert(pPool->cPresent);
4227	pPage->cPresent--;
4228	pPool->cPresent--;
4229	pgmTrackDerefGCPhys(pPool, pPage, pPhysPage, iPte);
4230	return;
4231	}
4232
4233	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp; found page has HCPhys=%RHp\n",
4234	HCPhys, GCPhys, PGM_PAGE_GET_HCPHYS(pPhysPage)));
4235	}
4236	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
4237	}
4238
4239
4240	/**
4241	* Clear references to guest physical memory.
4242	*
4243	* @param pPool The pool.
4244	* @param pPage The page.
4245	* @param HCPhys The host physical address corresponding to the guest page.
4246	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
4247	* @param iPte Shadow pte index
4248	*/
4249	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte)
4250	{
4251	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
4252
4253	/*
4254	* Try the hint first.
4255	*/
4256	RTHCPHYS HCPhysHinted;
4257	PVM pVM = pPool->CTX_SUFF(pVM);
4258	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysHint);
4259	if (pPhysPage)
4260	{
4261	HCPhysHinted = PGM_PAGE_GET_HCPHYS(pPhysPage);
4262	Assert(HCPhysHinted);
4263	if (HCPhysHinted == HCPhys)
4264	{
4265	Assert(pPage->cPresent);
4266	Assert(pPool->cPresent);
4267	pPage->cPresent--;
4268	pPool->cPresent--;
4269	pgmTrackDerefGCPhys(pPool, pPage, pPhysPage, iPte);
4270	return;
4271	}
4272	}
4273	else
4274	HCPhysHinted = UINT64_C(0xdeadbeefdeadbeef);
4275
4276	/*
4277	* Damn, the hint didn't work. We'll have to do an expensive linear search.
4278	*/
4279	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
4280	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRangesX);
4281	while (pRam)
4282	{
4283	unsigned iPage = pRam->cb >> PAGE_SHIFT;
4284	while (iPage-- > 0)
4285	{
4286	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4287	{
4288	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
4289	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
4290	Assert(pPage->cPresent);
4291	Assert(pPool->cPresent);
4292	pPage->cPresent--;
4293	pPool->cPresent--;
4294	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4295	return;
4296	}
4297	}
4298	pRam = pRam->CTX_SUFF(pNext);
4299	}
4300
4301	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp (Hinted page has HCPhys = %RHp)\n", HCPhys, GCPhysHint, HCPhysHinted));
4302	}
4303
4304
4305	/**
4306	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
4307	*
4308	* @param pPool The pool.
4309	* @param pPage The page.
4310	* @param pShwPT The shadow page table (mapping of the page).
4311	* @param pGstPT The guest page table.
4312	*/
4313	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
4314	{
4315	RTGCPHYS32 const fPgMask = pPage->fA20Enabled ? X86_PTE_PG_MASK : X86_PTE_PG_MASK & ~RT_BIT_32(20);
4316	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4317	{
4318	Assert(!(pShwPT->a[i].u & RT_BIT_32(10)));
4319	if (pShwPT->a[i].n.u1Present)
4320	{
4321	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
4322	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4323	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & fPgMask, i);
4324	if (!pPage->cPresent)
4325	break;
4326	}
4327	}
4328	}
4329
4330
4331	/**
4332	* Clear references to guest physical memory in a PAE / 32-bit page table.
4333	*
4334	* @param pPool The pool.
4335	* @param pPage The page.
4336	* @param pShwPT The shadow page table (mapping of the page).
4337	* @param pGstPT The guest page table (just a half one).
4338	*/
4339	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
4340	{
4341	RTGCPHYS32 const fPgMask = pPage->fA20Enabled ? X86_PTE_PG_MASK : X86_PTE_PG_MASK & ~RT_BIT_32(20);
4342	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4343	{
4344	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4345	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4346	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4347	{
4348	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
4349	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PG_MASK));
4350	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & fPgMask, i);
4351	if (!pPage->cPresent)
4352	break;
4353	}
4354	}
4355	}
4356
4357
4358	/**
4359	* Clear references to guest physical memory in a PAE / PAE page table.
4360	*
4361	* @param pPool The pool.
4362	* @param pPage The page.
4363	* @param pShwPT The shadow page table (mapping of the page).
4364	* @param pGstPT The guest page table.
4365	*/
4366	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
4367	{
4368	RTGCPHYS const fPgMask = pPage->fA20Enabled ? X86_PTE_PAE_PG_MASK : X86_PTE_PAE_PG_MASK & ~RT_BIT_64(20);
4369	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4370	{
4371	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4372	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4373	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4374	{
4375	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4376	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4377	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & fPgMask, i);
4378	if (!pPage->cPresent)
4379	break;
4380	}
4381	}
4382	}
4383
4384
4385	/**
4386	* Clear references to guest physical memory in a 32-bit / 4MB page table.
4387	*
4388	* @param pPool The pool.
4389	* @param pPage The page.
4390	* @param pShwPT The shadow page table (mapping of the page).
4391	*/
4392	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4393	{
4394	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4395	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4396	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4397	{
4398	Assert(!(pShwPT->a[i].u & RT_BIT_32(10)));
4399	if (pShwPT->a[i].n.u1Present)
4400	{
4401	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4402	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
4403	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys & GCPhysA20Mask, i);
4404	if (!pPage->cPresent)
4405	break;
4406	}
4407	}
4408	}
4409
4410
4411	/**
4412	* Clear references to guest physical memory in a PAE / 2/4MB page table.
4413	*
4414	* @param pPool The pool.
4415	* @param pPage The page.
4416	* @param pShwPT The shadow page table (mapping of the page).
4417	*/
4418	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT)
4419	{
4420	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4421	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4422	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4423	{
4424	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4425	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4426	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4427	{
4428	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4429	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys));
4430	pgmPoolTracDerefGCPhys(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys & GCPhysA20Mask, i);
4431	if (!pPage->cPresent)
4432	break;
4433	}
4434	}
4435	}
4436
4437
4438	/**
4439	* Clear references to shadowed pages in an EPT page table.
4440	*
4441	* @param pPool The pool.
4442	* @param pPage The page.
4443	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4444	*/
4445	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4446	{
4447	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4448	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4449	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4450	{
4451	Assert((pShwPT->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4452	if (pShwPT->a[i].n.u1Present)
4453	{
4454	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4455	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4456	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys & GCPhysA20Mask, i);
4457	if (!pPage->cPresent)
4458	break;
4459	}
4460	}
4461	}
4462
4463
4464	/**
4465	* Clear references to shadowed pages in a 32 bits page directory.
4466	*
4467	* @param pPool The pool.
4468	* @param pPage The page.
4469	* @param pShwPD The shadow page directory (mapping of the page).
4470	*/
4471	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4472	{
4473	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4474	{
4475	Assert(!(pShwPD->a[i].u & RT_BIT_32(9)));
4476	if ( pShwPD->a[i].n.u1Present
4477	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4478	)
4479	{
4480	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4481	if (pSubPage)
4482	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4483	else
4484	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4485	}
4486	}
4487	}
4488
4489
4490	/**
4491	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4492	*
4493	* @param pPool The pool.
4494	* @param pPage The page.
4495	* @param pShwPD The shadow page directory (mapping of the page).
4496	*/
4497	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4498	{
4499	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4500	{
4501	if ( pShwPD->a[i].n.u1Present
4502	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING))
4503	{
4504	#ifdef PGM_WITH_LARGE_PAGES
4505	if (pShwPD->a[i].b.u1Size)
4506	{
4507	Log4(("pgmPoolTrackDerefPDPae: i=%d pde=%RX64 GCPhys=%RX64\n",
4508	i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4509	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK,
4510	pPage->GCPhys + i * 2 * _1M /* pPage->GCPhys = base address of the memory described by the PD */,
4511	i);
4512	}
4513	else
4514	#endif
4515	{
4516	Assert((pShwPD->a[i].u & (X86_PDE_PAE_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4517	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4518	if (pSubPage)
4519	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4520	else
4521	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4522	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4523	}
4524	}
4525	}
4526	}
4527
4528
4529	/**
4530	* Clear references to shadowed pages in a PAE page directory pointer table.
4531	*
4532	* @param pPool The pool.
4533	* @param pPage The page.
4534	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4535	*/
4536	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4537	{
4538	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4539	{
4540	Assert((pShwPDPT->a[i].u & (X86_PDPE_PAE_MBZ_MASK \| UINT64_C(0x7ff0000000000200))) == 0);
4541	if ( pShwPDPT->a[i].n.u1Present
4542	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4543	)
4544	{
4545	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4546	if (pSubPage)
4547	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4548	else
4549	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4550	}
4551	}
4552	}
4553
4554
4555	/**
4556	* Clear references to shadowed pages in a 64-bit page directory pointer table.
4557	*
4558	* @param pPool The pool.
4559	* @param pPage The page.
4560	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4561	*/
4562	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4563	{
4564	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4565	{
4566	Assert((pShwPDPT->a[i].u & (X86_PDPE_LM_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4567	if (pShwPDPT->a[i].n.u1Present)
4568	{
4569	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4570	if (pSubPage)
4571	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4572	else
4573	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4574	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4575	}
4576	}
4577	}
4578
4579
4580	/**
4581	* Clear references to shadowed pages in a 64-bit level 4 page table.
4582	*
4583	* @param pPool The pool.
4584	* @param pPage The page.
4585	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4586	*/
4587	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4588	{
4589	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4590	{
4591	Assert((pShwPML4->a[i].u & (X86_PML4E_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4592	if (pShwPML4->a[i].n.u1Present)
4593	{
4594	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4595	if (pSubPage)
4596	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4597	else
4598	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4599	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4600	}
4601	}
4602	}
4603
4604
4605	/**
4606	* Clear references to shadowed pages in an EPT page directory.
4607	*
4608	* @param pPool The pool.
4609	* @param pPage The page.
4610	* @param pShwPD The shadow page directory (mapping of the page).
4611	*/
4612	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4613	{
4614	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4615	{
4616	Assert((pShwPD->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4617	if (pShwPD->a[i].n.u1Present)
4618	{
4619	#ifdef PGM_WITH_LARGE_PAGES
4620	if (pShwPD->a[i].b.u1Size)
4621	{
4622	Log4(("pgmPoolTrackDerefPDEPT: i=%d pde=%RX64 GCPhys=%RX64\n",
4623	i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4624	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK,
4625	pPage->GCPhys + i * 2 * _1M /* pPage->GCPhys = base address of the memory described by the PD */,
4626	i);
4627	}
4628	else
4629	#endif
4630	{
4631	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4632	if (pSubPage)
4633	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4634	else
4635	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4636	}
4637	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4638	}
4639	}
4640	}
4641
4642
4643	/**
4644	* Clear references to shadowed pages in an EPT page directory pointer table.
4645	*
4646	* @param pPool The pool.
4647	* @param pPage The page.
4648	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4649	*/
4650	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4651	{
4652	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4653	{
4654	Assert((pShwPDPT->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4655	if (pShwPDPT->a[i].n.u1Present)
4656	{
4657	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4658	if (pSubPage)
4659	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4660	else
4661	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4662	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4663	}
4664	}
4665	}
4666
4667
4668	/**
4669	* Clears all references made by this page.
4670	*
4671	* This includes other shadow pages and GC physical addresses.
4672	*
4673	* @param pPool The pool.
4674	* @param pPage The page.
4675	*/
4676	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4677	{
4678	/*
4679	* Map the shadow page and take action according to the page kind.
4680	*/
4681	PVM pVM = pPool->CTX_SUFF(pVM);
4682	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4683	switch (pPage->enmKind)
4684	{
4685	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4686	{
4687	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4688	void *pvGst;
4689	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4690	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4691	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4692	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4693	break;
4694	}
4695
4696	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4697	{
4698	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4699	void *pvGst;
4700	int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4701	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst);
4702	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4703	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4704	break;
4705	}
4706
4707	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4708	{
4709	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4710	void *pvGst;
4711	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4712	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
4713	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4714	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4715	break;
4716	}
4717
4718	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4719	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4720	{
4721	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4722	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4723	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4724	break;
4725	}
4726
4727	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4728	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4729	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4730	{
4731	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4732	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PPGMSHWPTPAE)pvShw);
4733	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4734	break;
4735	}
4736
4737	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4738	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4739	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4740	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4741	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4742	case PGMPOOLKIND_PAE_PD_PHYS:
4743	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4744	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4745	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4746	break;
4747
4748	case PGMPOOLKIND_32BIT_PD_PHYS:
4749	case PGMPOOLKIND_32BIT_PD:
4750	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4751	break;
4752
4753	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4754	case PGMPOOLKIND_PAE_PDPT:
4755	case PGMPOOLKIND_PAE_PDPT_PHYS:
4756	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4757	break;
4758
4759	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4760	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4761	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4762	break;
4763
4764	case PGMPOOLKIND_64BIT_PML4:
4765	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4766	break;
4767
4768	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4769	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4770	break;
4771
4772	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4773	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4774	break;
4775
4776	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4777	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4778	break;
4779
4780	default:
4781	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4782	}
4783
4784	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4785	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4786	ASMMemZeroPage(pvShw);
4787	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4788	pPage->fZeroed = true;
4789	Assert(!pPage->cPresent);
4790	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
4791	}
4792
4793
4794	/**
4795	* Flushes a pool page.
4796	*
4797	* This moves the page to the free list after removing all user references to it.
4798	*
4799	* @returns VBox status code.
4800	* @retval VINF_SUCCESS on success.
4801	* @param pPool The pool.
4802	* @param HCPhys The HC physical address of the shadow page.
4803	* @param fFlush Flush the TLBS when required (should only be false in very specific use cases!!)
4804	*/
4805	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush)
4806	{
4807	PVM pVM = pPool->CTX_SUFF(pVM);
4808	bool fFlushRequired = false;
4809
4810	int rc = VINF_SUCCESS;
4811	STAM_PROFILE_START(&pPool->StatFlushPage, f);
4812	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4813	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4814
4815	/*
4816	* Reject any attempts at flushing any of the special root pages (shall
4817	* not happen).
4818	*/
4819	AssertMsgReturn(pPage->idx >= PGMPOOL_IDX_FIRST,
4820	("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n",
4821	pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx),
4822	VINF_SUCCESS);
4823
4824	pgmLock(pVM);
4825
4826	/*
4827	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4828	*/
4829	if (pgmPoolIsPageLocked(pPage))
4830	{
4831	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4832	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4833	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4834	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
4835	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4836	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4837	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4838	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4839	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD
4840	\|\| pPage->enmKind == PGMPOOLKIND_ROOT_NESTED,
4841	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4842	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4843	pgmUnlock(pVM);
4844	return VINF_SUCCESS;
4845	}
4846
4847	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4848	/* Start a subset so we won't run out of mapping space. */
4849	PVMCPU pVCpu = VMMGetCpu(pVM);
4850	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
4851	#endif
4852
4853	/*
4854	* Mark the page as being in need of an ASMMemZeroPage().
4855	*/
4856	pPage->fZeroed = false;
4857
4858	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4859	if (pPage->fDirty)
4860	pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirtyEntry, false /* do not remove */);
4861	#endif
4862
4863	/* If there are any users of this table, then we must issue a tlb flush on all VCPUs. */
4864	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
4865	fFlushRequired = true;
4866
4867	/*
4868	* Clear the page.
4869	*/
4870	pgmPoolTrackClearPageUsers(pPool, pPage);
4871	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4872	pgmPoolTrackDeref(pPool, pPage);
4873	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4874
4875	/*
4876	* Flush it from the cache.
4877	*/
4878	pgmPoolCacheFlushPage(pPool, pPage);
4879
4880	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4881	/* Heavy stuff done. */
4882	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
4883	#endif
4884
4885	/*
4886	* Deregistering the monitoring.
4887	*/
4888	if (pPage->fMonitored)
4889	rc = pgmPoolMonitorFlush(pPool, pPage);
4890
4891	/*
4892	* Free the page.
4893	*/
4894	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4895	pPage->iNext = pPool->iFreeHead;
4896	pPool->iFreeHead = pPage->idx;
4897	pPage->enmKind = PGMPOOLKIND_FREE;
4898	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4899	pPage->GCPhys = NIL_RTGCPHYS;
4900	pPage->fReusedFlushPending = false;
4901
4902	pPool->cUsedPages--;
4903
4904	/* Flush the TLBs of all VCPUs if required. */
4905	if ( fFlushRequired
4906	&& fFlush)
4907	{
4908	PGM_INVL_ALL_VCPU_TLBS(pVM);
4909	}
4910
4911	pgmUnlock(pVM);
4912	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4913	return rc;
4914	}
4915
4916
4917	/**
4918	* Frees a usage of a pool page.
4919	*
4920	* The caller is responsible to updating the user table so that it no longer
4921	* references the shadow page.
4922	*
4923	* @param pPool The pool.
4924	* @param HCPhys The HC physical address of the shadow page.
4925	* @param iUser The shadow page pool index of the user table.
4926	* NIL_PGMPOOL_IDX for root pages.
4927	* @param iUserTable The index into the user table (shadowed). Ignored if
4928	* root page.
4929	*/
4930	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4931	{
4932	PVM pVM = pPool->CTX_SUFF(pVM);
4933
4934	STAM_PROFILE_START(&pPool->StatFree, a);
4935	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%d iUserTable=%#x\n",
4936	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4937	AssertReturnVoid(pPage->idx >= PGMPOOL_IDX_FIRST); /* paranoia (#6349) */
4938
4939	pgmLock(pVM);
4940	if (iUser != NIL_PGMPOOL_IDX)
4941	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4942	if (!pPage->fCached)
4943	pgmPoolFlushPage(pPool, pPage);
4944	pgmUnlock(pVM);
4945	STAM_PROFILE_STOP(&pPool->StatFree, a);
4946	}
4947
4948
4949	/**
4950	* Makes one or more free page free.
4951	*
4952	* @returns VBox status code.
4953	* @retval VINF_SUCCESS on success.
4954	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4955	*
4956	* @param pPool The pool.
4957	* @param enmKind Page table kind
4958	* @param iUser The user of the page.
4959	*/
4960	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4961	{
4962	PVM pVM = pPool->CTX_SUFF(pVM);
4963	LogFlow(("pgmPoolMakeMoreFreePages: enmKind=%d iUser=%d\n", enmKind, iUser));
4964	NOREF(enmKind);
4965
4966	/*
4967	* If the pool isn't full grown yet, expand it.
4968	*/
4969	if ( pPool->cCurPages < pPool->cMaxPages
4970	#if defined(IN_RC)
4971	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4972	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4973	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4974	#endif
4975	)
4976	{
4977	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4978	#ifdef IN_RING3
4979	int rc = PGMR3PoolGrow(pVM);
4980	#else
4981	int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4982	#endif
4983	if (RT_FAILURE(rc))
4984	return rc;
4985	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4986	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4987	return VINF_SUCCESS;
4988	}
4989
4990	/*
4991	* Free one cached page.
4992	*/
4993	return pgmPoolCacheFreeOne(pPool, iUser);
4994	}
4995
4996
4997	/**
4998	* Allocates a page from the pool.
4999	*
5000	* This page may actually be a cached page and not in need of any processing
5001	* on the callers part.
5002	*
5003	* @returns VBox status code.
5004	* @retval VINF_SUCCESS if a NEW page was allocated.
5005	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
5006	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
5007	*
5008	* @param pVM Pointer to the VM.
5009	* @param GCPhys The GC physical address of the page we're gonna shadow.
5010	* For 4MB and 2MB PD entries, it's the first address the
5011	* shadow PT is covering.
5012	* @param enmKind The kind of mapping.
5013	* @param enmAccess Access type for the mapping (only relevant for big pages)
5014	* @param fA20Enabled Whether the A20 gate is enabled or not.
5015	* @param iUser The shadow page pool index of the user table. Root
5016	* pages should pass NIL_PGMPOOL_IDX.
5017	* @param iUserTable The index into the user table (shadowed). Ignored for
5018	* root pages (iUser == NIL_PGMPOOL_IDX).
5019	* @param fLockPage Lock the page
5020	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
5021	*/
5022	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
5023	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage)
5024	{
5025	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5026	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
5027	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%d iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
5028	*ppPage = NULL;
5029	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
5030	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
5031	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
5032
5033	pgmLock(pVM);
5034
5035	if (pPool->fCacheEnabled)
5036	{
5037	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, fA20Enabled, iUser, iUserTable, ppPage);
5038	if (RT_SUCCESS(rc2))
5039	{
5040	if (fLockPage)
5041	pgmPoolLockPage(pPool, *ppPage);
5042	pgmUnlock(pVM);
5043	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5044	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
5045	return rc2;
5046	}
5047	}
5048
5049	/*
5050	* Allocate a new one.
5051	*/
5052	int rc = VINF_SUCCESS;
5053	uint16_t iNew = pPool->iFreeHead;
5054	if (iNew == NIL_PGMPOOL_IDX)
5055	{
5056	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
5057	if (RT_FAILURE(rc))
5058	{
5059	pgmUnlock(pVM);
5060	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
5061	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5062	return rc;
5063	}
5064	iNew = pPool->iFreeHead;
5065	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_PGM_POOL_IPE);
5066	}
5067
5068	/* unlink the free head */
5069	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
5070	pPool->iFreeHead = pPage->iNext;
5071	pPage->iNext = NIL_PGMPOOL_IDX;
5072
5073	/*
5074	* Initialize it.
5075	*/
5076	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
5077	pPage->enmKind = enmKind;
5078	pPage->enmAccess = enmAccess;
5079	pPage->GCPhys = GCPhys;
5080	pPage->fA20Enabled = fA20Enabled;
5081	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
5082	pPage->fMonitored = false;
5083	pPage->fCached = false;
5084	pPage->fDirty = false;
5085	pPage->fReusedFlushPending = false;
5086	pPage->cModifications = 0;
5087	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5088	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5089	pPage->cPresent = 0;
5090	pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
5091	pPage->idxDirtyEntry = 0;
5092	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
5093	pPage->GCPtrLastAccessHandlerRip = NIL_RTGCPTR;
5094	pPage->cLastAccessHandler = 0;
5095	pPage->cLocked = 0;
5096	# ifdef VBOX_STRICT
5097	pPage->GCPtrDirtyFault = NIL_RTGCPTR;
5098	# endif
5099
5100	/*
5101	* Insert into the tracking and cache. If this fails, free the page.
5102	*/
5103	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
5104	if (RT_FAILURE(rc3))
5105	{
5106	pPool->cUsedPages--;
5107	pPage->enmKind = PGMPOOLKIND_FREE;
5108	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5109	pPage->GCPhys = NIL_RTGCPHYS;
5110	pPage->iNext = pPool->iFreeHead;
5111	pPool->iFreeHead = pPage->idx;
5112	pgmUnlock(pVM);
5113	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5114	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
5115	return rc3;
5116	}
5117
5118	/*
5119	* Commit the allocation, clear the page and return.
5120	*/
5121	#ifdef VBOX_WITH_STATISTICS
5122	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
5123	pPool->cUsedPagesHigh = pPool->cUsedPages;
5124	#endif
5125
5126	if (!pPage->fZeroed)
5127	{
5128	STAM_PROFILE_START(&pPool->StatZeroPage, z);
5129	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
5130	ASMMemZeroPage(pv);
5131	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
5132	}
5133
5134	*ppPage = pPage;
5135	if (fLockPage)
5136	pgmPoolLockPage(pPool, pPage);
5137	pgmUnlock(pVM);
5138	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
5139	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
5140	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5141	return rc;
5142	}
5143
5144
5145	/**
5146	* Frees a usage of a pool page.
5147	*
5148	* @param pVM Pointer to the VM.
5149	* @param HCPhys The HC physical address of the shadow page.
5150	* @param iUser The shadow page pool index of the user table.
5151	* NIL_PGMPOOL_IDX if root page.
5152	* @param iUserTable The index into the user table (shadowed). Ignored if
5153	* root page.
5154	*/
5155	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
5156	{
5157	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%d iUserTable=%#x\n", HCPhys, iUser, iUserTable));
5158	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5159	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
5160	}
5161
5162
5163	/**
5164	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
5165	*
5166	* @returns Pointer to the shadow page structure.
5167	* @param pPool The pool.
5168	* @param HCPhys The HC physical address of the shadow page.
5169	*/
5170	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
5171	{
5172	PGM_LOCK_ASSERT_OWNER(pPool->CTX_SUFF(pVM));
5173
5174	/*
5175	* Look up the page.
5176	*/
5177	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
5178
5179	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
5180	return pPage;
5181	}
5182
5183
5184	/**
5185	* Internal worker for finding a page for debugging purposes, no assertions.
5186	*
5187	* @returns Pointer to the shadow page structure. NULL on if not found.
5188	* @param pPool The pool.
5189	* @param HCPhys The HC physical address of the shadow page.
5190	*/
5191	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys)
5192	{
5193	PGM_LOCK_ASSERT_OWNER(pPool->CTX_SUFF(pVM));
5194	return (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
5195	}
5196
5197	#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
5198
5199	/**
5200	* Flush the specified page if present
5201	*
5202	* @param pVM Pointer to the VM.
5203	* @param GCPhys Guest physical address of the page to flush
5204	*/
5205	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
5206	{
5207	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5208
5209	VM_ASSERT_EMT(pVM);
5210
5211	/*
5212	* Look up the GCPhys in the hash.
5213	*/
5214	GCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
5215	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
5216	if (i == NIL_PGMPOOL_IDX)
5217	return;
5218
5219	do
5220	{
5221	PPGMPOOLPAGE pPage = &pPool->aPages[i];
5222	if (pPage->GCPhys - GCPhys < PAGE_SIZE)
5223	{
5224	switch (pPage->enmKind)
5225	{
5226	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5227	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5228	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5229	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5230	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5231	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5232	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5233	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5234	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5235	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5236	case PGMPOOLKIND_64BIT_PML4:
5237	case PGMPOOLKIND_32BIT_PD:
5238	case PGMPOOLKIND_PAE_PDPT:
5239	{
5240	Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
5241	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5242	if (pPage->fDirty)
5243	STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
5244	else
5245	#endif
5246	STAM_COUNTER_INC(&pPool->StatForceFlushPage);
5247	Assert(!pgmPoolIsPageLocked(pPage));
5248	pgmPoolMonitorChainFlush(pPool, pPage);
5249	return;
5250	}
5251
5252	/* ignore, no monitoring. */
5253	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5254	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5255	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5256	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5257	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5258	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5259	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5260	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5261	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5262	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5263	case PGMPOOLKIND_ROOT_NESTED:
5264	case PGMPOOLKIND_PAE_PD_PHYS:
5265	case PGMPOOLKIND_PAE_PDPT_PHYS:
5266	case PGMPOOLKIND_32BIT_PD_PHYS:
5267	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5268	break;
5269
5270	default:
5271	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
5272	}
5273	}
5274
5275	/* next */
5276	i = pPage->iNext;
5277	} while (i != NIL_PGMPOOL_IDX);
5278	return;
5279	}
5280
5281	#endif /* IN_RING3 */
5282	#ifdef IN_RING3
5283
5284	/**
5285	* Reset CPU on hot plugging.
5286	*
5287	* @param pVM Pointer to the VM.
5288	* @param pVCpu The virtual CPU.
5289	*/
5290	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
5291	{
5292	pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
5293
5294	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5295	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5296	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5297	}
5298
5299
5300	/**
5301	* Flushes the entire cache.
5302	*
5303	* It will assert a global CR3 flush (FF) and assumes the caller is aware of
5304	* this and execute this CR3 flush.
5305	*
5306	* @param pPool The pool.
5307	*/
5308	void pgmR3PoolReset(PVM pVM)
5309	{
5310	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5311
5312	PGM_LOCK_ASSERT_OWNER(pVM);
5313	STAM_PROFILE_START(&pPool->StatR3Reset, a);
5314	LogFlow(("pgmR3PoolReset:\n"));
5315
5316	/*
5317	* If there are no pages in the pool, there is nothing to do.
5318	*/
5319	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
5320	{
5321	STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5322	return;
5323	}
5324
5325	/*
5326	* Exit the shadow mode since we're going to clear everything,
5327	* including the root page.
5328	*/
5329	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5330	pgmR3ExitShadowModeBeforePoolFlush(&pVM->aCpus[i]);
5331
5332	/*
5333	* Nuke the free list and reinsert all pages into it.
5334	*/
5335	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
5336	{
5337	PPGMPOOLPAGE pPage = &pPool->aPages[i];
5338
5339	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
5340	if (pPage->fMonitored)
5341	pgmPoolMonitorFlush(pPool, pPage);
5342	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5343	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5344	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5345	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5346	pPage->cModifications = 0;
5347	pPage->GCPhys = NIL_RTGCPHYS;
5348	pPage->enmKind = PGMPOOLKIND_FREE;
5349	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5350	Assert(pPage->idx == i);
5351	pPage->iNext = i + 1;
5352	pPage->fA20Enabled = true;
5353	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
5354	pPage->fSeenNonGlobal = false;
5355	pPage->fMonitored = false;
5356	pPage->fDirty = false;
5357	pPage->fCached = false;
5358	pPage->fReusedFlushPending = false;
5359	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
5360	pPage->iAgeNext = NIL_PGMPOOL_IDX;
5361	pPage->iAgePrev = NIL_PGMPOOL_IDX;
5362	pPage->GCPtrLastAccessHandlerRip = NIL_RTGCPTR;
5363	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
5364	pPage->cLastAccessHandler = 0;
5365	pPage->cLocked = 0;
5366	#ifdef VBOX_STRICT
5367	pPage->GCPtrDirtyFault = NIL_RTGCPTR;
5368	#endif
5369	}
5370	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
5371	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
5372	pPool->cUsedPages = 0;
5373
5374	/*
5375	* Zap and reinitialize the user records.
5376	*/
5377	pPool->cPresent = 0;
5378	pPool->iUserFreeHead = 0;
5379	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
5380	const unsigned cMaxUsers = pPool->cMaxUsers;
5381	for (unsigned i = 0; i < cMaxUsers; i++)
5382	{
5383	paUsers[i].iNext = i + 1;
5384	paUsers[i].iUser = NIL_PGMPOOL_IDX;
5385	paUsers[i].iUserTable = 0xfffffffe;
5386	}
5387	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
5388
5389	/*
5390	* Clear all the GCPhys links and rebuild the phys ext free list.
5391	*/
5392	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
5393	pRam;
5394	pRam = pRam->CTX_SUFF(pNext))
5395	{
5396	unsigned iPage = pRam->cb >> PAGE_SHIFT;
5397	while (iPage-- > 0)
5398	PGM_PAGE_SET_TRACKING(pVM, &pRam->aPages[iPage], 0);
5399	}
5400
5401	pPool->iPhysExtFreeHead = 0;
5402	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
5403	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
5404	for (unsigned i = 0; i < cMaxPhysExts; i++)
5405	{
5406	paPhysExts[i].iNext = i + 1;
5407	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
5408	paPhysExts[i].apte[0] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5409	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
5410	paPhysExts[i].apte[1] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5411	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
5412	paPhysExts[i].apte[2] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5413	}
5414	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
5415
5416	/*
5417	* Just zap the modified list.
5418	*/
5419	pPool->cModifiedPages = 0;
5420	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5421
5422	/*
5423	* Clear the GCPhys hash and the age list.
5424	*/
5425	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5426	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5427	pPool->iAgeHead = NIL_PGMPOOL_IDX;
5428	pPool->iAgeTail = NIL_PGMPOOL_IDX;
5429
5430	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5431	/* Clear all dirty pages. */
5432	pPool->idxFreeDirtyPage = 0;
5433	pPool->cDirtyPages = 0;
5434	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
5435	pPool->aDirtyPages[i].uIdx = NIL_PGMPOOL_IDX;
5436	#endif
5437
5438	/*
5439	* Reinsert active pages into the hash and ensure monitoring chains are correct.
5440	*/
5441	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5442	{
5443	/*
5444	* Re-enter the shadowing mode and assert Sync CR3 FF.
5445	*/
5446	PVMCPU pVCpu = &pVM->aCpus[i];
5447	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5448	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5449	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5450	}
5451
5452	STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5453	}
5454
5455	#endif /* IN_RING3 */
5456
5457	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
5458	/**
5459	* Stringifies a PGMPOOLKIND value.
5460	*/
5461	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5462	{
5463	switch ((PGMPOOLKIND)enmKind)
5464	{
5465	case PGMPOOLKIND_INVALID:
5466	return "PGMPOOLKIND_INVALID";
5467	case PGMPOOLKIND_FREE:
5468	return "PGMPOOLKIND_FREE";
5469	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5470	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5471	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5472	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5473	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5474	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5475	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5476	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5477	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5478	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5479	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5480	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5481	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5482	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5483	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5484	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5485	case PGMPOOLKIND_32BIT_PD:
5486	return "PGMPOOLKIND_32BIT_PD";
5487	case PGMPOOLKIND_32BIT_PD_PHYS:
5488	return "PGMPOOLKIND_32BIT_PD_PHYS";
5489	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5490	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5491	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5492	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5493	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5494	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5495	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5496	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5497	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5498	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5499	case PGMPOOLKIND_PAE_PD_PHYS:
5500	return "PGMPOOLKIND_PAE_PD_PHYS";
5501	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5502	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5503	case PGMPOOLKIND_PAE_PDPT:
5504	return "PGMPOOLKIND_PAE_PDPT";
5505	case PGMPOOLKIND_PAE_PDPT_PHYS:
5506	return "PGMPOOLKIND_PAE_PDPT_PHYS";
5507	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5508	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5509	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5510	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5511	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5512	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5513	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5514	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5515	case PGMPOOLKIND_64BIT_PML4:
5516	return "PGMPOOLKIND_64BIT_PML4";
5517	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5518	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5519	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5520	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5521	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5522	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5523	case PGMPOOLKIND_ROOT_NESTED:
5524	return "PGMPOOLKIND_ROOT_NESTED";
5525	}
5526	return "Unknown kind!";
5527	}
5528	#endif /* LOG_ENABLED \|\| VBOX_STRICT */
5529

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