VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp@ 84044

Last change on this file since 84044 was 82968, checked in by vboxsync, 4 years ago

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1/* $Id: PGMAllMap.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM
23#include <VBox/vmm/pgm.h>
24#include <VBox/vmm/em.h>
25#include "PGMInternal.h"
26#include <VBox/vmm/vmcc.h>
27#include "PGMInline.h"
28#include <VBox/err.h>
29#include <iprt/asm-amd64-x86.h>
30#include <iprt/assert.h>
31
32
33#ifndef PGM_WITHOUT_MAPPINGS
34
35/**
36 * Maps a range of physical pages at a given virtual address
37 * in the guest context.
38 *
39 * The GC virtual address range must be within an existing mapping.
40 *
41 * @returns VBox status code.
42 * @param pVM The cross context VM structure.
43 * @param GCPtr Where to map the page(s). Must be page aligned.
44 * @param HCPhys Start of the range of physical pages. Must be page aligned.
45 * @param cbPages Number of bytes to map. Must be page aligned.
46 * @param fFlags Page flags (X86_PTE_*).
47 */
48VMMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags)
49{
50 AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
51
52 /*
53 * Validate input.
54 */
55 AssertMsg(RT_ALIGN_T(GCPtr, PAGE_SIZE, RTGCUINTPTR) == GCPtr, ("Invalid alignment GCPtr=%#x\n", GCPtr));
56 AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n", cbPages));
57 AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
58
59 /* hypervisor defaults */
60 if (!fFlags)
61 fFlags = X86_PTE_P | X86_PTE_A | X86_PTE_D;
62
63 /*
64 * Find the mapping.
65 */
66 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
67 while (pCur)
68 {
69 if (GCPtr - pCur->GCPtr < pCur->cb)
70 {
71 if (GCPtr + cbPages - 1 > pCur->GCPtrLast)
72 {
73 AssertMsgFailed(("Invalid range!!\n"));
74 return VERR_INVALID_PARAMETER;
75 }
76
77 /*
78 * Setup PTE.
79 */
80 X86PTEPAE Pte;
81 Pte.u = fFlags | (HCPhys & X86_PTE_PAE_PG_MASK);
82
83 /*
84 * Update the page tables.
85 */
86 for (;;)
87 {
88 RTGCUINTPTR off = GCPtr - pCur->GCPtr;
89 const unsigned iPT = off >> X86_PD_SHIFT;
90 const unsigned iPageNo = (off >> PAGE_SHIFT) & X86_PT_MASK;
91
92 /* 32-bit */
93 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPageNo].u = (uint32_t)Pte.u; /* ASSUMES HCPhys < 4GB and/or that we're never gonna do 32-bit on a PAE host! */
94
95 /* pae */
96 PGMSHWPTEPAE_SET(pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512], Pte.u);
97
98 /* next */
99 cbPages -= PAGE_SIZE;
100 if (!cbPages)
101 break;
102 GCPtr += PAGE_SIZE;
103 Pte.u += PAGE_SIZE;
104 }
105
106 return VINF_SUCCESS;
107 }
108
109 /* next */
110 pCur = pCur->CTX_SUFF(pNext);
111 }
112
113 AssertMsgFailed(("GCPtr=%#x was not found in any mapping ranges!\n", GCPtr));
114 return VERR_INVALID_PARAMETER;
115}
116
117
118/**
119 * Sets (replaces) the page flags for a range of pages in a mapping.
120 *
121 * @returns VBox status code.
122 * @param pVM The cross context VM structure.
123 * @param GCPtr Virtual address of the first page in the range.
124 * @param cb Size (in bytes) of the range to apply the modification to.
125 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
126 */
127VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags)
128{
129 return PGMMapModifyPage(pVM, GCPtr, cb, fFlags, 0);
130}
131
132
133/**
134 * Modify page flags for a range of pages in a mapping.
135 *
136 * The existing flags are ANDed with the fMask and ORed with the fFlags.
137 *
138 * @returns VBox status code.
139 * @param pVM The cross context VM structure.
140 * @param GCPtr Virtual address of the first page in the range.
141 * @param cb Size (in bytes) of the range to apply the modification to.
142 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
143 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
144 */
145VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
146{
147 /*
148 * Validate input.
149 */
150 AssertMsg(!(fFlags & (X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX)), ("fFlags=%#x\n", fFlags));
151 Assert(cb);
152
153 /*
154 * Align the input.
155 */
156 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
157 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
158 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
159
160 /*
161 * Find the mapping.
162 */
163 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
164 while (pCur)
165 {
166 RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
167 if (off < pCur->cb)
168 {
169 AssertMsgReturn(off + cb <= pCur->cb,
170 ("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
171 GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
172 VERR_INVALID_PARAMETER);
173
174 /*
175 * Perform the requested operation.
176 */
177 while (cb > 0)
178 {
179 unsigned iPT = off >> X86_PD_SHIFT;
180 unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
181 while (cb > 0 && iPTE < RT_ELEMENTS(pCur->aPTs[iPT].CTX_SUFF(pPT)->a))
182 {
183 /* 32-Bit */
184 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u &= fMask | X86_PTE_PG_MASK;
185 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u |= fFlags & ~X86_PTE_PG_MASK;
186
187 /* PAE */
188 PPGMSHWPTEPAE pPtePae = &pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
189 PGMSHWPTEPAE_SET(*pPtePae,
190 ( PGMSHWPTEPAE_GET_U(*pPtePae)
191 & (fMask | X86_PTE_PAE_PG_MASK))
192 | (fFlags & ~(X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX)));
193
194 /* invalidate tls */
195 PGM_INVL_PG(VMMGetCpu(pVM), (RTGCUINTPTR)pCur->GCPtr + off);
196
197 /* next */
198 iPTE++;
199 cb -= PAGE_SIZE;
200 off += PAGE_SIZE;
201 }
202 }
203
204 return VINF_SUCCESS;
205 }
206 /* next */
207 pCur = pCur->CTX_SUFF(pNext);
208 }
209
210 AssertMsgFailed(("Page range %#x LB%#x not found\n", GCPtr, cb));
211 return VERR_INVALID_PARAMETER;
212}
213
214
215/**
216 * Get information about a page in a mapping.
217 *
218 * This differs from PGMShwGetPage and PGMGstGetPage in that it only consults
219 * the page table to calculate the flags.
220 *
221 * @returns VINF_SUCCESS, VERR_PAGE_NOT_PRESENT or VERR_NOT_FOUND.
222 * @param pVM The cross context VM structure.
223 * @param GCPtr The page address.
224 * @param pfFlags Where to return the flags. Optional.
225 * @param pHCPhys Where to return the address. Optional.
226 */
227VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
228{
229 /*
230 * Find the mapping.
231 */
232 GCPtr &= PAGE_BASE_GC_MASK;
233 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
234 while (pCur)
235 {
236 RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
237 if (off < pCur->cb)
238 {
239 /*
240 * Dig out the information.
241 */
242 int rc = VINF_SUCCESS;
243 unsigned iPT = off >> X86_PD_SHIFT;
244 unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
245 PCPGMSHWPTEPAE pPtePae = &pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
246 if (PGMSHWPTEPAE_IS_P(*pPtePae))
247 {
248 if (pfFlags)
249 *pfFlags = PGMSHWPTEPAE_GET_U(*pPtePae) & ~X86_PTE_PAE_PG_MASK;
250 if (pHCPhys)
251 *pHCPhys = PGMSHWPTEPAE_GET_HCPHYS(*pPtePae);
252 }
253 else
254 rc = VERR_PAGE_NOT_PRESENT;
255 return rc;
256 }
257 /* next */
258 pCur = pCur->CTX_SUFF(pNext);
259 }
260
261 return VERR_NOT_FOUND;
262}
263
264
265/**
266 * Sets all PDEs involved with the mapping in the shadow page table.
267 *
268 * Ignored if mappings are disabled (i.e. if HM is enabled).
269 *
270 * @param pVM The cross context VM structure.
271 * @param pMap Pointer to the mapping in question.
272 * @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
273 */
274void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
275{
276 Log4(("pgmMapSetShadowPDEs new pde %x (mappings enabled %d)\n", iNewPDE, pgmMapAreMappingsEnabled(pVM)));
277
278 if (!pgmMapAreMappingsEnabled(pVM))
279 return;
280
281 /* This only applies to raw mode where we only support 1 VCPU. */
282 PVMCPU pVCpu = VMMGetCpu0(pVM);
283 if (!pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
284 return; /* too early */
285
286 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
287 Assert(enmShadowMode <= PGMMODE_PAE_NX);
288
289 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
290
291 /*
292 * Insert the page tables into the shadow page directories.
293 */
294 unsigned i = pMap->cPTs;
295 iNewPDE += i;
296 while (i-- > 0)
297 {
298 iNewPDE--;
299
300 switch (enmShadowMode)
301 {
302 case PGMMODE_32_BIT:
303 {
304 PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(pVCpu);
305 AssertFatal(pShw32BitPd);
306
307 /* Free any previous user, unless it's us. */
308 Assert( (pShw32BitPd->a[iNewPDE].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
309 || (pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK) == pMap->aPTs[i].HCPhysPT);
310 if ( pShw32BitPd->a[iNewPDE].n.u1Present
311 && !(pShw32BitPd->a[iNewPDE].u & PGM_PDFLAGS_MAPPING))
312 pgmPoolFree(pVM, pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iNewPDE);
313
314 /* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags. */
315 pShw32BitPd->a[iNewPDE].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
316 | (uint32_t)pMap->aPTs[i].HCPhysPT;
317 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShw32BitPd);
318 break;
319 }
320
321 case PGMMODE_PAE:
322 case PGMMODE_PAE_NX:
323 {
324 const uint32_t iPdPt = iNewPDE / 256;
325 unsigned iPaePde = iNewPDE * 2 % 512;
326 PX86PDPT pShwPdpt = pgmShwGetPaePDPTPtr(pVCpu);
327 Assert(pShwPdpt);
328
329 /*
330 * Get the shadow PD.
331 * If no PD, sync it (PAE guest) or fake (not present or 32-bit guest).
332 * Note! The RW, US and A bits are reserved for PAE PDPTEs. Setting the
333 * accessed bit causes invalid VT-x guest state errors.
334 */
335 PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT);
336 if (!pShwPaePd)
337 {
338 X86PDPE GstPdpe;
339 if (PGMGetGuestMode(pVCpu) < PGMMODE_PAE)
340 GstPdpe.u = X86_PDPE_P;
341 else
342 {
343 PX86PDPE pGstPdpe = pgmGstGetPaePDPEPtr(pVCpu, iPdPt << X86_PDPT_SHIFT);
344 if (pGstPdpe)
345 GstPdpe = *pGstPdpe;
346 else
347 GstPdpe.u = X86_PDPE_P;
348 }
349 int rc = pgmShwSyncPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT, GstPdpe.u, &pShwPaePd);
350 AssertFatalRC(rc);
351 }
352 Assert(pShwPaePd);
353
354 /*
355 * Mark the page as locked; disallow flushing.
356 */
357 PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
358 AssertFatal(pPoolPagePd);
359 if (!pgmPoolIsPageLocked(pPoolPagePd))
360 pgmPoolLockPage(pPool, pPoolPagePd);
361# ifdef VBOX_STRICT
362 else if (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING)
363 {
364 Assert(PGMGetGuestMode(pVCpu) >= PGMMODE_PAE); /** @todo We may hit this during reset, will fix later. */
365 AssertFatalMsg( (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0
366 || !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
367 ("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK, pMap->aPTs[i].HCPhysPaePT0));
368 Assert(pShwPaePd->a[iPaePde+1].u & PGM_PDFLAGS_MAPPING);
369 AssertFatalMsg( (pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1
370 || !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
371 ("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK, pMap->aPTs[i].HCPhysPaePT1));
372 }
373# endif
374
375 /*
376 * Insert our first PT, freeing anything we might be replacing unless it's a mapping (i.e. us).
377 */
378 Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
379 || (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0);
380 if ( pShwPaePd->a[iPaePde].n.u1Present
381 && !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
382 {
383 Assert(!(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
384 pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK, pPoolPagePd->idx, iPaePde);
385 }
386 pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
387 | pMap->aPTs[i].HCPhysPaePT0;
388
389 /* 2nd 2 MB PDE of the 4 MB region, same as above. */
390 iPaePde++;
391 AssertFatal(iPaePde < 512);
392 Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
393 || (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1);
394 if ( pShwPaePd->a[iPaePde].n.u1Present
395 && !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
396 pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iPaePde);
397 pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
398 | pMap->aPTs[i].HCPhysPaePT1;
399
400 /*
401 * Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode)
402 */
403 pShwPdpt->a[iPdPt].u |= PGM_PLXFLAGS_MAPPING;
404
405 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPaePd);
406 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPdpt);
407 break;
408 }
409
410 default:
411 AssertFailed();
412 break;
413 }
414 }
415}
416
417
418/**
419 * Clears all PDEs involved with the mapping in the shadow page table.
420 *
421 * Ignored if mappings are disabled (i.e. if HM is enabled).
422 *
423 * @param pVM The cross context VM structure.
424 * @param pShwPageCR3 CR3 root page
425 * @param pMap Pointer to the mapping in question.
426 * @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
427 * @param fDeactivateCR3 Set if it's pgmMapDeactivateCR3 calling.
428 */
429void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3)
430{
431 Log(("pgmMapClearShadowPDEs: old pde %x (cPTs=%x) (mappings enabled %d) fDeactivateCR3=%RTbool\n", iOldPDE, pMap->cPTs, pgmMapAreMappingsEnabled(pVM), fDeactivateCR3));
432
433 /*
434 * Skip this if it doesn't apply.
435 */
436 if (!pgmMapAreMappingsEnabled(pVM))
437 return;
438
439 Assert(pShwPageCR3);
440
441 /* This only applies to raw mode where we only support 1 VCPU. */
442 PVMCPU pVCpu = VMMGetCpu0(pVM);
443# error fixme
444
445 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
446
447 PX86PDPT pCurrentShwPdpt = NULL;
448 if ( PGMGetGuestMode(pVCpu) >= PGMMODE_PAE
449 && pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
450 pCurrentShwPdpt = pgmShwGetPaePDPTPtr(pVCpu);
451
452 unsigned i = pMap->cPTs;
453 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
454
455 iOldPDE += i;
456 while (i-- > 0)
457 {
458 iOldPDE--;
459
460 switch(enmShadowMode)
461 {
462 case PGMMODE_32_BIT:
463 {
464 PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
465 AssertFatal(pShw32BitPd);
466
467 Assert(!pShw32BitPd->a[iOldPDE].n.u1Present || (pShw32BitPd->a[iOldPDE].u & PGM_PDFLAGS_MAPPING));
468 pShw32BitPd->a[iOldPDE].u = 0;
469 break;
470 }
471
472 case PGMMODE_PAE:
473 case PGMMODE_PAE_NX:
474 {
475 const unsigned iPdpt = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
476 unsigned iPaePde = iOldPDE * 2 % 512;
477 PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
478 PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, pShwPdpt, (iPdpt << X86_PDPT_SHIFT));
479
480 /*
481 * Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode)
482 */
483 if (fDeactivateCR3)
484 pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
485 else if (pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING)
486 {
487 /* See if there are any other mappings here. This is suboptimal code. */
488 pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
489 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
490 if ( pCur != pMap
491 && ( (pCur->GCPtr >> X86_PDPT_SHIFT) == iPdpt
492 || (pCur->GCPtrLast >> X86_PDPT_SHIFT) == iPdpt))
493 {
494 pShwPdpt->a[iPdpt].u |= PGM_PLXFLAGS_MAPPING;
495 break;
496 }
497 }
498
499 /*
500 * If the page directory of the old CR3 is reused in the new one, then don't
501 * clear the hypervisor mappings.
502 */
503 if ( pCurrentShwPdpt
504 && (pCurrentShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) == (pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) )
505 {
506 LogFlow(("pgmMapClearShadowPDEs: Pdpe %d reused -> don't clear hypervisor mappings!\n", iPdpt));
507 break;
508 }
509
510 /*
511 * Clear the mappings in the PD.
512 */
513 AssertFatal(pShwPaePd);
514 Assert(!pShwPaePd->a[iPaePde].n.u1Present || (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
515 pShwPaePd->a[iPaePde].u = 0;
516
517 iPaePde++;
518 AssertFatal(iPaePde < 512);
519 Assert(!pShwPaePd->a[iPaePde].n.u1Present || (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
520 pShwPaePd->a[iPaePde].u = 0;
521
522 /*
523 * Unlock the shadow pool PD page if the PDPTE no longer holds any mappings.
524 */
525 if ( fDeactivateCR3
526 || !(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
527 {
528 PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
529 AssertFatal(pPoolPagePd);
530 if (pgmPoolIsPageLocked(pPoolPagePd))
531 pgmPoolUnlockPage(pPool, pPoolPagePd);
532 }
533 break;
534 }
535
536 default:
537 AssertFailed();
538 break;
539 }
540 }
541
542 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pCurrentShwPdpt);
543}
544
545# if defined(VBOX_STRICT) && !defined(IN_RING0)
546
547/**
548 * Clears all PDEs involved with the mapping in the shadow page table.
549 *
550 * @param pVM The cross context VM structure.
551 * @param pVCpu The cross context virtual CPU structure.
552 * @param pShwPageCR3 CR3 root page
553 * @param pMap Pointer to the mapping in question.
554 * @param iPDE The index of the 32-bit PDE corresponding to the base of the mapping.
555 */
556static void pgmMapCheckShadowPDEs(PVM pVM, PVMCPU pVCpu, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE)
557{
558 Assert(pShwPageCR3);
559
560 uint32_t i = pMap->cPTs;
561 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
562 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
563
564 iPDE += i;
565 while (i-- > 0)
566 {
567 iPDE--;
568
569 switch (enmShadowMode)
570 {
571 case PGMMODE_32_BIT:
572 {
573 PCX86PD pShw32BitPd = (PCX86PD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
574 AssertFatal(pShw32BitPd);
575
576 AssertMsg(pShw32BitPd->a[iPDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT),
577 ("Expected %x vs %x; iPDE=%#x %RGv %s\n",
578 pShw32BitPd->a[iPDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT),
579 iPDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
580 break;
581 }
582
583 case PGMMODE_PAE:
584 case PGMMODE_PAE_NX:
585 {
586 const unsigned iPdpt = iPDE / 256; /* iPDE * 2 / 512; iPDE is in 4 MB pages */
587 unsigned iPaePDE = iPDE * 2 % 512;
588 PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
589 PCX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, pShwPdpt, iPdpt << X86_PDPT_SHIFT);
590 AssertFatal(pShwPaePd);
591
592 AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0),
593 ("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
594 pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0),
595 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
596
597 iPaePDE++;
598 AssertFatal(iPaePDE < 512);
599
600 AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1),
601 ("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
602 pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1),
603 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
604
605 AssertMsg(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING,
606 ("%RX64; iPdpt=%#x iPDE=%#x iPaePDE=%#x %RGv %s\n",
607 pShwPdpt->a[iPdpt].u,
608 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
609
610 PCPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
611 AssertFatal(pPoolPagePd);
612 AssertMsg(pPoolPagePd->cLocked, (".idx=%d .type=%d\n", pPoolPagePd->idx, pPoolPagePd->enmKind));
613 break;
614 }
615
616 default:
617 AssertFailed();
618 break;
619 }
620 }
621}
622
623
624/**
625 * Check the hypervisor mappings in the active CR3.
626 *
627 * Ignored if mappings are disabled (i.e. if HM is enabled).
628 *
629 * @param pVM The cross context VM structure.
630 */
631VMMDECL(void) PGMMapCheck(PVM pVM)
632{
633 /*
634 * Can skip this if mappings are disabled.
635 */
636 if (!pgmMapAreMappingsEnabled(pVM))
637 return;
638
639 /* This only applies to raw mode where we only support 1 VCPU. */
640 Assert(pVM->cCpus == 1);
641 PVMCPU pVCpu = VMMGetCpu0(pVM);
642 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
643
644 /*
645 * Iterate mappings.
646 */
647 pgmLock(pVM); /* to avoid assertions */
648 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
649 {
650 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
651 pgmMapCheckShadowPDEs(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
652 }
653 pgmUnlock(pVM);
654}
655
656
657# endif /* defined(VBOX_STRICT) && !defined(IN_RING0) */
658
659/**
660 * Apply the hypervisor mappings to the active CR3.
661 *
662 * Ignored if mappings are disabled (i.e. if HM is enabled).
663 *
664 * @returns VBox status code.
665 * @param pVM The cross context VM structure.
666 * @param pShwPageCR3 CR3 root page
667 */
668int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
669{
670 RT_NOREF_PV(pShwPageCR3);
671
672 /*
673 * Skip this if it doesn't apply.
674 */
675 if (!pgmMapAreMappingsEnabled(pVM))
676 return VINF_SUCCESS;
677
678 /* Note! This might not be logged successfully in RC because we usually
679 cannot flush the log at this point. */
680 Log4(("pgmMapActivateCR3: fixed mappings=%RTbool idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
681
682# ifdef VBOX_STRICT
683 PVMCPU pVCpu = VMMGetCpu0(pVM);
684 Assert(pShwPageCR3 && pShwPageCR3 == pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
685# endif
686
687 /*
688 * Iterate mappings.
689 */
690 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
691 {
692 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
693 pgmMapSetShadowPDEs(pVM, pCur, iPDE);
694 }
695 return VINF_SUCCESS;
696}
697
698
699/**
700 * Remove the hypervisor mappings from the specified CR3
701 *
702 * Ignored if mappings are disabled (i.e. if HM is enabled).
703 *
704 * @returns VBox status code.
705 * @param pVM The cross context VM structure.
706 * @param pShwPageCR3 CR3 root page
707 */
708int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
709{
710 /*
711 * Skip this if it doesn't apply.
712 */
713 if (!pgmMapAreMappingsEnabled(pVM))
714 return VINF_SUCCESS;
715
716 Assert(pShwPageCR3);
717 Log4(("pgmMapDeactivateCR3: fixed mappings=%d idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
718
719 /*
720 * Iterate mappings.
721 */
722 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
723 {
724 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
725 pgmMapClearShadowPDEs(pVM, pShwPageCR3, pCur, iPDE, true /*fDeactivateCR3*/);
726 }
727 return VINF_SUCCESS;
728}
729
730
731/**
732 * Checks guest PD for conflicts with VMM GC mappings.
733 *
734 * @returns true if conflict detected.
735 * @returns false if not.
736 * @param pVM The cross context VM structure.
737 */
738VMMDECL(bool) PGMMapHasConflicts(PVM pVM)
739{
740 /*
741 * Can skip this if mappings are safely fixed.
742 */
743 if (!pgmMapAreMappingsFloating(pVM))
744 return false;
745 AssertReturn(pgmMapAreMappingsEnabled(pVM), false);
746
747 /* This only applies to raw mode where we only support 1 VCPU. */
748 PVMCPU pVCpu = &VMCC_GET_CPU_0(pVM);
749
750 PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
751 Assert(enmGuestMode <= PGMMODE_PAE_NX);
752
753 /*
754 * Iterate mappings.
755 */
756 if (enmGuestMode == PGMMODE_32_BIT)
757 {
758 /*
759 * Resolve the page directory.
760 */
761 PX86PD pPD = pgmGstGet32bitPDPtr(pVCpu);
762 Assert(pPD);
763
764 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
765 {
766 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
767 unsigned iPT = pCur->cPTs;
768 while (iPT-- > 0)
769 if (pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */)
770 {
771 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
772
773# ifdef IN_RING3
774 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
775 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
776 (iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
777 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
778# else
779 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
780 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
781 (iPT + iPDE) << X86_PD_SHIFT,
782 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
783# endif
784 return true;
785 }
786 }
787 }
788 else if ( enmGuestMode == PGMMODE_PAE
789 || enmGuestMode == PGMMODE_PAE_NX)
790 {
791 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
792 {
793 RTGCPTR GCPtr = pCur->GCPtr;
794
795 unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
796 while (iPT-- > 0)
797 {
798 X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
799
800 if (Pde.n.u1Present)
801 {
802 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
803# ifdef IN_RING3
804 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
805 " PDE=%016RX64.\n",
806 GCPtr, pCur->pszDesc, Pde.u));
807# else
808 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
809 " PDE=%016RX64.\n",
810 GCPtr, Pde.u));
811# endif
812 return true;
813 }
814 GCPtr += (1 << X86_PD_PAE_SHIFT);
815 }
816 }
817 }
818 else
819 AssertFailed();
820
821 return false;
822}
823
824
825/**
826 * Checks and resolves (ring 3 only) guest conflicts with the guest mappings.
827 *
828 * @returns VBox status code.
829 * @param pVM The cross context VM structure.
830 */
831int pgmMapResolveConflicts(PVM pVM)
832{
833 /* The caller is expected to check these two conditions. */
834 Assert(!pVM->pgm.s.fMappingsFixed);
835 Assert(pgmMapAreMappingsEnabled(pVM));
836
837 /* This only applies to raw mode where we only support 1 VCPU. */
838 Assert(pVM->cCpus == 1);
839 PVMCPU pVCpu = &VMCC_GET_CPU_0(pVM);
840 PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
841 Assert(enmGuestMode <= PGMMODE_PAE_NX);
842
843 if (enmGuestMode == PGMMODE_32_BIT)
844 {
845 /*
846 * Resolve the page directory.
847 */
848 PX86PD pPD = pgmGstGet32bitPDPtr(pVCpu);
849 Assert(pPD);
850
851 /*
852 * Iterate mappings.
853 */
854 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; )
855 {
856 PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
857 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
858 unsigned iPT = pCur->cPTs;
859 while (iPT-- > 0)
860 {
861 if (pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */)
862 {
863 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
864
865# ifdef IN_RING3
866 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
867 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
868 (iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
869 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
870 int rc = pgmR3SyncPTResolveConflict(pVM, pCur, pPD, iPDE << X86_PD_SHIFT);
871 AssertRCReturn(rc, rc);
872 break;
873# else
874 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
875 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
876 (iPT + iPDE) << X86_PD_SHIFT,
877 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
878 return VINF_PGM_SYNC_CR3;
879# endif
880 }
881 }
882 pCur = pNext;
883 }
884 }
885 else if ( enmGuestMode == PGMMODE_PAE
886 || enmGuestMode == PGMMODE_PAE_NX)
887 {
888 /*
889 * Iterate mappings.
890 */
891 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur;)
892 {
893 PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
894 RTGCPTR GCPtr = pCur->GCPtr;
895 unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
896 while (iPT-- > 0)
897 {
898 X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
899
900 if (Pde.n.u1Present)
901 {
902 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
903# ifdef IN_RING3
904 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
905 " PDE=%016RX64.\n",
906 GCPtr, pCur->pszDesc, Pde.u));
907 int rc = pgmR3SyncPTResolveConflictPAE(pVM, pCur, pCur->GCPtr);
908 AssertRCReturn(rc, rc);
909 break;
910# else
911 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
912 " PDE=%016RX64.\n",
913 GCPtr, Pde.u));
914 return VINF_PGM_SYNC_CR3;
915# endif
916 }
917 GCPtr += (1 << X86_PD_PAE_SHIFT);
918 }
919 pCur = pNext;
920 }
921 }
922 else
923 AssertFailed();
924
925 Assert(!PGMMapHasConflicts(pVM));
926 return VINF_SUCCESS;
927}
928
929#endif /* !PGM_WITHOUT_MAPPINGS */
930
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