[92186] | 1 | /* $Id: PGMAllGstSlatEpt.cpp.h 96737 2022-09-14 12:05:19Z vboxsync $ */
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| 2 | /** @file
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| 3 | * VBox - Page Manager, Guest EPT SLAT - All context code.
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| 4 | */
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| 5 |
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| 6 | /*
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[96407] | 7 | * Copyright (C) 2021-2022 Oracle and/or its affiliates.
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[92186] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[92186] | 26 | */
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| 27 |
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[96737] | 28 | #if PGM_SLAT_TYPE != PGM_SLAT_TYPE_EPT
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| 29 | # error "Unsupported SLAT type."
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| 30 | #endif
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| 31 |
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[92480] | 32 | DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(PCVMCPUCC pVCpu, uint64_t uEntry)
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| 33 | {
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[93459] | 34 | if (!(uEntry & EPT_E_READ))
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[92480] | 35 | {
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| 36 | Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
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[93922] | 37 | Assert(!RT_BF_GET(pVCpu->pgm.s.uEptVpidCapMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY));
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| 38 | NOREF(pVCpu);
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| 39 | if (uEntry & (EPT_E_WRITE | EPT_E_EXECUTE))
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[92480] | 40 | return false;
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| 41 | }
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| 42 | return true;
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| 43 | }
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| 44 |
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| 45 |
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| 46 | DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(uint64_t uEntry, uint8_t uLevel)
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| 47 | {
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[93539] | 48 | Assert(uLevel <= 3 && uLevel >= 1); NOREF(uLevel);
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[93922] | 49 | uint8_t const fEptMemTypeMask = uEntry & VMX_BF_EPT_PT_MEMTYPE_MASK;
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| 50 | switch (fEptMemTypeMask)
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| 51 | {
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| 52 | case EPT_E_MEMTYPE_WB:
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| 53 | case EPT_E_MEMTYPE_UC:
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| 54 | case EPT_E_MEMTYPE_WP:
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| 55 | case EPT_E_MEMTYPE_WT:
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| 56 | case EPT_E_MEMTYPE_WC:
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| 57 | return true;
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| 58 | }
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| 59 | return false;
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[92480] | 60 | }
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| 61 |
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| 62 |
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[92476] | 63 | DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(PCVMCPUCC pVCpu, PPGMPTWALK pWalk, uint64_t uEntry, uint8_t uLevel)
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[92186] | 64 | {
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[92685] | 65 | static PGMWALKFAIL const s_afEptViolations[] = { PGM_WALKFAIL_EPT_VIOLATION, PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE };
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[92472] | 66 | uint8_t const fEptVeSupported = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxEptXcptVe;
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[93459] | 67 | uint8_t const fConvertible = RT_BOOL(uLevel == 1 || (uEntry & EPT_E_BIT_LEAF));
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| 68 | uint8_t const idxViolationType = fEptVeSupported & fConvertible & !RT_BF_GET(uEntry, VMX_BF_EPT_PT_SUPPRESS_VE);
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[92476] | 69 |
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| 70 | pWalk->fNotPresent = true;
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| 71 | pWalk->uLevel = uLevel;
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[93459] | 72 | pWalk->fFailed = s_afEptViolations[idxViolationType];
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[92186] | 73 | return VERR_PAGE_TABLE_NOT_PRESENT;
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| 74 | }
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| 75 |
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| 76 |
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[92476] | 77 | DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(PCVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel, int rc)
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[92186] | 78 | {
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| 79 | AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
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[92472] | 80 | pWalk->fBadPhysAddr = true;
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| 81 | pWalk->uLevel = uLevel;
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[93459] | 82 | pWalk->fFailed = PGM_WALKFAIL_EPT_VIOLATION;
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[92186] | 83 | return VERR_PAGE_TABLE_NOT_PRESENT;
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| 84 | }
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| 85 |
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| 86 |
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[93459] | 87 | DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel)
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[92186] | 88 | {
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[93459] | 89 | NOREF(pVCpu);
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| 90 | pWalk->fRsvdError = true;
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| 91 | pWalk->uLevel = uLevel;
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| 92 | pWalk->fFailed = PGM_WALKFAIL_EPT_MISCONFIG;
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[92186] | 93 | return VERR_PAGE_TABLE_NOT_PRESENT;
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| 94 | }
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| 95 |
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| 96 |
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[92685] | 97 | /**
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[96737] | 98 | * Walks the guest's EPT page table (second-level address translation).
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[92685] | 99 | *
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| 100 | * @returns VBox status code.
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| 101 | * @retval VINF_SUCCESS on success.
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| 102 | * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
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| 103 | *
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| 104 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
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| 105 | * @param GCPhysNested The nested-guest physical address to walk.
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| 106 | * @param fIsLinearAddrValid Whether the linear-address in @c GCPtrNested caused
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[93922] | 107 | * this page walk.
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[92685] | 108 | * @param GCPtrNested The nested-guest linear address that caused this
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[93922] | 109 | * page walk. If @c fIsLinearAddrValid is false, pass
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| 110 | * 0.
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[92685] | 111 | * @param pWalk The page walk info.
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[96737] | 112 | * @param pSlatWalk The SLAT mode specific page walk info.
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[92685] | 113 | */
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[92186] | 114 | DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(Walk)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested,
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[96737] | 115 | PPGMPTWALK pWalk, PSLATPTWALK pSlatWalk)
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[92186] | 116 | {
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[92685] | 117 | Assert(fIsLinearAddrValid || GCPtrNested == 0);
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| 118 |
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[92311] | 119 | /*
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[92426] | 120 | * Init walk structures.
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[92311] | 121 | */
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[92186] | 122 | RT_ZERO(*pWalk);
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[96737] | 123 | RT_ZERO(*pSlatWalk);
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[92186] | 124 |
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[92426] | 125 | pWalk->GCPtr = GCPtrNested;
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| 126 | pWalk->GCPhysNested = GCPhysNested;
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| 127 | pWalk->fIsLinearAddrValid = fIsLinearAddrValid;
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| 128 | pWalk->fIsSlat = true;
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| 129 |
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[92311] | 130 | /*
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| 131 | * Figure out EPT attributes that are cumulative (logical-AND) across page walks.
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| 132 | * - R, W, X_SUPER are unconditionally cumulative.
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| 133 | * See Intel spec. Table 26-7 "Exit Qualification for EPT Violations".
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| 134 | *
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[92541] | 135 | * - X_USER is cumulative but relevant only when mode-based execute control for EPT
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[92311] | 136 | * which we currently don't support it (asserted below).
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| 137 | *
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| 138 | * - MEMTYPE is not cumulative and only applicable to the final paging entry.
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| 139 | *
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| 140 | * - A, D EPT bits map to the regular page-table bit positions. Thus, they're not
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| 141 | * included in the mask below and handled separately. Accessed bits are
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| 142 | * cumulative but dirty bits are not cumulative as they're only applicable to
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| 143 | * the final paging entry.
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| 144 | */
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| 145 | Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
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[96737] | 146 | uint64_t const fEptAndMask = ( PGM_PTATTRS_EPT_R_MASK
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| 147 | | PGM_PTATTRS_EPT_W_MASK
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| 148 | | PGM_PTATTRS_EPT_X_SUPER_MASK) & PGM_PTATTRS_EPT_MASK;
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[92311] | 149 |
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| 150 | /*
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| 151 | * Do the walk.
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| 152 | */
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[92257] | 153 | uint64_t fEffective;
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[92186] | 154 | {
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[92480] | 155 | /*
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[93459] | 156 | * EPTP.
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[92481] | 157 | *
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[93459] | 158 | * We currently only support 4-level EPT paging.
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| 159 | * EPT 5-level paging was documented at some point (bit 7 of MSR_IA32_VMX_EPT_VPID_CAP)
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[92481] | 160 | * but for some reason seems to have been removed from subsequent specs.
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| 161 | */
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[96737] | 162 | int const rc = pgmGstGetEptPML4PtrEx(pVCpu, &pSlatWalk->pPml4);
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[92481] | 163 | if (RT_SUCCESS(rc))
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| 164 | { /* likely */ }
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[96737] | 165 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
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[92481] | 166 | }
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| 167 | {
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| 168 | /*
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[92480] | 169 | * PML4E.
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| 170 | */
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[92186] | 171 | PEPTPML4E pPml4e;
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[96737] | 172 | pSlatWalk->pPml4e = pPml4e = &pSlatWalk->pPml4->a[(GCPhysNested >> SLAT_PML4_SHIFT) & SLAT_PML4_MASK];
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[92186] | 173 | EPTPML4E Pml4e;
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[96737] | 174 | pSlatWalk->Pml4e.u = Pml4e.u = pPml4e->u;
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[92186] | 175 |
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[96737] | 176 | if (SLAT_IS_PGENTRY_PRESENT(pVCpu, Pml4e)) { /* probable */ }
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[92472] | 177 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pml4e.u, 4);
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[92186] | 178 |
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[96737] | 179 | if (RT_LIKELY( SLAT_IS_PML4E_VALID(pVCpu, Pml4e)
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[93459] | 180 | && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pml4e.u)))
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| 181 | { /* likely */ }
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| 182 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 4);
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[92186] | 183 |
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[96737] | 184 | uint64_t const fEptAttrs = Pml4e.u & EPT_PML4E_ATTR_MASK;
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| 185 | uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
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| 186 | uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
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| 187 | uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
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| 188 | uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
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| 189 | uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
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[94982] | 190 | fEffective = RT_BF_MAKE(PGM_PTATTRS_R, fRead)
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| 191 | | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
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| 192 | | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
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| 193 | | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
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[96737] | 194 | | fEptAndBits;
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[92426] | 195 | pWalk->fEffective = fEffective;
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[92186] | 196 |
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[96737] | 197 | int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & EPT_PML4E_PG_MASK, &pSlatWalk->pPdpt);
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[92186] | 198 | if (RT_SUCCESS(rc)) { /* probable */ }
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| 199 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
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| 200 | }
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| 201 | {
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[92480] | 202 | /*
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| 203 | * PDPTE.
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| 204 | */
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[92186] | 205 | PEPTPDPTE pPdpte;
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[96737] | 206 | pSlatWalk->pPdpte = pPdpte = &pSlatWalk->pPdpt->a[(GCPhysNested >> SLAT_PDPT_SHIFT) & SLAT_PDPT_MASK];
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[92186] | 207 | EPTPDPTE Pdpte;
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[96737] | 208 | pSlatWalk->Pdpte.u = Pdpte.u = pPdpte->u;
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[92186] | 209 |
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[96737] | 210 | if (SLAT_IS_PGENTRY_PRESENT(pVCpu, Pdpte)) { /* probable */ }
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[92472] | 211 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pdpte.u, 3);
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[92186] | 212 |
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[93459] | 213 | /* The order of the following "if" and "else if" statements matter. */
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[96737] | 214 | if ( SLAT_IS_PDPE_VALID(pVCpu, Pdpte)
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[93459] | 215 | && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pdpte.u))
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[92186] | 216 | {
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[96737] | 217 | uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE_ATTR_MASK;
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| 218 | uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
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| 219 | uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
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| 220 | uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
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| 221 | uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
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| 222 | uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
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[94982] | 223 | fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
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| 224 | | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
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| 225 | | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
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| 226 | | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
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[96737] | 227 | | fEptAndBits;
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[92426] | 228 | pWalk->fEffective = fEffective;
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[92186] | 229 | }
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[96737] | 230 | else if ( SLAT_IS_BIG_PDPE_VALID(pVCpu, Pdpte)
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[93459] | 231 | && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pdpte.u)
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[92480] | 232 | && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pdpte.u, 3))
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[92186] | 233 | {
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[96737] | 234 | uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE1G_ATTR_MASK;
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| 235 | uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
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| 236 | uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
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| 237 | uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
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| 238 | uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
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| 239 | uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
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| 240 | uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
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| 241 | uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
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[92333] | 242 | fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
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| 243 | | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
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[94982] | 244 | | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
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[92333] | 245 | | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
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[96737] | 246 | | fEptAndBits;
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[92311] | 247 | fEffective |= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
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[92333] | 248 | | RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
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[92426] | 249 | pWalk->fEffective = fEffective;
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[92311] | 250 |
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[96737] | 251 | pWalk->fGigantPage = true;
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| 252 | pWalk->fSucceeded = true;
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| 253 | pWalk->GCPhys = SLAT_GET_PDPE1G_GCPHYS(pVCpu, Pdpte)
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| 254 | | (GCPhysNested & SLAT_PAGE_1G_OFFSET_MASK);
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[92426] | 255 | PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
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[92186] | 256 | return VINF_SUCCESS;
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| 257 | }
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[93459] | 258 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 3);
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[92480] | 259 |
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[96737] | 260 | int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpte.u & EPT_PDPTE_PG_MASK, &pSlatWalk->pPd);
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[92480] | 261 | if (RT_SUCCESS(rc)) { /* probable */ }
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| 262 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
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[92186] | 263 | }
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| 264 | {
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[92480] | 265 | /*
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| 266 | * PDE.
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| 267 | */
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[96737] | 268 | PSLATPDE pPde;
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| 269 | pSlatWalk->pPde = pPde = &pSlatWalk->pPd->a[(GCPhysNested >> SLAT_PD_SHIFT) & SLAT_PD_MASK];
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| 270 | SLATPDE Pde;
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| 271 | pSlatWalk->Pde.u = Pde.u = pPde->u;
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[92426] | 272 |
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[96737] | 273 | if (SLAT_IS_PGENTRY_PRESENT(pVCpu, Pde)) { /* probable */ }
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[92472] | 274 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pde.u, 2);
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[92426] | 275 |
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[93459] | 276 | /* The order of the following "if" and "else if" statements matter. */
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[96737] | 277 | if ( SLAT_IS_PDE_VALID(pVCpu, Pde)
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[93459] | 278 | && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pde.u))
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[92186] | 279 | {
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[96737] | 280 | uint64_t const fEptAttrs = Pde.u & EPT_PDE_ATTR_MASK;
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| 281 | uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
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| 282 | uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
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| 283 | uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
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| 284 | uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
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| 285 | uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
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[94982] | 286 | fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
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| 287 | | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
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| 288 | | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
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| 289 | | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
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[96737] | 290 | | fEptAndBits;
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[92480] | 291 | pWalk->fEffective = fEffective;
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| 292 | }
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[96737] | 293 | else if ( SLAT_IS_BIG_PDE_VALID(pVCpu, Pde)
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[93459] | 294 | && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pde.u)
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[92480] | 295 | && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pde.u, 2))
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| 296 | {
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[96737] | 297 | uint64_t const fEptAttrs = Pde.u & EPT_PDE2M_ATTR_MASK;
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| 298 | uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
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| 299 | uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
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| 300 | uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
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| 301 | uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
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| 302 | uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
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| 303 | uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
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| 304 | uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
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[92333] | 305 | fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
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| 306 | | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
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[94982] | 307 | | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
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[92333] | 308 | | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
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[96737] | 309 | | fEptAndBits;
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[92311] | 310 | fEffective |= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
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[92333] | 311 | | RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
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[92426] | 312 | pWalk->fEffective = fEffective;
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[92333] | 313 |
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[96737] | 314 | pWalk->fBigPage = true;
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| 315 | pWalk->fSucceeded = true;
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| 316 | pWalk->GCPhys = SLAT_GET_PDE2M_GCPHYS(pVCpu, Pde)
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| 317 | | (GCPhysNested & SLAT_PAGE_2M_OFFSET_MASK);
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[92426] | 318 | PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
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[92186] | 319 | return VINF_SUCCESS;
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| 320 | }
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[93459] | 321 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 2);
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[92186] | 322 |
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[96737] | 323 | int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pde.u & EPT_PDE_PG_MASK, &pSlatWalk->pPt);
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[92186] | 324 | if (RT_SUCCESS(rc)) { /* probable */ }
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| 325 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
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| 326 | }
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| 327 | {
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[92480] | 328 | /*
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| 329 | * PTE.
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| 330 | */
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[96737] | 331 | PSLATPTE pPte;
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| 332 | pSlatWalk->pPte = pPte = &pSlatWalk->pPt->a[(GCPhysNested >> SLAT_PT_SHIFT) & SLAT_PT_MASK];
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| 333 | SLATPTE Pte;
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| 334 | pSlatWalk->Pte.u = Pte.u = pPte->u;
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[92186] | 335 |
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[96737] | 336 | if (SLAT_IS_PGENTRY_PRESENT(pVCpu, Pte)) { /* probable */ }
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[92472] | 337 | else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pte.u, 1);
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[92186] | 338 |
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[96737] | 339 | if ( SLAT_IS_PTE_VALID(pVCpu, Pte)
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[93459] | 340 | && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pte.u)
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[92480] | 341 | && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pte.u, 1))
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[93459] | 342 | { /* likely*/ }
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[92480] | 343 | else
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[93459] | 344 | return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 1);
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[92186] | 345 |
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[96737] | 346 | uint64_t const fEptAttrs = Pte.u & EPT_PTE_ATTR_MASK;
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| 347 | uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
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| 348 | uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
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| 349 | uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
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| 350 | uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
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| 351 | uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
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| 352 | uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
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| 353 | uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
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[92333] | 354 | fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
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| 355 | | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
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[94982] | 356 | | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
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[92333] | 357 | | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
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[96737] | 358 | | fEptAndBits;
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[92311] | 359 | fEffective |= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
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[92333] | 360 | | RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
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[92426] | 361 | pWalk->fEffective = fEffective;
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[92311] | 362 |
|
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[92426] | 363 | pWalk->fSucceeded = true;
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[96737] | 364 | pWalk->GCPhys = SLAT_GET_PTE_GCPHYS(pVCpu, Pte) | (GCPhysNested & GUEST_PAGE_OFFSET_MASK);
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[92186] | 365 | return VINF_SUCCESS;
|
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| 366 | }
|
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| 367 | }
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| 368 |
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