[23] | 1 | /* $Id: PGMAllGst.h 98103 2023-01-17 14:15:46Z vboxsync $ */
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[1] | 2 | /** @file
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| 3 | * VBox - Page Manager, Guest Paging Template - All context code.
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| 4 | */
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| 5 |
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| 6 | /*
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[98103] | 7 | * Copyright (C) 2006-2023 Oracle and/or its affiliates.
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[1] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[1] | 26 | */
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| 27 |
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| 28 |
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[73272] | 29 | /*********************************************************************************************************************************
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| 30 | * Internal Functions *
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| 31 | *********************************************************************************************************************************/
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[20374] | 32 | RT_C_DECLS_BEGIN
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[96740] | 33 | /** @todo Do we really need any of these forward declarations? */
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[30889] | 34 | #if PGM_GST_TYPE == PGM_TYPE_32BIT \
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| 35 | || PGM_GST_TYPE == PGM_TYPE_PAE \
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| 36 | || PGM_GST_TYPE == PGM_TYPE_AMD64
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[92426] | 37 | DECLINLINE(int) PGM_GST_NAME(Walk)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PGSTPTWALK pGstWalk);
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[30889] | 38 | #endif
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[96740] | 39 | PGM_GST_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
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[92426] | 40 | PGM_GST_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk);
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[80268] | 41 | PGM_GST_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
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[96740] | 42 | PGM_GST_DECL(int, Exit)(PVMCPUCC pVCpu);
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[73199] | 43 |
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| 44 | #ifdef IN_RING3 /* r3 only for now. */
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[80268] | 45 | PGM_GST_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
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[73199] | 46 | #endif
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[20374] | 47 | RT_C_DECLS_END
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[1] | 48 |
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| 49 |
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[73261] | 50 | /**
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| 51 | * Enters the guest mode.
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| 52 | *
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| 53 | * @returns VBox status code.
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| 54 | * @param pVCpu The cross context virtual CPU structure.
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| 55 | * @param GCPhysCR3 The physical address from the CR3 register.
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| 56 | */
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[80268] | 57 | PGM_GST_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
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[73261] | 58 | {
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| 59 | /*
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| 60 | * Map and monitor CR3
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| 61 | */
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| 62 | uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
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| 63 | AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
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| 64 | AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
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[92626] | 65 | return g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
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[73261] | 66 | }
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| 67 |
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| 68 |
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| 69 | /**
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| 70 | * Exits the guest mode.
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| 71 | *
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| 72 | * @returns VBox status code.
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| 73 | * @param pVCpu The cross context virtual CPU structure.
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| 74 | */
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[80268] | 75 | PGM_GST_DECL(int, Exit)(PVMCPUCC pVCpu)
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[73261] | 76 | {
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| 77 | uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
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| 78 | AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
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| 79 | AssertReturn(g_aPgmBothModeData[idxBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
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| 80 | return g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
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| 81 | }
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| 82 |
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| 83 |
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[30889] | 84 | #if PGM_GST_TYPE == PGM_TYPE_32BIT \
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| 85 | || PGM_GST_TYPE == PGM_TYPE_PAE \
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| 86 | || PGM_GST_TYPE == PGM_TYPE_AMD64
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[1] | 87 |
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[30889] | 88 |
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[92426] | 89 | DECLINLINE(int) PGM_GST_NAME(WalkReturnNotPresent)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, int iLevel)
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[30889] | 90 | {
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[39078] | 91 | NOREF(iLevel); NOREF(pVCpu);
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[92426] | 92 | pWalk->fNotPresent = true;
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| 93 | pWalk->uLevel = (uint8_t)iLevel;
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[30889] | 94 | return VERR_PAGE_TABLE_NOT_PRESENT;
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| 95 | }
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| 96 |
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[92426] | 97 | DECLINLINE(int) PGM_GST_NAME(WalkReturnBadPhysAddr)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, int iLevel, int rc)
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[30889] | 98 | {
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[39078] | 99 | AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
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[92426] | 100 | pWalk->fBadPhysAddr = true;
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| 101 | pWalk->uLevel = (uint8_t)iLevel;
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[30889] | 102 | return VERR_PAGE_TABLE_NOT_PRESENT;
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| 103 | }
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| 104 |
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[92426] | 105 | DECLINLINE(int) PGM_GST_NAME(WalkReturnRsvdError)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, int iLevel)
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[30889] | 106 | {
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[39078] | 107 | NOREF(pVCpu);
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[92426] | 108 | pWalk->fRsvdError = true;
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| 109 | pWalk->uLevel = (uint8_t)iLevel;
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[30889] | 110 | return VERR_PAGE_TABLE_NOT_PRESENT;
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| 111 | }
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| 112 |
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| 113 |
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[1] | 114 | /**
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[30889] | 115 | * Performs a guest page table walk.
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| 116 | *
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| 117 | * @returns VBox status code.
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| 118 | * @retval VINF_SUCCESS on success.
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| 119 | * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
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| 120 | *
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[58123] | 121 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
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[30889] | 122 | * @param GCPtr The guest virtual address to walk by.
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[92684] | 123 | * @param pWalk The page walk info.
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| 124 | * @param pGstWalk The guest mode specific page walk info.
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[30889] | 125 | */
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[92426] | 126 | DECLINLINE(int) PGM_GST_NAME(Walk)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PGSTPTWALK pGstWalk)
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[30889] | 127 | {
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| 128 | int rc;
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| 129 |
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[92186] | 130 | #ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
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[92426] | 131 | /** @def PGM_GST_SLAT_WALK
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| 132 | * Macro to perform guest second-level address translation (EPT or Nested).
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| 133 | *
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[92459] | 134 | * @param a_pVCpu The cross context virtual CPU structure of the calling
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| 135 | * EMT.
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[92426] | 136 | * @param a_GCPtrNested The nested-guest linear address that caused the
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| 137 | * second-level translation.
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| 138 | * @param a_GCPhysNested The nested-guest physical address to translate.
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| 139 | * @param a_GCPhysOut Where to store the guest-physical address (result).
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| 140 | */
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[92186] | 141 | # define PGM_GST_SLAT_WALK(a_pVCpu, a_GCPtrNested, a_GCPhysNested, a_GCPhysOut, a_pWalk) \
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| 142 | do { \
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[93572] | 143 | if ((a_pVCpu)->pgm.s.enmGuestSlatMode == PGMSLAT_EPT) \
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[92186] | 144 | { \
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[96739] | 145 | PGMPTWALK WalkSlat; \
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| 146 | PGMPTWALKGST WalkGstSlat; \
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| 147 | int const rcX = pgmGstSlatWalk(a_pVCpu, a_GCPhysNested, true /* fIsLinearAddrValid */, a_GCPtrNested, &WalkSlat, \
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| 148 | &WalkGstSlat); \
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[92186] | 149 | if (RT_SUCCESS(rcX)) \
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[96739] | 150 | (a_GCPhysOut) = WalkSlat.GCPhys; \
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[92186] | 151 | else \
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| 152 | { \
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[96739] | 153 | *(a_pWalk) = WalkSlat; \
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[92186] | 154 | return rcX; \
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| 155 | } \
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| 156 | } \
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| 157 | } while (0)
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| 158 | #endif
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| 159 |
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[30889] | 160 | /*
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[92426] | 161 | * Init the walking structures.
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[30889] | 162 | */
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| 163 | RT_ZERO(*pWalk);
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[92426] | 164 | RT_ZERO(*pGstWalk);
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| 165 | pWalk->GCPtr = GCPtr;
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[30889] | 166 |
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| 167 | # if PGM_GST_TYPE == PGM_TYPE_32BIT \
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| 168 | || PGM_GST_TYPE == PGM_TYPE_PAE
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| 169 | /*
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| 170 | * Boundary check for PAE and 32-bit (prevents trouble further down).
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| 171 | */
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| 172 | if (RT_UNLIKELY(GCPtr >= _4G))
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| 173 | return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 8);
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| 174 | # endif
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| 175 |
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[92331] | 176 | uint64_t fEffective;
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[30889] | 177 | {
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| 178 | # if PGM_GST_TYPE == PGM_TYPE_AMD64
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| 179 | /*
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[92186] | 180 | * The PML4 table.
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[30889] | 181 | */
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[92426] | 182 | rc = pgmGstGetLongModePML4PtrEx(pVCpu, &pGstWalk->pPml4);
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[65531] | 183 | if (RT_SUCCESS(rc)) { /* probable */ }
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| 184 | else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
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[30889] | 185 |
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[85073] | 186 | PX86PML4E pPml4e;
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[92426] | 187 | pGstWalk->pPml4e = pPml4e = &pGstWalk->pPml4->a[(GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK];
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[85073] | 188 | X86PML4E Pml4e;
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[92426] | 189 | pGstWalk->Pml4e.u = Pml4e.u = pPml4e->u;
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[30889] | 190 |
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[92062] | 191 | if (GST_IS_PGENTRY_PRESENT(pVCpu, Pml4e)) { /* probable */ }
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[65531] | 192 | else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 4);
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| 193 |
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| 194 | if (RT_LIKELY(GST_IS_PML4E_VALID(pVCpu, Pml4e))) { /* likely */ }
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| 195 | else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 4);
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| 196 |
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[93160] | 197 | fEffective = Pml4e.u & ( X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_PWT | X86_PML4E_PCD | X86_PML4E_A
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| 198 | | X86_PML4E_NX);
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| 199 | pWalk->fEffective = fEffective;
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[65531] | 200 |
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[30889] | 201 | /*
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[92186] | 202 | * The PDPT.
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[30889] | 203 | */
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[92186] | 204 | RTGCPHYS GCPhysPdpt = Pml4e.u & X86_PML4E_PG_MASK;
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| 205 | #ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
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| 206 | PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPdpt, GCPhysPdpt, pWalk);
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| 207 | #endif
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[92426] | 208 | rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPdpt, &pGstWalk->pPdpt);
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[65531] | 209 | if (RT_SUCCESS(rc)) { /* probable */ }
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| 210 | else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
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[30889] | 211 |
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| 212 | # elif PGM_GST_TYPE == PGM_TYPE_PAE
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[92426] | 213 | rc = pgmGstGetPaePDPTPtrEx(pVCpu, &pGstWalk->pPdpt);
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[65531] | 214 | if (RT_SUCCESS(rc)) { /* probable */ }
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| 215 | else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
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[92186] | 216 | #endif
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[30889] | 217 | }
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| 218 | {
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| 219 | # if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
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[85073] | 220 | PX86PDPE pPdpe;
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[92426] | 221 | pGstWalk->pPdpe = pPdpe = &pGstWalk->pPdpt->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
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[85073] | 222 | X86PDPE Pdpe;
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[92426] | 223 | pGstWalk->Pdpe.u = Pdpe.u = pPdpe->u;
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[30889] | 224 |
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[92062] | 225 | if (GST_IS_PGENTRY_PRESENT(pVCpu, Pdpe)) { /* probable */ }
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[65531] | 226 | else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 3);
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| 227 |
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| 228 | if (RT_LIKELY(GST_IS_PDPE_VALID(pVCpu, Pdpe))) { /* likely */ }
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| 229 | else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 3);
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| 230 |
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| 231 | # if PGM_GST_TYPE == PGM_TYPE_AMD64
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[93160] | 232 | fEffective &= (Pdpe.u & ( X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US
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| 233 | | X86_PDPE_PWT | X86_PDPE_PCD | X86_PDPE_A));
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| 234 | fEffective |= Pdpe.u & X86_PDPE_LM_NX;
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[65531] | 235 | # else
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[93160] | 236 | /*
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| 237 | * NX in the legacy-mode PAE PDPE is reserved. The valid check above ensures the NX bit is not set.
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| 238 | * The RW, US, A bits MBZ in PAE PDPTE entries but must be 1 the way we compute cumulative (effective) access rights.
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| 239 | */
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| 240 | Assert(!(Pdpe.u & X86_PDPE_LM_NX));
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| 241 | fEffective = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A
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| 242 | | (Pdpe.u & (X86_PDPE_PWT | X86_PDPE_PCD));
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[65531] | 243 | # endif
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[93160] | 244 | pWalk->fEffective = fEffective;
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[65531] | 245 |
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[30889] | 246 | /*
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[92186] | 247 | * The PD.
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[30889] | 248 | */
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[92186] | 249 | RTGCPHYS GCPhysPd = Pdpe.u & X86_PDPE_PG_MASK;
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| 250 | # ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
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| 251 | PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPd, GCPhysPd, pWalk);
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| 252 | # endif
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[92426] | 253 | rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPd, &pGstWalk->pPd);
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[65531] | 254 | if (RT_SUCCESS(rc)) { /* probable */ }
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| 255 | else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 2, rc);
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[92186] | 256 |
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[30889] | 257 | # elif PGM_GST_TYPE == PGM_TYPE_32BIT
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[92426] | 258 | rc = pgmGstGet32bitPDPtrEx(pVCpu, &pGstWalk->pPd);
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[65531] | 259 | if (RT_SUCCESS(rc)) { /* probable */ }
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| 260 | else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
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[30889] | 261 | # endif
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| 262 | }
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| 263 | {
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[85073] | 264 | PGSTPDE pPde;
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[92426] | 265 | pGstWalk->pPde = pPde = &pGstWalk->pPd->a[(GCPtr >> GST_PD_SHIFT) & GST_PD_MASK];
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[85073] | 266 | GSTPDE Pde;
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[92426] | 267 | pGstWalk->Pde.u = Pde.u = pPde->u;
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[92062] | 268 | if (GST_IS_PGENTRY_PRESENT(pVCpu, Pde)) { /* probable */ }
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[65531] | 269 | else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 2);
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[86476] | 270 | if ((Pde.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
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[30889] | 271 | {
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[65531] | 272 | if (RT_LIKELY(GST_IS_BIG_PDE_VALID(pVCpu, Pde))) { /* likely */ }
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| 273 | else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
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[30889] | 274 |
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[65531] | 275 | /*
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| 276 | * We're done.
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| 277 | */
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[92186] | 278 | # if PGM_GST_TYPE == PGM_TYPE_32BIT
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[93160] | 279 | fEffective = Pde.u & (X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PWT | X86_PDE4M_PCD | X86_PDE4M_A);
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[92186] | 280 | # else
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[93160] | 281 | fEffective &= Pde.u & (X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PWT | X86_PDE4M_PCD | X86_PDE4M_A);
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| 282 | fEffective |= Pde.u & X86_PDE2M_PAE_NX;
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[92186] | 283 | # endif
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[92257] | 284 | fEffective |= Pde.u & (X86_PDE4M_D | X86_PDE4M_G);
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| 285 | fEffective |= (Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT;
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[92426] | 286 | pWalk->fEffective = fEffective;
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[92319] | 287 | Assert(GST_IS_NX_ACTIVE(pVCpu) || !(fEffective & PGM_PTATTRS_NX_MASK));
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[92331] | 288 | Assert(fEffective & PGM_PTATTRS_R_MASK);
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[92186] | 289 |
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[92426] | 290 | pWalk->fBigPage = true;
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| 291 | pWalk->fSucceeded = true;
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[92186] | 292 | RTGCPHYS GCPhysPde = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
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| 293 | | (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
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| 294 | # ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
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| 295 | PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPde, GCPhysPde, pWalk);
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| 296 | # endif
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[92426] | 297 | pWalk->GCPhys = GCPhysPde;
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| 298 | PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
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[30889] | 299 | return VINF_SUCCESS;
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| 300 | }
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| 301 |
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| 302 | if (RT_UNLIKELY(!GST_IS_PDE_VALID(pVCpu, Pde)))
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| 303 | return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
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[92186] | 304 | # if PGM_GST_TYPE == PGM_TYPE_32BIT
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[93160] | 305 | fEffective = Pde.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD | X86_PDE_A);
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[65531] | 306 | # else
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[93160] | 307 | fEffective &= Pde.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD | X86_PDE_A);
|
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| 308 | fEffective |= Pde.u & X86_PDE_PAE_NX;
|
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[65531] | 309 | # endif
|
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[93160] | 310 | pWalk->fEffective = fEffective;
|
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[30889] | 311 |
|
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| 312 | /*
|
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[92186] | 313 | * The PT.
|
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[30889] | 314 | */
|
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[92186] | 315 | RTGCPHYS GCPhysPt = GST_GET_PDE_GCPHYS(Pde);
|
---|
| 316 | # ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
|
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| 317 | PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPt, GCPhysPt, pWalk);
|
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| 318 | # endif
|
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[92426] | 319 | rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPt, &pGstWalk->pPt);
|
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[65531] | 320 | if (RT_SUCCESS(rc)) { /* probable */ }
|
---|
| 321 | else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
|
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[30889] | 322 | }
|
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| 323 | {
|
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[85073] | 324 | PGSTPTE pPte;
|
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[92426] | 325 | pGstWalk->pPte = pPte = &pGstWalk->pPt->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
|
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[85073] | 326 | GSTPTE Pte;
|
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[92426] | 327 | pGstWalk->Pte.u = Pte.u = pPte->u;
|
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[30889] | 328 |
|
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[92062] | 329 | if (GST_IS_PGENTRY_PRESENT(pVCpu, Pte)) { /* probable */ }
|
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[65531] | 330 | else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 1);
|
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| 331 |
|
---|
| 332 | if (RT_LIKELY(GST_IS_PTE_VALID(pVCpu, Pte))) { /* likely */ }
|
---|
| 333 | else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 1);
|
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| 334 |
|
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[30889] | 335 | /*
|
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| 336 | * We're done.
|
---|
| 337 | */
|
---|
[93160] | 338 | fEffective &= Pte.u & (X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A);
|
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| 339 | fEffective |= Pte.u & (X86_PTE_D | X86_PTE_PAT | X86_PTE_G);
|
---|
| 340 | # if PGM_GST_TYPE != PGM_TYPE_32BIT
|
---|
| 341 | fEffective |= Pte.u & X86_PTE_PAE_NX;
|
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[92186] | 342 | # endif
|
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[92426] | 343 | pWalk->fEffective = fEffective;
|
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[92319] | 344 | Assert(GST_IS_NX_ACTIVE(pVCpu) || !(fEffective & PGM_PTATTRS_NX_MASK));
|
---|
[92331] | 345 | Assert(fEffective & PGM_PTATTRS_R_MASK);
|
---|
[65531] | 346 |
|
---|
[92426] | 347 | pWalk->fSucceeded = true;
|
---|
[92311] | 348 | RTGCPHYS GCPhysPte = GST_GET_PTE_GCPHYS(Pte)
|
---|
[93554] | 349 | | (GCPtr & GUEST_PAGE_OFFSET_MASK);
|
---|
[92186] | 350 | # ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
|
---|
| 351 | PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPte, GCPhysPte, pWalk);
|
---|
| 352 | # endif
|
---|
[92426] | 353 | pWalk->GCPhys = GCPhysPte;
|
---|
[30889] | 354 | return VINF_SUCCESS;
|
---|
| 355 | }
|
---|
| 356 | }
|
---|
| 357 |
|
---|
[92186] | 358 | #endif /* 32BIT, PAE, AMD64 */
|
---|
[30889] | 359 |
|
---|
| 360 | /**
|
---|
[1] | 361 | * Gets effective Guest OS page information.
|
---|
| 362 | *
|
---|
| 363 | * When GCPtr is in a big page, the function will return as if it was a normal
|
---|
| 364 | * 4KB page. If the need for distinguishing between big and normal page becomes
|
---|
| 365 | * necessary at a later point, a PGMGstGetPage Ex() will be created for that
|
---|
| 366 | * purpose.
|
---|
| 367 | *
|
---|
[58170] | 368 | * @returns VBox status code.
|
---|
[58123] | 369 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[23853] | 370 | * @param GCPtr Guest Context virtual address of the page.
|
---|
[92426] | 371 | * @param pWalk Where to store the page walk info.
|
---|
[1] | 372 | */
|
---|
[92426] | 373 | PGM_GST_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk)
|
---|
[1] | 374 | {
|
---|
| 375 | #if PGM_GST_TYPE == PGM_TYPE_REAL \
|
---|
| 376 | || PGM_GST_TYPE == PGM_TYPE_PROT
|
---|
[93572] | 377 |
|
---|
| 378 | RT_ZERO(*pWalk);
|
---|
| 379 | # ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
|
---|
| 380 | if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
|
---|
| 381 | {
|
---|
[96739] | 382 | PGMPTWALK WalkSlat;
|
---|
| 383 | PGMPTWALKGST WalkGstSlat;
|
---|
| 384 | int const rc = pgmGstSlatWalk(pVCpu, GCPtr, true /* fIsLinearAddrValid */, GCPtr, &WalkSlat, &WalkGstSlat);
|
---|
[93572] | 385 | if (RT_SUCCESS(rc))
|
---|
| 386 | {
|
---|
| 387 | pWalk->fSucceeded = true;
|
---|
| 388 | pWalk->GCPtr = GCPtr;
|
---|
[96739] | 389 | pWalk->GCPhys = WalkSlat.GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
|
---|
[93572] | 390 | pWalk->fEffective = X86_PTE_P | X86_PTE_RW | X86_PTE_US;
|
---|
| 391 | }
|
---|
| 392 | else
|
---|
[96739] | 393 | *pWalk = WalkSlat;
|
---|
[93572] | 394 | return rc;
|
---|
| 395 | }
|
---|
| 396 | # endif
|
---|
| 397 |
|
---|
[1] | 398 | /*
|
---|
| 399 | * Fake it.
|
---|
| 400 | */
|
---|
[92426] | 401 | pWalk->fSucceeded = true;
|
---|
| 402 | pWalk->GCPtr = GCPtr;
|
---|
[93931] | 403 | pWalk->GCPhys = GCPtr & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
|
---|
[92426] | 404 | pWalk->fEffective = X86_PTE_P | X86_PTE_RW | X86_PTE_US;
|
---|
[39078] | 405 | NOREF(pVCpu);
|
---|
[1] | 406 | return VINF_SUCCESS;
|
---|
| 407 |
|
---|
[30889] | 408 | #elif PGM_GST_TYPE == PGM_TYPE_32BIT \
|
---|
| 409 | || PGM_GST_TYPE == PGM_TYPE_PAE \
|
---|
| 410 | || PGM_GST_TYPE == PGM_TYPE_AMD64
|
---|
[1] | 411 |
|
---|
[92426] | 412 | GSTPTWALK GstWalk;
|
---|
[92642] | 413 | int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, pWalk, &GstWalk);
|
---|
[30889] | 414 | if (RT_FAILURE(rc))
|
---|
| 415 | return rc;
|
---|
[24997] | 416 |
|
---|
[92642] | 417 | Assert(pWalk->fSucceeded);
|
---|
| 418 | Assert(pWalk->GCPtr == GCPtr);
|
---|
| 419 |
|
---|
| 420 | PGMPTATTRS fFlags;
|
---|
| 421 | if (!pWalk->fBigPage)
|
---|
[92426] | 422 | fFlags = (GstWalk.Pte.u & ~(GST_PTE_PG_MASK | X86_PTE_RW | X86_PTE_US)) /* NX not needed */
|
---|
[92642] | 423 | | (pWalk->fEffective & (PGM_PTATTRS_W_MASK | PGM_PTATTRS_US_MASK))
|
---|
[12932] | 424 | # if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
|
---|
[92642] | 425 | | (pWalk->fEffective & PGM_PTATTRS_NX_MASK)
|
---|
[7629] | 426 | # endif
|
---|
[92426] | 427 | ;
|
---|
| 428 | else
|
---|
| 429 | {
|
---|
| 430 | fFlags = (GstWalk.Pde.u & ~(GST_PTE_PG_MASK | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PS)) /* NX not needed */
|
---|
[92642] | 431 | | (pWalk->fEffective & (PGM_PTATTRS_W_MASK | PGM_PTATTRS_US_MASK | PGM_PTATTRS_PAT_MASK))
|
---|
[12932] | 432 | # if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
|
---|
[92642] | 433 | | (pWalk->fEffective & PGM_PTATTRS_NX_MASK)
|
---|
[7730] | 434 | # endif
|
---|
[92426] | 435 | ;
|
---|
[1] | 436 | }
|
---|
[30889] | 437 |
|
---|
[93554] | 438 | pWalk->GCPhys &= ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
|
---|
[92426] | 439 | pWalk->fEffective = fFlags;
|
---|
[1] | 440 | return VINF_SUCCESS;
|
---|
[30889] | 441 |
|
---|
[1] | 442 | #else
|
---|
[7733] | 443 | # error "shouldn't be here!"
|
---|
[1] | 444 | /* something else... */
|
---|
| 445 | return VERR_NOT_SUPPORTED;
|
---|
| 446 | #endif
|
---|
| 447 | }
|
---|
| 448 |
|
---|
| 449 |
|
---|
| 450 | /**
|
---|
| 451 | * Modify page flags for a range of pages in the guest's tables
|
---|
| 452 | *
|
---|
| 453 | * The existing flags are ANDed with the fMask and ORed with the fFlags.
|
---|
| 454 | *
|
---|
| 455 | * @returns VBox status code.
|
---|
[58123] | 456 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[1] | 457 | * @param GCPtr Virtual address of the first page in the range. Page aligned!
|
---|
| 458 | * @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
|
---|
| 459 | * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
|
---|
| 460 | * @param fMask The AND mask - page flags X86_PTE_*.
|
---|
| 461 | */
|
---|
[80268] | 462 | PGM_GST_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
|
---|
[1] | 463 | {
|
---|
[93554] | 464 | Assert((cb & GUEST_PAGE_OFFSET_MASK) == 0); RT_NOREF_PV(cb);
|
---|
[30889] | 465 |
|
---|
[1] | 466 | #if PGM_GST_TYPE == PGM_TYPE_32BIT \
|
---|
| 467 | || PGM_GST_TYPE == PGM_TYPE_PAE \
|
---|
| 468 | || PGM_GST_TYPE == PGM_TYPE_AMD64
|
---|
| 469 | for (;;)
|
---|
| 470 | {
|
---|
[92426] | 471 | PGMPTWALK Walk;
|
---|
| 472 | GSTPTWALK GstWalk;
|
---|
| 473 | int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk, &GstWalk);
|
---|
[30889] | 474 | if (RT_FAILURE(rc))
|
---|
| 475 | return rc;
|
---|
[13919] | 476 |
|
---|
[92426] | 477 | if (!Walk.fBigPage)
|
---|
[1] | 478 | {
|
---|
| 479 | /*
|
---|
[30889] | 480 | * 4KB Page table, process
|
---|
[1] | 481 | *
|
---|
[30889] | 482 | * Walk pages till we're done.
|
---|
[1] | 483 | */
|
---|
| 484 | unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
|
---|
[92426] | 485 | while (iPTE < RT_ELEMENTS(GstWalk.pPt->a))
|
---|
[1] | 486 | {
|
---|
[92426] | 487 | GSTPTE Pte = GstWalk.pPt->a[iPTE];
|
---|
[32036] | 488 | Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK))
|
---|
[1] | 489 | | (fFlags & ~GST_PTE_PG_MASK);
|
---|
[92426] | 490 | GstWalk.pPt->a[iPTE] = Pte;
|
---|
[1] | 491 |
|
---|
| 492 | /* next page */
|
---|
[93554] | 493 | cb -= GUEST_PAGE_SIZE;
|
---|
[1] | 494 | if (!cb)
|
---|
| 495 | return VINF_SUCCESS;
|
---|
[93554] | 496 | GCPtr += GUEST_PAGE_SIZE;
|
---|
[1] | 497 | iPTE++;
|
---|
| 498 | }
|
---|
| 499 | }
|
---|
| 500 | else
|
---|
| 501 | {
|
---|
| 502 | /*
|
---|
[31849] | 503 | * 2/4MB Page table
|
---|
[1] | 504 | */
|
---|
[30889] | 505 | GSTPDE PdeNew;
|
---|
[11531] | 506 | # if PGM_GST_TYPE == PGM_TYPE_32BIT
|
---|
[92426] | 507 | PdeNew.u = (GstWalk.Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PG_HIGH_MASK | X86_PDE4M_PS))
|
---|
[11531] | 508 | # else
|
---|
[92426] | 509 | PdeNew.u = (GstWalk.Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PS))
|
---|
[11531] | 510 | # endif
|
---|
[30889] | 511 | | (fFlags & ~GST_PTE_PG_MASK)
|
---|
| 512 | | ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
|
---|
[92426] | 513 | *GstWalk.pPde = PdeNew;
|
---|
[1] | 514 |
|
---|
| 515 | /* advance */
|
---|
| 516 | const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
|
---|
| 517 | if (cbDone >= cb)
|
---|
| 518 | return VINF_SUCCESS;
|
---|
| 519 | cb -= cbDone;
|
---|
| 520 | GCPtr += cbDone;
|
---|
| 521 | }
|
---|
| 522 | }
|
---|
| 523 |
|
---|
| 524 | #else
|
---|
[2227] | 525 | /* real / protected mode: ignore. */
|
---|
[39078] | 526 | NOREF(pVCpu); NOREF(GCPtr); NOREF(fFlags); NOREF(fMask);
|
---|
[2227] | 527 | return VINF_SUCCESS;
|
---|
[1] | 528 | #endif
|
---|
| 529 | }
|
---|
| 530 |
|
---|
| 531 |
|
---|
[73268] | 532 | #ifdef IN_RING3
|
---|
| 533 | /**
|
---|
| 534 | * Relocate any GC pointers related to guest mode paging.
|
---|
| 535 | *
|
---|
| 536 | * @returns VBox status code.
|
---|
| 537 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 538 | * @param offDelta The relocation offset.
|
---|
| 539 | */
|
---|
[80268] | 540 | PGM_GST_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta)
|
---|
[73268] | 541 | {
|
---|
[80181] | 542 | RT_NOREF(pVCpu, offDelta);
|
---|
[73268] | 543 | return VINF_SUCCESS;
|
---|
| 544 | }
|
---|
| 545 | #endif
|
---|