VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 96879

Last change on this file since 96879 was 96879, checked in by vboxsync, 20 months ago

VMM/PGM: Nested VMX: bugref:10092 Nested EPT shadow page-pool handling.
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File size: 146.9 KB
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1/* $Id: PGMAll.cpp 96879 2022-09-26 17:43:43Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_PGM
33#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
34#include <VBox/vmm/pgm.h>
35#include <VBox/vmm/cpum.h>
36#include <VBox/vmm/selm.h>
37#include <VBox/vmm/iem.h>
38#include <VBox/vmm/iom.h>
39#include <VBox/sup.h>
40#include <VBox/vmm/mm.h>
41#include <VBox/vmm/stam.h>
42#include <VBox/vmm/trpm.h>
43#include <VBox/vmm/em.h>
44#include <VBox/vmm/hm.h>
45#include <VBox/vmm/hm_vmx.h>
46#include "PGMInternal.h"
47#include <VBox/vmm/vmcc.h>
48#include "PGMInline.h"
49#include <iprt/assert.h>
50#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
51# include <iprt/asm-amd64-x86.h>
52#endif
53#include <iprt/string.h>
54#include <VBox/log.h>
55#include <VBox/param.h>
56#include <VBox/err.h>
57
58
59/*********************************************************************************************************************************
60* Internal Functions *
61*********************************************************************************************************************************/
62DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
63DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
64DECLINLINE(int) pgmGstMapCr3(PVMCPUCC pVCpu, RTGCPHYS GCPhysCr3, PRTHCPTR pHCPtrGuestCr3);
65#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
66static int pgmGstSlatWalk(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
67 PPGMPTWALKGST pGstWalk);
68static int pgmGstSlatWalkPhys(PVMCPUCC pVCpu, PGMSLAT enmSlatMode, RTGCPHYS GCPhysNested, PPGMPTWALK pWalk,
69 PPGMPTWALKGST pGstWalk);
70static int pgmGstSlatTranslateCr3(PVMCPUCC pVCpu, uint64_t uCr3, PRTGCPHYS pGCPhysCr3);
71static int pgmShwGetNestedEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPhysNested, PEPTPDPT *ppPdpt, PEPTPD *ppPD,
72 PPGMPTWALKGST pGstWalkAll);
73#endif
74static int pgmShwSyncLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
75static int pgmShwGetEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
76
77
78#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
79# define PGM_SLAT_TYPE PGM_SLAT_TYPE_EPT
80# include "PGMSlatDefs.h"
81# include "PGMAllGstSlatEpt.cpp.h"
82# undef PGM_SLAT_TYPE
83#endif
84
85
86/*
87 * Shadow - 32-bit mode
88 */
89#define PGM_SHW_TYPE PGM_TYPE_32BIT
90#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
91#include "PGMAllShw.h"
92
93/* Guest - real mode */
94#define PGM_GST_TYPE PGM_TYPE_REAL
95#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
96#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
97#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
98#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
99#include "PGMGstDefs.h"
100#include "PGMAllGst.h"
101#include "PGMAllBth.h"
102#undef BTH_PGMPOOLKIND_PT_FOR_PT
103#undef BTH_PGMPOOLKIND_ROOT
104#undef PGM_BTH_NAME
105#undef PGM_GST_TYPE
106#undef PGM_GST_NAME
107
108/* Guest - protected mode */
109#define PGM_GST_TYPE PGM_TYPE_PROT
110#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
111#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
112#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
113#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
114#include "PGMGstDefs.h"
115#include "PGMAllGst.h"
116#include "PGMAllBth.h"
117#undef BTH_PGMPOOLKIND_PT_FOR_PT
118#undef BTH_PGMPOOLKIND_ROOT
119#undef PGM_BTH_NAME
120#undef PGM_GST_TYPE
121#undef PGM_GST_NAME
122
123/* Guest - 32-bit mode */
124#define PGM_GST_TYPE PGM_TYPE_32BIT
125#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
126#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
127#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
128#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
129#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
130#include "PGMGstDefs.h"
131#include "PGMAllGst.h"
132#include "PGMAllBth.h"
133#undef BTH_PGMPOOLKIND_PT_FOR_BIG
134#undef BTH_PGMPOOLKIND_PT_FOR_PT
135#undef BTH_PGMPOOLKIND_ROOT
136#undef PGM_BTH_NAME
137#undef PGM_GST_TYPE
138#undef PGM_GST_NAME
139
140#undef PGM_SHW_TYPE
141#undef PGM_SHW_NAME
142
143
144/*
145 * Shadow - PAE mode
146 */
147#define PGM_SHW_TYPE PGM_TYPE_PAE
148#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
149#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
150#include "PGMAllShw.h"
151
152/* Guest - real mode */
153#define PGM_GST_TYPE PGM_TYPE_REAL
154#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
155#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
156#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
157#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
158#include "PGMGstDefs.h"
159#include "PGMAllBth.h"
160#undef BTH_PGMPOOLKIND_PT_FOR_PT
161#undef BTH_PGMPOOLKIND_ROOT
162#undef PGM_BTH_NAME
163#undef PGM_GST_TYPE
164#undef PGM_GST_NAME
165
166/* Guest - protected mode */
167#define PGM_GST_TYPE PGM_TYPE_PROT
168#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
169#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
170#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
171#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
172#include "PGMGstDefs.h"
173#include "PGMAllBth.h"
174#undef BTH_PGMPOOLKIND_PT_FOR_PT
175#undef BTH_PGMPOOLKIND_ROOT
176#undef PGM_BTH_NAME
177#undef PGM_GST_TYPE
178#undef PGM_GST_NAME
179
180/* Guest - 32-bit mode */
181#define PGM_GST_TYPE PGM_TYPE_32BIT
182#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
183#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
184#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
185#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
186#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
187#include "PGMGstDefs.h"
188#include "PGMAllBth.h"
189#undef BTH_PGMPOOLKIND_PT_FOR_BIG
190#undef BTH_PGMPOOLKIND_PT_FOR_PT
191#undef BTH_PGMPOOLKIND_ROOT
192#undef PGM_BTH_NAME
193#undef PGM_GST_TYPE
194#undef PGM_GST_NAME
195
196
197/* Guest - PAE mode */
198#define PGM_GST_TYPE PGM_TYPE_PAE
199#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
200#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
201#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
202#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
203#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
204#include "PGMGstDefs.h"
205#include "PGMAllGst.h"
206#include "PGMAllBth.h"
207#undef BTH_PGMPOOLKIND_PT_FOR_BIG
208#undef BTH_PGMPOOLKIND_PT_FOR_PT
209#undef BTH_PGMPOOLKIND_ROOT
210#undef PGM_BTH_NAME
211#undef PGM_GST_TYPE
212#undef PGM_GST_NAME
213
214#undef PGM_SHW_TYPE
215#undef PGM_SHW_NAME
216
217
218/*
219 * Shadow - AMD64 mode
220 */
221#define PGM_SHW_TYPE PGM_TYPE_AMD64
222#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
223#include "PGMAllShw.h"
224
225/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
226/** @todo retire this hack. */
227#define PGM_GST_TYPE PGM_TYPE_PROT
228#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
229#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
230#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
231#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
232#include "PGMGstDefs.h"
233#include "PGMAllBth.h"
234#undef BTH_PGMPOOLKIND_PT_FOR_PT
235#undef BTH_PGMPOOLKIND_ROOT
236#undef PGM_BTH_NAME
237#undef PGM_GST_TYPE
238#undef PGM_GST_NAME
239
240#ifdef VBOX_WITH_64_BITS_GUESTS
241/* Guest - AMD64 mode */
242# define PGM_GST_TYPE PGM_TYPE_AMD64
243# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
244# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
245# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
246# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
247# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
248# include "PGMGstDefs.h"
249# include "PGMAllGst.h"
250# include "PGMAllBth.h"
251# undef BTH_PGMPOOLKIND_PT_FOR_BIG
252# undef BTH_PGMPOOLKIND_PT_FOR_PT
253# undef BTH_PGMPOOLKIND_ROOT
254# undef PGM_BTH_NAME
255# undef PGM_GST_TYPE
256# undef PGM_GST_NAME
257#endif /* VBOX_WITH_64_BITS_GUESTS */
258
259#undef PGM_SHW_TYPE
260#undef PGM_SHW_NAME
261
262
263/*
264 * Shadow - 32-bit nested paging mode.
265 */
266#define PGM_SHW_TYPE PGM_TYPE_NESTED_32BIT
267#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_32BIT(name)
268#include "PGMAllShw.h"
269
270/* Guest - real mode */
271#define PGM_GST_TYPE PGM_TYPE_REAL
272#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
273#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_REAL(name)
274#include "PGMGstDefs.h"
275#include "PGMAllBth.h"
276#undef PGM_BTH_NAME
277#undef PGM_GST_TYPE
278#undef PGM_GST_NAME
279
280/* Guest - protected mode */
281#define PGM_GST_TYPE PGM_TYPE_PROT
282#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
283#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PROT(name)
284#include "PGMGstDefs.h"
285#include "PGMAllBth.h"
286#undef PGM_BTH_NAME
287#undef PGM_GST_TYPE
288#undef PGM_GST_NAME
289
290/* Guest - 32-bit mode */
291#define PGM_GST_TYPE PGM_TYPE_32BIT
292#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
293#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_32BIT(name)
294#include "PGMGstDefs.h"
295#include "PGMAllBth.h"
296#undef PGM_BTH_NAME
297#undef PGM_GST_TYPE
298#undef PGM_GST_NAME
299
300/* Guest - PAE mode */
301#define PGM_GST_TYPE PGM_TYPE_PAE
302#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
303#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PAE(name)
304#include "PGMGstDefs.h"
305#include "PGMAllBth.h"
306#undef PGM_BTH_NAME
307#undef PGM_GST_TYPE
308#undef PGM_GST_NAME
309
310#ifdef VBOX_WITH_64_BITS_GUESTS
311/* Guest - AMD64 mode */
312# define PGM_GST_TYPE PGM_TYPE_AMD64
313# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
314# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_AMD64(name)
315# include "PGMGstDefs.h"
316# include "PGMAllBth.h"
317# undef PGM_BTH_NAME
318# undef PGM_GST_TYPE
319# undef PGM_GST_NAME
320#endif /* VBOX_WITH_64_BITS_GUESTS */
321
322#undef PGM_SHW_TYPE
323#undef PGM_SHW_NAME
324
325
326/*
327 * Shadow - PAE nested paging mode.
328 */
329#define PGM_SHW_TYPE PGM_TYPE_NESTED_PAE
330#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_PAE(name)
331#include "PGMAllShw.h"
332
333/* Guest - real mode */
334#define PGM_GST_TYPE PGM_TYPE_REAL
335#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
336#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_REAL(name)
337#include "PGMGstDefs.h"
338#include "PGMAllBth.h"
339#undef PGM_BTH_NAME
340#undef PGM_GST_TYPE
341#undef PGM_GST_NAME
342
343/* Guest - protected mode */
344#define PGM_GST_TYPE PGM_TYPE_PROT
345#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
346#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PROT(name)
347#include "PGMGstDefs.h"
348#include "PGMAllBth.h"
349#undef PGM_BTH_NAME
350#undef PGM_GST_TYPE
351#undef PGM_GST_NAME
352
353/* Guest - 32-bit mode */
354#define PGM_GST_TYPE PGM_TYPE_32BIT
355#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
356#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_32BIT(name)
357#include "PGMGstDefs.h"
358#include "PGMAllBth.h"
359#undef PGM_BTH_NAME
360#undef PGM_GST_TYPE
361#undef PGM_GST_NAME
362
363/* Guest - PAE mode */
364#define PGM_GST_TYPE PGM_TYPE_PAE
365#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
366#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PAE(name)
367#include "PGMGstDefs.h"
368#include "PGMAllBth.h"
369#undef PGM_BTH_NAME
370#undef PGM_GST_TYPE
371#undef PGM_GST_NAME
372
373#ifdef VBOX_WITH_64_BITS_GUESTS
374/* Guest - AMD64 mode */
375# define PGM_GST_TYPE PGM_TYPE_AMD64
376# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
377# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_AMD64(name)
378# include "PGMGstDefs.h"
379# include "PGMAllBth.h"
380# undef PGM_BTH_NAME
381# undef PGM_GST_TYPE
382# undef PGM_GST_NAME
383#endif /* VBOX_WITH_64_BITS_GUESTS */
384
385#undef PGM_SHW_TYPE
386#undef PGM_SHW_NAME
387
388
389/*
390 * Shadow - AMD64 nested paging mode.
391 */
392#define PGM_SHW_TYPE PGM_TYPE_NESTED_AMD64
393#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_AMD64(name)
394#include "PGMAllShw.h"
395
396/* Guest - real mode */
397#define PGM_GST_TYPE PGM_TYPE_REAL
398#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
399#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_REAL(name)
400#include "PGMGstDefs.h"
401#include "PGMAllBth.h"
402#undef PGM_BTH_NAME
403#undef PGM_GST_TYPE
404#undef PGM_GST_NAME
405
406/* Guest - protected mode */
407#define PGM_GST_TYPE PGM_TYPE_PROT
408#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
409#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PROT(name)
410#include "PGMGstDefs.h"
411#include "PGMAllBth.h"
412#undef PGM_BTH_NAME
413#undef PGM_GST_TYPE
414#undef PGM_GST_NAME
415
416/* Guest - 32-bit mode */
417#define PGM_GST_TYPE PGM_TYPE_32BIT
418#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
419#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_32BIT(name)
420#include "PGMGstDefs.h"
421#include "PGMAllBth.h"
422#undef PGM_BTH_NAME
423#undef PGM_GST_TYPE
424#undef PGM_GST_NAME
425
426/* Guest - PAE mode */
427#define PGM_GST_TYPE PGM_TYPE_PAE
428#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
429#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PAE(name)
430#include "PGMGstDefs.h"
431#include "PGMAllBth.h"
432#undef PGM_BTH_NAME
433#undef PGM_GST_TYPE
434#undef PGM_GST_NAME
435
436#ifdef VBOX_WITH_64_BITS_GUESTS
437/* Guest - AMD64 mode */
438# define PGM_GST_TYPE PGM_TYPE_AMD64
439# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
440# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_AMD64(name)
441# include "PGMGstDefs.h"
442# include "PGMAllBth.h"
443# undef PGM_BTH_NAME
444# undef PGM_GST_TYPE
445# undef PGM_GST_NAME
446#endif /* VBOX_WITH_64_BITS_GUESTS */
447
448#undef PGM_SHW_TYPE
449#undef PGM_SHW_NAME
450
451
452/*
453 * Shadow - EPT.
454 */
455#define PGM_SHW_TYPE PGM_TYPE_EPT
456#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
457#include "PGMAllShw.h"
458
459/* Guest - real mode */
460#define PGM_GST_TYPE PGM_TYPE_REAL
461#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
462#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
463#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
464#include "PGMGstDefs.h"
465#include "PGMAllBth.h"
466#undef BTH_PGMPOOLKIND_PT_FOR_PT
467#undef PGM_BTH_NAME
468#undef PGM_GST_TYPE
469#undef PGM_GST_NAME
470
471/* Guest - protected mode */
472#define PGM_GST_TYPE PGM_TYPE_PROT
473#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
474#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
475#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
476#include "PGMGstDefs.h"
477#include "PGMAllBth.h"
478#undef BTH_PGMPOOLKIND_PT_FOR_PT
479#undef PGM_BTH_NAME
480#undef PGM_GST_TYPE
481#undef PGM_GST_NAME
482
483/* Guest - 32-bit mode */
484#define PGM_GST_TYPE PGM_TYPE_32BIT
485#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
486#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
487#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
488#include "PGMGstDefs.h"
489#include "PGMAllBth.h"
490#undef BTH_PGMPOOLKIND_PT_FOR_PT
491#undef PGM_BTH_NAME
492#undef PGM_GST_TYPE
493#undef PGM_GST_NAME
494
495/* Guest - PAE mode */
496#define PGM_GST_TYPE PGM_TYPE_PAE
497#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
498#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
499#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
500#include "PGMGstDefs.h"
501#include "PGMAllBth.h"
502#undef BTH_PGMPOOLKIND_PT_FOR_PT
503#undef PGM_BTH_NAME
504#undef PGM_GST_TYPE
505#undef PGM_GST_NAME
506
507#ifdef VBOX_WITH_64_BITS_GUESTS
508/* Guest - AMD64 mode */
509# define PGM_GST_TYPE PGM_TYPE_AMD64
510# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
511# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
512# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
513# include "PGMGstDefs.h"
514# include "PGMAllBth.h"
515# undef BTH_PGMPOOLKIND_PT_FOR_PT
516# undef PGM_BTH_NAME
517# undef PGM_GST_TYPE
518# undef PGM_GST_NAME
519#endif /* VBOX_WITH_64_BITS_GUESTS */
520
521#undef PGM_SHW_TYPE
522#undef PGM_SHW_NAME
523
524
525/*
526 * Shadow - NEM / None.
527 */
528#define PGM_SHW_TYPE PGM_TYPE_NONE
529#define PGM_SHW_NAME(name) PGM_SHW_NAME_NONE(name)
530#include "PGMAllShw.h"
531
532/* Guest - real mode */
533#define PGM_GST_TYPE PGM_TYPE_REAL
534#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
535#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_REAL(name)
536#include "PGMGstDefs.h"
537#include "PGMAllBth.h"
538#undef PGM_BTH_NAME
539#undef PGM_GST_TYPE
540#undef PGM_GST_NAME
541
542/* Guest - protected mode */
543#define PGM_GST_TYPE PGM_TYPE_PROT
544#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
545#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_PROT(name)
546#include "PGMGstDefs.h"
547#include "PGMAllBth.h"
548#undef PGM_BTH_NAME
549#undef PGM_GST_TYPE
550#undef PGM_GST_NAME
551
552/* Guest - 32-bit mode */
553#define PGM_GST_TYPE PGM_TYPE_32BIT
554#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
555#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_32BIT(name)
556#include "PGMGstDefs.h"
557#include "PGMAllBth.h"
558#undef PGM_BTH_NAME
559#undef PGM_GST_TYPE
560#undef PGM_GST_NAME
561
562/* Guest - PAE mode */
563#define PGM_GST_TYPE PGM_TYPE_PAE
564#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
565#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_PAE(name)
566#include "PGMGstDefs.h"
567#include "PGMAllBth.h"
568#undef PGM_BTH_NAME
569#undef PGM_GST_TYPE
570#undef PGM_GST_NAME
571
572#ifdef VBOX_WITH_64_BITS_GUESTS
573/* Guest - AMD64 mode */
574# define PGM_GST_TYPE PGM_TYPE_AMD64
575# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
576# define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_AMD64(name)
577# include "PGMGstDefs.h"
578# include "PGMAllBth.h"
579# undef PGM_BTH_NAME
580# undef PGM_GST_TYPE
581# undef PGM_GST_NAME
582#endif /* VBOX_WITH_64_BITS_GUESTS */
583
584#undef PGM_SHW_TYPE
585#undef PGM_SHW_NAME
586
587
588
589/**
590 * Guest mode data array.
591 */
592PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE] =
593{
594 { UINT32_MAX, NULL, NULL, NULL, NULL }, /* 0 */
595 {
596 PGM_TYPE_REAL,
597 PGM_GST_NAME_REAL(GetPage),
598 PGM_GST_NAME_REAL(ModifyPage),
599 PGM_GST_NAME_REAL(Enter),
600 PGM_GST_NAME_REAL(Exit),
601#ifdef IN_RING3
602 PGM_GST_NAME_REAL(Relocate),
603#endif
604 },
605 {
606 PGM_TYPE_PROT,
607 PGM_GST_NAME_PROT(GetPage),
608 PGM_GST_NAME_PROT(ModifyPage),
609 PGM_GST_NAME_PROT(Enter),
610 PGM_GST_NAME_PROT(Exit),
611#ifdef IN_RING3
612 PGM_GST_NAME_PROT(Relocate),
613#endif
614 },
615 {
616 PGM_TYPE_32BIT,
617 PGM_GST_NAME_32BIT(GetPage),
618 PGM_GST_NAME_32BIT(ModifyPage),
619 PGM_GST_NAME_32BIT(Enter),
620 PGM_GST_NAME_32BIT(Exit),
621#ifdef IN_RING3
622 PGM_GST_NAME_32BIT(Relocate),
623#endif
624 },
625 {
626 PGM_TYPE_PAE,
627 PGM_GST_NAME_PAE(GetPage),
628 PGM_GST_NAME_PAE(ModifyPage),
629 PGM_GST_NAME_PAE(Enter),
630 PGM_GST_NAME_PAE(Exit),
631#ifdef IN_RING3
632 PGM_GST_NAME_PAE(Relocate),
633#endif
634 },
635#ifdef VBOX_WITH_64_BITS_GUESTS
636 {
637 PGM_TYPE_AMD64,
638 PGM_GST_NAME_AMD64(GetPage),
639 PGM_GST_NAME_AMD64(ModifyPage),
640 PGM_GST_NAME_AMD64(Enter),
641 PGM_GST_NAME_AMD64(Exit),
642# ifdef IN_RING3
643 PGM_GST_NAME_AMD64(Relocate),
644# endif
645 },
646#endif
647};
648
649
650/**
651 * The shadow mode data array.
652 */
653PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE] =
654{
655 { UINT8_MAX, NULL, NULL, NULL, NULL }, /* 0 */
656 { UINT8_MAX, NULL, NULL, NULL, NULL }, /* PGM_TYPE_REAL */
657 { UINT8_MAX, NULL, NULL, NULL, NULL }, /* PGM_TYPE_PROT */
658 {
659 PGM_TYPE_32BIT,
660 PGM_SHW_NAME_32BIT(GetPage),
661 PGM_SHW_NAME_32BIT(ModifyPage),
662 PGM_SHW_NAME_32BIT(Enter),
663 PGM_SHW_NAME_32BIT(Exit),
664#ifdef IN_RING3
665 PGM_SHW_NAME_32BIT(Relocate),
666#endif
667 },
668 {
669 PGM_TYPE_PAE,
670 PGM_SHW_NAME_PAE(GetPage),
671 PGM_SHW_NAME_PAE(ModifyPage),
672 PGM_SHW_NAME_PAE(Enter),
673 PGM_SHW_NAME_PAE(Exit),
674#ifdef IN_RING3
675 PGM_SHW_NAME_PAE(Relocate),
676#endif
677 },
678 {
679 PGM_TYPE_AMD64,
680 PGM_SHW_NAME_AMD64(GetPage),
681 PGM_SHW_NAME_AMD64(ModifyPage),
682 PGM_SHW_NAME_AMD64(Enter),
683 PGM_SHW_NAME_AMD64(Exit),
684#ifdef IN_RING3
685 PGM_SHW_NAME_AMD64(Relocate),
686#endif
687 },
688 {
689 PGM_TYPE_NESTED_32BIT,
690 PGM_SHW_NAME_NESTED_32BIT(GetPage),
691 PGM_SHW_NAME_NESTED_32BIT(ModifyPage),
692 PGM_SHW_NAME_NESTED_32BIT(Enter),
693 PGM_SHW_NAME_NESTED_32BIT(Exit),
694#ifdef IN_RING3
695 PGM_SHW_NAME_NESTED_32BIT(Relocate),
696#endif
697 },
698 {
699 PGM_TYPE_NESTED_PAE,
700 PGM_SHW_NAME_NESTED_PAE(GetPage),
701 PGM_SHW_NAME_NESTED_PAE(ModifyPage),
702 PGM_SHW_NAME_NESTED_PAE(Enter),
703 PGM_SHW_NAME_NESTED_PAE(Exit),
704#ifdef IN_RING3
705 PGM_SHW_NAME_NESTED_PAE(Relocate),
706#endif
707 },
708 {
709 PGM_TYPE_NESTED_AMD64,
710 PGM_SHW_NAME_NESTED_AMD64(GetPage),
711 PGM_SHW_NAME_NESTED_AMD64(ModifyPage),
712 PGM_SHW_NAME_NESTED_AMD64(Enter),
713 PGM_SHW_NAME_NESTED_AMD64(Exit),
714#ifdef IN_RING3
715 PGM_SHW_NAME_NESTED_AMD64(Relocate),
716#endif
717 },
718 {
719 PGM_TYPE_EPT,
720 PGM_SHW_NAME_EPT(GetPage),
721 PGM_SHW_NAME_EPT(ModifyPage),
722 PGM_SHW_NAME_EPT(Enter),
723 PGM_SHW_NAME_EPT(Exit),
724#ifdef IN_RING3
725 PGM_SHW_NAME_EPT(Relocate),
726#endif
727 },
728 {
729 PGM_TYPE_NONE,
730 PGM_SHW_NAME_NONE(GetPage),
731 PGM_SHW_NAME_NONE(ModifyPage),
732 PGM_SHW_NAME_NONE(Enter),
733 PGM_SHW_NAME_NONE(Exit),
734#ifdef IN_RING3
735 PGM_SHW_NAME_NONE(Relocate),
736#endif
737 },
738};
739
740
741/**
742 * The guest+shadow mode data array.
743 */
744PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE] =
745{
746#if !defined(IN_RING3) && !defined(VBOX_STRICT)
747# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
748# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
749 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Trap0eHandler), Nm(NestedTrap0eHandler) }
750
751#elif !defined(IN_RING3) && defined(VBOX_STRICT)
752# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
753# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
754 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Trap0eHandler), Nm(NestedTrap0eHandler), Nm(AssertCR3) }
755
756#elif defined(IN_RING3) && !defined(VBOX_STRICT)
757# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL }
758# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
759 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), }
760
761#elif defined(IN_RING3) && defined(VBOX_STRICT)
762# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
763# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
764 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(AssertCR3) }
765
766#else
767# error "Misconfig."
768#endif
769
770 /* 32-bit shadow paging mode: */
771 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
772 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_32BIT_REAL),
773 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_32BIT_PROT),
774 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_32BIT_32BIT),
775 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_PAE - illegal */
776 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_AMD64 - illegal */
777 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
778 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_PAE - illegal */
779 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
780 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_EPT - illegal */
781 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NONE - illegal */
782
783 /* PAE shadow paging mode: */
784 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
785 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_PAE_REAL),
786 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_PAE_PROT),
787 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_PAE_32BIT),
788 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_PAE_PAE),
789 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_AMD64 - illegal */
790 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_32BIT - illegal */
791 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_PAE - illegal */
792 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
793 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_EPT - illegal */
794 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NONE - illegal */
795
796 /* AMD64 shadow paging mode: */
797 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
798 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_AMD64_REAL),
799 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_AMD64_PROT),
800 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_AMD64_32BIT),
801 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_AMD64_PAE),
802#ifdef VBOX_WITH_64_BITS_GUESTS
803 PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_AMD64_AMD64),
804#else
805 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_AMD64 - illegal */
806#endif
807 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
808 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_PAE - illegal */
809 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
810 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_EPT - illegal */
811 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NONE - illegal */
812
813 /* 32-bit nested paging mode: */
814 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
815 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_32BIT_REAL),
816 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_32BIT_PROT),
817 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_32BIT_32BIT),
818 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_32BIT_PAE),
819#ifdef VBOX_WITH_64_BITS_GUESTS
820 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_32BIT_AMD64),
821#else
822 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64 - illegal */
823#endif
824 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
825 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_PAE - illegal */
826 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
827 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_EPT - illegal */
828 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NONE - illegal */
829
830 /* PAE nested paging mode: */
831 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
832 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_PAE_REAL),
833 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_PAE_PROT),
834 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_PAE_32BIT),
835 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_PAE_PAE),
836#ifdef VBOX_WITH_64_BITS_GUESTS
837 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_PAE_AMD64),
838#else
839 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64 - illegal */
840#endif
841 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_32BIT - illegal */
842 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_PAE - illegal */
843 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
844 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_EPT - illegal */
845 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NONE - illegal */
846
847 /* AMD64 nested paging mode: */
848 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
849 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_AMD64_REAL),
850 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_AMD64_PROT),
851 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_AMD64_32BIT),
852 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_AMD64_PAE),
853#ifdef VBOX_WITH_64_BITS_GUESTS
854 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_AMD64_AMD64),
855#else
856 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64 - illegal */
857#endif
858 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
859 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_PAE - illegal */
860 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
861 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_EPT - illegal */
862 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NONE - illegal */
863
864 /* EPT nested paging mode: */
865 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
866 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_REAL, PGM_BTH_NAME_EPT_REAL),
867 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PROT, PGM_BTH_NAME_EPT_PROT),
868 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
869 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PAE, PGM_BTH_NAME_EPT_PAE),
870#ifdef VBOX_WITH_64_BITS_GUESTS
871 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
872#else
873 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_AMD64 - illegal */
874#endif
875 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_32BIT - illegal */
876 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_PAE - illegal */
877 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_AMD64 - illegal */
878 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_EPT - illegal */
879 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NONE - illegal */
880
881 /* NONE / NEM: */
882 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
883 PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_REAL, PGM_BTH_NAME_EPT_REAL),
884 PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_PROT, PGM_BTH_NAME_EPT_PROT),
885 PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
886 PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_PAE, PGM_BTH_NAME_EPT_PAE),
887#ifdef VBOX_WITH_64_BITS_GUESTS
888 PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
889#else
890 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_AMD64 - illegal */
891#endif
892 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_32BIT - illegal */
893 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_PAE - illegal */
894 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_AMD64 - illegal */
895 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_EPT - illegal */
896 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NONE - illegal */
897
898
899#undef PGMMODEDATABTH_ENTRY
900#undef PGMMODEDATABTH_NULL_ENTRY
901};
902
903
904/**
905 * Gets the CR3 mask corresponding to the given paging mode.
906 *
907 * @returns The CR3 mask.
908 * @param enmMode The paging mode.
909 * @param enmSlatMode The second-level address translation mode.
910 */
911DECLINLINE(uint64_t) pgmGetCr3MaskForMode(PGMMODE enmMode, PGMSLAT enmSlatMode)
912{
913 /** @todo This work can be optimized either by storing the masks in
914 * pVCpu->pgm.s.afGstCr3Masks[] for all PGMMODEs -or- just do this once and
915 * store the result when entering guest mode since we currently use it only
916 * for enmGuestMode. */
917 if (enmSlatMode == PGMSLAT_DIRECT)
918 {
919 Assert(enmMode != PGMMODE_EPT);
920 switch (enmMode)
921 {
922 case PGMMODE_PAE:
923 case PGMMODE_PAE_NX:
924 return X86_CR3_PAE_PAGE_MASK;
925 case PGMMODE_AMD64:
926 case PGMMODE_AMD64_NX:
927 return X86_CR3_AMD64_PAGE_MASK;
928 default:
929 return X86_CR3_PAGE_MASK;
930 }
931 }
932 else
933 {
934 Assert(enmSlatMode == PGMSLAT_EPT);
935 return X86_CR3_EPT_PAGE_MASK;
936 }
937}
938
939
940/**
941 * Gets the masked CR3 value according to the current guest paging mode.
942 *
943 * @returns The masked PGM CR3 value.
944 * @param pVCpu The cross context virtual CPU structure.
945 * @param uCr3 The raw guest CR3 value.
946 */
947DECLINLINE(RTGCPHYS) pgmGetGuestMaskedCr3(PVMCPUCC pVCpu, uint64_t uCr3)
948{
949 uint64_t const fCr3Mask = pgmGetCr3MaskForMode(pVCpu->pgm.s.enmGuestMode, pVCpu->pgm.s.enmGuestSlatMode);
950 RTGCPHYS GCPhysCR3 = (RTGCPHYS)(uCr3 & fCr3Mask);
951 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
952 return GCPhysCR3;
953}
954
955
956#ifdef IN_RING0
957/**
958 * #PF Handler.
959 *
960 * @returns VBox status code (appropriate for trap handling and GC return).
961 * @param pVCpu The cross context virtual CPU structure.
962 * @param uErr The trap error code.
963 * @param pRegFrame Trap register frame.
964 * @param pvFault The fault address.
965 */
966VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
967{
968 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
969
970 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
971 STAM_PROFILE_START(&pVCpu->pgm.s.Stats.StatRZTrap0e, a);
972 STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = NULL; } );
973
974
975# ifdef VBOX_WITH_STATISTICS
976 /*
977 * Error code stats.
978 */
979 if (uErr & X86_TRAP_PF_US)
980 {
981 if (!(uErr & X86_TRAP_PF_P))
982 {
983 if (uErr & X86_TRAP_PF_RW)
984 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSNotPresentWrite);
985 else
986 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSNotPresentRead);
987 }
988 else if (uErr & X86_TRAP_PF_RW)
989 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSWrite);
990 else if (uErr & X86_TRAP_PF_RSVD)
991 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSReserved);
992 else if (uErr & X86_TRAP_PF_ID)
993 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSNXE);
994 else
995 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSRead);
996 }
997 else
998 { /* Supervisor */
999 if (!(uErr & X86_TRAP_PF_P))
1000 {
1001 if (uErr & X86_TRAP_PF_RW)
1002 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVNotPresentWrite);
1003 else
1004 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVNotPresentRead);
1005 }
1006 else if (uErr & X86_TRAP_PF_RW)
1007 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVWrite);
1008 else if (uErr & X86_TRAP_PF_ID)
1009 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSNXE);
1010 else if (uErr & X86_TRAP_PF_RSVD)
1011 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVReserved);
1012 }
1013# endif /* VBOX_WITH_STATISTICS */
1014
1015 /*
1016 * Call the worker.
1017 */
1018 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1019 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1020 AssertReturn(g_aPgmBothModeData[idxBth].pfnTrap0eHandler, VERR_PGM_MODE_IPE);
1021 bool fLockTaken = false;
1022 int rc = g_aPgmBothModeData[idxBth].pfnTrap0eHandler(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
1023 if (fLockTaken)
1024 {
1025 PGM_LOCK_ASSERT_OWNER(pVM);
1026 PGM_UNLOCK(pVM);
1027 }
1028 LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
1029
1030 /*
1031 * Return code tweaks.
1032 */
1033 if (rc != VINF_SUCCESS)
1034 {
1035 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
1036 rc = VINF_SUCCESS;
1037
1038 /* Note: hack alert for difficult to reproduce problem. */
1039 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
1040 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
1041 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
1042 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
1043 {
1044 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
1045 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
1046 rc = VINF_SUCCESS;
1047 }
1048 }
1049
1050 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eGuestPF); });
1051 STAM_STATS({ if (!pVCpu->pgmr0.s.pStatTrap0eAttributionR0)
1052 pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Misc; });
1053 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.Stats.StatRZTrap0e, pVCpu->pgmr0.s.pStatTrap0eAttributionR0, a);
1054 return rc;
1055}
1056#endif /* IN_RING0 */
1057
1058
1059/**
1060 * Prefetch a page
1061 *
1062 * Typically used to sync commonly used pages before entering raw mode
1063 * after a CR3 reload.
1064 *
1065 * @returns VBox status code suitable for scheduling.
1066 * @retval VINF_SUCCESS on success.
1067 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
1068 * @param pVCpu The cross context virtual CPU structure.
1069 * @param GCPtrPage Page to invalidate.
1070 */
1071VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1072{
1073 STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,Prefetch), a);
1074
1075 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1076 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1077 AssertReturn(g_aPgmBothModeData[idxBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
1078 int rc = g_aPgmBothModeData[idxBth].pfnPrefetchPage(pVCpu, GCPtrPage);
1079
1080 STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,Prefetch), a);
1081 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1082 return rc;
1083}
1084
1085
1086/**
1087 * Emulation of the invlpg instruction (HC only actually).
1088 *
1089 * @returns Strict VBox status code, special care required.
1090 * @retval VINF_PGM_SYNC_CR3 - handled.
1091 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
1092 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
1093 *
1094 * @param pVCpu The cross context virtual CPU structure.
1095 * @param GCPtrPage Page to invalidate.
1096 *
1097 * @remark ASSUMES the page table entry or page directory is valid. Fairly
1098 * safe, but there could be edge cases!
1099 *
1100 * @todo Flush page or page directory only if necessary!
1101 * @todo VBOXSTRICTRC
1102 */
1103VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1104{
1105 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1106 int rc;
1107 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
1108
1109 IEMTlbInvalidatePage(pVCpu, GCPtrPage);
1110
1111 /*
1112 * Call paging mode specific worker.
1113 */
1114 STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage), a);
1115 PGM_LOCK_VOID(pVM);
1116
1117 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1118 AssertReturnStmt(idxBth < RT_ELEMENTS(g_aPgmBothModeData), PGM_UNLOCK(pVM), VERR_PGM_MODE_IPE);
1119 AssertReturnStmt(g_aPgmBothModeData[idxBth].pfnInvalidatePage, PGM_UNLOCK(pVM), VERR_PGM_MODE_IPE);
1120 rc = g_aPgmBothModeData[idxBth].pfnInvalidatePage(pVCpu, GCPtrPage);
1121
1122 PGM_UNLOCK(pVM);
1123 STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage), a);
1124
1125 /* Ignore all irrelevant error codes. */
1126 if ( rc == VERR_PAGE_NOT_PRESENT
1127 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1128 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
1129 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
1130 rc = VINF_SUCCESS;
1131
1132 return rc;
1133}
1134
1135
1136/**
1137 * Executes an instruction using the interpreter.
1138 *
1139 * @returns VBox status code (appropriate for trap handling and GC return).
1140 * @param pVM The cross context VM structure.
1141 * @param pVCpu The cross context virtual CPU structure.
1142 * @param pRegFrame Register frame.
1143 * @param pvFault Fault address.
1144 */
1145VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
1146{
1147 NOREF(pVM);
1148 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, pRegFrame, pvFault);
1149 if (rc == VERR_EM_INTERPRETER)
1150 rc = VINF_EM_RAW_EMULATE_INSTR;
1151 if (rc != VINF_SUCCESS)
1152 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
1153 return rc;
1154}
1155
1156
1157/**
1158 * Gets effective page information (from the VMM page directory).
1159 *
1160 * @returns VBox status code.
1161 * @param pVCpu The cross context virtual CPU structure.
1162 * @param GCPtr Guest Context virtual address of the page.
1163 * @param pfFlags Where to store the flags. These are X86_PTE_*.
1164 * @param pHCPhys Where to store the HC physical address of the page.
1165 * This is page aligned.
1166 * @remark You should use PGMMapGetPage() for pages in a mapping.
1167 */
1168VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
1169{
1170 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1171 PGM_LOCK_VOID(pVM);
1172
1173 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1174 AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1175 AssertReturn(g_aPgmShadowModeData[idxShw].pfnGetPage, VERR_PGM_MODE_IPE);
1176 int rc = g_aPgmShadowModeData[idxShw].pfnGetPage(pVCpu, GCPtr, pfFlags, pHCPhys);
1177
1178 PGM_UNLOCK(pVM);
1179 return rc;
1180}
1181
1182
1183/**
1184 * Modify page flags for a range of pages in the shadow context.
1185 *
1186 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1187 *
1188 * @returns VBox status code.
1189 * @param pVCpu The cross context virtual CPU structure.
1190 * @param GCPtr Virtual address of the first page in the range.
1191 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1192 * @param fMask The AND mask - page flags X86_PTE_*.
1193 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1194 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1195 * @remark You must use PGMMapModifyPage() for pages in a mapping.
1196 */
1197DECLINLINE(int) pdmShwModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
1198{
1199 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1200 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
1201
1202 GCPtr &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK; /** @todo this ain't necessary, right... */
1203
1204 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1205 PGM_LOCK_VOID(pVM);
1206
1207 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1208 AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1209 AssertReturn(g_aPgmShadowModeData[idxShw].pfnModifyPage, VERR_PGM_MODE_IPE);
1210 int rc = g_aPgmShadowModeData[idxShw].pfnModifyPage(pVCpu, GCPtr, GUEST_PAGE_SIZE, fFlags, fMask, fOpFlags);
1211
1212 PGM_UNLOCK(pVM);
1213 return rc;
1214}
1215
1216
1217/**
1218 * Changing the page flags for a single page in the shadow page tables so as to
1219 * make it read-only.
1220 *
1221 * @returns VBox status code.
1222 * @param pVCpu The cross context virtual CPU structure.
1223 * @param GCPtr Virtual address of the first page in the range.
1224 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1225 */
1226VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1227{
1228 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
1229}
1230
1231
1232/**
1233 * Changing the page flags for a single page in the shadow page tables so as to
1234 * make it writable.
1235 *
1236 * The call must know with 101% certainty that the guest page tables maps this
1237 * as writable too. This function will deal shared, zero and write monitored
1238 * pages.
1239 *
1240 * @returns VBox status code.
1241 * @param pVCpu The cross context virtual CPU structure.
1242 * @param GCPtr Virtual address of the first page in the range.
1243 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1244 */
1245VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1246{
1247 if (pVCpu->pgm.s.enmShadowMode != PGMMODE_NONE) /* avoid assertions */
1248 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
1249 return VINF_SUCCESS;
1250}
1251
1252
1253/**
1254 * Changing the page flags for a single page in the shadow page tables so as to
1255 * make it not present.
1256 *
1257 * @returns VBox status code.
1258 * @param pVCpu The cross context virtual CPU structure.
1259 * @param GCPtr Virtual address of the first page in the range.
1260 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1261 */
1262VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1263{
1264 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
1265}
1266
1267
1268/**
1269 * Changing the page flags for a single page in the shadow page tables so as to
1270 * make it supervisor and writable.
1271 *
1272 * This if for dealing with CR0.WP=0 and readonly user pages.
1273 *
1274 * @returns VBox status code.
1275 * @param pVCpu The cross context virtual CPU structure.
1276 * @param GCPtr Virtual address of the first page in the range.
1277 * @param fBigPage Whether or not this is a big page. If it is, we have to
1278 * change the shadow PDE as well. If it isn't, the caller
1279 * has checked that the shadow PDE doesn't need changing.
1280 * We ASSUME 4KB pages backing the big page here!
1281 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1282 */
1283int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags)
1284{
1285 int rc = pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)X86_PTE_US, fOpFlags);
1286 if (rc == VINF_SUCCESS && fBigPage)
1287 {
1288 /* this is a bit ugly... */
1289 switch (pVCpu->pgm.s.enmShadowMode)
1290 {
1291 case PGMMODE_32_BIT:
1292 {
1293 PX86PDE pPde = pgmShwGet32BitPDEPtr(pVCpu, GCPtr);
1294 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1295 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1296 pPde->u |= X86_PDE_RW;
1297 Log(("-> PDE=%#llx (32)\n", pPde->u));
1298 break;
1299 }
1300 case PGMMODE_PAE:
1301 case PGMMODE_PAE_NX:
1302 {
1303 PX86PDEPAE pPde = pgmShwGetPaePDEPtr(pVCpu, GCPtr);
1304 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1305 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1306 pPde->u |= X86_PDE_RW;
1307 Log(("-> PDE=%#llx (PAE)\n", pPde->u));
1308 break;
1309 }
1310 default:
1311 AssertFailedReturn(VERR_INTERNAL_ERROR_4);
1312 }
1313 }
1314 return rc;
1315}
1316
1317
1318/**
1319 * Gets the shadow page directory for the specified address, PAE.
1320 *
1321 * @returns Pointer to the shadow PD.
1322 * @param pVCpu The cross context virtual CPU structure.
1323 * @param GCPtr The address.
1324 * @param uGstPdpe Guest PDPT entry. Valid.
1325 * @param ppPD Receives address of page directory
1326 */
1327int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1328{
1329 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1330 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1331 PPGMPOOLPAGE pShwPage;
1332 int rc;
1333 PGM_LOCK_ASSERT_OWNER(pVM);
1334
1335
1336 /* Allocate page directory if not present. */
1337 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1338 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1339 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1340 X86PGPAEUINT const uPdpe = pPdpe->u;
1341 if (uPdpe & (X86_PDPE_P | X86_PDPE_PG_MASK))
1342 {
1343 pShwPage = pgmPoolGetPage(pPool, uPdpe & X86_PDPE_PG_MASK);
1344 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1345 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1346
1347 pgmPoolCacheUsed(pPool, pShwPage);
1348
1349 /* Update the entry if necessary. */
1350 X86PGPAEUINT const uPdpeNew = pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A)) | (uPdpe & PGM_PDPT_FLAGS);
1351 if (uPdpeNew == uPdpe)
1352 { /* likely */ }
1353 else
1354 ASMAtomicWriteU64(&pPdpe->u, uPdpeNew);
1355 }
1356 else
1357 {
1358 RTGCPTR64 GCPdPt;
1359 PGMPOOLKIND enmKind;
1360 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
1361 {
1362 /* AMD-V nested paging or real/protected mode without paging. */
1363 GCPdPt = GCPtr & ~(RT_BIT_64(X86_PDPT_SHIFT) - 1);
1364 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1365 }
1366 else if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
1367 {
1368 if (uGstPdpe & X86_PDPE_P)
1369 {
1370 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1371 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
1372 }
1373 else
1374 {
1375 /* PD not present; guest must reload CR3 to change it.
1376 * No need to monitor anything in this case. */
1377 /** @todo r=bird: WTF is hit?!? */
1378 /*Assert(VM_IS_RAW_MODE_ENABLED(pVM)); - ??? */
1379 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1380 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1381 Assert(uGstPdpe & X86_PDPE_P); /* caller should do this already */
1382 }
1383 }
1384 else
1385 {
1386 GCPdPt = CPUMGetGuestCR3(pVCpu);
1387 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
1388 }
1389
1390 /* Create a reference back to the PDPT by using the index in its shadow page. */
1391 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1392 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /*fLockPage*/,
1393 &pShwPage);
1394 AssertRCReturn(rc, rc);
1395
1396 /* Hook it up. */
1397 ASMAtomicWriteU64(&pPdpe->u, pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A)) | (uPdpe & PGM_PDPT_FLAGS));
1398 }
1399 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
1400
1401 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1402 return VINF_SUCCESS;
1403}
1404
1405
1406/**
1407 * Gets the pointer to the shadow page directory entry for an address, PAE.
1408 *
1409 * @returns Pointer to the PDE.
1410 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1411 * @param GCPtr The address.
1412 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1413 */
1414DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1415{
1416 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1417 PGM_LOCK_ASSERT_OWNER(pVM);
1418
1419 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1420 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1421 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1422 X86PGPAEUINT const uPdpe = pPdpt->a[iPdPt].u;
1423 if (!(uPdpe & X86_PDPE_P))
1424 {
1425 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, uPdpe));
1426 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1427 }
1428 AssertMsg(uPdpe & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1429
1430 /* Fetch the pgm pool shadow descriptor. */
1431 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), uPdpe & X86_PDPE_PG_MASK);
1432 AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1433
1434 *ppShwPde = pShwPde;
1435 return VINF_SUCCESS;
1436}
1437
1438
1439/**
1440 * Syncs the SHADOW page directory pointer for the specified address.
1441 *
1442 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1443 *
1444 * The caller is responsible for making sure the guest has a valid PD before
1445 * calling this function.
1446 *
1447 * @returns VBox status code.
1448 * @param pVCpu The cross context virtual CPU structure.
1449 * @param GCPtr The address.
1450 * @param uGstPml4e Guest PML4 entry (valid).
1451 * @param uGstPdpe Guest PDPT entry (valid).
1452 * @param ppPD Receives address of page directory
1453 */
1454static int pgmShwSyncLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1455{
1456 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1457 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1458 bool const fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1459 int rc;
1460
1461 PGM_LOCK_ASSERT_OWNER(pVM);
1462
1463 /*
1464 * PML4.
1465 */
1466 PPGMPOOLPAGE pShwPage;
1467 {
1468 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1469 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1470 X86PGPAEUINT const uPml4e = pPml4e->u;
1471
1472 /* Allocate page directory pointer table if not present. */
1473 if (uPml4e & (X86_PML4E_P | X86_PML4E_PG_MASK))
1474 {
1475 pShwPage = pgmPoolGetPage(pPool, uPml4e & X86_PML4E_PG_MASK);
1476 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1477
1478 pgmPoolCacheUsed(pPool, pShwPage);
1479
1480 /* Update the entry if needed. */
1481 X86PGPAEUINT const uPml4eNew = pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask)
1482 | (uPml4e & PGM_PML4_FLAGS);
1483 if (uPml4e == uPml4eNew)
1484 { /* likely */ }
1485 else
1486 ASMAtomicWriteU64(&pPml4e->u, uPml4eNew);
1487 }
1488 else
1489 {
1490 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1491
1492 RTGCPTR64 GCPml4;
1493 PGMPOOLKIND enmKind;
1494 if (fNestedPagingOrNoGstPaging)
1495 {
1496 /* AMD-V nested paging or real/protected mode without paging */
1497 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT; /** @todo bogus calculation for PML5 */
1498 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1499 }
1500 else
1501 {
1502 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1503 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1504 }
1505
1506 /* Create a reference back to the PDPT by using the index in its shadow page. */
1507 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1508 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1509 &pShwPage);
1510 AssertRCReturn(rc, rc);
1511
1512 /* Hook it up. */
1513 ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask)
1514 | (uPml4e & PGM_PML4_FLAGS));
1515 }
1516 }
1517
1518 /*
1519 * PDPT.
1520 */
1521 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1522 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1523 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1524 X86PGPAEUINT const uPdpe = pPdpe->u;
1525
1526 /* Allocate page directory if not present. */
1527 if (uPdpe & (X86_PDPE_P | X86_PDPE_PG_MASK))
1528 {
1529 pShwPage = pgmPoolGetPage(pPool, uPdpe & X86_PDPE_PG_MASK);
1530 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1531
1532 pgmPoolCacheUsed(pPool, pShwPage);
1533
1534 /* Update the entry if needed. */
1535 X86PGPAEUINT const uPdpeNew = pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask)
1536 | (uPdpe & PGM_PDPT_FLAGS);
1537 if (uPdpe == uPdpeNew)
1538 { /* likely */ }
1539 else
1540 ASMAtomicWriteU64(&pPdpe->u, uPdpeNew);
1541 }
1542 else
1543 {
1544 RTGCPTR64 GCPdPt;
1545 PGMPOOLKIND enmKind;
1546 if (fNestedPagingOrNoGstPaging)
1547 {
1548 /* AMD-V nested paging or real/protected mode without paging */
1549 GCPdPt = GCPtr & ~(RT_BIT_64(iPdPt << X86_PDPT_SHIFT) - 1);
1550 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1551 }
1552 else
1553 {
1554 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1555 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1556 }
1557
1558 /* Create a reference back to the PDPT by using the index in its shadow page. */
1559 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1560 pShwPage->idx, iPdPt, false /*fLockPage*/,
1561 &pShwPage);
1562 AssertRCReturn(rc, rc);
1563
1564 /* Hook it up. */
1565 ASMAtomicWriteU64(&pPdpe->u,
1566 pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask) | (uPdpe & PGM_PDPT_FLAGS));
1567 }
1568
1569 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1570 return VINF_SUCCESS;
1571}
1572
1573
1574/**
1575 * Gets the SHADOW page directory pointer for the specified address (long mode).
1576 *
1577 * @returns VBox status code.
1578 * @param pVCpu The cross context virtual CPU structure.
1579 * @param GCPtr The address.
1580 * @param ppPml4e Receives the address of the page map level 4 entry.
1581 * @param ppPdpt Receives the address of the page directory pointer table.
1582 * @param ppPD Receives the address of the page directory.
1583 */
1584DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1585{
1586 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1587 PGM_LOCK_ASSERT_OWNER(pVM);
1588
1589 /*
1590 * PML4
1591 */
1592 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1593 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1594 AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1595 if (ppPml4e)
1596 *ppPml4e = (PX86PML4E)pPml4e;
1597 X86PGPAEUINT const uPml4e = pPml4e->u;
1598 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, uPml4e));
1599 if (!(uPml4e & X86_PML4E_P)) /** @todo other code is check for NULL page frame number! */
1600 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1601
1602 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1603 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, uPml4e & X86_PML4E_PG_MASK);
1604 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1605
1606 /*
1607 * PDPT
1608 */
1609 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1610 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1611 X86PGPAEUINT const uPdpe = pPdpt->a[iPdPt].u;
1612 if (!(uPdpe & X86_PDPE_P)) /** @todo other code is check for NULL page frame number! */
1613 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1614
1615 pShwPage = pgmPoolGetPage(pPool, uPdpe & X86_PDPE_PG_MASK);
1616 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1617
1618 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1619 Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1620 return VINF_SUCCESS;
1621}
1622
1623
1624/**
1625 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1626 * backing pages in case the PDPT or PML4 entry is missing.
1627 *
1628 * @returns VBox status code.
1629 * @param pVCpu The cross context virtual CPU structure.
1630 * @param GCPtr The address.
1631 * @param ppPdpt Receives address of pdpt
1632 * @param ppPD Receives address of page directory
1633 */
1634static int pgmShwGetEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1635{
1636 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1637 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1638 int rc;
1639
1640 Assert(pVM->pgm.s.fNestedPaging);
1641 PGM_LOCK_ASSERT_OWNER(pVM);
1642
1643 /*
1644 * PML4 level.
1645 */
1646 PEPTPML4 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1647 Assert(pPml4);
1648
1649 /* Allocate page directory pointer table if not present. */
1650 PPGMPOOLPAGE pShwPage;
1651 {
1652 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1653 PEPTPML4E pPml4e = &pPml4->a[iPml4];
1654 EPTPML4E Pml4e;
1655 Pml4e.u = pPml4e->u;
1656 if (!(Pml4e.u & (EPT_E_PG_MASK | EPT_E_READ)))
1657 {
1658 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1659 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1660 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1661 &pShwPage);
1662 AssertRCReturn(rc, rc);
1663
1664 /* Hook up the new PDPT now. */
1665 ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE);
1666 }
1667 else
1668 {
1669 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1670 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1671
1672 pgmPoolCacheUsed(pPool, pShwPage);
1673
1674 /* Hook up the cached PDPT if needed (probably not given 512*512 PTs to sync). */
1675 if (Pml4e.u == (pShwPage->Core.Key | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE))
1676 { }
1677 else
1678 ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE);
1679 }
1680 }
1681
1682 /*
1683 * PDPT level.
1684 */
1685 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1686 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1687 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1688
1689 if (ppPdpt)
1690 *ppPdpt = pPdpt;
1691
1692 /* Allocate page directory if not present. */
1693 EPTPDPTE Pdpe;
1694 Pdpe.u = pPdpe->u;
1695 if (!(Pdpe.u & (EPT_E_PG_MASK | EPT_E_READ)))
1696 {
1697 RTGCPTR64 const GCPdPt = GCPtr & ~(RT_BIT_64(EPT_PDPT_SHIFT) - 1);
1698 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1699 pShwPage->idx, iPdPt, false /*fLockPage*/,
1700 &pShwPage);
1701 AssertRCReturn(rc, rc);
1702
1703 /* Hook up the new PD now. */
1704 ASMAtomicWriteU64(&pPdpe->u, pShwPage->Core.Key | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE);
1705 }
1706 else
1707 {
1708 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1709 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1710
1711 pgmPoolCacheUsed(pPool, pShwPage);
1712
1713 /* Hook up the cached PD if needed (probably not given there are 512 PTs we may need sync). */
1714 if (Pdpe.u == (pShwPage->Core.Key | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE))
1715 { }
1716 else
1717 ASMAtomicWriteU64(&pPdpe->u, pShwPage->Core.Key | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE);
1718 }
1719
1720 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1721 return VINF_SUCCESS;
1722}
1723
1724
1725#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1726/**
1727 * Syncs the SHADOW nested-guest page directory pointer for the specified address.
1728 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1729 *
1730 * @returns VBox status code.
1731 * @param pVCpu The cross context virtual CPU structure.
1732 * @param GCPhysNested The nested-guest physical address.
1733 * @param ppPdpt Where to store the PDPT. Optional, can be NULL.
1734 * @param ppPD Where to store the PD. Optional, can be NULL.
1735 * @param pGstWalkAll The guest walk info.
1736 */
1737static int pgmShwGetNestedEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPhysNested, PEPTPDPT *ppPdpt, PEPTPD *ppPD,
1738 PPGMPTWALKGST pGstWalkAll)
1739{
1740 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1741 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1742 int rc;
1743
1744 PPGMPOOLPAGE pShwPage;
1745 Assert(pVM->pgm.s.fNestedPaging);
1746 Assert(pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT);
1747 PGM_LOCK_ASSERT_OWNER(pVM);
1748
1749 /*
1750 * PML4 level.
1751 */
1752 {
1753 PEPTPML4 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1754 Assert(pPml4);
1755
1756 /* Allocate page directory pointer table if not present. */
1757 {
1758 uint64_t const fShwFlags = pGstWalkAll->u.Ept.Pml4e.u & pVCpu->pgm.s.fGstEptShadowedPml4eMask;
1759 const unsigned iPml4e = (GCPhysNested >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1760 PEPTPML4E pPml4e = &pPml4->a[iPml4e];
1761
1762 if (!(pPml4e->u & (EPT_E_PG_MASK | EPT_PRESENT_MASK)))
1763 {
1764 RTGCPHYS const GCPhysPdpt = pGstWalkAll->u.Ept.Pml4e.u & EPT_PML4E_PG_MASK;
1765 rc = pgmPoolAlloc(pVM, GCPhysPdpt, PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT, PGMPOOLACCESS_DONTCARE,
1766 PGM_A20_IS_ENABLED(pVCpu), pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4e, false /*fLockPage*/,
1767 &pShwPage);
1768 AssertRCReturn(rc, rc);
1769
1770 /* Hook up the new PDPT now. */
1771 ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key | fShwFlags);
1772 }
1773 else
1774 {
1775 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1776 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1777
1778 pgmPoolCacheUsed(pPool, pShwPage);
1779
1780 /* Hook up the cached PDPT if needed (probably not given 512*512 PTs to sync). */
1781 if (pPml4e->u != (pShwPage->Core.Key | fShwFlags))
1782 ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key | fShwFlags);
1783 }
1784 Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
1785 Log7Func(("GstPml4e=%RX64 ShwPml4e=%RX64 iPml4e=%u\n", pGstWalkAll->u.Ept.Pml4e.u, pPml4e->u, iPml4e));
1786 }
1787 }
1788
1789 /*
1790 * PDPT level.
1791 */
1792 {
1793 AssertReturn(!(pGstWalkAll->u.Ept.Pdpte.u & EPT_E_LEAF), VERR_NOT_SUPPORTED); /* shadowing 1GB pages not supported yet. */
1794
1795 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1796 if (ppPdpt)
1797 *ppPdpt = pPdpt;
1798
1799 uint64_t const fShwFlags = pGstWalkAll->u.Ept.Pdpte.u & pVCpu->pgm.s.fGstEptShadowedPdpteMask;
1800 const unsigned iPdPte = (GCPhysNested >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1801 PEPTPDPTE pPdpte = &pPdpt->a[iPdPte];
1802
1803 if (!(pPdpte->u & (EPT_E_PG_MASK | EPT_PRESENT_MASK)))
1804 {
1805 RTGCPHYS const GCPhysPd = pGstWalkAll->u.Ept.Pdpte.u & EPT_PDPTE_PG_MASK;
1806 rc = pgmPoolAlloc(pVM, GCPhysPd, PGMPOOLKIND_EPT_PD_FOR_EPT_PD, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1807 pShwPage->idx, iPdPte, false /*fLockPage*/, &pShwPage);
1808 AssertRCReturn(rc, rc);
1809
1810 /* Hook up the new PD now. */
1811 ASMAtomicWriteU64(&pPdpte->u, pShwPage->Core.Key | fShwFlags);
1812 }
1813 else
1814 {
1815 pShwPage = pgmPoolGetPage(pPool, pPdpte->u & EPT_PDPTE_PG_MASK);
1816 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1817
1818 pgmPoolCacheUsed(pPool, pShwPage);
1819
1820 /* Hook up the cached PD if needed (probably not given there are 512 PTs we may need sync). */
1821 if (pPdpte->u != (pShwPage->Core.Key | fShwFlags))
1822 ASMAtomicWriteU64(&pPdpte->u, pShwPage->Core.Key | fShwFlags);
1823 }
1824 Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
1825 Log7Func(("GstPdpte=%RX64 ShwPdpte=%RX64 iPdPte=%u \n", pGstWalkAll->u.Ept.Pdpte.u, pPdpte->u, iPdPte));
1826
1827 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1828 }
1829
1830 return VINF_SUCCESS;
1831}
1832#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
1833
1834
1835#ifdef IN_RING0
1836/**
1837 * Synchronizes a range of nested page table entries.
1838 *
1839 * The caller must own the PGM lock.
1840 *
1841 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1842 * @param GCPhys Where to start.
1843 * @param cPages How many pages which entries should be synced.
1844 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1845 * host paging mode for AMD-V).
1846 */
1847int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint32_t cPages, PGMMODE enmShwPagingMode)
1848{
1849 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1850
1851/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
1852 int rc;
1853 switch (enmShwPagingMode)
1854 {
1855 case PGMMODE_32_BIT:
1856 {
1857 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1858 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1859 break;
1860 }
1861
1862 case PGMMODE_PAE:
1863 case PGMMODE_PAE_NX:
1864 {
1865 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1866 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1867 break;
1868 }
1869
1870 case PGMMODE_AMD64:
1871 case PGMMODE_AMD64_NX:
1872 {
1873 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1874 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1875 break;
1876 }
1877
1878 case PGMMODE_EPT:
1879 {
1880 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1881 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1882 break;
1883 }
1884
1885 default:
1886 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
1887 }
1888 return rc;
1889}
1890#endif /* IN_RING0 */
1891
1892
1893/**
1894 * Gets effective Guest OS page information.
1895 *
1896 * When GCPtr is in a big page, the function will return as if it was a normal
1897 * 4KB page. If the need for distinguishing between big and normal page becomes
1898 * necessary at a later point, a PGMGstGetPage() will be created for that
1899 * purpose.
1900 *
1901 * @returns VBox status code.
1902 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1903 * @param GCPtr Guest Context virtual address of the page.
1904 * @param pWalk Where to store the page walk information.
1905 */
1906VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk)
1907{
1908 VMCPU_ASSERT_EMT(pVCpu);
1909 Assert(pWalk);
1910 uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
1911 AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
1912 AssertReturn(g_aPgmGuestModeData[idx].pfnGetPage, VERR_PGM_MODE_IPE);
1913 return g_aPgmGuestModeData[idx].pfnGetPage(pVCpu, GCPtr, pWalk);
1914}
1915
1916
1917/**
1918 * Maps the guest CR3.
1919 *
1920 * @returns VBox status code.
1921 * @param pVCpu The cross context virtual CPU structure.
1922 * @param GCPhysCr3 The guest CR3 value.
1923 * @param pHCPtrGuestCr3 Where to store the mapped memory.
1924 */
1925DECLINLINE(int) pgmGstMapCr3(PVMCPUCC pVCpu, RTGCPHYS GCPhysCr3, PRTHCPTR pHCPtrGuestCr3)
1926{
1927 /** @todo this needs some reworking wrt. locking? */
1928 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1929 PGM_LOCK_VOID(pVM);
1930 PPGMPAGE pPageCr3 = pgmPhysGetPage(pVM, GCPhysCr3);
1931 AssertReturnStmt(pPageCr3, PGM_UNLOCK(pVM), VERR_PGM_INVALID_CR3_ADDR);
1932
1933 RTHCPTR HCPtrGuestCr3;
1934 int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCr3, GCPhysCr3, (void **)&HCPtrGuestCr3);
1935 PGM_UNLOCK(pVM);
1936
1937 *pHCPtrGuestCr3 = HCPtrGuestCr3;
1938 return rc;
1939}
1940
1941
1942/**
1943 * Unmaps the guest CR3.
1944 *
1945 * @returns VBox status code.
1946 * @param pVCpu The cross context virtual CPU structure.
1947 */
1948DECLINLINE(int) pgmGstUnmapCr3(PVMCPUCC pVCpu)
1949{
1950 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1951 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1952 AssertReturn(g_aPgmBothModeData[idxBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
1953 return g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
1954}
1955
1956
1957/**
1958 * Performs a guest page table walk.
1959 *
1960 * The guest should be in paged protect mode or long mode when making a call to
1961 * this function.
1962 *
1963 * @returns VBox status code.
1964 * @retval VINF_SUCCESS on success.
1965 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
1966 * @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
1967 * not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
1968 *
1969 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1970 * @param GCPtr The guest virtual address to walk by.
1971 * @param pWalk Where to return the walk result. This is valid for some
1972 * error codes as well.
1973 * @param pGstWalk The guest mode specific page walk information.
1974 */
1975int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk)
1976{
1977 VMCPU_ASSERT_EMT(pVCpu);
1978 switch (pVCpu->pgm.s.enmGuestMode)
1979 {
1980 case PGMMODE_32_BIT:
1981 pGstWalk->enmType = PGMPTWALKGSTTYPE_32BIT;
1982 return PGM_GST_NAME_32BIT(Walk)(pVCpu, GCPtr, pWalk, &pGstWalk->u.Legacy);
1983
1984 case PGMMODE_PAE:
1985 case PGMMODE_PAE_NX:
1986 pGstWalk->enmType = PGMPTWALKGSTTYPE_PAE;
1987 return PGM_GST_NAME_PAE(Walk)(pVCpu, GCPtr, pWalk, &pGstWalk->u.Pae);
1988
1989 case PGMMODE_AMD64:
1990 case PGMMODE_AMD64_NX:
1991 pGstWalk->enmType = PGMPTWALKGSTTYPE_AMD64;
1992 return PGM_GST_NAME_AMD64(Walk)(pVCpu, GCPtr, pWalk, &pGstWalk->u.Amd64);
1993
1994 case PGMMODE_REAL:
1995 case PGMMODE_PROTECTED:
1996 pGstWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
1997 return VERR_PGM_NOT_USED_IN_MODE;
1998
1999 case PGMMODE_EPT:
2000 case PGMMODE_NESTED_32BIT:
2001 case PGMMODE_NESTED_PAE:
2002 case PGMMODE_NESTED_AMD64:
2003 default:
2004 AssertFailed();
2005 pGstWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
2006 return VERR_PGM_NOT_USED_IN_MODE;
2007 }
2008}
2009
2010
2011#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2012/**
2013 * Performs a guest second-level address translation (SLAT).
2014 *
2015 * The guest paging mode must be 32-bit, PAE or AMD64 when making a call to this
2016 * function.
2017 *
2018 * @returns VBox status code.
2019 * @retval VINF_SUCCESS on success.
2020 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
2021 * @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
2022 * not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
2023 *
2024 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2025 * @param GCPhysNested The nested-guest physical address being translated
2026 * (input).
2027 * @param fIsLinearAddrValid Whether the linear address in @a GCPtrNested is
2028 * valid. This indicates the SLAT is caused when
2029 * translating a nested-guest linear address.
2030 * @param GCPtrNested The nested-guest virtual address that initiated the
2031 * SLAT. If none, pass NIL_RTGCPTR.
2032 * @param pWalk Where to return the walk result. This is valid for
2033 * some error codes as well.
2034 * @param pGstWalk The second-level paging-mode specific walk
2035 * information.
2036 */
2037static int pgmGstSlatWalk(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested,
2038 PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk)
2039{
2040 /* SLAT mode must be valid at this point as this should only be used -after- we have determined SLAT mode. */
2041 Assert( pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_DIRECT
2042 && pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_INVALID);
2043 switch (pVCpu->pgm.s.enmGuestSlatMode)
2044 {
2045 case PGMSLAT_EPT:
2046 pGstWalk->enmType = PGMPTWALKGSTTYPE_EPT;
2047 return PGM_GST_SLAT_NAME_EPT(Walk)(pVCpu, GCPhysNested, fIsLinearAddrValid, GCPtrNested, pWalk, &pGstWalk->u.Ept);
2048
2049 default:
2050 AssertFailed();
2051 pGstWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
2052 return VERR_PGM_NOT_USED_IN_MODE;
2053 }
2054}
2055
2056
2057/**
2058 * Performs a guest second-level address translation (SLAT) for a nested-guest
2059 * physical address.
2060 *
2061 * This version requires the SLAT mode to be provided by the caller because we could
2062 * be in the process of switching paging modes (MOV CRX) and cannot presume control
2063 * register values.
2064 *
2065 * @returns VBox status code.
2066 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2067 * @param enmSlatMode The second-level paging mode to use.
2068 * @param GCPhysNested The nested-guest physical address to translate.
2069 * @param pWalk Where to store the walk result.
2070 * @param pGstWalk Where to store the second-level paging-mode specific
2071 * walk information.
2072 */
2073static int pgmGstSlatWalkPhys(PVMCPUCC pVCpu, PGMSLAT enmSlatMode, RTGCPHYS GCPhysNested, PPGMPTWALK pWalk,
2074 PPGMPTWALKGST pGstWalk)
2075{
2076 AssertPtr(pWalk);
2077 AssertPtr(pGstWalk);
2078 switch (enmSlatMode)
2079 {
2080 case PGMSLAT_EPT:
2081 pGstWalk->enmType = PGMPTWALKGSTTYPE_EPT;
2082 return PGM_GST_SLAT_NAME_EPT(Walk)(pVCpu, GCPhysNested, false /* fIsLinearaddrValid */, 0 /* GCPtrNested */,
2083 pWalk, &pGstWalk->u.Ept);
2084
2085 default:
2086 AssertFailed();
2087 return VERR_PGM_NOT_USED_IN_MODE;
2088 }
2089}
2090#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
2091
2092
2093/**
2094 * Tries to continue the previous walk.
2095 *
2096 * @note Requires the caller to hold the PGM lock from the first
2097 * pgmGstPtWalk() call to the last pgmGstPtWalkNext() call. Otherwise
2098 * we cannot use the pointers.
2099 *
2100 * @returns VBox status code.
2101 * @retval VINF_SUCCESS on success.
2102 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
2103 * @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
2104 * not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
2105 *
2106 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2107 * @param GCPtr The guest virtual address to walk by.
2108 * @param pWalk Pointer to the previous walk result and where to return
2109 * the result of this walk. This is valid for some error
2110 * codes as well.
2111 * @param pGstWalk The guest-mode specific walk information.
2112 */
2113int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk)
2114{
2115 /*
2116 * We can only handle successfully walks.
2117 * We also limit ourselves to the next page.
2118 */
2119 if ( pWalk->fSucceeded
2120 && GCPtr - pWalk->GCPtr == GUEST_PAGE_SIZE)
2121 {
2122 Assert(pWalk->uLevel == 0);
2123 if (pGstWalk->enmType == PGMPTWALKGSTTYPE_AMD64)
2124 {
2125 /*
2126 * AMD64
2127 */
2128 if (!pWalk->fGigantPage && !pWalk->fBigPage)
2129 {
2130 /*
2131 * We fall back to full walk if the PDE table changes, if any
2132 * reserved bits are set, or if the effective page access changes.
2133 */
2134 const uint64_t fPteSame = X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_PWT
2135 | X86_PTE_PCD | X86_PTE_A | X86_PTE_PAE_NX;
2136 const uint64_t fPdeSame = X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT
2137 | X86_PDE_PCD | X86_PDE_A | X86_PDE_PAE_NX | X86_PDE_PS;
2138
2139 if ((GCPtr >> X86_PD_PAE_SHIFT) == (pWalk->GCPtr >> X86_PD_PAE_SHIFT))
2140 {
2141 if (pGstWalk->u.Amd64.pPte)
2142 {
2143 X86PTEPAE Pte;
2144 Pte.u = pGstWalk->u.Amd64.pPte[1].u;
2145 if ( (Pte.u & fPteSame) == (pGstWalk->u.Amd64.Pte.u & fPteSame)
2146 && !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2147 {
2148 pWalk->GCPtr = GCPtr;
2149 pWalk->GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2150 pGstWalk->u.Amd64.Pte.u = Pte.u;
2151 pGstWalk->u.Amd64.pPte++;
2152 return VINF_SUCCESS;
2153 }
2154 }
2155 }
2156 else if ((GCPtr >> X86_PDPT_SHIFT) == (pWalk->GCPtr >> X86_PDPT_SHIFT))
2157 {
2158 Assert(!((GCPtr >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK)); /* Must be first PT entry. */
2159 if (pGstWalk->u.Amd64.pPde)
2160 {
2161 X86PDEPAE Pde;
2162 Pde.u = pGstWalk->u.Amd64.pPde[1].u;
2163 if ( (Pde.u & fPdeSame) == (pGstWalk->u.Amd64.Pde.u & fPdeSame)
2164 && !(Pde.u & (pVCpu)->pgm.s.fGstAmd64MbzPdeMask))
2165 {
2166 /* Get the new PTE and check out the first entry. */
2167 int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, PGM_A20_APPLY(pVCpu, (Pde.u & X86_PDE_PAE_PG_MASK)),
2168 &pGstWalk->u.Amd64.pPt);
2169 if (RT_SUCCESS(rc))
2170 {
2171 pGstWalk->u.Amd64.pPte = &pGstWalk->u.Amd64.pPt->a[0];
2172 X86PTEPAE Pte;
2173 Pte.u = pGstWalk->u.Amd64.pPte->u;
2174 if ( (Pte.u & fPteSame) == (pGstWalk->u.Amd64.Pte.u & fPteSame)
2175 && !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2176 {
2177 pWalk->GCPtr = GCPtr;
2178 pWalk->GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2179 pGstWalk->u.Amd64.Pte.u = Pte.u;
2180 pGstWalk->u.Amd64.Pde.u = Pde.u;
2181 pGstWalk->u.Amd64.pPde++;
2182 return VINF_SUCCESS;
2183 }
2184 }
2185 }
2186 }
2187 }
2188 }
2189 else if (!pWalk->fGigantPage)
2190 {
2191 if ((GCPtr & X86_PAGE_2M_BASE_MASK) == (pWalk->GCPtr & X86_PAGE_2M_BASE_MASK))
2192 {
2193 pWalk->GCPtr = GCPtr;
2194 pWalk->GCPhys += GUEST_PAGE_SIZE;
2195 return VINF_SUCCESS;
2196 }
2197 }
2198 else
2199 {
2200 if ((GCPtr & X86_PAGE_1G_BASE_MASK) == (pWalk->GCPtr & X86_PAGE_1G_BASE_MASK))
2201 {
2202 pWalk->GCPtr = GCPtr;
2203 pWalk->GCPhys += GUEST_PAGE_SIZE;
2204 return VINF_SUCCESS;
2205 }
2206 }
2207 }
2208 }
2209 /* Case we don't handle. Do full walk. */
2210 return pgmGstPtWalk(pVCpu, GCPtr, pWalk, pGstWalk);
2211}
2212
2213
2214/**
2215 * Modify page flags for a range of pages in the guest's tables
2216 *
2217 * The existing flags are ANDed with the fMask and ORed with the fFlags.
2218 *
2219 * @returns VBox status code.
2220 * @param pVCpu The cross context virtual CPU structure.
2221 * @param GCPtr Virtual address of the first page in the range.
2222 * @param cb Size (in bytes) of the range to apply the modification to.
2223 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
2224 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
2225 * Be very CAREFUL when ~'ing constants which could be 32-bit!
2226 */
2227VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
2228{
2229 STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,GstModifyPage), a);
2230 VMCPU_ASSERT_EMT(pVCpu);
2231
2232 /*
2233 * Validate input.
2234 */
2235 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
2236 Assert(cb);
2237
2238 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
2239
2240 /*
2241 * Adjust input.
2242 */
2243 cb += GCPtr & GUEST_PAGE_OFFSET_MASK;
2244 cb = RT_ALIGN_Z(cb, GUEST_PAGE_SIZE);
2245 GCPtr &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
2246
2247 /*
2248 * Call worker.
2249 */
2250 uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
2251 AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
2252 AssertReturn(g_aPgmGuestModeData[idx].pfnModifyPage, VERR_PGM_MODE_IPE);
2253 int rc = g_aPgmGuestModeData[idx].pfnModifyPage(pVCpu, GCPtr, cb, fFlags, fMask);
2254
2255 STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,GstModifyPage), a);
2256 return rc;
2257}
2258
2259
2260/**
2261 * Checks whether the given PAE PDPEs are potentially valid for the guest.
2262 *
2263 * @returns @c true if the PDPE is valid, @c false otherwise.
2264 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2265 * @param paPaePdpes The PAE PDPEs to validate.
2266 *
2267 * @remarks This function -only- checks the reserved bits in the PDPE entries.
2268 */
2269VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes)
2270{
2271 Assert(paPaePdpes);
2272 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
2273 {
2274 X86PDPE const PaePdpe = paPaePdpes[i];
2275 if ( !(PaePdpe.u & X86_PDPE_P)
2276 || !(PaePdpe.u & pVCpu->pgm.s.fGstPaeMbzPdpeMask))
2277 { /* likely */ }
2278 else
2279 return false;
2280 }
2281 return true;
2282}
2283
2284
2285/**
2286 * Performs the lazy mapping of the 32-bit guest PD.
2287 *
2288 * @returns VBox status code.
2289 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2290 * @param ppPd Where to return the pointer to the mapping. This is
2291 * always set.
2292 */
2293int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd)
2294{
2295 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2296 PGM_LOCK_VOID(pVM);
2297
2298 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
2299
2300 RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, pVCpu->pgm.s.GCPhysCR3);
2301 PPGMPAGE pPage;
2302 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2303 if (RT_SUCCESS(rc))
2304 {
2305 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)ppPd);
2306 if (RT_SUCCESS(rc))
2307 {
2308# ifdef IN_RING3
2309 pVCpu->pgm.s.pGst32BitPdR0 = NIL_RTR0PTR;
2310 pVCpu->pgm.s.pGst32BitPdR3 = *ppPd;
2311# else
2312 pVCpu->pgm.s.pGst32BitPdR3 = NIL_RTR0PTR;
2313 pVCpu->pgm.s.pGst32BitPdR0 = *ppPd;
2314# endif
2315 PGM_UNLOCK(pVM);
2316 return VINF_SUCCESS;
2317 }
2318 AssertRC(rc);
2319 }
2320 PGM_UNLOCK(pVM);
2321
2322 *ppPd = NULL;
2323 return rc;
2324}
2325
2326
2327/**
2328 * Performs the lazy mapping of the PAE guest PDPT.
2329 *
2330 * @returns VBox status code.
2331 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2332 * @param ppPdpt Where to return the pointer to the mapping. This is
2333 * always set.
2334 */
2335int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt)
2336{
2337 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
2338 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2339 PGM_LOCK_VOID(pVM);
2340
2341 RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, pVCpu->pgm.s.GCPhysCR3);
2342 PPGMPAGE pPage;
2343 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2344 if (RT_SUCCESS(rc))
2345 {
2346 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)ppPdpt);
2347 if (RT_SUCCESS(rc))
2348 {
2349# ifdef IN_RING3
2350 pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
2351 pVCpu->pgm.s.pGstPaePdptR3 = *ppPdpt;
2352# else
2353 pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
2354 pVCpu->pgm.s.pGstPaePdptR0 = *ppPdpt;
2355# endif
2356 PGM_UNLOCK(pVM);
2357 return VINF_SUCCESS;
2358 }
2359 AssertRC(rc);
2360 }
2361
2362 PGM_UNLOCK(pVM);
2363 *ppPdpt = NULL;
2364 return rc;
2365}
2366
2367
2368/**
2369 * Performs the lazy mapping / updating of a PAE guest PD.
2370 *
2371 * @returns Pointer to the mapping.
2372 * @returns VBox status code.
2373 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2374 * @param iPdpt Which PD entry to map (0..3).
2375 * @param ppPd Where to return the pointer to the mapping. This is
2376 * always set.
2377 */
2378int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
2379{
2380 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2381 PGM_LOCK_VOID(pVM);
2382
2383 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
2384 Assert(pGuestPDPT);
2385 Assert(pGuestPDPT->a[iPdpt].u & X86_PDPE_P);
2386 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
2387 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
2388
2389 PPGMPAGE pPage;
2390 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2391 if (RT_SUCCESS(rc))
2392 {
2393 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)ppPd);
2394 AssertRC(rc);
2395 if (RT_SUCCESS(rc))
2396 {
2397# ifdef IN_RING3
2398 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = NIL_RTR0PTR;
2399 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = *ppPd;
2400# else
2401 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = NIL_RTR3PTR;
2402 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = *ppPd;
2403# endif
2404 if (fChanged)
2405 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
2406 PGM_UNLOCK(pVM);
2407 return VINF_SUCCESS;
2408 }
2409 }
2410
2411 /* Invalid page or some failure, invalidate the entry. */
2412 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
2413 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = NIL_RTR3PTR;
2414 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = NIL_RTR0PTR;
2415
2416 PGM_UNLOCK(pVM);
2417 return rc;
2418}
2419
2420
2421/**
2422 * Performs the lazy mapping of the 32-bit guest PD.
2423 *
2424 * @returns VBox status code.
2425 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2426 * @param ppPml4 Where to return the pointer to the mapping. This will
2427 * always be set.
2428 */
2429int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4)
2430{
2431 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
2432 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2433 PGM_LOCK_VOID(pVM);
2434
2435 RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, pVCpu->pgm.s.GCPhysCR3);
2436 PPGMPAGE pPage;
2437 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2438 if (RT_SUCCESS(rc))
2439 {
2440 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)ppPml4);
2441 if (RT_SUCCESS(rc))
2442 {
2443# ifdef IN_RING3
2444 pVCpu->pgm.s.pGstAmd64Pml4R0 = NIL_RTR0PTR;
2445 pVCpu->pgm.s.pGstAmd64Pml4R3 = *ppPml4;
2446# else
2447 pVCpu->pgm.s.pGstAmd64Pml4R3 = NIL_RTR3PTR;
2448 pVCpu->pgm.s.pGstAmd64Pml4R0 = *ppPml4;
2449# endif
2450 PGM_UNLOCK(pVM);
2451 return VINF_SUCCESS;
2452 }
2453 }
2454
2455 PGM_UNLOCK(pVM);
2456 *ppPml4 = NULL;
2457 return rc;
2458}
2459
2460
2461#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2462 /**
2463 * Performs the lazy mapping of the guest PML4 table when using EPT paging.
2464 *
2465 * @returns VBox status code.
2466 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2467 * @param ppEptPml4 Where to return the pointer to the mapping. This will
2468 * always be set.
2469 */
2470int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppEptPml4)
2471{
2472 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstEptPml4));
2473 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2474 PGM_LOCK_VOID(pVM);
2475
2476 RTGCPHYS const GCPhysEpt = pVCpu->pgm.s.uEptPtr & EPT_EPTP_PG_MASK;
2477 PPGMPAGE pPage;
2478 int rc = pgmPhysGetPageEx(pVM, GCPhysEpt, &pPage);
2479 if (RT_SUCCESS(rc))
2480 {
2481 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysEpt, (void **)ppEptPml4);
2482 if (RT_SUCCESS(rc))
2483 {
2484# ifdef IN_RING3
2485 pVCpu->pgm.s.pGstEptPml4R0 = NIL_RTR0PTR;
2486 pVCpu->pgm.s.pGstEptPml4R3 = *ppEptPml4;
2487# else
2488 pVCpu->pgm.s.pGstEptPml4R3 = NIL_RTR3PTR;
2489 pVCpu->pgm.s.pGstEptPml4R0 = *ppEptPml4;
2490# endif
2491 PGM_UNLOCK(pVM);
2492 return VINF_SUCCESS;
2493 }
2494 }
2495
2496 PGM_UNLOCK(pVM);
2497 *ppEptPml4 = NULL;
2498 return rc;
2499}
2500#endif
2501
2502
2503/**
2504 * Gets the current CR3 register value for the shadow memory context.
2505 * @returns CR3 value.
2506 * @param pVCpu The cross context virtual CPU structure.
2507 */
2508VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
2509{
2510 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2511 AssertPtrReturn(pPoolPage, NIL_RTHCPHYS);
2512 return pPoolPage->Core.Key;
2513}
2514
2515
2516/**
2517 * Forces lazy remapping of the guest's PAE page-directory structures.
2518 *
2519 * @param pVCpu The cross context virtual CPU structure.
2520 */
2521static void pgmGstFlushPaePdpes(PVMCPU pVCpu)
2522{
2523 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGCPhysGstPaePDs); i++)
2524 {
2525 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2526 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2527 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2528 }
2529}
2530
2531
2532#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2533/**
2534 * Performs second-level address translation for the given CR3 and updates the
2535 * nested-guest CR3 when successful.
2536 *
2537 * @returns VBox status code.
2538 * @param pVCpu The cross context virtual CPU structure.
2539 * @param uCr3 The masked nested-guest CR3 value.
2540 * @param pGCPhysCR3 Where to store the translated CR3.
2541 *
2542 * @warning This updates PGMCPU::GCPhysNstGstCR3 when the translation succeeds. Be
2543 * mindful of this in code that's hyper sensitive to the order of
2544 * operations.
2545 */
2546static int pgmGstSlatTranslateCr3(PVMCPUCC pVCpu, uint64_t uCr3, PRTGCPHYS pGCPhysCr3)
2547{
2548# if 0
2549 if (uCr3 != pVCpu->pgm.s.GCPhysNstGstCR3)
2550# endif
2551 {
2552 PGMPTWALK Walk;
2553 PGMPTWALKGST GstWalk;
2554 int const rc = pgmGstSlatWalkPhys(pVCpu, PGMSLAT_EPT, uCr3, &Walk, &GstWalk);
2555 if (RT_SUCCESS(rc))
2556 {
2557 /* Update nested-guest CR3. */
2558 pVCpu->pgm.s.GCPhysNstGstCR3 = uCr3;
2559
2560 /* Pass back the translated result. */
2561 *pGCPhysCr3 = Walk.GCPhys;
2562 return VINF_SUCCESS;
2563 }
2564
2565 /* Translation failed. */
2566 *pGCPhysCr3 = NIL_RTGCPHYS;
2567 return rc;
2568 }
2569
2570# if 0
2571 /*
2572 * If the nested-guest CR3 has not changed, then the previously
2573 * translated CR3 result (i.e. GCPhysCR3) is passed back.
2574 */
2575 *pGCPhysCr3 = pVCpu->pgm.s.GCPhysCR3;
2576 return VINF_SUCCESS;
2577# endif
2578}
2579#endif
2580
2581
2582/**
2583 * Performs and schedules necessary updates following a CR3 load or reload.
2584 *
2585 * This will normally involve mapping the guest PD or nPDPT
2586 *
2587 * @returns VBox status code.
2588 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
2589 * safely be ignored and overridden since the FF will be set too then.
2590 * @param pVCpu The cross context virtual CPU structure.
2591 * @param cr3 The new cr3.
2592 * @param fGlobal Indicates whether this is a global flush or not.
2593 */
2594VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal)
2595{
2596 STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLB), a);
2597 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2598
2599 VMCPU_ASSERT_EMT(pVCpu);
2600
2601 /*
2602 * Always flag the necessary updates; necessary for hardware acceleration
2603 */
2604 /** @todo optimize this, it shouldn't always be necessary. */
2605 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2606 if (fGlobal)
2607 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2608
2609 /*
2610 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2611 */
2612 RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2613 RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, cr3);
2614#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2615 if ( pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT
2616 && PGMMODE_WITH_PAGING(pVCpu->pgm.s.enmGuestMode))
2617 {
2618 RTGCPHYS GCPhysOut;
2619 int const rc = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
2620 if (RT_SUCCESS(rc))
2621 GCPhysCR3 = GCPhysOut;
2622 else
2623 {
2624 /* CR3 SLAT translation failed but we try to pretend it
2625 succeeded for the reasons mentioned in PGMHCChangeMode(). */
2626 AssertMsgFailed(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", cr3, rc));
2627 int const rc2 = pgmGstUnmapCr3(pVCpu);
2628 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2629 pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
2630 return rc2;
2631 }
2632 }
2633#endif
2634
2635 LogFlowFunc(("cr3=%RX64 old=%RX64 fGlobal=%d\n", cr3, GCPhysOldCR3, fGlobal));
2636 int rc = VINF_SUCCESS;
2637 if (GCPhysOldCR3 != GCPhysCR3)
2638 {
2639 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2640 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2641 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2642
2643 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2644 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2645 if (RT_LIKELY(rc == VINF_SUCCESS))
2646 { }
2647 else
2648 {
2649 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
2650 Assert(VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
2651 pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped) = false;
2652 pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
2653 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
2654 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
2655 }
2656
2657 if (fGlobal)
2658 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
2659 else
2660 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBNewCR3));
2661 }
2662 else
2663 {
2664#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2665 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2666 if (pPool->cDirtyPages)
2667 {
2668 PGM_LOCK_VOID(pVM);
2669 pgmPoolResetDirtyPages(pVM);
2670 PGM_UNLOCK(pVM);
2671 }
2672#endif
2673 if (fGlobal)
2674 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
2675 else
2676 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBSameCR3));
2677
2678 /*
2679 * Flush PAE PDPTEs.
2680 */
2681 if (PGMMODE_IS_PAE(pVCpu->pgm.s.enmGuestMode))
2682 pgmGstFlushPaePdpes(pVCpu);
2683 }
2684
2685 IEMTlbInvalidateAll(pVCpu);
2686 STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLB), a);
2687 return rc;
2688}
2689
2690
2691/**
2692 * Performs and schedules necessary updates following a CR3 load or reload when
2693 * using nested or extended paging.
2694 *
2695 * This API is an alternative to PGMFlushTLB that avoids actually flushing the
2696 * TLB and triggering a SyncCR3.
2697 *
2698 * This will normally involve mapping the guest PD or nPDPT
2699 *
2700 * @returns VBox status code.
2701 * @retval VINF_SUCCESS.
2702 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync (not for nested
2703 * paging modes). This can safely be ignored and overridden since the
2704 * FF will be set too then.
2705 * @param pVCpu The cross context virtual CPU structure.
2706 * @param cr3 The new CR3.
2707 */
2708VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3)
2709{
2710 VMCPU_ASSERT_EMT(pVCpu);
2711
2712 /* We assume we're only called in nested paging mode. */
2713 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2714
2715 /*
2716 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2717 */
2718 RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2719 RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, cr3);
2720#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2721 if (CPUMIsGuestVmxEptPagingEnabled(pVCpu))
2722 {
2723 RTGCPHYS GCPhysOut;
2724 int const rc = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
2725 if (RT_SUCCESS(rc))
2726 GCPhysCR3 = GCPhysOut;
2727 else
2728 {
2729 /* CR3 SLAT translation failed but we try to pretend it
2730 succeeded for the reasons mentioned in PGMHCChangeMode(). */
2731 Log(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", cr3, rc));
2732 int const rc2 = pgmGstUnmapCr3(pVCpu);
2733 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2734 pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
2735 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2736 return rc2;
2737 }
2738 }
2739#endif
2740
2741 LogFlowFunc(("cr3=%RX64 old=%RX64\n", cr3, GCPhysOldCR3));
2742 int rc = VINF_SUCCESS;
2743 if (GCPhysOldCR3 != GCPhysCR3)
2744 {
2745 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2746 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2747 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2748
2749 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2750 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2751
2752 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
2753 }
2754 /*
2755 * Flush PAE PDPTEs.
2756 */
2757 else if (PGMMODE_IS_PAE(pVCpu->pgm.s.enmGuestMode))
2758 pgmGstFlushPaePdpes(pVCpu);
2759
2760 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2761 return rc;
2762}
2763
2764
2765/**
2766 * Synchronize the paging structures.
2767 *
2768 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
2769 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
2770 * in several places, most importantly whenever the CR3 is loaded.
2771 *
2772 * @returns VBox status code. May return VINF_PGM_SYNC_CR3 in RC/R0.
2773 * @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
2774 * the VMM into guest context.
2775 * @param pVCpu The cross context virtual CPU structure.
2776 * @param cr0 Guest context CR0 register
2777 * @param cr3 Guest context CR3 register
2778 * @param cr4 Guest context CR4 register
2779 * @param fGlobal Including global page directories or not
2780 */
2781VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2782{
2783 int rc;
2784
2785 VMCPU_ASSERT_EMT(pVCpu);
2786
2787 /*
2788 * The pool may have pending stuff and even require a return to ring-3 to
2789 * clear the whole thing.
2790 */
2791 rc = pgmPoolSyncCR3(pVCpu);
2792 if (rc != VINF_SUCCESS)
2793 return rc;
2794
2795 /*
2796 * We might be called when we shouldn't.
2797 *
2798 * The mode switching will ensure that the PD is resynced after every mode
2799 * switch. So, if we find ourselves here when in protected or real mode
2800 * we can safely clear the FF and return immediately.
2801 */
2802 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2803 {
2804 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
2805 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2806 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2807 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2808 return VINF_SUCCESS;
2809 }
2810
2811 /* If global pages are not supported, then all flushes are global. */
2812 if (!(cr4 & X86_CR4_PGE))
2813 fGlobal = true;
2814 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
2815 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2816
2817 /*
2818 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
2819 * This should be done before SyncCR3.
2820 */
2821 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2822 {
2823 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2824
2825 RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2826 RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, cr3);
2827#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2828 if (CPUMIsGuestVmxEptPagingEnabled(pVCpu))
2829 {
2830 RTGCPHYS GCPhysOut;
2831 int rc2 = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
2832 if (RT_SUCCESS(rc2))
2833 GCPhysCR3 = GCPhysOut;
2834 else
2835 {
2836 /* CR3 SLAT translation failed but we try to pretend it
2837 succeeded for the reasons mentioned in PGMHCChangeMode(). */
2838 AssertMsgFailed(("Failed to translate CR3 %#RX64. rc=%Rrc\n", cr3, rc2));
2839 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2840 pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
2841 return rc2;
2842 }
2843 }
2844#endif
2845 Assert(!pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped));
2846 if (GCPhysOldCR3 != GCPhysCR3)
2847 {
2848 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2849 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2850 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2851 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2852 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2853 }
2854
2855 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2856 if ( rc == VINF_PGM_SYNC_CR3
2857 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2858 {
2859 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2860#ifdef IN_RING3
2861 rc = pgmPoolSyncCR3(pVCpu);
2862#else
2863 if (rc == VINF_PGM_SYNC_CR3)
2864 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
2865 return VINF_PGM_SYNC_CR3;
2866#endif
2867 }
2868 AssertRCReturn(rc, rc);
2869 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2870 }
2871
2872 /*
2873 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2874 */
2875 STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
2876
2877 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2878 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2879 AssertReturn(g_aPgmBothModeData[idxBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
2880 rc = g_aPgmBothModeData[idxBth].pfnSyncCR3(pVCpu, cr0, cr3, cr4, fGlobal);
2881
2882 STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
2883 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2884 if (rc == VINF_SUCCESS)
2885 {
2886 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2887 {
2888 /* Go back to ring 3 if a pgm pool sync is again pending. */
2889 return VINF_PGM_SYNC_CR3;
2890 }
2891
2892 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2893 {
2894 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2895 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2896 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2897 }
2898 }
2899
2900 /*
2901 * Now flush the CR3 (guest context).
2902 */
2903 if (rc == VINF_SUCCESS)
2904 PGM_INVL_VCPU_TLBS(pVCpu);
2905 return rc;
2906}
2907
2908
2909/**
2910 * Maps all the PAE PDPE entries.
2911 *
2912 * @returns VBox status code.
2913 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2914 * @param paPaePdpes The new PAE PDPE values.
2915 *
2916 * @remarks This function may be invoked during the process of changing the guest
2917 * paging mode to PAE, hence the guest state (CR0, CR4 etc.) may not
2918 * reflect PAE paging just yet.
2919 */
2920VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes)
2921{
2922 Assert(paPaePdpes);
2923 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
2924 {
2925 X86PDPE const PaePdpe = paPaePdpes[i];
2926
2927 /*
2928 * In some cases (e.g. in SVM with nested paging) the validation of the PAE PDPEs
2929 * are deferred.[1] Also, different situations require different handling of invalid
2930 * PDPE entries. Here we assume the caller has already validated or doesn't require
2931 * validation of the PDPEs.
2932 *
2933 * In the case of nested EPT (i.e. for nested-guests), the PAE PDPEs have been
2934 * validated by the VMX transition.
2935 *
2936 * [1] -- See AMD spec. 15.25.10 "Legacy PAE Mode".
2937 */
2938 if ((PaePdpe.u & (pVCpu->pgm.s.fGstPaeMbzPdpeMask | X86_PDPE_P)) == X86_PDPE_P)
2939 {
2940 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2941 RTHCPTR HCPtr;
2942 RTGCPHYS const GCPhys = PGM_A20_APPLY(pVCpu, PaePdpe.u & X86_PDPE_PG_MASK);
2943
2944 PGM_LOCK_VOID(pVM);
2945 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
2946 AssertReturnStmt(pPage, PGM_UNLOCK(pVM), VERR_PGM_INVALID_PDPE_ADDR);
2947 int const rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
2948 PGM_UNLOCK(pVM);
2949 if (RT_SUCCESS(rc))
2950 {
2951#ifdef IN_RING3
2952 pVCpu->pgm.s.apGstPaePDsR3[i] = (PX86PDPAE)HCPtr;
2953 pVCpu->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
2954#else
2955 pVCpu->pgm.s.apGstPaePDsR3[i] = NIL_RTR3PTR;
2956 pVCpu->pgm.s.apGstPaePDsR0[i] = (PX86PDPAE)HCPtr;
2957#endif
2958 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
2959 continue;
2960 }
2961 AssertMsgFailed(("PGMPhysMapPaePdpes: rc2=%d GCPhys=%RGp i=%d\n", rc, GCPhys, i));
2962 }
2963 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2964 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2965 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2966 }
2967
2968 /*
2969 * Update CPUM with the PAE PDPEs.
2970 */
2971 CPUMSetGuestPaePdpes(pVCpu, paPaePdpes);
2972 return VINF_SUCCESS;
2973}
2974
2975
2976/**
2977 * Validates and maps the PDPT and PAE PDPEs referenced by the given CR3.
2978 *
2979 * @returns VBox status code.
2980 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2981 * @param cr3 The guest CR3 value.
2982 *
2983 * @remarks This function may be invoked during the process of changing the guest
2984 * paging mode to PAE but the guest state (CR0, CR4 etc.) may not reflect
2985 * PAE paging just yet.
2986 */
2987VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3)
2988{
2989 /*
2990 * Read the page-directory-pointer table (PDPT) at CR3.
2991 */
2992 RTGCPHYS GCPhysCR3 = (cr3 & X86_CR3_PAE_PAGE_MASK);
2993 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2994
2995#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2996 if (CPUMIsGuestVmxEptPagingEnabled(pVCpu))
2997 {
2998 RTGCPHYS GCPhysOut;
2999 int const rc = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
3000 if (RT_SUCCESS(rc))
3001 GCPhysCR3 = GCPhysOut;
3002 else
3003 {
3004 AssertMsgFailed(("Failed to load CR3 at %#RX64. rc=%Rrc\n", GCPhysCR3, rc));
3005 return rc;
3006 }
3007 }
3008#endif
3009
3010 RTHCPTR HCPtrGuestCr3;
3011 int rc = pgmGstMapCr3(pVCpu, GCPhysCR3, &HCPtrGuestCr3);
3012 if (RT_SUCCESS(rc))
3013 {
3014 /*
3015 * Validate the page-directory-pointer table entries (PDPE).
3016 */
3017 X86PDPE aPaePdpes[X86_PG_PAE_PDPE_ENTRIES];
3018 memcpy(&aPaePdpes[0], HCPtrGuestCr3, sizeof(aPaePdpes));
3019 if (PGMGstArePaePdpesValid(pVCpu, &aPaePdpes[0]))
3020 {
3021 /*
3022 * Map the PDPT.
3023 * We deliberately don't update PGM's GCPhysCR3 here as it's expected
3024 * that PGMFlushTLB will be called soon and only a change to CR3 then
3025 * will cause the shadow page tables to be updated.
3026 */
3027#ifdef IN_RING3
3028 pVCpu->pgm.s.pGstPaePdptR3 = (PX86PDPT)HCPtrGuestCr3;
3029 pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
3030#else
3031 pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
3032 pVCpu->pgm.s.pGstPaePdptR0 = (PX86PDPT)HCPtrGuestCr3;
3033#endif
3034
3035 /*
3036 * Map the PDPEs and update CPUM.
3037 */
3038 rc = PGMGstMapPaePdpes(pVCpu, &aPaePdpes[0]);
3039 if (RT_SUCCESS(rc))
3040 {
3041#ifdef IN_RING3
3042 pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = true;
3043 pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
3044#else
3045 pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
3046 pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = true;
3047#endif
3048 pVCpu->pgm.s.GCPhysPaeCR3 = GCPhysCR3;
3049 }
3050 }
3051 else
3052 rc = VERR_PGM_PAE_PDPE_RSVD;
3053 }
3054 return rc;
3055}
3056
3057
3058/**
3059 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
3060 *
3061 * @returns VBox status code, with the following informational code for
3062 * VM scheduling.
3063 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
3064 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
3065 *
3066 * @param pVCpu The cross context virtual CPU structure.
3067 * @param cr0 The new cr0.
3068 * @param cr4 The new cr4.
3069 * @param efer The new extended feature enable register.
3070 * @param fForce Whether to force a mode change.
3071 */
3072VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer, bool fForce)
3073{
3074 VMCPU_ASSERT_EMT(pVCpu);
3075
3076 /*
3077 * Calc the new guest mode.
3078 *
3079 * Note! We check PG before PE and without requiring PE because of the
3080 * special AMD-V paged real mode (APM vol 2, rev 3.28, 15.9).
3081 */
3082 PGMMODE enmGuestMode;
3083 if (cr0 & X86_CR0_PG)
3084 {
3085 if (!(cr4 & X86_CR4_PAE))
3086 {
3087 bool const fPse = !!(cr4 & X86_CR4_PSE);
3088 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
3089 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
3090 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
3091 enmGuestMode = PGMMODE_32_BIT;
3092 }
3093 else if (!(efer & MSR_K6_EFER_LME))
3094 {
3095 if (!(efer & MSR_K6_EFER_NXE))
3096 enmGuestMode = PGMMODE_PAE;
3097 else
3098 enmGuestMode = PGMMODE_PAE_NX;
3099 }
3100 else
3101 {
3102 if (!(efer & MSR_K6_EFER_NXE))
3103 enmGuestMode = PGMMODE_AMD64;
3104 else
3105 enmGuestMode = PGMMODE_AMD64_NX;
3106 }
3107 }
3108 else if (!(cr0 & X86_CR0_PE))
3109 enmGuestMode = PGMMODE_REAL;
3110 else
3111 enmGuestMode = PGMMODE_PROTECTED;
3112
3113 /*
3114 * Did it change?
3115 */
3116 if ( !fForce
3117 && pVCpu->pgm.s.enmGuestMode == enmGuestMode)
3118 return VINF_SUCCESS;
3119
3120 /* Flush the TLB */
3121 PGM_INVL_VCPU_TLBS(pVCpu);
3122 return PGMHCChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode, fForce);
3123}
3124
3125
3126/**
3127 * Converts a PGMMODE value to a PGM_TYPE_* \#define.
3128 *
3129 * @returns PGM_TYPE_*.
3130 * @param pgmMode The mode value to convert.
3131 */
3132DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3133{
3134 switch (pgmMode)
3135 {
3136 case PGMMODE_REAL: return PGM_TYPE_REAL;
3137 case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3138 case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3139 case PGMMODE_PAE:
3140 case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3141 case PGMMODE_AMD64:
3142 case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3143 case PGMMODE_NESTED_32BIT: return PGM_TYPE_NESTED_32BIT;
3144 case PGMMODE_NESTED_PAE: return PGM_TYPE_NESTED_PAE;
3145 case PGMMODE_NESTED_AMD64: return PGM_TYPE_NESTED_AMD64;
3146 case PGMMODE_EPT: return PGM_TYPE_EPT;
3147 case PGMMODE_NONE: return PGM_TYPE_NONE;
3148 default:
3149 AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3150 }
3151}
3152
3153
3154/**
3155 * Calculates the shadow paging mode.
3156 *
3157 * @returns The shadow paging mode.
3158 * @param pVM The cross context VM structure.
3159 * @param enmGuestMode The guest mode.
3160 * @param enmHostMode The host mode.
3161 * @param enmShadowMode The current shadow mode.
3162 */
3163static PGMMODE pgmCalcShadowMode(PVMCC pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode)
3164{
3165 switch (enmGuestMode)
3166 {
3167 case PGMMODE_REAL:
3168 case PGMMODE_PROTECTED:
3169 switch (enmHostMode)
3170 {
3171 case SUPPAGINGMODE_32_BIT:
3172 case SUPPAGINGMODE_32_BIT_GLOBAL:
3173 enmShadowMode = PGMMODE_32_BIT;
3174 break;
3175
3176 case SUPPAGINGMODE_PAE:
3177 case SUPPAGINGMODE_PAE_NX:
3178 case SUPPAGINGMODE_PAE_GLOBAL:
3179 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3180 enmShadowMode = PGMMODE_PAE;
3181 break;
3182
3183 case SUPPAGINGMODE_AMD64:
3184 case SUPPAGINGMODE_AMD64_GLOBAL:
3185 case SUPPAGINGMODE_AMD64_NX:
3186 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3187 enmShadowMode = PGMMODE_PAE;
3188 break;
3189
3190 default:
3191 AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3192 }
3193 break;
3194
3195 case PGMMODE_32_BIT:
3196 switch (enmHostMode)
3197 {
3198 case SUPPAGINGMODE_32_BIT:
3199 case SUPPAGINGMODE_32_BIT_GLOBAL:
3200 enmShadowMode = PGMMODE_32_BIT;
3201 break;
3202
3203 case SUPPAGINGMODE_PAE:
3204 case SUPPAGINGMODE_PAE_NX:
3205 case SUPPAGINGMODE_PAE_GLOBAL:
3206 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3207 enmShadowMode = PGMMODE_PAE;
3208 break;
3209
3210 case SUPPAGINGMODE_AMD64:
3211 case SUPPAGINGMODE_AMD64_GLOBAL:
3212 case SUPPAGINGMODE_AMD64_NX:
3213 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3214 enmShadowMode = PGMMODE_PAE;
3215 break;
3216
3217 default:
3218 AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3219 }
3220 break;
3221
3222 case PGMMODE_PAE:
3223 case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3224 switch (enmHostMode)
3225 {
3226 case SUPPAGINGMODE_32_BIT:
3227 case SUPPAGINGMODE_32_BIT_GLOBAL:
3228 enmShadowMode = PGMMODE_PAE;
3229 break;
3230
3231 case SUPPAGINGMODE_PAE:
3232 case SUPPAGINGMODE_PAE_NX:
3233 case SUPPAGINGMODE_PAE_GLOBAL:
3234 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3235 enmShadowMode = PGMMODE_PAE;
3236 break;
3237
3238 case SUPPAGINGMODE_AMD64:
3239 case SUPPAGINGMODE_AMD64_GLOBAL:
3240 case SUPPAGINGMODE_AMD64_NX:
3241 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3242 enmShadowMode = PGMMODE_PAE;
3243 break;
3244
3245 default:
3246 AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3247 }
3248 break;
3249
3250 case PGMMODE_AMD64:
3251 case PGMMODE_AMD64_NX:
3252 switch (enmHostMode)
3253 {
3254 case SUPPAGINGMODE_32_BIT:
3255 case SUPPAGINGMODE_32_BIT_GLOBAL:
3256 enmShadowMode = PGMMODE_AMD64;
3257 break;
3258
3259 case SUPPAGINGMODE_PAE:
3260 case SUPPAGINGMODE_PAE_NX:
3261 case SUPPAGINGMODE_PAE_GLOBAL:
3262 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3263 enmShadowMode = PGMMODE_AMD64;
3264 break;
3265
3266 case SUPPAGINGMODE_AMD64:
3267 case SUPPAGINGMODE_AMD64_GLOBAL:
3268 case SUPPAGINGMODE_AMD64_NX:
3269 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3270 enmShadowMode = PGMMODE_AMD64;
3271 break;
3272
3273 default:
3274 AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3275 }
3276 break;
3277
3278 default:
3279 AssertLogRelMsgFailedReturn(("enmGuestMode=%d\n", enmGuestMode), PGMMODE_INVALID);
3280 }
3281
3282 /*
3283 * Override the shadow mode when NEM, IEM or nested paging is active.
3284 */
3285 if (!VM_IS_HM_ENABLED(pVM))
3286 {
3287 Assert(VM_IS_NEM_ENABLED(pVM) || VM_IS_EXEC_ENGINE_IEM(pVM));
3288 pVM->pgm.s.fNestedPaging = true;
3289 enmShadowMode = PGMMODE_NONE;
3290 }
3291 else
3292 {
3293 bool fNestedPaging = HMIsNestedPagingActive(pVM);
3294 pVM->pgm.s.fNestedPaging = fNestedPaging;
3295 if (fNestedPaging)
3296 {
3297 if (HMIsVmxActive(pVM))
3298 enmShadowMode = PGMMODE_EPT;
3299 else
3300 {
3301 /* The nested SVM paging depends on the host one. */
3302 Assert(HMIsSvmActive(pVM));
3303 if ( enmGuestMode == PGMMODE_AMD64
3304 || enmGuestMode == PGMMODE_AMD64_NX)
3305 enmShadowMode = PGMMODE_NESTED_AMD64;
3306 else
3307 switch (pVM->pgm.s.enmHostMode)
3308 {
3309 case SUPPAGINGMODE_32_BIT:
3310 case SUPPAGINGMODE_32_BIT_GLOBAL:
3311 enmShadowMode = PGMMODE_NESTED_32BIT;
3312 break;
3313
3314 case SUPPAGINGMODE_PAE:
3315 case SUPPAGINGMODE_PAE_GLOBAL:
3316 case SUPPAGINGMODE_PAE_NX:
3317 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3318 enmShadowMode = PGMMODE_NESTED_PAE;
3319 break;
3320
3321 case SUPPAGINGMODE_AMD64:
3322 case SUPPAGINGMODE_AMD64_GLOBAL:
3323 case SUPPAGINGMODE_AMD64_NX:
3324 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3325 enmShadowMode = PGMMODE_NESTED_AMD64;
3326 break;
3327
3328 default:
3329 AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode), PGMMODE_INVALID);
3330 }
3331 }
3332 }
3333#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3334 else
3335 {
3336 /* Nested paging is a requirement for nested VT-x. */
3337 AssertLogRelMsgReturn(enmGuestMode != PGMMODE_EPT, ("enmHostMode=%d\n", pVM->pgm.s.enmHostMode), PGMMODE_INVALID);
3338 }
3339#endif
3340 }
3341
3342 return enmShadowMode;
3343}
3344
3345
3346/**
3347 * Performs the actual mode change.
3348 * This is called by PGMChangeMode and pgmR3InitPaging().
3349 *
3350 * @returns VBox status code. May suspend or power off the VM on error, but this
3351 * will trigger using FFs and not informational status codes.
3352 *
3353 * @param pVM The cross context VM structure.
3354 * @param pVCpu The cross context virtual CPU structure.
3355 * @param enmGuestMode The new guest mode. This is assumed to be different from
3356 * the current mode.
3357 * @param fForce Whether to force a shadow paging mode change.
3358 */
3359VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode, bool fForce)
3360{
3361 Log(("PGMHCChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3362 STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3363
3364 /*
3365 * Calc the shadow mode and switcher.
3366 */
3367 PGMMODE const enmShadowMode = pgmCalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode);
3368 bool const fShadowModeChanged = enmShadowMode != pVCpu->pgm.s.enmShadowMode || fForce;
3369
3370 /*
3371 * Exit old mode(s).
3372 */
3373 /* shadow */
3374 if (fShadowModeChanged)
3375 {
3376 LogFlow(("PGMHCChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3377 uintptr_t idxOldShw = pVCpu->pgm.s.idxShadowModeData;
3378 if ( idxOldShw < RT_ELEMENTS(g_aPgmShadowModeData)
3379 && g_aPgmShadowModeData[idxOldShw].pfnExit)
3380 {
3381 int rc = g_aPgmShadowModeData[idxOldShw].pfnExit(pVCpu);
3382 AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
3383 }
3384 }
3385 else
3386 LogFlow(("PGMHCChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3387
3388 /* guest */
3389 uintptr_t const idxOldGst = pVCpu->pgm.s.idxGuestModeData;
3390 if ( idxOldGst < RT_ELEMENTS(g_aPgmGuestModeData)
3391 && g_aPgmGuestModeData[idxOldGst].pfnExit)
3392 {
3393 int rc = g_aPgmGuestModeData[idxOldGst].pfnExit(pVCpu);
3394 AssertMsgReturn(RT_SUCCESS(rc), ("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc), rc);
3395 }
3396 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
3397 pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
3398 pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
3399 Assert(!pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped));
3400
3401 /*
3402 * Change the paging mode data indexes.
3403 */
3404 uintptr_t idxNewGst = pVCpu->pgm.s.idxGuestModeData = pgmModeToType(enmGuestMode);
3405 AssertReturn(idxNewGst < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
3406 AssertReturn(g_aPgmGuestModeData[idxNewGst].uType == idxNewGst, VERR_PGM_MODE_IPE);
3407 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnGetPage, VERR_PGM_MODE_IPE);
3408 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnModifyPage, VERR_PGM_MODE_IPE);
3409 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnExit, VERR_PGM_MODE_IPE);
3410 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnEnter, VERR_PGM_MODE_IPE);
3411#ifdef IN_RING3
3412 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnRelocate, VERR_PGM_MODE_IPE);
3413#endif
3414
3415 uintptr_t const idxNewShw = pVCpu->pgm.s.idxShadowModeData = pgmModeToType(enmShadowMode);
3416 AssertReturn(idxNewShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
3417 AssertReturn(g_aPgmShadowModeData[idxNewShw].uType == idxNewShw, VERR_PGM_MODE_IPE);
3418 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnGetPage, VERR_PGM_MODE_IPE);
3419 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnModifyPage, VERR_PGM_MODE_IPE);
3420 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnExit, VERR_PGM_MODE_IPE);
3421 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnEnter, VERR_PGM_MODE_IPE);
3422#ifdef IN_RING3
3423 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnRelocate, VERR_PGM_MODE_IPE);
3424#endif
3425
3426 uintptr_t const idxNewBth = pVCpu->pgm.s.idxBothModeData = (idxNewShw - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END + idxNewGst;
3427 AssertReturn(g_aPgmBothModeData[idxNewBth].uShwType == idxNewShw, VERR_PGM_MODE_IPE);
3428 AssertReturn(g_aPgmBothModeData[idxNewBth].uGstType == idxNewGst, VERR_PGM_MODE_IPE);
3429 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnInvalidatePage, VERR_PGM_MODE_IPE);
3430 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
3431 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
3432 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnVerifyAccessSyncPage, VERR_PGM_MODE_IPE);
3433 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnMapCR3, VERR_PGM_MODE_IPE);
3434 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
3435 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnEnter, VERR_PGM_MODE_IPE);
3436#ifdef VBOX_STRICT
3437 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnAssertCR3, VERR_PGM_MODE_IPE);
3438#endif
3439
3440 /*
3441 * Determine SLAT mode -before- entering the new shadow mode!
3442 */
3443 pVCpu->pgm.s.enmGuestSlatMode = !CPUMIsGuestVmxEptPagingEnabled(pVCpu) ? PGMSLAT_DIRECT : PGMSLAT_EPT;
3444
3445 /*
3446 * Enter new shadow mode (if changed).
3447 */
3448 if (fShadowModeChanged)
3449 {
3450 pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3451 int rc = g_aPgmShadowModeData[idxNewShw].pfnEnter(pVCpu, enmGuestMode >= PGMMODE_AMD64);
3452 AssertLogRelMsgRCReturnStmt(rc, ("Entering enmShadowMode=%s failed: %Rrc\n", PGMGetModeName(enmShadowMode), rc),
3453 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID, rc);
3454 }
3455
3456 /*
3457 * Always flag the necessary updates
3458 */
3459 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3460
3461 /*
3462 * Enter the new guest and shadow+guest modes.
3463 */
3464 /* Calc the new CR3 value. */
3465 RTGCPHYS GCPhysCR3;
3466 switch (enmGuestMode)
3467 {
3468 case PGMMODE_REAL:
3469 case PGMMODE_PROTECTED:
3470 GCPhysCR3 = NIL_RTGCPHYS;
3471 break;
3472
3473 case PGMMODE_32_BIT:
3474 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3475 break;
3476
3477 case PGMMODE_PAE_NX:
3478 case PGMMODE_PAE:
3479 if (!pVM->cpum.ro.GuestFeatures.fPae)
3480#ifdef IN_RING3 /** @todo r=bird: wrong place, probably hasn't really worked for a while. */
3481 return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3482 N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (System/Processor)"));
3483#else
3484 AssertLogRelMsgFailedReturn(("enmGuestMode=%s - Try enable PAE for the guest!\n", PGMGetModeName(enmGuestMode)), VERR_PGM_MODE_IPE);
3485
3486#endif
3487 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3488 break;
3489
3490#ifdef VBOX_WITH_64_BITS_GUESTS
3491 case PGMMODE_AMD64_NX:
3492 case PGMMODE_AMD64:
3493 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_AMD64_PAGE_MASK;
3494 break;
3495#endif
3496 default:
3497 AssertLogRelMsgFailedReturn(("enmGuestMode=%d\n", enmGuestMode), VERR_PGM_MODE_IPE);
3498 }
3499
3500#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3501 /*
3502 * If a nested-guest is using EPT paging:
3503 * - Update the second-level address translation (SLAT) mode.
3504 * - Indicate that the CR3 is nested-guest physical address.
3505 */
3506 if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
3507 {
3508 if (PGMMODE_WITH_PAGING(enmGuestMode))
3509 {
3510 /*
3511 * Translate CR3 to its guest-physical address.
3512 * We don't use pgmGstSlatTranslateCr3() here as we want to update GCPhysNstGstCR3 -after-
3513 * switching modes to keep it consistent with how GCPhysCR3 is updated.
3514 */
3515 PGMPTWALK Walk;
3516 PGMPTWALKGST GstWalk;
3517 int const rc = pgmGstSlatWalkPhys(pVCpu, PGMSLAT_EPT, GCPhysCR3, &Walk, &GstWalk);
3518 if (RT_SUCCESS(rc))
3519 { /* likely */ }
3520 else
3521 {
3522 /*
3523 * SLAT failed but we avoid reporting this to the caller because the caller
3524 * is not supposed to fail. The only time the caller needs to indicate a
3525 * failure to software is when PAE paging is used by the nested-guest, but
3526 * we handle the PAE case separately (e.g., see VMX transition in IEM).
3527 * In all other cases, the failure will be indicated when CR3 tries to be
3528 * translated on the next linear-address memory access.
3529 * See Intel spec. 27.2.1 "EPT Overview".
3530 */
3531 Log(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", GCPhysCR3, rc));
3532
3533 /* Trying to coax PGM to succeed for the time being... */
3534 Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3535 pVCpu->pgm.s.GCPhysNstGstCR3 = GCPhysCR3;
3536 pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3537 HMHCChangedPagingMode(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3538 return VINF_SUCCESS;
3539 }
3540 pVCpu->pgm.s.GCPhysNstGstCR3 = GCPhysCR3;
3541 GCPhysCR3 = Walk.GCPhys & X86_CR3_EPT_PAGE_MASK;
3542 }
3543 }
3544 else
3545 Assert(pVCpu->pgm.s.GCPhysNstGstCR3 == NIL_RTGCPHYS);
3546#endif
3547
3548 /*
3549 * Enter the new guest mode.
3550 */
3551 pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3552 int rc = g_aPgmGuestModeData[idxNewGst].pfnEnter(pVCpu, GCPhysCR3);
3553 int rc2 = g_aPgmBothModeData[idxNewBth].pfnEnter(pVCpu, GCPhysCR3);
3554
3555 /* Set the new guest CR3 (and nested-guest CR3). */
3556 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3557
3558 /* status codes. */
3559 AssertRC(rc);
3560 AssertRC(rc2);
3561 if (RT_SUCCESS(rc))
3562 {
3563 rc = rc2;
3564 if (RT_SUCCESS(rc)) /* no informational status codes. */
3565 rc = VINF_SUCCESS;
3566 }
3567
3568 /*
3569 * Notify HM.
3570 */
3571 HMHCChangedPagingMode(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3572 return rc;
3573}
3574
3575
3576/**
3577 * Called by CPUM or REM when CR0.WP changes to 1.
3578 *
3579 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3580 * @thread EMT
3581 */
3582VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu)
3583{
3584 /*
3585 * Netware WP0+RO+US hack cleanup when WP0 -> WP1.
3586 *
3587 * Use the counter to judge whether there might be pool pages with active
3588 * hacks in them. If there are, we will be running the risk of messing up
3589 * the guest by allowing it to write to read-only pages. Thus, we have to
3590 * clear the page pool ASAP if there is the slightest chance.
3591 */
3592 if (pVCpu->pgm.s.cNetwareWp0Hacks > 0)
3593 {
3594 Assert(pVCpu->CTX_SUFF(pVM)->cCpus == 1);
3595
3596 Log(("PGMCr0WpEnabled: %llu WP0 hacks active - clearing page pool\n", pVCpu->pgm.s.cNetwareWp0Hacks));
3597 pVCpu->pgm.s.cNetwareWp0Hacks = 0;
3598 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
3599 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3600 }
3601}
3602
3603
3604/**
3605 * Gets the current guest paging mode.
3606 *
3607 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
3608 *
3609 * @returns The current paging mode.
3610 * @param pVCpu The cross context virtual CPU structure.
3611 */
3612VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
3613{
3614 return pVCpu->pgm.s.enmGuestMode;
3615}
3616
3617
3618/**
3619 * Gets the current shadow paging mode.
3620 *
3621 * @returns The current paging mode.
3622 * @param pVCpu The cross context virtual CPU structure.
3623 */
3624VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
3625{
3626 return pVCpu->pgm.s.enmShadowMode;
3627}
3628
3629
3630/**
3631 * Gets the current host paging mode.
3632 *
3633 * @returns The current paging mode.
3634 * @param pVM The cross context VM structure.
3635 */
3636VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
3637{
3638 switch (pVM->pgm.s.enmHostMode)
3639 {
3640 case SUPPAGINGMODE_32_BIT:
3641 case SUPPAGINGMODE_32_BIT_GLOBAL:
3642 return PGMMODE_32_BIT;
3643
3644 case SUPPAGINGMODE_PAE:
3645 case SUPPAGINGMODE_PAE_GLOBAL:
3646 return PGMMODE_PAE;
3647
3648 case SUPPAGINGMODE_PAE_NX:
3649 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3650 return PGMMODE_PAE_NX;
3651
3652 case SUPPAGINGMODE_AMD64:
3653 case SUPPAGINGMODE_AMD64_GLOBAL:
3654 return PGMMODE_AMD64;
3655
3656 case SUPPAGINGMODE_AMD64_NX:
3657 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3658 return PGMMODE_AMD64_NX;
3659
3660 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
3661 }
3662
3663 return PGMMODE_INVALID;
3664}
3665
3666
3667/**
3668 * Get mode name.
3669 *
3670 * @returns read-only name string.
3671 * @param enmMode The mode which name is desired.
3672 */
3673VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
3674{
3675 switch (enmMode)
3676 {
3677 case PGMMODE_REAL: return "Real";
3678 case PGMMODE_PROTECTED: return "Protected";
3679 case PGMMODE_32_BIT: return "32-bit";
3680 case PGMMODE_PAE: return "PAE";
3681 case PGMMODE_PAE_NX: return "PAE+NX";
3682 case PGMMODE_AMD64: return "AMD64";
3683 case PGMMODE_AMD64_NX: return "AMD64+NX";
3684 case PGMMODE_NESTED_32BIT: return "Nested-32";
3685 case PGMMODE_NESTED_PAE: return "Nested-PAE";
3686 case PGMMODE_NESTED_AMD64: return "Nested-AMD64";
3687 case PGMMODE_EPT: return "EPT";
3688 case PGMMODE_NONE: return "None";
3689 default: return "unknown mode value";
3690 }
3691}
3692
3693
3694#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3695/**
3696 * Gets the SLAT mode name.
3697 *
3698 * @returns The read-only SLAT mode descriptive string.
3699 * @param enmSlatMode The SLAT mode value.
3700 */
3701VMM_INT_DECL(const char *) PGMGetSlatModeName(PGMSLAT enmSlatMode)
3702{
3703 switch (enmSlatMode)
3704 {
3705 case PGMSLAT_DIRECT: return "Direct";
3706 case PGMSLAT_EPT: return "EPT";
3707 case PGMSLAT_32BIT: return "32-bit";
3708 case PGMSLAT_PAE: return "PAE";
3709 case PGMSLAT_AMD64: return "AMD64";
3710 default: return "Unknown";
3711 }
3712}
3713#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
3714
3715
3716/**
3717 * Gets the physical address represented in the guest CR3 as PGM sees it.
3718 *
3719 * This is mainly for logging and debugging.
3720 *
3721 * @returns PGM's guest CR3 value.
3722 * @param pVCpu The cross context virtual CPU structure.
3723 */
3724VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu)
3725{
3726 return pVCpu->pgm.s.GCPhysCR3;
3727}
3728
3729
3730
3731/**
3732 * Notification from CPUM that the EFER.NXE bit has changed.
3733 *
3734 * @param pVCpu The cross context virtual CPU structure of the CPU for
3735 * which EFER changed.
3736 * @param fNxe The new NXE state.
3737 */
3738VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
3739{
3740/** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
3741 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
3742
3743 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
3744 if (fNxe)
3745 {
3746 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
3747 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
3748 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
3749 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3750 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
3751 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
3752 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
3753 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3754 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
3755 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
3756 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
3757
3758 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
3759 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
3760 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
3761 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
3762 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
3763 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
3764 }
3765 else
3766 {
3767 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
3768 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
3769 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
3770 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
3771 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
3772 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
3773 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
3774 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
3775 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
3776 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
3777 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
3778
3779 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
3780 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
3781 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
3782 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
3783 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
3784 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
3785 }
3786}
3787
3788
3789/**
3790 * Check if any pgm pool pages are marked dirty (not monitored)
3791 *
3792 * @returns bool locked/not locked
3793 * @param pVM The cross context VM structure.
3794 */
3795VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
3796{
3797 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
3798}
3799
3800
3801/**
3802 * Check if this VCPU currently owns the PGM lock.
3803 *
3804 * @returns bool owner/not owner
3805 * @param pVM The cross context VM structure.
3806 */
3807VMMDECL(bool) PGMIsLockOwner(PVMCC pVM)
3808{
3809 return PDMCritSectIsOwner(pVM, &pVM->pgm.s.CritSectX);
3810}
3811
3812
3813/**
3814 * Enable or disable large page usage
3815 *
3816 * @returns VBox status code.
3817 * @param pVM The cross context VM structure.
3818 * @param fUseLargePages Use/not use large pages
3819 */
3820VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages)
3821{
3822 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3823
3824 pVM->pgm.s.fUseLargePages = fUseLargePages;
3825 return VINF_SUCCESS;
3826}
3827
3828
3829/**
3830 * Acquire the PGM lock.
3831 *
3832 * @returns VBox status code
3833 * @param pVM The cross context VM structure.
3834 * @param fVoid Set if the caller cannot handle failure returns.
3835 * @param SRC_POS The source position of the caller (RT_SRC_POS).
3836 */
3837#if defined(VBOX_STRICT) || defined(DOXYGEN_RUNNING)
3838int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL)
3839#else
3840int pgmLock(PVMCC pVM, bool fVoid)
3841#endif
3842{
3843#if defined(VBOX_STRICT)
3844 int rc = PDMCritSectEnterDebug(pVM, &pVM->pgm.s.CritSectX, VINF_SUCCESS, (uintptr_t)ASMReturnAddress(), RT_SRC_POS_ARGS);
3845#else
3846 int rc = PDMCritSectEnter(pVM, &pVM->pgm.s.CritSectX, VINF_SUCCESS);
3847#endif
3848 if (RT_SUCCESS(rc))
3849 return rc;
3850 if (fVoid)
3851 PDM_CRITSECT_RELEASE_ASSERT_RC(pVM, &pVM->pgm.s.CritSectX, rc);
3852 else
3853 AssertRC(rc);
3854 return rc;
3855}
3856
3857
3858/**
3859 * Release the PGM lock.
3860 *
3861 * @returns VBox status code
3862 * @param pVM The cross context VM structure.
3863 */
3864void pgmUnlock(PVMCC pVM)
3865{
3866 uint32_t cDeprecatedPageLocks = pVM->pgm.s.cDeprecatedPageLocks;
3867 pVM->pgm.s.cDeprecatedPageLocks = 0;
3868 int rc = PDMCritSectLeave(pVM, &pVM->pgm.s.CritSectX);
3869 if (rc == VINF_SEM_NESTED)
3870 pVM->pgm.s.cDeprecatedPageLocks = cDeprecatedPageLocks;
3871}
3872
3873
3874#if !defined(IN_R0) || defined(LOG_ENABLED)
3875
3876/** Format handler for PGMPAGE.
3877 * @copydoc FNRTSTRFORMATTYPE */
3878static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3879 const char *pszType, void const *pvValue,
3880 int cchWidth, int cchPrecision, unsigned fFlags,
3881 void *pvUser)
3882{
3883 size_t cch;
3884 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
3885 if (RT_VALID_PTR(pPage))
3886 {
3887 char szTmp[64+80];
3888
3889 cch = 0;
3890
3891 /* The single char state stuff. */
3892 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
3893 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
3894
3895# define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
3896 if (IS_PART_INCLUDED(5))
3897 {
3898 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
3899 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
3900 }
3901
3902 /* The type. */
3903 if (IS_PART_INCLUDED(4))
3904 {
3905 szTmp[cch++] = ':';
3906 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
3907 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
3908 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
3909 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
3910 }
3911
3912 /* The numbers. */
3913 if (IS_PART_INCLUDED(3))
3914 {
3915 szTmp[cch++] = ':';
3916 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
3917 }
3918
3919 if (IS_PART_INCLUDED(2))
3920 {
3921 szTmp[cch++] = ':';
3922 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
3923 }
3924
3925 if (IS_PART_INCLUDED(6))
3926 {
3927 szTmp[cch++] = ':';
3928 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
3929 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
3930 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
3931 }
3932# undef IS_PART_INCLUDED
3933
3934 cch = pfnOutput(pvArgOutput, szTmp, cch);
3935 }
3936 else
3937 cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmpage-ptr>"));
3938 NOREF(pszType); NOREF(cchWidth); NOREF(pvUser);
3939 return cch;
3940}
3941
3942
3943/** Format handler for PGMRAMRANGE.
3944 * @copydoc FNRTSTRFORMATTYPE */
3945static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3946 const char *pszType, void const *pvValue,
3947 int cchWidth, int cchPrecision, unsigned fFlags,
3948 void *pvUser)
3949{
3950 size_t cch;
3951 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
3952 if (RT_VALID_PTR(pRam))
3953 {
3954 char szTmp[80];
3955 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
3956 cch = pfnOutput(pvArgOutput, szTmp, cch);
3957 }
3958 else
3959 cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmramrange-ptr>"));
3960 NOREF(pszType); NOREF(cchWidth); NOREF(cchPrecision); NOREF(pvUser); NOREF(fFlags);
3961 return cch;
3962}
3963
3964/** Format type andlers to be registered/deregistered. */
3965static const struct
3966{
3967 char szType[24];
3968 PFNRTSTRFORMATTYPE pfnHandler;
3969} g_aPgmFormatTypes[] =
3970{
3971 { "pgmpage", pgmFormatTypeHandlerPage },
3972 { "pgmramrange", pgmFormatTypeHandlerRamRange }
3973};
3974
3975#endif /* !IN_R0 || LOG_ENABLED */
3976
3977/**
3978 * Registers the global string format types.
3979 *
3980 * This should be called at module load time or in some other manner that ensure
3981 * that it's called exactly one time.
3982 *
3983 * @returns IPRT status code on RTStrFormatTypeRegister failure.
3984 */
3985VMMDECL(int) PGMRegisterStringFormatTypes(void)
3986{
3987#if !defined(IN_R0) || defined(LOG_ENABLED)
3988 int rc = VINF_SUCCESS;
3989 unsigned i;
3990 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
3991 {
3992 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
3993# ifdef IN_RING0
3994 if (rc == VERR_ALREADY_EXISTS)
3995 {
3996 /* in case of cleanup failure in ring-0 */
3997 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
3998 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
3999 }
4000# endif
4001 }
4002 if (RT_FAILURE(rc))
4003 while (i-- > 0)
4004 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
4005
4006 return rc;
4007#else
4008 return VINF_SUCCESS;
4009#endif
4010}
4011
4012
4013/**
4014 * Deregisters the global string format types.
4015 *
4016 * This should be called at module unload time or in some other manner that
4017 * ensure that it's called exactly one time.
4018 */
4019VMMDECL(void) PGMDeregisterStringFormatTypes(void)
4020{
4021#if !defined(IN_R0) || defined(LOG_ENABLED)
4022 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
4023 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
4024#endif
4025}
4026
4027
4028#ifdef VBOX_STRICT
4029/**
4030 * Asserts that everything related to the guest CR3 is correctly shadowed.
4031 *
4032 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
4033 * and assert the correctness of the guest CR3 mapping before asserting that the
4034 * shadow page tables is in sync with the guest page tables.
4035 *
4036 * @returns Number of conflicts.
4037 * @param pVM The cross context VM structure.
4038 * @param pVCpu The cross context virtual CPU structure.
4039 * @param cr3 The current guest CR3 register value.
4040 * @param cr4 The current guest CR4 register value.
4041 */
4042VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4)
4043{
4044 STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
4045
4046 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
4047 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), -VERR_PGM_MODE_IPE);
4048 AssertReturn(g_aPgmBothModeData[idxBth].pfnAssertCR3, -VERR_PGM_MODE_IPE);
4049
4050 PGM_LOCK_VOID(pVM);
4051 unsigned cErrors = g_aPgmBothModeData[idxBth].pfnAssertCR3(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
4052 PGM_UNLOCK(pVM);
4053
4054 STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
4055 return cErrors;
4056}
4057#endif /* VBOX_STRICT */
4058
4059
4060/**
4061 * Updates PGM's copy of the guest's EPT pointer.
4062 *
4063 * @param pVCpu The cross context virtual CPU structure.
4064 * @param uEptPtr The EPT pointer.
4065 *
4066 * @remarks This can be called as part of VM-entry so we might be in the midst of
4067 * switching to VMX non-root mode.
4068 */
4069VMM_INT_DECL(void) PGMSetGuestEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr)
4070{
4071 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4072 PGM_LOCK_VOID(pVM);
4073 pVCpu->pgm.s.uEptPtr = uEptPtr;
4074 pVCpu->pgm.s.pGstEptPml4R3 = 0;
4075 pVCpu->pgm.s.pGstEptPml4R0 = 0;
4076 PGM_UNLOCK(pVM);
4077}
4078
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