[87477] | 1 | /* $Id: PDMAllIommu.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
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| 2 | /** @file
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| 3 | * PDM IOMMU - All Contexts.
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| 4 | */
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| 5 |
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| 6 | /*
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[96407] | 7 | * Copyright (C) 2021-2022 Oracle and/or its affiliates.
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[87477] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[87477] | 26 | */
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| 27 |
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| 28 |
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| 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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| 32 | #define LOG_GROUP LOG_GROUP_PDM
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| 33 | #define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
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| 34 | #include "PDMInternal.h"
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| 35 |
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| 36 | #include <VBox/vmm/vmcc.h>
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[87652] | 37 | #include <iprt/string.h>
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[87477] | 38 | #ifdef IN_RING3
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| 39 | # include <iprt/mem.h>
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| 40 | #endif
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| 41 |
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| 42 |
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[87478] | 43 | /*********************************************************************************************************************************
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| 44 | * Defined Constants And Macros *
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| 45 | *********************************************************************************************************************************/
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[87477] | 46 | /**
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[87478] | 47 | * Gets the PDM IOMMU for the current context from the PDM device instance.
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| 48 | */
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| 49 | #ifdef IN_RING0
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| 50 | #define PDMDEVINS_TO_IOMMU(a_pDevIns) &(a_pDevIns)->Internal.s.pGVM->pdmr0.s.aIommus[0];
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| 51 | #else
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| 52 | #define PDMDEVINS_TO_IOMMU(a_pDevIns) &(a_pDevIns)->Internal.s.pVMR3->pdm.s.aIommus[0];
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| 53 | #endif
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| 54 |
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| 55 |
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| 56 | /**
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[87477] | 57 | * Gets the PCI device ID (Bus:Dev:Fn) for the given PCI device.
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| 58 | *
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| 59 | * @returns PCI device ID.
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| 60 | * @param pDevIns The device instance.
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| 61 | * @param pPciDev The PCI device structure. Cannot be NULL.
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| 62 | */
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| 63 | DECL_FORCE_INLINE(uint16_t) pdmIommuGetPciDeviceId(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
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| 64 | {
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| 65 | uint8_t const idxBus = pPciDev->Int.s.idxPdmBus;
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| 66 | #if defined(IN_RING0)
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| 67 | PGVM pGVM = pDevIns->Internal.s.pGVM;
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| 68 | Assert(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
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| 69 | PCPDMPCIBUSR0 pBus = &pGVM->pdmr0.s.aPciBuses[idxBus];
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| 70 | #elif defined(IN_RING3)
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| 71 | PVM pVM = pDevIns->Internal.s.pVMR3;
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| 72 | Assert(idxBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses));
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| 73 | PCPDMPCIBUS pBus = &pVM->pdm.s.aPciBuses[idxBus];
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| 74 | #endif
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| 75 | return PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn);
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| 76 | }
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| 77 |
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| 78 |
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[88631] | 79 | /**
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| 80 | * Returns whether an IOMMU instance is present.
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| 81 | *
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| 82 | * @returns @c true if an IOMMU is present, @c false otherwise.
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| 83 | * @param pDevIns The device instance.
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| 84 | */
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| 85 | bool pdmIommuIsPresent(PPDMDEVINS pDevIns)
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| 86 | {
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[88636] | 87 | #ifdef IN_RING0
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| 88 | PCPDMIOMMUR3 pIommuR3 = &pDevIns->Internal.s.pGVM->pdm.s.aIommus[0];
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| 89 | #else
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| 90 | PCPDMIOMMUR3 pIommuR3 = &pDevIns->Internal.s.pVMR3->pdm.s.aIommus[0];
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| 91 | #endif
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| 92 | return pIommuR3->pDevInsR3 != NULL;
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[88631] | 93 | }
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| 94 |
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| 95 |
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[87494] | 96 | /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
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[88078] | 97 | int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
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[87494] | 98 | {
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| 99 | PPDMIOMMU pIommu = PDMDEVINS_TO_IOMMU(pDevIns);
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| 100 | PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
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[88638] | 101 | Assert(pDevInsIommu);
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| 102 | if (pDevInsIommu != pDevIns)
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| 103 | return pIommu->pfnMsiRemap(pDevInsIommu, idDevice, pMsiIn, pMsiOut);
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| 104 | return VERR_IOMMU_CANNOT_CALL_SELF;
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[87494] | 105 | }
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| 106 |
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| 107 |
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[87477] | 108 | /**
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| 109 | * Bus master physical memory read after translating the physical address using the
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| 110 | * IOMMU.
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| 111 | *
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| 112 | * @returns VBox status code.
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| 113 | * @retval VERR_IOMMU_NOT_PRESENT if an IOMMU is not present.
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| 114 | *
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| 115 | * @param pDevIns The device instance.
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| 116 | * @param pPciDev The PCI device. Cannot be NULL.
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| 117 | * @param GCPhys The guest-physical address to read.
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| 118 | * @param pvBuf Where to put the data read.
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| 119 | * @param cbRead How many bytes to read.
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| 120 | * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
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| 121 | *
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| 122 | * @thread Any.
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| 123 | */
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| 124 | int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags)
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| 125 | {
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[87478] | 126 | PPDMIOMMU pIommu = PDMDEVINS_TO_IOMMU(pDevIns);
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[87477] | 127 | PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
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[88638] | 128 | if (pDevInsIommu)
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[87477] | 129 | {
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[88638] | 130 | if (pDevInsIommu != pDevIns)
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| 131 | { /* likely */ }
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| 132 | else
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| 133 | return VERR_IOMMU_CANNOT_CALL_SELF;
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| 134 |
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[88078] | 135 | uint16_t const idDevice = pdmIommuGetPciDeviceId(pDevIns, pPciDev);
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[87477] | 136 | int rc = VINF_SUCCESS;
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| 137 | while (cbRead > 0)
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| 138 | {
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| 139 | RTGCPHYS GCPhysOut;
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| 140 | size_t cbContig;
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[88078] | 141 | rc = pIommu->pfnMemAccess(pDevInsIommu, idDevice, GCPhys, cbRead, PDMIOMMU_MEM_F_READ, &GCPhysOut, &cbContig);
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[87477] | 142 | if (RT_SUCCESS(rc))
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| 143 | {
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[90042] | 144 | Assert(cbContig > 0 && cbContig <= cbRead);
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[87477] | 145 | /** @todo Handle strict return codes from PGMPhysRead. */
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[90028] | 146 | rc = pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhysOut, pvBuf, cbContig, fFlags);
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[87477] | 147 | if (RT_SUCCESS(rc))
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| 148 | {
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| 149 | cbRead -= cbContig;
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| 150 | pvBuf = (void *)((uintptr_t)pvBuf + cbContig);
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| 151 | GCPhys += cbContig;
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| 152 | }
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| 153 | else
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| 154 | break;
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| 155 | }
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| 156 | else
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| 157 | {
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[88078] | 158 | LogFunc(("IOMMU memory read failed. idDevice=%#x GCPhys=%#RGp cb=%zu rc=%Rrc\n", idDevice, GCPhys, cbRead, rc));
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[87652] | 159 |
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| 160 | /*
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| 161 | * We should initialize the read buffer on failure for devices that don't check
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| 162 | * return codes (but would verify the data). But we still want to propagate the
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| 163 | * error code from the IOMMU to the device, see @bugref{9936#c3}.
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| 164 | */
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| 165 | memset(pvBuf, 0xff, cbRead);
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[87477] | 166 | break;
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| 167 | }
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| 168 | }
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| 169 | return rc;
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| 170 | }
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| 171 | return VERR_IOMMU_NOT_PRESENT;
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| 172 | }
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| 173 |
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| 174 |
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| 175 | /**
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| 176 | * Bus master physical memory write after translating the physical address using the
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| 177 | * IOMMU.
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| 178 | *
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| 179 | * @returns VBox status code.
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| 180 | * @retval VERR_IOMMU_NOT_PRESENT if an IOMMU is not present.
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| 181 | *
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| 182 | * @param pDevIns The device instance.
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| 183 | * @param pPciDev The PCI device structure. Cannot be NULL.
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| 184 | * @param GCPhys The guest-physical address to write.
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| 185 | * @param pvBuf The data to write.
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[87483] | 186 | * @param cbWrite How many bytes to write.
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[87477] | 187 | * @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
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| 188 | *
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| 189 | * @thread Any.
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| 190 | */
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| 191 | int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite,
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| 192 | uint32_t fFlags)
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| 193 | {
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[87478] | 194 | PPDMIOMMU pIommu = PDMDEVINS_TO_IOMMU(pDevIns);
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[87477] | 195 | PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
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[88638] | 196 | if (pDevInsIommu)
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[87477] | 197 | {
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[88638] | 198 | if (pDevInsIommu != pDevIns)
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| 199 | { /* likely */ }
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| 200 | else
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| 201 | return VERR_IOMMU_CANNOT_CALL_SELF;
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| 202 |
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[88078] | 203 | uint16_t const idDevice = pdmIommuGetPciDeviceId(pDevIns, pPciDev);
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[87477] | 204 | int rc = VINF_SUCCESS;
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| 205 | while (cbWrite > 0)
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| 206 | {
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| 207 | RTGCPHYS GCPhysOut;
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| 208 | size_t cbContig;
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[88078] | 209 | rc = pIommu->pfnMemAccess(pDevInsIommu, idDevice, GCPhys, cbWrite, PDMIOMMU_MEM_F_WRITE, &GCPhysOut, &cbContig);
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[87477] | 210 | if (RT_SUCCESS(rc))
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| 211 | {
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[90042] | 212 | Assert(cbContig > 0 && cbContig <= cbWrite);
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[87477] | 213 | /** @todo Handle strict return codes from PGMPhysWrite. */
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[90028] | 214 | rc = pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhysOut, pvBuf, cbContig, fFlags);
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[87477] | 215 | if (RT_SUCCESS(rc))
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| 216 | {
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| 217 | cbWrite -= cbContig;
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| 218 | pvBuf = (const void *)((uintptr_t)pvBuf + cbContig);
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| 219 | GCPhys += cbContig;
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| 220 | }
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| 221 | else
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| 222 | break;
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| 223 | }
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| 224 | else
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| 225 | {
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[90042] | 226 | LogFunc(("IOMMU memory write failed. idDevice=%#x GCPhys=%#RGp cb=%zu rc=%Rrc\n", idDevice, GCPhys, cbWrite, rc));
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[87477] | 227 | break;
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| 228 | }
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| 229 | }
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| 230 | return rc;
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| 231 | }
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| 232 | return VERR_IOMMU_NOT_PRESENT;
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| 233 | }
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| 234 |
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| 235 |
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[87494] | 236 | #ifdef IN_RING3
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[87477] | 237 | /**
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| 238 | * Requests the mapping of a guest page into ring-3 in preparation for a bus master
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| 239 | * physical memory read operation.
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| 240 | *
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| 241 | * Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
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| 242 | *
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| 243 | * @returns VBox status code.
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| 244 | * @retval VERR_IOMMU_NOT_PRESENT if an IOMMU is not present.
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| 245 | *
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| 246 | * @param pDevIns The device instance.
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| 247 | * @param pPciDev The PCI device structure. Cannot be NULL.
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| 248 | * @param GCPhys The guest physical address of the page that should be
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| 249 | * mapped.
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| 250 | * @param fFlags Flags reserved for future use, MBZ.
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| 251 | * @param ppv Where to store the address corresponding to GCPhys.
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| 252 | * @param pLock Where to store the lock information that
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| 253 | * pfnPhysReleasePageMappingLock needs.
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| 254 | */
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[87494] | 255 | int pdmR3IommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
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| 256 | PPGMPAGEMAPLOCK pLock)
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[87477] | 257 | {
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[87478] | 258 | PPDMIOMMU pIommu = PDMDEVINS_TO_IOMMU(pDevIns);
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[87477] | 259 | PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
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[88638] | 260 | if (pDevInsIommu)
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[87477] | 261 | {
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[88638] | 262 | if (pDevInsIommu != pDevIns)
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| 263 | { /* likely */ }
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| 264 | else
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| 265 | return VERR_IOMMU_CANNOT_CALL_SELF;
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| 266 |
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[88078] | 267 | uint16_t const idDevice = pdmIommuGetPciDeviceId(pDevIns, pPciDev);
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[87477] | 268 | size_t cbContig = 0;
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| 269 | RTGCPHYS GCPhysOut = NIL_RTGCPHYS;
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[88078] | 270 | int rc = pIommu->pfnMemAccess(pDevInsIommu, idDevice, GCPhys & X86_PAGE_BASE_MASK, X86_PAGE_SIZE, PDMIOMMU_MEM_F_READ,
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[87477] | 271 | &GCPhysOut, &cbContig);
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| 272 | if (RT_SUCCESS(rc))
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| 273 | {
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| 274 | Assert(GCPhysOut != NIL_RTGCPHYS);
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| 275 | Assert(cbContig == X86_PAGE_SIZE);
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| 276 | return pDevIns->pHlpR3->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhysOut, fFlags, ppv, pLock);
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| 277 | }
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| 278 |
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[88078] | 279 | LogFunc(("IOMMU memory read for pointer access failed. idDevice=%#x GCPhys=%#RGp rc=%Rrc\n", idDevice, GCPhys, rc));
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[87477] | 280 | return rc;
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| 281 | }
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| 282 | return VERR_IOMMU_NOT_PRESENT;
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| 283 | }
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| 284 |
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| 285 |
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| 286 | /**
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| 287 | * Requests the mapping of a guest page into ring-3 in preparation for a bus master
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| 288 | * physical memory write operation.
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| 289 | *
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| 290 | * Refer pfnPhysGCPhys2CCPtr() for further details.
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| 291 | *
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| 292 | * @returns VBox status code.
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| 293 | * @retval VERR_IOMMU_NOT_PRESENT if an IOMMU is not present.
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| 294 | *
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| 295 | * @param pDevIns The device instance.
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| 296 | * @param pPciDev The PCI device structure. Cannot be NULL.
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| 297 | * @param GCPhys The guest physical address of the page that should be
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| 298 | * mapped.
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| 299 | * @param fFlags Flags reserved for future use, MBZ.
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| 300 | * @param ppv Where to store the address corresponding to GCPhys.
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| 301 | * @param pLock Where to store the lock information that
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| 302 | * pfnPhysReleasePageMappingLock needs.
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| 303 | */
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[87494] | 304 | int pdmR3IommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
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| 305 | PPGMPAGEMAPLOCK pLock)
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[87477] | 306 | {
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[87478] | 307 | PPDMIOMMU pIommu = PDMDEVINS_TO_IOMMU(pDevIns);
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[87477] | 308 | PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
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[88638] | 309 | if (pDevInsIommu)
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[87477] | 310 | {
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[88638] | 311 | if (pDevInsIommu != pDevIns)
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| 312 | { /* likely */ }
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| 313 | else
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| 314 | return VERR_IOMMU_CANNOT_CALL_SELF;
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| 315 |
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[88078] | 316 | uint16_t const idDevice = pdmIommuGetPciDeviceId(pDevIns, pPciDev);
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[87477] | 317 | size_t cbContig = 0;
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| 318 | RTGCPHYS GCPhysOut = NIL_RTGCPHYS;
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[88078] | 319 | int rc = pIommu->pfnMemAccess(pDevInsIommu, idDevice, GCPhys & X86_PAGE_BASE_MASK, X86_PAGE_SIZE, PDMIOMMU_MEM_F_WRITE,
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[87477] | 320 | &GCPhysOut, &cbContig);
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| 321 | if (RT_SUCCESS(rc))
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| 322 | {
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| 323 | Assert(GCPhysOut != NIL_RTGCPHYS);
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| 324 | Assert(cbContig == X86_PAGE_SIZE);
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| 325 | return pDevIns->pHlpR3->pfnPhysGCPhys2CCPtr(pDevIns, GCPhysOut, fFlags, ppv, pLock);
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| 326 | }
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| 327 |
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[88078] | 328 | LogFunc(("IOMMU memory write for pointer access failed. idDevice=%#x GCPhys=%#RGp rc=%Rrc\n", idDevice, GCPhys, rc));
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[87477] | 329 | return rc;
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| 330 | }
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| 331 | return VERR_IOMMU_NOT_PRESENT;
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| 332 | }
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| 333 |
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| 334 |
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| 335 | /**
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| 336 | * Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
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| 337 | * master physical memory read operation.
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| 338 | *
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| 339 | * Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
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| 340 | *
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| 341 | * @returns VBox status code.
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| 342 | * @retval VERR_IOMMU_NOT_PRESENT if an IOMMU is not present.
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| 343 | *
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| 344 | * @param pDevIns The device instance.
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| 345 | * @param pPciDev The PCI device structure. Cannot be NULL.
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| 346 | * @param cPages Number of pages to lock.
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| 347 | * @param paGCPhysPages The guest physical address of the pages that
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| 348 | * should be mapped (@a cPages entries).
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| 349 | * @param fFlags Flags reserved for future use, MBZ.
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| 350 | * @param papvPages Where to store the ring-3 mapping addresses
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| 351 | * corresponding to @a paGCPhysPages.
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| 352 | * @param paLocks Where to store the locking information that
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| 353 | * pfnPhysBulkReleasePageMappingLock needs (@a cPages
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| 354 | * in length).
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| 355 | */
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[87494] | 356 | int pdmR3IommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
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| 357 | uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks)
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[87477] | 358 | {
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[87478] | 359 | PPDMIOMMU pIommu = PDMDEVINS_TO_IOMMU(pDevIns);
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[87477] | 360 | PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
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[88638] | 361 | if (pDevInsIommu)
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[87477] | 362 | {
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[88638] | 363 | if (pDevInsIommu != pDevIns)
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| 364 | { /* likely */ }
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| 365 | else
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| 366 | return VERR_IOMMU_CANNOT_CALL_SELF;
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| 367 |
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[87477] | 368 | /* Allocate space for translated addresses. */
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| 369 | size_t const cbIovas = cPages * sizeof(uint64_t);
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| 370 | PRTGCPHYS paGCPhysOut = (PRTGCPHYS)RTMemAllocZ(cbIovas);
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| 371 | if (paGCPhysOut)
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| 372 | { /* likely */ }
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| 373 | else
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| 374 | {
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| 375 | LogFunc(("caller='%s'/%d: returns %Rrc - Failed to alloc %zu bytes for IOVA addresses\n",
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| 376 | pDevIns->pReg->szName, pDevIns->iInstance, VERR_NO_MEMORY, cbIovas));
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| 377 | return VERR_NO_MEMORY;
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| 378 | }
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| 379 |
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| 380 | /* Ask the IOMMU for corresponding translated physical addresses. */
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[88078] | 381 | uint16_t const idDevice = pdmIommuGetPciDeviceId(pDevIns, pPciDev);
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[87477] | 382 | AssertCompile(sizeof(RTGCPHYS) == sizeof(uint64_t));
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[88078] | 383 | int rc = pIommu->pfnMemBulkAccess(pDevInsIommu, idDevice, cPages, (uint64_t const *)paGCPhysPages, PDMIOMMU_MEM_F_READ,
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[87477] | 384 | paGCPhysOut);
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| 385 | if (RT_SUCCESS(rc))
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| 386 | {
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| 387 | /* Perform the bulk mapping but with the translated addresses. */
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| 388 | rc = pDevIns->pHlpR3->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysOut, fFlags, papvPages, paLocks);
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| 389 | if (RT_FAILURE(rc))
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| 390 | LogFunc(("Bulk mapping for read access failed. cPages=%zu fFlags=%#x rc=%Rrc\n", rc, cPages, fFlags));
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| 391 | }
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| 392 | else
|
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[88078] | 393 | LogFunc(("Bulk translation for read access failed. idDevice=%#x cPages=%zu rc=%Rrc\n", idDevice, cPages, rc));
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[87477] | 394 |
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| 395 | RTMemFree(paGCPhysOut);
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| 396 | return rc;
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| 397 | }
|
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| 398 | return VERR_IOMMU_NOT_PRESENT;
|
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| 399 | }
|
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| 400 |
|
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| 401 |
|
---|
| 402 | /**
|
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| 403 | * Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
|
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| 404 | * master physical memory write operation.
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| 405 | *
|
---|
| 406 | * Refer pfnPhysBulkGCPhys2CCPtr() for further details.
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| 407 | *
|
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| 408 | * @returns VBox status code.
|
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| 409 | * @retval VERR_IOMMU_NOT_PRESENT if an IOMMU is not present.
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| 410 | *
|
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| 411 | * @param pDevIns The device instance.
|
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| 412 | * @param pPciDev The PCI device structure. Cannot be NULL.
|
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| 413 | * @param cPages Number of pages to lock.
|
---|
| 414 | * @param paGCPhysPages The guest physical address of the pages that
|
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| 415 | * should be mapped (@a cPages entries).
|
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| 416 | * @param fFlags Flags reserved for future use, MBZ.
|
---|
| 417 | * @param papvPages Where to store the ring-3 mapping addresses
|
---|
| 418 | * corresponding to @a paGCPhysPages.
|
---|
| 419 | * @param paLocks Where to store the locking information that
|
---|
| 420 | * pfnPhysBulkReleasePageMappingLock needs (@a cPages
|
---|
| 421 | * in length).
|
---|
| 422 | */
|
---|
[87494] | 423 | int pdmR3IommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
|
---|
| 424 | uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
|
---|
[87477] | 425 | {
|
---|
[87478] | 426 | PPDMIOMMU pIommu = PDMDEVINS_TO_IOMMU(pDevIns);
|
---|
[87477] | 427 | PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
|
---|
[88638] | 428 | if (pDevInsIommu)
|
---|
[87477] | 429 | {
|
---|
[88638] | 430 | if (pDevInsIommu != pDevIns)
|
---|
| 431 | { /* likely */ }
|
---|
| 432 | else
|
---|
| 433 | return VERR_IOMMU_CANNOT_CALL_SELF;
|
---|
| 434 |
|
---|
[87477] | 435 | /* Allocate space for translated addresses. */
|
---|
| 436 | size_t const cbIovas = cPages * sizeof(uint64_t);
|
---|
| 437 | PRTGCPHYS paGCPhysOut = (PRTGCPHYS)RTMemAllocZ(cbIovas);
|
---|
| 438 | if (paGCPhysOut)
|
---|
| 439 | { /* likely */ }
|
---|
| 440 | else
|
---|
| 441 | {
|
---|
| 442 | LogFunc(("caller='%s'/%d: returns %Rrc - Failed to alloc %zu bytes for IOVA addresses\n",
|
---|
| 443 | pDevIns->pReg->szName, pDevIns->iInstance, VERR_NO_MEMORY, cbIovas));
|
---|
| 444 | return VERR_NO_MEMORY;
|
---|
| 445 | }
|
---|
| 446 |
|
---|
| 447 | /* Ask the IOMMU for corresponding translated physical addresses. */
|
---|
[88078] | 448 | uint16_t const idDevice = pdmIommuGetPciDeviceId(pDevIns, pPciDev);
|
---|
[87477] | 449 | AssertCompile(sizeof(RTGCPHYS) == sizeof(uint64_t));
|
---|
[88078] | 450 | int rc = pIommu->pfnMemBulkAccess(pDevInsIommu, idDevice, cPages, (uint64_t const *)paGCPhysPages, PDMIOMMU_MEM_F_WRITE,
|
---|
[87477] | 451 | paGCPhysOut);
|
---|
| 452 | if (RT_SUCCESS(rc))
|
---|
| 453 | {
|
---|
| 454 | /* Perform the bulk mapping but with the translated addresses. */
|
---|
| 455 | rc = pDevIns->pHlpR3->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysOut, fFlags, papvPages, paLocks);
|
---|
| 456 | if (RT_FAILURE(rc))
|
---|
| 457 | LogFunc(("Bulk mapping of addresses failed. cPages=%zu fFlags=%#x rc=%Rrc\n", rc, cPages, fFlags));
|
---|
| 458 | }
|
---|
| 459 | else
|
---|
[88078] | 460 | LogFunc(("IOMMU bulk translation failed. idDevice=%#x cPages=%zu rc=%Rrc\n", idDevice, cPages, rc));
|
---|
[87477] | 461 |
|
---|
| 462 | RTMemFree(paGCPhysOut);
|
---|
| 463 | return rc;
|
---|
| 464 | }
|
---|
| 465 | return VERR_IOMMU_NOT_PRESENT;
|
---|
| 466 | }
|
---|
[87494] | 467 | #endif /* IN_RING3 */
|
---|
[87477] | 468 |
|
---|