VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllThrdTables.h@ 104321

Last change on this file since 104321 was 104321, checked in by vboxsync, 7 weeks ago

VMM/IEM: Drop the IEMTHRDEDCALLENTRY::idxRange field as nobody uses it. bugref:10369
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1/* $Id: IEMAllThrdTables.h 104321 2024-04-12 15:08:36Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Threaded Recompilation, Instruction Tables.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_VMMAll_IEMAllThrdTables_h
29#define VMM_INCLUDED_SRC_VMMAll_IEMAllThrdTables_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/*********************************************************************************************************************************
36* Header Files *
37*********************************************************************************************************************************/
38#ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
39# define LOG_GROUP LOG_GROUP_IEM_RE_THREADED
40#endif
41#define IEM_WITH_CODE_TLB_AND_OPCODE_BUF /* A bit hackish, but its all in IEMInline.h. */
42#define VMCPU_INCL_CPUM_GST_CTX
43#include <VBox/vmm/iem.h>
44#include <VBox/vmm/cpum.h>
45#include <VBox/vmm/apic.h>
46#include <VBox/vmm/pdm.h>
47#include <VBox/vmm/pgm.h>
48#include <VBox/vmm/iom.h>
49#include <VBox/vmm/em.h>
50#include <VBox/vmm/hm.h>
51#include <VBox/vmm/nem.h>
52#include <VBox/vmm/gim.h>
53#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
54# include <VBox/vmm/em.h>
55# include <VBox/vmm/hm_svm.h>
56#endif
57#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
58# include <VBox/vmm/hmvmxinline.h>
59#endif
60#include <VBox/vmm/tm.h>
61#include <VBox/vmm/dbgf.h>
62#include <VBox/vmm/dbgftrace.h>
63#ifndef TST_IEM_CHECK_MC
64# include "IEMInternal.h"
65#endif
66#include <VBox/vmm/vmcc.h>
67#include <VBox/log.h>
68#include <VBox/err.h>
69#include <VBox/param.h>
70#include <VBox/dis.h>
71#include <VBox/disopcode-x86-amd64.h>
72#include <iprt/asm-math.h>
73#include <iprt/assert.h>
74#include <iprt/mem.h>
75#include <iprt/string.h>
76#include <iprt/x86.h>
77
78#ifndef TST_IEM_CHECK_MC
79# include "IEMInline.h"
80# include "IEMOpHlp.h"
81# include "IEMMc.h"
82#endif
83
84#include "IEMThreadedFunctions.h"
85#include "IEMN8veRecompiler.h" /* For a_fGstShwFlush and iemThreadedRecompilerMcDeferToCImpl0. */
86
87
88/*
89 * Narrow down configs here to avoid wasting time on unused configs here.
90 */
91
92#ifndef IEM_WITH_CODE_TLB
93# error The code TLB must be enabled for the recompiler.
94#endif
95
96#ifndef IEM_WITH_DATA_TLB
97# error The data TLB must be enabled for the recompiler.
98#endif
99
100#ifndef IEM_WITH_SETJMP
101# error The setjmp approach must be enabled for the recompiler.
102#endif
103
104
105/*********************************************************************************************************************************
106* Defined Constants And Macros *
107*********************************************************************************************************************************/
108#define g_apfnOneByteMap g_apfnIemThreadedRecompilerOneByteMap
109#define g_apfnTwoByteMap g_apfnIemThreadedRecompilerTwoByteMap
110#define g_apfnThreeByte0f3a g_apfnIemThreadedRecompilerThreeByte0f3a
111#define g_apfnThreeByte0f38 g_apfnIemThreadedRecompilerThreeByte0f38
112#define g_apfnVexMap1 g_apfnIemThreadedRecompilerVecMap1
113#define g_apfnVexMap2 g_apfnIemThreadedRecompilerVecMap2
114#define g_apfnVexMap3 g_apfnIemThreadedRecompilerVecMap3
115
116
117/*
118 * Override IEM_MC_BEGIN to take down the IEM_CIMPL_F_XXX flags.
119 */
120#undef IEM_MC_BEGIN
121#define IEM_MC_BEGIN(a_fMcFlags, a_fCImplFlags) \
122 { \
123 pVCpu->iem.s.fTbCurInstr = (a_fCImplFlags) /*| ((a_fMcFlags) << 20*/
124
125/*
126 * Override IEM_MC_CALC_RM_EFF_ADDR to use iemOpHlpCalcRmEffAddrJmpEx and produce uEffAddrInfo.
127 */
128#undef IEM_MC_CALC_RM_EFF_ADDR
129#ifndef IEM_WITH_SETJMP
130# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
131 uint64_t uEffAddrInfo; \
132 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddrJmpEx(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &(a_GCPtrEff), &uEffAddrInfo))
133#else
134# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
135 uint64_t uEffAddrInfo; \
136 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmpEx(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &uEffAddrInfo))
137#endif
138
139/*
140 * Likewise override IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES so we fetch all the opcodes.
141 */
142#undef IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES
143#define IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(a_bRm) do { \
144 uint64_t uEffAddrInfo; \
145 (void)iemOpHlpCalcRmEffAddrJmpEx(pVCpu, bRm, 0, &uEffAddrInfo); \
146 } while (0)
147
148/*
149 * Override the IEM_MC_REL_JMP_S*_AND_FINISH macros to check for zero byte jumps.
150 */
151#undef IEM_MC_REL_JMP_S8_AND_FINISH
152#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) do { \
153 Assert(pVCpu->iem.s.fTbBranched != 0); \
154 if ((a_i8) == 0) \
155 pVCpu->iem.s.fTbBranched |= IEMBRANCHED_F_ZERO; \
156 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize); \
157 } while (0)
158
159#undef IEM_MC_REL_JMP_S16_AND_FINISH
160#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) do { \
161 Assert(pVCpu->iem.s.fTbBranched != 0); \
162 if ((a_i16) == 0) \
163 pVCpu->iem.s.fTbBranched |= IEMBRANCHED_F_ZERO; \
164 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16)); \
165 } while (0)
166
167#undef IEM_MC_REL_JMP_S32_AND_FINISH
168#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) do { \
169 Assert(pVCpu->iem.s.fTbBranched != 0); \
170 if ((a_i32) == 0) \
171 pVCpu->iem.s.fTbBranched |= IEMBRANCHED_F_ZERO; \
172 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize); \
173 } while (0)
174
175
176/*
177 * Emit call macros.
178 */
179#define IEM_MC2_BEGIN_EMIT_CALLS(a_fCheckIrqBefore) \
180 { \
181 PIEMTB const pTb = pVCpu->iem.s.pCurTbR3; \
182 uint8_t const cbInstrMc2 = IEM_GET_INSTR_LEN(pVCpu); \
183 AssertMsg(pVCpu->iem.s.offOpcode == cbInstrMc2, \
184 ("%u vs %u (%04x:%08RX64)\n", pVCpu->iem.s.offOpcode, cbInstrMc2, \
185 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip)); \
186 \
187 /* If we need to check for IRQs before the instruction, we do that before \
188 adding any opcodes as it may abort the instruction. \
189 Note! During compilation, we may swap IRQ and #PF exceptions here \
190 in a manner that a real CPU would not do. However it shouldn't \
191 be something that is easy (if at all possible) to observe in the \
192 guest, so fine. The unexpected end-of-tb below have the same \
193 potential "issue". */ \
194 if (!(a_fCheckIrqBefore) || iemThreadedCompileEmitIrqCheckBefore(pVCpu, pTb)) \
195 { /* likely */ } \
196 else \
197 return VINF_IEM_RECOMPILE_END_TB; \
198 \
199 /* No page crossing, right? */ \
200 uint16_t const offOpcodeMc2 = pTb->cbOpcodes; \
201 uint8_t const idxRangeMc2 = pTb->cRanges - 1; \
202 if ( !pVCpu->iem.s.fTbCrossedPage \
203 && !pVCpu->iem.s.fTbCheckOpcodes \
204 && !pVCpu->iem.s.fTbBranched \
205 && !(pTb->fFlags & IEMTB_F_CS_LIM_CHECKS)) \
206 { \
207 /** @todo Custom copy function, given range is 1 thru 15 bytes. */ \
208 memcpy(&pTb->pabOpcodes[offOpcodeMc2], pVCpu->iem.s.abOpcode, pVCpu->iem.s.offOpcode); \
209 pTb->cbOpcodes = offOpcodeMc2 + pVCpu->iem.s.offOpcode; \
210 pTb->aRanges[idxRangeMc2].cbOpcodes += cbInstrMc2; \
211 Assert(pTb->cbOpcodes <= pVCpu->iem.s.cbOpcodesAllocated); \
212 } \
213 else if (iemThreadedCompileBeginEmitCallsComplications(pVCpu, pTb)) \
214 { /* likely */ } \
215 else \
216 return VINF_IEM_RECOMPILE_END_TB; \
217 \
218 uint8_t const idxInstrMc2 = pTb->cInstructions; \
219 \
220 /* Emit hardware instruction breakpoint check if enabled. */ \
221 if (!(pTb->fFlags & IEM_F_PENDING_BRK_INSTR)) \
222 { /* likely */ } \
223 else \
224 IEM_MC2_EMIT_CALL_0(kIemThreadedFunc_BltIn_CheckHwInstrBps)
225
226#define IEM_MC2_EMIT_CALL_0(a_enmFunction) do { \
227 IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
228 \
229 LogFlow(("Call #%u: " #a_enmFunction "\n", pTb->Thrd.cCalls)); \
230 PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
231 pCall->enmFunction = a_enmFunction; \
232 pCall->idxInstr = idxInstrMc2; \
233 pCall->cbOpcode = cbInstrMc2; \
234 pCall->offOpcode = offOpcodeMc2; \
235 pCall->uUnused0 = 0; \
236 pCall->auParams[0] = 0; \
237 pCall->auParams[1] = 0; \
238 pCall->auParams[2] = 0; \
239 } while (0)
240#define IEM_MC2_EMIT_CALL_1(a_enmFunction, a_uArg0) do { \
241 IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
242 uint64_t const uArg0Check = (a_uArg0); RT_NOREF(uArg0Check); \
243 \
244 LogFlow(("Call #%u: " #a_enmFunction " a0=%RX64\n", pTb->Thrd.cCalls, (uint64_t)a_uArg0)); \
245 PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
246 pCall->enmFunction = a_enmFunction; \
247 pCall->idxInstr = idxInstrMc2; \
248 pCall->cbOpcode = cbInstrMc2; \
249 pCall->offOpcode = offOpcodeMc2; \
250 pCall->uUnused0 = 0; \
251 pCall->auParams[0] = a_uArg0; \
252 pCall->auParams[1] = 0; \
253 pCall->auParams[2] = 0; \
254 } while (0)
255#define IEM_MC2_EMIT_CALL_2(a_enmFunction, a_uArg0, a_uArg1) do { \
256 IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
257 uint64_t const uArg0Check = (a_uArg0); RT_NOREF(uArg0Check); \
258 uint64_t const uArg1Check = (a_uArg1); RT_NOREF(uArg1Check); \
259 \
260 LogFlow(("Call #%u: " #a_enmFunction " a0=%RX64 a1=%RX64\n", pTb->Thrd.cCalls, (uint64_t)a_uArg0, (uint64_t)a_uArg1)); \
261 PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
262 pCall->enmFunction = a_enmFunction; \
263 pCall->idxInstr = idxInstrMc2; \
264 pCall->cbOpcode = cbInstrMc2; \
265 pCall->offOpcode = offOpcodeMc2; \
266 pCall->uUnused0 = 0; \
267 pCall->auParams[0] = a_uArg0; \
268 pCall->auParams[1] = a_uArg1; \
269 pCall->auParams[2] = 0; \
270 } while (0)
271#define IEM_MC2_EMIT_CALL_3(a_enmFunction, a_uArg0, a_uArg1, a_uArg2) do { \
272 IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
273 uint64_t const uArg0Check = (a_uArg0); RT_NOREF(uArg0Check); \
274 uint64_t const uArg1Check = (a_uArg1); RT_NOREF(uArg1Check); \
275 uint64_t const uArg2Check = (a_uArg2); RT_NOREF(uArg2Check); \
276 \
277 LogFlow(("Call #%u: " #a_enmFunction " a0=%RX64 a1=%RX64 a2=%RX64\n", pTb->Thrd.cCalls, (uint64_t)a_uArg0, (uint64_t)a_uArg1, (uint64_t)a_uArg2)); \
278 PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
279 pCall->enmFunction = a_enmFunction; \
280 pCall->idxInstr = idxInstrMc2; \
281 pCall->offOpcode = offOpcodeMc2; \
282 pCall->cbOpcode = cbInstrMc2; \
283 pCall->uUnused0 = 0; \
284 pCall->auParams[0] = a_uArg0; \
285 pCall->auParams[1] = a_uArg1; \
286 pCall->auParams[2] = a_uArg2; \
287 } while (0)
288#define IEM_MC2_END_EMIT_CALLS(a_fCImplFlags) \
289 Assert(pTb->cInstructions <= pTb->Thrd.cCalls); \
290 if (pTb->cInstructions < 255) \
291 pTb->cInstructions++; \
292 uint32_t const fCImplFlagsMc2 = (a_fCImplFlags); \
293 RT_NOREF(fCImplFlagsMc2); \
294 } while (0)
295
296
297/*
298 * IEM_MC_DEFER_TO_CIMPL_0 is easily wrapped up.
299 *
300 * Doing so will also take care of IEMOP_RAISE_DIVIDE_ERROR, IEMOP_RAISE_INVALID_LOCK_PREFIX,
301 * IEMOP_RAISE_INVALID_OPCODE and their users.
302 */
303#undef IEM_MC_DEFER_TO_CIMPL_0_RET
304#define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl) \
305 return iemThreadedRecompilerMcDeferToCImpl0(pVCpu, a_fFlags, a_fGstShwFlush, a_pfnCImpl)
306
307DECLINLINE(VBOXSTRICTRC)
308iemThreadedRecompilerMcDeferToCImpl0(PVMCPUCC pVCpu, uint32_t fFlags, uint64_t fGstShwFlush, PFNIEMCIMPL0 pfnCImpl)
309{
310 LogFlow(("CImpl0: %04x:%08RX64 LB %#x: %#x %#RX64 %p\n",
311 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IEM_GET_INSTR_LEN(pVCpu), fFlags, fGstShwFlush, pfnCImpl));
312 pVCpu->iem.s.fTbCurInstr = fFlags;
313
314 IEM_MC2_BEGIN_EMIT_CALLS(fFlags & IEM_CIMPL_F_CHECK_IRQ_BEFORE);
315 IEM_MC2_EMIT_CALL_3(kIemThreadedFunc_BltIn_DeferToCImpl0, (uintptr_t)pfnCImpl, IEM_GET_INSTR_LEN(pVCpu), fGstShwFlush);
316 if ( (fFlags & (IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT))
317 && !(fFlags & (IEM_CIMPL_F_END_TB | IEM_CIMPL_F_BRANCH_FAR)))
318 IEM_MC2_EMIT_CALL_1(kIemThreadedFunc_BltIn_CheckMode, pVCpu->iem.s.fExec);
319 IEM_MC2_END_EMIT_CALLS(fFlags);
320
321 /*
322 * We have to repeat work normally done by kdCImplFlags and
323 * ThreadedFunctionVariation.emitThreadedCallStmts here.
324 */
325 AssertCompile(IEM_CIMPL_F_BRANCH_DIRECT == IEMBRANCHED_F_DIRECT);
326 AssertCompile(IEM_CIMPL_F_BRANCH_INDIRECT == IEMBRANCHED_F_INDIRECT);
327 AssertCompile(IEM_CIMPL_F_BRANCH_RELATIVE == IEMBRANCHED_F_RELATIVE);
328 AssertCompile(IEM_CIMPL_F_BRANCH_CONDITIONAL == IEMBRANCHED_F_CONDITIONAL);
329 AssertCompile(IEM_CIMPL_F_BRANCH_FAR == IEMBRANCHED_F_FAR);
330
331 if (fFlags & (IEM_CIMPL_F_END_TB | IEM_CIMPL_F_BRANCH_FAR))
332 pVCpu->iem.s.fEndTb = true;
333 else if (fFlags & IEM_CIMPL_F_BRANCH_ANY)
334 pVCpu->iem.s.fTbBranched = fFlags & (IEM_CIMPL_F_BRANCH_ANY | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_CONDITIONAL);
335
336 if (fFlags & IEM_CIMPL_F_CHECK_IRQ_BEFORE)
337 pVCpu->iem.s.cInstrTillIrqCheck = 0;
338
339 return pfnCImpl(pVCpu, IEM_GET_INSTR_LEN(pVCpu));
340}
341
342
343/**
344 * Helper for indicating that we've branched.
345 */
346DECL_FORCE_INLINE(void) iemThreadedSetBranched(PVMCPUCC pVCpu, uint8_t fTbBranched)
347{
348 pVCpu->iem.s.fTbBranched = fTbBranched;
349 //pVCpu->iem.s.GCPhysTbBranchSrcBuf = pVCpu->iem.s.GCPhysInstrBuf;
350 //pVCpu->iem.s.GCVirtTbBranchSrcBuf = pVCpu->iem.s.uInstrBufPc;
351}
352
353
354#endif /* !VMM_INCLUDED_SRC_VMMAll_IEMAllThrdTables_h */
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