VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap3.cpp.h@ 96860

Last change on this file since 96860 was 96652, checked in by vboxsync, 21 months ago

VMM/IEM: Implement [v]pclmulqdq instruction, ​bugref:9898
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1/* $Id: IEMAllInstructionsVexMap3.cpp.h 96652 2022-09-08 08:49:40Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4 *
5 * @remarks IEMAllInstructionsThree0f3a.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 3
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128, imm8
39 * - vpxxx ymm0, ymm1, ymm2/mem256, imm8
40 *
41 * Takes function table for function w/o implicit state parameter.
42 *
43 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
44 */
45FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
46{
47 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48 if (IEM_IS_MODRM_REG_MODE(bRm))
49 {
50 /*
51 * Register, register.
52 */
53 if (pVCpu->iem.s.uVexLength)
54 {
55 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
56 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
57 IEM_MC_BEGIN(4, 3);
58 IEM_MC_LOCAL(RTUINT256U, uDst);
59 IEM_MC_LOCAL(RTUINT256U, uSrc1);
60 IEM_MC_LOCAL(RTUINT256U, uSrc2);
61 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
62 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
63 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
64 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
65 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
66 IEM_MC_PREPARE_AVX_USAGE();
67 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
68 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
69 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
70 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
71 IEM_MC_ADVANCE_RIP();
72 IEM_MC_END();
73 }
74 else
75 {
76 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
77 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
78 IEM_MC_BEGIN(4, 0);
79 IEM_MC_ARG(PRTUINT128U, puDst, 0);
80 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
81 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
82 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
83 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
84 IEM_MC_PREPARE_AVX_USAGE();
85 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
86 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
87 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
88 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
89 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
90 IEM_MC_ADVANCE_RIP();
91 IEM_MC_END();
92 }
93 }
94 else
95 {
96 /*
97 * Register, memory.
98 */
99 if (pVCpu->iem.s.uVexLength)
100 {
101 IEM_MC_BEGIN(4, 4);
102 IEM_MC_LOCAL(RTUINT256U, uDst);
103 IEM_MC_LOCAL(RTUINT256U, uSrc1);
104 IEM_MC_LOCAL(RTUINT256U, uSrc2);
105 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
106 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
107 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
108 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
109
110 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
111 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
112 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
113 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
114 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
115 IEM_MC_PREPARE_AVX_USAGE();
116
117 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
118 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
119 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
120 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
121
122 IEM_MC_ADVANCE_RIP();
123 IEM_MC_END();
124 }
125 else
126 {
127 IEM_MC_BEGIN(4, 2);
128 IEM_MC_LOCAL(RTUINT128U, uSrc2);
129 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
130 IEM_MC_ARG(PRTUINT128U, puDst, 0);
131 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
132 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
133
134 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
135 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
136 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
137 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
138 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
139 IEM_MC_PREPARE_AVX_USAGE();
140
141 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
142 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
143 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
144 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
145 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
146
147 IEM_MC_ADVANCE_RIP();
148 IEM_MC_END();
149 }
150 }
151 return VINF_SUCCESS;
152}
153
154
155/** Opcode VEX.66.0F3A 0x00. */
156FNIEMOP_STUB(iemOp_vpermq_Vqq_Wqq_Ib);
157/** Opcode VEX.66.0F3A 0x01. */
158FNIEMOP_STUB(iemOp_vpermqd_Vqq_Wqq_Ib);
159/** Opcode VEX.66.0F3A 0x02. */
160FNIEMOP_STUB(iemOp_vpblendd_Vx_Wx_Ib);
161/* Opcode VEX.66.0F3A 0x03 - invalid */
162/** Opcode VEX.66.0F3A 0x04. */
163FNIEMOP_STUB(iemOp_vpermilps_Vx_Wx_Ib);
164/** Opcode VEX.66.0F3A 0x05. */
165FNIEMOP_STUB(iemOp_vpermilpd_Vx_Wx_Ib);
166/** Opcode VEX.66.0F3A 0x06 (vex only) */
167FNIEMOP_STUB(iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib);
168/* Opcode VEX.66.0F3A 0x07 - invalid */
169/** Opcode VEX.66.0F3A 0x08. */
170FNIEMOP_STUB(iemOp_vroundps_Vx_Wx_Ib);
171/** Opcode VEX.66.0F3A 0x09. */
172FNIEMOP_STUB(iemOp_vroundpd_Vx_Wx_Ib);
173/** Opcode VEX.66.0F3A 0x0a. */
174FNIEMOP_STUB(iemOp_vroundss_Vss_Wss_Ib);
175/** Opcode VEX.66.0F3A 0x0b. */
176FNIEMOP_STUB(iemOp_vroundsd_Vsd_Wsd_Ib);
177
178
179/** Opcode VEX.66.0F3A 0x0c. */
180FNIEMOP_DEF(iemOp_vblendps_Vx_Hx_Wx_Ib)
181{
182 IEMOP_MNEMONIC3(VEX_RVM, VBLENDPS, vblendps, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
183 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendps);
184 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
185}
186
187
188/** Opcode VEX.66.0F3A 0x0d. */
189FNIEMOP_DEF(iemOp_vblendpd_Vx_Hx_Wx_Ib)
190{
191 IEMOP_MNEMONIC3(VEX_RVM, VBLENDPD, vblendpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
192 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendpd);
193 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
194}
195
196
197/** Opcode VEX.66.0F3A 0x0e. */
198FNIEMOP_DEF(iemOp_vpblendw_Vx_Hx_Wx_Ib)
199{
200 IEMOP_MNEMONIC3(VEX_RVM, VPBLENDW, vpblendw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
201 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendw);
202 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
203}
204
205
206/** Opcode VEX.0F3A 0x0f - invalid. */
207
208
209/** Opcode VEX.66.0F3A 0x0f. */
210FNIEMOP_DEF(iemOp_vpalignr_Vx_Hx_Wx_Ib)
211{
212 IEMOP_MNEMONIC3(VEX_RVM, VPALIGNR, vpalignr, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
213 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpalignr);
214 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
215}
216
217
218/* Opcode VEX.66.0F3A 0x10 - invalid */
219/* Opcode VEX.66.0F3A 0x11 - invalid */
220/* Opcode VEX.66.0F3A 0x12 - invalid */
221/* Opcode VEX.66.0F3A 0x13 - invalid */
222/** Opcode VEX.66.0F3A 0x14. */
223FNIEMOP_STUB(iemOp_vpextrb_RdMb_Vdq_Ib);
224/** Opcode VEX.66.0F3A 0x15. */
225FNIEMOP_STUB(iemOp_vpextrw_RdMw_Vdq_Ib);
226/** Opcode VEX.66.0F3A 0x16. */
227FNIEMOP_STUB(iemOp_vpextrd_q_RdMw_Vdq_Ib);
228/** Opcode VEX.66.0F3A 0x17. */
229FNIEMOP_STUB(iemOp_vextractps_Ed_Vdq_Ib);
230/** Opcode VEX.66.0F3A 0x18 (vex only). */
231FNIEMOP_STUB(iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib);
232/** Opcode VEX.66.0F3A 0x19 (vex only). */
233FNIEMOP_STUB(iemOp_vextractf128_Wdq_Vqq_Ib);
234/* Opcode VEX.66.0F3A 0x1a - invalid */
235/* Opcode VEX.66.0F3A 0x1b - invalid */
236/* Opcode VEX.66.0F3A 0x1c - invalid */
237/** Opcode VEX.66.0F3A 0x1d (vex only). */
238FNIEMOP_STUB(iemOp_vcvtps2ph_Wx_Vx_Ib);
239/* Opcode VEX.66.0F3A 0x1e - invalid */
240/* Opcode VEX.66.0F3A 0x1f - invalid */
241
242
243/** Opcode VEX.66.0F3A 0x20. */
244FNIEMOP_STUB(iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib);
245/** Opcode VEX.66.0F3A 0x21, */
246FNIEMOP_STUB(iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib);
247/** Opcode VEX.66.0F3A 0x22. */
248FNIEMOP_STUB(iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib);
249/* Opcode VEX.66.0F3A 0x23 - invalid */
250/* Opcode VEX.66.0F3A 0x24 - invalid */
251/* Opcode VEX.66.0F3A 0x25 - invalid */
252/* Opcode VEX.66.0F3A 0x26 - invalid */
253/* Opcode VEX.66.0F3A 0x27 - invalid */
254/* Opcode VEX.66.0F3A 0x28 - invalid */
255/* Opcode VEX.66.0F3A 0x29 - invalid */
256/* Opcode VEX.66.0F3A 0x2a - invalid */
257/* Opcode VEX.66.0F3A 0x2b - invalid */
258/* Opcode VEX.66.0F3A 0x2c - invalid */
259/* Opcode VEX.66.0F3A 0x2d - invalid */
260/* Opcode VEX.66.0F3A 0x2e - invalid */
261/* Opcode VEX.66.0F3A 0x2f - invalid */
262
263
264/* Opcode VEX.66.0F3A 0x30 - invalid */
265/* Opcode VEX.66.0F3A 0x31 - invalid */
266/* Opcode VEX.66.0F3A 0x32 - invalid */
267/* Opcode VEX.66.0F3A 0x33 - invalid */
268/* Opcode VEX.66.0F3A 0x34 - invalid */
269/* Opcode VEX.66.0F3A 0x35 - invalid */
270/* Opcode VEX.66.0F3A 0x36 - invalid */
271/* Opcode VEX.66.0F3A 0x37 - invalid */
272/** Opcode VEX.66.0F3A 0x38 (vex only). */
273FNIEMOP_STUB(iemOp_vinserti128_Vqq_Hqq_Wqq_Ib);
274/** Opcode VEX.66.0F3A 0x39 (vex only). */
275FNIEMOP_STUB(iemOp_vextracti128_Wdq_Vqq_Ib);
276/* Opcode VEX.66.0F3A 0x3a - invalid */
277/* Opcode VEX.66.0F3A 0x3b - invalid */
278/* Opcode VEX.66.0F3A 0x3c - invalid */
279/* Opcode VEX.66.0F3A 0x3d - invalid */
280/* Opcode VEX.66.0F3A 0x3e - invalid */
281/* Opcode VEX.66.0F3A 0x3f - invalid */
282
283
284/** Opcode VEX.66.0F3A 0x40. */
285FNIEMOP_STUB(iemOp_vdpps_Vx_Hx_Wx_Ib);
286/** Opcode VEX.66.0F3A 0x41, */
287FNIEMOP_STUB(iemOp_vdppd_Vdq_Hdq_Wdq_Ib);
288/** Opcode VEX.66.0F3A 0x42. */
289FNIEMOP_STUB(iemOp_vmpsadbw_Vx_Hx_Wx_Ib);
290/* Opcode VEX.66.0F3A 0x43 - invalid */
291
292
293/** Opcode VEX.66.0F3A 0x44. */
294FNIEMOP_DEF(iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib)
295{
296 //IEMOP_MNEMONIC3(VEX_RVM, VPCLMULQDQ, vpclmulqdq, Vdq, Hdq, Wdq, DISOPTYPE_HARMLESS, 0); /* @todo */
297
298 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
299 if (IEM_IS_MODRM_REG_MODE(bRm))
300 {
301 /*
302 * Register, register.
303 */
304 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
305 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
306 IEM_MC_BEGIN(4, 0);
307 IEM_MC_ARG(PRTUINT128U, puDst, 0);
308 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
309 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
310 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
311 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
312 IEM_MC_PREPARE_AVX_USAGE();
313 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
314 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
315 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
316 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
317 puDst, puSrc1, puSrc2, bImmArg);
318 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
319 IEM_MC_ADVANCE_RIP();
320 IEM_MC_END();
321 }
322 else
323 {
324 /*
325 * Register, memory.
326 */
327 IEM_MC_BEGIN(4, 2);
328 IEM_MC_LOCAL(RTUINT128U, uSrc2);
329 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
330 IEM_MC_ARG(PRTUINT128U, puDst, 0);
331 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
332 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
333
334 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
335 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
336 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
337 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
338 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
339 IEM_MC_PREPARE_AVX_USAGE();
340
341 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
342 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
343 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
344 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
345 puDst, puSrc1, puSrc2, bImmArg);
346 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
347
348 IEM_MC_ADVANCE_RIP();
349 IEM_MC_END();
350 }
351 return VINF_SUCCESS;
352}
353
354
355/* Opcode VEX.66.0F3A 0x45 - invalid */
356/** Opcode VEX.66.0F3A 0x46 (vex only) */
357FNIEMOP_STUB(iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib);
358/* Opcode VEX.66.0F3A 0x47 - invalid */
359/** Opcode VEX.66.0F3A 0x48 (AMD tables only). */
360FNIEMOP_STUB(iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx);
361/** Opcode VEX.66.0F3A 0x49 (AMD tables only). */
362FNIEMOP_STUB(iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx);
363
364
365/**
366 * Common worker for AVX2 instructions on the forms:
367 * - vpxxx xmm0, xmm1, xmm2/mem128, xmm4
368 * - vpxxx ymm0, ymm1, ymm2/mem256, ymm4
369 *
370 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
371 */
372FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
373{
374 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
375 if (IEM_IS_MODRM_REG_MODE(bRm))
376 {
377 /*
378 * Register, register.
379 */
380 if (pVCpu->iem.s.uVexLength)
381 {
382 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
383
384 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
385 IEM_MC_BEGIN(4, 4);
386 IEM_MC_LOCAL(RTUINT256U, uDst);
387 IEM_MC_LOCAL(RTUINT256U, uSrc1);
388 IEM_MC_LOCAL(RTUINT256U, uSrc2);
389 IEM_MC_LOCAL(RTUINT256U, uSrc3);
390 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
391 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
392 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
393 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
394 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
395 IEM_MC_PREPARE_AVX_USAGE();
396 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
397 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
398 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
399 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
400 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
401 IEM_MC_ADVANCE_RIP();
402 IEM_MC_END();
403 }
404 else
405 {
406 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
407
408 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
409 IEM_MC_BEGIN(4, 0);
410 IEM_MC_ARG(PRTUINT128U, puDst, 0);
411 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
412 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
413 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
414 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
415 IEM_MC_PREPARE_AVX_USAGE();
416 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
417 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
418 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
419 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
420 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
421 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
422 IEM_MC_ADVANCE_RIP();
423 IEM_MC_END();
424 }
425 }
426 else
427 {
428 /*
429 * Register, memory.
430 */
431 if (pVCpu->iem.s.uVexLength)
432 {
433 IEM_MC_BEGIN(4, 5);
434 IEM_MC_LOCAL(RTUINT256U, uDst);
435 IEM_MC_LOCAL(RTUINT256U, uSrc1);
436 IEM_MC_LOCAL(RTUINT256U, uSrc2);
437 IEM_MC_LOCAL(RTUINT256U, uSrc3);
438 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
439 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
440 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
441 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
442 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
443
444 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
445 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
446
447 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
448 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
449 IEM_MC_PREPARE_AVX_USAGE();
450
451 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
452 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
453 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_EFFECTIVE_VVVV(pVCpu));
454 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
455 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
456 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
457
458 IEM_MC_ADVANCE_RIP();
459 IEM_MC_END();
460 }
461 else
462 {
463 IEM_MC_BEGIN(4, 2);
464 IEM_MC_LOCAL(RTUINT128U, uSrc2);
465 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
466 IEM_MC_ARG(PRTUINT128U, puDst, 0);
467 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
468 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
469 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
470
471 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
472 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
473
474 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
475 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
476 IEM_MC_PREPARE_AVX_USAGE();
477
478 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
479 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
480 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
481 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
482 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
483 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
484
485 IEM_MC_ADVANCE_RIP();
486 IEM_MC_END();
487 }
488 }
489 return VINF_SUCCESS;
490}
491
492
493/** Opcode VEX.66.0F3A 0x4a (vex only). */
494FNIEMOP_DEF(iemOp_vblendvps_Vx_Hx_Wx_Lx)
495{
496 //IEMOP_MNEMONIC4(VEX_RVM, VBLENDVPS, vpblendvps, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
497 IEMOPBLENDOP_INIT_VARS(vblendvps);
498 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
499}
500
501
502/** Opcode VEX.66.0F3A 0x4b (vex only). */
503FNIEMOP_DEF(iemOp_vblendvpd_Vx_Hx_Wx_Lx)
504{
505 //IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVPD, blendvpd, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
506 IEMOPBLENDOP_INIT_VARS(vblendvpd);
507 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
508}
509
510
511/** Opcode VEX.66.0F3A 0x4c (vex only). */
512FNIEMOP_DEF(iemOp_vpblendvb_Vx_Hx_Wx_Lx)
513{
514 //IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVB, vpblendvb, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
515 IEMOPBLENDOP_INIT_VARS(vpblendvb);
516 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
517}
518
519
520/* Opcode VEX.66.0F3A 0x4d - invalid */
521/* Opcode VEX.66.0F3A 0x4e - invalid */
522/* Opcode VEX.66.0F3A 0x4f - invalid */
523
524
525/* Opcode VEX.66.0F3A 0x50 - invalid */
526/* Opcode VEX.66.0F3A 0x51 - invalid */
527/* Opcode VEX.66.0F3A 0x52 - invalid */
528/* Opcode VEX.66.0F3A 0x53 - invalid */
529/* Opcode VEX.66.0F3A 0x54 - invalid */
530/* Opcode VEX.66.0F3A 0x55 - invalid */
531/* Opcode VEX.66.0F3A 0x56 - invalid */
532/* Opcode VEX.66.0F3A 0x57 - invalid */
533/* Opcode VEX.66.0F3A 0x58 - invalid */
534/* Opcode VEX.66.0F3A 0x59 - invalid */
535/* Opcode VEX.66.0F3A 0x5a - invalid */
536/* Opcode VEX.66.0F3A 0x5b - invalid */
537/** Opcode VEX.66.0F3A 0x5c (AMD tables only). */
538FNIEMOP_STUB(iemOp_vfmaddsubps_Vx_Lx_Wx_Hx);
539/** Opcode VEX.66.0F3A 0x5d (AMD tables only). */
540FNIEMOP_STUB(iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx);
541/** Opcode VEX.66.0F3A 0x5e (AMD tables only). */
542FNIEMOP_STUB(iemOp_vfmsubaddps_Vx_Lx_Wx_Hx);
543/** Opcode VEX.66.0F3A 0x5f (AMD tables only). */
544FNIEMOP_STUB(iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx);
545
546
547/** Opcode VEX.66.0F3A 0x60. */
548FNIEMOP_STUB(iemOp_vpcmpestrm_Vdq_Wdq_Ib);
549/** Opcode VEX.66.0F3A 0x61, */
550FNIEMOP_STUB(iemOp_vpcmpestri_Vdq_Wdq_Ib);
551/** Opcode VEX.66.0F3A 0x62. */
552FNIEMOP_STUB(iemOp_vpcmpistrm_Vdq_Wdq_Ib);
553/** Opcode VEX.66.0F3A 0x63*/
554FNIEMOP_STUB(iemOp_vpcmpistri_Vdq_Wdq_Ib);
555/* Opcode VEX.66.0F3A 0x64 - invalid */
556/* Opcode VEX.66.0F3A 0x65 - invalid */
557/* Opcode VEX.66.0F3A 0x66 - invalid */
558/* Opcode VEX.66.0F3A 0x67 - invalid */
559/** Opcode VEX.66.0F3A 0x68 (AMD tables only). */
560FNIEMOP_STUB(iemOp_vfmaddps_Vx_Lx_Wx_Hx);
561/** Opcode VEX.66.0F3A 0x69 (AMD tables only). */
562FNIEMOP_STUB(iemOp_vfmaddpd_Vx_Lx_Wx_Hx);
563/** Opcode VEX.66.0F3A 0x6a (AMD tables only). */
564FNIEMOP_STUB(iemOp_vfmaddss_Vx_Lx_Wx_Hx);
565/** Opcode VEX.66.0F3A 0x6b (AMD tables only). */
566FNIEMOP_STUB(iemOp_vfmaddsd_Vx_Lx_Wx_Hx);
567/** Opcode VEX.66.0F3A 0x6c (AMD tables only). */
568FNIEMOP_STUB(iemOp_vfmsubps_Vx_Lx_Wx_Hx);
569/** Opcode VEX.66.0F3A 0x6d (AMD tables only). */
570FNIEMOP_STUB(iemOp_vfmsubpd_Vx_Lx_Wx_Hx);
571/** Opcode VEX.66.0F3A 0x6e (AMD tables only). */
572FNIEMOP_STUB(iemOp_vfmsubss_Vx_Lx_Wx_Hx);
573/** Opcode VEX.66.0F3A 0x6f (AMD tables only). */
574FNIEMOP_STUB(iemOp_vfmsubsd_Vx_Lx_Wx_Hx);
575
576/* Opcode VEX.66.0F3A 0x70 - invalid */
577/* Opcode VEX.66.0F3A 0x71 - invalid */
578/* Opcode VEX.66.0F3A 0x72 - invalid */
579/* Opcode VEX.66.0F3A 0x73 - invalid */
580/* Opcode VEX.66.0F3A 0x74 - invalid */
581/* Opcode VEX.66.0F3A 0x75 - invalid */
582/* Opcode VEX.66.0F3A 0x76 - invalid */
583/* Opcode VEX.66.0F3A 0x77 - invalid */
584/** Opcode VEX.66.0F3A 0x78 (AMD tables only). */
585FNIEMOP_STUB(iemOp_vfnmaddps_Vx_Lx_Wx_Hx);
586/** Opcode VEX.66.0F3A 0x79 (AMD tables only). */
587FNIEMOP_STUB(iemOp_vfnmaddpd_Vx_Lx_Wx_Hx);
588/** Opcode VEX.66.0F3A 0x7a (AMD tables only). */
589FNIEMOP_STUB(iemOp_vfnmaddss_Vx_Lx_Wx_Hx);
590/** Opcode VEX.66.0F3A 0x7b (AMD tables only). */
591FNIEMOP_STUB(iemOp_vfnmaddsd_Vx_Lx_Wx_Hx);
592/** Opcode VEX.66.0F3A 0x7c (AMD tables only). */
593FNIEMOP_STUB(iemOp_vfnmsubps_Vx_Lx_Wx_Hx);
594/** Opcode VEX.66.0F3A 0x7d (AMD tables only). */
595FNIEMOP_STUB(iemOp_vfnmsubpd_Vx_Lx_Wx_Hx);
596/** Opcode VEX.66.0F3A 0x7e (AMD tables only). */
597FNIEMOP_STUB(iemOp_vfnmsubss_Vx_Lx_Wx_Hx);
598/** Opcode VEX.66.0F3A 0x7f (AMD tables only). */
599FNIEMOP_STUB(iemOp_vfnmsubsd_Vx_Lx_Wx_Hx);
600
601/* Opcodes 0x0f 0x80 thru 0x0f 0xb0 are unused. */
602
603
604/* Opcode 0x0f 0xc0 - invalid */
605/* Opcode 0x0f 0xc1 - invalid */
606/* Opcode 0x0f 0xc2 - invalid */
607/* Opcode 0x0f 0xc3 - invalid */
608/* Opcode 0x0f 0xc4 - invalid */
609/* Opcode 0x0f 0xc5 - invalid */
610/* Opcode 0x0f 0xc6 - invalid */
611/* Opcode 0x0f 0xc7 - invalid */
612/* Opcode 0x0f 0xc8 - invalid */
613/* Opcode 0x0f 0xc9 - invalid */
614/* Opcode 0x0f 0xca - invalid */
615/* Opcode 0x0f 0xcb - invalid */
616/* Opcode 0x0f 0xcc */
617FNIEMOP_STUB(iemOp_vsha1rnds4_Vdq_Wdq_Ib);
618/* Opcode 0x0f 0xcd - invalid */
619/* Opcode 0x0f 0xce - invalid */
620/* Opcode 0x0f 0xcf - invalid */
621
622
623/* Opcode VEX.66.0F3A 0xd0 - invalid */
624/* Opcode VEX.66.0F3A 0xd1 - invalid */
625/* Opcode VEX.66.0F3A 0xd2 - invalid */
626/* Opcode VEX.66.0F3A 0xd3 - invalid */
627/* Opcode VEX.66.0F3A 0xd4 - invalid */
628/* Opcode VEX.66.0F3A 0xd5 - invalid */
629/* Opcode VEX.66.0F3A 0xd6 - invalid */
630/* Opcode VEX.66.0F3A 0xd7 - invalid */
631/* Opcode VEX.66.0F3A 0xd8 - invalid */
632/* Opcode VEX.66.0F3A 0xd9 - invalid */
633/* Opcode VEX.66.0F3A 0xda - invalid */
634/* Opcode VEX.66.0F3A 0xdb - invalid */
635/* Opcode VEX.66.0F3A 0xdc - invalid */
636/* Opcode VEX.66.0F3A 0xdd - invalid */
637/* Opcode VEX.66.0F3A 0xde - invalid */
638/* Opcode VEX.66.0F3A 0xdf - (aeskeygenassist). */
639FNIEMOP_STUB(iemOp_vaeskeygen_Vdq_Wdq_Ib);
640
641
642/** Opcode VEX.F2.0F3A (vex only) */
643FNIEMOP_DEF(iemOp_rorx_Gy_Ey_Ib)
644{
645 IEMOP_MNEMONIC3(VEX_RMI, RORX, rorx, Gy, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO);
646 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
647 return iemOp_InvalidNeedRMImm8(pVCpu);
648 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
649 if (IEM_IS_MODRM_REG_MODE(bRm))
650 {
651 /*
652 * Register, register.
653 */
654 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
655 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
656 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
657 {
658 IEM_MC_BEGIN(3, 0);
659 IEM_MC_ARG(uint64_t *, pDst, 0);
660 IEM_MC_ARG(uint64_t, uSrc1, 1);
661 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
662 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
663 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
664 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
665 IEM_MC_ADVANCE_RIP();
666 IEM_MC_END();
667 }
668 else
669 {
670 IEM_MC_BEGIN(3, 0);
671 IEM_MC_ARG(uint32_t *, pDst, 0);
672 IEM_MC_ARG(uint32_t, uSrc1, 1);
673 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
674 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
675 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
676 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
677 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
678 IEM_MC_ADVANCE_RIP();
679 IEM_MC_END();
680 }
681 }
682 else
683 {
684 /*
685 * Register, memory.
686 */
687 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
688 {
689 IEM_MC_BEGIN(3, 1);
690 IEM_MC_ARG(uint64_t *, pDst, 0);
691 IEM_MC_ARG(uint64_t, uSrc1, 1);
692 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
693 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
694 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
695 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
696 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
697 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
698 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
699 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
700 IEM_MC_ADVANCE_RIP();
701 IEM_MC_END();
702 }
703 else
704 {
705 IEM_MC_BEGIN(3, 1);
706 IEM_MC_ARG(uint32_t *, pDst, 0);
707 IEM_MC_ARG(uint32_t, uSrc1, 1);
708 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
709 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
710 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
711 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
712 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
713 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
714 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
715 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
716 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
717 IEM_MC_ADVANCE_RIP();
718 IEM_MC_END();
719 }
720 }
721 return VINF_SUCCESS;
722}
723
724
725/**
726 * VEX opcode map \#3.
727 *
728 * @sa g_apfnThreeByte0f3a
729 */
730IEM_STATIC const PFNIEMOP g_apfnVexMap3[] =
731{
732 /* no prefix, 066h prefix f3h prefix, f2h prefix */
733 /* 0x00 */ iemOp_InvalidNeedRMImm8, iemOp_vpermq_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
734 /* 0x01 */ iemOp_InvalidNeedRMImm8, iemOp_vpermqd_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
735 /* 0x02 */ iemOp_InvalidNeedRMImm8, iemOp_vpblendd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
736 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
737 /* 0x04 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
738 /* 0x05 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
739 /* 0x06 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
740 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
741 /* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_vroundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
742 /* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_vroundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
743 /* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_vroundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
744 /* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_vroundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
745 /* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_vblendps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
746 /* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_vblendpd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
747 /* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_vpblendw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
748 /* 0x0f */ iemOp_InvalidNeedRMImm8, iemOp_vpalignr_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
749
750 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
751 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
752 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
753 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
754 /* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
755 /* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
756 /* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
757 /* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_vextractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
758 /* 0x18 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
759 /* 0x19 */ iemOp_InvalidNeedRMImm8, iemOp_vextractf128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
760 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
761 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
762 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
763 /* 0x1d */ iemOp_InvalidNeedRMImm8, iemOp_vcvtps2ph_Wx_Vx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
764 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
765 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
766
767 /* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
768 /* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
769 /* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
770 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
771 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
772 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
773 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
774 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
775 /* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
776 /* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
777 /* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
778 /* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
779 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
780 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
781 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
782 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
783
784 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
785 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
786 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
787 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
788 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
789 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
790 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
791 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
792 /* 0x38 */ iemOp_InvalidNeedRMImm8, iemOp_vinserti128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
793 /* 0x39 */ iemOp_InvalidNeedRMImm8, iemOp_vextracti128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
794 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
795 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
796 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
797 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
798 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
799 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
800
801 /* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_vdpps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
802 /* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_vdppd_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
803 /* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_vmpsadbw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
804 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
805 /* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
806 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
807 /* 0x46 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
808 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
809 /* 0x48 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
810 /* 0x49 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
811 /* 0x4a */ iemOp_InvalidNeedRMImm8, iemOp_vblendvps_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
812 /* 0x4b */ iemOp_InvalidNeedRMImm8, iemOp_vblendvpd_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
813 /* 0x4c */ iemOp_InvalidNeedRMImm8, iemOp_vpblendvb_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
814 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
815 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
816 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
817
818 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
819 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
820 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
821 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
822 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
823 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
824 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
825 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
826 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
827 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
828 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
829 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
830 /* 0x5c */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
831 /* 0x5d */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
832 /* 0x5e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
833 /* 0x5f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
834
835 /* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
836 /* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
837 /* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
838 /* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
839 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
840 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
841 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
842 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
843 /* 0x68 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
844 /* 0x69 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
845 /* 0x6a */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
846 /* 0x6b */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
847 /* 0x6c */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
848 /* 0x6d */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
849 /* 0x6e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
850 /* 0x6f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
851
852 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
853 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
854 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
855 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
856 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
857 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
858 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
859 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
860 /* 0x78 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
861 /* 0x79 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
862 /* 0x7a */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
863 /* 0x7b */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
864 /* 0x7c */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
865 /* 0x7d */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
866 /* 0x7e */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
867 /* 0x7f */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
868
869 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
870 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
871 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
872 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
873 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
874 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
875 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
876 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
877 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
878 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
879 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
880 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
881 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
882 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
883 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
884 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
885
886 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
887 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
888 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
889 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
890 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
891 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
892 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
893 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
894 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
895 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
896 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
897 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
898 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
899 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
900 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
901 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
902
903 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
904 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
905 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
906 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
907 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
908 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
909 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
910 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
911 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
912 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
913 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
914 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
915 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
916 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
917 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
918 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
919
920 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
921 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
922 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
923 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
924 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
925 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
926 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
927 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
928 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
929 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
930 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
931 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
932 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
933 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
934 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
935 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
936
937 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
938 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
939 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
940 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
941 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
942 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
943 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
944 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
945 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
946 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
947 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
948 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
949 /* 0xcc */ iemOp_vsha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
950 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
951 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
952 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
953
954 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
955 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
956 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
957 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
958 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
959 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
960 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
961 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
962 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
963 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
964 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
965 /* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
966 /* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
967 /* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
968 /* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
969 /* 0xdf */ iemOp_vaeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
970
971 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
972 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
973 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
974 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
975 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
976 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
977 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
978 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
979 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
980 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
981 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
982 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
983 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
984 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
985 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
986 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
987
988 /* 0xf0 */ iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_rorx_Gy_Ey_Ib,
989 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
990 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
991 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
992 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
993 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
994 /* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
995 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
996 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
997 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
998 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
999 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1000 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1001 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1002 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1003 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1004};
1005AssertCompile(RT_ELEMENTS(g_apfnVexMap3) == 1024);
1006
1007/** @} */
1008
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