VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap3.cpp.h@ 96533

Last change on this file since 96533 was 96533, checked in by vboxsync, 3 years ago

VMM/IEM: Implement [v]palignr instructions, bugref:9898
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1/* $Id: IEMAllInstructionsVexMap3.cpp.h 96533 2022-08-27 10:47:35Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4 *
5 * @remarks IEMAllInstructionsThree0f3a.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 3
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128, imm8
39 * - vpxxx ymm0, ymm1, ymm2/mem256, imm8
40 *
41 * Takes function table for function w/o implicit state parameter.
42 *
43 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
44 */
45FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
46{
47 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48 if (IEM_IS_MODRM_REG_MODE(bRm))
49 {
50 /*
51 * Register, register.
52 */
53 if (pVCpu->iem.s.uVexLength)
54 {
55 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
56 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
57 IEM_MC_BEGIN(4, 3);
58 IEM_MC_LOCAL(RTUINT256U, uDst);
59 IEM_MC_LOCAL(RTUINT256U, uSrc1);
60 IEM_MC_LOCAL(RTUINT256U, uSrc2);
61 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
62 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
63 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
64 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
65 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
66 IEM_MC_PREPARE_AVX_USAGE();
67 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
68 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
69 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
70 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
71 IEM_MC_ADVANCE_RIP();
72 IEM_MC_END();
73 }
74 else
75 {
76 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
77 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
78 IEM_MC_BEGIN(4, 0);
79 IEM_MC_ARG(PRTUINT128U, puDst, 0);
80 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
81 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
82 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
83 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
84 IEM_MC_PREPARE_AVX_USAGE();
85 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
86 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
87 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
88 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
89 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
90 IEM_MC_ADVANCE_RIP();
91 IEM_MC_END();
92 }
93 }
94 else
95 {
96 /*
97 * Register, memory.
98 */
99 if (pVCpu->iem.s.uVexLength)
100 {
101 IEM_MC_BEGIN(4, 4);
102 IEM_MC_LOCAL(RTUINT256U, uDst);
103 IEM_MC_LOCAL(RTUINT256U, uSrc1);
104 IEM_MC_LOCAL(RTUINT256U, uSrc2);
105 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
106 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
107 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
108 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
109
110 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
111 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
112 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
113 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
114 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
115 IEM_MC_PREPARE_AVX_USAGE();
116
117 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
118 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
119 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
120 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
121
122 IEM_MC_ADVANCE_RIP();
123 IEM_MC_END();
124 }
125 else
126 {
127 IEM_MC_BEGIN(4, 2);
128 IEM_MC_LOCAL(RTUINT128U, uSrc2);
129 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
130 IEM_MC_ARG(PRTUINT128U, puDst, 0);
131 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
132 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
133
134 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
135 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
136 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
137 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
138 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
139 IEM_MC_PREPARE_AVX_USAGE();
140
141 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
142 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
143 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
144 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
145 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
146
147 IEM_MC_ADVANCE_RIP();
148 IEM_MC_END();
149 }
150 }
151 return VINF_SUCCESS;
152}
153
154
155/** Opcode VEX.66.0F3A 0x00. */
156FNIEMOP_STUB(iemOp_vpermq_Vqq_Wqq_Ib);
157/** Opcode VEX.66.0F3A 0x01. */
158FNIEMOP_STUB(iemOp_vpermqd_Vqq_Wqq_Ib);
159/** Opcode VEX.66.0F3A 0x02. */
160FNIEMOP_STUB(iemOp_vpblendd_Vx_Wx_Ib);
161/* Opcode VEX.66.0F3A 0x03 - invalid */
162/** Opcode VEX.66.0F3A 0x04. */
163FNIEMOP_STUB(iemOp_vpermilps_Vx_Wx_Ib);
164/** Opcode VEX.66.0F3A 0x05. */
165FNIEMOP_STUB(iemOp_vpermilpd_Vx_Wx_Ib);
166/** Opcode VEX.66.0F3A 0x06 (vex only) */
167FNIEMOP_STUB(iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib);
168/* Opcode VEX.66.0F3A 0x07 - invalid */
169/** Opcode VEX.66.0F3A 0x08. */
170FNIEMOP_STUB(iemOp_vroundps_Vx_Wx_Ib);
171/** Opcode VEX.66.0F3A 0x09. */
172FNIEMOP_STUB(iemOp_vroundpd_Vx_Wx_Ib);
173/** Opcode VEX.66.0F3A 0x0a. */
174FNIEMOP_STUB(iemOp_vroundss_Vss_Wss_Ib);
175/** Opcode VEX.66.0F3A 0x0b. */
176FNIEMOP_STUB(iemOp_vroundsd_Vsd_Wsd_Ib);
177/** Opcode VEX.66.0F3A 0x0c. */
178FNIEMOP_STUB(iemOp_vblendps_Vx_Hx_Wx_Ib);
179/** Opcode VEX.66.0F3A 0x0d. */
180FNIEMOP_STUB(iemOp_vblendpd_Vx_Hx_Wx_Ib);
181/** Opcode VEX.66.0F3A 0x0e. */
182FNIEMOP_STUB(iemOp_vblendw_Vx_Hx_Wx_Ib);
183/** Opcode VEX.0F3A 0x0f - invalid. */
184
185
186/** Opcode VEX.66.0F3A 0x0f. */
187FNIEMOP_DEF(iemOp_vpalignr_Vx_Hx_Wx_Ib)
188{
189 IEMOP_MNEMONIC3(VEX_RVM, VPALIGNR, vpalignr, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
190 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpalignr);
191 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
192}
193
194
195/* Opcode VEX.66.0F3A 0x10 - invalid */
196/* Opcode VEX.66.0F3A 0x11 - invalid */
197/* Opcode VEX.66.0F3A 0x12 - invalid */
198/* Opcode VEX.66.0F3A 0x13 - invalid */
199/** Opcode VEX.66.0F3A 0x14. */
200FNIEMOP_STUB(iemOp_vpextrb_RdMb_Vdq_Ib);
201/** Opcode VEX.66.0F3A 0x15. */
202FNIEMOP_STUB(iemOp_vpextrw_RdMw_Vdq_Ib);
203/** Opcode VEX.66.0F3A 0x16. */
204FNIEMOP_STUB(iemOp_vpextrd_q_RdMw_Vdq_Ib);
205/** Opcode VEX.66.0F3A 0x17. */
206FNIEMOP_STUB(iemOp_vextractps_Ed_Vdq_Ib);
207/** Opcode VEX.66.0F3A 0x18 (vex only). */
208FNIEMOP_STUB(iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib);
209/** Opcode VEX.66.0F3A 0x19 (vex only). */
210FNIEMOP_STUB(iemOp_vextractf128_Wdq_Vqq_Ib);
211/* Opcode VEX.66.0F3A 0x1a - invalid */
212/* Opcode VEX.66.0F3A 0x1b - invalid */
213/* Opcode VEX.66.0F3A 0x1c - invalid */
214/** Opcode VEX.66.0F3A 0x1d (vex only). */
215FNIEMOP_STUB(iemOp_vcvtps2ph_Wx_Vx_Ib);
216/* Opcode VEX.66.0F3A 0x1e - invalid */
217/* Opcode VEX.66.0F3A 0x1f - invalid */
218
219
220/** Opcode VEX.66.0F3A 0x20. */
221FNIEMOP_STUB(iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib);
222/** Opcode VEX.66.0F3A 0x21, */
223FNIEMOP_STUB(iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib);
224/** Opcode VEX.66.0F3A 0x22. */
225FNIEMOP_STUB(iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib);
226/* Opcode VEX.66.0F3A 0x23 - invalid */
227/* Opcode VEX.66.0F3A 0x24 - invalid */
228/* Opcode VEX.66.0F3A 0x25 - invalid */
229/* Opcode VEX.66.0F3A 0x26 - invalid */
230/* Opcode VEX.66.0F3A 0x27 - invalid */
231/* Opcode VEX.66.0F3A 0x28 - invalid */
232/* Opcode VEX.66.0F3A 0x29 - invalid */
233/* Opcode VEX.66.0F3A 0x2a - invalid */
234/* Opcode VEX.66.0F3A 0x2b - invalid */
235/* Opcode VEX.66.0F3A 0x2c - invalid */
236/* Opcode VEX.66.0F3A 0x2d - invalid */
237/* Opcode VEX.66.0F3A 0x2e - invalid */
238/* Opcode VEX.66.0F3A 0x2f - invalid */
239
240
241/* Opcode VEX.66.0F3A 0x30 - invalid */
242/* Opcode VEX.66.0F3A 0x31 - invalid */
243/* Opcode VEX.66.0F3A 0x32 - invalid */
244/* Opcode VEX.66.0F3A 0x33 - invalid */
245/* Opcode VEX.66.0F3A 0x34 - invalid */
246/* Opcode VEX.66.0F3A 0x35 - invalid */
247/* Opcode VEX.66.0F3A 0x36 - invalid */
248/* Opcode VEX.66.0F3A 0x37 - invalid */
249/** Opcode VEX.66.0F3A 0x38 (vex only). */
250FNIEMOP_STUB(iemOp_vinserti128_Vqq_Hqq_Wqq_Ib);
251/** Opcode VEX.66.0F3A 0x39 (vex only). */
252FNIEMOP_STUB(iemOp_vextracti128_Wdq_Vqq_Ib);
253/* Opcode VEX.66.0F3A 0x3a - invalid */
254/* Opcode VEX.66.0F3A 0x3b - invalid */
255/* Opcode VEX.66.0F3A 0x3c - invalid */
256/* Opcode VEX.66.0F3A 0x3d - invalid */
257/* Opcode VEX.66.0F3A 0x3e - invalid */
258/* Opcode VEX.66.0F3A 0x3f - invalid */
259
260
261/** Opcode VEX.66.0F3A 0x40. */
262FNIEMOP_STUB(iemOp_vdpps_Vx_Hx_Wx_Ib);
263/** Opcode VEX.66.0F3A 0x41, */
264FNIEMOP_STUB(iemOp_vdppd_Vdq_Hdq_Wdq_Ib);
265/** Opcode VEX.66.0F3A 0x42. */
266FNIEMOP_STUB(iemOp_vmpsadbw_Vx_Hx_Wx_Ib);
267/* Opcode VEX.66.0F3A 0x43 - invalid */
268/** Opcode VEX.66.0F3A 0x44. */
269FNIEMOP_STUB(iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib);
270/* Opcode VEX.66.0F3A 0x45 - invalid */
271/** Opcode VEX.66.0F3A 0x46 (vex only) */
272FNIEMOP_STUB(iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib);
273/* Opcode VEX.66.0F3A 0x47 - invalid */
274/** Opcode VEX.66.0F3A 0x48 (AMD tables only). */
275FNIEMOP_STUB(iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx);
276/** Opcode VEX.66.0F3A 0x49 (AMD tables only). */
277FNIEMOP_STUB(iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx);
278
279
280/**
281 * Common worker for AVX2 instructions on the forms:
282 * - vpxxx xmm0, xmm1, xmm2/mem128, xmm4
283 * - vpxxx ymm0, ymm1, ymm2/mem256, ymm4
284 *
285 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
286 */
287FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
288{
289 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
290 if (IEM_IS_MODRM_REG_MODE(bRm))
291 {
292 /*
293 * Register, register.
294 */
295 if (pVCpu->iem.s.uVexLength)
296 {
297 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
298
299 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
300 IEM_MC_BEGIN(4, 4);
301 IEM_MC_LOCAL(RTUINT256U, uDst);
302 IEM_MC_LOCAL(RTUINT256U, uSrc1);
303 IEM_MC_LOCAL(RTUINT256U, uSrc2);
304 IEM_MC_LOCAL(RTUINT256U, uSrc3);
305 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
306 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
307 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
308 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
309 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
310 IEM_MC_PREPARE_AVX_USAGE();
311 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
312 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
313 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
314 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
315 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
316 IEM_MC_ADVANCE_RIP();
317 IEM_MC_END();
318 }
319 else
320 {
321 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
322
323 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
324 IEM_MC_BEGIN(4, 0);
325 IEM_MC_ARG(PRTUINT128U, puDst, 0);
326 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
327 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
328 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
329 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
330 IEM_MC_PREPARE_AVX_USAGE();
331 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
332 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
333 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
334 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
335 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
336 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
337 IEM_MC_ADVANCE_RIP();
338 IEM_MC_END();
339 }
340 }
341 else
342 {
343 /*
344 * Register, memory.
345 */
346 if (pVCpu->iem.s.uVexLength)
347 {
348 IEM_MC_BEGIN(4, 5);
349 IEM_MC_LOCAL(RTUINT256U, uDst);
350 IEM_MC_LOCAL(RTUINT256U, uSrc1);
351 IEM_MC_LOCAL(RTUINT256U, uSrc2);
352 IEM_MC_LOCAL(RTUINT256U, uSrc3);
353 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
354 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
355 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
356 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
357 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
358
359 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
360 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
361
362 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
363 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
364 IEM_MC_PREPARE_AVX_USAGE();
365
366 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
367 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
368 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_EFFECTIVE_VVVV(pVCpu));
369 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
370 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
371 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
372
373 IEM_MC_ADVANCE_RIP();
374 IEM_MC_END();
375 }
376 else
377 {
378 IEM_MC_BEGIN(4, 2);
379 IEM_MC_LOCAL(RTUINT128U, uSrc2);
380 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
381 IEM_MC_ARG(PRTUINT128U, puDst, 0);
382 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
383 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
384 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
385
386 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
387 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
388
389 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
390 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
391 IEM_MC_PREPARE_AVX_USAGE();
392
393 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
394 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
395 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
396 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
397 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
398 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
399
400 IEM_MC_ADVANCE_RIP();
401 IEM_MC_END();
402 }
403 }
404 return VINF_SUCCESS;
405}
406
407
408/** Opcode VEX.66.0F3A 0x4a (vex only). */
409FNIEMOP_DEF(iemOp_vblendvps_Vx_Hx_Wx_Lx)
410{
411 //IEMOP_MNEMONIC4(VEX_RVM, VBLENDVPS, vpblendvps, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
412 IEMOPBLENDOP_INIT_VARS(vblendvps);
413 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
414}
415
416
417/** Opcode VEX.66.0F3A 0x4b (vex only). */
418FNIEMOP_DEF(iemOp_vblendvpd_Vx_Hx_Wx_Lx)
419{
420 //IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVPD, blendvpd, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
421 IEMOPBLENDOP_INIT_VARS(vblendvpd);
422 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
423}
424
425
426/** Opcode VEX.66.0F3A 0x4c (vex only). */
427FNIEMOP_DEF(iemOp_vpblendvb_Vx_Hx_Wx_Lx)
428{
429 //IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVB, vpblendvb, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
430 IEMOPBLENDOP_INIT_VARS(vpblendvb);
431 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
432}
433
434
435/* Opcode VEX.66.0F3A 0x4d - invalid */
436/* Opcode VEX.66.0F3A 0x4e - invalid */
437/* Opcode VEX.66.0F3A 0x4f - invalid */
438
439
440/* Opcode VEX.66.0F3A 0x50 - invalid */
441/* Opcode VEX.66.0F3A 0x51 - invalid */
442/* Opcode VEX.66.0F3A 0x52 - invalid */
443/* Opcode VEX.66.0F3A 0x53 - invalid */
444/* Opcode VEX.66.0F3A 0x54 - invalid */
445/* Opcode VEX.66.0F3A 0x55 - invalid */
446/* Opcode VEX.66.0F3A 0x56 - invalid */
447/* Opcode VEX.66.0F3A 0x57 - invalid */
448/* Opcode VEX.66.0F3A 0x58 - invalid */
449/* Opcode VEX.66.0F3A 0x59 - invalid */
450/* Opcode VEX.66.0F3A 0x5a - invalid */
451/* Opcode VEX.66.0F3A 0x5b - invalid */
452/** Opcode VEX.66.0F3A 0x5c (AMD tables only). */
453FNIEMOP_STUB(iemOp_vfmaddsubps_Vx_Lx_Wx_Hx);
454/** Opcode VEX.66.0F3A 0x5d (AMD tables only). */
455FNIEMOP_STUB(iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx);
456/** Opcode VEX.66.0F3A 0x5e (AMD tables only). */
457FNIEMOP_STUB(iemOp_vfmsubaddps_Vx_Lx_Wx_Hx);
458/** Opcode VEX.66.0F3A 0x5f (AMD tables only). */
459FNIEMOP_STUB(iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx);
460
461
462/** Opcode VEX.66.0F3A 0x60. */
463FNIEMOP_STUB(iemOp_vpcmpestrm_Vdq_Wdq_Ib);
464/** Opcode VEX.66.0F3A 0x61, */
465FNIEMOP_STUB(iemOp_vpcmpestri_Vdq_Wdq_Ib);
466/** Opcode VEX.66.0F3A 0x62. */
467FNIEMOP_STUB(iemOp_vpcmpistrm_Vdq_Wdq_Ib);
468/** Opcode VEX.66.0F3A 0x63*/
469FNIEMOP_STUB(iemOp_vpcmpistri_Vdq_Wdq_Ib);
470/* Opcode VEX.66.0F3A 0x64 - invalid */
471/* Opcode VEX.66.0F3A 0x65 - invalid */
472/* Opcode VEX.66.0F3A 0x66 - invalid */
473/* Opcode VEX.66.0F3A 0x67 - invalid */
474/** Opcode VEX.66.0F3A 0x68 (AMD tables only). */
475FNIEMOP_STUB(iemOp_vfmaddps_Vx_Lx_Wx_Hx);
476/** Opcode VEX.66.0F3A 0x69 (AMD tables only). */
477FNIEMOP_STUB(iemOp_vfmaddpd_Vx_Lx_Wx_Hx);
478/** Opcode VEX.66.0F3A 0x6a (AMD tables only). */
479FNIEMOP_STUB(iemOp_vfmaddss_Vx_Lx_Wx_Hx);
480/** Opcode VEX.66.0F3A 0x6b (AMD tables only). */
481FNIEMOP_STUB(iemOp_vfmaddsd_Vx_Lx_Wx_Hx);
482/** Opcode VEX.66.0F3A 0x6c (AMD tables only). */
483FNIEMOP_STUB(iemOp_vfmsubps_Vx_Lx_Wx_Hx);
484/** Opcode VEX.66.0F3A 0x6d (AMD tables only). */
485FNIEMOP_STUB(iemOp_vfmsubpd_Vx_Lx_Wx_Hx);
486/** Opcode VEX.66.0F3A 0x6e (AMD tables only). */
487FNIEMOP_STUB(iemOp_vfmsubss_Vx_Lx_Wx_Hx);
488/** Opcode VEX.66.0F3A 0x6f (AMD tables only). */
489FNIEMOP_STUB(iemOp_vfmsubsd_Vx_Lx_Wx_Hx);
490
491/* Opcode VEX.66.0F3A 0x70 - invalid */
492/* Opcode VEX.66.0F3A 0x71 - invalid */
493/* Opcode VEX.66.0F3A 0x72 - invalid */
494/* Opcode VEX.66.0F3A 0x73 - invalid */
495/* Opcode VEX.66.0F3A 0x74 - invalid */
496/* Opcode VEX.66.0F3A 0x75 - invalid */
497/* Opcode VEX.66.0F3A 0x76 - invalid */
498/* Opcode VEX.66.0F3A 0x77 - invalid */
499/** Opcode VEX.66.0F3A 0x78 (AMD tables only). */
500FNIEMOP_STUB(iemOp_vfnmaddps_Vx_Lx_Wx_Hx);
501/** Opcode VEX.66.0F3A 0x79 (AMD tables only). */
502FNIEMOP_STUB(iemOp_vfnmaddpd_Vx_Lx_Wx_Hx);
503/** Opcode VEX.66.0F3A 0x7a (AMD tables only). */
504FNIEMOP_STUB(iemOp_vfnmaddss_Vx_Lx_Wx_Hx);
505/** Opcode VEX.66.0F3A 0x7b (AMD tables only). */
506FNIEMOP_STUB(iemOp_vfnmaddsd_Vx_Lx_Wx_Hx);
507/** Opcode VEX.66.0F3A 0x7c (AMD tables only). */
508FNIEMOP_STUB(iemOp_vfnmsubps_Vx_Lx_Wx_Hx);
509/** Opcode VEX.66.0F3A 0x7d (AMD tables only). */
510FNIEMOP_STUB(iemOp_vfnmsubpd_Vx_Lx_Wx_Hx);
511/** Opcode VEX.66.0F3A 0x7e (AMD tables only). */
512FNIEMOP_STUB(iemOp_vfnmsubss_Vx_Lx_Wx_Hx);
513/** Opcode VEX.66.0F3A 0x7f (AMD tables only). */
514FNIEMOP_STUB(iemOp_vfnmsubsd_Vx_Lx_Wx_Hx);
515
516/* Opcodes 0x0f 0x80 thru 0x0f 0xb0 are unused. */
517
518
519/* Opcode 0x0f 0xc0 - invalid */
520/* Opcode 0x0f 0xc1 - invalid */
521/* Opcode 0x0f 0xc2 - invalid */
522/* Opcode 0x0f 0xc3 - invalid */
523/* Opcode 0x0f 0xc4 - invalid */
524/* Opcode 0x0f 0xc5 - invalid */
525/* Opcode 0x0f 0xc6 - invalid */
526/* Opcode 0x0f 0xc7 - invalid */
527/* Opcode 0x0f 0xc8 - invalid */
528/* Opcode 0x0f 0xc9 - invalid */
529/* Opcode 0x0f 0xca - invalid */
530/* Opcode 0x0f 0xcb - invalid */
531/* Opcode 0x0f 0xcc */
532FNIEMOP_STUB(iemOp_vsha1rnds4_Vdq_Wdq_Ib);
533/* Opcode 0x0f 0xcd - invalid */
534/* Opcode 0x0f 0xce - invalid */
535/* Opcode 0x0f 0xcf - invalid */
536
537
538/* Opcode VEX.66.0F3A 0xd0 - invalid */
539/* Opcode VEX.66.0F3A 0xd1 - invalid */
540/* Opcode VEX.66.0F3A 0xd2 - invalid */
541/* Opcode VEX.66.0F3A 0xd3 - invalid */
542/* Opcode VEX.66.0F3A 0xd4 - invalid */
543/* Opcode VEX.66.0F3A 0xd5 - invalid */
544/* Opcode VEX.66.0F3A 0xd6 - invalid */
545/* Opcode VEX.66.0F3A 0xd7 - invalid */
546/* Opcode VEX.66.0F3A 0xd8 - invalid */
547/* Opcode VEX.66.0F3A 0xd9 - invalid */
548/* Opcode VEX.66.0F3A 0xda - invalid */
549/* Opcode VEX.66.0F3A 0xdb - invalid */
550/* Opcode VEX.66.0F3A 0xdc - invalid */
551/* Opcode VEX.66.0F3A 0xdd - invalid */
552/* Opcode VEX.66.0F3A 0xde - invalid */
553/* Opcode VEX.66.0F3A 0xdf - (aeskeygenassist). */
554FNIEMOP_STUB(iemOp_vaeskeygen_Vdq_Wdq_Ib);
555
556
557/** Opcode VEX.F2.0F3A (vex only) */
558FNIEMOP_DEF(iemOp_rorx_Gy_Ey_Ib)
559{
560 IEMOP_MNEMONIC3(VEX_RMI, RORX, rorx, Gy, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO);
561 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
562 return iemOp_InvalidNeedRMImm8(pVCpu);
563 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
564 if (IEM_IS_MODRM_REG_MODE(bRm))
565 {
566 /*
567 * Register, register.
568 */
569 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
570 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
571 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
572 {
573 IEM_MC_BEGIN(3, 0);
574 IEM_MC_ARG(uint64_t *, pDst, 0);
575 IEM_MC_ARG(uint64_t, uSrc1, 1);
576 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
577 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
578 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
579 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
580 IEM_MC_ADVANCE_RIP();
581 IEM_MC_END();
582 }
583 else
584 {
585 IEM_MC_BEGIN(3, 0);
586 IEM_MC_ARG(uint32_t *, pDst, 0);
587 IEM_MC_ARG(uint32_t, uSrc1, 1);
588 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
589 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
590 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
591 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
592 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
593 IEM_MC_ADVANCE_RIP();
594 IEM_MC_END();
595 }
596 }
597 else
598 {
599 /*
600 * Register, memory.
601 */
602 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
603 {
604 IEM_MC_BEGIN(3, 1);
605 IEM_MC_ARG(uint64_t *, pDst, 0);
606 IEM_MC_ARG(uint64_t, uSrc1, 1);
607 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
608 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
609 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
610 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
611 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
612 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
613 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
614 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
615 IEM_MC_ADVANCE_RIP();
616 IEM_MC_END();
617 }
618 else
619 {
620 IEM_MC_BEGIN(3, 1);
621 IEM_MC_ARG(uint32_t *, pDst, 0);
622 IEM_MC_ARG(uint32_t, uSrc1, 1);
623 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
624 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
625 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
626 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
627 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
628 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
629 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
630 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
631 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
632 IEM_MC_ADVANCE_RIP();
633 IEM_MC_END();
634 }
635 }
636 return VINF_SUCCESS;
637}
638
639
640/**
641 * VEX opcode map \#3.
642 *
643 * @sa g_apfnThreeByte0f3a
644 */
645IEM_STATIC const PFNIEMOP g_apfnVexMap3[] =
646{
647 /* no prefix, 066h prefix f3h prefix, f2h prefix */
648 /* 0x00 */ iemOp_InvalidNeedRMImm8, iemOp_vpermq_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
649 /* 0x01 */ iemOp_InvalidNeedRMImm8, iemOp_vpermqd_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
650 /* 0x02 */ iemOp_InvalidNeedRMImm8, iemOp_vpblendd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
651 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
652 /* 0x04 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
653 /* 0x05 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
654 /* 0x06 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
655 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
656 /* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_vroundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
657 /* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_vroundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
658 /* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_vroundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
659 /* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_vroundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
660 /* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_vblendps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
661 /* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_vblendpd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
662 /* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_vblendw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
663 /* 0x0f */ iemOp_InvalidNeedRMImm8, iemOp_vpalignr_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
664
665 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
666 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
667 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
668 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
669 /* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
670 /* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
671 /* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
672 /* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_vextractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
673 /* 0x18 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
674 /* 0x19 */ iemOp_InvalidNeedRMImm8, iemOp_vextractf128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
675 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
676 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
677 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
678 /* 0x1d */ iemOp_InvalidNeedRMImm8, iemOp_vcvtps2ph_Wx_Vx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
679 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
680 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
681
682 /* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
683 /* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
684 /* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
685 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
686 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
687 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
688 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
689 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
690 /* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
691 /* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
692 /* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
693 /* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
694 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
695 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
696 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
697 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
698
699 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
700 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
701 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
702 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
703 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
704 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
705 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
706 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
707 /* 0x38 */ iemOp_InvalidNeedRMImm8, iemOp_vinserti128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
708 /* 0x39 */ iemOp_InvalidNeedRMImm8, iemOp_vextracti128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
709 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
710 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
711 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
712 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
713 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
714 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
715
716 /* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_vdpps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
717 /* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_vdppd_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
718 /* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_vmpsadbw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
719 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
720 /* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
721 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
722 /* 0x46 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
723 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
724 /* 0x48 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
725 /* 0x49 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
726 /* 0x4a */ iemOp_InvalidNeedRMImm8, iemOp_vblendvps_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
727 /* 0x4b */ iemOp_InvalidNeedRMImm8, iemOp_vblendvpd_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
728 /* 0x4c */ iemOp_InvalidNeedRMImm8, iemOp_vpblendvb_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
729 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
730 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
731 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
732
733 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
734 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
735 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
736 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
737 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
738 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
739 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
740 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
741 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
742 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
743 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
744 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
745 /* 0x5c */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
746 /* 0x5d */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
747 /* 0x5e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
748 /* 0x5f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
749
750 /* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
751 /* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
752 /* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
753 /* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
754 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
755 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
756 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
757 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
758 /* 0x68 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
759 /* 0x69 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
760 /* 0x6a */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
761 /* 0x6b */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
762 /* 0x6c */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
763 /* 0x6d */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
764 /* 0x6e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
765 /* 0x6f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
766
767 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
768 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
769 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
770 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
771 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
772 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
773 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
774 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
775 /* 0x78 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
776 /* 0x79 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
777 /* 0x7a */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
778 /* 0x7b */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
779 /* 0x7c */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
780 /* 0x7d */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
781 /* 0x7e */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
782 /* 0x7f */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
783
784 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
785 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
786 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
787 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
788 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
789 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
790 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
791 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
792 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
793 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
794 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
795 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
796 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
797 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
798 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
799 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
800
801 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
802 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
803 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
804 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
805 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
806 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
807 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
808 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
809 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
810 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
811 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
812 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
813 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
814 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
815 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
816 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
817
818 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
819 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
820 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
821 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
822 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
823 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
824 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
825 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
826 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
827 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
828 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
829 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
830 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
831 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
832 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
833 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
834
835 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
836 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
837 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
838 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
839 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
840 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
841 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
842 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
843 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
844 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
845 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
846 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
847 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
848 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
849 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
850 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
851
852 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
853 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
854 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
855 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
856 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
857 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
858 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
859 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
860 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
861 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
862 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
863 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
864 /* 0xcc */ iemOp_vsha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
865 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
866 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
867 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
868
869 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
870 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
871 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
872 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
873 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
874 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
875 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
876 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
877 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
878 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
879 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
880 /* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
881 /* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
882 /* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
883 /* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
884 /* 0xdf */ iemOp_vaeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
885
886 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
887 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
888 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
889 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
890 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
891 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
892 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
893 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
894 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
895 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
896 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
897 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
898 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
899 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
900 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
901 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
902
903 /* 0xf0 */ iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_rorx_Gy_Ey_Ib,
904 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
905 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
906 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
907 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
908 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
909 /* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
910 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
911 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
912 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
913 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
914 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
915 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
916 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
917 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
918 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
919};
920AssertCompile(RT_ELEMENTS(g_apfnVexMap3) == 1024);
921
922/** @} */
923
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