VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap3.cpp.h@ 96454

Last change on this file since 96454 was 96454, checked in by vboxsync, 3 years ago

VMM/IEM: Implement [v]pblendvb/[v]blendvps/[v]blendvpd instructions, bugref:9898
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1/* $Id: IEMAllInstructionsVexMap3.cpp.h 96454 2022-08-24 12:53:47Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4 *
5 * @remarks IEMAllInstructionsThree0f3a.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 3
33 * @{
34 */
35
36/** Opcode VEX.66.0F3A 0x00. */
37FNIEMOP_STUB(iemOp_vpermq_Vqq_Wqq_Ib);
38/** Opcode VEX.66.0F3A 0x01. */
39FNIEMOP_STUB(iemOp_vpermqd_Vqq_Wqq_Ib);
40/** Opcode VEX.66.0F3A 0x02. */
41FNIEMOP_STUB(iemOp_vpblendd_Vx_Wx_Ib);
42/* Opcode VEX.66.0F3A 0x03 - invalid */
43/** Opcode VEX.66.0F3A 0x04. */
44FNIEMOP_STUB(iemOp_vpermilps_Vx_Wx_Ib);
45/** Opcode VEX.66.0F3A 0x05. */
46FNIEMOP_STUB(iemOp_vpermilpd_Vx_Wx_Ib);
47/** Opcode VEX.66.0F3A 0x06 (vex only) */
48FNIEMOP_STUB(iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib);
49/* Opcode VEX.66.0F3A 0x07 - invalid */
50/** Opcode VEX.66.0F3A 0x08. */
51FNIEMOP_STUB(iemOp_vroundps_Vx_Wx_Ib);
52/** Opcode VEX.66.0F3A 0x09. */
53FNIEMOP_STUB(iemOp_vroundpd_Vx_Wx_Ib);
54/** Opcode VEX.66.0F3A 0x0a. */
55FNIEMOP_STUB(iemOp_vroundss_Vss_Wss_Ib);
56/** Opcode VEX.66.0F3A 0x0b. */
57FNIEMOP_STUB(iemOp_vroundsd_Vsd_Wsd_Ib);
58/** Opcode VEX.66.0F3A 0x0c. */
59FNIEMOP_STUB(iemOp_vblendps_Vx_Hx_Wx_Ib);
60/** Opcode VEX.66.0F3A 0x0d. */
61FNIEMOP_STUB(iemOp_vblendpd_Vx_Hx_Wx_Ib);
62/** Opcode VEX.66.0F3A 0x0e. */
63FNIEMOP_STUB(iemOp_vblendw_Vx_Hx_Wx_Ib);
64/** Opcode VEX.0F3A 0x0f - invalid. */
65/** Opcode VEX.66.0F3A 0x0f. */
66FNIEMOP_STUB(iemOp_vpalignr_Vx_Hx_Wx_Ib);
67
68
69/* Opcode VEX.66.0F3A 0x10 - invalid */
70/* Opcode VEX.66.0F3A 0x11 - invalid */
71/* Opcode VEX.66.0F3A 0x12 - invalid */
72/* Opcode VEX.66.0F3A 0x13 - invalid */
73/** Opcode VEX.66.0F3A 0x14. */
74FNIEMOP_STUB(iemOp_vpextrb_RdMb_Vdq_Ib);
75/** Opcode VEX.66.0F3A 0x15. */
76FNIEMOP_STUB(iemOp_vpextrw_RdMw_Vdq_Ib);
77/** Opcode VEX.66.0F3A 0x16. */
78FNIEMOP_STUB(iemOp_vpextrd_q_RdMw_Vdq_Ib);
79/** Opcode VEX.66.0F3A 0x17. */
80FNIEMOP_STUB(iemOp_vextractps_Ed_Vdq_Ib);
81/** Opcode VEX.66.0F3A 0x18 (vex only). */
82FNIEMOP_STUB(iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib);
83/** Opcode VEX.66.0F3A 0x19 (vex only). */
84FNIEMOP_STUB(iemOp_vextractf128_Wdq_Vqq_Ib);
85/* Opcode VEX.66.0F3A 0x1a - invalid */
86/* Opcode VEX.66.0F3A 0x1b - invalid */
87/* Opcode VEX.66.0F3A 0x1c - invalid */
88/** Opcode VEX.66.0F3A 0x1d (vex only). */
89FNIEMOP_STUB(iemOp_vcvtps2ph_Wx_Vx_Ib);
90/* Opcode VEX.66.0F3A 0x1e - invalid */
91/* Opcode VEX.66.0F3A 0x1f - invalid */
92
93
94/** Opcode VEX.66.0F3A 0x20. */
95FNIEMOP_STUB(iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib);
96/** Opcode VEX.66.0F3A 0x21, */
97FNIEMOP_STUB(iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib);
98/** Opcode VEX.66.0F3A 0x22. */
99FNIEMOP_STUB(iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib);
100/* Opcode VEX.66.0F3A 0x23 - invalid */
101/* Opcode VEX.66.0F3A 0x24 - invalid */
102/* Opcode VEX.66.0F3A 0x25 - invalid */
103/* Opcode VEX.66.0F3A 0x26 - invalid */
104/* Opcode VEX.66.0F3A 0x27 - invalid */
105/* Opcode VEX.66.0F3A 0x28 - invalid */
106/* Opcode VEX.66.0F3A 0x29 - invalid */
107/* Opcode VEX.66.0F3A 0x2a - invalid */
108/* Opcode VEX.66.0F3A 0x2b - invalid */
109/* Opcode VEX.66.0F3A 0x2c - invalid */
110/* Opcode VEX.66.0F3A 0x2d - invalid */
111/* Opcode VEX.66.0F3A 0x2e - invalid */
112/* Opcode VEX.66.0F3A 0x2f - invalid */
113
114
115/* Opcode VEX.66.0F3A 0x30 - invalid */
116/* Opcode VEX.66.0F3A 0x31 - invalid */
117/* Opcode VEX.66.0F3A 0x32 - invalid */
118/* Opcode VEX.66.0F3A 0x33 - invalid */
119/* Opcode VEX.66.0F3A 0x34 - invalid */
120/* Opcode VEX.66.0F3A 0x35 - invalid */
121/* Opcode VEX.66.0F3A 0x36 - invalid */
122/* Opcode VEX.66.0F3A 0x37 - invalid */
123/** Opcode VEX.66.0F3A 0x38 (vex only). */
124FNIEMOP_STUB(iemOp_vinserti128_Vqq_Hqq_Wqq_Ib);
125/** Opcode VEX.66.0F3A 0x39 (vex only). */
126FNIEMOP_STUB(iemOp_vextracti128_Wdq_Vqq_Ib);
127/* Opcode VEX.66.0F3A 0x3a - invalid */
128/* Opcode VEX.66.0F3A 0x3b - invalid */
129/* Opcode VEX.66.0F3A 0x3c - invalid */
130/* Opcode VEX.66.0F3A 0x3d - invalid */
131/* Opcode VEX.66.0F3A 0x3e - invalid */
132/* Opcode VEX.66.0F3A 0x3f - invalid */
133
134
135/** Opcode VEX.66.0F3A 0x40. */
136FNIEMOP_STUB(iemOp_vdpps_Vx_Hx_Wx_Ib);
137/** Opcode VEX.66.0F3A 0x41, */
138FNIEMOP_STUB(iemOp_vdppd_Vdq_Hdq_Wdq_Ib);
139/** Opcode VEX.66.0F3A 0x42. */
140FNIEMOP_STUB(iemOp_vmpsadbw_Vx_Hx_Wx_Ib);
141/* Opcode VEX.66.0F3A 0x43 - invalid */
142/** Opcode VEX.66.0F3A 0x44. */
143FNIEMOP_STUB(iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib);
144/* Opcode VEX.66.0F3A 0x45 - invalid */
145/** Opcode VEX.66.0F3A 0x46 (vex only) */
146FNIEMOP_STUB(iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib);
147/* Opcode VEX.66.0F3A 0x47 - invalid */
148/** Opcode VEX.66.0F3A 0x48 (AMD tables only). */
149FNIEMOP_STUB(iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx);
150/** Opcode VEX.66.0F3A 0x49 (AMD tables only). */
151FNIEMOP_STUB(iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx);
152
153
154/**
155 * Common worker for AVX2 instructions on the forms:
156 * - vpxxx xmm0, xmm1, xmm2/mem128, xmm4
157 * - vpxxx ymm0, ymm1, ymm2/mem256, ymm4
158 *
159 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
160 */
161FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
162{
163 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
164 if (IEM_IS_MODRM_REG_MODE(bRm))
165 {
166 /*
167 * Register, register.
168 */
169 if (pVCpu->iem.s.uVexLength)
170 {
171 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
172
173 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
174 IEM_MC_BEGIN(4, 4);
175 IEM_MC_LOCAL(RTUINT256U, uDst);
176 IEM_MC_LOCAL(RTUINT256U, uSrc1);
177 IEM_MC_LOCAL(RTUINT256U, uSrc2);
178 IEM_MC_LOCAL(RTUINT256U, uSrc3);
179 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
180 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
181 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
182 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
183 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
184 IEM_MC_PREPARE_AVX_USAGE();
185 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
186 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
187 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
188 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
189 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
190 IEM_MC_ADVANCE_RIP();
191 IEM_MC_END();
192 }
193 else
194 {
195 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
196
197 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
198 IEM_MC_BEGIN(4, 0);
199 IEM_MC_ARG(PRTUINT128U, puDst, 0);
200 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
201 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
202 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
203 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
204 IEM_MC_PREPARE_AVX_USAGE();
205 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
206 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
207 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
208 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
209 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
210 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
211 IEM_MC_ADVANCE_RIP();
212 IEM_MC_END();
213 }
214 }
215 else
216 {
217 /*
218 * Register, memory.
219 */
220 if (pVCpu->iem.s.uVexLength)
221 {
222 IEM_MC_BEGIN(4, 5);
223 IEM_MC_LOCAL(RTUINT256U, uDst);
224 IEM_MC_LOCAL(RTUINT256U, uSrc1);
225 IEM_MC_LOCAL(RTUINT256U, uSrc2);
226 IEM_MC_LOCAL(RTUINT256U, uSrc3);
227 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
228 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
229 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
230 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
231 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
232
233 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
234 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
235
236 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
237 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
238 IEM_MC_PREPARE_AVX_USAGE();
239
240 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
241 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
242 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_EFFECTIVE_VVVV(pVCpu));
243 IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
244 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
245 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
246
247 IEM_MC_ADVANCE_RIP();
248 IEM_MC_END();
249 }
250 else
251 {
252 IEM_MC_BEGIN(4, 2);
253 IEM_MC_LOCAL(RTUINT128U, uSrc2);
254 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
255 IEM_MC_ARG(PRTUINT128U, puDst, 0);
256 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
257 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
258 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
259
260 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
261 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
262
263 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
264 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
265 IEM_MC_PREPARE_AVX_USAGE();
266
267 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
268 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
269 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
270 IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
271 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
272 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
273
274 IEM_MC_ADVANCE_RIP();
275 IEM_MC_END();
276 }
277 }
278 return VINF_SUCCESS;
279}
280
281
282/** Opcode VEX.66.0F3A 0x4a (vex only). */
283FNIEMOP_DEF(iemOp_vblendvps_Vx_Hx_Wx_Lx)
284{
285 //IEMOP_MNEMONIC4(VEX_RVM, VBLENDVPS, vpblendvps, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
286 IEMOPBLENDOP_INIT_VARS(vblendvps);
287 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
288}
289
290
291/** Opcode VEX.66.0F3A 0x4b (vex only). */
292FNIEMOP_DEF(iemOp_vblendvpd_Vx_Hx_Wx_Lx)
293{
294 //IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVPD, blendvpd, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
295 IEMOPBLENDOP_INIT_VARS(vblendvpd);
296 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
297}
298
299
300/** Opcode VEX.66.0F3A 0x4c (vex only). */
301FNIEMOP_DEF(iemOp_vpblendvb_Vx_Hx_Wx_Lx)
302{
303 //IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVB, vpblendvb, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
304 IEMOPBLENDOP_INIT_VARS(vpblendvb);
305 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
306}
307
308
309/* Opcode VEX.66.0F3A 0x4d - invalid */
310/* Opcode VEX.66.0F3A 0x4e - invalid */
311/* Opcode VEX.66.0F3A 0x4f - invalid */
312
313
314/* Opcode VEX.66.0F3A 0x50 - invalid */
315/* Opcode VEX.66.0F3A 0x51 - invalid */
316/* Opcode VEX.66.0F3A 0x52 - invalid */
317/* Opcode VEX.66.0F3A 0x53 - invalid */
318/* Opcode VEX.66.0F3A 0x54 - invalid */
319/* Opcode VEX.66.0F3A 0x55 - invalid */
320/* Opcode VEX.66.0F3A 0x56 - invalid */
321/* Opcode VEX.66.0F3A 0x57 - invalid */
322/* Opcode VEX.66.0F3A 0x58 - invalid */
323/* Opcode VEX.66.0F3A 0x59 - invalid */
324/* Opcode VEX.66.0F3A 0x5a - invalid */
325/* Opcode VEX.66.0F3A 0x5b - invalid */
326/** Opcode VEX.66.0F3A 0x5c (AMD tables only). */
327FNIEMOP_STUB(iemOp_vfmaddsubps_Vx_Lx_Wx_Hx);
328/** Opcode VEX.66.0F3A 0x5d (AMD tables only). */
329FNIEMOP_STUB(iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx);
330/** Opcode VEX.66.0F3A 0x5e (AMD tables only). */
331FNIEMOP_STUB(iemOp_vfmsubaddps_Vx_Lx_Wx_Hx);
332/** Opcode VEX.66.0F3A 0x5f (AMD tables only). */
333FNIEMOP_STUB(iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx);
334
335
336/** Opcode VEX.66.0F3A 0x60. */
337FNIEMOP_STUB(iemOp_vpcmpestrm_Vdq_Wdq_Ib);
338/** Opcode VEX.66.0F3A 0x61, */
339FNIEMOP_STUB(iemOp_vpcmpestri_Vdq_Wdq_Ib);
340/** Opcode VEX.66.0F3A 0x62. */
341FNIEMOP_STUB(iemOp_vpcmpistrm_Vdq_Wdq_Ib);
342/** Opcode VEX.66.0F3A 0x63*/
343FNIEMOP_STUB(iemOp_vpcmpistri_Vdq_Wdq_Ib);
344/* Opcode VEX.66.0F3A 0x64 - invalid */
345/* Opcode VEX.66.0F3A 0x65 - invalid */
346/* Opcode VEX.66.0F3A 0x66 - invalid */
347/* Opcode VEX.66.0F3A 0x67 - invalid */
348/** Opcode VEX.66.0F3A 0x68 (AMD tables only). */
349FNIEMOP_STUB(iemOp_vfmaddps_Vx_Lx_Wx_Hx);
350/** Opcode VEX.66.0F3A 0x69 (AMD tables only). */
351FNIEMOP_STUB(iemOp_vfmaddpd_Vx_Lx_Wx_Hx);
352/** Opcode VEX.66.0F3A 0x6a (AMD tables only). */
353FNIEMOP_STUB(iemOp_vfmaddss_Vx_Lx_Wx_Hx);
354/** Opcode VEX.66.0F3A 0x6b (AMD tables only). */
355FNIEMOP_STUB(iemOp_vfmaddsd_Vx_Lx_Wx_Hx);
356/** Opcode VEX.66.0F3A 0x6c (AMD tables only). */
357FNIEMOP_STUB(iemOp_vfmsubps_Vx_Lx_Wx_Hx);
358/** Opcode VEX.66.0F3A 0x6d (AMD tables only). */
359FNIEMOP_STUB(iemOp_vfmsubpd_Vx_Lx_Wx_Hx);
360/** Opcode VEX.66.0F3A 0x6e (AMD tables only). */
361FNIEMOP_STUB(iemOp_vfmsubss_Vx_Lx_Wx_Hx);
362/** Opcode VEX.66.0F3A 0x6f (AMD tables only). */
363FNIEMOP_STUB(iemOp_vfmsubsd_Vx_Lx_Wx_Hx);
364
365/* Opcode VEX.66.0F3A 0x70 - invalid */
366/* Opcode VEX.66.0F3A 0x71 - invalid */
367/* Opcode VEX.66.0F3A 0x72 - invalid */
368/* Opcode VEX.66.0F3A 0x73 - invalid */
369/* Opcode VEX.66.0F3A 0x74 - invalid */
370/* Opcode VEX.66.0F3A 0x75 - invalid */
371/* Opcode VEX.66.0F3A 0x76 - invalid */
372/* Opcode VEX.66.0F3A 0x77 - invalid */
373/** Opcode VEX.66.0F3A 0x78 (AMD tables only). */
374FNIEMOP_STUB(iemOp_vfnmaddps_Vx_Lx_Wx_Hx);
375/** Opcode VEX.66.0F3A 0x79 (AMD tables only). */
376FNIEMOP_STUB(iemOp_vfnmaddpd_Vx_Lx_Wx_Hx);
377/** Opcode VEX.66.0F3A 0x7a (AMD tables only). */
378FNIEMOP_STUB(iemOp_vfnmaddss_Vx_Lx_Wx_Hx);
379/** Opcode VEX.66.0F3A 0x7b (AMD tables only). */
380FNIEMOP_STUB(iemOp_vfnmaddsd_Vx_Lx_Wx_Hx);
381/** Opcode VEX.66.0F3A 0x7c (AMD tables only). */
382FNIEMOP_STUB(iemOp_vfnmsubps_Vx_Lx_Wx_Hx);
383/** Opcode VEX.66.0F3A 0x7d (AMD tables only). */
384FNIEMOP_STUB(iemOp_vfnmsubpd_Vx_Lx_Wx_Hx);
385/** Opcode VEX.66.0F3A 0x7e (AMD tables only). */
386FNIEMOP_STUB(iemOp_vfnmsubss_Vx_Lx_Wx_Hx);
387/** Opcode VEX.66.0F3A 0x7f (AMD tables only). */
388FNIEMOP_STUB(iemOp_vfnmsubsd_Vx_Lx_Wx_Hx);
389
390/* Opcodes 0x0f 0x80 thru 0x0f 0xb0 are unused. */
391
392
393/* Opcode 0x0f 0xc0 - invalid */
394/* Opcode 0x0f 0xc1 - invalid */
395/* Opcode 0x0f 0xc2 - invalid */
396/* Opcode 0x0f 0xc3 - invalid */
397/* Opcode 0x0f 0xc4 - invalid */
398/* Opcode 0x0f 0xc5 - invalid */
399/* Opcode 0x0f 0xc6 - invalid */
400/* Opcode 0x0f 0xc7 - invalid */
401/* Opcode 0x0f 0xc8 - invalid */
402/* Opcode 0x0f 0xc9 - invalid */
403/* Opcode 0x0f 0xca - invalid */
404/* Opcode 0x0f 0xcb - invalid */
405/* Opcode 0x0f 0xcc */
406FNIEMOP_STUB(iemOp_vsha1rnds4_Vdq_Wdq_Ib);
407/* Opcode 0x0f 0xcd - invalid */
408/* Opcode 0x0f 0xce - invalid */
409/* Opcode 0x0f 0xcf - invalid */
410
411
412/* Opcode VEX.66.0F3A 0xd0 - invalid */
413/* Opcode VEX.66.0F3A 0xd1 - invalid */
414/* Opcode VEX.66.0F3A 0xd2 - invalid */
415/* Opcode VEX.66.0F3A 0xd3 - invalid */
416/* Opcode VEX.66.0F3A 0xd4 - invalid */
417/* Opcode VEX.66.0F3A 0xd5 - invalid */
418/* Opcode VEX.66.0F3A 0xd6 - invalid */
419/* Opcode VEX.66.0F3A 0xd7 - invalid */
420/* Opcode VEX.66.0F3A 0xd8 - invalid */
421/* Opcode VEX.66.0F3A 0xd9 - invalid */
422/* Opcode VEX.66.0F3A 0xda - invalid */
423/* Opcode VEX.66.0F3A 0xdb - invalid */
424/* Opcode VEX.66.0F3A 0xdc - invalid */
425/* Opcode VEX.66.0F3A 0xdd - invalid */
426/* Opcode VEX.66.0F3A 0xde - invalid */
427/* Opcode VEX.66.0F3A 0xdf - (aeskeygenassist). */
428FNIEMOP_STUB(iemOp_vaeskeygen_Vdq_Wdq_Ib);
429
430
431/** Opcode VEX.F2.0F3A (vex only) */
432FNIEMOP_DEF(iemOp_rorx_Gy_Ey_Ib)
433{
434 IEMOP_MNEMONIC3(VEX_RMI, RORX, rorx, Gy, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO);
435 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
436 return iemOp_InvalidNeedRMImm8(pVCpu);
437 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
438 if (IEM_IS_MODRM_REG_MODE(bRm))
439 {
440 /*
441 * Register, register.
442 */
443 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
444 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
445 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
446 {
447 IEM_MC_BEGIN(3, 0);
448 IEM_MC_ARG(uint64_t *, pDst, 0);
449 IEM_MC_ARG(uint64_t, uSrc1, 1);
450 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
451 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
452 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
453 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
454 IEM_MC_ADVANCE_RIP();
455 IEM_MC_END();
456 }
457 else
458 {
459 IEM_MC_BEGIN(3, 0);
460 IEM_MC_ARG(uint32_t *, pDst, 0);
461 IEM_MC_ARG(uint32_t, uSrc1, 1);
462 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
463 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
464 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
465 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
466 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
467 IEM_MC_ADVANCE_RIP();
468 IEM_MC_END();
469 }
470 }
471 else
472 {
473 /*
474 * Register, memory.
475 */
476 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
477 {
478 IEM_MC_BEGIN(3, 1);
479 IEM_MC_ARG(uint64_t *, pDst, 0);
480 IEM_MC_ARG(uint64_t, uSrc1, 1);
481 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
482 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
483 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
484 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
485 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
486 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
487 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
488 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
489 IEM_MC_ADVANCE_RIP();
490 IEM_MC_END();
491 }
492 else
493 {
494 IEM_MC_BEGIN(3, 1);
495 IEM_MC_ARG(uint32_t *, pDst, 0);
496 IEM_MC_ARG(uint32_t, uSrc1, 1);
497 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
498 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
499 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
500 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
501 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
502 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
503 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
504 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
505 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
506 IEM_MC_ADVANCE_RIP();
507 IEM_MC_END();
508 }
509 }
510 return VINF_SUCCESS;
511}
512
513
514/**
515 * VEX opcode map \#3.
516 *
517 * @sa g_apfnThreeByte0f3a
518 */
519IEM_STATIC const PFNIEMOP g_apfnVexMap3[] =
520{
521 /* no prefix, 066h prefix f3h prefix, f2h prefix */
522 /* 0x00 */ iemOp_InvalidNeedRMImm8, iemOp_vpermq_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
523 /* 0x01 */ iemOp_InvalidNeedRMImm8, iemOp_vpermqd_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
524 /* 0x02 */ iemOp_InvalidNeedRMImm8, iemOp_vpblendd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
525 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
526 /* 0x04 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
527 /* 0x05 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
528 /* 0x06 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
529 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
530 /* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_vroundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
531 /* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_vroundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
532 /* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_vroundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
533 /* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_vroundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
534 /* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_vblendps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
535 /* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_vblendpd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
536 /* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_vblendw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
537 /* 0x0f */ iemOp_InvalidNeedRMImm8, iemOp_vpalignr_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
538
539 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
540 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
541 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
542 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
543 /* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
544 /* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
545 /* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
546 /* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_vextractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
547 /* 0x18 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
548 /* 0x19 */ iemOp_InvalidNeedRMImm8, iemOp_vextractf128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
549 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
550 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
551 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
552 /* 0x1d */ iemOp_InvalidNeedRMImm8, iemOp_vcvtps2ph_Wx_Vx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
553 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
554 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
555
556 /* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
557 /* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
558 /* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
559 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
560 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
561 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
562 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
563 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
564 /* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
565 /* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
566 /* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
567 /* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
568 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
569 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
570 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
571 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
572
573 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
574 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
575 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
576 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
577 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
578 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
579 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
580 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
581 /* 0x38 */ iemOp_InvalidNeedRMImm8, iemOp_vinserti128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
582 /* 0x39 */ iemOp_InvalidNeedRMImm8, iemOp_vextracti128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
583 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
584 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
585 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
586 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
587 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
588 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
589
590 /* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_vdpps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
591 /* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_vdppd_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
592 /* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_vmpsadbw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
593 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
594 /* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
595 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
596 /* 0x46 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
597 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
598 /* 0x48 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
599 /* 0x49 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
600 /* 0x4a */ iemOp_InvalidNeedRMImm8, iemOp_vblendvps_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
601 /* 0x4b */ iemOp_InvalidNeedRMImm8, iemOp_vblendvpd_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
602 /* 0x4c */ iemOp_InvalidNeedRMImm8, iemOp_vpblendvb_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
603 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
604 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
605 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
606
607 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
608 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
609 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
610 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
611 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
612 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
613 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
614 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
615 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
616 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
617 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
618 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
619 /* 0x5c */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
620 /* 0x5d */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
621 /* 0x5e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
622 /* 0x5f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
623
624 /* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
625 /* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
626 /* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
627 /* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
628 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
629 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
630 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
631 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
632 /* 0x68 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
633 /* 0x69 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
634 /* 0x6a */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
635 /* 0x6b */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
636 /* 0x6c */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
637 /* 0x6d */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
638 /* 0x6e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
639 /* 0x6f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
640
641 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
642 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
643 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
644 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
645 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
646 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
647 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
648 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
649 /* 0x78 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
650 /* 0x79 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
651 /* 0x7a */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
652 /* 0x7b */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
653 /* 0x7c */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
654 /* 0x7d */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
655 /* 0x7e */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
656 /* 0x7f */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
657
658 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
659 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
660 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
661 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
662 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
663 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
664 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
665 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
666 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
667 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
668 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
669 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
670 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
671 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
672 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
673 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
674
675 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
676 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
677 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
678 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
679 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
680 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
681 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
682 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
683 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
684 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
685 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
686 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
687 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
688 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
689 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
690 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
691
692 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
693 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
694 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
695 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
696 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
697 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
698 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
699 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
700 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
701 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
702 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
703 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
704 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
705 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
706 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
707 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
708
709 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
710 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
711 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
712 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
713 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
714 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
715 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
716 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
717 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
718 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
719 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
720 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
721 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
722 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
723 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
724 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
725
726 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
727 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
728 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
729 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
730 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
731 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
732 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
733 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
734 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
735 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
736 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
737 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
738 /* 0xcc */ iemOp_vsha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
739 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
740 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
741 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
742
743 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
744 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
745 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
746 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
747 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
748 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
749 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
750 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
751 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
752 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
753 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
754 /* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
755 /* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
756 /* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
757 /* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
758 /* 0xdf */ iemOp_vaeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
759
760 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
761 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
762 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
763 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
764 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
765 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
766 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
767 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
768 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
769 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
770 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
771 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
772 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
773 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
774 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
775 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
776
777 /* 0xf0 */ iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_rorx_Gy_Ey_Ib,
778 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
779 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
780 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
781 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
782 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
783 /* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
784 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
785 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
786 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
787 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
788 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
789 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
790 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
791 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
792 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
793};
794AssertCompile(RT_ELEMENTS(g_apfnVexMap3) == 1024);
795
796/** @} */
797
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