VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h@ 96104

Last change on this file since 96104 was 96099, checked in by vboxsync, 3 years ago

VMM/IEM: Implement [v]pmuldq instructions, bugref:9898
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1/* $Id: IEMAllInstructionsVexMap2.cpp.h 96099 2022-08-07 19:22:43Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsThree0f38.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2022 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.virtualbox.org. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 */
20
21
22/** @name VEX Opcode Map 2
23 * @{
24 */
25
26/* Opcode VEX.0F38 0x00 - invalid. */
27
28
29/** Opcode VEX.66.0F38 0x00. */
30FNIEMOP_DEF(iemOp_vpshufb_Vx_Hx_Wx)
31{
32 IEMOP_MNEMONIC3(VEX_RVM, VPSHUFB, vpshufb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
33 IEMOPMEDIAF3_INIT_VARS(vpshufb);
34 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
35}
36
37
38/* Opcode VEX.0F38 0x01 - invalid. */
39
40
41/** Opcode VEX.66.0F38 0x01. */
42FNIEMOP_DEF(iemOp_vphaddw_Vx_Hx_Wx)
43{
44 IEMOP_MNEMONIC3(VEX_RVM, VPHADDW, vphaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
45 IEMOPMEDIAOPTF3_INIT_VARS(vphaddw);
46 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
47}
48
49
50/* Opcode VEX.0F38 0x02 - invalid. */
51
52
53/** Opcode VEX.66.0F38 0x02. */
54FNIEMOP_DEF(iemOp_vphaddd_Vx_Hx_Wx)
55{
56 IEMOP_MNEMONIC3(VEX_RVM, VPHADDD, vphaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
57 IEMOPMEDIAOPTF3_INIT_VARS(vphaddd);
58 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
59}
60
61
62/* Opcode VEX.0F38 0x03 - invalid. */
63
64
65/** Opcode VEX.66.0F38 0x03. */
66FNIEMOP_DEF(iemOp_vphaddsw_Vx_Hx_Wx)
67{
68 IEMOP_MNEMONIC3(VEX_RVM, VPHADDSW, vphaddsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
69 IEMOPMEDIAOPTF3_INIT_VARS(vphaddsw);
70 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
71}
72
73
74/* Opcode VEX.0F38 0x04 - invalid. */
75
76
77/** Opcode VEX.66.0F38 0x04. */
78FNIEMOP_DEF(iemOp_vpmaddubsw_Vx_Hx_Wx)
79{
80 IEMOP_MNEMONIC3(VEX_RVM, VPMADDUBSW, vpmaddubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
81 IEMOPMEDIAOPTF3_INIT_VARS(vpmaddubsw);
82 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
83}
84
85
86/* Opcode VEX.0F38 0x05 - invalid. */
87
88
89/** Opcode VEX.66.0F38 0x05. */
90FNIEMOP_DEF(iemOp_vphsubw_Vx_Hx_Wx)
91{
92 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBW, vphsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
93 IEMOPMEDIAOPTF3_INIT_VARS(vphsubw);
94 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
95}
96
97
98/* Opcode VEX.0F38 0x06 - invalid. */
99
100
101/** Opcode VEX.66.0F38 0x06. */
102FNIEMOP_DEF(iemOp_vphsubd_Vx_Hx_Wx)
103{
104 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBD, vphsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
105 IEMOPMEDIAOPTF3_INIT_VARS(vphsubd);
106 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
107}
108
109
110/* Opcode VEX.0F38 0x07 - invalid. */
111
112
113/** Opcode VEX.66.0F38 0x07. */
114FNIEMOP_DEF(iemOp_vphsubsw_Vx_Hx_Wx)
115{
116 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBSW, vphsubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
117 IEMOPMEDIAOPTF3_INIT_VARS(vphsubsw);
118 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
119}
120
121
122/* Opcode VEX.0F38 0x08 - invalid. */
123
124
125/** Opcode VEX.66.0F38 0x08. */
126FNIEMOP_DEF(iemOp_vpsignb_Vx_Hx_Wx)
127{
128 IEMOP_MNEMONIC3(VEX_RVM, VPSIGNB, vpsignb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
129 IEMOPMEDIAOPTF3_INIT_VARS(vpsignb);
130 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
131}
132
133
134/* Opcode VEX.0F38 0x09 - invalid. */
135
136
137/** Opcode VEX.66.0F38 0x09. */
138FNIEMOP_DEF(iemOp_vpsignw_Vx_Hx_Wx)
139{
140 IEMOP_MNEMONIC3(VEX_RVM, VPSIGNW, vpsignw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
141 IEMOPMEDIAOPTF3_INIT_VARS(vpsignw);
142 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
143}
144
145
146/* Opcode VEX.0F38 0x0a - invalid. */
147
148
149/** Opcode VEX.66.0F38 0x0a. */
150FNIEMOP_DEF(iemOp_vpsignd_Vx_Hx_Wx)
151{
152 IEMOP_MNEMONIC3(VEX_RVM, VPSIGND, vpsignd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
153 IEMOPMEDIAOPTF3_INIT_VARS(vpsignd);
154 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
155}
156
157
158/* Opcode VEX.0F38 0x0b - invalid. */
159
160
161/** Opcode VEX.66.0F38 0x0b. */
162FNIEMOP_DEF(iemOp_vpmulhrsw_Vx_Hx_Wx)
163{
164 IEMOP_MNEMONIC3(VEX_RVM, VPMULHRSW, vpmulhrsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
165 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhrsw);
166 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
167}
168
169
170/* Opcode VEX.0F38 0x0c - invalid. */
171/** Opcode VEX.66.0F38 0x0c. */
172FNIEMOP_STUB(iemOp_vpermilps_Vx_Hx_Wx);
173/* Opcode VEX.0F38 0x0d - invalid. */
174/** Opcode VEX.66.0F38 0x0d. */
175FNIEMOP_STUB(iemOp_vpermilpd_Vx_Hx_Wx);
176/* Opcode VEX.0F38 0x0e - invalid. */
177/** Opcode VEX.66.0F38 0x0e. */
178FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
179/* Opcode VEX.0F38 0x0f - invalid. */
180/** Opcode VEX.66.0F38 0x0f. */
181FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
182
183
184/* Opcode VEX.0F38 0x10 - invalid */
185/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
186/* Opcode VEX.0F38 0x11 - invalid */
187/* Opcode VEX.66.0F38 0x11 - invalid */
188/* Opcode VEX.0F38 0x12 - invalid */
189/* Opcode VEX.66.0F38 0x12 - invalid */
190/* Opcode VEX.0F38 0x13 - invalid */
191/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
192/* Opcode VEX.0F38 0x14 - invalid */
193/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
194/* Opcode VEX.0F38 0x15 - invalid */
195/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
196/* Opcode VEX.0F38 0x16 - invalid */
197/** Opcode VEX.66.0F38 0x16. */
198FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
199/* Opcode VEX.0F38 0x17 - invalid */
200
201
202/** Opcode VEX.66.0F38 0x17 - invalid */
203FNIEMOP_DEF(iemOp_vptest_Vx_Wx)
204{
205 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
206 if (IEM_IS_MODRM_REG_MODE(bRm))
207 {
208 /*
209 * Register, register.
210 */
211 if (pVCpu->iem.s.uVexLength)
212 {
213 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
214 IEM_MC_BEGIN(3, 2);
215 IEM_MC_LOCAL(RTUINT256U, uSrc1);
216 IEM_MC_LOCAL(RTUINT256U, uSrc2);
217 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
218 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
219 IEM_MC_ARG(uint32_t *, pEFlags, 2);
220 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
221 IEM_MC_PREPARE_AVX_USAGE();
222 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
223 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
224 IEM_MC_REF_EFLAGS(pEFlags);
225 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
226 puSrc1, puSrc2, pEFlags);
227 IEM_MC_ADVANCE_RIP();
228 IEM_MC_END();
229 }
230 else
231 {
232 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
233 IEM_MC_BEGIN(3, 0);
234 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
235 IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
236 IEM_MC_ARG(uint32_t *, pEFlags, 2);
237 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
238 IEM_MC_PREPARE_AVX_USAGE();
239 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
240 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
241 IEM_MC_REF_EFLAGS(pEFlags);
242 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
243 IEM_MC_ADVANCE_RIP();
244 IEM_MC_END();
245 }
246 }
247 else
248 {
249 /*
250 * Register, memory.
251 */
252 if (pVCpu->iem.s.uVexLength)
253 {
254 IEM_MC_BEGIN(3, 3);
255 IEM_MC_LOCAL(RTUINT256U, uSrc1);
256 IEM_MC_LOCAL(RTUINT256U, uSrc2);
257 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
258 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
259 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
260 IEM_MC_ARG(uint32_t *, pEFlags, 2);
261
262 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
263 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
264 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
265 IEM_MC_PREPARE_AVX_USAGE();
266
267 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
268 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
269 IEM_MC_REF_EFLAGS(pEFlags);
270 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
271 puSrc1, puSrc2, pEFlags);
272
273 IEM_MC_ADVANCE_RIP();
274 IEM_MC_END();
275 }
276 else
277 {
278 IEM_MC_BEGIN(3, 2);
279 IEM_MC_LOCAL(RTUINT128U, uSrc2);
280 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
281 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
282 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
283 IEM_MC_ARG(uint32_t *, pEFlags, 2);
284
285 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
286 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
287 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
288 IEM_MC_PREPARE_AVX_USAGE();
289
290 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
291 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
292 IEM_MC_REF_EFLAGS(pEFlags);
293 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
294
295 IEM_MC_ADVANCE_RIP();
296 IEM_MC_END();
297 }
298 }
299 return VINF_SUCCESS;
300
301}
302
303
304/* Opcode VEX.0F38 0x18 - invalid */
305/** Opcode VEX.66.0F38 0x18. */
306FNIEMOP_STUB(iemOp_vbroadcastss_Vx_Wd);
307/* Opcode VEX.0F38 0x19 - invalid */
308/** Opcode VEX.66.0F38 0x19. */
309FNIEMOP_STUB(iemOp_vbroadcastsd_Vqq_Wq);
310/* Opcode VEX.0F38 0x1a - invalid */
311/** Opcode VEX.66.0F38 0x1a. */
312FNIEMOP_STUB(iemOp_vbroadcastf128_Vqq_Mdq);
313/* Opcode VEX.0F38 0x1b - invalid */
314/* Opcode VEX.66.0F38 0x1b - invalid */
315/* Opcode VEX.0F38 0x1c - invalid. */
316
317
318/** Opcode VEX.66.0F38 0x1c. */
319FNIEMOP_DEF(iemOp_vpabsb_Vx_Wx)
320{
321 IEMOP_MNEMONIC2(VEX_RM, VPABSB, vpabsb, Vx, Wx, DISOPTYPE_HARMLESS, 0);
322 IEMOPMEDIAOPTF2_INIT_VARS(vpabsb);
323 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
324}
325
326
327/* Opcode VEX.0F38 0x1d - invalid. */
328
329
330/** Opcode VEX.66.0F38 0x1d. */
331FNIEMOP_DEF(iemOp_vpabsw_Vx_Wx)
332{
333 IEMOP_MNEMONIC2(VEX_RM, VPABSW, vpabsw, Vx, Wx, DISOPTYPE_HARMLESS, 0);
334 IEMOPMEDIAOPTF2_INIT_VARS(vpabsw);
335 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
336}
337
338/* Opcode VEX.0F38 0x1e - invalid. */
339
340
341/** Opcode VEX.66.0F38 0x1e. */
342FNIEMOP_DEF(iemOp_vpabsd_Vx_Wx)
343{
344 IEMOP_MNEMONIC2(VEX_RM, VPABSD, vpabsd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
345 IEMOPMEDIAOPTF2_INIT_VARS(vpabsd);
346 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
347}
348
349
350/* Opcode VEX.0F38 0x1f - invalid */
351/* Opcode VEX.66.0F38 0x1f - invalid */
352
353
354/** Opcode VEX.66.0F38 0x20. */
355FNIEMOP_STUB(iemOp_vpmovsxbw_Vx_UxMq);
356/** Opcode VEX.66.0F38 0x21. */
357FNIEMOP_STUB(iemOp_vpmovsxbd_Vx_UxMd);
358/** Opcode VEX.66.0F38 0x22. */
359FNIEMOP_STUB(iemOp_vpmovsxbq_Vx_UxMw);
360/** Opcode VEX.66.0F38 0x23. */
361FNIEMOP_STUB(iemOp_vpmovsxwd_Vx_UxMq);
362/** Opcode VEX.66.0F38 0x24. */
363FNIEMOP_STUB(iemOp_vpmovsxwq_Vx_UxMd);
364/** Opcode VEX.66.0F38 0x25. */
365FNIEMOP_STUB(iemOp_vpmovsxdq_Vx_UxMq);
366/* Opcode VEX.66.0F38 0x26 - invalid */
367/* Opcode VEX.66.0F38 0x27 - invalid */
368
369
370/** Opcode VEX.66.0F38 0x28. */
371FNIEMOP_DEF(iemOp_vpmuldq_Vx_Hx_Wx)
372{
373 IEMOP_MNEMONIC3(VEX_RVM, VPMULDQ, vpmuldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
374 IEMOPMEDIAOPTF3_INIT_VARS(vpmuldq);
375 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
376}
377
378
379/** Opcode VEX.66.0F38 0x29. */
380FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
381{
382 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
383 IEMOPMEDIAF3_INIT_VARS(vpcmpeqq);
384 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
385}
386
387
388FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
389{
390 Assert(pVCpu->iem.s.uVexLength <= 1);
391 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
392 if (IEM_IS_MODRM_MEM_MODE(bRm))
393 {
394 if (pVCpu->iem.s.uVexLength == 0)
395 {
396 /**
397 * @opcode 0x2a
398 * @opcodesub !11 mr/reg vex.l=0
399 * @oppfx 0x66
400 * @opcpuid avx
401 * @opgroup og_avx_cachect
402 * @opxcpttype 1
403 * @optest op1=-1 op2=2 -> op1=2
404 * @optest op1=0 op2=-42 -> op1=-42
405 */
406 /* 128-bit: Memory, register. */
407 IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
408 DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
409 IEM_MC_BEGIN(0, 2);
410 IEM_MC_LOCAL(RTUINT128U, uSrc);
411 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
412
413 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
414 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
415 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
416 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
417
418 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
419 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
420
421 IEM_MC_ADVANCE_RIP();
422 IEM_MC_END();
423 }
424 else
425 {
426 /**
427 * @opdone
428 * @opcode 0x2a
429 * @opcodesub !11 mr/reg vex.l=1
430 * @oppfx 0x66
431 * @opcpuid avx2
432 * @opgroup og_avx2_cachect
433 * @opxcpttype 1
434 * @optest op1=-1 op2=2 -> op1=2
435 * @optest op1=0 op2=-42 -> op1=-42
436 */
437 /* 256-bit: Memory, register. */
438 IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
439 DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
440 IEM_MC_BEGIN(0, 2);
441 IEM_MC_LOCAL(RTUINT256U, uSrc);
442 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
443
444 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
445 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
446 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
447 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
448
449 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
450 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
451
452 IEM_MC_ADVANCE_RIP();
453 IEM_MC_END();
454 }
455 return VINF_SUCCESS;
456 }
457
458 /**
459 * @opdone
460 * @opmnemonic udvex660f382arg
461 * @opcode 0x2a
462 * @opcodesub 11 mr/reg
463 * @oppfx 0x66
464 * @opunused immediate
465 * @opcpuid avx
466 * @optest ->
467 */
468 return IEMOP_RAISE_INVALID_OPCODE();
469}
470
471
472/** Opcode VEX.66.0F38 0x2b. */
473FNIEMOP_DEF(iemOp_vpackusdw_Vx_Hx_Wx)
474{
475 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSDW, vpackusdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
476 IEMOPMEDIAOPTF3_INIT_VARS( vpackusdw);
477 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
478}
479
480
481/** Opcode VEX.66.0F38 0x2c. */
482FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
483/** Opcode VEX.66.0F38 0x2d. */
484FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
485/** Opcode VEX.66.0F38 0x2e. */
486FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
487/** Opcode VEX.66.0F38 0x2f. */
488FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
489
490/** Opcode VEX.66.0F38 0x30. */
491FNIEMOP_STUB(iemOp_vpmovzxbw_Vx_UxMq);
492/** Opcode VEX.66.0F38 0x31. */
493FNIEMOP_STUB(iemOp_vpmovzxbd_Vx_UxMd);
494/** Opcode VEX.66.0F38 0x32. */
495FNIEMOP_STUB(iemOp_vpmovzxbq_Vx_UxMw);
496/** Opcode VEX.66.0F38 0x33. */
497FNIEMOP_STUB(iemOp_vpmovzxwd_Vx_UxMq);
498/** Opcode VEX.66.0F38 0x34. */
499FNIEMOP_STUB(iemOp_vpmovzxwq_Vx_UxMd);
500/** Opcode VEX.66.0F38 0x35. */
501FNIEMOP_STUB(iemOp_vpmovzxdq_Vx_UxMq);
502/* Opcode VEX.66.0F38 0x36. */
503FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
504
505
506/** Opcode VEX.66.0F38 0x37. */
507FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
508{
509 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
510 IEMOPMEDIAF3_INIT_VARS(vpcmpgtq);
511 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
512}
513
514
515/** Opcode VEX.66.0F38 0x38. */
516FNIEMOP_DEF(iemOp_vpminsb_Vx_Hx_Wx)
517{
518 IEMOP_MNEMONIC3(VEX_RVM, VPMINSB, vpminsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
519 IEMOPMEDIAF3_INIT_VARS(vpminsb);
520 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
521}
522
523
524/** Opcode VEX.66.0F38 0x39. */
525FNIEMOP_DEF(iemOp_vpminsd_Vx_Hx_Wx)
526{
527 IEMOP_MNEMONIC3(VEX_RVM, VPMINSD, vpminsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
528 IEMOPMEDIAF3_INIT_VARS(vpminsd);
529 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
530}
531
532
533/** Opcode VEX.66.0F38 0x3a. */
534FNIEMOP_DEF(iemOp_vpminuw_Vx_Hx_Wx)
535{
536 IEMOP_MNEMONIC3(VEX_RVM, VPMINUW, vpminuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
537 IEMOPMEDIAF3_INIT_VARS(vpminuw);
538 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
539}
540
541
542/** Opcode VEX.66.0F38 0x3b. */
543FNIEMOP_DEF(iemOp_vpminud_Vx_Hx_Wx)
544{
545 IEMOP_MNEMONIC3(VEX_RVM, VPMINUD, vpminud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
546 IEMOPMEDIAF3_INIT_VARS(vpminud);
547 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
548}
549
550
551/** Opcode VEX.66.0F38 0x3c. */
552FNIEMOP_DEF(iemOp_vpmaxsb_Vx_Hx_Wx)
553{
554 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSB, vpmaxsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
555 IEMOPMEDIAF3_INIT_VARS(vpmaxsb);
556 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
557}
558
559
560/** Opcode VEX.66.0F38 0x3d. */
561FNIEMOP_DEF(iemOp_vpmaxsd_Vx_Hx_Wx)
562{
563 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSD, vpmaxsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
564 IEMOPMEDIAF3_INIT_VARS(vpmaxsd);
565 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
566}
567
568
569/** Opcode VEX.66.0F38 0x3e. */
570FNIEMOP_DEF(iemOp_vpmaxuw_Vx_Hx_Wx)
571{
572 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUW, vpmaxuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
573 IEMOPMEDIAF3_INIT_VARS(vpmaxuw);
574 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
575}
576
577
578/** Opcode VEX.66.0F38 0x3f. */
579FNIEMOP_DEF(iemOp_vpmaxud_Vx_Hx_Wx)
580{
581 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUD, vpmaxud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
582 IEMOPMEDIAF3_INIT_VARS(vpmaxud);
583 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
584}
585
586
587/** Opcode VEX.66.0F38 0x40. */
588FNIEMOP_DEF(iemOp_vpmulld_Vx_Hx_Wx)
589{
590 IEMOP_MNEMONIC3(VEX_RVM, VPMULLD, vpmulld, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
591 IEMOPMEDIAOPTF3_INIT_VARS(vpmulld);
592 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
593}
594
595
596/** Opcode VEX.66.0F38 0x41. */
597FNIEMOP_STUB(iemOp_vphminposuw_Vdq_Wdq);
598/* Opcode VEX.66.0F38 0x42 - invalid. */
599/* Opcode VEX.66.0F38 0x43 - invalid. */
600/* Opcode VEX.66.0F38 0x44 - invalid. */
601/** Opcode VEX.66.0F38 0x45. */
602FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
603/** Opcode VEX.66.0F38 0x46. */
604FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
605/** Opcode VEX.66.0F38 0x47. */
606FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
607/* Opcode VEX.66.0F38 0x48 - invalid. */
608/* Opcode VEX.66.0F38 0x49 - invalid. */
609/* Opcode VEX.66.0F38 0x4a - invalid. */
610/* Opcode VEX.66.0F38 0x4b - invalid. */
611/* Opcode VEX.66.0F38 0x4c - invalid. */
612/* Opcode VEX.66.0F38 0x4d - invalid. */
613/* Opcode VEX.66.0F38 0x4e - invalid. */
614/* Opcode VEX.66.0F38 0x4f - invalid. */
615
616/* Opcode VEX.66.0F38 0x50 - invalid. */
617/* Opcode VEX.66.0F38 0x51 - invalid. */
618/* Opcode VEX.66.0F38 0x52 - invalid. */
619/* Opcode VEX.66.0F38 0x53 - invalid. */
620/* Opcode VEX.66.0F38 0x54 - invalid. */
621/* Opcode VEX.66.0F38 0x55 - invalid. */
622/* Opcode VEX.66.0F38 0x56 - invalid. */
623/* Opcode VEX.66.0F38 0x57 - invalid. */
624/** Opcode VEX.66.0F38 0x58. */
625FNIEMOP_STUB(iemOp_vpbroadcastd_Vx_Wx);
626/** Opcode VEX.66.0F38 0x59. */
627FNIEMOP_STUB(iemOp_vpbroadcastq_Vx_Wx);
628/** Opcode VEX.66.0F38 0x5a. */
629FNIEMOP_STUB(iemOp_vbroadcasti128_Vqq_Mdq);
630/* Opcode VEX.66.0F38 0x5b - invalid. */
631/* Opcode VEX.66.0F38 0x5c - invalid. */
632/* Opcode VEX.66.0F38 0x5d - invalid. */
633/* Opcode VEX.66.0F38 0x5e - invalid. */
634/* Opcode VEX.66.0F38 0x5f - invalid. */
635
636/* Opcode VEX.66.0F38 0x60 - invalid. */
637/* Opcode VEX.66.0F38 0x61 - invalid. */
638/* Opcode VEX.66.0F38 0x62 - invalid. */
639/* Opcode VEX.66.0F38 0x63 - invalid. */
640/* Opcode VEX.66.0F38 0x64 - invalid. */
641/* Opcode VEX.66.0F38 0x65 - invalid. */
642/* Opcode VEX.66.0F38 0x66 - invalid. */
643/* Opcode VEX.66.0F38 0x67 - invalid. */
644/* Opcode VEX.66.0F38 0x68 - invalid. */
645/* Opcode VEX.66.0F38 0x69 - invalid. */
646/* Opcode VEX.66.0F38 0x6a - invalid. */
647/* Opcode VEX.66.0F38 0x6b - invalid. */
648/* Opcode VEX.66.0F38 0x6c - invalid. */
649/* Opcode VEX.66.0F38 0x6d - invalid. */
650/* Opcode VEX.66.0F38 0x6e - invalid. */
651/* Opcode VEX.66.0F38 0x6f - invalid. */
652
653/* Opcode VEX.66.0F38 0x70 - invalid. */
654/* Opcode VEX.66.0F38 0x71 - invalid. */
655/* Opcode VEX.66.0F38 0x72 - invalid. */
656/* Opcode VEX.66.0F38 0x73 - invalid. */
657/* Opcode VEX.66.0F38 0x74 - invalid. */
658/* Opcode VEX.66.0F38 0x75 - invalid. */
659/* Opcode VEX.66.0F38 0x76 - invalid. */
660/* Opcode VEX.66.0F38 0x77 - invalid. */
661/** Opcode VEX.66.0F38 0x78. */
662FNIEMOP_STUB(iemOp_vpboardcastb_Vx_Wx);
663/** Opcode VEX.66.0F38 0x79. */
664FNIEMOP_STUB(iemOp_vpboardcastw_Vx_Wx);
665/* Opcode VEX.66.0F38 0x7a - invalid. */
666/* Opcode VEX.66.0F38 0x7b - invalid. */
667/* Opcode VEX.66.0F38 0x7c - invalid. */
668/* Opcode VEX.66.0F38 0x7d - invalid. */
669/* Opcode VEX.66.0F38 0x7e - invalid. */
670/* Opcode VEX.66.0F38 0x7f - invalid. */
671
672/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
673/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
674/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
675/* Opcode VEX.66.0F38 0x83 - invalid. */
676/* Opcode VEX.66.0F38 0x84 - invalid. */
677/* Opcode VEX.66.0F38 0x85 - invalid. */
678/* Opcode VEX.66.0F38 0x86 - invalid. */
679/* Opcode VEX.66.0F38 0x87 - invalid. */
680/* Opcode VEX.66.0F38 0x88 - invalid. */
681/* Opcode VEX.66.0F38 0x89 - invalid. */
682/* Opcode VEX.66.0F38 0x8a - invalid. */
683/* Opcode VEX.66.0F38 0x8b - invalid. */
684/** Opcode VEX.66.0F38 0x8c. */
685FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
686/* Opcode VEX.66.0F38 0x8d - invalid. */
687/** Opcode VEX.66.0F38 0x8e. */
688FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
689/* Opcode VEX.66.0F38 0x8f - invalid. */
690
691/** Opcode VEX.66.0F38 0x90 (vex only). */
692FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
693/** Opcode VEX.66.0F38 0x91 (vex only). */
694FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
695/** Opcode VEX.66.0F38 0x92 (vex only). */
696FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
697/** Opcode VEX.66.0F38 0x93 (vex only). */
698FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
699/* Opcode VEX.66.0F38 0x94 - invalid. */
700/* Opcode VEX.66.0F38 0x95 - invalid. */
701/** Opcode VEX.66.0F38 0x96 (vex only). */
702FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
703/** Opcode VEX.66.0F38 0x97 (vex only). */
704FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
705/** Opcode VEX.66.0F38 0x98 (vex only). */
706FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
707/** Opcode VEX.66.0F38 0x99 (vex only). */
708FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
709/** Opcode VEX.66.0F38 0x9a (vex only). */
710FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
711/** Opcode VEX.66.0F38 0x9b (vex only). */
712FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
713/** Opcode VEX.66.0F38 0x9c (vex only). */
714FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
715/** Opcode VEX.66.0F38 0x9d (vex only). */
716FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
717/** Opcode VEX.66.0F38 0x9e (vex only). */
718FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
719/** Opcode VEX.66.0F38 0x9f (vex only). */
720FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
721
722/* Opcode VEX.66.0F38 0xa0 - invalid. */
723/* Opcode VEX.66.0F38 0xa1 - invalid. */
724/* Opcode VEX.66.0F38 0xa2 - invalid. */
725/* Opcode VEX.66.0F38 0xa3 - invalid. */
726/* Opcode VEX.66.0F38 0xa4 - invalid. */
727/* Opcode VEX.66.0F38 0xa5 - invalid. */
728/** Opcode VEX.66.0F38 0xa6 (vex only). */
729FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
730/** Opcode VEX.66.0F38 0xa7 (vex only). */
731FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
732/** Opcode VEX.66.0F38 0xa8 (vex only). */
733FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
734/** Opcode VEX.66.0F38 0xa9 (vex only). */
735FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
736/** Opcode VEX.66.0F38 0xaa (vex only). */
737FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
738/** Opcode VEX.66.0F38 0xab (vex only). */
739FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
740/** Opcode VEX.66.0F38 0xac (vex only). */
741FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
742/** Opcode VEX.66.0F38 0xad (vex only). */
743FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
744/** Opcode VEX.66.0F38 0xae (vex only). */
745FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
746/** Opcode VEX.66.0F38 0xaf (vex only). */
747FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
748
749/* Opcode VEX.66.0F38 0xb0 - invalid. */
750/* Opcode VEX.66.0F38 0xb1 - invalid. */
751/* Opcode VEX.66.0F38 0xb2 - invalid. */
752/* Opcode VEX.66.0F38 0xb3 - invalid. */
753/* Opcode VEX.66.0F38 0xb4 - invalid. */
754/* Opcode VEX.66.0F38 0xb5 - invalid. */
755/** Opcode VEX.66.0F38 0xb6 (vex only). */
756FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
757/** Opcode VEX.66.0F38 0xb7 (vex only). */
758FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
759/** Opcode VEX.66.0F38 0xb8 (vex only). */
760FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
761/** Opcode VEX.66.0F38 0xb9 (vex only). */
762FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
763/** Opcode VEX.66.0F38 0xba (vex only). */
764FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
765/** Opcode VEX.66.0F38 0xbb (vex only). */
766FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
767/** Opcode VEX.66.0F38 0xbc (vex only). */
768FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
769/** Opcode VEX.66.0F38 0xbd (vex only). */
770FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
771/** Opcode VEX.66.0F38 0xbe (vex only). */
772FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
773/** Opcode VEX.66.0F38 0xbf (vex only). */
774FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
775
776/* Opcode VEX.0F38 0xc0 - invalid. */
777/* Opcode VEX.66.0F38 0xc0 - invalid. */
778/* Opcode VEX.0F38 0xc1 - invalid. */
779/* Opcode VEX.66.0F38 0xc1 - invalid. */
780/* Opcode VEX.0F38 0xc2 - invalid. */
781/* Opcode VEX.66.0F38 0xc2 - invalid. */
782/* Opcode VEX.0F38 0xc3 - invalid. */
783/* Opcode VEX.66.0F38 0xc3 - invalid. */
784/* Opcode VEX.0F38 0xc4 - invalid. */
785/* Opcode VEX.66.0F38 0xc4 - invalid. */
786/* Opcode VEX.0F38 0xc5 - invalid. */
787/* Opcode VEX.66.0F38 0xc5 - invalid. */
788/* Opcode VEX.0F38 0xc6 - invalid. */
789/* Opcode VEX.66.0F38 0xc6 - invalid. */
790/* Opcode VEX.0F38 0xc7 - invalid. */
791/* Opcode VEX.66.0F38 0xc7 - invalid. */
792/** Opcode VEX.0F38 0xc8. */
793FNIEMOP_STUB(iemOp_vsha1nexte_Vdq_Wdq);
794/* Opcode VEX.66.0F38 0xc8 - invalid. */
795/** Opcode VEX.0F38 0xc9. */
796FNIEMOP_STUB(iemOp_vsha1msg1_Vdq_Wdq);
797/* Opcode VEX.66.0F38 0xc9 - invalid. */
798/** Opcode VEX.0F38 0xca. */
799FNIEMOP_STUB(iemOp_vsha1msg2_Vdq_Wdq);
800/* Opcode VEX.66.0F38 0xca - invalid. */
801/** Opcode VEX.0F38 0xcb. */
802FNIEMOP_STUB(iemOp_vsha256rnds2_Vdq_Wdq);
803/* Opcode VEX.66.0F38 0xcb - invalid. */
804/** Opcode VEX.0F38 0xcc. */
805FNIEMOP_STUB(iemOp_vsha256msg1_Vdq_Wdq);
806/* Opcode VEX.66.0F38 0xcc - invalid. */
807/** Opcode VEX.0F38 0xcd. */
808FNIEMOP_STUB(iemOp_vsha256msg2_Vdq_Wdq);
809/* Opcode VEX.66.0F38 0xcd - invalid. */
810/* Opcode VEX.0F38 0xce - invalid. */
811/* Opcode VEX.66.0F38 0xce - invalid. */
812/* Opcode VEX.0F38 0xcf - invalid. */
813/* Opcode VEX.66.0F38 0xcf - invalid. */
814
815/* Opcode VEX.66.0F38 0xd0 - invalid. */
816/* Opcode VEX.66.0F38 0xd1 - invalid. */
817/* Opcode VEX.66.0F38 0xd2 - invalid. */
818/* Opcode VEX.66.0F38 0xd3 - invalid. */
819/* Opcode VEX.66.0F38 0xd4 - invalid. */
820/* Opcode VEX.66.0F38 0xd5 - invalid. */
821/* Opcode VEX.66.0F38 0xd6 - invalid. */
822/* Opcode VEX.66.0F38 0xd7 - invalid. */
823/* Opcode VEX.66.0F38 0xd8 - invalid. */
824/* Opcode VEX.66.0F38 0xd9 - invalid. */
825/* Opcode VEX.66.0F38 0xda - invalid. */
826/** Opcode VEX.66.0F38 0xdb. */
827FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
828/** Opcode VEX.66.0F38 0xdc. */
829FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
830/** Opcode VEX.66.0F38 0xdd. */
831FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
832/** Opcode VEX.66.0F38 0xde. */
833FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
834/** Opcode VEX.66.0F38 0xdf. */
835FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
836
837/* Opcode VEX.66.0F38 0xe0 - invalid. */
838/* Opcode VEX.66.0F38 0xe1 - invalid. */
839/* Opcode VEX.66.0F38 0xe2 - invalid. */
840/* Opcode VEX.66.0F38 0xe3 - invalid. */
841/* Opcode VEX.66.0F38 0xe4 - invalid. */
842/* Opcode VEX.66.0F38 0xe5 - invalid. */
843/* Opcode VEX.66.0F38 0xe6 - invalid. */
844/* Opcode VEX.66.0F38 0xe7 - invalid. */
845/* Opcode VEX.66.0F38 0xe8 - invalid. */
846/* Opcode VEX.66.0F38 0xe9 - invalid. */
847/* Opcode VEX.66.0F38 0xea - invalid. */
848/* Opcode VEX.66.0F38 0xeb - invalid. */
849/* Opcode VEX.66.0F38 0xec - invalid. */
850/* Opcode VEX.66.0F38 0xed - invalid. */
851/* Opcode VEX.66.0F38 0xee - invalid. */
852/* Opcode VEX.66.0F38 0xef - invalid. */
853
854
855/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
856/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
857/* Opcode VEX.F3.0F38 0xf0 - invalid. */
858/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
859
860/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
861/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
862/* Opcode VEX.F3.0F38 0xf1 - invalid. */
863/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
864
865/** Opcode VEX.0F38 0xf2 - ANDN (vex only). */
866FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
867{
868 IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
869 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1)
870 return iemOp_InvalidNeedRM(pVCpu);
871 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF);
872 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
873 if (IEM_IS_MODRM_REG_MODE(bRm))
874 {
875 /*
876 * Register, register.
877 */
878 IEMOP_HLP_DONE_VEX_DECODING_L0();
879 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
880 {
881 IEM_MC_BEGIN(4, 0);
882 IEM_MC_ARG(uint64_t *, pDst, 0);
883 IEM_MC_ARG(uint64_t, uSrc1, 1);
884 IEM_MC_ARG(uint64_t, uSrc2, 2);
885 IEM_MC_ARG(uint32_t *, pEFlags, 3);
886 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
887 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
888 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
889 IEM_MC_REF_EFLAGS(pEFlags);
890 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
891 pDst, uSrc1, uSrc2, pEFlags);
892 IEM_MC_ADVANCE_RIP();
893 IEM_MC_END();
894 }
895 else
896 {
897 IEM_MC_BEGIN(4, 0);
898 IEM_MC_ARG(uint32_t *, pDst, 0);
899 IEM_MC_ARG(uint32_t, uSrc1, 1);
900 IEM_MC_ARG(uint32_t, uSrc2, 2);
901 IEM_MC_ARG(uint32_t *, pEFlags, 3);
902 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
903 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
904 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
905 IEM_MC_REF_EFLAGS(pEFlags);
906 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
907 pDst, uSrc1, uSrc2, pEFlags);
908 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
909 IEM_MC_ADVANCE_RIP();
910 IEM_MC_END();
911 }
912 }
913 else
914 {
915 /*
916 * Register, memory.
917 */
918 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
919 {
920 IEM_MC_BEGIN(4, 1);
921 IEM_MC_ARG(uint64_t *, pDst, 0);
922 IEM_MC_ARG(uint64_t, uSrc1, 1);
923 IEM_MC_ARG(uint64_t, uSrc2, 2);
924 IEM_MC_ARG(uint32_t *, pEFlags, 3);
925 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
926 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
927 IEMOP_HLP_DONE_VEX_DECODING_L0();
928 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
929 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
930 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
931 IEM_MC_REF_EFLAGS(pEFlags);
932 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
933 pDst, uSrc1, uSrc2, pEFlags);
934 IEM_MC_ADVANCE_RIP();
935 IEM_MC_END();
936 }
937 else
938 {
939 IEM_MC_BEGIN(4, 1);
940 IEM_MC_ARG(uint32_t *, pDst, 0);
941 IEM_MC_ARG(uint32_t, uSrc1, 1);
942 IEM_MC_ARG(uint32_t, uSrc2, 2);
943 IEM_MC_ARG(uint32_t *, pEFlags, 3);
944 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
945 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
946 IEMOP_HLP_DONE_VEX_DECODING_L0();
947 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
948 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
949 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
950 IEM_MC_REF_EFLAGS(pEFlags);
951 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
952 pDst, uSrc1, uSrc2, pEFlags);
953 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
954 IEM_MC_ADVANCE_RIP();
955 IEM_MC_END();
956 }
957 }
958 return VINF_SUCCESS;
959}
960
961/* Opcode VEX.66.0F38 0xf2 - invalid. */
962/* Opcode VEX.F3.0F38 0xf2 - invalid. */
963/* Opcode VEX.F2.0F38 0xf2 - invalid. */
964
965
966/* Opcode VEX.0F38 0xf3 - invalid. */
967/* Opcode VEX.66.0F38 0xf3 - invalid. */
968
969/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
970
971/** Body for the vex group 17 instructions. */
972#define IEMOP_BODY_By_Ey(a_Instr) \
973 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1) \
974 return iemOp_InvalidWithRM(pVCpu, bRm); /* decode memory variant? */ \
975 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF); \
976 if (IEM_IS_MODRM_REG_MODE(bRm)) \
977 { \
978 /* \
979 * Register, register. \
980 */ \
981 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
982 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
983 { \
984 IEM_MC_BEGIN(3, 0); \
985 IEM_MC_ARG(uint64_t *, pDst, 0); \
986 IEM_MC_ARG(uint64_t, uSrc, 1); \
987 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
988 IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
989 IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
990 IEM_MC_REF_EFLAGS(pEFlags); \
991 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
992 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
993 IEM_MC_ADVANCE_RIP(); \
994 IEM_MC_END(); \
995 } \
996 else \
997 { \
998 IEM_MC_BEGIN(3, 0); \
999 IEM_MC_ARG(uint32_t *, pDst, 0); \
1000 IEM_MC_ARG(uint32_t, uSrc, 1); \
1001 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1002 IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1003 IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1004 IEM_MC_REF_EFLAGS(pEFlags); \
1005 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
1006 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
1007 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1008 IEM_MC_ADVANCE_RIP(); \
1009 IEM_MC_END(); \
1010 } \
1011 } \
1012 else \
1013 { \
1014 /* \
1015 * Register, memory. \
1016 */ \
1017 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1018 { \
1019 IEM_MC_BEGIN(3, 1); \
1020 IEM_MC_ARG(uint64_t *, pDst, 0); \
1021 IEM_MC_ARG(uint64_t, uSrc, 1); \
1022 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1023 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1024 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1025 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1026 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1027 IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1028 IEM_MC_REF_EFLAGS(pEFlags); \
1029 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
1030 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
1031 IEM_MC_ADVANCE_RIP(); \
1032 IEM_MC_END(); \
1033 } \
1034 else \
1035 { \
1036 IEM_MC_BEGIN(3, 1); \
1037 IEM_MC_ARG(uint32_t *, pDst, 0); \
1038 IEM_MC_ARG(uint32_t, uSrc, 1); \
1039 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1040 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1041 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1042 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1043 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1044 IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1045 IEM_MC_REF_EFLAGS(pEFlags); \
1046 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
1047 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
1048 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1049 IEM_MC_ADVANCE_RIP(); \
1050 IEM_MC_END(); \
1051 } \
1052 } \
1053 return VINF_SUCCESS
1054
1055
1056/* Opcode VEX.F3.0F38 0xf3 /1. */
1057/** @opcode /1
1058 * @opmaps vexgrp17 */
1059FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
1060{
1061 IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1062 IEMOP_BODY_By_Ey(blsr);
1063}
1064
1065
1066/* Opcode VEX.F3.0F38 0xf3 /2. */
1067/** @opcode /2
1068 * @opmaps vexgrp17 */
1069FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
1070{
1071 IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1072 IEMOP_BODY_By_Ey(blsmsk);
1073}
1074
1075
1076/* Opcode VEX.F3.0F38 0xf3 /3. */
1077/** @opcode /3
1078 * @opmaps vexgrp17 */
1079FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
1080{
1081 IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1082 IEMOP_BODY_By_Ey(blsi);
1083}
1084
1085
1086/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
1087/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
1088/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
1089/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
1090
1091/**
1092 * Group 17 jump table for the VEX.F3 variant.
1093 */
1094IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
1095{
1096 /* /0 */ iemOp_InvalidWithRM,
1097 /* /1 */ iemOp_VGrp17_blsr_By_Ey,
1098 /* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
1099 /* /3 */ iemOp_VGrp17_blsi_By_Ey,
1100 /* /4 */ iemOp_InvalidWithRM,
1101 /* /5 */ iemOp_InvalidWithRM,
1102 /* /6 */ iemOp_InvalidWithRM,
1103 /* /7 */ iemOp_InvalidWithRM
1104};
1105AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
1106
1107/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
1108FNIEMOP_DEF(iemOp_VGrp17_f3)
1109{
1110 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1111 return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[IEM_GET_MODRM_REG_8(bRm)], bRm);
1112}
1113
1114/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
1115
1116
1117/* Opcode VEX.0F38 0xf4 - invalid. */
1118/* Opcode VEX.66.0F38 0xf4 - invalid. */
1119/* Opcode VEX.F3.0F38 0xf4 - invalid. */
1120/* Opcode VEX.F2.0F38 0xf4 - invalid. */
1121
1122/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
1123#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
1124 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1125 return iemOp_InvalidNeedRM(pVCpu); \
1126 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
1127 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1128 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1129 { \
1130 /* \
1131 * Register, register. \
1132 */ \
1133 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1134 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1135 { \
1136 IEM_MC_BEGIN(4, 0); \
1137 IEM_MC_ARG(uint64_t *, pDst, 0); \
1138 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1139 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1140 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1141 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1142 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1143 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1144 IEM_MC_REF_EFLAGS(pEFlags); \
1145 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1146 iemAImpl_ ## a_Instr ## _u64_fallback), \
1147 pDst, uSrc1, uSrc2, pEFlags); \
1148 IEM_MC_ADVANCE_RIP(); \
1149 IEM_MC_END(); \
1150 } \
1151 else \
1152 { \
1153 IEM_MC_BEGIN(4, 0); \
1154 IEM_MC_ARG(uint32_t *, pDst, 0); \
1155 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1156 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1157 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1158 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1159 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1160 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1161 IEM_MC_REF_EFLAGS(pEFlags); \
1162 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1163 iemAImpl_ ## a_Instr ## _u32_fallback), \
1164 pDst, uSrc1, uSrc2, pEFlags); \
1165 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1166 IEM_MC_ADVANCE_RIP(); \
1167 IEM_MC_END(); \
1168 } \
1169 } \
1170 else \
1171 { \
1172 /* \
1173 * Register, memory. \
1174 */ \
1175 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1176 { \
1177 IEM_MC_BEGIN(4, 1); \
1178 IEM_MC_ARG(uint64_t *, pDst, 0); \
1179 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1180 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1181 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1182 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1183 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1184 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1185 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1186 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1187 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1188 IEM_MC_REF_EFLAGS(pEFlags); \
1189 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1190 iemAImpl_ ## a_Instr ## _u64_fallback), \
1191 pDst, uSrc1, uSrc2, pEFlags); \
1192 IEM_MC_ADVANCE_RIP(); \
1193 IEM_MC_END(); \
1194 } \
1195 else \
1196 { \
1197 IEM_MC_BEGIN(4, 1); \
1198 IEM_MC_ARG(uint32_t *, pDst, 0); \
1199 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1200 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1201 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1202 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1203 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1204 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1205 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1206 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1207 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1208 IEM_MC_REF_EFLAGS(pEFlags); \
1209 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1210 iemAImpl_ ## a_Instr ## _u32_fallback), \
1211 pDst, uSrc1, uSrc2, pEFlags); \
1212 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1213 IEM_MC_ADVANCE_RIP(); \
1214 IEM_MC_END(); \
1215 } \
1216 } \
1217 return VINF_SUCCESS
1218
1219/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
1220#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember, a_fUndefFlags) \
1221 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1222 return iemOp_InvalidNeedRM(pVCpu); \
1223 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
1224 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1225 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1226 { \
1227 /* \
1228 * Register, register. \
1229 */ \
1230 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1231 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1232 { \
1233 IEM_MC_BEGIN(3, 0); \
1234 IEM_MC_ARG(uint64_t *, pDst, 0); \
1235 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1236 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1237 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1238 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1239 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1240 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1241 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1242 IEM_MC_ADVANCE_RIP(); \
1243 IEM_MC_END(); \
1244 } \
1245 else \
1246 { \
1247 IEM_MC_BEGIN(3, 0); \
1248 IEM_MC_ARG(uint32_t *, pDst, 0); \
1249 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1250 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1251 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1252 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1253 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1254 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1255 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1256 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1257 IEM_MC_ADVANCE_RIP(); \
1258 IEM_MC_END(); \
1259 } \
1260 } \
1261 else \
1262 { \
1263 /* \
1264 * Register, memory. \
1265 */ \
1266 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1267 { \
1268 IEM_MC_BEGIN(3, 1); \
1269 IEM_MC_ARG(uint64_t *, pDst, 0); \
1270 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1271 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1272 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1273 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1274 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1275 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1276 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1277 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1278 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1279 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1280 IEM_MC_ADVANCE_RIP(); \
1281 IEM_MC_END(); \
1282 } \
1283 else \
1284 { \
1285 IEM_MC_BEGIN(3, 1); \
1286 IEM_MC_ARG(uint32_t *, pDst, 0); \
1287 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1288 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1289 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1290 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1291 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1292 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1293 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1294 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1295 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1296 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1297 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1298 IEM_MC_ADVANCE_RIP(); \
1299 IEM_MC_END(); \
1300 } \
1301 } \
1302 return VINF_SUCCESS
1303
1304/** Opcode VEX.0F38 0xf5 (vex only). */
1305FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
1306{
1307 IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1308 IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF | X86_EFL_PF);
1309}
1310
1311/* Opcode VEX.66.0F38 0xf5 - invalid. */
1312
1313/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
1314#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
1315 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1316 return iemOp_InvalidNeedRM(pVCpu); \
1317 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1318 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1319 { \
1320 /* \
1321 * Register, register. \
1322 */ \
1323 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1324 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1325 { \
1326 IEM_MC_BEGIN(3, 0); \
1327 IEM_MC_ARG(uint64_t *, pDst, 0); \
1328 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1329 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1330 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1331 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1332 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1333 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1334 iemAImpl_ ## a_Instr ## _u64, \
1335 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1336 IEM_MC_ADVANCE_RIP(); \
1337 IEM_MC_END(); \
1338 } \
1339 else \
1340 { \
1341 IEM_MC_BEGIN(3, 0); \
1342 IEM_MC_ARG(uint32_t *, pDst, 0); \
1343 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1344 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1345 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1346 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1347 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1348 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1349 iemAImpl_ ## a_Instr ## _u32, \
1350 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1351 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1352 IEM_MC_ADVANCE_RIP(); \
1353 IEM_MC_END(); \
1354 } \
1355 } \
1356 else \
1357 { \
1358 /* \
1359 * Register, memory. \
1360 */ \
1361 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1362 { \
1363 IEM_MC_BEGIN(3, 1); \
1364 IEM_MC_ARG(uint64_t *, pDst, 0); \
1365 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1366 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1367 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1368 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1369 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1370 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1371 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1372 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1373 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1374 iemAImpl_ ## a_Instr ## _u64, \
1375 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1376 IEM_MC_ADVANCE_RIP(); \
1377 IEM_MC_END(); \
1378 } \
1379 else \
1380 { \
1381 IEM_MC_BEGIN(3, 1); \
1382 IEM_MC_ARG(uint32_t *, pDst, 0); \
1383 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1384 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1385 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1386 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1387 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1388 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1389 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1390 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1391 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1392 iemAImpl_ ## a_Instr ## _u32, \
1393 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1394 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1395 IEM_MC_ADVANCE_RIP(); \
1396 IEM_MC_END(); \
1397 } \
1398 } \
1399 return VINF_SUCCESS;
1400
1401
1402/** Opcode VEX.F3.0F38 0xf5 (vex only). */
1403FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
1404{
1405 IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1406 IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
1407}
1408
1409
1410/** Opcode VEX.F2.0F38 0xf5 (vex only). */
1411FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
1412{
1413 IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1414 IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
1415}
1416
1417
1418/* Opcode VEX.0F38 0xf6 - invalid. */
1419/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
1420/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
1421
1422
1423/** Opcode VEX.F2.0F38 0xf6 (vex only) */
1424FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
1425{
1426 IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1427 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
1428 return iemOp_InvalidNeedRM(pVCpu);
1429 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1430 if (IEM_IS_MODRM_REG_MODE(bRm))
1431 {
1432 /*
1433 * Register, register.
1434 */
1435 IEMOP_HLP_DONE_VEX_DECODING_L0();
1436 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1437 {
1438 IEM_MC_BEGIN(4, 0);
1439 IEM_MC_ARG(uint64_t *, pDst1, 0);
1440 IEM_MC_ARG(uint64_t *, pDst2, 1);
1441 IEM_MC_ARG(uint64_t, uSrc1, 2);
1442 IEM_MC_ARG(uint64_t, uSrc2, 3);
1443 IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1444 IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1445 IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1446 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1447 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1448 pDst1, pDst2, uSrc1, uSrc2);
1449 IEM_MC_ADVANCE_RIP();
1450 IEM_MC_END();
1451 }
1452 else
1453 {
1454 IEM_MC_BEGIN(4, 0);
1455 IEM_MC_ARG(uint32_t *, pDst1, 0);
1456 IEM_MC_ARG(uint32_t *, pDst2, 1);
1457 IEM_MC_ARG(uint32_t, uSrc1, 2);
1458 IEM_MC_ARG(uint32_t, uSrc2, 3);
1459 IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1460 IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1461 IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1462 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1463 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1464 pDst1, pDst2, uSrc1, uSrc2);
1465 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1466 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1467 IEM_MC_ADVANCE_RIP();
1468 IEM_MC_END();
1469 }
1470 }
1471 else
1472 {
1473 /*
1474 * Register, memory.
1475 */
1476 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1477 {
1478 IEM_MC_BEGIN(4, 1);
1479 IEM_MC_ARG(uint64_t *, pDst1, 0);
1480 IEM_MC_ARG(uint64_t *, pDst2, 1);
1481 IEM_MC_ARG(uint64_t, uSrc1, 2);
1482 IEM_MC_ARG(uint64_t, uSrc2, 3);
1483 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1484 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1485 IEMOP_HLP_DONE_VEX_DECODING_L0();
1486 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1487 IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1488 IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1489 IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1490 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1491 pDst1, pDst2, uSrc1, uSrc2);
1492 IEM_MC_ADVANCE_RIP();
1493 IEM_MC_END();
1494 }
1495 else
1496 {
1497 IEM_MC_BEGIN(4, 1);
1498 IEM_MC_ARG(uint32_t *, pDst1, 0);
1499 IEM_MC_ARG(uint32_t *, pDst2, 1);
1500 IEM_MC_ARG(uint32_t, uSrc1, 2);
1501 IEM_MC_ARG(uint32_t, uSrc2, 3);
1502 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1503 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1504 IEMOP_HLP_DONE_VEX_DECODING_L0();
1505 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1506 IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1507 IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1508 IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1509 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1510 pDst1, pDst2, uSrc1, uSrc2);
1511 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1512 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1513 IEM_MC_ADVANCE_RIP();
1514 IEM_MC_END();
1515 }
1516 }
1517 return VINF_SUCCESS;
1518}
1519
1520
1521/** Opcode VEX.0F38 0xf7 (vex only). */
1522FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
1523{
1524 IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1525 IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF | X86_EFL_AF | X86_EFL_PF);
1526}
1527
1528
1529/** Opcode VEX.66.0F38 0xf7 (vex only). */
1530FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
1531{
1532 IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1533 IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2, 0);
1534}
1535
1536
1537/** Opcode VEX.F3.0F38 0xf7 (vex only). */
1538FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
1539{
1540 IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1541 IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2, 0);
1542}
1543
1544
1545/** Opcode VEX.F2.0F38 0xf7 (vex only). */
1546FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
1547{
1548 IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1549 IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2, 0);
1550}
1551
1552/* Opcode VEX.0F38 0xf8 - invalid. */
1553/* Opcode VEX.66.0F38 0xf8 - invalid. */
1554/* Opcode VEX.F3.0F38 0xf8 - invalid. */
1555/* Opcode VEX.F2.0F38 0xf8 - invalid. */
1556
1557/* Opcode VEX.0F38 0xf9 - invalid. */
1558/* Opcode VEX.66.0F38 0xf9 - invalid. */
1559/* Opcode VEX.F3.0F38 0xf9 - invalid. */
1560/* Opcode VEX.F2.0F38 0xf9 - invalid. */
1561
1562/* Opcode VEX.0F38 0xfa - invalid. */
1563/* Opcode VEX.66.0F38 0xfa - invalid. */
1564/* Opcode VEX.F3.0F38 0xfa - invalid. */
1565/* Opcode VEX.F2.0F38 0xfa - invalid. */
1566
1567/* Opcode VEX.0F38 0xfb - invalid. */
1568/* Opcode VEX.66.0F38 0xfb - invalid. */
1569/* Opcode VEX.F3.0F38 0xfb - invalid. */
1570/* Opcode VEX.F2.0F38 0xfb - invalid. */
1571
1572/* Opcode VEX.0F38 0xfc - invalid. */
1573/* Opcode VEX.66.0F38 0xfc - invalid. */
1574/* Opcode VEX.F3.0F38 0xfc - invalid. */
1575/* Opcode VEX.F2.0F38 0xfc - invalid. */
1576
1577/* Opcode VEX.0F38 0xfd - invalid. */
1578/* Opcode VEX.66.0F38 0xfd - invalid. */
1579/* Opcode VEX.F3.0F38 0xfd - invalid. */
1580/* Opcode VEX.F2.0F38 0xfd - invalid. */
1581
1582/* Opcode VEX.0F38 0xfe - invalid. */
1583/* Opcode VEX.66.0F38 0xfe - invalid. */
1584/* Opcode VEX.F3.0F38 0xfe - invalid. */
1585/* Opcode VEX.F2.0F38 0xfe - invalid. */
1586
1587/* Opcode VEX.0F38 0xff - invalid. */
1588/* Opcode VEX.66.0F38 0xff - invalid. */
1589/* Opcode VEX.F3.0F38 0xff - invalid. */
1590/* Opcode VEX.F2.0F38 0xff - invalid. */
1591
1592
1593/**
1594 * VEX opcode map \#2.
1595 *
1596 * @sa g_apfnThreeByte0f38
1597 */
1598IEM_STATIC const PFNIEMOP g_apfnVexMap2[] =
1599{
1600 /* no prefix, 066h prefix f3h prefix, f2h prefix */
1601 /* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1602 /* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1603 /* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1604 /* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1605 /* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1606 /* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1607 /* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1608 /* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1609 /* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1610 /* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1611 /* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1612 /* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1613 /* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1614 /* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1615 /* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1616 /* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1617
1618 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
1619 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1620 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1621 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1622 /* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
1623 /* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
1624 /* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1625 /* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1626 /* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1627 /* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1628 /* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1629 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1630 /* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1631 /* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1632 /* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1633 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1634
1635 /* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1636 /* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1637 /* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1638 /* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1639 /* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1640 /* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1641 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1642 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1643 /* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1644 /* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1645 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1646 /* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1647 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1648 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1649 /* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1650 /* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1651
1652 /* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1653 /* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1654 /* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1655 /* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1656 /* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1657 /* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1658 /* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1659 /* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1660 /* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1661 /* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1662 /* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1663 /* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1664 /* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1665 /* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1666 /* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1667 /* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1668
1669 /* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1670 /* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1671 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1672 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1673 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1674 /* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1675 /* 0x46 */ iemOp_InvalidNeedRM, iemOp_vsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1676 /* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1677 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1678 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1679 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1680 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1681 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1682 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1683 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1684 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1685
1686 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1687 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1688 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1689 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1690 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1691 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1692 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1693 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1694 /* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1695 /* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1696 /* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1697 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1698 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1699 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1700 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1701 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1702
1703 /* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1704 /* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1705 /* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1706 /* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1707 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1708 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1709 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1710 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1711 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1712 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1713 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1714 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1715 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1716 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1717 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1718 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1719
1720 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1721 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1722 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1723 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1724 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1725 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1726 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1727 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1728 /* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpboardcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1729 /* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpboardcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1730 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1731 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1732 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1733 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1734 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1735 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1736
1737 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
1738 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
1739 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
1740 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1741 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1742 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1743 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1744 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1745 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1746 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1747 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1748 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1749 /* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1750 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1751 /* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1752 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1753
1754 /* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1755 /* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1756 /* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1757 /* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1758 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1759 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1760 /* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1761 /* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1762 /* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1763 /* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1764 /* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1765 /* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1766 /* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1767 /* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1768 /* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1769 /* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1770
1771 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1772 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1773 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1774 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1775 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1776 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1777 /* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1778 /* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1779 /* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1780 /* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1781 /* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1782 /* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1783 /* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1784 /* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1785 /* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1786 /* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1787
1788 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1789 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1790 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1791 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1792 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1793 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1794 /* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1795 /* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1796 /* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1797 /* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1798 /* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1799 /* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1800 /* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1801 /* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1802 /* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1803 /* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1804
1805 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1806 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1807 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1808 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1809 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1810 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1811 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1812 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1813 /* 0xc8 */ iemOp_vsha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1814 /* 0xc9 */ iemOp_vsha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1815 /* 0xca */ iemOp_vsha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1816 /* 0xcb */ iemOp_vsha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1817 /* 0xcc */ iemOp_vsha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1818 /* 0xcd */ iemOp_vsha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1819 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1820 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1821
1822 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1823 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1824 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1825 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1826 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1827 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1828 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1829 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1830 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1831 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1832 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1833 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1834 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1835 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1836 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1837 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1838
1839 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1840 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1841 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1842 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1843 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1844 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1845 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1846 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1847 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1848 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1849 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1850 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1851 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1852 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1853 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1854 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1855
1856 /* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1857 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1858 /* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1859 /* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1860 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1861 /* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
1862 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
1863 /* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
1864 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1865 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1866 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1867 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1868 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1869 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1870 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1871 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1872};
1873AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
1874
1875/** @} */
1876
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