VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h@ 96713

Last change on this file since 96713 was 96713, checked in by vboxsync, 3 years ago

VMM/IEM: Implement [v]movmskps/[v]movmskpd instructions, bugref:9898
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1/* $Id: IEMAllInstructionsVexMap1.cpp.h 96713 2022-09-13 09:09:57Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsTwoByte0f.cpp.h is a legacy mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 1
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128
39 * - vpxxx ymm0, ymm1, ymm2/mem256
40 *
41 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
42 */
43FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, PCIEMOPMEDIAF3, pImpl)
44{
45 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
46 if (IEM_IS_MODRM_REG_MODE(bRm))
47 {
48 /*
49 * Register, register.
50 */
51 if (pVCpu->iem.s.uVexLength)
52 {
53 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
54 IEM_MC_BEGIN(4, 3);
55 IEM_MC_LOCAL(RTUINT256U, uDst);
56 IEM_MC_LOCAL(RTUINT256U, uSrc1);
57 IEM_MC_LOCAL(RTUINT256U, uSrc2);
58 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
59 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 1);
60 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 2);
61 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 3);
62 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
63 IEM_MC_PREPARE_AVX_USAGE();
64 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
65 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
66 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
67 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
68 IEM_MC_ADVANCE_RIP();
69 IEM_MC_END();
70 }
71 else
72 {
73 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
74 IEM_MC_BEGIN(4, 0);
75 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
76 IEM_MC_ARG(PRTUINT128U, puDst, 1);
77 IEM_MC_ARG(PCRTUINT128U, puSrc1, 2);
78 IEM_MC_ARG(PCRTUINT128U, puSrc2, 3);
79 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
80 IEM_MC_PREPARE_AVX_USAGE();
81 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
82 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
83 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
84 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
85 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
86 IEM_MC_ADVANCE_RIP();
87 IEM_MC_END();
88 }
89 }
90 else
91 {
92 /*
93 * Register, memory.
94 */
95 if (pVCpu->iem.s.uVexLength)
96 {
97 IEM_MC_BEGIN(4, 4);
98 IEM_MC_LOCAL(RTUINT256U, uDst);
99 IEM_MC_LOCAL(RTUINT256U, uSrc1);
100 IEM_MC_LOCAL(RTUINT256U, uSrc2);
101 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
102 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
103 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 1);
104 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 2);
105 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 3);
106
107 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
108 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
109 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
110 IEM_MC_PREPARE_AVX_USAGE();
111
112 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
113 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
114 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
115 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
116
117 IEM_MC_ADVANCE_RIP();
118 IEM_MC_END();
119 }
120 else
121 {
122 IEM_MC_BEGIN(4, 2);
123 IEM_MC_LOCAL(RTUINT128U, uSrc2);
124 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
125 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
126 IEM_MC_ARG(PRTUINT128U, puDst, 1);
127 IEM_MC_ARG(PCRTUINT128U, puSrc1, 2);
128 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 3);
129
130 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
131 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
132 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
133 IEM_MC_PREPARE_AVX_USAGE();
134
135 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
136 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
137 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
138 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
139 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
140
141 IEM_MC_ADVANCE_RIP();
142 IEM_MC_END();
143 }
144 }
145 return VINF_SUCCESS;
146}
147
148
149/**
150 * Common worker for AVX2 instructions on the forms:
151 * - vpxxx xmm0, xmm1, xmm2/mem128
152 * - vpxxx ymm0, ymm1, ymm2/mem256
153 *
154 * Takes function table for function w/o implicit state parameter.
155 *
156 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
157 */
158FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, PCIEMOPMEDIAOPTF3, pImpl)
159{
160 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
161 if (IEM_IS_MODRM_REG_MODE(bRm))
162 {
163 /*
164 * Register, register.
165 */
166 if (pVCpu->iem.s.uVexLength)
167 {
168 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
169 IEM_MC_BEGIN(3, 3);
170 IEM_MC_LOCAL(RTUINT256U, uDst);
171 IEM_MC_LOCAL(RTUINT256U, uSrc1);
172 IEM_MC_LOCAL(RTUINT256U, uSrc2);
173 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
174 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
175 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
176 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
177 IEM_MC_PREPARE_AVX_USAGE();
178 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
179 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
180 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
181 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
182 IEM_MC_ADVANCE_RIP();
183 IEM_MC_END();
184 }
185 else
186 {
187 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
188 IEM_MC_BEGIN(3, 0);
189 IEM_MC_ARG(PRTUINT128U, puDst, 0);
190 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
191 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
192 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
193 IEM_MC_PREPARE_AVX_USAGE();
194 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
195 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
196 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
197 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
198 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
199 IEM_MC_ADVANCE_RIP();
200 IEM_MC_END();
201 }
202 }
203 else
204 {
205 /*
206 * Register, memory.
207 */
208 if (pVCpu->iem.s.uVexLength)
209 {
210 IEM_MC_BEGIN(3, 4);
211 IEM_MC_LOCAL(RTUINT256U, uDst);
212 IEM_MC_LOCAL(RTUINT256U, uSrc1);
213 IEM_MC_LOCAL(RTUINT256U, uSrc2);
214 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
215 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
216 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
217 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
218
219 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
220 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
221 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
222 IEM_MC_PREPARE_AVX_USAGE();
223
224 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
225 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
226 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
227 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
228
229 IEM_MC_ADVANCE_RIP();
230 IEM_MC_END();
231 }
232 else
233 {
234 IEM_MC_BEGIN(3, 2);
235 IEM_MC_LOCAL(RTUINT128U, uSrc2);
236 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
237 IEM_MC_ARG(PRTUINT128U, puDst, 0);
238 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
239 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
240
241 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
242 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
243 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
244 IEM_MC_PREPARE_AVX_USAGE();
245
246 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
247 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
248 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
249 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
250 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
251
252 IEM_MC_ADVANCE_RIP();
253 IEM_MC_END();
254 }
255 }
256 return VINF_SUCCESS;
257}
258
259
260/**
261 * Common worker for AVX2 instructions on the forms:
262 * - vpunpckhxx xmm0, xmm1, xmm2/mem128
263 * - vpunpckhxx ymm0, ymm1, ymm2/mem256
264 *
265 * The 128-bit memory version of this instruction may elect to skip fetching the
266 * lower 64 bits of the operand. We, however, do not.
267 *
268 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
269 */
270FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, PCIEMOPMEDIAOPTF3, pImpl)
271{
272 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
273}
274
275
276/**
277 * Common worker for AVX2 instructions on the forms:
278 * - vpunpcklxx xmm0, xmm1, xmm2/mem128
279 * - vpunpcklxx ymm0, ymm1, ymm2/mem256
280 *
281 * The 128-bit memory version of this instruction may elect to skip fetching the
282 * higher 64 bits of the operand. We, however, do not.
283 *
284 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
285 */
286FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, PCIEMOPMEDIAOPTF3, pImpl)
287{
288 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
289}
290
291
292/**
293 * Common worker for AVX2 instructions on the forms:
294 * - vpxxx xmm0, xmm1/mem128
295 * - vpxxx ymm0, ymm1/mem256
296 *
297 * Takes function table for function w/o implicit state parameter.
298 *
299 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
300 */
301FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, PCIEMOPMEDIAOPTF2, pImpl)
302{
303 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
304 if (IEM_IS_MODRM_REG_MODE(bRm))
305 {
306 /*
307 * Register, register.
308 */
309 if (pVCpu->iem.s.uVexLength)
310 {
311 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
312 IEM_MC_BEGIN(2, 2);
313 IEM_MC_LOCAL(RTUINT256U, uDst);
314 IEM_MC_LOCAL(RTUINT256U, uSrc);
315 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
316 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
317 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
318 IEM_MC_PREPARE_AVX_USAGE();
319 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
320 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
321 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
322 IEM_MC_ADVANCE_RIP();
323 IEM_MC_END();
324 }
325 else
326 {
327 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
328 IEM_MC_BEGIN(2, 0);
329 IEM_MC_ARG(PRTUINT128U, puDst, 0);
330 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
331 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
332 IEM_MC_PREPARE_AVX_USAGE();
333 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
334 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
335 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
336 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
337 IEM_MC_ADVANCE_RIP();
338 IEM_MC_END();
339 }
340 }
341 else
342 {
343 /*
344 * Register, memory.
345 */
346 if (pVCpu->iem.s.uVexLength)
347 {
348 IEM_MC_BEGIN(2, 3);
349 IEM_MC_LOCAL(RTUINT256U, uDst);
350 IEM_MC_LOCAL(RTUINT256U, uSrc);
351 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
352 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
353 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
354
355 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
356 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
357 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
358 IEM_MC_PREPARE_AVX_USAGE();
359
360 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
361 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
362 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
363
364 IEM_MC_ADVANCE_RIP();
365 IEM_MC_END();
366 }
367 else
368 {
369 IEM_MC_BEGIN(2, 2);
370 IEM_MC_LOCAL(RTUINT128U, uSrc);
371 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
372 IEM_MC_ARG(PRTUINT128U, puDst, 0);
373 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
374
375 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
376 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
377 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
378 IEM_MC_PREPARE_AVX_USAGE();
379
380 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
381 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
382 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
383 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
384
385 IEM_MC_ADVANCE_RIP();
386 IEM_MC_END();
387 }
388 }
389 return VINF_SUCCESS;
390}
391
392
393/* Opcode VEX.0F 0x00 - invalid */
394/* Opcode VEX.0F 0x01 - invalid */
395/* Opcode VEX.0F 0x02 - invalid */
396/* Opcode VEX.0F 0x03 - invalid */
397/* Opcode VEX.0F 0x04 - invalid */
398/* Opcode VEX.0F 0x05 - invalid */
399/* Opcode VEX.0F 0x06 - invalid */
400/* Opcode VEX.0F 0x07 - invalid */
401/* Opcode VEX.0F 0x08 - invalid */
402/* Opcode VEX.0F 0x09 - invalid */
403/* Opcode VEX.0F 0x0a - invalid */
404
405/** Opcode VEX.0F 0x0b. */
406FNIEMOP_DEF(iemOp_vud2)
407{
408 IEMOP_MNEMONIC(vud2, "vud2");
409 return IEMOP_RAISE_INVALID_OPCODE();
410}
411
412/* Opcode VEX.0F 0x0c - invalid */
413/* Opcode VEX.0F 0x0d - invalid */
414/* Opcode VEX.0F 0x0e - invalid */
415/* Opcode VEX.0F 0x0f - invalid */
416
417
418/**
419 * @opcode 0x10
420 * @oppfx none
421 * @opcpuid avx
422 * @opgroup og_avx_simdfp_datamove
423 * @opxcpttype 4UA
424 * @optest op1=1 op2=2 -> op1=2
425 * @optest op1=0 op2=-22 -> op1=-22
426 */
427FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
428{
429 IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
430 Assert(pVCpu->iem.s.uVexLength <= 1);
431 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
432 if (IEM_IS_MODRM_REG_MODE(bRm))
433 {
434 /*
435 * Register, register.
436 */
437 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
438 IEM_MC_BEGIN(0, 0);
439 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
440 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
441 if (pVCpu->iem.s.uVexLength == 0)
442 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
443 IEM_GET_MODRM_RM(pVCpu, bRm));
444 else
445 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
446 IEM_GET_MODRM_RM(pVCpu, bRm));
447 IEM_MC_ADVANCE_RIP();
448 IEM_MC_END();
449 }
450 else if (pVCpu->iem.s.uVexLength == 0)
451 {
452 /*
453 * 128-bit: Register, Memory
454 */
455 IEM_MC_BEGIN(0, 2);
456 IEM_MC_LOCAL(RTUINT128U, uSrc);
457 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
458
459 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
460 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
461 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
462 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
463
464 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
465 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
466
467 IEM_MC_ADVANCE_RIP();
468 IEM_MC_END();
469 }
470 else
471 {
472 /*
473 * 256-bit: Register, Memory
474 */
475 IEM_MC_BEGIN(0, 2);
476 IEM_MC_LOCAL(RTUINT256U, uSrc);
477 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
478
479 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
480 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
481 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
482 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
483
484 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
485 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
486
487 IEM_MC_ADVANCE_RIP();
488 IEM_MC_END();
489 }
490 return VINF_SUCCESS;
491}
492
493
494/**
495 * @opcode 0x10
496 * @oppfx 0x66
497 * @opcpuid avx
498 * @opgroup og_avx_simdfp_datamove
499 * @opxcpttype 4UA
500 * @optest op1=1 op2=2 -> op1=2
501 * @optest op1=0 op2=-22 -> op1=-22
502 */
503FNIEMOP_DEF(iemOp_vmovupd_Vpd_Wpd)
504{
505 IEMOP_MNEMONIC2(VEX_RM, VMOVUPD, vmovupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
506 Assert(pVCpu->iem.s.uVexLength <= 1);
507 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
508 if (IEM_IS_MODRM_REG_MODE(bRm))
509 {
510 /*
511 * Register, register.
512 */
513 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
514 IEM_MC_BEGIN(0, 0);
515 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
516 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
517 if (pVCpu->iem.s.uVexLength == 0)
518 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
519 IEM_GET_MODRM_RM(pVCpu, bRm));
520 else
521 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
522 IEM_GET_MODRM_RM(pVCpu, bRm));
523 IEM_MC_ADVANCE_RIP();
524 IEM_MC_END();
525 }
526 else if (pVCpu->iem.s.uVexLength == 0)
527 {
528 /*
529 * 128-bit: Memory, register.
530 */
531 IEM_MC_BEGIN(0, 2);
532 IEM_MC_LOCAL(RTUINT128U, uSrc);
533 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
534
535 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
536 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
537 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
538 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
539
540 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
541 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
542
543 IEM_MC_ADVANCE_RIP();
544 IEM_MC_END();
545 }
546 else
547 {
548 /*
549 * 256-bit: Memory, register.
550 */
551 IEM_MC_BEGIN(0, 2);
552 IEM_MC_LOCAL(RTUINT256U, uSrc);
553 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
554
555 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
556 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
557 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
558 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
559
560 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
561 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
562
563 IEM_MC_ADVANCE_RIP();
564 IEM_MC_END();
565 }
566 return VINF_SUCCESS;
567}
568
569
570FNIEMOP_DEF(iemOp_vmovss_Vss_Hss_Wss)
571{
572 Assert(pVCpu->iem.s.uVexLength <= 1);
573 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
574 if (IEM_IS_MODRM_REG_MODE(bRm))
575 {
576 /**
577 * @opcode 0x10
578 * @oppfx 0xf3
579 * @opcodesub 11 mr/reg
580 * @opcpuid avx
581 * @opgroup og_avx_simdfp_datamerge
582 * @opxcpttype 5
583 * @optest op1=1 op2=0 op3=2 -> op1=2
584 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
585 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
586 * @optest op1=3 op2=-2 op3=0x77 -> op1=-8589934473
587 * @note HssHi refers to bits 127:32.
588 */
589 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
590 IEMOP_HLP_DONE_VEX_DECODING();
591 IEM_MC_BEGIN(0, 0);
592
593 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
594 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
595 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
596 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
597 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
598 IEM_MC_ADVANCE_RIP();
599 IEM_MC_END();
600 }
601 else
602 {
603 /**
604 * @opdone
605 * @opcode 0x10
606 * @oppfx 0xf3
607 * @opcodesub !11 mr/reg
608 * @opcpuid avx
609 * @opgroup og_avx_simdfp_datamove
610 * @opxcpttype 5
611 * @opfunction iemOp_vmovss_Vss_Hss_Wss
612 * @optest op1=1 op2=2 -> op1=2
613 * @optest op1=0 op2=-22 -> op1=-22
614 */
615 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
616 IEM_MC_BEGIN(0, 2);
617 IEM_MC_LOCAL(uint32_t, uSrc);
618 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
619
620 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
621 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
622 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
623 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
624
625 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
626 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
627
628 IEM_MC_ADVANCE_RIP();
629 IEM_MC_END();
630 }
631
632 return VINF_SUCCESS;
633}
634
635
636FNIEMOP_DEF(iemOp_vmovsd_Vsd_Hsd_Wsd)
637{
638 Assert(pVCpu->iem.s.uVexLength <= 1);
639 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
640 if (IEM_IS_MODRM_REG_MODE(bRm))
641 {
642 /**
643 * @opcode 0x10
644 * @oppfx 0xf2
645 * @opcodesub 11 mr/reg
646 * @opcpuid avx
647 * @opgroup og_avx_simdfp_datamerge
648 * @opxcpttype 5
649 * @optest op1=1 op2=0 op3=2 -> op1=2
650 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
651 * @optest op1=3 op2=-1 op3=0x77 ->
652 * op1=0xffffffffffffffff0000000000000077
653 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077
654 */
655 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
656 IEMOP_HLP_DONE_VEX_DECODING();
657 IEM_MC_BEGIN(0, 0);
658
659 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
660 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
661 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
662 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
663 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
664 IEM_MC_ADVANCE_RIP();
665 IEM_MC_END();
666 }
667 else
668 {
669 /**
670 * @opdone
671 * @opcode 0x10
672 * @oppfx 0xf2
673 * @opcodesub !11 mr/reg
674 * @opcpuid avx
675 * @opgroup og_avx_simdfp_datamove
676 * @opxcpttype 5
677 * @opfunction iemOp_vmovsd_Vsd_Hsd_Wsd
678 * @optest op1=1 op2=2 -> op1=2
679 * @optest op1=0 op2=-22 -> op1=-22
680 */
681 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
682 IEM_MC_BEGIN(0, 2);
683 IEM_MC_LOCAL(uint64_t, uSrc);
684 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
685
686 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
687 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
688 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
689 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
690
691 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
692 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
693
694 IEM_MC_ADVANCE_RIP();
695 IEM_MC_END();
696 }
697
698 return VINF_SUCCESS;
699}
700
701
702/**
703 * @opcode 0x11
704 * @oppfx none
705 * @opcpuid avx
706 * @opgroup og_avx_simdfp_datamove
707 * @opxcpttype 4UA
708 * @optest op1=1 op2=2 -> op1=2
709 * @optest op1=0 op2=-22 -> op1=-22
710 */
711FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
712{
713 IEMOP_MNEMONIC2(VEX_MR, VMOVUPS, vmovups, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
714 Assert(pVCpu->iem.s.uVexLength <= 1);
715 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
716 if (IEM_IS_MODRM_REG_MODE(bRm))
717 {
718 /*
719 * Register, register.
720 */
721 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
722 IEM_MC_BEGIN(0, 0);
723 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
724 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
725 if (pVCpu->iem.s.uVexLength == 0)
726 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
727 IEM_GET_MODRM_REG(pVCpu, bRm));
728 else
729 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
730 IEM_GET_MODRM_REG(pVCpu, bRm));
731 IEM_MC_ADVANCE_RIP();
732 IEM_MC_END();
733 }
734 else if (pVCpu->iem.s.uVexLength == 0)
735 {
736 /*
737 * 128-bit: Memory, register.
738 */
739 IEM_MC_BEGIN(0, 2);
740 IEM_MC_LOCAL(RTUINT128U, uSrc);
741 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
742
743 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
744 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
745 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
746 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
747
748 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
749 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
750
751 IEM_MC_ADVANCE_RIP();
752 IEM_MC_END();
753 }
754 else
755 {
756 /*
757 * 256-bit: Memory, register.
758 */
759 IEM_MC_BEGIN(0, 2);
760 IEM_MC_LOCAL(RTUINT256U, uSrc);
761 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
762
763 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
764 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
765 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
766 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
767
768 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
769 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
770
771 IEM_MC_ADVANCE_RIP();
772 IEM_MC_END();
773 }
774 return VINF_SUCCESS;
775}
776
777
778/**
779 * @opcode 0x11
780 * @oppfx 0x66
781 * @opcpuid avx
782 * @opgroup og_avx_simdfp_datamove
783 * @opxcpttype 4UA
784 * @optest op1=1 op2=2 -> op1=2
785 * @optest op1=0 op2=-22 -> op1=-22
786 */
787FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
788{
789 IEMOP_MNEMONIC2(VEX_MR, VMOVUPD, vmovupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
790 Assert(pVCpu->iem.s.uVexLength <= 1);
791 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
792 if (IEM_IS_MODRM_REG_MODE(bRm))
793 {
794 /*
795 * Register, register.
796 */
797 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
798 IEM_MC_BEGIN(0, 0);
799 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
800 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
801 if (pVCpu->iem.s.uVexLength == 0)
802 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
803 IEM_GET_MODRM_REG(pVCpu, bRm));
804 else
805 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
806 IEM_GET_MODRM_REG(pVCpu, bRm));
807 IEM_MC_ADVANCE_RIP();
808 IEM_MC_END();
809 }
810 else if (pVCpu->iem.s.uVexLength == 0)
811 {
812 /*
813 * 128-bit: Memory, register.
814 */
815 IEM_MC_BEGIN(0, 2);
816 IEM_MC_LOCAL(RTUINT128U, uSrc);
817 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
818
819 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
820 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
821 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
822 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
823
824 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
825 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
826
827 IEM_MC_ADVANCE_RIP();
828 IEM_MC_END();
829 }
830 else
831 {
832 /*
833 * 256-bit: Memory, register.
834 */
835 IEM_MC_BEGIN(0, 2);
836 IEM_MC_LOCAL(RTUINT256U, uSrc);
837 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
838
839 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
840 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
841 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
842 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
843
844 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
845 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
846
847 IEM_MC_ADVANCE_RIP();
848 IEM_MC_END();
849 }
850 return VINF_SUCCESS;
851}
852
853
854FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
855{
856 Assert(pVCpu->iem.s.uVexLength <= 1);
857 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
858 if (IEM_IS_MODRM_REG_MODE(bRm))
859 {
860 /**
861 * @opcode 0x11
862 * @oppfx 0xf3
863 * @opcodesub 11 mr/reg
864 * @opcpuid avx
865 * @opgroup og_avx_simdfp_datamerge
866 * @opxcpttype 5
867 * @optest op1=1 op2=0 op3=2 -> op1=2
868 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
869 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
870 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077
871 */
872 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
873 IEMOP_HLP_DONE_VEX_DECODING();
874 IEM_MC_BEGIN(0, 0);
875
876 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
877 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
878 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
879 IEM_GET_MODRM_REG(pVCpu, bRm),
880 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
881 IEM_MC_ADVANCE_RIP();
882 IEM_MC_END();
883 }
884 else
885 {
886 /**
887 * @opdone
888 * @opcode 0x11
889 * @oppfx 0xf3
890 * @opcodesub !11 mr/reg
891 * @opcpuid avx
892 * @opgroup og_avx_simdfp_datamove
893 * @opxcpttype 5
894 * @opfunction iemOp_vmovss_Vss_Hss_Wss
895 * @optest op1=1 op2=2 -> op1=2
896 * @optest op1=0 op2=-22 -> op1=-22
897 */
898 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
899 IEM_MC_BEGIN(0, 2);
900 IEM_MC_LOCAL(uint32_t, uSrc);
901 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
902
903 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
904 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
905 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
906 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
907
908 IEM_MC_FETCH_YREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
909 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
910
911 IEM_MC_ADVANCE_RIP();
912 IEM_MC_END();
913 }
914
915 return VINF_SUCCESS;
916}
917
918
919FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hsd_Vsd)
920{
921 Assert(pVCpu->iem.s.uVexLength <= 1);
922 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
923 if (IEM_IS_MODRM_REG_MODE(bRm))
924 {
925 /**
926 * @opcode 0x11
927 * @oppfx 0xf2
928 * @opcodesub 11 mr/reg
929 * @opcpuid avx
930 * @opgroup og_avx_simdfp_datamerge
931 * @opxcpttype 5
932 * @optest op1=1 op2=0 op3=2 -> op1=2
933 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
934 * @optest op1=3 op2=-1 op3=0x77 ->
935 * op1=0xffffffffffffffff0000000000000077
936 * @optest op2=0x42 op3=0x77 -> op1=0x420000000000000077
937 */
938 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
939 IEMOP_HLP_DONE_VEX_DECODING();
940 IEM_MC_BEGIN(0, 0);
941
942 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
943 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
944 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
945 IEM_GET_MODRM_REG(pVCpu, bRm),
946 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
947 IEM_MC_ADVANCE_RIP();
948 IEM_MC_END();
949 }
950 else
951 {
952 /**
953 * @opdone
954 * @opcode 0x11
955 * @oppfx 0xf2
956 * @opcodesub !11 mr/reg
957 * @opcpuid avx
958 * @opgroup og_avx_simdfp_datamove
959 * @opxcpttype 5
960 * @opfunction iemOp_vmovsd_Wsd_Hsd_Vsd
961 * @optest op1=1 op2=2 -> op1=2
962 * @optest op1=0 op2=-22 -> op1=-22
963 */
964 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
965 IEM_MC_BEGIN(0, 2);
966 IEM_MC_LOCAL(uint64_t, uSrc);
967 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
968
969 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
970 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
971 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
972 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
973
974 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
975 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
976
977 IEM_MC_ADVANCE_RIP();
978 IEM_MC_END();
979 }
980
981 return VINF_SUCCESS;
982}
983
984
985FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
986{
987 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
988 if (IEM_IS_MODRM_REG_MODE(bRm))
989 {
990 /**
991 * @opcode 0x12
992 * @opcodesub 11 mr/reg
993 * @oppfx none
994 * @opcpuid avx
995 * @opgroup og_avx_simdfp_datamerge
996 * @opxcpttype 7LZ
997 * @optest op2=0x2200220122022203
998 * op3=0x3304330533063307
999 * -> op1=0x22002201220222033304330533063307
1000 * @optest op2=-1 op3=-42 -> op1=-42
1001 * @note op3 and op2 are only the 8-byte high XMM register halfs.
1002 */
1003 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1004
1005 IEMOP_HLP_DONE_VEX_DECODING_L0();
1006 IEM_MC_BEGIN(0, 0);
1007
1008 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1009 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1010 IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1011 IEM_GET_MODRM_RM(pVCpu, bRm),
1012 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1013
1014 IEM_MC_ADVANCE_RIP();
1015 IEM_MC_END();
1016 }
1017 else
1018 {
1019 /**
1020 * @opdone
1021 * @opcode 0x12
1022 * @opcodesub !11 mr/reg
1023 * @oppfx none
1024 * @opcpuid avx
1025 * @opgroup og_avx_simdfp_datamove
1026 * @opxcpttype 5LZ
1027 * @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
1028 * @optest op1=1 op2=0 op3=0 -> op1=0
1029 * @optest op1=0 op2=-1 op3=-1 -> op1=-1
1030 * @optest op1=1 op2=2 op3=3 -> op1=0x20000000000000003
1031 * @optest op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042
1032 */
1033 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1034
1035 IEM_MC_BEGIN(0, 2);
1036 IEM_MC_LOCAL(uint64_t, uSrc);
1037 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1038
1039 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1040 IEMOP_HLP_DONE_VEX_DECODING_L0();
1041 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1042 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1043
1044 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1045 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1046 uSrc,
1047 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1048
1049 IEM_MC_ADVANCE_RIP();
1050 IEM_MC_END();
1051 }
1052 return VINF_SUCCESS;
1053}
1054
1055
1056/**
1057 * @opcode 0x12
1058 * @opcodesub !11 mr/reg
1059 * @oppfx 0x66
1060 * @opcpuid avx
1061 * @opgroup og_avx_pcksclr_datamerge
1062 * @opxcpttype 5LZ
1063 * @optest op2=0 op3=2 -> op1=2
1064 * @optest op2=0x22 op3=0x33 -> op1=0x220000000000000033
1065 * @optest op2=0xfffffff0fffffff1 op3=0xeeeeeee8eeeeeee9
1066 * -> op1=0xfffffff0fffffff1eeeeeee8eeeeeee9
1067 */
1068FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
1069{
1070 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1071 if (IEM_IS_MODRM_MEM_MODE(bRm))
1072 {
1073 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1074
1075 IEM_MC_BEGIN(0, 2);
1076 IEM_MC_LOCAL(uint64_t, uSrc);
1077 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1078
1079 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1080 IEMOP_HLP_DONE_VEX_DECODING_L0();
1081 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1082 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1083
1084 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1085 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1086 uSrc,
1087 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1088
1089 IEM_MC_ADVANCE_RIP();
1090 IEM_MC_END();
1091 return VINF_SUCCESS;
1092 }
1093
1094 /**
1095 * @opdone
1096 * @opmnemonic udvex660f12m3
1097 * @opcode 0x12
1098 * @opcodesub 11 mr/reg
1099 * @oppfx 0x66
1100 * @opunused immediate
1101 * @opcpuid avx
1102 * @optest ->
1103 */
1104 return IEMOP_RAISE_INVALID_OPCODE();
1105}
1106
1107
1108/**
1109 * @opcode 0x12
1110 * @oppfx 0xf3
1111 * @opcpuid avx
1112 * @opgroup og_avx_pcksclr_datamove
1113 * @opxcpttype 4
1114 * @optest vex.l==0 / op1=-1 op2=0xdddddddd00000002eeeeeeee00000001
1115 * -> op1=0x00000002000000020000000100000001
1116 * @optest vex.l==1 /
1117 * op2=0xbbbbbbbb00000004cccccccc00000003dddddddd00000002eeeeeeee00000001
1118 * -> op1=0x0000000400000004000000030000000300000002000000020000000100000001
1119 */
1120FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
1121{
1122 IEMOP_MNEMONIC2(VEX_RM, VMOVSLDUP, vmovsldup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1123 Assert(pVCpu->iem.s.uVexLength <= 1);
1124 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1125 if (IEM_IS_MODRM_REG_MODE(bRm))
1126 {
1127 /*
1128 * Register, register.
1129 */
1130 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1131 if (pVCpu->iem.s.uVexLength == 0)
1132 {
1133 IEM_MC_BEGIN(2, 0);
1134 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1135 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1136
1137 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1138 IEM_MC_PREPARE_AVX_USAGE();
1139
1140 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1141 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1142 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
1143 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1144
1145 IEM_MC_ADVANCE_RIP();
1146 IEM_MC_END();
1147 }
1148 else
1149 {
1150 IEM_MC_BEGIN(3, 0);
1151 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1152 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1153 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1154
1155 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1156 IEM_MC_PREPARE_AVX_USAGE();
1157 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rr, iYRegDst, iYRegSrc);
1158
1159 IEM_MC_ADVANCE_RIP();
1160 IEM_MC_END();
1161 }
1162 }
1163 else
1164 {
1165 /*
1166 * Register, memory.
1167 */
1168 if (pVCpu->iem.s.uVexLength == 0)
1169 {
1170 IEM_MC_BEGIN(2, 2);
1171 IEM_MC_LOCAL(RTUINT128U, uSrc);
1172 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1173 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1174 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1175
1176 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1177 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1178 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1179 IEM_MC_PREPARE_AVX_USAGE();
1180
1181 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1182 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1183 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
1184 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1185
1186 IEM_MC_ADVANCE_RIP();
1187 IEM_MC_END();
1188 }
1189 else
1190 {
1191 IEM_MC_BEGIN(3, 2);
1192 IEM_MC_LOCAL(RTUINT256U, uSrc);
1193 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1194 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1195 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1196 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1197
1198 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1199 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1200 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1201 IEM_MC_PREPARE_AVX_USAGE();
1202
1203 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1204 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rm, iYRegDst, puSrc);
1205
1206 IEM_MC_ADVANCE_RIP();
1207 IEM_MC_END();
1208 }
1209 }
1210 return VINF_SUCCESS;
1211}
1212
1213
1214/**
1215 * @opcode 0x12
1216 * @oppfx 0xf2
1217 * @opcpuid avx
1218 * @opgroup og_avx_pcksclr_datamove
1219 * @opxcpttype 5
1220 * @optest vex.l==0 / op2=0xddddddddeeeeeeee2222222211111111
1221 * -> op1=0x22222222111111112222222211111111
1222 * @optest vex.l==1 / op2=0xbbbbbbbbcccccccc4444444433333333ddddddddeeeeeeee2222222211111111
1223 * -> op1=0x4444444433333333444444443333333322222222111111112222222211111111
1224 */
1225FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
1226{
1227 IEMOP_MNEMONIC2(VEX_RM, VMOVDDUP, vmovddup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1228 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1229 if (IEM_IS_MODRM_REG_MODE(bRm))
1230 {
1231 /*
1232 * Register, register.
1233 */
1234 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1235 if (pVCpu->iem.s.uVexLength == 0)
1236 {
1237 IEM_MC_BEGIN(2, 0);
1238 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1239 IEM_MC_ARG(uint64_t, uSrc, 1);
1240
1241 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1242 IEM_MC_PREPARE_AVX_USAGE();
1243
1244 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1245 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1246 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
1247 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1248
1249 IEM_MC_ADVANCE_RIP();
1250 IEM_MC_END();
1251 }
1252 else
1253 {
1254 IEM_MC_BEGIN(3, 0);
1255 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1256 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1257 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1258
1259 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1260 IEM_MC_PREPARE_AVX_USAGE();
1261 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rr, iYRegDst, iYRegSrc);
1262
1263 IEM_MC_ADVANCE_RIP();
1264 IEM_MC_END();
1265 }
1266 }
1267 else
1268 {
1269 /*
1270 * Register, memory.
1271 */
1272 if (pVCpu->iem.s.uVexLength == 0)
1273 {
1274 IEM_MC_BEGIN(2, 2);
1275 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1276 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1277 IEM_MC_ARG(uint64_t, uSrc, 1);
1278
1279 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1280 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1281 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1282 IEM_MC_PREPARE_AVX_USAGE();
1283
1284 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1285 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1286 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
1287 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1288
1289 IEM_MC_ADVANCE_RIP();
1290 IEM_MC_END();
1291 }
1292 else
1293 {
1294 IEM_MC_BEGIN(3, 2);
1295 IEM_MC_LOCAL(RTUINT256U, uSrc);
1296 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1297 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1298 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1299 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1300
1301 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1302 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1303 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1304 IEM_MC_PREPARE_AVX_USAGE();
1305
1306 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1307 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rm, iYRegDst, puSrc);
1308
1309 IEM_MC_ADVANCE_RIP();
1310 IEM_MC_END();
1311 }
1312 }
1313 return VINF_SUCCESS;
1314}
1315
1316
1317/**
1318 * @opcode 0x13
1319 * @opcodesub !11 mr/reg
1320 * @oppfx none
1321 * @opcpuid avx
1322 * @opgroup og_avx_simdfp_datamove
1323 * @opxcpttype 5
1324 * @optest op1=1 op2=2 -> op1=2
1325 * @optest op1=0 op2=-42 -> op1=-42
1326 */
1327FNIEMOP_DEF(iemOp_vmovlps_Mq_Vq)
1328{
1329 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1330 if (IEM_IS_MODRM_MEM_MODE(bRm))
1331 {
1332 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPS, vmovlps, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1333
1334 IEM_MC_BEGIN(0, 2);
1335 IEM_MC_LOCAL(uint64_t, uSrc);
1336 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1337
1338 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1339 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1340 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1341 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1342
1343 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1344 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1345
1346 IEM_MC_ADVANCE_RIP();
1347 IEM_MC_END();
1348 return VINF_SUCCESS;
1349 }
1350
1351 /**
1352 * @opdone
1353 * @opmnemonic udvex0f13m3
1354 * @opcode 0x13
1355 * @opcodesub 11 mr/reg
1356 * @oppfx none
1357 * @opunused immediate
1358 * @opcpuid avx
1359 * @optest ->
1360 */
1361 return IEMOP_RAISE_INVALID_OPCODE();
1362}
1363
1364
1365/**
1366 * @opcode 0x13
1367 * @opcodesub !11 mr/reg
1368 * @oppfx 0x66
1369 * @opcpuid avx
1370 * @opgroup og_avx_pcksclr_datamove
1371 * @opxcpttype 5
1372 * @optest op1=1 op2=2 -> op1=2
1373 * @optest op1=0 op2=-42 -> op1=-42
1374 */
1375FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
1376{
1377 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1378 if (IEM_IS_MODRM_MEM_MODE(bRm))
1379 {
1380 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPD, vmovlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1381 IEM_MC_BEGIN(0, 2);
1382 IEM_MC_LOCAL(uint64_t, uSrc);
1383 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1384
1385 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1386 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1387 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1388 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1389
1390 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1391 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1392
1393 IEM_MC_ADVANCE_RIP();
1394 IEM_MC_END();
1395 return VINF_SUCCESS;
1396 }
1397
1398 /**
1399 * @opdone
1400 * @opmnemonic udvex660f13m3
1401 * @opcode 0x13
1402 * @opcodesub 11 mr/reg
1403 * @oppfx 0x66
1404 * @opunused immediate
1405 * @opcpuid avx
1406 * @optest ->
1407 */
1408 return IEMOP_RAISE_INVALID_OPCODE();
1409}
1410
1411/* Opcode VEX.F3.0F 0x13 - invalid */
1412/* Opcode VEX.F2.0F 0x13 - invalid */
1413
1414/** Opcode VEX.0F 0x14 - vunpcklps Vx, Hx, Wx*/
1415FNIEMOP_DEF(iemOp_vunpcklps_Vx_Hx_Wx)
1416{
1417 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPS, vunpcklps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1418 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklps);
1419 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1420}
1421
1422
1423/** Opcode VEX.66.0F 0x14 - vunpcklpd Vx,Hx,Wx */
1424FNIEMOP_DEF(iemOp_vunpcklpd_Vx_Hx_Wx)
1425{
1426 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPD, vunpcklpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1427 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklpd);
1428 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1429}
1430
1431
1432/* Opcode VEX.F3.0F 0x14 - invalid */
1433/* Opcode VEX.F2.0F 0x14 - invalid */
1434
1435
1436/** Opcode VEX.0F 0x15 - vunpckhps Vx, Hx, Wx */
1437FNIEMOP_DEF(iemOp_vunpckhps_Vx_Hx_Wx)
1438{
1439 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPS, vunpckhps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1440 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhps);
1441 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1442}
1443
1444
1445/** Opcode VEX.66.0F 0x15 - vunpckhpd Vx,Hx,Wx */
1446FNIEMOP_DEF(iemOp_vunpckhpd_Vx_Hx_Wx)
1447{
1448 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPD, vunpckhpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
1449 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhpd);
1450 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1451}
1452
1453
1454/* Opcode VEX.F3.0F 0x15 - invalid */
1455/* Opcode VEX.F2.0F 0x15 - invalid */
1456
1457
1458FNIEMOP_DEF(iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq)
1459{
1460 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1461 if (IEM_IS_MODRM_REG_MODE(bRm))
1462 {
1463 /**
1464 * @opcode 0x16
1465 * @opcodesub 11 mr/reg
1466 * @oppfx none
1467 * @opcpuid avx
1468 * @opgroup og_avx_simdfp_datamerge
1469 * @opxcpttype 7LZ
1470 */
1471 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVLHPS, vmovlhps, Vq_WO, Hq, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1472
1473 IEMOP_HLP_DONE_VEX_DECODING_L0();
1474 IEM_MC_BEGIN(0, 0);
1475
1476 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1477 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1478 IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1479 IEM_GET_MODRM_RM(pVCpu, bRm),
1480 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1481
1482 IEM_MC_ADVANCE_RIP();
1483 IEM_MC_END();
1484 }
1485 else
1486 {
1487 /**
1488 * @opdone
1489 * @opcode 0x16
1490 * @opcodesub !11 mr/reg
1491 * @oppfx none
1492 * @opcpuid avx
1493 * @opgroup og_avx_simdfp_datamove
1494 * @opxcpttype 5LZ
1495 * @opfunction iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq
1496 */
1497 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPS, vmovhps, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1498
1499 IEM_MC_BEGIN(0, 2);
1500 IEM_MC_LOCAL(uint64_t, uSrc);
1501 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1502
1503 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1504 IEMOP_HLP_DONE_VEX_DECODING_L0();
1505 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1506 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1507
1508 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1509 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1510 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1511 uSrc);
1512
1513 IEM_MC_ADVANCE_RIP();
1514 IEM_MC_END();
1515 }
1516 return VINF_SUCCESS;
1517}
1518
1519
1520/**
1521 * @opcode 0x16
1522 * @opcodesub !11 mr/reg
1523 * @oppfx 0x66
1524 * @opcpuid avx
1525 * @opgroup og_avx_pcksclr_datamerge
1526 * @opxcpttype 5LZ
1527 */
1528FNIEMOP_DEF(iemOp_vmovhpd_Vdq_Hq_Mq)
1529{
1530 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1531 if (IEM_IS_MODRM_MEM_MODE(bRm))
1532 {
1533 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPD, vmovhpd, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1534
1535 IEM_MC_BEGIN(0, 2);
1536 IEM_MC_LOCAL(uint64_t, uSrc);
1537 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1538
1539 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1540 IEMOP_HLP_DONE_VEX_DECODING_L0();
1541 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1542 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1543
1544 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1545 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1546 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1547 uSrc);
1548
1549 IEM_MC_ADVANCE_RIP();
1550 IEM_MC_END();
1551 return VINF_SUCCESS;
1552 }
1553
1554 /**
1555 * @opdone
1556 * @opmnemonic udvex660f16m3
1557 * @opcode 0x12
1558 * @opcodesub 11 mr/reg
1559 * @oppfx 0x66
1560 * @opunused immediate
1561 * @opcpuid avx
1562 * @optest ->
1563 */
1564 return IEMOP_RAISE_INVALID_OPCODE();
1565}
1566
1567
1568/** Opcode VEX.F3.0F 0x16 - vmovshdup Vx, Wx */
1569/**
1570 * @opcode 0x16
1571 * @oppfx 0xf3
1572 * @opcpuid avx
1573 * @opgroup og_avx_pcksclr_datamove
1574 * @opxcpttype 4
1575 */
1576FNIEMOP_DEF(iemOp_vmovshdup_Vx_Wx)
1577{
1578 IEMOP_MNEMONIC2(VEX_RM, VMOVSHDUP, vmovshdup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1579 Assert(pVCpu->iem.s.uVexLength <= 1);
1580 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1581 if (IEM_IS_MODRM_REG_MODE(bRm))
1582 {
1583 /*
1584 * Register, register.
1585 */
1586 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1587 if (pVCpu->iem.s.uVexLength == 0)
1588 {
1589 IEM_MC_BEGIN(2, 0);
1590 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1591 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1592
1593 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1594 IEM_MC_PREPARE_AVX_USAGE();
1595
1596 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1597 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1598 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movshdup, puDst, puSrc);
1599 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1600
1601 IEM_MC_ADVANCE_RIP();
1602 IEM_MC_END();
1603 }
1604 else
1605 {
1606 IEM_MC_BEGIN(3, 0);
1607 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1608 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1609 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1610
1611 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1612 IEM_MC_PREPARE_AVX_USAGE();
1613 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovshdup_256_rr, iYRegDst, iYRegSrc);
1614
1615 IEM_MC_ADVANCE_RIP();
1616 IEM_MC_END();
1617 }
1618 }
1619 else
1620 {
1621 /*
1622 * Register, memory.
1623 */
1624 if (pVCpu->iem.s.uVexLength == 0)
1625 {
1626 IEM_MC_BEGIN(2, 2);
1627 IEM_MC_LOCAL(RTUINT128U, uSrc);
1628 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1629 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1630 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1631
1632 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1633 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1634 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1635 IEM_MC_PREPARE_AVX_USAGE();
1636
1637 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1638 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1639 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movshdup, puDst, puSrc);
1640 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1641
1642 IEM_MC_ADVANCE_RIP();
1643 IEM_MC_END();
1644 }
1645 else
1646 {
1647 IEM_MC_BEGIN(3, 2);
1648 IEM_MC_LOCAL(RTUINT256U, uSrc);
1649 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1650 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1651 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1652 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1653
1654 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1655 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1656 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1657 IEM_MC_PREPARE_AVX_USAGE();
1658
1659 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1660 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovshdup_256_rm, iYRegDst, puSrc);
1661
1662 IEM_MC_ADVANCE_RIP();
1663 IEM_MC_END();
1664 }
1665 }
1666 return VINF_SUCCESS;
1667}
1668
1669
1670/* Opcode VEX.F2.0F 0x16 - invalid */
1671
1672
1673/**
1674 * @opcode 0x17
1675 * @opcodesub !11 mr/reg
1676 * @oppfx none
1677 * @opcpuid avx
1678 * @opgroup og_avx_simdfp_datamove
1679 * @opxcpttype 5
1680 */
1681FNIEMOP_DEF(iemOp_vmovhps_Mq_Vq)
1682{
1683 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1684 if (IEM_IS_MODRM_MEM_MODE(bRm))
1685 {
1686 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPS, vmovhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1687
1688 IEM_MC_BEGIN(0, 2);
1689 IEM_MC_LOCAL(uint64_t, uSrc);
1690 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1691
1692 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1693 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1694 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1695 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1696
1697 IEM_MC_FETCH_YREG_2ND_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1698 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1699
1700 IEM_MC_ADVANCE_RIP();
1701 IEM_MC_END();
1702 return VINF_SUCCESS;
1703 }
1704
1705 /**
1706 * @opdone
1707 * @opmnemonic udvex0f17m3
1708 * @opcode 0x17
1709 * @opcodesub 11 mr/reg
1710 * @oppfx none
1711 * @opunused immediate
1712 * @opcpuid avx
1713 * @optest ->
1714 */
1715 return IEMOP_RAISE_INVALID_OPCODE();
1716}
1717
1718
1719/**
1720 * @opcode 0x17
1721 * @opcodesub !11 mr/reg
1722 * @oppfx 0x66
1723 * @opcpuid avx
1724 * @opgroup og_avx_pcksclr_datamove
1725 * @opxcpttype 5
1726 */
1727FNIEMOP_DEF(iemOp_vmovhpd_Mq_Vq)
1728{
1729 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1730 if (IEM_IS_MODRM_MEM_MODE(bRm))
1731 {
1732 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPD, vmovhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1733 IEM_MC_BEGIN(0, 2);
1734 IEM_MC_LOCAL(uint64_t, uSrc);
1735 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1736
1737 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1738 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1739 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1740 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1741
1742 IEM_MC_FETCH_YREG_2ND_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1743 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1744
1745 IEM_MC_ADVANCE_RIP();
1746 IEM_MC_END();
1747 return VINF_SUCCESS;
1748 }
1749
1750 /**
1751 * @opdone
1752 * @opmnemonic udvex660f17m3
1753 * @opcode 0x17
1754 * @opcodesub 11 mr/reg
1755 * @oppfx 0x66
1756 * @opunused immediate
1757 * @opcpuid avx
1758 * @optest ->
1759 */
1760 return IEMOP_RAISE_INVALID_OPCODE();
1761}
1762
1763
1764/* Opcode VEX.F3.0F 0x17 - invalid */
1765/* Opcode VEX.F2.0F 0x17 - invalid */
1766
1767
1768/* Opcode VEX.0F 0x18 - invalid */
1769/* Opcode VEX.0F 0x19 - invalid */
1770/* Opcode VEX.0F 0x1a - invalid */
1771/* Opcode VEX.0F 0x1b - invalid */
1772/* Opcode VEX.0F 0x1c - invalid */
1773/* Opcode VEX.0F 0x1d - invalid */
1774/* Opcode VEX.0F 0x1e - invalid */
1775/* Opcode VEX.0F 0x1f - invalid */
1776
1777/* Opcode VEX.0F 0x20 - invalid */
1778/* Opcode VEX.0F 0x21 - invalid */
1779/* Opcode VEX.0F 0x22 - invalid */
1780/* Opcode VEX.0F 0x23 - invalid */
1781/* Opcode VEX.0F 0x24 - invalid */
1782/* Opcode VEX.0F 0x25 - invalid */
1783/* Opcode VEX.0F 0x26 - invalid */
1784/* Opcode VEX.0F 0x27 - invalid */
1785
1786/**
1787 * @opcode 0x28
1788 * @oppfx none
1789 * @opcpuid avx
1790 * @opgroup og_avx_pcksclr_datamove
1791 * @opxcpttype 1
1792 * @optest op1=1 op2=2 -> op1=2
1793 * @optest op1=0 op2=-42 -> op1=-42
1794 * @note Almost identical to vmovapd.
1795 */
1796FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
1797{
1798 IEMOP_MNEMONIC2(VEX_RM, VMOVAPS, vmovaps, Vps_WO, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1799 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1800 Assert(pVCpu->iem.s.uVexLength <= 1);
1801 if (IEM_IS_MODRM_REG_MODE(bRm))
1802 {
1803 /*
1804 * Register, register.
1805 */
1806 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1807 IEM_MC_BEGIN(1, 0);
1808
1809 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1810 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1811 if (pVCpu->iem.s.uVexLength == 0)
1812 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1813 IEM_GET_MODRM_RM(pVCpu, bRm));
1814 else
1815 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1816 IEM_GET_MODRM_RM(pVCpu, bRm));
1817 IEM_MC_ADVANCE_RIP();
1818 IEM_MC_END();
1819 }
1820 else
1821 {
1822 /*
1823 * Register, memory.
1824 */
1825 if (pVCpu->iem.s.uVexLength == 0)
1826 {
1827 IEM_MC_BEGIN(0, 2);
1828 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1829 IEM_MC_LOCAL(RTUINT128U, uSrc);
1830
1831 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1832 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1833 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1834 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1835
1836 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1837 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1838
1839 IEM_MC_ADVANCE_RIP();
1840 IEM_MC_END();
1841 }
1842 else
1843 {
1844 IEM_MC_BEGIN(0, 2);
1845 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1846 IEM_MC_LOCAL(RTUINT256U, uSrc);
1847
1848 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1849 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1850 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1851 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1852
1853 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1854 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1855
1856 IEM_MC_ADVANCE_RIP();
1857 IEM_MC_END();
1858 }
1859 }
1860 return VINF_SUCCESS;
1861}
1862
1863
1864/**
1865 * @opcode 0x28
1866 * @oppfx 66
1867 * @opcpuid avx
1868 * @opgroup og_avx_pcksclr_datamove
1869 * @opxcpttype 1
1870 * @optest op1=1 op2=2 -> op1=2
1871 * @optest op1=0 op2=-42 -> op1=-42
1872 * @note Almost identical to vmovaps
1873 */
1874FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
1875{
1876 IEMOP_MNEMONIC2(VEX_RM, VMOVAPD, vmovapd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1877 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1878 Assert(pVCpu->iem.s.uVexLength <= 1);
1879 if (IEM_IS_MODRM_REG_MODE(bRm))
1880 {
1881 /*
1882 * Register, register.
1883 */
1884 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1885 IEM_MC_BEGIN(1, 0);
1886
1887 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1888 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1889 if (pVCpu->iem.s.uVexLength == 0)
1890 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1891 IEM_GET_MODRM_RM(pVCpu, bRm));
1892 else
1893 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1894 IEM_GET_MODRM_RM(pVCpu, bRm));
1895 IEM_MC_ADVANCE_RIP();
1896 IEM_MC_END();
1897 }
1898 else
1899 {
1900 /*
1901 * Register, memory.
1902 */
1903 if (pVCpu->iem.s.uVexLength == 0)
1904 {
1905 IEM_MC_BEGIN(0, 2);
1906 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1907 IEM_MC_LOCAL(RTUINT128U, uSrc);
1908
1909 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1910 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1911 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1912 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1913
1914 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1915 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1916
1917 IEM_MC_ADVANCE_RIP();
1918 IEM_MC_END();
1919 }
1920 else
1921 {
1922 IEM_MC_BEGIN(0, 2);
1923 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1924 IEM_MC_LOCAL(RTUINT256U, uSrc);
1925
1926 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1927 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1928 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1929 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1930
1931 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1932 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1933
1934 IEM_MC_ADVANCE_RIP();
1935 IEM_MC_END();
1936 }
1937 }
1938 return VINF_SUCCESS;
1939}
1940
1941/**
1942 * @opmnemonic udvexf30f28
1943 * @opcode 0x28
1944 * @oppfx 0xf3
1945 * @opunused vex.modrm
1946 * @opcpuid avx
1947 * @optest ->
1948 * @opdone
1949 */
1950
1951/**
1952 * @opmnemonic udvexf20f28
1953 * @opcode 0x28
1954 * @oppfx 0xf2
1955 * @opunused vex.modrm
1956 * @opcpuid avx
1957 * @optest ->
1958 * @opdone
1959 */
1960
1961/**
1962 * @opcode 0x29
1963 * @oppfx none
1964 * @opcpuid avx
1965 * @opgroup og_avx_pcksclr_datamove
1966 * @opxcpttype 1
1967 * @optest op1=1 op2=2 -> op1=2
1968 * @optest op1=0 op2=-42 -> op1=-42
1969 * @note Almost identical to vmovapd.
1970 */
1971FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
1972{
1973 IEMOP_MNEMONIC2(VEX_MR, VMOVAPS, vmovaps, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1974 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1975 Assert(pVCpu->iem.s.uVexLength <= 1);
1976 if (IEM_IS_MODRM_REG_MODE(bRm))
1977 {
1978 /*
1979 * Register, register.
1980 */
1981 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1982 IEM_MC_BEGIN(1, 0);
1983
1984 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1985 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1986 if (pVCpu->iem.s.uVexLength == 0)
1987 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
1988 IEM_GET_MODRM_REG(pVCpu, bRm));
1989 else
1990 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
1991 IEM_GET_MODRM_REG(pVCpu, bRm));
1992 IEM_MC_ADVANCE_RIP();
1993 IEM_MC_END();
1994 }
1995 else
1996 {
1997 /*
1998 * Register, memory.
1999 */
2000 if (pVCpu->iem.s.uVexLength == 0)
2001 {
2002 IEM_MC_BEGIN(0, 2);
2003 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2004 IEM_MC_LOCAL(RTUINT128U, uSrc);
2005
2006 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2007 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2008 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2009 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2010
2011 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2012 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2013
2014 IEM_MC_ADVANCE_RIP();
2015 IEM_MC_END();
2016 }
2017 else
2018 {
2019 IEM_MC_BEGIN(0, 2);
2020 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2021 IEM_MC_LOCAL(RTUINT256U, uSrc);
2022
2023 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2024 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2025 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2026 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2027
2028 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2029 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2030
2031 IEM_MC_ADVANCE_RIP();
2032 IEM_MC_END();
2033 }
2034 }
2035 return VINF_SUCCESS;
2036}
2037
2038/**
2039 * @opcode 0x29
2040 * @oppfx 66
2041 * @opcpuid avx
2042 * @opgroup og_avx_pcksclr_datamove
2043 * @opxcpttype 1
2044 * @optest op1=1 op2=2 -> op1=2
2045 * @optest op1=0 op2=-42 -> op1=-42
2046 * @note Almost identical to vmovaps
2047 */
2048FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
2049{
2050 IEMOP_MNEMONIC2(VEX_MR, VMOVAPD, vmovapd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2051 Assert(pVCpu->iem.s.uVexLength <= 1);
2052 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2053 if (IEM_IS_MODRM_REG_MODE(bRm))
2054 {
2055 /*
2056 * Register, register.
2057 */
2058 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2059 IEM_MC_BEGIN(1, 0);
2060
2061 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2062 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2063 if (pVCpu->iem.s.uVexLength == 0)
2064 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2065 IEM_GET_MODRM_REG(pVCpu, bRm));
2066 else
2067 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2068 IEM_GET_MODRM_REG(pVCpu, bRm));
2069 IEM_MC_ADVANCE_RIP();
2070 IEM_MC_END();
2071 }
2072 else
2073 {
2074 /*
2075 * Register, memory.
2076 */
2077 if (pVCpu->iem.s.uVexLength == 0)
2078 {
2079 IEM_MC_BEGIN(0, 2);
2080 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2081 IEM_MC_LOCAL(RTUINT128U, uSrc);
2082
2083 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2084 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2085 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2086 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2087
2088 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2089 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2090
2091 IEM_MC_ADVANCE_RIP();
2092 IEM_MC_END();
2093 }
2094 else
2095 {
2096 IEM_MC_BEGIN(0, 2);
2097 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2098 IEM_MC_LOCAL(RTUINT256U, uSrc);
2099
2100 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2101 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2102 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2103 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2104
2105 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2106 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2107
2108 IEM_MC_ADVANCE_RIP();
2109 IEM_MC_END();
2110 }
2111 }
2112 return VINF_SUCCESS;
2113}
2114
2115
2116/**
2117 * @opmnemonic udvexf30f29
2118 * @opcode 0x29
2119 * @oppfx 0xf3
2120 * @opunused vex.modrm
2121 * @opcpuid avx
2122 * @optest ->
2123 * @opdone
2124 */
2125
2126/**
2127 * @opmnemonic udvexf20f29
2128 * @opcode 0x29
2129 * @oppfx 0xf2
2130 * @opunused vex.modrm
2131 * @opcpuid avx
2132 * @optest ->
2133 * @opdone
2134 */
2135
2136
2137/** Opcode VEX.0F 0x2a - invalid */
2138/** Opcode VEX.66.0F 0x2a - invalid */
2139/** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
2140FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
2141/** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
2142FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
2143
2144
2145/**
2146 * @opcode 0x2b
2147 * @opcodesub !11 mr/reg
2148 * @oppfx none
2149 * @opcpuid avx
2150 * @opgroup og_avx_cachect
2151 * @opxcpttype 1
2152 * @optest op1=1 op2=2 -> op1=2
2153 * @optest op1=0 op2=-42 -> op1=-42
2154 * @note Identical implementation to vmovntpd
2155 */
2156FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
2157{
2158 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPS, vmovntps, Mps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2159 Assert(pVCpu->iem.s.uVexLength <= 1);
2160 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2161 if (IEM_IS_MODRM_MEM_MODE(bRm))
2162 {
2163 /*
2164 * memory, register.
2165 */
2166 if (pVCpu->iem.s.uVexLength == 0)
2167 {
2168 IEM_MC_BEGIN(0, 2);
2169 IEM_MC_LOCAL(RTUINT128U, uSrc);
2170 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2171
2172 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2173 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2174 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2175 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2176
2177 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2178 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2179
2180 IEM_MC_ADVANCE_RIP();
2181 IEM_MC_END();
2182 }
2183 else
2184 {
2185 IEM_MC_BEGIN(0, 2);
2186 IEM_MC_LOCAL(RTUINT256U, uSrc);
2187 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2188
2189 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2190 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2191 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2192 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2193
2194 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2195 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2196
2197 IEM_MC_ADVANCE_RIP();
2198 IEM_MC_END();
2199 }
2200 }
2201 /* The register, register encoding is invalid. */
2202 else
2203 return IEMOP_RAISE_INVALID_OPCODE();
2204 return VINF_SUCCESS;
2205}
2206
2207/**
2208 * @opcode 0x2b
2209 * @opcodesub !11 mr/reg
2210 * @oppfx 0x66
2211 * @opcpuid avx
2212 * @opgroup og_avx_cachect
2213 * @opxcpttype 1
2214 * @optest op1=1 op2=2 -> op1=2
2215 * @optest op1=0 op2=-42 -> op1=-42
2216 * @note Identical implementation to vmovntps
2217 */
2218FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
2219{
2220 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPD, vmovntpd, Mpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2221 Assert(pVCpu->iem.s.uVexLength <= 1);
2222 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2223 if (IEM_IS_MODRM_MEM_MODE(bRm))
2224 {
2225 /*
2226 * memory, register.
2227 */
2228 if (pVCpu->iem.s.uVexLength == 0)
2229 {
2230 IEM_MC_BEGIN(0, 2);
2231 IEM_MC_LOCAL(RTUINT128U, uSrc);
2232 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2233
2234 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2235 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2236 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2237 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2238
2239 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2240 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2241
2242 IEM_MC_ADVANCE_RIP();
2243 IEM_MC_END();
2244 }
2245 else
2246 {
2247 IEM_MC_BEGIN(0, 2);
2248 IEM_MC_LOCAL(RTUINT256U, uSrc);
2249 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2250
2251 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2252 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2253 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2254 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2255
2256 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2257 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2258
2259 IEM_MC_ADVANCE_RIP();
2260 IEM_MC_END();
2261 }
2262 }
2263 /* The register, register encoding is invalid. */
2264 else
2265 return IEMOP_RAISE_INVALID_OPCODE();
2266 return VINF_SUCCESS;
2267}
2268
2269/**
2270 * @opmnemonic udvexf30f2b
2271 * @opcode 0x2b
2272 * @oppfx 0xf3
2273 * @opunused vex.modrm
2274 * @opcpuid avx
2275 * @optest ->
2276 * @opdone
2277 */
2278
2279/**
2280 * @opmnemonic udvexf20f2b
2281 * @opcode 0x2b
2282 * @oppfx 0xf2
2283 * @opunused vex.modrm
2284 * @opcpuid avx
2285 * @optest ->
2286 * @opdone
2287 */
2288
2289
2290/* Opcode VEX.0F 0x2c - invalid */
2291/* Opcode VEX.66.0F 0x2c - invalid */
2292/** Opcode VEX.F3.0F 0x2c - vcvttss2si Gy, Wss */
2293FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
2294/** Opcode VEX.F2.0F 0x2c - vcvttsd2si Gy, Wsd */
2295FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
2296
2297/* Opcode VEX.0F 0x2d - invalid */
2298/* Opcode VEX.66.0F 0x2d - invalid */
2299/** Opcode VEX.F3.0F 0x2d - vcvtss2si Gy, Wss */
2300FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
2301/** Opcode VEX.F2.0F 0x2d - vcvtsd2si Gy, Wsd */
2302FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
2303
2304/** Opcode VEX.0F 0x2e - vucomiss Vss, Wss */
2305FNIEMOP_STUB(iemOp_vucomiss_Vss_Wss);
2306/** Opcode VEX.66.0F 0x2e - vucomisd Vsd, Wsd */
2307FNIEMOP_STUB(iemOp_vucomisd_Vsd_Wsd);
2308/* Opcode VEX.F3.0F 0x2e - invalid */
2309/* Opcode VEX.F2.0F 0x2e - invalid */
2310
2311/** Opcode VEX.0F 0x2f - vcomiss Vss, Wss */
2312FNIEMOP_STUB(iemOp_vcomiss_Vss_Wss);
2313/** Opcode VEX.66.0F 0x2f - vcomisd Vsd, Wsd */
2314FNIEMOP_STUB(iemOp_vcomisd_Vsd_Wsd);
2315/* Opcode VEX.F3.0F 0x2f - invalid */
2316/* Opcode VEX.F2.0F 0x2f - invalid */
2317
2318/* Opcode VEX.0F 0x30 - invalid */
2319/* Opcode VEX.0F 0x31 - invalid */
2320/* Opcode VEX.0F 0x32 - invalid */
2321/* Opcode VEX.0F 0x33 - invalid */
2322/* Opcode VEX.0F 0x34 - invalid */
2323/* Opcode VEX.0F 0x35 - invalid */
2324/* Opcode VEX.0F 0x36 - invalid */
2325/* Opcode VEX.0F 0x37 - invalid */
2326/* Opcode VEX.0F 0x38 - invalid */
2327/* Opcode VEX.0F 0x39 - invalid */
2328/* Opcode VEX.0F 0x3a - invalid */
2329/* Opcode VEX.0F 0x3b - invalid */
2330/* Opcode VEX.0F 0x3c - invalid */
2331/* Opcode VEX.0F 0x3d - invalid */
2332/* Opcode VEX.0F 0x3e - invalid */
2333/* Opcode VEX.0F 0x3f - invalid */
2334/* Opcode VEX.0F 0x40 - invalid */
2335/* Opcode VEX.0F 0x41 - invalid */
2336/* Opcode VEX.0F 0x42 - invalid */
2337/* Opcode VEX.0F 0x43 - invalid */
2338/* Opcode VEX.0F 0x44 - invalid */
2339/* Opcode VEX.0F 0x45 - invalid */
2340/* Opcode VEX.0F 0x46 - invalid */
2341/* Opcode VEX.0F 0x47 - invalid */
2342/* Opcode VEX.0F 0x48 - invalid */
2343/* Opcode VEX.0F 0x49 - invalid */
2344/* Opcode VEX.0F 0x4a - invalid */
2345/* Opcode VEX.0F 0x4b - invalid */
2346/* Opcode VEX.0F 0x4c - invalid */
2347/* Opcode VEX.0F 0x4d - invalid */
2348/* Opcode VEX.0F 0x4e - invalid */
2349/* Opcode VEX.0F 0x4f - invalid */
2350
2351
2352/** Opcode VEX.0F 0x50 - vmovmskps Gy, Ups */
2353FNIEMOP_DEF(iemOp_vmovmskps_Gy_Ups)
2354{
2355 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPS, vmovmskps, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2356 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2357 if (IEM_IS_MODRM_REG_MODE(bRm))
2358 {
2359 /*
2360 * Register, register.
2361 */
2362 if (pVCpu->iem.s.uVexLength == 0)
2363 {
2364 IEMOP_HLP_DONE_VEX_DECODING();
2365 IEM_MC_BEGIN(2, 1);
2366 IEM_MC_LOCAL(uint8_t, u8Dst);
2367 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2368 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2369 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2370 IEM_MC_PREPARE_AVX_USAGE();
2371 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2372 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskps_u128, iemAImpl_vmovmskps_u128_fallback),
2373 pu8Dst, puSrc);
2374 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2375 IEM_MC_ADVANCE_RIP();
2376 IEM_MC_END();
2377 }
2378 else
2379 {
2380 IEMOP_HLP_DONE_VEX_DECODING();
2381 IEM_MC_BEGIN(2, 2);
2382 IEM_MC_LOCAL(uint8_t, u8Dst);
2383 IEM_MC_LOCAL(RTUINT256U, uSrc);
2384 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2385 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2386
2387 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
2388 IEM_MC_PREPARE_AVX_USAGE();
2389 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2390 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskps_u256, iemAImpl_vmovmskps_u256_fallback),
2391 pu8Dst, puSrc);
2392 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2393 IEM_MC_ADVANCE_RIP();
2394 IEM_MC_END();
2395 }
2396 return VINF_SUCCESS;
2397 }
2398
2399 /* No memory operand. */
2400 return IEMOP_RAISE_INVALID_OPCODE();
2401}
2402
2403
2404/** Opcode VEX.66.0F 0x50 - vmovmskpd Gy,Upd */
2405FNIEMOP_DEF(iemOp_vmovmskpd_Gy_Upd)
2406{
2407{
2408 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPD, vmovmskpd, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2409 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2410 if (IEM_IS_MODRM_REG_MODE(bRm))
2411 {
2412 /*
2413 * Register, register.
2414 */
2415 if (pVCpu->iem.s.uVexLength == 0)
2416 {
2417 IEMOP_HLP_DONE_VEX_DECODING();
2418 IEM_MC_BEGIN(2, 1);
2419 IEM_MC_LOCAL(uint8_t, u8Dst);
2420 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2421 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2422 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2423 IEM_MC_PREPARE_AVX_USAGE();
2424 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2425 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskpd_u128, iemAImpl_vmovmskpd_u128_fallback),
2426 pu8Dst, puSrc);
2427 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2428 IEM_MC_ADVANCE_RIP();
2429 IEM_MC_END();
2430 }
2431 else
2432 {
2433 IEMOP_HLP_DONE_VEX_DECODING();
2434 IEM_MC_BEGIN(2, 2);
2435 IEM_MC_LOCAL(uint8_t, u8Dst);
2436 IEM_MC_LOCAL(RTUINT256U, uSrc);
2437 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2438 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2439
2440 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
2441 IEM_MC_PREPARE_AVX_USAGE();
2442 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2443 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskpd_u256, iemAImpl_vmovmskpd_u256_fallback),
2444 pu8Dst, puSrc);
2445 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2446 IEM_MC_ADVANCE_RIP();
2447 IEM_MC_END();
2448 }
2449 return VINF_SUCCESS;
2450 }
2451
2452 /* No memory operand. */
2453 return IEMOP_RAISE_INVALID_OPCODE();
2454}
2455}
2456
2457
2458/* Opcode VEX.F3.0F 0x50 - invalid */
2459/* Opcode VEX.F2.0F 0x50 - invalid */
2460
2461/** Opcode VEX.0F 0x51 - vsqrtps Vps, Wps */
2462FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
2463/** Opcode VEX.66.0F 0x51 - vsqrtpd Vpd, Wpd */
2464FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
2465/** Opcode VEX.F3.0F 0x51 - vsqrtss Vss, Hss, Wss */
2466FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
2467/** Opcode VEX.F2.0F 0x51 - vsqrtsd Vsd, Hsd, Wsd */
2468FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
2469
2470/** Opcode VEX.0F 0x52 - vrsqrtps Vps, Wps */
2471FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
2472/* Opcode VEX.66.0F 0x52 - invalid */
2473/** Opcode VEX.F3.0F 0x52 - vrsqrtss Vss, Hss, Wss */
2474FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
2475/* Opcode VEX.F2.0F 0x52 - invalid */
2476
2477/** Opcode VEX.0F 0x53 - vrcpps Vps, Wps */
2478FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
2479/* Opcode VEX.66.0F 0x53 - invalid */
2480/** Opcode VEX.F3.0F 0x53 - vrcpss Vss, Hss, Wss */
2481FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
2482/* Opcode VEX.F2.0F 0x53 - invalid */
2483
2484
2485/** Opcode VEX.0F 0x54 - vandps Vps, Hps, Wps */
2486FNIEMOP_DEF(iemOp_vandps_Vps_Hps_Wps)
2487{
2488 IEMOP_MNEMONIC3(VEX_RVM, VANDPS, vandps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2489 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2490 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2491}
2492
2493
2494/** Opcode VEX.66.0F 0x54 - vandpd Vpd, Hpd, Wpd */
2495FNIEMOP_DEF(iemOp_vandpd_Vpd_Hpd_Wpd)
2496{
2497 IEMOP_MNEMONIC3(VEX_RVM, VANDPD, vandpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2498 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2499 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2500}
2501
2502
2503/* Opcode VEX.F3.0F 0x54 - invalid */
2504/* Opcode VEX.F2.0F 0x54 - invalid */
2505
2506
2507/** Opcode VEX.0F 0x55 - vandnps Vps, Hps, Wps */
2508FNIEMOP_DEF(iemOp_vandnps_Vps_Hps_Wps)
2509{
2510 IEMOP_MNEMONIC3(VEX_RVM, VANDNPS, vandnps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2511 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2512 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2513}
2514
2515
2516/** Opcode VEX.66.0F 0x55 - vandnpd Vpd, Hpd, Wpd */
2517FNIEMOP_DEF(iemOp_vandnpd_Vpd_Hpd_Wpd)
2518{
2519 IEMOP_MNEMONIC3(VEX_RVM, VANDNPD, vandnpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2520 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2521 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2522}
2523
2524
2525/* Opcode VEX.F3.0F 0x55 - invalid */
2526/* Opcode VEX.F2.0F 0x55 - invalid */
2527
2528/** Opcode VEX.0F 0x56 - vorps Vps, Hps, Wps */
2529FNIEMOP_DEF(iemOp_vorps_Vps_Hps_Wps)
2530{
2531 IEMOP_MNEMONIC3(VEX_RVM, VORPS, vorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2532 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2533 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2534}
2535
2536
2537/** Opcode VEX.66.0F 0x56 - vorpd Vpd, Hpd, Wpd */
2538FNIEMOP_DEF(iemOp_vorpd_Vpd_Hpd_Wpd)
2539{
2540 IEMOP_MNEMONIC3(VEX_RVM, VORPD, vorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2541 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2542 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2543}
2544
2545
2546/* Opcode VEX.F3.0F 0x56 - invalid */
2547/* Opcode VEX.F2.0F 0x56 - invalid */
2548
2549
2550/** Opcode VEX.0F 0x57 - vxorps Vps, Hps, Wps */
2551FNIEMOP_DEF(iemOp_vxorps_Vps_Hps_Wps)
2552{
2553 IEMOP_MNEMONIC3(VEX_RVM, VXORPS, vxorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2554 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2555 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2556}
2557
2558
2559/** Opcode VEX.66.0F 0x57 - vxorpd Vpd, Hpd, Wpd */
2560FNIEMOP_DEF(iemOp_vxorpd_Vpd_Hpd_Wpd)
2561{
2562 IEMOP_MNEMONIC3(VEX_RVM, VXORPD, vxorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2563 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2564 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2565}
2566
2567
2568/* Opcode VEX.F3.0F 0x57 - invalid */
2569/* Opcode VEX.F2.0F 0x57 - invalid */
2570
2571/** Opcode VEX.0F 0x58 - vaddps Vps, Hps, Wps */
2572FNIEMOP_STUB(iemOp_vaddps_Vps_Hps_Wps);
2573/** Opcode VEX.66.0F 0x58 - vaddpd Vpd, Hpd, Wpd */
2574FNIEMOP_STUB(iemOp_vaddpd_Vpd_Hpd_Wpd);
2575/** Opcode VEX.F3.0F 0x58 - vaddss Vss, Hss, Wss */
2576FNIEMOP_STUB(iemOp_vaddss_Vss_Hss_Wss);
2577/** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
2578FNIEMOP_STUB(iemOp_vaddsd_Vsd_Hsd_Wsd);
2579
2580/** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
2581FNIEMOP_STUB(iemOp_vmulps_Vps_Hps_Wps);
2582/** Opcode VEX.66.0F 0x59 - vmulpd Vpd, Hpd, Wpd */
2583FNIEMOP_STUB(iemOp_vmulpd_Vpd_Hpd_Wpd);
2584/** Opcode VEX.F3.0F 0x59 - vmulss Vss, Hss, Wss */
2585FNIEMOP_STUB(iemOp_vmulss_Vss_Hss_Wss);
2586/** Opcode VEX.F2.0F 0x59 - vmulsd Vsd, Hsd, Wsd */
2587FNIEMOP_STUB(iemOp_vmulsd_Vsd_Hsd_Wsd);
2588
2589/** Opcode VEX.0F 0x5a - vcvtps2pd Vpd, Wps */
2590FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
2591/** Opcode VEX.66.0F 0x5a - vcvtpd2ps Vps, Wpd */
2592FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
2593/** Opcode VEX.F3.0F 0x5a - vcvtss2sd Vsd, Hx, Wss */
2594FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
2595/** Opcode VEX.F2.0F 0x5a - vcvtsd2ss Vss, Hx, Wsd */
2596FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
2597
2598/** Opcode VEX.0F 0x5b - vcvtdq2ps Vps, Wdq */
2599FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
2600/** Opcode VEX.66.0F 0x5b - vcvtps2dq Vdq, Wps */
2601FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
2602/** Opcode VEX.F3.0F 0x5b - vcvttps2dq Vdq, Wps */
2603FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
2604/* Opcode VEX.F2.0F 0x5b - invalid */
2605
2606/** Opcode VEX.0F 0x5c - vsubps Vps, Hps, Wps */
2607FNIEMOP_STUB(iemOp_vsubps_Vps_Hps_Wps);
2608/** Opcode VEX.66.0F 0x5c - vsubpd Vpd, Hpd, Wpd */
2609FNIEMOP_STUB(iemOp_vsubpd_Vpd_Hpd_Wpd);
2610/** Opcode VEX.F3.0F 0x5c - vsubss Vss, Hss, Wss */
2611FNIEMOP_STUB(iemOp_vsubss_Vss_Hss_Wss);
2612/** Opcode VEX.F2.0F 0x5c - vsubsd Vsd, Hsd, Wsd */
2613FNIEMOP_STUB(iemOp_vsubsd_Vsd_Hsd_Wsd);
2614
2615/** Opcode VEX.0F 0x5d - vminps Vps, Hps, Wps */
2616FNIEMOP_STUB(iemOp_vminps_Vps_Hps_Wps);
2617/** Opcode VEX.66.0F 0x5d - vminpd Vpd, Hpd, Wpd */
2618FNIEMOP_STUB(iemOp_vminpd_Vpd_Hpd_Wpd);
2619/** Opcode VEX.F3.0F 0x5d - vminss Vss, Hss, Wss */
2620FNIEMOP_STUB(iemOp_vminss_Vss_Hss_Wss);
2621/** Opcode VEX.F2.0F 0x5d - vminsd Vsd, Hsd, Wsd */
2622FNIEMOP_STUB(iemOp_vminsd_Vsd_Hsd_Wsd);
2623
2624/** Opcode VEX.0F 0x5e - vdivps Vps, Hps, Wps */
2625FNIEMOP_STUB(iemOp_vdivps_Vps_Hps_Wps);
2626/** Opcode VEX.66.0F 0x5e - vdivpd Vpd, Hpd, Wpd */
2627FNIEMOP_STUB(iemOp_vdivpd_Vpd_Hpd_Wpd);
2628/** Opcode VEX.F3.0F 0x5e - vdivss Vss, Hss, Wss */
2629FNIEMOP_STUB(iemOp_vdivss_Vss_Hss_Wss);
2630/** Opcode VEX.F2.0F 0x5e - vdivsd Vsd, Hsd, Wsd */
2631FNIEMOP_STUB(iemOp_vdivsd_Vsd_Hsd_Wsd);
2632
2633/** Opcode VEX.0F 0x5f - vmaxps Vps, Hps, Wps */
2634FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
2635/** Opcode VEX.66.0F 0x5f - vmaxpd Vpd, Hpd, Wpd */
2636FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
2637/** Opcode VEX.F3.0F 0x5f - vmaxss Vss, Hss, Wss */
2638FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
2639/** Opcode VEX.F2.0F 0x5f - vmaxsd Vsd, Hsd, Wsd */
2640FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
2641
2642
2643/* Opcode VEX.0F 0x60 - invalid */
2644
2645
2646/** Opcode VEX.66.0F 0x60 - vpunpcklbw Vx, Hx, Wx */
2647FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
2648{
2649 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLBW, vpunpcklbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2650 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklbw);
2651 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2652}
2653
2654
2655/* Opcode VEX.F3.0F 0x60 - invalid */
2656
2657
2658/* Opcode VEX.0F 0x61 - invalid */
2659
2660
2661/** Opcode VEX.66.0F 0x61 - vpunpcklwd Vx, Hx, Wx */
2662FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
2663{
2664 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLWD, vpunpcklwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2665 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklwd);
2666 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2667}
2668
2669
2670/* Opcode VEX.F3.0F 0x61 - invalid */
2671
2672
2673/* Opcode VEX.0F 0x62 - invalid */
2674
2675/** Opcode VEX.66.0F 0x62 - vpunpckldq Vx, Hx, Wx */
2676FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
2677{
2678 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLDQ, vpunpckldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2679 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckldq);
2680 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2681}
2682
2683
2684/* Opcode VEX.F3.0F 0x62 - invalid */
2685
2686
2687
2688/* Opcode VEX.0F 0x63 - invalid */
2689
2690
2691/** Opcode VEX.66.0F 0x63 - vpacksswb Vx, Hx, Wx */
2692FNIEMOP_DEF(iemOp_vpacksswb_Vx_Hx_Wx)
2693{
2694 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSWB, vpacksswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2695 IEMOPMEDIAOPTF3_INIT_VARS( vpacksswb);
2696 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2697}
2698
2699
2700/* Opcode VEX.F3.0F 0x63 - invalid */
2701
2702/* Opcode VEX.0F 0x64 - invalid */
2703
2704
2705/** Opcode VEX.66.0F 0x64 - vpcmpgtb Vx, Hx, Wx */
2706FNIEMOP_DEF(iemOp_vpcmpgtb_Vx_Hx_Wx)
2707{
2708 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTB, vpcmpgtb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2709 IEMOPMEDIAF3_INIT_VARS( vpcmpgtb);
2710 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2711}
2712
2713
2714/* Opcode VEX.F3.0F 0x64 - invalid */
2715
2716/* Opcode VEX.0F 0x65 - invalid */
2717
2718
2719/** Opcode VEX.66.0F 0x65 - vpcmpgtw Vx, Hx, Wx */
2720FNIEMOP_DEF(iemOp_vpcmpgtw_Vx_Hx_Wx)
2721{
2722 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTW, vpcmpgtw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2723 IEMOPMEDIAF3_INIT_VARS( vpcmpgtw);
2724 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2725}
2726
2727
2728/* Opcode VEX.F3.0F 0x65 - invalid */
2729
2730/* Opcode VEX.0F 0x66 - invalid */
2731
2732
2733/** Opcode VEX.66.0F 0x66 - vpcmpgtd Vx, Hx, Wx */
2734FNIEMOP_DEF(iemOp_vpcmpgtd_Vx_Hx_Wx)
2735{
2736 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTD, vpcmpgtd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2737 IEMOPMEDIAF3_INIT_VARS( vpcmpgtd);
2738 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2739}
2740
2741
2742/* Opcode VEX.F3.0F 0x66 - invalid */
2743
2744/* Opcode VEX.0F 0x67 - invalid */
2745
2746
2747/** Opcode VEX.66.0F 0x67 - vpackuswb Vx, Hx, W */
2748FNIEMOP_DEF(iemOp_vpackuswb_Vx_Hx_W)
2749{
2750 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSWB, vpackuswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2751 IEMOPMEDIAOPTF3_INIT_VARS( vpackuswb);
2752 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2753}
2754
2755
2756/* Opcode VEX.F3.0F 0x67 - invalid */
2757
2758
2759///**
2760// * Common worker for SSE2 instructions on the form:
2761// * pxxxx xmm1, xmm2/mem128
2762// *
2763// * The 2nd operand is the second half of a register, which in the memory case
2764// * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
2765// * where it may read the full 128 bits or only the upper 64 bits.
2766// *
2767// * Exceptions type 4.
2768// */
2769//FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
2770//{
2771// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2772// if (IEM_IS_MODRM_REG_MODE(bRm))
2773// {
2774// /*
2775// * Register, register.
2776// */
2777// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2778// IEM_MC_BEGIN(2, 0);
2779// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2780// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2781// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2782// IEM_MC_PREPARE_SSE_USAGE();
2783// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2784// IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2785// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2786// IEM_MC_ADVANCE_RIP();
2787// IEM_MC_END();
2788// }
2789// else
2790// {
2791// /*
2792// * Register, memory.
2793// */
2794// IEM_MC_BEGIN(2, 2);
2795// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2796// IEM_MC_LOCAL(RTUINT128U, uSrc);
2797// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2798// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2799//
2800// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2801// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2802// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2803// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
2804//
2805// IEM_MC_PREPARE_SSE_USAGE();
2806// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2807// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2808//
2809// IEM_MC_ADVANCE_RIP();
2810// IEM_MC_END();
2811// }
2812// return VINF_SUCCESS;
2813//}
2814
2815
2816/* Opcode VEX.0F 0x68 - invalid */
2817
2818/** Opcode VEX.66.0F 0x68 - vpunpckhbw Vx, Hx, Wx */
2819FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
2820{
2821 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHBW, vpunpckhbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2822 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhbw);
2823 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2824}
2825
2826
2827/* Opcode VEX.F3.0F 0x68 - invalid */
2828
2829
2830/* Opcode VEX.0F 0x69 - invalid */
2831
2832
2833/** Opcode VEX.66.0F 0x69 - vpunpckhwd Vx, Hx, Wx */
2834FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
2835{
2836 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHWD, vpunpckhwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2837 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhwd);
2838 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2839}
2840
2841
2842/* Opcode VEX.F3.0F 0x69 - invalid */
2843
2844
2845/* Opcode VEX.0F 0x6a - invalid */
2846
2847
2848/** Opcode VEX.66.0F 0x6a - vpunpckhdq Vx, Hx, W */
2849FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
2850{
2851 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHDQ, vpunpckhdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2852 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhdq);
2853 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2854}
2855
2856
2857/* Opcode VEX.F3.0F 0x6a - invalid */
2858
2859
2860/* Opcode VEX.0F 0x6b - invalid */
2861
2862
2863/** Opcode VEX.66.0F 0x6b - vpackssdw Vx, Hx, Wx */
2864FNIEMOP_DEF(iemOp_vpackssdw_Vx_Hx_Wx)
2865{
2866 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSDW, vpackssdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2867 IEMOPMEDIAOPTF3_INIT_VARS( vpackssdw);
2868 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2869}
2870
2871
2872/* Opcode VEX.F3.0F 0x6b - invalid */
2873
2874
2875/* Opcode VEX.0F 0x6c - invalid */
2876
2877
2878/** Opcode VEX.66.0F 0x6c - vpunpcklqdq Vx, Hx, Wx */
2879FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
2880{
2881 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLQDQ, vpunpcklqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2882 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklqdq);
2883 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2884}
2885
2886
2887/* Opcode VEX.F3.0F 0x6c - invalid */
2888/* Opcode VEX.F2.0F 0x6c - invalid */
2889
2890
2891/* Opcode VEX.0F 0x6d - invalid */
2892
2893
2894/** Opcode VEX.66.0F 0x6d - vpunpckhqdq Vx, Hx, W */
2895FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
2896{
2897 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHQDQ, vpunpckhqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
2898 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhqdq);
2899 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2900}
2901
2902
2903/* Opcode VEX.F3.0F 0x6d - invalid */
2904
2905
2906/* Opcode VEX.0F 0x6e - invalid */
2907
2908FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
2909{
2910 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2911 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2912 {
2913 /**
2914 * @opcode 0x6e
2915 * @opcodesub rex.w=1
2916 * @oppfx 0x66
2917 * @opcpuid avx
2918 * @opgroup og_avx_simdint_datamov
2919 * @opxcpttype 5
2920 * @optest 64-bit / op1=1 op2=2 -> op1=2
2921 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
2922 */
2923 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Eq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
2924 if (IEM_IS_MODRM_REG_MODE(bRm))
2925 {
2926 /* XMM, greg64 */
2927 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2928 IEM_MC_BEGIN(0, 1);
2929 IEM_MC_LOCAL(uint64_t, u64Tmp);
2930
2931 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2932 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2933
2934 IEM_MC_FETCH_GREG_U64(u64Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
2935 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
2936
2937 IEM_MC_ADVANCE_RIP();
2938 IEM_MC_END();
2939 }
2940 else
2941 {
2942 /* XMM, [mem64] */
2943 IEM_MC_BEGIN(0, 2);
2944 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2945 IEM_MC_LOCAL(uint64_t, u64Tmp);
2946
2947 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2948 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2949 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2950 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2951
2952 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2953 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
2954
2955 IEM_MC_ADVANCE_RIP();
2956 IEM_MC_END();
2957 }
2958 }
2959 else
2960 {
2961 /**
2962 * @opdone
2963 * @opcode 0x6e
2964 * @opcodesub rex.w=0
2965 * @oppfx 0x66
2966 * @opcpuid avx
2967 * @opgroup og_avx_simdint_datamov
2968 * @opxcpttype 5
2969 * @opfunction iemOp_vmovd_q_Vy_Ey
2970 * @optest op1=1 op2=2 -> op1=2
2971 * @optest op1=0 op2=-42 -> op1=-42
2972 */
2973 IEMOP_MNEMONIC2(VEX_RM, VMOVD, vmovd, Vd_WO, Ed, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
2974 if (IEM_IS_MODRM_REG_MODE(bRm))
2975 {
2976 /* XMM, greg32 */
2977 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2978 IEM_MC_BEGIN(0, 1);
2979 IEM_MC_LOCAL(uint32_t, u32Tmp);
2980
2981 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2982 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2983
2984 IEM_MC_FETCH_GREG_U32(u32Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
2985 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
2986
2987 IEM_MC_ADVANCE_RIP();
2988 IEM_MC_END();
2989 }
2990 else
2991 {
2992 /* XMM, [mem32] */
2993 IEM_MC_BEGIN(0, 2);
2994 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2995 IEM_MC_LOCAL(uint32_t, u32Tmp);
2996
2997 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2998 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2999 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3000 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3001
3002 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3003 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3004
3005 IEM_MC_ADVANCE_RIP();
3006 IEM_MC_END();
3007 }
3008 }
3009 return VINF_SUCCESS;
3010}
3011
3012
3013/* Opcode VEX.F3.0F 0x6e - invalid */
3014
3015
3016/* Opcode VEX.0F 0x6f - invalid */
3017
3018/**
3019 * @opcode 0x6f
3020 * @oppfx 0x66
3021 * @opcpuid avx
3022 * @opgroup og_avx_simdint_datamove
3023 * @opxcpttype 1
3024 * @optest op1=1 op2=2 -> op1=2
3025 * @optest op1=0 op2=-42 -> op1=-42
3026 */
3027FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
3028{
3029 IEMOP_MNEMONIC2(VEX_RM, VMOVDQA, vmovdqa, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3030 Assert(pVCpu->iem.s.uVexLength <= 1);
3031 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3032 if (IEM_IS_MODRM_REG_MODE(bRm))
3033 {
3034 /*
3035 * Register, register.
3036 */
3037 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3038 IEM_MC_BEGIN(0, 0);
3039
3040 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3041 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3042 if (pVCpu->iem.s.uVexLength == 0)
3043 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3044 IEM_GET_MODRM_RM(pVCpu, bRm));
3045 else
3046 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3047 IEM_GET_MODRM_RM(pVCpu, bRm));
3048 IEM_MC_ADVANCE_RIP();
3049 IEM_MC_END();
3050 }
3051 else if (pVCpu->iem.s.uVexLength == 0)
3052 {
3053 /*
3054 * Register, memory128.
3055 */
3056 IEM_MC_BEGIN(0, 2);
3057 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3058 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3059
3060 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3061 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3062 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3063 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3064
3065 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3066 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3067
3068 IEM_MC_ADVANCE_RIP();
3069 IEM_MC_END();
3070 }
3071 else
3072 {
3073 /*
3074 * Register, memory256.
3075 */
3076 IEM_MC_BEGIN(0, 2);
3077 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3078 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3079
3080 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3081 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3082 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3083 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3084
3085 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3086 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3087
3088 IEM_MC_ADVANCE_RIP();
3089 IEM_MC_END();
3090 }
3091 return VINF_SUCCESS;
3092}
3093
3094/**
3095 * @opcode 0x6f
3096 * @oppfx 0xf3
3097 * @opcpuid avx
3098 * @opgroup og_avx_simdint_datamove
3099 * @opxcpttype 4UA
3100 * @optest op1=1 op2=2 -> op1=2
3101 * @optest op1=0 op2=-42 -> op1=-42
3102 */
3103FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
3104{
3105 IEMOP_MNEMONIC2(VEX_RM, VMOVDQU, vmovdqu, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3106 Assert(pVCpu->iem.s.uVexLength <= 1);
3107 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3108 if (IEM_IS_MODRM_REG_MODE(bRm))
3109 {
3110 /*
3111 * Register, register.
3112 */
3113 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3114 IEM_MC_BEGIN(0, 0);
3115
3116 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3117 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3118 if (pVCpu->iem.s.uVexLength == 0)
3119 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3120 IEM_GET_MODRM_RM(pVCpu, bRm));
3121 else
3122 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3123 IEM_GET_MODRM_RM(pVCpu, bRm));
3124 IEM_MC_ADVANCE_RIP();
3125 IEM_MC_END();
3126 }
3127 else if (pVCpu->iem.s.uVexLength == 0)
3128 {
3129 /*
3130 * Register, memory128.
3131 */
3132 IEM_MC_BEGIN(0, 2);
3133 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3134 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3135
3136 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3137 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3138 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3139 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3140
3141 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3142 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3143
3144 IEM_MC_ADVANCE_RIP();
3145 IEM_MC_END();
3146 }
3147 else
3148 {
3149 /*
3150 * Register, memory256.
3151 */
3152 IEM_MC_BEGIN(0, 2);
3153 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3154 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3155
3156 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3157 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3158 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3159 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3160
3161 IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3162 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3163
3164 IEM_MC_ADVANCE_RIP();
3165 IEM_MC_END();
3166 }
3167 return VINF_SUCCESS;
3168}
3169
3170
3171/* Opcode VEX.0F 0x70 - invalid */
3172
3173
3174/**
3175 * Common worker for AVX/AVX2 instructions on the forms:
3176 * - vpxxx xmm0, xmm2/mem128, imm8
3177 * - vpxxx ymm0, ymm2/mem256, imm8
3178 *
3179 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
3180 */
3181FNIEMOP_DEF_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, PFNIEMAIMPLMEDIAPSHUFU128, pfnU128, PFNIEMAIMPLMEDIAPSHUFU256, pfnU256)
3182{
3183 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3184 if (IEM_IS_MODRM_REG_MODE(bRm))
3185 {
3186 /*
3187 * Register, register.
3188 */
3189 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3190 if (pVCpu->iem.s.uVexLength)
3191 {
3192 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3193 IEM_MC_BEGIN(3, 2);
3194 IEM_MC_LOCAL(RTUINT256U, uDst);
3195 IEM_MC_LOCAL(RTUINT256U, uSrc);
3196 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3197 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3198 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3199 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3200 IEM_MC_PREPARE_AVX_USAGE();
3201 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3202 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bEvilArg);
3203 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3204 IEM_MC_ADVANCE_RIP();
3205 IEM_MC_END();
3206 }
3207 else
3208 {
3209 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3210 IEM_MC_BEGIN(3, 0);
3211 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3212 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
3213 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3214 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3215 IEM_MC_PREPARE_AVX_USAGE();
3216 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3217 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3218 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bEvilArg);
3219 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3220 IEM_MC_ADVANCE_RIP();
3221 IEM_MC_END();
3222 }
3223 }
3224 else
3225 {
3226 /*
3227 * Register, memory.
3228 */
3229 if (pVCpu->iem.s.uVexLength)
3230 {
3231 IEM_MC_BEGIN(3, 3);
3232 IEM_MC_LOCAL(RTUINT256U, uDst);
3233 IEM_MC_LOCAL(RTUINT256U, uSrc);
3234 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3235 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3236 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3237
3238 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3239 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3240 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3241 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3242 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3243 IEM_MC_PREPARE_AVX_USAGE();
3244
3245 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3246 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bEvilArg);
3247 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3248
3249 IEM_MC_ADVANCE_RIP();
3250 IEM_MC_END();
3251 }
3252 else
3253 {
3254 IEM_MC_BEGIN(3, 1);
3255 IEM_MC_LOCAL(RTUINT128U, uSrc);
3256 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3257 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3258 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
3259
3260 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3261 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3262 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3263 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
3264 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
3265 IEM_MC_PREPARE_AVX_USAGE();
3266
3267 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3268 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3269 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bEvilArg);
3270 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3271
3272 IEM_MC_ADVANCE_RIP();
3273 IEM_MC_END();
3274 }
3275 }
3276 return VINF_SUCCESS;
3277}
3278
3279
3280/** Opcode VEX.66.0F 0x70 - vpshufd Vx, Wx, Ib */
3281FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
3282{
3283 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFD, vpshufd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3284 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufd_u128,
3285 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufd_u256, iemAImpl_vpshufd_u256_fallback));
3286
3287}
3288
3289
3290/** Opcode VEX.F3.0F 0x70 - vpshufhw Vx, Wx, Ib */
3291FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
3292{
3293 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFHW, vpshufhw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3294 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufhw_u128,
3295 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufhw_u256, iemAImpl_vpshufhw_u256_fallback));
3296
3297}
3298
3299
3300/** Opcode VEX.F2.0F 0x70 - vpshuflw Vx, Wx, Ib */
3301FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
3302{
3303 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFLW, vpshuflw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
3304 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshuflw_u128,
3305 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshuflw_u256, iemAImpl_vpshuflw_u256_fallback));
3306}
3307
3308
3309/* Opcode VEX.0F 0x71 11/2 - invalid. */
3310/** Opcode VEX.66.0F 0x71 11/2. */
3311FNIEMOP_STUB_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm);
3312
3313/* Opcode VEX.0F 0x71 11/4 - invalid */
3314/** Opcode VEX.66.0F 0x71 11/4. */
3315FNIEMOP_STUB_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm);
3316
3317/* Opcode VEX.0F 0x71 11/6 - invalid */
3318/** Opcode VEX.66.0F 0x71 11/6. */
3319FNIEMOP_STUB_1(iemOp_VGrp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm);
3320
3321
3322/**
3323 * VEX Group 12 jump table for register variant.
3324 */
3325IEM_STATIC const PFNIEMOPRM g_apfnVexGroup12RegReg[] =
3326{
3327 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3328 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3329 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3330 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3331 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3332 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3333 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3334 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3335};
3336AssertCompile(RT_ELEMENTS(g_apfnVexGroup12RegReg) == 8*4);
3337
3338
3339/** Opcode VEX.0F 0x71. */
3340FNIEMOP_DEF(iemOp_VGrp12)
3341{
3342 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3343 if (IEM_IS_MODRM_REG_MODE(bRm))
3344 /* register, register */
3345 return FNIEMOP_CALL_1(g_apfnVexGroup12RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3346 + pVCpu->iem.s.idxPrefix], bRm);
3347 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3348}
3349
3350
3351/* Opcode VEX.0F 0x72 11/2 - invalid. */
3352/** Opcode VEX.66.0F 0x72 11/2. */
3353FNIEMOP_STUB_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm);
3354
3355/* Opcode VEX.0F 0x72 11/4 - invalid. */
3356/** Opcode VEX.66.0F 0x72 11/4. */
3357FNIEMOP_STUB_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm);
3358
3359/* Opcode VEX.0F 0x72 11/6 - invalid. */
3360/** Opcode VEX.66.0F 0x72 11/6. */
3361FNIEMOP_STUB_1(iemOp_VGrp13_vpslld_Hx_Ux_Ib, uint8_t, bRm);
3362
3363
3364/**
3365 * Group 13 jump table for register variant.
3366 */
3367IEM_STATIC const PFNIEMOPRM g_apfnVexGroup13RegReg[] =
3368{
3369 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3370 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3371 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3372 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3373 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3374 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3375 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3376 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3377};
3378AssertCompile(RT_ELEMENTS(g_apfnVexGroup13RegReg) == 8*4);
3379
3380/** Opcode VEX.0F 0x72. */
3381FNIEMOP_DEF(iemOp_VGrp13)
3382{
3383 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3384 if (IEM_IS_MODRM_REG_MODE(bRm))
3385 /* register, register */
3386 return FNIEMOP_CALL_1(g_apfnVexGroup13RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3387 + pVCpu->iem.s.idxPrefix], bRm);
3388 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3389}
3390
3391
3392/* Opcode VEX.0F 0x73 11/2 - invalid. */
3393/** Opcode VEX.66.0F 0x73 11/2. */
3394FNIEMOP_STUB_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm);
3395
3396/** Opcode VEX.66.0F 0x73 11/3. */
3397FNIEMOP_STUB_1(iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm);
3398
3399/* Opcode VEX.0F 0x73 11/6 - invalid. */
3400/** Opcode VEX.66.0F 0x73 11/6. */
3401FNIEMOP_STUB_1(iemOp_VGrp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm);
3402
3403/** Opcode VEX.66.0F 0x73 11/7. */
3404FNIEMOP_STUB_1(iemOp_VGrp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm);
3405
3406/**
3407 * Group 14 jump table for register variant.
3408 */
3409IEM_STATIC const PFNIEMOPRM g_apfnVexGroup14RegReg[] =
3410{
3411 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3412 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3413 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3414 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3415 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3416 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3417 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3418 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3419};
3420AssertCompile(RT_ELEMENTS(g_apfnVexGroup14RegReg) == 8*4);
3421
3422
3423/** Opcode VEX.0F 0x73. */
3424FNIEMOP_DEF(iemOp_VGrp14)
3425{
3426 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3427 if (IEM_IS_MODRM_REG_MODE(bRm))
3428 /* register, register */
3429 return FNIEMOP_CALL_1(g_apfnVexGroup14RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3430 + pVCpu->iem.s.idxPrefix], bRm);
3431 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3432}
3433
3434
3435/* Opcode VEX.0F 0x74 - invalid */
3436
3437
3438/** Opcode VEX.66.0F 0x74 - vpcmpeqb Vx, Hx, Wx */
3439FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
3440{
3441 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQB, vpcmpeqb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3442 IEMOPMEDIAF3_INIT_VARS( vpcmpeqb);
3443 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3444}
3445
3446/* Opcode VEX.F3.0F 0x74 - invalid */
3447/* Opcode VEX.F2.0F 0x74 - invalid */
3448
3449
3450/* Opcode VEX.0F 0x75 - invalid */
3451
3452
3453/** Opcode VEX.66.0F 0x75 - vpcmpeqw Vx, Hx, Wx */
3454FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
3455{
3456 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQW, vpcmpeqw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3457 IEMOPMEDIAF3_INIT_VARS( vpcmpeqw);
3458 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3459}
3460
3461
3462/* Opcode VEX.F3.0F 0x75 - invalid */
3463/* Opcode VEX.F2.0F 0x75 - invalid */
3464
3465
3466/* Opcode VEX.0F 0x76 - invalid */
3467
3468
3469/** Opcode VEX.66.0F 0x76 - vpcmpeqd Vx, Hx, Wx */
3470FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
3471{
3472 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQD, vpcmpeqd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3473 IEMOPMEDIAF3_INIT_VARS( vpcmpeqd);
3474 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3475}
3476
3477
3478/* Opcode VEX.F3.0F 0x76 - invalid */
3479/* Opcode VEX.F2.0F 0x76 - invalid */
3480
3481
3482/** Opcode VEX.0F 0x77 - vzeroupperv vzeroallv */
3483FNIEMOP_STUB(iemOp_vzeroupperv__vzeroallv);
3484/* Opcode VEX.66.0F 0x77 - invalid */
3485/* Opcode VEX.F3.0F 0x77 - invalid */
3486/* Opcode VEX.F2.0F 0x77 - invalid */
3487
3488/* Opcode VEX.0F 0x78 - invalid */
3489/* Opcode VEX.66.0F 0x78 - invalid */
3490/* Opcode VEX.F3.0F 0x78 - invalid */
3491/* Opcode VEX.F2.0F 0x78 - invalid */
3492
3493/* Opcode VEX.0F 0x79 - invalid */
3494/* Opcode VEX.66.0F 0x79 - invalid */
3495/* Opcode VEX.F3.0F 0x79 - invalid */
3496/* Opcode VEX.F2.0F 0x79 - invalid */
3497
3498/* Opcode VEX.0F 0x7a - invalid */
3499/* Opcode VEX.66.0F 0x7a - invalid */
3500/* Opcode VEX.F3.0F 0x7a - invalid */
3501/* Opcode VEX.F2.0F 0x7a - invalid */
3502
3503/* Opcode VEX.0F 0x7b - invalid */
3504/* Opcode VEX.66.0F 0x7b - invalid */
3505/* Opcode VEX.F3.0F 0x7b - invalid */
3506/* Opcode VEX.F2.0F 0x7b - invalid */
3507
3508/* Opcode VEX.0F 0x7c - invalid */
3509/** Opcode VEX.66.0F 0x7c - vhaddpd Vpd, Hpd, Wpd */
3510FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
3511/* Opcode VEX.F3.0F 0x7c - invalid */
3512/** Opcode VEX.F2.0F 0x7c - vhaddps Vps, Hps, Wps */
3513FNIEMOP_STUB(iemOp_vhaddps_Vps_Hps_Wps);
3514
3515/* Opcode VEX.0F 0x7d - invalid */
3516/** Opcode VEX.66.0F 0x7d - vhsubpd Vpd, Hpd, Wpd */
3517FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
3518/* Opcode VEX.F3.0F 0x7d - invalid */
3519/** Opcode VEX.F2.0F 0x7d - vhsubps Vps, Hps, Wps */
3520FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
3521
3522
3523/* Opcode VEX.0F 0x7e - invalid */
3524
3525FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
3526{
3527 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3528 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3529 {
3530 /**
3531 * @opcode 0x7e
3532 * @opcodesub rex.w=1
3533 * @oppfx 0x66
3534 * @opcpuid avx
3535 * @opgroup og_avx_simdint_datamov
3536 * @opxcpttype 5
3537 * @optest 64-bit / op1=1 op2=2 -> op1=2
3538 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
3539 */
3540 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Eq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3541 if (IEM_IS_MODRM_REG_MODE(bRm))
3542 {
3543 /* greg64, XMM */
3544 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3545 IEM_MC_BEGIN(0, 1);
3546 IEM_MC_LOCAL(uint64_t, u64Tmp);
3547
3548 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3549 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3550
3551 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3552 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Tmp);
3553
3554 IEM_MC_ADVANCE_RIP();
3555 IEM_MC_END();
3556 }
3557 else
3558 {
3559 /* [mem64], XMM */
3560 IEM_MC_BEGIN(0, 2);
3561 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3562 IEM_MC_LOCAL(uint64_t, u64Tmp);
3563
3564 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3565 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3566 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3567 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3568
3569 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3570 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
3571
3572 IEM_MC_ADVANCE_RIP();
3573 IEM_MC_END();
3574 }
3575 }
3576 else
3577 {
3578 /**
3579 * @opdone
3580 * @opcode 0x7e
3581 * @opcodesub rex.w=0
3582 * @oppfx 0x66
3583 * @opcpuid avx
3584 * @opgroup og_avx_simdint_datamov
3585 * @opxcpttype 5
3586 * @opfunction iemOp_vmovd_q_Vy_Ey
3587 * @optest op1=1 op2=2 -> op1=2
3588 * @optest op1=0 op2=-42 -> op1=-42
3589 */
3590 IEMOP_MNEMONIC2(VEX_MR, VMOVD, vmovd, Ed_WO, Vd, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3591 if (IEM_IS_MODRM_REG_MODE(bRm))
3592 {
3593 /* greg32, XMM */
3594 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3595 IEM_MC_BEGIN(0, 1);
3596 IEM_MC_LOCAL(uint32_t, u32Tmp);
3597
3598 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3599 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3600
3601 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3602 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Tmp);
3603
3604 IEM_MC_ADVANCE_RIP();
3605 IEM_MC_END();
3606 }
3607 else
3608 {
3609 /* [mem32], XMM */
3610 IEM_MC_BEGIN(0, 2);
3611 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3612 IEM_MC_LOCAL(uint32_t, u32Tmp);
3613
3614 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3615 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3616 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3617 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3618
3619 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3620 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
3621
3622 IEM_MC_ADVANCE_RIP();
3623 IEM_MC_END();
3624 }
3625 }
3626 return VINF_SUCCESS;
3627}
3628
3629/**
3630 * @opcode 0x7e
3631 * @oppfx 0xf3
3632 * @opcpuid avx
3633 * @opgroup og_avx_pcksclr_datamove
3634 * @opxcpttype none
3635 * @optest op1=1 op2=2 -> op1=2
3636 * @optest op1=0 op2=-42 -> op1=-42
3637 */
3638FNIEMOP_DEF(iemOp_vmovq_Vq_Wq)
3639{
3640 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
3641 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3642 if (IEM_IS_MODRM_REG_MODE(bRm))
3643 {
3644 /*
3645 * Register, register.
3646 */
3647 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3648 IEM_MC_BEGIN(0, 0);
3649
3650 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3651 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3652
3653 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3654 IEM_GET_MODRM_RM(pVCpu, bRm));
3655 IEM_MC_ADVANCE_RIP();
3656 IEM_MC_END();
3657 }
3658 else
3659 {
3660 /*
3661 * Memory, register.
3662 */
3663 IEM_MC_BEGIN(0, 2);
3664 IEM_MC_LOCAL(uint64_t, uSrc);
3665 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3666
3667 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3668 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3669 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3670 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3671
3672 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3673 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
3674
3675 IEM_MC_ADVANCE_RIP();
3676 IEM_MC_END();
3677 }
3678 return VINF_SUCCESS;
3679
3680}
3681/* Opcode VEX.F2.0F 0x7e - invalid */
3682
3683
3684/* Opcode VEX.0F 0x7f - invalid */
3685
3686/**
3687 * @opcode 0x7f
3688 * @oppfx 0x66
3689 * @opcpuid avx
3690 * @opgroup og_avx_simdint_datamove
3691 * @opxcpttype 1
3692 * @optest op1=1 op2=2 -> op1=2
3693 * @optest op1=0 op2=-42 -> op1=-42
3694 */
3695FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
3696{
3697 IEMOP_MNEMONIC2(VEX_MR, VMOVDQA, vmovdqa, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3698 Assert(pVCpu->iem.s.uVexLength <= 1);
3699 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3700 if (IEM_IS_MODRM_REG_MODE(bRm))
3701 {
3702 /*
3703 * Register, register.
3704 */
3705 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3706 IEM_MC_BEGIN(0, 0);
3707
3708 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3709 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3710 if (pVCpu->iem.s.uVexLength == 0)
3711 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
3712 IEM_GET_MODRM_REG(pVCpu, bRm));
3713 else
3714 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
3715 IEM_GET_MODRM_REG(pVCpu, bRm));
3716 IEM_MC_ADVANCE_RIP();
3717 IEM_MC_END();
3718 }
3719 else if (pVCpu->iem.s.uVexLength == 0)
3720 {
3721 /*
3722 * Register, memory128.
3723 */
3724 IEM_MC_BEGIN(0, 2);
3725 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3726 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3727
3728 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3729 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3730 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3731 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3732
3733 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3734 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
3735
3736 IEM_MC_ADVANCE_RIP();
3737 IEM_MC_END();
3738 }
3739 else
3740 {
3741 /*
3742 * Register, memory256.
3743 */
3744 IEM_MC_BEGIN(0, 2);
3745 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3746 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3747
3748 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3749 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3750 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3751 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3752
3753 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3754 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
3755
3756 IEM_MC_ADVANCE_RIP();
3757 IEM_MC_END();
3758 }
3759 return VINF_SUCCESS;
3760}
3761
3762/**
3763 * @opcode 0x7f
3764 * @oppfx 0xf3
3765 * @opcpuid avx
3766 * @opgroup og_avx_simdint_datamove
3767 * @opxcpttype 4UA
3768 * @optest op1=1 op2=2 -> op1=2
3769 * @optest op1=0 op2=-42 -> op1=-42
3770 */
3771FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
3772{
3773 IEMOP_MNEMONIC2(VEX_MR, VMOVDQU, vmovdqu, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3774 Assert(pVCpu->iem.s.uVexLength <= 1);
3775 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3776 if (IEM_IS_MODRM_REG_MODE(bRm))
3777 {
3778 /*
3779 * Register, register.
3780 */
3781 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3782 IEM_MC_BEGIN(0, 0);
3783
3784 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3785 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3786 if (pVCpu->iem.s.uVexLength == 0)
3787 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
3788 IEM_GET_MODRM_REG(pVCpu, bRm));
3789 else
3790 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
3791 IEM_GET_MODRM_REG(pVCpu, bRm));
3792 IEM_MC_ADVANCE_RIP();
3793 IEM_MC_END();
3794 }
3795 else if (pVCpu->iem.s.uVexLength == 0)
3796 {
3797 /*
3798 * Register, memory128.
3799 */
3800 IEM_MC_BEGIN(0, 2);
3801 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3802 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3803
3804 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3805 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3806 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3807 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3808
3809 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3810 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
3811
3812 IEM_MC_ADVANCE_RIP();
3813 IEM_MC_END();
3814 }
3815 else
3816 {
3817 /*
3818 * Register, memory256.
3819 */
3820 IEM_MC_BEGIN(0, 2);
3821 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3822 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3823
3824 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3825 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
3826 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3827 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3828
3829 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3830 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
3831
3832 IEM_MC_ADVANCE_RIP();
3833 IEM_MC_END();
3834 }
3835 return VINF_SUCCESS;
3836}
3837
3838/* Opcode VEX.F2.0F 0x7f - invalid */
3839
3840
3841/* Opcode VEX.0F 0x80 - invalid */
3842/* Opcode VEX.0F 0x81 - invalid */
3843/* Opcode VEX.0F 0x82 - invalid */
3844/* Opcode VEX.0F 0x83 - invalid */
3845/* Opcode VEX.0F 0x84 - invalid */
3846/* Opcode VEX.0F 0x85 - invalid */
3847/* Opcode VEX.0F 0x86 - invalid */
3848/* Opcode VEX.0F 0x87 - invalid */
3849/* Opcode VEX.0F 0x88 - invalid */
3850/* Opcode VEX.0F 0x89 - invalid */
3851/* Opcode VEX.0F 0x8a - invalid */
3852/* Opcode VEX.0F 0x8b - invalid */
3853/* Opcode VEX.0F 0x8c - invalid */
3854/* Opcode VEX.0F 0x8d - invalid */
3855/* Opcode VEX.0F 0x8e - invalid */
3856/* Opcode VEX.0F 0x8f - invalid */
3857/* Opcode VEX.0F 0x90 - invalid */
3858/* Opcode VEX.0F 0x91 - invalid */
3859/* Opcode VEX.0F 0x92 - invalid */
3860/* Opcode VEX.0F 0x93 - invalid */
3861/* Opcode VEX.0F 0x94 - invalid */
3862/* Opcode VEX.0F 0x95 - invalid */
3863/* Opcode VEX.0F 0x96 - invalid */
3864/* Opcode VEX.0F 0x97 - invalid */
3865/* Opcode VEX.0F 0x98 - invalid */
3866/* Opcode VEX.0F 0x99 - invalid */
3867/* Opcode VEX.0F 0x9a - invalid */
3868/* Opcode VEX.0F 0x9b - invalid */
3869/* Opcode VEX.0F 0x9c - invalid */
3870/* Opcode VEX.0F 0x9d - invalid */
3871/* Opcode VEX.0F 0x9e - invalid */
3872/* Opcode VEX.0F 0x9f - invalid */
3873/* Opcode VEX.0F 0xa0 - invalid */
3874/* Opcode VEX.0F 0xa1 - invalid */
3875/* Opcode VEX.0F 0xa2 - invalid */
3876/* Opcode VEX.0F 0xa3 - invalid */
3877/* Opcode VEX.0F 0xa4 - invalid */
3878/* Opcode VEX.0F 0xa5 - invalid */
3879/* Opcode VEX.0F 0xa6 - invalid */
3880/* Opcode VEX.0F 0xa7 - invalid */
3881/* Opcode VEX.0F 0xa8 - invalid */
3882/* Opcode VEX.0F 0xa9 - invalid */
3883/* Opcode VEX.0F 0xaa - invalid */
3884/* Opcode VEX.0F 0xab - invalid */
3885/* Opcode VEX.0F 0xac - invalid */
3886/* Opcode VEX.0F 0xad - invalid */
3887
3888
3889/* Opcode VEX.0F 0xae mem/0 - invalid. */
3890/* Opcode VEX.0F 0xae mem/1 - invalid. */
3891
3892/**
3893 * @ opmaps grp15
3894 * @ opcode !11/2
3895 * @ oppfx none
3896 * @ opcpuid sse
3897 * @ opgroup og_sse_mxcsrsm
3898 * @ opxcpttype 5
3899 * @ optest op1=0 -> mxcsr=0
3900 * @ optest op1=0x2083 -> mxcsr=0x2083
3901 * @ optest op1=0xfffffffe -> value.xcpt=0xd
3902 * @ optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
3903 * @ optest op1=0x2083 cr0|=em -> value.xcpt=0x6
3904 * @ optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
3905 * @ optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
3906 * @ optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
3907 * @ optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
3908 * @ optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
3909 * @ optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
3910 */
3911FNIEMOP_STUB_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm);
3912//FNIEMOP_DEF_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm)
3913//{
3914// IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
3915// if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse)
3916// return IEMOP_RAISE_INVALID_OPCODE();
3917//
3918// IEM_MC_BEGIN(2, 0);
3919// IEM_MC_ARG(uint8_t, iEffSeg, 0);
3920// IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
3921// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
3922// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3923// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3924// IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
3925// IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
3926// IEM_MC_END();
3927// return VINF_SUCCESS;
3928//}
3929
3930
3931/**
3932 * @opmaps vexgrp15
3933 * @opcode !11/3
3934 * @oppfx none
3935 * @opcpuid avx
3936 * @opgroup og_avx_mxcsrsm
3937 * @opxcpttype 5
3938 * @optest mxcsr=0 -> op1=0
3939 * @optest mxcsr=0x2083 -> op1=0x2083
3940 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
3941 * @optest !amd / mxcsr=0x2085 cr0|=em -> op1=0x2085
3942 * @optest amd / mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
3943 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
3944 * @optest mxcsr=0x2087 cr4&~=osfxsr -> op1=0x2087
3945 * @optest mxcsr=0x208f cr4&~=osxsave -> value.xcpt=0x6
3946 * @optest mxcsr=0x2087 cr4&~=osfxsr,osxsave -> value.xcpt=0x6
3947 * @optest !amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x7
3948 * @optest amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
3949 * @optest !amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> op1=0x2089
3950 * @optest amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
3951 * @optest !amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x7
3952 * @optest amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
3953 * @optest !amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x7
3954 * @optest amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
3955 * @optest !amd / mxcsr=0x208c xcr0&~=all_avx -> value.xcpt=0x6
3956 * @optest amd / mxcsr=0x208c xcr0&~=all_avx -> op1=0x208c
3957 * @optest !amd / mxcsr=0x208d xcr0&~=all_avx_sse -> value.xcpt=0x6
3958 * @optest amd / mxcsr=0x208d xcr0&~=all_avx_sse -> op1=0x208d
3959 * @optest !amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x6
3960 * @optest amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x7
3961 * @optest mxcsr=0x2082 cr0|=ts cr4&~=osxsave -> value.xcpt=0x6
3962 * @optest mxcsr=0x2081 xcr0&~=all_avx cr0|=ts cr4&~=osxsave
3963 * -> value.xcpt=0x6
3964 * @remarks AMD Jaguar CPU (f0x16,m0,s1) \#UD when CR0.EM is set. It also
3965 * doesn't seem to check XCR0[2:1] != 11b. This does not match the
3966 * APMv4 rev 3.17 page 509.
3967 * @todo Test this instruction on AMD Ryzen.
3968 */
3969FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm)
3970{
3971 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
3972 IEM_MC_BEGIN(2, 0);
3973 IEM_MC_ARG(uint8_t, iEffSeg, 0);
3974 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
3975 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
3976 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3977 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3978 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
3979 IEM_MC_CALL_CIMPL_2(iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);
3980 IEM_MC_END();
3981 return VINF_SUCCESS;
3982}
3983
3984/* Opcode VEX.0F 0xae mem/4 - invalid. */
3985/* Opcode VEX.0F 0xae mem/5 - invalid. */
3986/* Opcode VEX.0F 0xae mem/6 - invalid. */
3987/* Opcode VEX.0F 0xae mem/7 - invalid. */
3988
3989/* Opcode VEX.0F 0xae 11b/0 - invalid. */
3990/* Opcode VEX.0F 0xae 11b/1 - invalid. */
3991/* Opcode VEX.0F 0xae 11b/2 - invalid. */
3992/* Opcode VEX.0F 0xae 11b/3 - invalid. */
3993/* Opcode VEX.0F 0xae 11b/4 - invalid. */
3994/* Opcode VEX.0F 0xae 11b/5 - invalid. */
3995/* Opcode VEX.0F 0xae 11b/6 - invalid. */
3996/* Opcode VEX.0F 0xae 11b/7 - invalid. */
3997
3998/**
3999 * Vex group 15 jump table for memory variant.
4000 */
4001IEM_STATIC const PFNIEMOPRM g_apfnVexGroup15MemReg[] =
4002{ /* pfx: none, 066h, 0f3h, 0f2h */
4003 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4004 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4005 /* /2 */ iemOp_VGrp15_vldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4006 /* /3 */ iemOp_VGrp15_vstmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4007 /* /4 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4008 /* /5 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4009 /* /6 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4010 /* /7 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4011};
4012AssertCompile(RT_ELEMENTS(g_apfnVexGroup15MemReg) == 8*4);
4013
4014
4015/** Opcode vex. 0xae. */
4016FNIEMOP_DEF(iemOp_VGrp15)
4017{
4018 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4019 if (IEM_IS_MODRM_REG_MODE(bRm))
4020 /* register, register */
4021 return FNIEMOP_CALL_1(iemOp_InvalidWithRM, bRm);
4022
4023 /* memory, register */
4024 return FNIEMOP_CALL_1(g_apfnVexGroup15MemReg[ IEM_GET_MODRM_REG_8(bRm) * 4
4025 + pVCpu->iem.s.idxPrefix], bRm);
4026}
4027
4028
4029/* Opcode VEX.0F 0xaf - invalid. */
4030
4031/* Opcode VEX.0F 0xb0 - invalid. */
4032/* Opcode VEX.0F 0xb1 - invalid. */
4033/* Opcode VEX.0F 0xb2 - invalid. */
4034/* Opcode VEX.0F 0xb2 - invalid. */
4035/* Opcode VEX.0F 0xb3 - invalid. */
4036/* Opcode VEX.0F 0xb4 - invalid. */
4037/* Opcode VEX.0F 0xb5 - invalid. */
4038/* Opcode VEX.0F 0xb6 - invalid. */
4039/* Opcode VEX.0F 0xb7 - invalid. */
4040/* Opcode VEX.0F 0xb8 - invalid. */
4041/* Opcode VEX.0F 0xb9 - invalid. */
4042/* Opcode VEX.0F 0xba - invalid. */
4043/* Opcode VEX.0F 0xbb - invalid. */
4044/* Opcode VEX.0F 0xbc - invalid. */
4045/* Opcode VEX.0F 0xbd - invalid. */
4046/* Opcode VEX.0F 0xbe - invalid. */
4047/* Opcode VEX.0F 0xbf - invalid. */
4048
4049/* Opcode VEX.0F 0xc0 - invalid. */
4050/* Opcode VEX.66.0F 0xc0 - invalid. */
4051/* Opcode VEX.F3.0F 0xc0 - invalid. */
4052/* Opcode VEX.F2.0F 0xc0 - invalid. */
4053
4054/* Opcode VEX.0F 0xc1 - invalid. */
4055/* Opcode VEX.66.0F 0xc1 - invalid. */
4056/* Opcode VEX.F3.0F 0xc1 - invalid. */
4057/* Opcode VEX.F2.0F 0xc1 - invalid. */
4058
4059/** Opcode VEX.0F 0xc2 - vcmpps Vps,Hps,Wps,Ib */
4060FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
4061/** Opcode VEX.66.0F 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
4062FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
4063/** Opcode VEX.F3.0F 0xc2 - vcmpss Vss,Hss,Wss,Ib */
4064FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
4065/** Opcode VEX.F2.0F 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
4066FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
4067
4068/* Opcode VEX.0F 0xc3 - invalid */
4069/* Opcode VEX.66.0F 0xc3 - invalid */
4070/* Opcode VEX.F3.0F 0xc3 - invalid */
4071/* Opcode VEX.F2.0F 0xc3 - invalid */
4072
4073/* Opcode VEX.0F 0xc4 - invalid */
4074
4075
4076/** Opcode VEX.66.0F 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
4077FNIEMOP_DEF(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib)
4078{
4079 /*IEMOP_MNEMONIC4(VEX_RMV, VPINSRW, vpinsrw, Vdq, Vdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
4080 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4081 if (IEM_IS_MODRM_REG_MODE(bRm))
4082 {
4083 /*
4084 * Register, register.
4085 */
4086 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
4087 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4088 IEM_MC_BEGIN(4, 0);
4089 IEM_MC_ARG(PRTUINT128U, puDst, 0);
4090 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4091 IEM_MC_ARG(uint16_t, u16Src, 2);
4092 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 3);
4093 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4094 IEM_MC_PREPARE_AVX_USAGE();
4095 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4096 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4097 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, bRm));
4098 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpinsrw_u128, iemAImpl_vpinsrw_u128_fallback),
4099 puDst, puSrc, u16Src, bEvilArg);
4100 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
4101 IEM_MC_ADVANCE_RIP();
4102 IEM_MC_END();
4103 }
4104 else
4105 {
4106 /*
4107 * Register, memory.
4108 */
4109 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
4110 IEM_MC_BEGIN(4, 1);
4111 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4112 IEM_MC_ARG(PRTUINT128U, puDst, 0);
4113 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4114 IEM_MC_ARG(uint16_t, u16Src, 2);
4115 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 3);
4116
4117 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4118 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4119 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4120 IEM_MC_PREPARE_AVX_USAGE();
4121
4122 IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4123 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4124 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4125 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpinsrw_u128, iemAImpl_vpinsrw_u128_fallback),
4126 puDst, puSrc, u16Src, bEvilArg);
4127 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
4128
4129 IEM_MC_ADVANCE_RIP();
4130 IEM_MC_END();
4131 }
4132
4133 return VINF_SUCCESS;
4134}
4135
4136
4137/* Opcode VEX.F3.0F 0xc4 - invalid */
4138/* Opcode VEX.F2.0F 0xc4 - invalid */
4139
4140/* Opcode VEX.0F 0xc5 - invlid */
4141
4142
4143/** Opcode VEX.66.0F 0xc5 - vpextrw Gd, Udq, Ib */
4144FNIEMOP_DEF(iemOp_vpextrw_Gd_Udq_Ib)
4145{
4146 IEMOP_MNEMONIC3(VEX_RMI_REG, VPEXTRW, vpextrw, Gd, Ux, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
4147 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4148 if (IEM_IS_MODRM_REG_MODE(bRm))
4149 {
4150 /*
4151 * Register, register.
4152 */
4153 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
4154 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4155 IEM_MC_BEGIN(3, 1);
4156 IEM_MC_LOCAL(uint16_t, u16Dst);
4157 IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Dst, u16Dst, 0);
4158 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4159 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
4160 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4161 IEM_MC_PREPARE_AVX_USAGE();
4162 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4163 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpextrw_u128, iemAImpl_vpextrw_u128_fallback),
4164 pu16Dst, puSrc, bEvilArg);
4165 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst);
4166 IEM_MC_ADVANCE_RIP();
4167 IEM_MC_END();
4168 return VINF_SUCCESS;
4169 }
4170
4171 /* No memory operand. */
4172 return IEMOP_RAISE_INVALID_OPCODE();
4173}
4174
4175
4176/* Opcode VEX.F3.0F 0xc5 - invalid */
4177/* Opcode VEX.F2.0F 0xc5 - invalid */
4178
4179
4180#define VSHUFP_X(a_Instr) \
4181 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
4182 if (IEM_IS_MODRM_REG_MODE(bRm)) \
4183 { \
4184 /* \
4185 * Register, register. \
4186 */ \
4187 if (pVCpu->iem.s.uVexLength) \
4188 { \
4189 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil); \
4190 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4191 IEM_MC_BEGIN(4, 3); \
4192 IEM_MC_LOCAL(RTUINT256U, uDst); \
4193 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4194 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4195 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4196 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4197 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4198 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 3); \
4199 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4200 IEM_MC_PREPARE_AVX_USAGE(); \
4201 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4202 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4203 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4204 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bEvilArg); \
4205 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4206 IEM_MC_ADVANCE_RIP(); \
4207 IEM_MC_END(); \
4208 } \
4209 else \
4210 { \
4211 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil); \
4212 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4213 IEM_MC_BEGIN(4, 0); \
4214 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4215 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4216 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2); \
4217 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 3); \
4218 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4219 IEM_MC_PREPARE_AVX_USAGE(); \
4220 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4221 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4222 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4223 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4224 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bEvilArg); \
4225 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4226 IEM_MC_ADVANCE_RIP(); \
4227 IEM_MC_END(); \
4228 } \
4229 } \
4230 else \
4231 { \
4232 /* \
4233 * Register, memory. \
4234 */ \
4235 if (pVCpu->iem.s.uVexLength) \
4236 { \
4237 IEM_MC_BEGIN(4, 4); \
4238 IEM_MC_LOCAL(RTUINT256U, uDst); \
4239 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4240 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4241 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4242 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4243 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4244 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4245 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
4246 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil); \
4247 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 3); \
4248 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4249 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4250 IEM_MC_PREPARE_AVX_USAGE(); \
4251 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4252 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4253 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4254 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bEvilArg); \
4255 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4256 IEM_MC_ADVANCE_RIP(); \
4257 IEM_MC_END(); \
4258 } \
4259 else \
4260 { \
4261 IEM_MC_BEGIN(4, 2); \
4262 IEM_MC_LOCAL(RTUINT128U, uSrc2); \
4263 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4264 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4265 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4266 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2); \
4267 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
4268 uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil); \
4269 IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 3); \
4270 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4271 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
4272 IEM_MC_PREPARE_AVX_USAGE(); \
4273 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4274 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4275 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4276 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4277 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bEvilArg); \
4278 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4279 IEM_MC_ADVANCE_RIP(); \
4280 IEM_MC_END(); \
4281 } \
4282 } \
4283 return VINF_SUCCESS;
4284
4285/** Opcode VEX.0F 0xc6 - vshufps Vps,Hps,Wps,Ib */
4286FNIEMOP_DEF(iemOp_vshufps_Vps_Hps_Wps_Ib)
4287{
4288 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPS, vshufps, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
4289 VSHUFP_X(vshufps);
4290}
4291
4292
4293/** Opcode VEX.66.0F 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
4294FNIEMOP_DEF(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib)
4295{
4296 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPD, vshufpd, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
4297 VSHUFP_X(vshufpd);
4298}
4299#undef VSHUFP_X
4300
4301
4302/* Opcode VEX.F3.0F 0xc6 - invalid */
4303/* Opcode VEX.F2.0F 0xc6 - invalid */
4304
4305/* Opcode VEX.0F 0xc7 - invalid */
4306/* Opcode VEX.66.0F 0xc7 - invalid */
4307/* Opcode VEX.F3.0F 0xc7 - invalid */
4308/* Opcode VEX.F2.0F 0xc7 - invalid */
4309
4310/* Opcode VEX.0F 0xc8 - invalid */
4311/* Opcode VEX.0F 0xc9 - invalid */
4312/* Opcode VEX.0F 0xca - invalid */
4313/* Opcode VEX.0F 0xcb - invalid */
4314/* Opcode VEX.0F 0xcc - invalid */
4315/* Opcode VEX.0F 0xcd - invalid */
4316/* Opcode VEX.0F 0xce - invalid */
4317/* Opcode VEX.0F 0xcf - invalid */
4318
4319
4320/* Opcode VEX.0F 0xd0 - invalid */
4321/** Opcode VEX.66.0F 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
4322FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
4323/* Opcode VEX.F3.0F 0xd0 - invalid */
4324/** Opcode VEX.F2.0F 0xd0 - vaddsubps Vps, Hps, Wps */
4325FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
4326
4327/* Opcode VEX.0F 0xd1 - invalid */
4328/** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
4329FNIEMOP_STUB(iemOp_vpsrlw_Vx_Hx_W);
4330/* Opcode VEX.F3.0F 0xd1 - invalid */
4331/* Opcode VEX.F2.0F 0xd1 - invalid */
4332
4333/* Opcode VEX.0F 0xd2 - invalid */
4334/** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
4335FNIEMOP_STUB(iemOp_vpsrld_Vx_Hx_Wx);
4336/* Opcode VEX.F3.0F 0xd2 - invalid */
4337/* Opcode VEX.F2.0F 0xd2 - invalid */
4338
4339/* Opcode VEX.0F 0xd3 - invalid */
4340/** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
4341FNIEMOP_STUB(iemOp_vpsrlq_Vx_Hx_Wx);
4342/* Opcode VEX.F3.0F 0xd3 - invalid */
4343/* Opcode VEX.F2.0F 0xd3 - invalid */
4344
4345/* Opcode VEX.0F 0xd4 - invalid */
4346
4347
4348/** Opcode VEX.66.0F 0xd4 - vpaddq Vx, Hx, W */
4349FNIEMOP_DEF(iemOp_vpaddq_Vx_Hx_Wx)
4350{
4351 IEMOP_MNEMONIC3(VEX_RVM, VPADDQ, vpaddq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4352 IEMOPMEDIAF3_INIT_VARS( vpaddq);
4353 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4354}
4355
4356
4357/* Opcode VEX.F3.0F 0xd4 - invalid */
4358/* Opcode VEX.F2.0F 0xd4 - invalid */
4359
4360/* Opcode VEX.0F 0xd5 - invalid */
4361
4362
4363/** Opcode VEX.66.0F 0xd5 - vpmullw Vx, Hx, Wx */
4364FNIEMOP_DEF(iemOp_vpmullw_Vx_Hx_Wx)
4365{
4366 IEMOP_MNEMONIC3(VEX_RVM, VPMULLW, vpmullw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4367 IEMOPMEDIAOPTF3_INIT_VARS(vpmullw);
4368 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4369}
4370
4371
4372/* Opcode VEX.F3.0F 0xd5 - invalid */
4373/* Opcode VEX.F2.0F 0xd5 - invalid */
4374
4375/* Opcode VEX.0F 0xd6 - invalid */
4376
4377/**
4378 * @opcode 0xd6
4379 * @oppfx 0x66
4380 * @opcpuid avx
4381 * @opgroup og_avx_pcksclr_datamove
4382 * @opxcpttype none
4383 * @optest op1=-1 op2=2 -> op1=2
4384 * @optest op1=0 op2=-42 -> op1=-42
4385 */
4386FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
4387{
4388 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Wq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4389 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4390 if (IEM_IS_MODRM_REG_MODE(bRm))
4391 {
4392 /*
4393 * Register, register.
4394 */
4395 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
4396 IEM_MC_BEGIN(0, 0);
4397
4398 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4399 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4400
4401 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4402 IEM_GET_MODRM_REG(pVCpu, bRm));
4403 IEM_MC_ADVANCE_RIP();
4404 IEM_MC_END();
4405 }
4406 else
4407 {
4408 /*
4409 * Memory, register.
4410 */
4411 IEM_MC_BEGIN(0, 2);
4412 IEM_MC_LOCAL(uint64_t, uSrc);
4413 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4414
4415 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4416 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
4417 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4418 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4419
4420 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
4421 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
4422
4423 IEM_MC_ADVANCE_RIP();
4424 IEM_MC_END();
4425 }
4426 return VINF_SUCCESS;
4427}
4428
4429/* Opcode VEX.F3.0F 0xd6 - invalid */
4430/* Opcode VEX.F2.0F 0xd6 - invalid */
4431
4432
4433/* Opcode VEX.0F 0xd7 - invalid */
4434
4435/** Opcode VEX.66.0F 0xd7 - */
4436FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
4437{
4438 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4439 /* Docs says register only. */
4440 if (IEM_IS_MODRM_REG_MODE(bRm)) /** @todo test that this is registers only. */
4441 {
4442 /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
4443 IEMOP_MNEMONIC2(RM_REG, VPMOVMSKB, vpmovmskb, Gd, Ux, DISOPTYPE_SSE | DISOPTYPE_HARMLESS, 0);
4444 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4445 if (pVCpu->iem.s.uVexLength)
4446 {
4447 IEM_MC_BEGIN(2, 1);
4448 IEM_MC_ARG(uint64_t *, puDst, 0);
4449 IEM_MC_LOCAL(RTUINT256U, uSrc);
4450 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
4451 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
4452 IEM_MC_PREPARE_AVX_USAGE();
4453 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4454 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4455 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpmovmskb_u256,
4456 iemAImpl_vpmovmskb_u256_fallback), puDst, puSrc);
4457 IEM_MC_ADVANCE_RIP();
4458 IEM_MC_END();
4459 }
4460 else
4461 {
4462 IEM_MC_BEGIN(2, 0);
4463 IEM_MC_ARG(uint64_t *, puDst, 0);
4464 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4465 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
4466 IEM_MC_PREPARE_AVX_USAGE();
4467 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4468 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4469 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_pmovmskb_u128, puDst, puSrc);
4470 IEM_MC_ADVANCE_RIP();
4471 IEM_MC_END();
4472 }
4473 return VINF_SUCCESS;
4474 }
4475 return IEMOP_RAISE_INVALID_OPCODE();
4476}
4477
4478
4479/* Opcode VEX.F3.0F 0xd7 - invalid */
4480/* Opcode VEX.F2.0F 0xd7 - invalid */
4481
4482
4483/* Opcode VEX.0F 0xd8 - invalid */
4484/** Opcode VEX.66.0F 0xd8 - vpsubusb Vx, Hx, W */
4485FNIEMOP_STUB(iemOp_vpsubusb_Vx_Hx_W);
4486/* Opcode VEX.F3.0F 0xd8 - invalid */
4487/* Opcode VEX.F2.0F 0xd8 - invalid */
4488
4489/* Opcode VEX.0F 0xd9 - invalid */
4490/** Opcode VEX.66.0F 0xd9 - vpsubusw Vx, Hx, Wx */
4491FNIEMOP_STUB(iemOp_vpsubusw_Vx_Hx_Wx);
4492/* Opcode VEX.F3.0F 0xd9 - invalid */
4493/* Opcode VEX.F2.0F 0xd9 - invalid */
4494
4495/* Opcode VEX.0F 0xda - invalid */
4496
4497
4498/** Opcode VEX.66.0F 0xda - vpminub Vx, Hx, Wx */
4499FNIEMOP_DEF(iemOp_vpminub_Vx_Hx_Wx)
4500{
4501 IEMOP_MNEMONIC3(VEX_RVM, VPMINUB, vpminub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4502 IEMOPMEDIAF3_INIT_VARS(vpminub);
4503 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4504}
4505
4506
4507/* Opcode VEX.F3.0F 0xda - invalid */
4508/* Opcode VEX.F2.0F 0xda - invalid */
4509
4510/* Opcode VEX.0F 0xdb - invalid */
4511
4512
4513/** Opcode VEX.66.0F 0xdb - vpand Vx, Hx, Wx */
4514FNIEMOP_DEF(iemOp_vpand_Vx_Hx_Wx)
4515{
4516 IEMOP_MNEMONIC3(VEX_RVM, VPAND, vpand, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4517 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4518 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
4519}
4520
4521
4522/* Opcode VEX.F3.0F 0xdb - invalid */
4523/* Opcode VEX.F2.0F 0xdb - invalid */
4524
4525/* Opcode VEX.0F 0xdc - invalid */
4526/** Opcode VEX.66.0F 0xdc - vpaddusb Vx, Hx, Wx */
4527FNIEMOP_STUB(iemOp_vpaddusb_Vx_Hx_Wx);
4528/* Opcode VEX.F3.0F 0xdc - invalid */
4529/* Opcode VEX.F2.0F 0xdc - invalid */
4530
4531/* Opcode VEX.0F 0xdd - invalid */
4532/** Opcode VEX.66.0F 0xdd - vpaddusw Vx, Hx, Wx */
4533FNIEMOP_STUB(iemOp_vpaddusw_Vx_Hx_Wx);
4534/* Opcode VEX.F3.0F 0xdd - invalid */
4535/* Opcode VEX.F2.0F 0xdd - invalid */
4536
4537/* Opcode VEX.0F 0xde - invalid */
4538
4539
4540/** Opcode VEX.66.0F 0xde - vpmaxub Vx, Hx, Wx */
4541FNIEMOP_DEF(iemOp_vpmaxub_Vx_Hx_Wx)
4542{
4543 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUB, vpmaxub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4544 IEMOPMEDIAF3_INIT_VARS(vpmaxub);
4545 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4546}
4547
4548
4549/* Opcode VEX.F3.0F 0xde - invalid */
4550/* Opcode VEX.F2.0F 0xde - invalid */
4551
4552/* Opcode VEX.0F 0xdf - invalid */
4553
4554
4555/** Opcode VEX.66.0F 0xdf - vpandn Vx, Hx, Wx */
4556FNIEMOP_DEF(iemOp_vpandn_Vx_Hx_Wx)
4557{
4558 IEMOP_MNEMONIC3(VEX_RVM, VPANDN, vpandn, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4559 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4560 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
4561}
4562
4563
4564/* Opcode VEX.F3.0F 0xdf - invalid */
4565/* Opcode VEX.F2.0F 0xdf - invalid */
4566
4567/* Opcode VEX.0F 0xe0 - invalid */
4568
4569
4570/** Opcode VEX.66.0F 0xe0 - vpavgb Vx, Hx, Wx */
4571FNIEMOP_DEF(iemOp_vpavgb_Vx_Hx_Wx)
4572{
4573 IEMOP_MNEMONIC3(VEX_RVM, VPAVGB, vpavgb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4574 IEMOPMEDIAOPTF3_INIT_VARS(vpavgb);
4575 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4576}
4577
4578
4579/* Opcode VEX.F3.0F 0xe0 - invalid */
4580/* Opcode VEX.F2.0F 0xe0 - invalid */
4581
4582/* Opcode VEX.0F 0xe1 - invalid */
4583/** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */
4584FNIEMOP_STUB(iemOp_vpsraw_Vx_Hx_W);
4585/* Opcode VEX.F3.0F 0xe1 - invalid */
4586/* Opcode VEX.F2.0F 0xe1 - invalid */
4587
4588/* Opcode VEX.0F 0xe2 - invalid */
4589/** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */
4590FNIEMOP_STUB(iemOp_vpsrad_Vx_Hx_Wx);
4591/* Opcode VEX.F3.0F 0xe2 - invalid */
4592/* Opcode VEX.F2.0F 0xe2 - invalid */
4593
4594/* Opcode VEX.0F 0xe3 - invalid */
4595
4596
4597/** Opcode VEX.66.0F 0xe3 - vpavgw Vx, Hx, Wx */
4598FNIEMOP_DEF(iemOp_vpavgw_Vx_Hx_Wx)
4599{
4600 IEMOP_MNEMONIC3(VEX_RVM, VPAVGW, vpavgw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4601 IEMOPMEDIAOPTF3_INIT_VARS(vpavgw);
4602 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4603}
4604
4605
4606/* Opcode VEX.F3.0F 0xe3 - invalid */
4607/* Opcode VEX.F2.0F 0xe3 - invalid */
4608
4609/* Opcode VEX.0F 0xe4 - invalid */
4610
4611
4612/** Opcode VEX.66.0F 0xe4 - vpmulhuw Vx, Hx, Wx */
4613FNIEMOP_DEF(iemOp_vpmulhuw_Vx_Hx_Wx)
4614{
4615 IEMOP_MNEMONIC3(VEX_RVM, VPMULHUW, vpmulhuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4616 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhuw);
4617 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4618}
4619
4620
4621/* Opcode VEX.F3.0F 0xe4 - invalid */
4622/* Opcode VEX.F2.0F 0xe4 - invalid */
4623
4624/* Opcode VEX.0F 0xe5 - invalid */
4625
4626
4627/** Opcode VEX.66.0F 0xe5 - vpmulhw Vx, Hx, Wx */
4628FNIEMOP_DEF(iemOp_vpmulhw_Vx_Hx_Wx)
4629{
4630 IEMOP_MNEMONIC3(VEX_RVM, VPMULHW, vpmulhw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
4631 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhw);
4632 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4633}
4634
4635
4636/* Opcode VEX.F3.0F 0xe5 - invalid */
4637/* Opcode VEX.F2.0F 0xe5 - invalid */
4638
4639/* Opcode VEX.0F 0xe6 - invalid */
4640/** Opcode VEX.66.0F 0xe6 - vcvttpd2dq Vx, Wpd */
4641FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
4642/** Opcode VEX.F3.0F 0xe6 - vcvtdq2pd Vx, Wpd */
4643FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
4644/** Opcode VEX.F2.0F 0xe6 - vcvtpd2dq Vx, Wpd */
4645FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
4646
4647
4648/* Opcode VEX.0F 0xe7 - invalid */
4649
4650/**
4651 * @opcode 0xe7
4652 * @opcodesub !11 mr/reg
4653 * @oppfx 0x66
4654 * @opcpuid avx
4655 * @opgroup og_avx_cachect
4656 * @opxcpttype 1
4657 * @optest op1=-1 op2=2 -> op1=2
4658 * @optest op1=0 op2=-42 -> op1=-42
4659 */
4660FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
4661{
4662 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTDQ, vmovntdq, Mx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4663 Assert(pVCpu->iem.s.uVexLength <= 1);
4664 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4665 if (IEM_IS_MODRM_MEM_MODE(bRm))
4666 {
4667 if (pVCpu->iem.s.uVexLength == 0)
4668 {
4669 /*
4670 * 128-bit: Memory, register.
4671 */
4672 IEM_MC_BEGIN(0, 2);
4673 IEM_MC_LOCAL(RTUINT128U, uSrc);
4674 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4675
4676 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4677 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4678 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4679 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4680
4681 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
4682 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
4683
4684 IEM_MC_ADVANCE_RIP();
4685 IEM_MC_END();
4686 }
4687 else
4688 {
4689 /*
4690 * 256-bit: Memory, register.
4691 */
4692 IEM_MC_BEGIN(0, 2);
4693 IEM_MC_LOCAL(RTUINT256U, uSrc);
4694 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4695
4696 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4697 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4698 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4699 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4700
4701 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
4702 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
4703
4704 IEM_MC_ADVANCE_RIP();
4705 IEM_MC_END();
4706 }
4707 return VINF_SUCCESS;
4708 }
4709 /**
4710 * @opdone
4711 * @opmnemonic udvex660fe7reg
4712 * @opcode 0xe7
4713 * @opcodesub 11 mr/reg
4714 * @oppfx 0x66
4715 * @opunused immediate
4716 * @opcpuid avx
4717 * @optest ->
4718 */
4719 return IEMOP_RAISE_INVALID_OPCODE();
4720}
4721
4722/* Opcode VEX.F3.0F 0xe7 - invalid */
4723/* Opcode VEX.F2.0F 0xe7 - invalid */
4724
4725
4726/* Opcode VEX.0F 0xe8 - invalid */
4727/** Opcode VEX.66.0F 0xe8 - vpsubsb Vx, Hx, W */
4728FNIEMOP_STUB(iemOp_vpsubsb_Vx_Hx_W);
4729/* Opcode VEX.F3.0F 0xe8 - invalid */
4730/* Opcode VEX.F2.0F 0xe8 - invalid */
4731
4732/* Opcode VEX.0F 0xe9 - invalid */
4733/** Opcode VEX.66.0F 0xe9 - vpsubsw Vx, Hx, Wx */
4734FNIEMOP_STUB(iemOp_vpsubsw_Vx_Hx_Wx);
4735/* Opcode VEX.F3.0F 0xe9 - invalid */
4736/* Opcode VEX.F2.0F 0xe9 - invalid */
4737
4738/* Opcode VEX.0F 0xea - invalid */
4739
4740
4741/** Opcode VEX.66.0F 0xea - vpminsw Vx, Hx, Wx */
4742FNIEMOP_DEF(iemOp_vpminsw_Vx_Hx_Wx)
4743{
4744 IEMOP_MNEMONIC3(VEX_RVM, VPMINSW, vpminsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4745 IEMOPMEDIAF3_INIT_VARS(vpminsw);
4746 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4747}
4748
4749
4750/* Opcode VEX.F3.0F 0xea - invalid */
4751/* Opcode VEX.F2.0F 0xea - invalid */
4752
4753/* Opcode VEX.0F 0xeb - invalid */
4754
4755
4756/** Opcode VEX.66.0F 0xeb - vpor Vx, Hx, Wx */
4757FNIEMOP_DEF(iemOp_vpor_Vx_Hx_Wx)
4758{
4759 IEMOP_MNEMONIC3(VEX_RVM, VPOR, vpor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4760 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4761 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
4762}
4763
4764
4765
4766/* Opcode VEX.F3.0F 0xeb - invalid */
4767/* Opcode VEX.F2.0F 0xeb - invalid */
4768
4769/* Opcode VEX.0F 0xec - invalid */
4770/** Opcode VEX.66.0F 0xec - vpaddsb Vx, Hx, Wx */
4771FNIEMOP_STUB(iemOp_vpaddsb_Vx_Hx_Wx);
4772/* Opcode VEX.F3.0F 0xec - invalid */
4773/* Opcode VEX.F2.0F 0xec - invalid */
4774
4775/* Opcode VEX.0F 0xed - invalid */
4776/** Opcode VEX.66.0F 0xed - vpaddsw Vx, Hx, Wx */
4777FNIEMOP_STUB(iemOp_vpaddsw_Vx_Hx_Wx);
4778/* Opcode VEX.F3.0F 0xed - invalid */
4779/* Opcode VEX.F2.0F 0xed - invalid */
4780
4781/* Opcode VEX.0F 0xee - invalid */
4782
4783
4784/** Opcode VEX.66.0F 0xee - vpmaxsw Vx, Hx, Wx */
4785FNIEMOP_DEF(iemOp_vpmaxsw_Vx_Hx_Wx)
4786{
4787 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSW, vpmaxsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4788 IEMOPMEDIAF3_INIT_VARS(vpmaxsw);
4789 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4790}
4791
4792
4793/* Opcode VEX.F3.0F 0xee - invalid */
4794/* Opcode VEX.F2.0F 0xee - invalid */
4795
4796
4797/* Opcode VEX.0F 0xef - invalid */
4798
4799
4800/** Opcode VEX.66.0F 0xef - vpxor Vx, Hx, Wx */
4801FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
4802{
4803 IEMOP_MNEMONIC3(VEX_RVM, VPXOR, vpxor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4804 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4805 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
4806}
4807
4808
4809/* Opcode VEX.F3.0F 0xef - invalid */
4810/* Opcode VEX.F2.0F 0xef - invalid */
4811
4812/* Opcode VEX.0F 0xf0 - invalid */
4813/* Opcode VEX.66.0F 0xf0 - invalid */
4814
4815
4816/** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
4817FNIEMOP_DEF(iemOp_vlddqu_Vx_Mx)
4818{
4819 IEMOP_MNEMONIC2(VEX_RM_MEM, VLDDQU, vlddqu, Vx_WO, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4820 Assert(pVCpu->iem.s.uVexLength <= 1);
4821 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4822 if (IEM_IS_MODRM_REG_MODE(bRm))
4823 {
4824 /*
4825 * Register, register - (not implemented, assuming it raises \#UD).
4826 */
4827 return IEMOP_RAISE_INVALID_OPCODE();
4828 }
4829 else if (pVCpu->iem.s.uVexLength == 0)
4830 {
4831 /*
4832 * Register, memory128.
4833 */
4834 IEM_MC_BEGIN(0, 2);
4835 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4836 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4837
4838 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4839 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4840 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4841 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4842
4843 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4844 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
4845
4846 IEM_MC_ADVANCE_RIP();
4847 IEM_MC_END();
4848 }
4849 else
4850 {
4851 /*
4852 * Register, memory256.
4853 */
4854 IEM_MC_BEGIN(0, 2);
4855 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4856 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4857
4858 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4859 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
4860 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4861 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4862
4863 IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4864 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
4865
4866 IEM_MC_ADVANCE_RIP();
4867 IEM_MC_END();
4868 }
4869 return VINF_SUCCESS;
4870}
4871
4872
4873/* Opcode VEX.0F 0xf1 - invalid */
4874/** Opcode VEX.66.0F 0xf1 - vpsllw Vx, Hx, W */
4875FNIEMOP_STUB(iemOp_vpsllw_Vx_Hx_W);
4876/* Opcode VEX.F2.0F 0xf1 - invalid */
4877
4878/* Opcode VEX.0F 0xf2 - invalid */
4879/** Opcode VEX.66.0F 0xf2 - vpslld Vx, Hx, Wx */
4880FNIEMOP_STUB(iemOp_vpslld_Vx_Hx_Wx);
4881/* Opcode VEX.F2.0F 0xf2 - invalid */
4882
4883/* Opcode VEX.0F 0xf3 - invalid */
4884/** Opcode VEX.66.0F 0xf3 - vpsllq Vx, Hx, Wx */
4885FNIEMOP_STUB(iemOp_vpsllq_Vx_Hx_Wx);
4886/* Opcode VEX.F2.0F 0xf3 - invalid */
4887
4888/* Opcode VEX.0F 0xf4 - invalid */
4889
4890
4891/** Opcode VEX.66.0F 0xf4 - vpmuludq Vx, Hx, W */
4892FNIEMOP_DEF(iemOp_vpmuludq_Vx_Hx_W)
4893{
4894 IEMOP_MNEMONIC3(VEX_RVM, VPMULUDQ, vpmuludq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4895 IEMOPMEDIAOPTF3_INIT_VARS(vpmuludq);
4896 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4897}
4898
4899
4900/* Opcode VEX.F2.0F 0xf4 - invalid */
4901
4902/* Opcode VEX.0F 0xf5 - invalid */
4903/** Opcode VEX.66.0F 0xf5 - vpmaddwd Vx, Hx, Wx */
4904FNIEMOP_STUB(iemOp_vpmaddwd_Vx_Hx_Wx);
4905/* Opcode VEX.F2.0F 0xf5 - invalid */
4906
4907/* Opcode VEX.0F 0xf6 - invalid */
4908
4909
4910/** Opcode VEX.66.0F 0xf6 - vpsadbw Vx, Hx, Wx */
4911FNIEMOP_DEF(iemOp_vpsadbw_Vx_Hx_Wx)
4912{
4913 IEMOP_MNEMONIC3(VEX_RVM, VPSADBW, vpsadbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4914 IEMOPMEDIAOPTF3_INIT_VARS(vpsadbw);
4915 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4916}
4917
4918
4919/* Opcode VEX.F2.0F 0xf6 - invalid */
4920
4921/* Opcode VEX.0F 0xf7 - invalid */
4922/** Opcode VEX.66.0F 0xf7 - vmaskmovdqu Vdq, Udq */
4923FNIEMOP_STUB(iemOp_vmaskmovdqu_Vdq_Udq);
4924/* Opcode VEX.F2.0F 0xf7 - invalid */
4925
4926/* Opcode VEX.0F 0xf8 - invalid */
4927
4928
4929/** Opcode VEX.66.0F 0xf8 - vpsubb Vx, Hx, W */
4930FNIEMOP_DEF(iemOp_vpsubb_Vx_Hx_Wx)
4931{
4932 IEMOP_MNEMONIC3(VEX_RVM, VPSUBB, vpsubb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4933 IEMOPMEDIAF3_INIT_VARS( vpsubb);
4934 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4935}
4936
4937
4938/* Opcode VEX.F2.0F 0xf8 - invalid */
4939
4940/* Opcode VEX.0F 0xf9 - invalid */
4941
4942
4943/** Opcode VEX.66.0F 0xf9 - vpsubw Vx, Hx, Wx */
4944FNIEMOP_DEF(iemOp_vpsubw_Vx_Hx_Wx)
4945{
4946 IEMOP_MNEMONIC3(VEX_RVM, VPSUBW, vpsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4947 IEMOPMEDIAF3_INIT_VARS( vpsubw);
4948 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4949}
4950
4951
4952/* Opcode VEX.F2.0F 0xf9 - invalid */
4953
4954/* Opcode VEX.0F 0xfa - invalid */
4955
4956
4957/** Opcode VEX.66.0F 0xfa - vpsubd Vx, Hx, Wx */
4958FNIEMOP_DEF(iemOp_vpsubd_Vx_Hx_Wx)
4959{
4960 IEMOP_MNEMONIC3(VEX_RVM, VPSUBD, vpsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4961 IEMOPMEDIAF3_INIT_VARS( vpsubd);
4962 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4963}
4964
4965
4966/* Opcode VEX.F2.0F 0xfa - invalid */
4967
4968/* Opcode VEX.0F 0xfb - invalid */
4969
4970
4971/** Opcode VEX.66.0F 0xfb - vpsubq Vx, Hx, W */
4972FNIEMOP_DEF(iemOp_vpsubq_Vx_Hx_Wx)
4973{
4974 IEMOP_MNEMONIC3(VEX_RVM, VPSUBQ, vpsubq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4975 IEMOPMEDIAF3_INIT_VARS( vpsubq);
4976 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4977}
4978
4979
4980/* Opcode VEX.F2.0F 0xfb - invalid */
4981
4982/* Opcode VEX.0F 0xfc - invalid */
4983
4984
4985/** Opcode VEX.66.0F 0xfc - vpaddb Vx, Hx, Wx */
4986FNIEMOP_DEF(iemOp_vpaddb_Vx_Hx_Wx)
4987{
4988 IEMOP_MNEMONIC3(VEX_RVM, VPADDB, vpaddb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4989 IEMOPMEDIAF3_INIT_VARS( vpaddb);
4990 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4991}
4992
4993
4994/* Opcode VEX.F2.0F 0xfc - invalid */
4995
4996/* Opcode VEX.0F 0xfd - invalid */
4997
4998
4999/** Opcode VEX.66.0F 0xfd - vpaddw Vx, Hx, Wx */
5000FNIEMOP_DEF(iemOp_vpaddw_Vx_Hx_Wx)
5001{
5002 IEMOP_MNEMONIC3(VEX_RVM, VPADDW, vpaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5003 IEMOPMEDIAF3_INIT_VARS( vpaddw);
5004 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5005}
5006
5007
5008/* Opcode VEX.F2.0F 0xfd - invalid */
5009
5010/* Opcode VEX.0F 0xfe - invalid */
5011
5012
5013/** Opcode VEX.66.0F 0xfe - vpaddd Vx, Hx, W */
5014FNIEMOP_DEF(iemOp_vpaddd_Vx_Hx_Wx)
5015{
5016 IEMOP_MNEMONIC3(VEX_RVM, VPADDD, vpaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5017 IEMOPMEDIAF3_INIT_VARS( vpaddd);
5018 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5019}
5020
5021
5022/* Opcode VEX.F2.0F 0xfe - invalid */
5023
5024
5025/** Opcode **** 0x0f 0xff - UD0 */
5026FNIEMOP_DEF(iemOp_vud0)
5027{
5028 IEMOP_MNEMONIC(vud0, "vud0");
5029 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
5030 {
5031 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
5032#ifndef TST_IEM_CHECK_MC
5033 RTGCPTR GCPtrEff;
5034 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
5035 if (rcStrict != VINF_SUCCESS)
5036 return rcStrict;
5037#endif
5038 IEMOP_HLP_DONE_DECODING();
5039 }
5040 return IEMOP_RAISE_INVALID_OPCODE();
5041}
5042
5043
5044
5045/**
5046 * VEX opcode map \#1.
5047 *
5048 * @sa g_apfnTwoByteMap
5049 */
5050IEM_STATIC const PFNIEMOP g_apfnVexMap1[] =
5051{
5052 /* no prefix, 066h prefix f3h prefix, f2h prefix */
5053 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
5054 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
5055 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
5056 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
5057 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
5058 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
5059 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
5060 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
5061 /* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
5062 /* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
5063 /* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
5064 /* 0x0b */ IEMOP_X4(iemOp_vud2), /* ?? */
5065 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
5066 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
5067 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
5068 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
5069
5070 /* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vss_Hss_Wss, iemOp_vmovsd_Vsd_Hsd_Wsd,
5071 /* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hss_Vss, iemOp_vmovsd_Wsd_Hsd_Vsd,
5072 /* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
5073 /* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5074 /* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5075 /* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5076 /* 0x16 */ iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpd_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
5077 /* 0x17 */ iemOp_vmovhps_Mq_Vq, iemOp_vmovhpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5078 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
5079 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
5080 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
5081 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
5082 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
5083 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
5084 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
5085 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
5086
5087 /* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
5088 /* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
5089 /* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
5090 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
5091 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
5092 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
5093 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
5094 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
5095 /* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5096 /* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5097 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
5098 /* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5099 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
5100 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
5101 /* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5102 /* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5103
5104 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
5105 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
5106 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
5107 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
5108 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
5109 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
5110 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
5111 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
5112 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5113 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5114 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5115 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5116 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5117 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5118 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5119 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5120
5121 /* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
5122 /* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
5123 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
5124 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
5125 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
5126 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
5127 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
5128 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
5129 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
5130 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
5131 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
5132 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
5133 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
5134 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
5135 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
5136 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
5137
5138 /* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5139 /* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
5140 /* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
5141 /* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
5142 /* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5143 /* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5144 /* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5145 /* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5146 /* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
5147 /* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
5148 /* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
5149 /* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
5150 /* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
5151 /* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
5152 /* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
5153 /* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
5154
5155 /* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5156 /* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5157 /* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5158 /* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5159 /* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5160 /* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5161 /* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5162 /* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5163 /* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5164 /* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5165 /* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5166 /* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5167 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5168 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5169 /* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5170 /* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
5171
5172 /* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
5173 /* 0x71 */ iemOp_InvalidNeedRM, iemOp_VGrp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5174 /* 0x72 */ iemOp_InvalidNeedRM, iemOp_VGrp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5175 /* 0x73 */ iemOp_InvalidNeedRM, iemOp_VGrp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5176 /* 0x74 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5177 /* 0x75 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5178 /* 0x76 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5179 /* 0x77 */ iemOp_vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5180 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
5181 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
5182 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
5183 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
5184 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
5185 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
5186 /* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
5187 /* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
5188
5189 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
5190 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
5191 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
5192 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
5193 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
5194 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
5195 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
5196 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
5197 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
5198 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
5199 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
5200 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
5201 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
5202 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
5203 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
5204 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
5205
5206 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
5207 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
5208 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
5209 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
5210 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
5211 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
5212 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
5213 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
5214 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
5215 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
5216 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
5217 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
5218 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
5219 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
5220 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
5221 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
5222
5223 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5224 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5225 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
5226 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5227 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
5228 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
5229 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
5230 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5231 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5232 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5233 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
5234 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
5235 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
5236 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
5237 /* 0xae */ IEMOP_X4(iemOp_VGrp15),
5238 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
5239
5240 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5241 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5242 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
5243 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5244 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
5245 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
5246 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
5247 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5248 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5249 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5250 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
5251 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
5252 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
5253 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
5254 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
5255 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
5256
5257 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5258 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5259 /* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
5260 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5261 /* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
5262 /* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
5263 /* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
5264 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5265 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5266 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5267 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
5268 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
5269 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
5270 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
5271 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
5272 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
5273
5274 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
5275 /* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5276 /* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5277 /* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5278 /* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5279 /* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5280 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5281 /* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5282 /* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5283 /* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5284 /* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5285 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5286 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5287 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5288 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5289 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5290
5291 /* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5292 /* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5293 /* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5294 /* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5295 /* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5296 /* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5297 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
5298 /* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5299 /* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5300 /* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5301 /* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5302 /* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5303 /* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5304 /* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5305 /* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5306 /* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5307
5308 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
5309 /* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5310 /* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5311 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5312 /* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5313 /* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5314 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5315 /* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5316 /* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5317 /* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5318 /* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5319 /* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5320 /* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5321 /* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5322 /* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5323 /* 0xff */ IEMOP_X4(iemOp_vud0) /* ?? */
5324};
5325AssertCompile(RT_ELEMENTS(g_apfnVexMap1) == 1024);
5326/** @} */
5327
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