VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h@ 96860

Last change on this file since 96860 was 96652, checked in by vboxsync, 21 months ago

VMM/IEM: Implement [v]pclmulqdq instruction, ​bugref:9898
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1/* $Id: IEMAllInstructionsThree0f3a.cpp.h 96652 2022-09-08 08:49:40Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4 *
5 * @remarks IEMAllInstructionsVexMap3.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name Three byte opcodes with first two bytes 0x0f 0x3a
33 * @{
34 */
35
36/**
37 * Common worker for SSSE3 instructions on the forms:
38 * pxxx xmm1, xmm2/mem128, imm8
39 *
40 * Proper alignment of the 128-bit operand is enforced.
41 * Exceptions type 4. SSSE3 cpuid checks.
42 *
43 * @sa iemOpCommonSse41_FullFullImm8_To_Full
44 */
45FNIEMOP_DEF_1(iemOpCommonSsse3_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
46{
47 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48 if (IEM_IS_MODRM_REG_MODE(bRm))
49 {
50 /*
51 * Register, register.
52 */
53 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
54 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
55 IEM_MC_BEGIN(3, 0);
56 IEM_MC_ARG(PRTUINT128U, puDst, 0);
57 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
58 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
59 IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
60 IEM_MC_PREPARE_SSE_USAGE();
61 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
62 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
63 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
64 IEM_MC_ADVANCE_RIP();
65 IEM_MC_END();
66 }
67 else
68 {
69 /*
70 * Register, memory.
71 */
72 IEM_MC_BEGIN(3, 2);
73 IEM_MC_ARG(PRTUINT128U, puDst, 0);
74 IEM_MC_LOCAL(RTUINT128U, uSrc);
75 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
76 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
77
78 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
79 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
80 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
81 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
82 IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
83 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84
85 IEM_MC_PREPARE_SSE_USAGE();
86 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
88
89 IEM_MC_ADVANCE_RIP();
90 IEM_MC_END();
91 }
92 return VINF_SUCCESS;
93}
94
95
96/**
97 * Common worker for SSE 4.1 instructions on the forms:
98 * pxxx xmm1, xmm2/mem128, imm8
99 *
100 * Proper alignment of the 128-bit operand is enforced.
101 * Exceptions type 4. SSE 4.1 cpuid checks.
102 *
103 * @sa iemOpCommonSsse3_FullFullImm8_To_Full
104 */
105FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
106{
107 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
108 if (IEM_IS_MODRM_REG_MODE(bRm))
109 {
110 /*
111 * Register, register.
112 */
113 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
114 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
115 IEM_MC_BEGIN(3, 0);
116 IEM_MC_ARG(PRTUINT128U, puDst, 0);
117 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
118 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
119 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
120 IEM_MC_PREPARE_SSE_USAGE();
121 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
122 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
123 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
124 IEM_MC_ADVANCE_RIP();
125 IEM_MC_END();
126 }
127 else
128 {
129 /*
130 * Register, memory.
131 */
132 IEM_MC_BEGIN(3, 2);
133 IEM_MC_ARG(PRTUINT128U, puDst, 0);
134 IEM_MC_LOCAL(RTUINT128U, uSrc);
135 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
136 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
137
138 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
139 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
140 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
141 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
142 IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
143 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
144
145 IEM_MC_PREPARE_SSE_USAGE();
146 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
147 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
148
149 IEM_MC_ADVANCE_RIP();
150 IEM_MC_END();
151 }
152 return VINF_SUCCESS;
153}
154
155
156/** Opcode 0x66 0x0f 0x00 - invalid (vex only). */
157/** Opcode 0x66 0x0f 0x01 - invalid (vex only). */
158/** Opcode 0x66 0x0f 0x02 - invalid (vex only). */
159/* Opcode 0x66 0x0f 0x03 - invalid */
160/** Opcode 0x66 0x0f 0x04 - invalid (vex only). */
161/** Opcode 0x66 0x0f 0x05 - invalid (vex only). */
162/* Opcode 0x66 0x0f 0x06 - invalid (vex only) */
163/* Opcode 0x66 0x0f 0x07 - invalid */
164/** Opcode 0x66 0x0f 0x08. */
165FNIEMOP_STUB(iemOp_roundps_Vx_Wx_Ib);
166/** Opcode 0x66 0x0f 0x09. */
167FNIEMOP_STUB(iemOp_roundpd_Vx_Wx_Ib);
168/** Opcode 0x66 0x0f 0x0a. */
169FNIEMOP_STUB(iemOp_roundss_Vss_Wss_Ib);
170/** Opcode 0x66 0x0f 0x0b. */
171FNIEMOP_STUB(iemOp_roundsd_Vsd_Wsd_Ib);
172
173
174/** Opcode 0x66 0x0f 0x0c. */
175FNIEMOP_DEF(iemOp_blendps_Vx_Wx_Ib)
176{
177 IEMOP_MNEMONIC3(RMI, BLENDPS, blendps, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
178 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
179 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback));
180}
181
182
183/** Opcode 0x66 0x0f 0x0d. */
184FNIEMOP_DEF(iemOp_blendpd_Vx_Wx_Ib)
185{
186 IEMOP_MNEMONIC3(RMI, BLENDPD, blendpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
187 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
188 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback));
189}
190
191
192/** Opcode 0x66 0x0f 0x0e. */
193FNIEMOP_DEF(iemOp_pblendw_Vx_Wx_Ib)
194{
195 IEMOP_MNEMONIC3(RMI, PBLENDW, pblendw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
196 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
197 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback));
198}
199
200
201/** Opcode 0x0f 0x0f. */
202FNIEMOP_DEF(iemOp_palignr_Pq_Qq_Ib)
203{
204 IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Pq, Qq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
205 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
206 if (IEM_IS_MODRM_REG_MODE(bRm))
207 {
208 /*
209 * Register, register.
210 */
211 /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
212 /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
213 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
214 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
215 IEM_MC_BEGIN(3, 0);
216 IEM_MC_ARG(uint64_t *, pDst, 0);
217 IEM_MC_ARG(uint64_t, uSrc, 1);
218 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
219 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
220 IEM_MC_PREPARE_FPU_USAGE();
221 IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
222 IEM_MC_FETCH_MREG_U64(uSrc, IEM_GET_MODRM_RM_8(bRm));
223 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
224 pDst, uSrc, bImmArg);
225 IEM_MC_MODIFIED_MREG_BY_REF(pDst);
226 IEM_MC_FPU_TO_MMX_MODE();
227 IEM_MC_ADVANCE_RIP();
228 IEM_MC_END();
229 }
230 else
231 {
232 /*
233 * Register, memory.
234 */
235 IEM_MC_BEGIN(3, 1);
236 IEM_MC_ARG(uint64_t *, pDst, 0);
237 IEM_MC_ARG(uint64_t, uSrc, 1);
238 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
239
240 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
241 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
242 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
243 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
244 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
245 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
246
247 IEM_MC_PREPARE_FPU_USAGE();
248 IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
249 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
250 pDst, uSrc, bImmArg);
251 IEM_MC_MODIFIED_MREG_BY_REF(pDst);
252 IEM_MC_FPU_TO_MMX_MODE();
253
254 IEM_MC_ADVANCE_RIP();
255 IEM_MC_END();
256 }
257 return VINF_SUCCESS;
258}
259
260
261/** Opcode 0x66 0x0f 0x0f. */
262FNIEMOP_DEF(iemOp_palignr_Vx_Wx_Ib)
263{
264 IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
265 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFullImm8_To_Full,
266 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback));
267}
268
269
270/* Opcode 0x66 0x0f 0x10 - invalid */
271/* Opcode 0x66 0x0f 0x11 - invalid */
272/* Opcode 0x66 0x0f 0x12 - invalid */
273/* Opcode 0x66 0x0f 0x13 - invalid */
274/** Opcode 0x66 0x0f 0x14. */
275FNIEMOP_STUB(iemOp_pextrb_RdMb_Vdq_Ib);
276/** Opcode 0x66 0x0f 0x15. */
277FNIEMOP_STUB(iemOp_pextrw_RdMw_Vdq_Ib);
278/** Opcode 0x66 0x0f 0x16. */
279FNIEMOP_STUB(iemOp_pextrd_q_RdMw_Vdq_Ib);
280/** Opcode 0x66 0x0f 0x17. */
281FNIEMOP_STUB(iemOp_extractps_Ed_Vdq_Ib);
282/* Opcode 0x66 0x0f 0x18 - invalid (vex only). */
283/* Opcode 0x66 0x0f 0x19 - invalid (vex only). */
284/* Opcode 0x66 0x0f 0x1a - invalid */
285/* Opcode 0x66 0x0f 0x1b - invalid */
286/* Opcode 0x66 0x0f 0x1c - invalid */
287/* Opcode 0x66 0x0f 0x1d - invalid (vex only). */
288/* Opcode 0x66 0x0f 0x1e - invalid */
289/* Opcode 0x66 0x0f 0x1f - invalid */
290
291
292/** Opcode 0x66 0x0f 0x20. */
293FNIEMOP_STUB(iemOp_pinsrb_Vdq_RyMb_Ib);
294/** Opcode 0x66 0x0f 0x21, */
295FNIEMOP_STUB(iemOp_insertps_Vdq_UdqMd_Ib);
296/** Opcode 0x66 0x0f 0x22. */
297FNIEMOP_STUB(iemOp_pinsrd_q_Vdq_Ey_Ib);
298/* Opcode 0x66 0x0f 0x23 - invalid */
299/* Opcode 0x66 0x0f 0x24 - invalid */
300/* Opcode 0x66 0x0f 0x25 - invalid */
301/* Opcode 0x66 0x0f 0x26 - invalid */
302/* Opcode 0x66 0x0f 0x27 - invalid */
303/* Opcode 0x66 0x0f 0x28 - invalid */
304/* Opcode 0x66 0x0f 0x29 - invalid */
305/* Opcode 0x66 0x0f 0x2a - invalid */
306/* Opcode 0x66 0x0f 0x2b - invalid */
307/* Opcode 0x66 0x0f 0x2c - invalid */
308/* Opcode 0x66 0x0f 0x2d - invalid */
309/* Opcode 0x66 0x0f 0x2e - invalid */
310/* Opcode 0x66 0x0f 0x2f - invalid */
311
312
313/* Opcode 0x66 0x0f 0x30 - invalid */
314/* Opcode 0x66 0x0f 0x31 - invalid */
315/* Opcode 0x66 0x0f 0x32 - invalid */
316/* Opcode 0x66 0x0f 0x33 - invalid */
317/* Opcode 0x66 0x0f 0x34 - invalid */
318/* Opcode 0x66 0x0f 0x35 - invalid */
319/* Opcode 0x66 0x0f 0x36 - invalid */
320/* Opcode 0x66 0x0f 0x37 - invalid */
321/* Opcode 0x66 0x0f 0x38 - invalid (vex only). */
322/* Opcode 0x66 0x0f 0x39 - invalid (vex only). */
323/* Opcode 0x66 0x0f 0x3a - invalid */
324/* Opcode 0x66 0x0f 0x3b - invalid */
325/* Opcode 0x66 0x0f 0x3c - invalid */
326/* Opcode 0x66 0x0f 0x3d - invalid */
327/* Opcode 0x66 0x0f 0x3e - invalid */
328/* Opcode 0x66 0x0f 0x3f - invalid */
329
330
331/** Opcode 0x66 0x0f 0x40. */
332FNIEMOP_STUB(iemOp_dpps_Vx_Wx_Ib);
333/** Opcode 0x66 0x0f 0x41, */
334FNIEMOP_STUB(iemOp_dppd_Vdq_Wdq_Ib);
335/** Opcode 0x66 0x0f 0x42. */
336FNIEMOP_STUB(iemOp_mpsadbw_Vx_Wx_Ib);
337/* Opcode 0x66 0x0f 0x43 - invalid */
338
339
340/** Opcode 0x66 0x0f 0x44. */
341FNIEMOP_DEF(iemOp_pclmulqdq_Vdq_Wdq_Ib)
342{
343 IEMOP_MNEMONIC3(RMI, PCLMULQDQ, pclmulqdq, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
344
345 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
346 if (IEM_IS_MODRM_REG_MODE(bRm))
347 {
348 /*
349 * Register, register.
350 */
351 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
352 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
353 IEM_MC_BEGIN(3, 0);
354 IEM_MC_ARG(PRTUINT128U, puDst, 0);
355 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
356 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
357 IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
358 IEM_MC_PREPARE_SSE_USAGE();
359 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
360 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
361 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
362 iemAImpl_pclmulqdq_u128,
363 iemAImpl_pclmulqdq_u128_fallback),
364 puDst, puSrc, bImmArg);
365 IEM_MC_ADVANCE_RIP();
366 IEM_MC_END();
367 }
368 else
369 {
370 /*
371 * Register, memory.
372 */
373 IEM_MC_BEGIN(3, 2);
374 IEM_MC_ARG(PRTUINT128U, puDst, 0);
375 IEM_MC_LOCAL(RTUINT128U, uSrc);
376 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
377 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
378
379 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
380 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
381 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
382 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
383 IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
384 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
385
386 IEM_MC_PREPARE_SSE_USAGE();
387 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
388 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
389 iemAImpl_pclmulqdq_u128,
390 iemAImpl_pclmulqdq_u128_fallback),
391 puDst, puSrc, bImmArg);
392
393 IEM_MC_ADVANCE_RIP();
394 IEM_MC_END();
395 }
396 return VINF_SUCCESS;
397}
398
399
400/* Opcode 0x66 0x0f 0x45 - invalid */
401/* Opcode 0x66 0x0f 0x46 - invalid (vex only) */
402/* Opcode 0x66 0x0f 0x47 - invalid */
403/* Opcode 0x66 0x0f 0x48 - invalid */
404/* Opcode 0x66 0x0f 0x49 - invalid */
405/* Opcode 0x66 0x0f 0x4a - invalid (vex only). */
406/* Opcode 0x66 0x0f 0x4b - invalid (vex only). */
407/* Opcode 0x66 0x0f 0x4c - invalid (vex only). */
408/* Opcode 0x66 0x0f 0x4d - invalid */
409/* Opcode 0x66 0x0f 0x4e - invalid */
410/* Opcode 0x66 0x0f 0x4f - invalid */
411
412
413/* Opcode 0x66 0x0f 0x50 - invalid */
414/* Opcode 0x66 0x0f 0x51 - invalid */
415/* Opcode 0x66 0x0f 0x52 - invalid */
416/* Opcode 0x66 0x0f 0x53 - invalid */
417/* Opcode 0x66 0x0f 0x54 - invalid */
418/* Opcode 0x66 0x0f 0x55 - invalid */
419/* Opcode 0x66 0x0f 0x56 - invalid */
420/* Opcode 0x66 0x0f 0x57 - invalid */
421/* Opcode 0x66 0x0f 0x58 - invalid */
422/* Opcode 0x66 0x0f 0x59 - invalid */
423/* Opcode 0x66 0x0f 0x5a - invalid */
424/* Opcode 0x66 0x0f 0x5b - invalid */
425/* Opcode 0x66 0x0f 0x5c - invalid */
426/* Opcode 0x66 0x0f 0x5d - invalid */
427/* Opcode 0x66 0x0f 0x5e - invalid */
428/* Opcode 0x66 0x0f 0x5f - invalid */
429
430
431/** Opcode 0x66 0x0f 0x60. */
432FNIEMOP_STUB(iemOp_pcmpestrm_Vdq_Wdq_Ib);
433/** Opcode 0x66 0x0f 0x61, */
434FNIEMOP_STUB(iemOp_pcmpestri_Vdq_Wdq_Ib);
435/** Opcode 0x66 0x0f 0x62. */
436FNIEMOP_STUB(iemOp_pcmpistrm_Vdq_Wdq_Ib);
437
438
439/** Opcode 0x66 0x0f 0x63*/
440FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib)
441{
442 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
443 if (IEM_IS_MODRM_REG_MODE(bRm))
444 {
445 /*
446 * Register, register.
447 */
448 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
449 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
450 IEM_MC_BEGIN(4, 1);
451 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
452 IEM_MC_ARG(uint32_t *, pEFlags, 1);
453 IEM_MC_LOCAL(IEMPCMPISTRISRC, Src);
454 IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRISRC, pSrc, Src, 2);
455 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
456 IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
457 IEM_MC_PREPARE_SSE_USAGE();
458 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
459 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
460 IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
461 IEM_MC_REF_EFLAGS(pEFlags);
462 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
463 iemAImpl_pcmpistri_u128,
464 iemAImpl_pcmpistri_u128_fallback),
465 pu32Ecx, pEFlags, pSrc, bImmArg);
466 IEM_MC_ADVANCE_RIP();
467 IEM_MC_END();
468 }
469 else
470 {
471 /*
472 * Register, memory.
473 */
474 IEM_MC_BEGIN(4, 3);
475 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
476 IEM_MC_ARG(uint32_t *, pEFlags, 1);
477 IEM_MC_LOCAL(IEMPCMPISTRISRC, Src);
478 IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRISRC, pSrc, Src, 2);
479 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
480
481 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
482 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
483 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
484 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
485 IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
486 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
487
488 IEM_MC_PREPARE_SSE_USAGE();
489 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
490 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
491 IEM_MC_REF_EFLAGS(pEFlags);
492 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
493 iemAImpl_pcmpistri_u128,
494 iemAImpl_pcmpistri_u128_fallback),
495 pu32Ecx, pEFlags, pSrc, bImmArg);
496 IEM_MC_ADVANCE_RIP();
497 IEM_MC_END();
498 }
499 return VINF_SUCCESS;
500}
501
502
503/* Opcode 0x66 0x0f 0x64 - invalid */
504/* Opcode 0x66 0x0f 0x65 - invalid */
505/* Opcode 0x66 0x0f 0x66 - invalid */
506/* Opcode 0x66 0x0f 0x67 - invalid */
507/* Opcode 0x66 0x0f 0x68 - invalid */
508/* Opcode 0x66 0x0f 0x69 - invalid */
509/* Opcode 0x66 0x0f 0x6a - invalid */
510/* Opcode 0x66 0x0f 0x6b - invalid */
511/* Opcode 0x66 0x0f 0x6c - invalid */
512/* Opcode 0x66 0x0f 0x6d - invalid */
513/* Opcode 0x66 0x0f 0x6e - invalid */
514/* Opcode 0x66 0x0f 0x6f - invalid */
515
516/* Opcodes 0x0f 0x70 thru 0x0f 0xb0 are unused. */
517
518
519/* Opcode 0x0f 0xc0 - invalid */
520/* Opcode 0x0f 0xc1 - invalid */
521/* Opcode 0x0f 0xc2 - invalid */
522/* Opcode 0x0f 0xc3 - invalid */
523/* Opcode 0x0f 0xc4 - invalid */
524/* Opcode 0x0f 0xc5 - invalid */
525/* Opcode 0x0f 0xc6 - invalid */
526/* Opcode 0x0f 0xc7 - invalid */
527/* Opcode 0x0f 0xc8 - invalid */
528/* Opcode 0x0f 0xc9 - invalid */
529/* Opcode 0x0f 0xca - invalid */
530/* Opcode 0x0f 0xcb - invalid */
531/* Opcode 0x0f 0xcc */
532FNIEMOP_STUB(iemOp_sha1rnds4_Vdq_Wdq_Ib);
533/* Opcode 0x0f 0xcd - invalid */
534/* Opcode 0x0f 0xce - invalid */
535/* Opcode 0x0f 0xcf - invalid */
536
537
538/* Opcode 0x66 0x0f 0xd0 - invalid */
539/* Opcode 0x66 0x0f 0xd1 - invalid */
540/* Opcode 0x66 0x0f 0xd2 - invalid */
541/* Opcode 0x66 0x0f 0xd3 - invalid */
542/* Opcode 0x66 0x0f 0xd4 - invalid */
543/* Opcode 0x66 0x0f 0xd5 - invalid */
544/* Opcode 0x66 0x0f 0xd6 - invalid */
545/* Opcode 0x66 0x0f 0xd7 - invalid */
546/* Opcode 0x66 0x0f 0xd8 - invalid */
547/* Opcode 0x66 0x0f 0xd9 - invalid */
548/* Opcode 0x66 0x0f 0xda - invalid */
549/* Opcode 0x66 0x0f 0xdb - invalid */
550/* Opcode 0x66 0x0f 0xdc - invalid */
551/* Opcode 0x66 0x0f 0xdd - invalid */
552/* Opcode 0x66 0x0f 0xde - invalid */
553/* Opcode 0x66 0x0f 0xdf - (aeskeygenassist). */
554FNIEMOP_STUB(iemOp_aeskeygen_Vdq_Wdq_Ib);
555
556
557/* Opcode 0xf2 0x0f 0xf0 - invalid (vex only) */
558
559
560/**
561 * Three byte opcode map, first two bytes are 0x0f 0x3a.
562 * @sa g_apfnVexMap2
563 */
564IEM_STATIC const PFNIEMOP g_apfnThreeByte0f3a[] =
565{
566 /* no prefix, 066h prefix f3h prefix, f2h prefix */
567 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
568 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
569 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
570 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
571 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
572 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
573 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
574 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
575 /* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_roundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
576 /* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_roundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
577 /* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_roundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
578 /* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_roundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
579 /* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_blendps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
580 /* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_blendpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
581 /* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_pblendw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
582 /* 0x0f */ iemOp_palignr_Pq_Qq_Ib, iemOp_palignr_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
583
584 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
585 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
586 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
587 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
588 /* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_pextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
589 /* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_pextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
590 /* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_pextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
591 /* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_extractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
592 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
593 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
594 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
595 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
596 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
597 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
598 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
599 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
600
601 /* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrb_Vdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
602 /* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_insertps_Vdq_UdqMd_Ib,iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
603 /* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrd_q_Vdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
604 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
605 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
606 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
607 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
608 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
609 /* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
610 /* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
611 /* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
612 /* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
613 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
614 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
615 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
616 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
617
618 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
619 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
620 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
621 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
622 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
623 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
624 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
625 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
626 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
627 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
628 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
629 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
630 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
631 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
632 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
633 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
634
635 /* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_dpps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
636 /* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_dppd_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
637 /* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_mpsadbw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
638 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
639 /* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_pclmulqdq_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
640 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
641 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
642 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
643 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
644 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
645 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
646 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
647 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
648 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
649 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
650 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
651
652 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
653 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
654 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
655 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
656 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
657 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
658 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
659 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
660 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
661 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
662 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
663 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
664 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
665 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
666 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
667 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
668
669 /* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
670 /* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
671 /* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
672 /* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
673 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
674 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
675 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
676 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
677 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
678 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
679 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
680 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
681 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
682 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
683 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
684 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
685
686 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
687 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
688 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
689 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
690 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
691 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
692 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
693 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
694 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
695 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
696 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
697 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
698 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
699 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
700 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
701 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
702
703 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
704 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
705 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
706 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
707 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
708 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
709 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
710 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
711 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
712 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
713 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
714 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
715 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
716 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
717 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
718 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
719
720 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
721 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
722 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
723 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
724 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
725 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
726 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
727 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
728 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
729 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
730 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
731 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
732 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
733 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
734 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
735 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
736
737 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
738 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
739 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
740 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
741 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
742 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
743 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
744 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
745 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
746 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
747 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
748 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
749 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
750 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
751 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
752 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
753
754 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
755 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
756 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
757 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
758 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
759 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
760 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
761 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
762 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
763 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
764 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
765 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
766 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
767 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
768 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
769 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
770
771 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
772 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
773 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
774 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
775 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
776 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
777 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
778 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
779 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
780 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
781 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
782 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
783 /* 0xcc */ iemOp_sha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
784 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
785 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
786 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
787
788 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
789 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
790 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
791 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
792 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
793 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
794 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
795 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
796 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
797 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
798 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
799 /* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
800 /* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
801 /* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
802 /* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
803 /* 0xdf */ iemOp_InvalidNeedRMImm8, iemOp_aeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
804
805 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
806 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
807 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
808 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
809 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
810 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
811 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
812 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
813 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
814 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
815 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
816 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
817 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
818 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
819 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
820 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
821
822 /* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
823 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
824 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
825 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
826 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
827 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
828 /* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
829 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
830 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
831 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
832 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
833 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
834 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
835 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
836 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
837 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
838};
839AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f3a) == 1024);
840
841/** @} */
842
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