VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h@ 100594

Last change on this file since 100594 was 99343, checked in by vboxsync, 20 months ago

VMM/IEM: IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT -> IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT, since the CPUID check was removed they are identical. bugref:10369

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File size: 80.1 KB
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1/* $Id: IEMAllInstructionsThree0f3a.cpp.h 99343 2023-04-07 12:44:56Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4 *
5 * @remarks IEMAllInstructionsVexMap3.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name Three byte opcodes with first two bytes 0x0f 0x3a
33 * @{
34 */
35
36/**
37 * Common worker for SSSE3 instructions on the forms:
38 * pxxx xmm1, xmm2/mem128, imm8
39 *
40 * Proper alignment of the 128-bit operand is enforced.
41 * Exceptions type 4. SSSE3 cpuid checks.
42 *
43 * @sa iemOpCommonSse41_FullFullImm8_To_Full
44 */
45FNIEMOP_DEF_1(iemOpCommonSsse3_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
46{
47 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48 if (IEM_IS_MODRM_REG_MODE(bRm))
49 {
50 /*
51 * Register, register.
52 */
53 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
54 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
55 IEM_MC_BEGIN(3, 0);
56 IEM_MC_ARG(PRTUINT128U, puDst, 0);
57 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
58 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
59 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
60 IEM_MC_PREPARE_SSE_USAGE();
61 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
62 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
63 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
64 IEM_MC_ADVANCE_RIP_AND_FINISH();
65 IEM_MC_END();
66 }
67 else
68 {
69 /*
70 * Register, memory.
71 */
72 IEM_MC_BEGIN(3, 2);
73 IEM_MC_ARG(PRTUINT128U, puDst, 0);
74 IEM_MC_LOCAL(RTUINT128U, uSrc);
75 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
76 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
77
78 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
79 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
80 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
81 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
82 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
83 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84
85 IEM_MC_PREPARE_SSE_USAGE();
86 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
88
89 IEM_MC_ADVANCE_RIP_AND_FINISH();
90 IEM_MC_END();
91 }
92}
93
94
95/**
96 * Common worker for SSE 4.1 instructions on the forms:
97 * pxxx xmm1, xmm2/mem128, imm8
98 *
99 * Proper alignment of the 128-bit operand is enforced.
100 * No SIMD exceptions. SSE 4.1 cpuid checks.
101 *
102 * @sa iemOpCommonSsse3_FullFullImm8_To_Full
103 */
104FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
105{
106 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
107 if (IEM_IS_MODRM_REG_MODE(bRm))
108 {
109 /*
110 * XMM, XMM, imm8
111 */
112 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
114 IEM_MC_BEGIN(3, 0);
115 IEM_MC_ARG(PRTUINT128U, puDst, 0);
116 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
117 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
118 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
119 IEM_MC_PREPARE_SSE_USAGE();
120 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
121 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
122 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
123 IEM_MC_ADVANCE_RIP_AND_FINISH();
124 IEM_MC_END();
125 }
126 else
127 {
128 /*
129 * XMM, [mem128], imm8.
130 */
131 IEM_MC_BEGIN(3, 2);
132 IEM_MC_ARG(PRTUINT128U, puDst, 0);
133 IEM_MC_LOCAL(RTUINT128U, uSrc);
134 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
135 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
136
137 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
138 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
139 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
140 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
141 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
142 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143
144 IEM_MC_PREPARE_SSE_USAGE();
145 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
146 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
147
148 IEM_MC_ADVANCE_RIP_AND_FINISH();
149 IEM_MC_END();
150 }
151}
152
153
154/**
155 * Common worker for SSE 4.1 instructions of the form:
156 * xxx xmm1, xmm2/mem128, imm8
157 *
158 * Proper alignment of the 128-bit operand is enforced.
159 * MXCSR is used as input and output.
160 * Exceptions type 4. SSE 4.1 cpuid checks.
161 *
162 * @sa iemOpCommonSse41_FullFullImm8_To_Full
163 */
164FNIEMOP_DEF_1(iemOpCommonSse41Fp_FullFullImm8_To_Full, PFNIEMAIMPLMXCSRF2XMMIMM8, pfnU128)
165{
166 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167 if (IEM_IS_MODRM_REG_MODE(bRm))
168 {
169 /*
170 * XMM, XMM, imm8.
171 */
172 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
174 IEM_MC_BEGIN(4, 2);
175 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
176 IEM_MC_LOCAL(X86XMMREG, Dst);
177 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
178 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
179 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
180 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
181 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
182 IEM_MC_PREPARE_SSE_USAGE();
183 IEM_MC_REF_MXCSR(pfMxcsr);
184 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
185 IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
186 IEM_MC_CALL_VOID_AIMPL_4(pfnU128, pfMxcsr, pDst, pSrc, bImmArg);
187 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
188 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
189
190 IEM_MC_ADVANCE_RIP_AND_FINISH();
191 IEM_MC_END();
192 }
193 else
194 {
195 /*
196 * XMM, [mem128], imm8.
197 */
198 IEM_MC_BEGIN(4, 3);
199 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
200 IEM_MC_LOCAL(X86XMMREG, Dst);
201 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
202 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
203 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
204 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
205
206 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
207 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
208 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
209 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
210 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
211 IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
212
213 IEM_MC_PREPARE_SSE_USAGE();
214 IEM_MC_REF_MXCSR(pfMxcsr);
215 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
216 IEM_MC_CALL_VOID_AIMPL_4(pfnU128, pfMxcsr, pDst, pSrc, bImmArg);
217 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
218 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
219
220 IEM_MC_ADVANCE_RIP_AND_FINISH();
221 IEM_MC_END();
222 }
223}
224
225
226/**
227 * Common worker for SSE-style AES-NI instructions of the form:
228 * aesxxx xmm1, xmm2/mem128, imm8
229 *
230 * Proper alignment of the 128-bit operand is enforced.
231 * Exceptions type 4. AES-NI cpuid checks.
232 *
233 * @sa iemOpCommonSsse3_FullFullImm8_To_Full
234 * @sa iemOpCommonSse41_FullFullImm8_To_Full
235 */
236FNIEMOP_DEF_1(iemOpCommonAesNi_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
237{
238 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
239 if (IEM_IS_MODRM_REG_MODE(bRm))
240 {
241 /*
242 * Register, register.
243 */
244 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
245 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
246 IEM_MC_BEGIN(3, 0);
247 IEM_MC_ARG(PRTUINT128U, puDst, 0);
248 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
249 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
250 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
251 IEM_MC_PREPARE_SSE_USAGE();
252 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
253 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
254 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
255 IEM_MC_ADVANCE_RIP_AND_FINISH();
256 IEM_MC_END();
257 }
258 else
259 {
260 /*
261 * Register, memory.
262 */
263 IEM_MC_BEGIN(3, 2);
264 IEM_MC_ARG(PRTUINT128U, puDst, 0);
265 IEM_MC_LOCAL(RTUINT128U, uSrc);
266 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
267 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
268
269 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
270 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
271 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
272 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
273 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
274 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
275
276 IEM_MC_PREPARE_SSE_USAGE();
277 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
278 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
279
280 IEM_MC_ADVANCE_RIP_AND_FINISH();
281 IEM_MC_END();
282 }
283}
284
285
286/** Opcode 0x66 0x0f 0x00 - invalid (vex only). */
287/** Opcode 0x66 0x0f 0x01 - invalid (vex only). */
288/** Opcode 0x66 0x0f 0x02 - invalid (vex only). */
289/* Opcode 0x66 0x0f 0x03 - invalid */
290/** Opcode 0x66 0x0f 0x04 - invalid (vex only). */
291/** Opcode 0x66 0x0f 0x05 - invalid (vex only). */
292/* Opcode 0x66 0x0f 0x06 - invalid (vex only) */
293/* Opcode 0x66 0x0f 0x07 - invalid */
294/** Opcode 0x66 0x0f 0x08. */
295FNIEMOP_DEF(iemOp_roundps_Vx_Wx_Ib)
296{
297 IEMOP_MNEMONIC3(RMI, ROUNDPS, roundps, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
298 return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
299 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback));
300}
301
302
303/** Opcode 0x66 0x0f 0x09. */
304FNIEMOP_DEF(iemOp_roundpd_Vx_Wx_Ib)
305{
306 IEMOP_MNEMONIC3(RMI, ROUNDPD, roundpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
307 return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
308 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback));
309}
310
311
312/** Opcode 0x66 0x0f 0x0a. */
313FNIEMOP_DEF(iemOp_roundss_Vss_Wss_Ib)
314{
315 /* The instruction form is very similar to CMPSS. */
316 IEMOP_MNEMONIC3(RMI, ROUNDSS, roundss, Vss, Wss, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
317
318 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
319 if (IEM_IS_MODRM_REG_MODE(bRm))
320 {
321 /*
322 * XMM32, XMM32.
323 */
324 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
325 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
326 IEM_MC_BEGIN(4, 2);
327 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
328 IEM_MC_LOCAL(X86XMMREG, Dst);
329 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
330 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
331 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
332 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
333 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
334 IEM_MC_PREPARE_SSE_USAGE();
335 IEM_MC_REF_MXCSR(pfMxcsr);
336 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
337 IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
338 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundss_u128, pfMxcsr, pDst, pSrc, bImmArg);
339 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
340 IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst);
341
342 IEM_MC_ADVANCE_RIP_AND_FINISH();
343 IEM_MC_END();
344 }
345 else
346 {
347 /*
348 * XMM32, [mem32].
349 */
350 IEM_MC_BEGIN(4, 3);
351 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
352 IEM_MC_LOCAL(X86XMMREG, Dst);
353 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
354 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
355 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
356 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
357
358 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
359 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
360 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
361 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
362 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
363 IEM_MC_FETCH_MEM_XMM_U32(Src.uSrc2, 0 /*a_iDword */, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
364
365 IEM_MC_PREPARE_SSE_USAGE();
366 IEM_MC_REF_MXCSR(pfMxcsr);
367 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
368 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundss_u128, pfMxcsr, pDst, pSrc, bImmArg);
369 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
370 IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst);
371
372 IEM_MC_ADVANCE_RIP_AND_FINISH();
373 IEM_MC_END();
374 }
375}
376
377/** Opcode 0x66 0x0f 0x0b. */
378FNIEMOP_DEF(iemOp_roundsd_Vsd_Wsd_Ib)
379{
380 /* The instruction form is very similar to CMPSD. */
381 IEMOP_MNEMONIC3(RMI, ROUNDSD, roundsd, Vsd, Wsd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
382
383 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
384 if (IEM_IS_MODRM_REG_MODE(bRm))
385 {
386 /*
387 * XMM64, XMM64, imm8.
388 */
389 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
390 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
391 IEM_MC_BEGIN(4, 2);
392 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
393 IEM_MC_LOCAL(X86XMMREG, Dst);
394 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
395 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
396 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
397 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
398 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
399 IEM_MC_PREPARE_SSE_USAGE();
400 IEM_MC_REF_MXCSR(pfMxcsr);
401 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
402 IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
403 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundsd_u128, pfMxcsr, pDst, pSrc, bImmArg);
404 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
405 IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst);
406
407 IEM_MC_ADVANCE_RIP_AND_FINISH();
408 IEM_MC_END();
409 }
410 else
411 {
412 /*
413 * XMM64, [mem64], imm8.
414 */
415 IEM_MC_BEGIN(4, 3);
416 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
417 IEM_MC_LOCAL(X86XMMREG, Dst);
418 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
419 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
420 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
421 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
422
423 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
424 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
425 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
426 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
427 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
428 IEM_MC_FETCH_MEM_XMM_U64(Src.uSrc2, 0 /*a_iQword */, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
429
430 IEM_MC_PREPARE_SSE_USAGE();
431 IEM_MC_REF_MXCSR(pfMxcsr);
432 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
433 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundsd_u128, pfMxcsr, pDst, pSrc, bImmArg);
434 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
435 IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst);
436
437 IEM_MC_ADVANCE_RIP_AND_FINISH();
438 IEM_MC_END();
439 }
440}
441
442
443/** Opcode 0x66 0x0f 0x0c. */
444FNIEMOP_DEF(iemOp_blendps_Vx_Wx_Ib)
445{
446 IEMOP_MNEMONIC3(RMI, BLENDPS, blendps, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
447 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
448 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback));
449}
450
451
452/** Opcode 0x66 0x0f 0x0d. */
453FNIEMOP_DEF(iemOp_blendpd_Vx_Wx_Ib)
454{
455 IEMOP_MNEMONIC3(RMI, BLENDPD, blendpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
456 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
457 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback));
458}
459
460
461/** Opcode 0x66 0x0f 0x0e. */
462FNIEMOP_DEF(iemOp_pblendw_Vx_Wx_Ib)
463{
464 IEMOP_MNEMONIC3(RMI, PBLENDW, pblendw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
465 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
466 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback));
467}
468
469
470/** Opcode 0x0f 0x0f. */
471FNIEMOP_DEF(iemOp_palignr_Pq_Qq_Ib)
472{
473 IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Pq, Qq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
474 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
475 if (IEM_IS_MODRM_REG_MODE(bRm))
476 {
477 /*
478 * Register, register.
479 */
480 /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
481 /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
482 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
483 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
484 IEM_MC_BEGIN(3, 0);
485 IEM_MC_ARG(uint64_t *, pDst, 0);
486 IEM_MC_ARG(uint64_t, uSrc, 1);
487 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
488 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
489 IEM_MC_PREPARE_FPU_USAGE();
490 IEM_MC_FPU_TO_MMX_MODE();
491 IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
492 IEM_MC_FETCH_MREG_U64(uSrc, IEM_GET_MODRM_RM_8(bRm));
493 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
494 pDst, uSrc, bImmArg);
495 IEM_MC_MODIFIED_MREG_BY_REF(pDst);
496 IEM_MC_ADVANCE_RIP_AND_FINISH();
497 IEM_MC_END();
498 }
499 else
500 {
501 /*
502 * Register, memory.
503 */
504 IEM_MC_BEGIN(3, 1);
505 IEM_MC_ARG(uint64_t *, pDst, 0);
506 IEM_MC_ARG(uint64_t, uSrc, 1);
507 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
508
509 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
510 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
511 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
512 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
513 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
514 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
515
516 IEM_MC_PREPARE_FPU_USAGE();
517 IEM_MC_FPU_TO_MMX_MODE();
518 IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
519 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
520 pDst, uSrc, bImmArg);
521 IEM_MC_MODIFIED_MREG_BY_REF(pDst);
522
523 IEM_MC_ADVANCE_RIP_AND_FINISH();
524 IEM_MC_END();
525 }
526}
527
528
529/** Opcode 0x66 0x0f 0x0f. */
530FNIEMOP_DEF(iemOp_palignr_Vx_Wx_Ib)
531{
532 IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
533 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFullImm8_To_Full,
534 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback));
535}
536
537
538/* Opcode 0x66 0x0f 0x10 - invalid */
539/* Opcode 0x66 0x0f 0x11 - invalid */
540/* Opcode 0x66 0x0f 0x12 - invalid */
541/* Opcode 0x66 0x0f 0x13 - invalid */
542
543
544/** Opcode 0x66 0x0f 0x14. */
545FNIEMOP_DEF(iemOp_pextrb_RdMb_Vdq_Ib)
546{
547 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
548 IEMOP_MNEMONIC3(MRI, PEXTRB, pextrb, Ev, Vq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
549 if (IEM_IS_MODRM_REG_MODE(bRm))
550 {
551 /*
552 * greg32, XMM.
553 */
554 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
555 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
556 IEM_MC_BEGIN(0, 1);
557 IEM_MC_LOCAL(uint8_t, uValue);
558 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
559 IEM_MC_PREPARE_SSE_USAGE();
560 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/);
561 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
562 IEM_MC_ADVANCE_RIP_AND_FINISH();
563 IEM_MC_END();
564 }
565 else
566 {
567 /*
568 * [mem8], XMM.
569 */
570 IEM_MC_BEGIN(0, 2);
571 IEM_MC_LOCAL(uint8_t, uValue);
572 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
573
574 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
575 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
576 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
577 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
578 IEM_MC_PREPARE_SSE_USAGE();
579
580 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/);
581 IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
582 IEM_MC_ADVANCE_RIP_AND_FINISH();
583 IEM_MC_END();
584 }
585}
586
587
588/** Opcode 0x66 0x0f 0x15. */
589FNIEMOP_DEF(iemOp_pextrw_RdMw_Vdq_Ib)
590{
591 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
592 IEMOP_MNEMONIC3(MRI, PEXTRW, pextrw, Ev, Vq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
593 if (IEM_IS_MODRM_REG_MODE(bRm))
594 {
595 /*
596 * greg32, XMM.
597 */
598 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
599 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
600 IEM_MC_BEGIN(0, 1);
601 IEM_MC_LOCAL(uint16_t, uValue);
602 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
603 IEM_MC_PREPARE_SSE_USAGE();
604 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7 /*a_iWord*/);
605 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
606 IEM_MC_ADVANCE_RIP_AND_FINISH();
607 IEM_MC_END();
608 }
609 else
610 {
611 /*
612 * [mem16], XMM.
613 */
614 IEM_MC_BEGIN(0, 2);
615 IEM_MC_LOCAL(uint16_t, uValue);
616 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
617
618 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
619 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
620 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
621 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
622 IEM_MC_PREPARE_SSE_USAGE();
623
624 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7 /*a_iWord*/);
625 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
626 IEM_MC_ADVANCE_RIP_AND_FINISH();
627 IEM_MC_END();
628 }
629}
630
631
632FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib)
633{
634 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
635 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
636 {
637 /**
638 * @opcode 0x16
639 * @opcodesub rex.w=1
640 * @oppfx 0x66
641 * @opcpuid sse
642 */
643 IEMOP_MNEMONIC3(MRI, PEXTRQ, pextrq, Ev, Vq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
644 if (IEM_IS_MODRM_REG_MODE(bRm))
645 {
646 /*
647 * greg64, XMM.
648 */
649 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
650 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
651 IEM_MC_BEGIN(0, 1);
652 IEM_MC_LOCAL(uint64_t, uSrc);
653 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
654 IEM_MC_PREPARE_SSE_USAGE();
655 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /*a_iQword*/);
656 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
657 IEM_MC_ADVANCE_RIP_AND_FINISH();
658 IEM_MC_END();
659 }
660 else
661 {
662 /*
663 * [mem64], XMM.
664 */
665 IEM_MC_BEGIN(0, 2);
666 IEM_MC_LOCAL(uint64_t, uSrc);
667 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
668
669 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
670 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
671 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
672 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
673 IEM_MC_PREPARE_SSE_USAGE();
674
675 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /*a_iQword*/);
676 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
677 IEM_MC_ADVANCE_RIP_AND_FINISH();
678 IEM_MC_END();
679 }
680 }
681 else
682 {
683 /**
684 * @opdone
685 * @opcode 0x16
686 * @opcodesub rex.w=0
687 * @oppfx 0x66
688 * @opcpuid sse
689 */
690 IEMOP_MNEMONIC3(MRI, PEXTRD, pextrd, Ey, Vd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
691 if (IEM_IS_MODRM_REG_MODE(bRm))
692 {
693 /*
694 * greg32, XMM.
695 */
696 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
697 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
698 IEM_MC_BEGIN(0, 1);
699 IEM_MC_LOCAL(uint32_t, uSrc);
700 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
701 IEM_MC_PREPARE_SSE_USAGE();
702 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/);
703 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
704 IEM_MC_ADVANCE_RIP_AND_FINISH();
705 IEM_MC_END();
706 }
707 else
708 {
709 /*
710 * [mem32], XMM.
711 */
712 IEM_MC_BEGIN(0, 2);
713 IEM_MC_LOCAL(uint32_t, uSrc);
714 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
715
716 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
717 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
718 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
719 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
720 IEM_MC_PREPARE_SSE_USAGE();
721 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/);
722 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
723 IEM_MC_ADVANCE_RIP_AND_FINISH();
724 IEM_MC_END();
725 }
726 }
727}
728
729
730/** Opcode 0x66 0x0f 0x17. */
731FNIEMOP_DEF(iemOp_extractps_Ed_Vdq_Ib)
732{
733 IEMOP_MNEMONIC3(MRI, EXTRACTPS, extractps, Ed, Vdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
734 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
735 if (IEM_IS_MODRM_REG_MODE(bRm))
736 {
737 /*
738 * greg32, XMM.
739 */
740 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
741 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
742 IEM_MC_BEGIN(0, 1);
743 IEM_MC_LOCAL(uint32_t, uSrc);
744 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
745 IEM_MC_PREPARE_SSE_USAGE();
746 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/);
747 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
748 IEM_MC_ADVANCE_RIP_AND_FINISH();
749 IEM_MC_END();
750 }
751 else
752 {
753 /*
754 * [mem32], XMM.
755 */
756 IEM_MC_BEGIN(0, 2);
757 IEM_MC_LOCAL(uint32_t, uSrc);
758 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
759
760 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
761 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
762 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
763 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
764 IEM_MC_PREPARE_SSE_USAGE();
765 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/);
766 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
767 IEM_MC_ADVANCE_RIP_AND_FINISH();
768 IEM_MC_END();
769 }
770}
771
772
773/* Opcode 0x66 0x0f 0x18 - invalid (vex only). */
774/* Opcode 0x66 0x0f 0x19 - invalid (vex only). */
775/* Opcode 0x66 0x0f 0x1a - invalid */
776/* Opcode 0x66 0x0f 0x1b - invalid */
777/* Opcode 0x66 0x0f 0x1c - invalid */
778/* Opcode 0x66 0x0f 0x1d - invalid (vex only). */
779/* Opcode 0x66 0x0f 0x1e - invalid */
780/* Opcode 0x66 0x0f 0x1f - invalid */
781
782
783/** Opcode 0x66 0x0f 0x20. */
784FNIEMOP_DEF(iemOp_pinsrb_Vdq_RyMb_Ib)
785{
786 IEMOP_MNEMONIC3(RMI, PINSRB, pinsrb, Vd, Ey, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
787 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
788 if (IEM_IS_MODRM_REG_MODE(bRm))
789 {
790 /*
791 * XMM, greg32.
792 */
793 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
794 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
795 IEM_MC_BEGIN(0, 1);
796 IEM_MC_LOCAL(uint8_t, uSrc);
797 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
798 IEM_MC_PREPARE_SSE_USAGE();
799 IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
800 IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/, uSrc);
801 IEM_MC_ADVANCE_RIP_AND_FINISH();
802 IEM_MC_END();
803 }
804 else
805 {
806 /*
807 * XMM, [mem8].
808 */
809 IEM_MC_BEGIN(0, 2);
810 IEM_MC_LOCAL(uint8_t, uSrc);
811 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
812
813 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
814 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
815 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
816 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
817 IEM_MC_PREPARE_SSE_USAGE();
818
819 IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
820 IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/, uSrc);
821 IEM_MC_ADVANCE_RIP_AND_FINISH();
822 IEM_MC_END();
823 }
824}
825
826/** Opcode 0x66 0x0f 0x21, */
827FNIEMOP_DEF(iemOp_insertps_Vdq_UdqMd_Ib)
828{
829 IEMOP_MNEMONIC3(RMI, INSERTPS, insertps, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0); /// @todo
830 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
831 if (IEM_IS_MODRM_REG_MODE(bRm))
832 {
833 /*
834 * XMM, XMM.
835 */
836 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
837 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
838 IEM_MC_BEGIN(0, 3);
839 IEM_MC_LOCAL(uint32_t, uSrc);
840 IEM_MC_LOCAL(uint8_t, uSrcSel);
841 IEM_MC_LOCAL(uint8_t, uDstSel);
842 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
843 IEM_MC_PREPARE_SSE_USAGE();
844 IEM_MC_ASSIGN(uSrcSel, bImm);
845 IEM_MC_SHR_LOCAL_U8(uSrcSel, 6);
846 IEM_MC_AND_LOCAL_U8(uSrcSel, 3);
847 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), uSrcSel);
848 IEM_MC_ASSIGN(uDstSel, bImm);
849 IEM_MC_SHR_LOCAL_U8(uDstSel, 4);
850 IEM_MC_AND_LOCAL_U8(uDstSel, 3);
851 IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
852 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uDstSel, uSrc);
853 IEM_MC_ADVANCE_RIP_AND_FINISH();
854 IEM_MC_END();
855 }
856 else
857 {
858 /*
859 * XMM, [mem32].
860 */
861 IEM_MC_BEGIN(0, 3);
862 IEM_MC_LOCAL(uint32_t, uSrc);
863 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
864 IEM_MC_LOCAL(uint8_t, uDstSel);
865
866 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
867 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
868 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
869 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
870 IEM_MC_PREPARE_SSE_USAGE();
871
872 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
873 IEM_MC_ASSIGN(uDstSel, bImm);
874 IEM_MC_SHR_LOCAL_U8(uDstSel, 4);
875 IEM_MC_AND_LOCAL_U8(uDstSel, 3);
876 IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
877 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uDstSel, uSrc);
878 IEM_MC_ADVANCE_RIP_AND_FINISH();
879 IEM_MC_END();
880 }
881}
882
883FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib)
884{
885 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
886 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
887 {
888 /**
889 * @opcode 0x22
890 * @opcodesub rex.w=1
891 * @oppfx 0x66
892 * @opcpuid sse
893 */
894 IEMOP_MNEMONIC3(RMI, PINSRQ, pinsrq, Vq, Ey, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
895 if (IEM_IS_MODRM_REG_MODE(bRm))
896 {
897 /*
898 * XMM, greg64.
899 */
900 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
901 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
902 IEM_MC_BEGIN(0, 1);
903 IEM_MC_LOCAL(uint64_t, uSrc);
904 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
905 IEM_MC_PREPARE_SSE_USAGE();
906 IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
907 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /*a_iQword*/, uSrc);
908 IEM_MC_ADVANCE_RIP_AND_FINISH();
909 IEM_MC_END();
910 }
911 else
912 {
913 /*
914 * XMM, [mem64].
915 */
916 IEM_MC_BEGIN(0, 2);
917 IEM_MC_LOCAL(uint64_t, uSrc);
918 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
919
920 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
921 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
922 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
923 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
924 IEM_MC_PREPARE_SSE_USAGE();
925
926 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
927 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /*a_iQword*/, uSrc);
928 IEM_MC_ADVANCE_RIP_AND_FINISH();
929 IEM_MC_END();
930 }
931 }
932 else
933 {
934 /**
935 * @opdone
936 * @opcode 0x22
937 * @opcodesub rex.w=0
938 * @oppfx 0x66
939 * @opcpuid sse
940 */
941 IEMOP_MNEMONIC3(RMI, PINSRD, pinsrd, Vd, Ey, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
942 if (IEM_IS_MODRM_REG_MODE(bRm))
943 {
944 /*
945 * XMM, greg32.
946 */
947 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
948 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
949 IEM_MC_BEGIN(0, 1);
950 IEM_MC_LOCAL(uint32_t, uSrc);
951 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
952 IEM_MC_PREPARE_SSE_USAGE();
953 IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
954 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/, uSrc);
955 IEM_MC_ADVANCE_RIP_AND_FINISH();
956 IEM_MC_END();
957 }
958 else
959 {
960 /*
961 * XMM, [mem32].
962 */
963 IEM_MC_BEGIN(0, 2);
964 IEM_MC_LOCAL(uint32_t, uSrc);
965 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
966
967 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
968 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
969 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
970 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
971 IEM_MC_PREPARE_SSE_USAGE();
972
973 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
974 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/, uSrc);
975 IEM_MC_ADVANCE_RIP_AND_FINISH();
976 IEM_MC_END();
977 }
978 }
979}
980
981
982/* Opcode 0x66 0x0f 0x23 - invalid */
983/* Opcode 0x66 0x0f 0x24 - invalid */
984/* Opcode 0x66 0x0f 0x25 - invalid */
985/* Opcode 0x66 0x0f 0x26 - invalid */
986/* Opcode 0x66 0x0f 0x27 - invalid */
987/* Opcode 0x66 0x0f 0x28 - invalid */
988/* Opcode 0x66 0x0f 0x29 - invalid */
989/* Opcode 0x66 0x0f 0x2a - invalid */
990/* Opcode 0x66 0x0f 0x2b - invalid */
991/* Opcode 0x66 0x0f 0x2c - invalid */
992/* Opcode 0x66 0x0f 0x2d - invalid */
993/* Opcode 0x66 0x0f 0x2e - invalid */
994/* Opcode 0x66 0x0f 0x2f - invalid */
995
996
997/* Opcode 0x66 0x0f 0x30 - invalid */
998/* Opcode 0x66 0x0f 0x31 - invalid */
999/* Opcode 0x66 0x0f 0x32 - invalid */
1000/* Opcode 0x66 0x0f 0x33 - invalid */
1001/* Opcode 0x66 0x0f 0x34 - invalid */
1002/* Opcode 0x66 0x0f 0x35 - invalid */
1003/* Opcode 0x66 0x0f 0x36 - invalid */
1004/* Opcode 0x66 0x0f 0x37 - invalid */
1005/* Opcode 0x66 0x0f 0x38 - invalid (vex only). */
1006/* Opcode 0x66 0x0f 0x39 - invalid (vex only). */
1007/* Opcode 0x66 0x0f 0x3a - invalid */
1008/* Opcode 0x66 0x0f 0x3b - invalid */
1009/* Opcode 0x66 0x0f 0x3c - invalid */
1010/* Opcode 0x66 0x0f 0x3d - invalid */
1011/* Opcode 0x66 0x0f 0x3e - invalid */
1012/* Opcode 0x66 0x0f 0x3f - invalid */
1013
1014
1015/** Opcode 0x66 0x0f 0x40. */
1016FNIEMOP_DEF(iemOp_dpps_Vx_Wx_Ib)
1017{
1018 IEMOP_MNEMONIC3(RMI, DPPS, dpps, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1019 return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
1020 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback));
1021}
1022
1023
1024/** Opcode 0x66 0x0f 0x41, */
1025FNIEMOP_DEF(iemOp_dppd_Vdq_Wdq_Ib)
1026{
1027 IEMOP_MNEMONIC3(RMI, DPPD, dppd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1028 return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
1029 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback));
1030}
1031
1032
1033/** Opcode 0x66 0x0f 0x42. */
1034FNIEMOP_DEF(iemOp_mpsadbw_Vx_Wx_Ib)
1035{
1036 IEMOP_MNEMONIC3(RMI, MPSADBW, mpsadbw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1037 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
1038 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback));
1039}
1040
1041
1042/* Opcode 0x66 0x0f 0x43 - invalid */
1043
1044
1045/** Opcode 0x66 0x0f 0x44. */
1046FNIEMOP_DEF(iemOp_pclmulqdq_Vdq_Wdq_Ib)
1047{
1048 IEMOP_MNEMONIC3(RMI, PCLMULQDQ, pclmulqdq, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1049
1050 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1051 if (IEM_IS_MODRM_REG_MODE(bRm))
1052 {
1053 /*
1054 * Register, register.
1055 */
1056 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1057 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fPclMul);
1058 IEM_MC_BEGIN(3, 0);
1059 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1060 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1061 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
1062 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1063 IEM_MC_PREPARE_SSE_USAGE();
1064 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1065 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1066 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
1067 iemAImpl_pclmulqdq_u128,
1068 iemAImpl_pclmulqdq_u128_fallback),
1069 puDst, puSrc, bImmArg);
1070 IEM_MC_ADVANCE_RIP_AND_FINISH();
1071 IEM_MC_END();
1072 }
1073 else
1074 {
1075 /*
1076 * Register, memory.
1077 */
1078 IEM_MC_BEGIN(3, 2);
1079 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1080 IEM_MC_LOCAL(RTUINT128U, uSrc);
1081 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1082 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1083
1084 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1085 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1086 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
1087 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fPclMul);
1088 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1089 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1090
1091 IEM_MC_PREPARE_SSE_USAGE();
1092 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1093 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
1094 iemAImpl_pclmulqdq_u128,
1095 iemAImpl_pclmulqdq_u128_fallback),
1096 puDst, puSrc, bImmArg);
1097
1098 IEM_MC_ADVANCE_RIP_AND_FINISH();
1099 IEM_MC_END();
1100 }
1101}
1102
1103
1104/* Opcode 0x66 0x0f 0x45 - invalid */
1105/* Opcode 0x66 0x0f 0x46 - invalid (vex only) */
1106/* Opcode 0x66 0x0f 0x47 - invalid */
1107/* Opcode 0x66 0x0f 0x48 - invalid */
1108/* Opcode 0x66 0x0f 0x49 - invalid */
1109/* Opcode 0x66 0x0f 0x4a - invalid (vex only). */
1110/* Opcode 0x66 0x0f 0x4b - invalid (vex only). */
1111/* Opcode 0x66 0x0f 0x4c - invalid (vex only). */
1112/* Opcode 0x66 0x0f 0x4d - invalid */
1113/* Opcode 0x66 0x0f 0x4e - invalid */
1114/* Opcode 0x66 0x0f 0x4f - invalid */
1115
1116
1117/* Opcode 0x66 0x0f 0x50 - invalid */
1118/* Opcode 0x66 0x0f 0x51 - invalid */
1119/* Opcode 0x66 0x0f 0x52 - invalid */
1120/* Opcode 0x66 0x0f 0x53 - invalid */
1121/* Opcode 0x66 0x0f 0x54 - invalid */
1122/* Opcode 0x66 0x0f 0x55 - invalid */
1123/* Opcode 0x66 0x0f 0x56 - invalid */
1124/* Opcode 0x66 0x0f 0x57 - invalid */
1125/* Opcode 0x66 0x0f 0x58 - invalid */
1126/* Opcode 0x66 0x0f 0x59 - invalid */
1127/* Opcode 0x66 0x0f 0x5a - invalid */
1128/* Opcode 0x66 0x0f 0x5b - invalid */
1129/* Opcode 0x66 0x0f 0x5c - invalid */
1130/* Opcode 0x66 0x0f 0x5d - invalid */
1131/* Opcode 0x66 0x0f 0x5e - invalid */
1132/* Opcode 0x66 0x0f 0x5f - invalid */
1133
1134
1135/** Opcode 0x66 0x0f 0x60. */
1136FNIEMOP_DEF(iemOp_pcmpestrm_Vdq_Wdq_Ib)
1137{
1138 IEMOP_MNEMONIC3(RMI, PCMPESTRM, pcmpestrm, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1139
1140 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1141 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1142 {
1143 if (IEM_IS_MODRM_REG_MODE(bRm))
1144 {
1145 /*
1146 * Register, register.
1147 */
1148 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1149 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1150 IEM_MC_BEGIN(4, 1);
1151 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1152 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1153 IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1154 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1155 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1156 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1157 IEM_MC_PREPARE_SSE_USAGE();
1158 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1159 IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1160 IEM_MC_FETCH_GREG_U64(Src.u64Rax, X86_GREG_xAX);
1161 IEM_MC_FETCH_GREG_U64(Src.u64Rdx, X86_GREG_xDX);
1162 IEM_MC_REF_XREG_U128(puDst, 0 /*xmm0*/);
1163 IEM_MC_REF_EFLAGS(pEFlags);
1164 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1165 iemAImpl_pcmpestrm_u128,
1166 iemAImpl_pcmpestrm_u128_fallback),
1167 puDst, pEFlags, pSrc, bImmArg);
1168 IEM_MC_ADVANCE_RIP_AND_FINISH();
1169 IEM_MC_END();
1170 }
1171 else
1172 {
1173 /*
1174 * Register, memory.
1175 */
1176 IEM_MC_BEGIN(4, 3);
1177 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1178 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1179 IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1180 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1181 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1182
1183 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1184 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1185 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1186 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1187 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1188 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1189
1190 IEM_MC_PREPARE_SSE_USAGE();
1191 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1192 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1193 IEM_MC_FETCH_GREG_U64(Src.u64Rax, X86_GREG_xAX);
1194 IEM_MC_FETCH_GREG_U64(Src.u64Rdx, X86_GREG_xDX);
1195
1196 IEM_MC_REF_EFLAGS(pEFlags);
1197 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1198 iemAImpl_pcmpestri_u128,
1199 iemAImpl_pcmpestri_u128_fallback),
1200 pu32Ecx, pEFlags, pSrc, bImmArg);
1201 IEM_MC_ADVANCE_RIP_AND_FINISH();
1202 IEM_MC_END();
1203 }
1204 }
1205 else
1206 {
1207 if (IEM_IS_MODRM_REG_MODE(bRm))
1208 {
1209 /*
1210 * Register, register.
1211 */
1212 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1213 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1214 IEM_MC_BEGIN(4, 1);
1215 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1216 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1217 IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1218 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1219 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1220 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1221 IEM_MC_PREPARE_SSE_USAGE();
1222 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1223 IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1224 IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rax, X86_GREG_xAX);
1225 IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rdx, X86_GREG_xDX);
1226 IEM_MC_REF_XREG_U128(puDst, 0 /*xmm0*/);
1227 IEM_MC_REF_EFLAGS(pEFlags);
1228 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1229 iemAImpl_pcmpestrm_u128,
1230 iemAImpl_pcmpestrm_u128_fallback),
1231 puDst, pEFlags, pSrc, bImmArg);
1232 IEM_MC_ADVANCE_RIP_AND_FINISH();
1233 IEM_MC_END();
1234 }
1235 else
1236 {
1237 /*
1238 * Register, memory.
1239 */
1240 IEM_MC_BEGIN(4, 3);
1241 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1242 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1243 IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1244 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1245 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1246
1247 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1248 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1249 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1250 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1251 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1252 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1253
1254 IEM_MC_PREPARE_SSE_USAGE();
1255 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1256 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1257 IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rax, X86_GREG_xAX);
1258 IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rdx, X86_GREG_xDX);
1259 IEM_MC_REF_EFLAGS(pEFlags);
1260 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1261 iemAImpl_pcmpestri_u128,
1262 iemAImpl_pcmpestri_u128_fallback),
1263 pu32Ecx, pEFlags, pSrc, bImmArg);
1264 IEM_MC_ADVANCE_RIP_AND_FINISH();
1265 IEM_MC_END();
1266 }
1267 }
1268}
1269
1270
1271/** Opcode 0x66 0x0f 0x61, */
1272FNIEMOP_DEF(iemOp_pcmpestri_Vdq_Wdq_Ib)
1273{
1274 IEMOP_MNEMONIC3(RMI, PCMPESTRI, pcmpestri, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1275
1276 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1277 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1278 {
1279 if (IEM_IS_MODRM_REG_MODE(bRm))
1280 {
1281 /*
1282 * Register, register.
1283 */
1284 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1285 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1286 IEM_MC_BEGIN(4, 1);
1287 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1288 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1289 IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1290 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1291 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1292 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1293 IEM_MC_PREPARE_SSE_USAGE();
1294 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1295 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1296 IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1297 IEM_MC_FETCH_GREG_U64(Src.u64Rax, X86_GREG_xAX);
1298 IEM_MC_FETCH_GREG_U64(Src.u64Rdx, X86_GREG_xDX);
1299 IEM_MC_REF_EFLAGS(pEFlags);
1300 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1301 iemAImpl_pcmpestri_u128,
1302 iemAImpl_pcmpestri_u128_fallback),
1303 pu32Ecx, pEFlags, pSrc, bImmArg);
1304 /** @todo testcase: High dword of RCX cleared? */
1305 IEM_MC_ADVANCE_RIP_AND_FINISH();
1306 IEM_MC_END();
1307 }
1308 else
1309 {
1310 /*
1311 * Register, memory.
1312 */
1313 IEM_MC_BEGIN(4, 3);
1314 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1315 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1316 IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1317 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1318 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1319
1320 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1321 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1322 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1323 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1324 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1325 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1326
1327 IEM_MC_PREPARE_SSE_USAGE();
1328 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1329 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1330 IEM_MC_FETCH_GREG_U64(Src.u64Rax, X86_GREG_xAX);
1331 IEM_MC_FETCH_GREG_U64(Src.u64Rdx, X86_GREG_xDX);
1332 IEM_MC_REF_EFLAGS(pEFlags);
1333 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1334 iemAImpl_pcmpestri_u128,
1335 iemAImpl_pcmpestri_u128_fallback),
1336 pu32Ecx, pEFlags, pSrc, bImmArg);
1337 /** @todo testcase: High dword of RCX cleared? */
1338 IEM_MC_ADVANCE_RIP_AND_FINISH();
1339 IEM_MC_END();
1340 }
1341 }
1342 else
1343 {
1344 if (IEM_IS_MODRM_REG_MODE(bRm))
1345 {
1346 /*
1347 * Register, register.
1348 */
1349 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1350 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1351 IEM_MC_BEGIN(4, 1);
1352 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1353 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1354 IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1355 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1356 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1357 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1358 IEM_MC_PREPARE_SSE_USAGE();
1359 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1360 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1361 IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1362 IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rax, X86_GREG_xAX);
1363 IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rdx, X86_GREG_xDX);
1364 IEM_MC_REF_EFLAGS(pEFlags);
1365 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1366 iemAImpl_pcmpestri_u128,
1367 iemAImpl_pcmpestri_u128_fallback),
1368 pu32Ecx, pEFlags, pSrc, bImmArg);
1369 /** @todo testcase: High dword of RCX cleared? */
1370 IEM_MC_ADVANCE_RIP_AND_FINISH();
1371 IEM_MC_END();
1372 }
1373 else
1374 {
1375 /*
1376 * Register, memory.
1377 */
1378 IEM_MC_BEGIN(4, 3);
1379 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1380 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1381 IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1382 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1383 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1384
1385 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1386 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1387 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1388 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1389 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1390 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1391
1392 IEM_MC_PREPARE_SSE_USAGE();
1393 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1394 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1395 IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rax, X86_GREG_xAX);
1396 IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rdx, X86_GREG_xDX);
1397 IEM_MC_REF_EFLAGS(pEFlags);
1398 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1399 iemAImpl_pcmpestri_u128,
1400 iemAImpl_pcmpestri_u128_fallback),
1401 pu32Ecx, pEFlags, pSrc, bImmArg);
1402 /** @todo testcase: High dword of RCX cleared? */
1403 IEM_MC_ADVANCE_RIP_AND_FINISH();
1404 IEM_MC_END();
1405 }
1406 }
1407}
1408
1409
1410/** Opcode 0x66 0x0f 0x62. */
1411FNIEMOP_DEF(iemOp_pcmpistrm_Vdq_Wdq_Ib)
1412{
1413 IEMOP_MNEMONIC3(RMI, PCMPISTRM, pcmpistrm, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1414
1415 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1416 if (IEM_IS_MODRM_REG_MODE(bRm))
1417 {
1418 /*
1419 * Register, register.
1420 */
1421 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1422 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1423 IEM_MC_BEGIN(4, 1);
1424 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1425 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1426 IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1427 IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1428 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1429 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1430 IEM_MC_PREPARE_SSE_USAGE();
1431 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1432 IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1433 IEM_MC_REF_XREG_U128(puDst, 0 /*xmm0*/);
1434 IEM_MC_REF_EFLAGS(pEFlags);
1435 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1436 iemAImpl_pcmpistrm_u128,
1437 iemAImpl_pcmpistrm_u128_fallback),
1438 puDst, pEFlags, pSrc, bImmArg);
1439 IEM_MC_ADVANCE_RIP_AND_FINISH();
1440 IEM_MC_END();
1441 }
1442 else
1443 {
1444 /*
1445 * Register, memory.
1446 */
1447 IEM_MC_BEGIN(4, 3);
1448 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1449 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1450 IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1451 IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1452 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1453
1454 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1455 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1456 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1457 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1458 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1459 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1460
1461 IEM_MC_PREPARE_SSE_USAGE();
1462 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1463 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1464 IEM_MC_REF_EFLAGS(pEFlags);
1465 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1466 iemAImpl_pcmpistri_u128,
1467 iemAImpl_pcmpistri_u128_fallback),
1468 pu32Ecx, pEFlags, pSrc, bImmArg);
1469 IEM_MC_ADVANCE_RIP_AND_FINISH();
1470 IEM_MC_END();
1471 }
1472}
1473
1474
1475/** Opcode 0x66 0x0f 0x63*/
1476FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib)
1477{
1478 IEMOP_MNEMONIC3(RMI, PCMPISTRI, pcmpistri, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1479
1480 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1481 if (IEM_IS_MODRM_REG_MODE(bRm))
1482 {
1483 /*
1484 * Register, register.
1485 */
1486 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1487 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1488 IEM_MC_BEGIN(4, 1);
1489 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1490 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1491 IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1492 IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1493 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1494 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1495 IEM_MC_PREPARE_SSE_USAGE();
1496 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1497 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1498 IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1499 IEM_MC_REF_EFLAGS(pEFlags);
1500 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1501 iemAImpl_pcmpistri_u128,
1502 iemAImpl_pcmpistri_u128_fallback),
1503 pu32Ecx, pEFlags, pSrc, bImmArg);
1504 /** @todo testcase: High dword of RCX cleared? */
1505 IEM_MC_ADVANCE_RIP_AND_FINISH();
1506 IEM_MC_END();
1507 }
1508 else
1509 {
1510 /*
1511 * Register, memory.
1512 */
1513 IEM_MC_BEGIN(4, 3);
1514 IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1515 IEM_MC_ARG(uint32_t *, pEFlags, 1);
1516 IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1517 IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1518 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1519
1520 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1521 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1522 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1523 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1524 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1525 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1526
1527 IEM_MC_PREPARE_SSE_USAGE();
1528 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1529 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1530 IEM_MC_REF_EFLAGS(pEFlags);
1531 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1532 iemAImpl_pcmpistri_u128,
1533 iemAImpl_pcmpistri_u128_fallback),
1534 pu32Ecx, pEFlags, pSrc, bImmArg);
1535 /** @todo testcase: High dword of RCX cleared? */
1536 IEM_MC_ADVANCE_RIP_AND_FINISH();
1537 IEM_MC_END();
1538 }
1539}
1540
1541
1542/* Opcode 0x66 0x0f 0x64 - invalid */
1543/* Opcode 0x66 0x0f 0x65 - invalid */
1544/* Opcode 0x66 0x0f 0x66 - invalid */
1545/* Opcode 0x66 0x0f 0x67 - invalid */
1546/* Opcode 0x66 0x0f 0x68 - invalid */
1547/* Opcode 0x66 0x0f 0x69 - invalid */
1548/* Opcode 0x66 0x0f 0x6a - invalid */
1549/* Opcode 0x66 0x0f 0x6b - invalid */
1550/* Opcode 0x66 0x0f 0x6c - invalid */
1551/* Opcode 0x66 0x0f 0x6d - invalid */
1552/* Opcode 0x66 0x0f 0x6e - invalid */
1553/* Opcode 0x66 0x0f 0x6f - invalid */
1554
1555/* Opcodes 0x0f 0x70 thru 0x0f 0xb0 are unused. */
1556
1557
1558/* Opcode 0x0f 0xc0 - invalid */
1559/* Opcode 0x0f 0xc1 - invalid */
1560/* Opcode 0x0f 0xc2 - invalid */
1561/* Opcode 0x0f 0xc3 - invalid */
1562/* Opcode 0x0f 0xc4 - invalid */
1563/* Opcode 0x0f 0xc5 - invalid */
1564/* Opcode 0x0f 0xc6 - invalid */
1565/* Opcode 0x0f 0xc7 - invalid */
1566/* Opcode 0x0f 0xc8 - invalid */
1567/* Opcode 0x0f 0xc9 - invalid */
1568/* Opcode 0x0f 0xca - invalid */
1569/* Opcode 0x0f 0xcb - invalid */
1570
1571
1572/* Opcode 0x0f 0xcc */
1573FNIEMOP_DEF(iemOp_sha1rnds4_Vdq_Wdq_Ib)
1574{
1575 IEMOP_MNEMONIC3(RMI, SHA1RNDS4, sha1rnds4, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1576
1577 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1578 if (IEM_IS_MODRM_REG_MODE(bRm))
1579 {
1580 /*
1581 * XMM, XMM, imm8
1582 */
1583 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1584 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
1585 IEM_MC_BEGIN(3, 0);
1586 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1587 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1588 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
1589 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1590 IEM_MC_PREPARE_SSE_USAGE();
1591 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1592 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1593 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha,
1594 iemAImpl_sha1rnds4_u128,
1595 iemAImpl_sha1rnds4_u128_fallback),
1596 puDst, puSrc, bImmArg);
1597 IEM_MC_ADVANCE_RIP_AND_FINISH();
1598 IEM_MC_END();
1599 }
1600 else
1601 {
1602 /*
1603 * XMM, [mem128], imm8.
1604 */
1605 IEM_MC_BEGIN(3, 2);
1606 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1607 IEM_MC_LOCAL(RTUINT128U, uSrc);
1608 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1609 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1610
1611 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1612 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1613 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
1614 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
1615 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1616 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1617
1618 IEM_MC_PREPARE_SSE_USAGE();
1619 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1620 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha,
1621 iemAImpl_sha1rnds4_u128,
1622 iemAImpl_sha1rnds4_u128_fallback),
1623 puDst, puSrc, bImmArg);
1624 IEM_MC_ADVANCE_RIP_AND_FINISH();
1625 IEM_MC_END();
1626 }
1627}
1628
1629
1630/* Opcode 0x0f 0xcd - invalid */
1631/* Opcode 0x0f 0xce - invalid */
1632/* Opcode 0x0f 0xcf - invalid */
1633
1634
1635/* Opcode 0x66 0x0f 0xd0 - invalid */
1636/* Opcode 0x66 0x0f 0xd1 - invalid */
1637/* Opcode 0x66 0x0f 0xd2 - invalid */
1638/* Opcode 0x66 0x0f 0xd3 - invalid */
1639/* Opcode 0x66 0x0f 0xd4 - invalid */
1640/* Opcode 0x66 0x0f 0xd5 - invalid */
1641/* Opcode 0x66 0x0f 0xd6 - invalid */
1642/* Opcode 0x66 0x0f 0xd7 - invalid */
1643/* Opcode 0x66 0x0f 0xd8 - invalid */
1644/* Opcode 0x66 0x0f 0xd9 - invalid */
1645/* Opcode 0x66 0x0f 0xda - invalid */
1646/* Opcode 0x66 0x0f 0xdb - invalid */
1647/* Opcode 0x66 0x0f 0xdc - invalid */
1648/* Opcode 0x66 0x0f 0xdd - invalid */
1649/* Opcode 0x66 0x0f 0xde - invalid */
1650
1651
1652/* Opcode 0x66 0x0f 0xdf - (aeskeygenassist). */
1653FNIEMOP_DEF(iemOp_aeskeygen_Vdq_Wdq_Ib)
1654{
1655 IEMOP_MNEMONIC3(RMI, AESKEYGEN, aeskeygen, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1656 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFullImm8_To_Full,
1657 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback));
1658}
1659
1660
1661/* Opcode 0xf2 0x0f 0xf0 - invalid (vex only) */
1662
1663
1664/**
1665 * Three byte opcode map, first two bytes are 0x0f 0x3a.
1666 * @sa g_apfnVexMap2
1667 */
1668IEM_STATIC const PFNIEMOP g_apfnThreeByte0f3a[] =
1669{
1670 /* no prefix, 066h prefix f3h prefix, f2h prefix */
1671 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1672 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1673 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1674 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1675 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1676 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1677 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1678 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1679 /* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_roundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1680 /* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_roundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1681 /* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_roundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1682 /* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_roundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1683 /* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_blendps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1684 /* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_blendpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1685 /* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_pblendw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1686 /* 0x0f */ iemOp_palignr_Pq_Qq_Ib, iemOp_palignr_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1687
1688 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1689 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1690 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1691 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1692 /* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_pextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1693 /* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_pextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1694 /* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_pextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1695 /* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_extractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1696 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1697 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1698 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1699 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1700 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1701 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1702 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1703 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1704
1705 /* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrb_Vdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1706 /* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_insertps_Vdq_UdqMd_Ib,iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1707 /* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrd_q_Vdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1708 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1709 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1710 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1711 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1712 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1713 /* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1714 /* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1715 /* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1716 /* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1717 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1718 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1719 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1720 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1721
1722 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1723 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1724 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1725 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1726 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1727 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1728 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1729 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1730 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1731 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1732 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1733 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1734 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1735 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1736 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1737 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1738
1739 /* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_dpps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1740 /* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_dppd_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1741 /* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_mpsadbw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1742 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1743 /* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_pclmulqdq_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1744 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1745 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1746 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1747 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1748 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1749 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1750 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1751 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1752 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1753 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1754 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1755
1756 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1757 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1758 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1759 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1760 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1761 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1762 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1763 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1764 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1765 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1766 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1767 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1768 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1769 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1770 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1771 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1772
1773 /* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1774 /* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1775 /* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1776 /* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1777 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1778 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1779 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1780 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1781 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1782 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1783 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1784 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1785 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1786 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1787 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1788 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1789
1790 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1791 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1792 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1793 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1794 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1795 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1796 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1797 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1798 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1799 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1800 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1801 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1802 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1803 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1804 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1805 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1806
1807 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1808 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1809 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1810 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1811 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1812 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1813 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1814 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1815 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1816 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1817 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1818 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1819 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1820 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1821 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1822 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1823
1824 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1825 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1826 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1827 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1828 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1829 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1830 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1831 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1832 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1833 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1834 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1835 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1836 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1837 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1838 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1839 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1840
1841 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1842 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1843 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1844 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1845 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1846 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1847 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1848 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1849 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1850 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1851 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1852 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1853 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1854 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1855 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1856 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1857
1858 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1859 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1860 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1861 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1862 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1863 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1864 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1865 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1866 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1867 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1868 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1869 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1870 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1871 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1872 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1873 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1874
1875 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1876 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1877 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1878 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1879 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1880 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1881 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1882 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1883 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1884 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1885 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1886 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1887 /* 0xcc */ iemOp_sha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1888 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1889 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1890 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1891
1892 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1893 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1894 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1895 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1896 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1897 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1898 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1899 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1900 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1901 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1902 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1903 /* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1904 /* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1905 /* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1906 /* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1907 /* 0xdf */ iemOp_InvalidNeedRMImm8, iemOp_aeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1908
1909 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1910 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1911 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1912 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1913 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1914 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1915 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1916 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1917 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1918 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1919 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1920 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1921 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1922 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1923 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1924 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1925
1926 /* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1927 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1928 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1929 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1930 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1931 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1932 /* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1933 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1934 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1935 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1936 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1937 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1938 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1939 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1940 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1941 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1942};
1943AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f3a) == 1024);
1944
1945/** @} */
1946
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