IEMAllInstructionsThree0f38.cpp.h@ 96438

Last change on this file since 96438 was 96438, checked in by vboxsync, 3 years ago
VMM/IEM: Implement [v]phminposuw instructions, bugref:9898
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1	/* $Id: IEMAllInstructionsThree0f38.cpp.h 96438 2022-08-23 13:16:15Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstructionsVexMap2.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name Three byte opcodes with first two bytes 0x0f 0x38
33	* @{
34	*/
35
36	FNIEMOP_DEF_2(iemOpCommonMmx_FullFull_To_Full_Ex, PFNIEMAIMPLMEDIAF2U64, pfnU64, bool, fSupported); /* in IEMAllInstructionsTwoByteOf.cpp.h */
37
38
39	/**
40	* Common worker for SSSE3 instructions on the forms:
41	* pxxx xmm1, xmm2/mem128
42	*
43	* Proper alignment of the 128-bit operand is enforced.
44	* Exceptions type 4. SSSE3 cpuid checks.
45	*
46	* @sa iemOpCommonSse2_FullFull_To_Full
47	*/
48	FNIEMOP_DEF_1(iemOpCommonSsse3_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
49	{
50	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
51	if (IEM_IS_MODRM_REG_MODE(bRm))
52	{
53	/*
54	* Register, register.
55	*/
56	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
57	IEM_MC_BEGIN(2, 0);
58	IEM_MC_ARG(PRTUINT128U, puDst, 0);
59	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
60	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
61	IEM_MC_PREPARE_SSE_USAGE();
62	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
63	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
64	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
65	IEM_MC_ADVANCE_RIP();
66	IEM_MC_END();
67	}
68	else
69	{
70	/*
71	* Register, memory.
72	*/
73	IEM_MC_BEGIN(2, 2);
74	IEM_MC_ARG(PRTUINT128U, puDst, 0);
75	IEM_MC_LOCAL(RTUINT128U, uSrc);
76	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
77	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
78
79	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
80	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
81	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
82	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
83
84	IEM_MC_PREPARE_SSE_USAGE();
85	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
86	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
87
88	IEM_MC_ADVANCE_RIP();
89	IEM_MC_END();
90	}
91	return VINF_SUCCESS;
92	}
93
94
95	/**
96	* Common worker for SSE4.1 instructions on the forms:
97	* pxxx xmm1, xmm2/mem128
98	*
99	* Proper alignment of the 128-bit operand is enforced.
100	* Exceptions type 4. SSE4.1 cpuid checks.
101	*
102	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
103	* iemOpCommonSse42_FullFull_To_Full
104	*/
105	FNIEMOP_DEF_1(iemOpCommonSse41_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
106	{
107	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
108	if (IEM_IS_MODRM_REG_MODE(bRm))
109	{
110	/*
111	* Register, register.
112	*/
113	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
114	IEM_MC_BEGIN(2, 0);
115	IEM_MC_ARG(PRTUINT128U, puDst, 0);
116	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
117	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
118	IEM_MC_PREPARE_SSE_USAGE();
119	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
120	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
121	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
122	IEM_MC_ADVANCE_RIP();
123	IEM_MC_END();
124	}
125	else
126	{
127	/*
128	* Register, memory.
129	*/
130	IEM_MC_BEGIN(2, 2);
131	IEM_MC_ARG(PRTUINT128U, puDst, 0);
132	IEM_MC_LOCAL(RTUINT128U, uSrc);
133	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
134	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
135
136	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
137	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
138	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
139	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
140
141	IEM_MC_PREPARE_SSE_USAGE();
142	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
143	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
144
145	IEM_MC_ADVANCE_RIP();
146	IEM_MC_END();
147	}
148	return VINF_SUCCESS;
149	}
150
151
152	/**
153	* Common worker for SSE4.1 instructions on the forms:
154	* pxxx xmm1, xmm2/mem128
155	*
156	* Proper alignment of the 128-bit operand is enforced.
157	* Exceptions type 4. SSE4.1 cpuid checks.
158	*
159	* Unlike iemOpCommonSse41_FullFull_To_Full, the @a pfnU128 worker function
160	* takes no FXSAVE state, just the operands.
161	*
162	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
163	* iemOpCommonSse41_FullFull_To_Full, iemOpCommonSse42_FullFull_To_Full
164	*/
165	FNIEMOP_DEF_1(iemOpCommonSse41Opt_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
166	{
167	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
168	if (IEM_IS_MODRM_REG_MODE(bRm))
169	{
170	/*
171	* Register, register.
172	*/
173	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
174	IEM_MC_BEGIN(2, 0);
175	IEM_MC_ARG(PRTUINT128U, puDst, 0);
176	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
177	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
178	IEM_MC_PREPARE_SSE_USAGE();
179	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
180	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
181	IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
182	IEM_MC_ADVANCE_RIP();
183	IEM_MC_END();
184	}
185	else
186	{
187	/*
188	* Register, memory.
189	*/
190	IEM_MC_BEGIN(2, 2);
191	IEM_MC_ARG(PRTUINT128U, puDst, 0);
192	IEM_MC_LOCAL(RTUINT128U, uSrc);
193	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
194	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
195
196	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
197	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
198	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
199	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
200
201	IEM_MC_PREPARE_SSE_USAGE();
202	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
203	IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
204
205	IEM_MC_ADVANCE_RIP();
206	IEM_MC_END();
207	}
208	return VINF_SUCCESS;
209	}
210
211
212	/**
213	* Common worker for SSE4.2 instructions on the forms:
214	* pxxx xmm1, xmm2/mem128
215	*
216	* Proper alignment of the 128-bit operand is enforced.
217	* Exceptions type 4. SSE4.2 cpuid checks.
218	*
219	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
220	* iemOpCommonSse41_FullFull_To_Full
221	*/
222	FNIEMOP_DEF_1(iemOpCommonSse42_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
223	{
224	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
225	if (IEM_IS_MODRM_REG_MODE(bRm))
226	{
227	/*
228	* Register, register.
229	*/
230	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
231	IEM_MC_BEGIN(2, 0);
232	IEM_MC_ARG(PRTUINT128U, puDst, 0);
233	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
234	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
235	IEM_MC_PREPARE_SSE_USAGE();
236	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
237	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
238	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
239	IEM_MC_ADVANCE_RIP();
240	IEM_MC_END();
241	}
242	else
243	{
244	/*
245	* Register, memory.
246	*/
247	IEM_MC_BEGIN(2, 2);
248	IEM_MC_ARG(PRTUINT128U, puDst, 0);
249	IEM_MC_LOCAL(RTUINT128U, uSrc);
250	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
251	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
252
253	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
254	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
255	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
256	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
257
258	IEM_MC_PREPARE_SSE_USAGE();
259	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
260	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
261
262	IEM_MC_ADVANCE_RIP();
263	IEM_MC_END();
264	}
265	return VINF_SUCCESS;
266	}
267
268
269	/** Opcode 0x0f 0x38 0x00. */
270	FNIEMOP_DEF(iemOp_pshufb_Pq_Qq)
271	{
272	IEMOP_MNEMONIC2(RM, PSHUFB, pshufb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
273	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
274	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pshufb_u64,&iemAImpl_pshufb_u64_fallback),
275	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
276	}
277
278
279	/** Opcode 0x66 0x0f 0x38 0x00. */
280	FNIEMOP_DEF(iemOp_pshufb_Vx_Wx)
281	{
282	IEMOP_MNEMONIC2(RM, PSHUFB, pshufb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
283	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
284	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback));
285
286	}
287
288
289	/* Opcode 0x0f 0x38 0x01. */
290	FNIEMOP_DEF(iemOp_phaddw_Pq_Qq)
291	{
292	IEMOP_MNEMONIC2(RM, PHADDW, phaddw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
293	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
294	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddw_u64,&iemAImpl_phaddw_u64_fallback),
295	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
296	}
297
298
299	/** Opcode 0x66 0x0f 0x38 0x01. */
300	FNIEMOP_DEF(iemOp_phaddw_Vx_Wx)
301	{
302	IEMOP_MNEMONIC2(RM, PHADDW, phaddw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
303	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
304	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback));
305
306	}
307
308
309	/** Opcode 0x0f 0x38 0x02. */
310	FNIEMOP_DEF(iemOp_phaddd_Pq_Qq)
311	{
312	IEMOP_MNEMONIC2(RM, PHADDD, phaddd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
313	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
314	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddd_u64,&iemAImpl_phaddd_u64_fallback),
315	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
316	}
317
318
319	/** Opcode 0x66 0x0f 0x38 0x02. */
320	FNIEMOP_DEF(iemOp_phaddd_Vx_Wx)
321	{
322	IEMOP_MNEMONIC2(RM, PHADDD, phaddd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
323	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
324	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback));
325
326	}
327
328
329	/** Opcode 0x0f 0x38 0x03. */
330	FNIEMOP_DEF(iemOp_phaddsw_Pq_Qq)
331	{
332	IEMOP_MNEMONIC2(RM, PHADDSW, phaddsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
333	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
334	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddsw_u64,&iemAImpl_phaddsw_u64_fallback),
335	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
336	}
337
338
339	/** Opcode 0x66 0x0f 0x38 0x03. */
340	FNIEMOP_DEF(iemOp_phaddsw_Vx_Wx)
341	{
342	IEMOP_MNEMONIC2(RM, PHADDSW, phaddsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
343	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
344	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback));
345
346	}
347
348
349	/** Opcode 0x0f 0x38 0x04. */
350	FNIEMOP_DEF(iemOp_pmaddubsw_Pq_Qq)
351	{
352	IEMOP_MNEMONIC2(RM, PMADDUBSW, pmaddubsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
353	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
354	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmaddubsw_u64, &iemAImpl_pmaddubsw_u64_fallback),
355	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
356	}
357
358
359	/** Opcode 0x66 0x0f 0x38 0x04. */
360	FNIEMOP_DEF(iemOp_pmaddubsw_Vx_Wx)
361	{
362	IEMOP_MNEMONIC2(RM, PMADDUBSW, pmaddubsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
363	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
364	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback));
365
366	}
367
368
369	/** Opcode 0x0f 0x38 0x05. */
370	FNIEMOP_DEF(iemOp_phsubw_Pq_Qq)
371	{
372	IEMOP_MNEMONIC2(RM, PHSUBW, phsubw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
373	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
374	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubw_u64,&iemAImpl_phsubw_u64_fallback),
375	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
376	}
377
378
379	/** Opcode 0x66 0x0f 0x38 0x05. */
380	FNIEMOP_DEF(iemOp_phsubw_Vx_Wx)
381	{
382	IEMOP_MNEMONIC2(RM, PHSUBW, phsubw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
383	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
384	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback));
385
386	}
387
388
389	/** Opcode 0x0f 0x38 0x06. */
390	FNIEMOP_DEF(iemOp_phsubd_Pq_Qq)
391	{
392	IEMOP_MNEMONIC2(RM, PHSUBD, phsubd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
393	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
394	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubd_u64,&iemAImpl_phsubd_u64_fallback),
395	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
396	}
397
398
399
400	/** Opcode 0x66 0x0f 0x38 0x06. */
401	FNIEMOP_DEF(iemOp_phsubd_Vx_Wx)
402	{
403	IEMOP_MNEMONIC2(RM, PHSUBD, phsubd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
404	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
405	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback));
406
407	}
408
409
410	/** Opcode 0x0f 0x38 0x07. */
411	FNIEMOP_DEF(iemOp_phsubsw_Pq_Qq)
412	{
413	IEMOP_MNEMONIC2(RM, PHSUBSW, phsubsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
414	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
415	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubsw_u64,&iemAImpl_phsubsw_u64_fallback),
416	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
417	}
418
419
420	/** Opcode 0x66 0x0f 0x38 0x07. */
421	FNIEMOP_DEF(iemOp_phsubsw_Vx_Wx)
422	{
423	IEMOP_MNEMONIC2(RM, PHSUBSW, phsubsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
424	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
425	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback));
426
427	}
428
429
430	/** Opcode 0x0f 0x38 0x08. */
431	FNIEMOP_DEF(iemOp_psignb_Pq_Qq)
432	{
433	IEMOP_MNEMONIC2(RM, PSIGNB, psignb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
434	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
435	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignb_u64, &iemAImpl_psignb_u64_fallback),
436	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
437	}
438
439
440	/** Opcode 0x66 0x0f 0x38 0x08. */
441	FNIEMOP_DEF(iemOp_psignb_Vx_Wx)
442	{
443	IEMOP_MNEMONIC2(RM, PSIGNB, psignb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
444	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
445	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback));
446
447	}
448
449
450	/** Opcode 0x0f 0x38 0x09. */
451	FNIEMOP_DEF(iemOp_psignw_Pq_Qq)
452	{
453	IEMOP_MNEMONIC2(RM, PSIGNW, psignw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
454	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
455	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignw_u64, &iemAImpl_psignw_u64_fallback),
456	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
457	}
458
459
460	/** Opcode 0x66 0x0f 0x38 0x09. */
461	FNIEMOP_DEF(iemOp_psignw_Vx_Wx)
462	{
463	IEMOP_MNEMONIC2(RM, PSIGNW, psignw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
464	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
465	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback));
466
467	}
468
469
470	/** Opcode 0x0f 0x38 0x0a. */
471	FNIEMOP_DEF(iemOp_psignd_Pq_Qq)
472	{
473	IEMOP_MNEMONIC2(RM, PSIGND, psignd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
474	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
475	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignd_u64, &iemAImpl_psignd_u64_fallback),
476	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
477	}
478
479
480	/** Opcode 0x66 0x0f 0x38 0x0a. */
481	FNIEMOP_DEF(iemOp_psignd_Vx_Wx)
482	{
483	IEMOP_MNEMONIC2(RM, PSIGND, psignd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
484	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
485	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback));
486
487	}
488
489
490	/** Opcode 0x0f 0x38 0x0b. */
491	FNIEMOP_DEF(iemOp_pmulhrsw_Pq_Qq)
492	{
493	IEMOP_MNEMONIC2(RM, PMULHRSW, pmulhrsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
494	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
495	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmulhrsw_u64, &iemAImpl_pmulhrsw_u64_fallback),
496	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
497	}
498
499
500	/** Opcode 0x66 0x0f 0x38 0x0b. */
501	FNIEMOP_DEF(iemOp_pmulhrsw_Vx_Wx)
502	{
503	IEMOP_MNEMONIC2(RM, PMULHRSW, pmulhrsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
504	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
505	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback));
506
507	}
508
509
510	/* Opcode 0x0f 0x38 0x0c - invalid. */
511	/* Opcode 0x66 0x0f 0x38 0x0c - invalid (vex only). */
512	/* Opcode 0x0f 0x38 0x0d - invalid. */
513	/* Opcode 0x66 0x0f 0x38 0x0d - invalid (vex only). */
514	/* Opcode 0x0f 0x38 0x0e - invalid. */
515	/* Opcode 0x66 0x0f 0x38 0x0e - invalid (vex only). */
516	/* Opcode 0x0f 0x38 0x0f - invalid. */
517	/* Opcode 0x66 0x0f 0x38 0x0f - invalid (vex only). */
518
519
520	/* Opcode 0x0f 0x38 0x10 - invalid */
521	/** Opcode 0x66 0x0f 0x38 0x10 (legacy only). */
522	FNIEMOP_STUB(iemOp_pblendvb_Vdq_Wdq);
523	/* Opcode 0x0f 0x38 0x11 - invalid */
524	/* Opcode 0x66 0x0f 0x38 0x11 - invalid */
525	/* Opcode 0x0f 0x38 0x12 - invalid */
526	/* Opcode 0x66 0x0f 0x38 0x12 - invalid */
527	/* Opcode 0x0f 0x38 0x13 - invalid */
528	/* Opcode 0x66 0x0f 0x38 0x13 - invalid (vex only). */
529	/* Opcode 0x0f 0x38 0x14 - invalid */
530	/** Opcode 0x66 0x0f 0x38 0x14 (legacy only). */
531	FNIEMOP_STUB(iemOp_blendvps_Vdq_Wdq);
532	/* Opcode 0x0f 0x38 0x15 - invalid */
533	/** Opcode 0x66 0x0f 0x38 0x15 (legacy only). */
534	FNIEMOP_STUB(iemOp_blendvpd_Vdq_Wdq);
535	/* Opcode 0x0f 0x38 0x16 - invalid */
536	/* Opcode 0x66 0x0f 0x38 0x16 - invalid (vex only). */
537	/* Opcode 0x0f 0x38 0x17 - invalid */
538
539
540	/** Opcode 0x66 0x0f 0x38 0x17 - invalid */
541	FNIEMOP_DEF(iemOp_ptest_Vx_Wx)
542	{
543	IEMOP_MNEMONIC2(RM, PTEST, ptest, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
544	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
545	if (IEM_IS_MODRM_REG_MODE(bRm))
546	{
547	/*
548	* Register, register.
549	*/
550	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
551	IEM_MC_BEGIN(3, 0);
552	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
553	IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
554	IEM_MC_ARG(uint32_t *, pEFlags, 2);
555	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
556	IEM_MC_PREPARE_SSE_USAGE();
557	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
558	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
559	IEM_MC_REF_EFLAGS(pEFlags);
560	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
561	IEM_MC_ADVANCE_RIP();
562	IEM_MC_END();
563	}
564	else
565	{
566	/*
567	* Register, memory.
568	*/
569	IEM_MC_BEGIN(3, 2);
570	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
571	IEM_MC_LOCAL(RTUINT128U, uSrc2);
572	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
573	IEM_MC_ARG(uint32_t *, pEFlags, 2);
574	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
575
576	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
577	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
578	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
579	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
580
581	IEM_MC_PREPARE_SSE_USAGE();
582	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
583	IEM_MC_REF_EFLAGS(pEFlags);
584	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
585
586	IEM_MC_ADVANCE_RIP();
587	IEM_MC_END();
588	}
589	return VINF_SUCCESS;
590	}
591
592
593	/* Opcode 0x0f 0x38 0x18 - invalid */
594	/* Opcode 0x66 0x0f 0x38 0x18 - invalid (vex only). */
595	/* Opcode 0x0f 0x38 0x19 - invalid */
596	/* Opcode 0x66 0x0f 0x38 0x19 - invalid (vex only). */
597	/* Opcode 0x0f 0x38 0x1a - invalid */
598	/* Opcode 0x66 0x0f 0x38 0x1a - invalid (vex only). */
599	/* Opcode 0x0f 0x38 0x1b - invalid */
600	/* Opcode 0x66 0x0f 0x38 0x1b - invalid */
601
602
603	/** Opcode 0x0f 0x38 0x1c. */
604	FNIEMOP_DEF(iemOp_pabsb_Pq_Qq)
605	{
606	IEMOP_MNEMONIC2(RM, PABSB, pabsb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
607	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
608	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsb_u64, &iemAImpl_pabsb_u64_fallback),
609	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
610	}
611
612
613	/** Opcode 0x66 0x0f 0x38 0x1c. */
614	FNIEMOP_DEF(iemOp_pabsb_Vx_Wx)
615	{
616	IEMOP_MNEMONIC2(RM, PABSB, pabsb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
617	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
618	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback));
619
620	}
621
622
623	/** Opcode 0x0f 0x38 0x1d. */
624	FNIEMOP_DEF(iemOp_pabsw_Pq_Qq)
625	{
626	IEMOP_MNEMONIC2(RM, PABSW, pabsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
627	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
628	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsw_u64, &iemAImpl_pabsw_u64_fallback),
629	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
630	}
631
632
633	/** Opcode 0x66 0x0f 0x38 0x1d. */
634	FNIEMOP_DEF(iemOp_pabsw_Vx_Wx)
635	{
636	IEMOP_MNEMONIC2(RM, PABSW, pabsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
637	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
638	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback));
639
640	}
641
642
643	/** Opcode 0x0f 0x38 0x1e. */
644	FNIEMOP_DEF(iemOp_pabsd_Pq_Qq)
645	{
646	IEMOP_MNEMONIC2(RM, PABSD, pabsd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
647	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
648	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsd_u64, &iemAImpl_pabsd_u64_fallback),
649	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
650	}
651
652
653	/** Opcode 0x66 0x0f 0x38 0x1e. */
654	FNIEMOP_DEF(iemOp_pabsd_Vx_Wx)
655	{
656	IEMOP_MNEMONIC2(RM, PABSD, pabsd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
657	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
658	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback));
659
660	}
661
662
663	/* Opcode 0x0f 0x38 0x1f - invalid */
664	/* Opcode 0x66 0x0f 0x38 0x1f - invalid */
665
666
667	/** Body for the pmov{s,z}x* instructions. */
668	#define IEMOP_BODY_PMOV_S_Z(a_Instr, a_SrcWidth) \
669	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
670	if (IEM_IS_MODRM_REG_MODE(bRm)) \
671	{ \
672	/* \
673	* Register, register. \
674	*/ \
675	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
676	IEM_MC_BEGIN(2, 0); \
677	IEM_MC_ARG(PRTUINT128U, puDst, 0); \
678	IEM_MC_ARG(uint64_t, uSrc, 1); \
679	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); \
680	IEM_MC_PREPARE_SSE_USAGE(); \
681	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
682	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
683	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse41, \
684	iemAImpl_ ## a_Instr ## _u128, \
685	iemAImpl_v ## a_Instr ## _u128_fallback), \
686	puDst, uSrc); \
687	IEM_MC_ADVANCE_RIP(); \
688	IEM_MC_END(); \
689	} \
690	else \
691	{ \
692	/* \
693	* Register, memory. \
694	*/ \
695	IEM_MC_BEGIN(2, 2); \
696	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
697	IEM_MC_ARG(PRTUINT128U, puDst, 0); \
698	IEM_MC_ARG(uint ## a_SrcWidth ## _t, uSrc, 1); \
699	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
700	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
701	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT(); \
702	IEM_MC_PREPARE_SSE_USAGE(); \
703	IEM_MC_FETCH_MEM_U## a_SrcWidth (uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
704	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
705	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse41, \
706	iemAImpl_ ## a_Instr ## _u128, \
707	iemAImpl_v ## a_Instr ## _u128_fallback), \
708	puDst, uSrc); \
709	IEM_MC_ADVANCE_RIP(); \
710	IEM_MC_END(); \
711	} \
712	return VINF_SUCCESS
713
714
715	/** Opcode 0x66 0x0f 0x38 0x20. */
716	FNIEMOP_DEF(iemOp_pmovsxbw_Vx_UxMq)
717	{
718	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
719	IEMOP_MNEMONIC2(RM, PMOVSXBW, pmovsxbw, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
720	IEMOP_BODY_PMOV_S_Z(pmovsxbw, 64);
721	}
722
723
724	/** Opcode 0x66 0x0f 0x38 0x21. */
725	FNIEMOP_DEF(iemOp_pmovsxbd_Vx_UxMd)
726	{
727	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
728	IEMOP_MNEMONIC2(RM, PMOVSXBD, pmovsxbd, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
729	IEMOP_BODY_PMOV_S_Z(pmovsxbd, 32);
730	}
731
732
733	/** Opcode 0x66 0x0f 0x38 0x22. */
734	FNIEMOP_DEF(iemOp_pmovsxbq_Vx_UxMw)
735	{
736	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
737	IEMOP_MNEMONIC2(RM, PMOVSXBQ, pmovsxbq, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
738	IEMOP_BODY_PMOV_S_Z(pmovsxbq, 16);
739	}
740
741
742	/** Opcode 0x66 0x0f 0x38 0x23. */
743	FNIEMOP_DEF(iemOp_pmovsxwd_Vx_UxMq)
744	{
745	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
746	IEMOP_MNEMONIC2(RM, PMOVSXWD, pmovsxwd, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
747	IEMOP_BODY_PMOV_S_Z(pmovsxwd, 64);
748	}
749
750
751	/** Opcode 0x66 0x0f 0x38 0x24. */
752	FNIEMOP_DEF(iemOp_pmovsxwq_Vx_UxMd)
753	{
754	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
755	IEMOP_MNEMONIC2(RM, PMOVSXWQ, pmovsxwq, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
756	IEMOP_BODY_PMOV_S_Z(pmovsxwq, 32);
757	}
758
759
760	/** Opcode 0x66 0x0f 0x38 0x25. */
761	FNIEMOP_DEF(iemOp_pmovsxdq_Vx_UxMq)
762	{
763	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
764	IEMOP_MNEMONIC2(RM, PMOVSXDQ, pmovsxdq, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
765	IEMOP_BODY_PMOV_S_Z(pmovsxdq, 64);
766	}
767
768
769	/* Opcode 0x66 0x0f 0x38 0x26 - invalid */
770	/* Opcode 0x66 0x0f 0x38 0x27 - invalid */
771
772
773	/** Opcode 0x66 0x0f 0x38 0x28. */
774	FNIEMOP_DEF(iemOp_pmuldq_Vx_Wx)
775	{
776	IEMOP_MNEMONIC2(RM, PMULDQ, pmuldq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
777	return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
778	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback));
779	}
780
781
782	/** Opcode 0x66 0x0f 0x38 0x29. */
783	FNIEMOP_DEF(iemOp_pcmpeqq_Vx_Wx)
784	{
785	IEMOP_MNEMONIC2(RM, PCMPEQQ, pcmpeqq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
786	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
787	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback));
788	}
789
790
791	/**
792	* @opcode 0x2a
793	* @opcodesub !11 mr/reg
794	* @oppfx 0x66
795	* @opcpuid sse4.1
796	* @opgroup og_sse41_cachect
797	* @opxcpttype 1
798	* @optest op1=-1 op2=2 -> op1=2
799	* @optest op1=0 op2=-42 -> op1=-42
800	*/
801	FNIEMOP_DEF(iemOp_movntdqa_Vdq_Mdq)
802	{
803	IEMOP_MNEMONIC2(RM_MEM, MOVNTDQA, movntdqa, Vdq_WO, Mdq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
804	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
805	if (IEM_IS_MODRM_MEM_MODE(bRm))
806	{
807	/* Register, memory. */
808	IEM_MC_BEGIN(0, 2);
809	IEM_MC_LOCAL(RTUINT128U, uSrc);
810	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
811
812	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
813	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
814	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
815	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
816
817	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
818	IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
819
820	IEM_MC_ADVANCE_RIP();
821	IEM_MC_END();
822	return VINF_SUCCESS;
823	}
824
825	/**
826	* @opdone
827	* @opmnemonic ud660f382areg
828	* @opcode 0x2a
829	* @opcodesub 11 mr/reg
830	* @oppfx 0x66
831	* @opunused immediate
832	* @opcpuid sse
833	* @optest ->
834	*/
835	return IEMOP_RAISE_INVALID_OPCODE();
836	}
837
838
839	/** Opcode 0x66 0x0f 0x38 0x2b. */
840	FNIEMOP_DEF(iemOp_packusdw_Vx_Wx)
841	{
842	IEMOP_MNEMONIC2(RM, PACKUSDW, packusdw, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
843	return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full, iemAImpl_packusdw_u128);
844	}
845
846
847	/* Opcode 0x66 0x0f 0x38 0x2c - invalid (vex only). */
848	/* Opcode 0x66 0x0f 0x38 0x2d - invalid (vex only). */
849	/* Opcode 0x66 0x0f 0x38 0x2e - invalid (vex only). */
850	/* Opcode 0x66 0x0f 0x38 0x2f - invalid (vex only). */
851
852	/** Opcode 0x66 0x0f 0x38 0x30. */
853	FNIEMOP_DEF(iemOp_pmovzxbw_Vx_UxMq)
854	{
855	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
856	IEMOP_MNEMONIC2(RM, PMOVZXBW, pmovzxbw, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
857	IEMOP_BODY_PMOV_S_Z(pmovzxbw, 64);
858	}
859
860
861	/** Opcode 0x66 0x0f 0x38 0x31. */
862	FNIEMOP_DEF(iemOp_pmovzxbd_Vx_UxMd)
863	{
864	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
865	IEMOP_MNEMONIC2(RM, PMOVZXBD, pmovzxbd, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
866	IEMOP_BODY_PMOV_S_Z(pmovzxbd, 32);
867	}
868
869
870	/** Opcode 0x66 0x0f 0x38 0x32. */
871	FNIEMOP_DEF(iemOp_pmovzxbq_Vx_UxMw)
872	{
873	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
874	IEMOP_MNEMONIC2(RM, PMOVZXBQ, pmovzxbq, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
875	IEMOP_BODY_PMOV_S_Z(pmovzxbq, 16);
876	}
877
878
879	/** Opcode 0x66 0x0f 0x38 0x33. */
880	FNIEMOP_DEF(iemOp_pmovzxwd_Vx_UxMq)
881	{
882	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
883	IEMOP_MNEMONIC2(RM, PMOVZXWD, pmovzxwd, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
884	IEMOP_BODY_PMOV_S_Z(pmovzxwd, 64);
885	}
886
887
888	/** Opcode 0x66 0x0f 0x38 0x34. */
889	FNIEMOP_DEF(iemOp_pmovzxwq_Vx_UxMd)
890	{
891	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
892	IEMOP_MNEMONIC2(RM, PMOVZXWQ, pmovzxwq, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
893	IEMOP_BODY_PMOV_S_Z(pmovzxwq, 32);
894	}
895
896
897	/** Opcode 0x66 0x0f 0x38 0x35. */
898	FNIEMOP_DEF(iemOp_pmovzxdq_Vx_UxMq)
899	{
900	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
901	IEMOP_MNEMONIC2(RM, PMOVZXDQ, pmovzxdq, Vx, Wq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
902	IEMOP_BODY_PMOV_S_Z(pmovzxdq, 64);
903	}
904
905
906	/* Opcode 0x66 0x0f 0x38 0x36 - invalid (vex only). */
907
908
909	/** Opcode 0x66 0x0f 0x38 0x37. */
910	FNIEMOP_DEF(iemOp_pcmpgtq_Vx_Wx)
911	{
912	IEMOP_MNEMONIC2(RM, PCMPGTQ, pcmpgtq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
913	return FNIEMOP_CALL_1(iemOpCommonSse42_FullFull_To_Full,
914	IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback));
915	}
916
917
918	/** Opcode 0x66 0x0f 0x38 0x38. */
919	FNIEMOP_DEF(iemOp_pminsb_Vx_Wx)
920	{
921	IEMOP_MNEMONIC2(RM, PMINSB, pminsb, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
922	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
923	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback));
924	}
925
926
927	/** Opcode 0x66 0x0f 0x38 0x39. */
928	FNIEMOP_DEF(iemOp_pminsd_Vx_Wx)
929	{
930	IEMOP_MNEMONIC2(RM, PMINSD, pminsd, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
931	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
932	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback));
933	}
934
935
936	/** Opcode 0x66 0x0f 0x38 0x3a. */
937	FNIEMOP_DEF(iemOp_pminuw_Vx_Wx)
938	{
939	IEMOP_MNEMONIC2(RM, PMINUW, pminuw, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
940	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
941	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback));
942	}
943
944
945	/** Opcode 0x66 0x0f 0x38 0x3b. */
946	FNIEMOP_DEF(iemOp_pminud_Vx_Wx)
947	{
948	IEMOP_MNEMONIC2(RM, PMINUD, pminud, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
949	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
950	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback));
951	}
952
953
954	/** Opcode 0x66 0x0f 0x38 0x3c. */
955	FNIEMOP_DEF(iemOp_pmaxsb_Vx_Wx)
956	{
957	IEMOP_MNEMONIC2(RM, PMAXSB, pmaxsb, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
958	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
959	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback));
960	}
961
962
963	/** Opcode 0x66 0x0f 0x38 0x3d. */
964	FNIEMOP_DEF(iemOp_pmaxsd_Vx_Wx)
965	{
966	IEMOP_MNEMONIC2(RM, PMAXSD, pmaxsd, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
967	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
968	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback));
969	}
970
971
972	/** Opcode 0x66 0x0f 0x38 0x3e. */
973	FNIEMOP_DEF(iemOp_pmaxuw_Vx_Wx)
974	{
975	IEMOP_MNEMONIC2(RM, PMAXUW, pmaxuw, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
976	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
977	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback));
978	}
979
980
981	/** Opcode 0x66 0x0f 0x38 0x3f. */
982	FNIEMOP_DEF(iemOp_pmaxud_Vx_Wx)
983	{
984	IEMOP_MNEMONIC2(RM, PMAXUD, pmaxud, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
985	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
986	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback));
987	}
988
989
990	/** Opcode 0x66 0x0f 0x38 0x40. */
991	FNIEMOP_DEF(iemOp_pmulld_Vx_Wx)
992	{
993	IEMOP_MNEMONIC2(RM, PMULLD, pmulld, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
994	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
995	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback));
996	}
997
998
999	/** Opcode 0x66 0x0f 0x38 0x41. */
1000	FNIEMOP_DEF(iemOp_phminposuw_Vdq_Wdq)
1001	{
1002	IEMOP_MNEMONIC2(RM, PHMINPOSUW, phminposuw, Vdq, Wdq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1003	return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1004	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback));
1005	}
1006
1007
1008	/* Opcode 0x66 0x0f 0x38 0x42 - invalid. */
1009	/* Opcode 0x66 0x0f 0x38 0x43 - invalid. */
1010	/* Opcode 0x66 0x0f 0x38 0x44 - invalid. */
1011	/* Opcode 0x66 0x0f 0x38 0x45 - invalid (vex only). */
1012	/* Opcode 0x66 0x0f 0x38 0x46 - invalid (vex only). */
1013	/* Opcode 0x66 0x0f 0x38 0x47 - invalid (vex only). */
1014	/* Opcode 0x66 0x0f 0x38 0x48 - invalid. */
1015	/* Opcode 0x66 0x0f 0x38 0x49 - invalid. */
1016	/* Opcode 0x66 0x0f 0x38 0x4a - invalid. */
1017	/* Opcode 0x66 0x0f 0x38 0x4b - invalid. */
1018	/* Opcode 0x66 0x0f 0x38 0x4c - invalid. */
1019	/* Opcode 0x66 0x0f 0x38 0x4d - invalid. */
1020	/* Opcode 0x66 0x0f 0x38 0x4e - invalid. */
1021	/* Opcode 0x66 0x0f 0x38 0x4f - invalid. */
1022
1023	/* Opcode 0x66 0x0f 0x38 0x50 - invalid. */
1024	/* Opcode 0x66 0x0f 0x38 0x51 - invalid. */
1025	/* Opcode 0x66 0x0f 0x38 0x52 - invalid. */
1026	/* Opcode 0x66 0x0f 0x38 0x53 - invalid. */
1027	/* Opcode 0x66 0x0f 0x38 0x54 - invalid. */
1028	/* Opcode 0x66 0x0f 0x38 0x55 - invalid. */
1029	/* Opcode 0x66 0x0f 0x38 0x56 - invalid. */
1030	/* Opcode 0x66 0x0f 0x38 0x57 - invalid. */
1031	/* Opcode 0x66 0x0f 0x38 0x58 - invalid (vex only). */
1032	/* Opcode 0x66 0x0f 0x38 0x59 - invalid (vex only). */
1033	/* Opcode 0x66 0x0f 0x38 0x5a - invalid (vex only). */
1034	/* Opcode 0x66 0x0f 0x38 0x5b - invalid. */
1035	/* Opcode 0x66 0x0f 0x38 0x5c - invalid. */
1036	/* Opcode 0x66 0x0f 0x38 0x5d - invalid. */
1037	/* Opcode 0x66 0x0f 0x38 0x5e - invalid. */
1038	/* Opcode 0x66 0x0f 0x38 0x5f - invalid. */
1039
1040	/* Opcode 0x66 0x0f 0x38 0x60 - invalid. */
1041	/* Opcode 0x66 0x0f 0x38 0x61 - invalid. */
1042	/* Opcode 0x66 0x0f 0x38 0x62 - invalid. */
1043	/* Opcode 0x66 0x0f 0x38 0x63 - invalid. */
1044	/* Opcode 0x66 0x0f 0x38 0x64 - invalid. */
1045	/* Opcode 0x66 0x0f 0x38 0x65 - invalid. */
1046	/* Opcode 0x66 0x0f 0x38 0x66 - invalid. */
1047	/* Opcode 0x66 0x0f 0x38 0x67 - invalid. */
1048	/* Opcode 0x66 0x0f 0x38 0x68 - invalid. */
1049	/* Opcode 0x66 0x0f 0x38 0x69 - invalid. */
1050	/* Opcode 0x66 0x0f 0x38 0x6a - invalid. */
1051	/* Opcode 0x66 0x0f 0x38 0x6b - invalid. */
1052	/* Opcode 0x66 0x0f 0x38 0x6c - invalid. */
1053	/* Opcode 0x66 0x0f 0x38 0x6d - invalid. */
1054	/* Opcode 0x66 0x0f 0x38 0x6e - invalid. */
1055	/* Opcode 0x66 0x0f 0x38 0x6f - invalid. */
1056
1057	/* Opcode 0x66 0x0f 0x38 0x70 - invalid. */
1058	/* Opcode 0x66 0x0f 0x38 0x71 - invalid. */
1059	/* Opcode 0x66 0x0f 0x38 0x72 - invalid. */
1060	/* Opcode 0x66 0x0f 0x38 0x73 - invalid. */
1061	/* Opcode 0x66 0x0f 0x38 0x74 - invalid. */
1062	/* Opcode 0x66 0x0f 0x38 0x75 - invalid. */
1063	/* Opcode 0x66 0x0f 0x38 0x76 - invalid. */
1064	/* Opcode 0x66 0x0f 0x38 0x77 - invalid. */
1065	/* Opcode 0x66 0x0f 0x38 0x78 - invalid (vex only). */
1066	/* Opcode 0x66 0x0f 0x38 0x79 - invalid (vex only). */
1067	/* Opcode 0x66 0x0f 0x38 0x7a - invalid. */
1068	/* Opcode 0x66 0x0f 0x38 0x7b - invalid. */
1069	/* Opcode 0x66 0x0f 0x38 0x7c - invalid. */
1070	/* Opcode 0x66 0x0f 0x38 0x7d - invalid. */
1071	/* Opcode 0x66 0x0f 0x38 0x7e - invalid. */
1072	/* Opcode 0x66 0x0f 0x38 0x7f - invalid. */
1073
1074	/** Opcode 0x66 0x0f 0x38 0x80. */
1075	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1076	FNIEMOP_DEF(iemOp_invept_Gy_Mdq)
1077	{
1078	IEMOP_MNEMONIC(invept, "invept Gy,Mdq");
1079	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1080	IEMOP_HLP_IN_VMX_OPERATION("invept", kVmxVDiag_Invept);
1081	IEMOP_HLP_VMX_INSTR("invept", kVmxVDiag_Invept);
1082	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1083	if (IEM_IS_MODRM_MEM_MODE(bRm))
1084	{
1085	/* Register, memory. */
1086	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
1087	{
1088	IEM_MC_BEGIN(3, 0);
1089	IEM_MC_ARG(uint8_t, iEffSeg, 0);
1090	IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
1091	IEM_MC_ARG(uint64_t, uInveptType, 2);
1092	IEM_MC_FETCH_GREG_U64(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
1093	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
1094	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1095	IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
1096	IEM_MC_END();
1097	}
1098	else
1099	{
1100	IEM_MC_BEGIN(3, 0);
1101	IEM_MC_ARG(uint8_t, iEffSeg, 0);
1102	IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
1103	IEM_MC_ARG(uint32_t, uInveptType, 2);
1104	IEM_MC_FETCH_GREG_U32(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
1105	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
1106	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1107	IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
1108	IEM_MC_END();
1109	}
1110	}
1111	Log(("iemOp_invept_Gy_Mdq: invalid encoding -> #UD\n"));
1112	return IEMOP_RAISE_INVALID_OPCODE();
1113	}
1114	#else
1115	FNIEMOP_STUB(iemOp_invept_Gy_Mdq);
1116	#endif
1117
1118	/** Opcode 0x66 0x0f 0x38 0x81. */
1119	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1120	FNIEMOP_DEF(iemOp_invvpid_Gy_Mdq)
1121	{
1122	IEMOP_MNEMONIC(invvpid, "invvpid Gy,Mdq");
1123	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1124	IEMOP_HLP_IN_VMX_OPERATION("invvpid", kVmxVDiag_Invvpid);
1125	IEMOP_HLP_VMX_INSTR("invvpid", kVmxVDiag_Invvpid);
1126	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1127	if (IEM_IS_MODRM_MEM_MODE(bRm))
1128	{
1129	/* Register, memory. */
1130	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
1131	{
1132	IEM_MC_BEGIN(3, 0);
1133	IEM_MC_ARG(uint8_t, iEffSeg, 0);
1134	IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
1135	IEM_MC_ARG(uint64_t, uInvvpidType, 2);
1136	IEM_MC_FETCH_GREG_U64(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1137	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
1138	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1139	IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
1140	IEM_MC_END();
1141	}
1142	else
1143	{
1144	IEM_MC_BEGIN(3, 0);
1145	IEM_MC_ARG(uint8_t, iEffSeg, 0);
1146	IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
1147	IEM_MC_ARG(uint32_t, uInvvpidType, 2);
1148	IEM_MC_FETCH_GREG_U32(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1149	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
1150	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1151	IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
1152	IEM_MC_END();
1153	}
1154	}
1155	Log(("iemOp_invvpid_Gy_Mdq: invalid encoding -> #UD\n"));
1156	return IEMOP_RAISE_INVALID_OPCODE();
1157	}
1158	#else
1159	FNIEMOP_STUB(iemOp_invvpid_Gy_Mdq);
1160	#endif
1161
1162	/** Opcode 0x66 0x0f 0x38 0x82. */
1163	FNIEMOP_DEF(iemOp_invpcid_Gy_Mdq)
1164	{
1165	IEMOP_MNEMONIC(invpcid, "invpcid Gy,Mdq");
1166	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1167	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1168	if (IEM_IS_MODRM_MEM_MODE(bRm))
1169	{
1170	/* Register, memory. */
1171	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
1172	{
1173	IEM_MC_BEGIN(3, 0);
1174	IEM_MC_ARG(uint8_t, iEffSeg, 0);
1175	IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
1176	IEM_MC_ARG(uint64_t, uInvpcidType, 2);
1177	IEM_MC_FETCH_GREG_U64(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1178	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
1179	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1180	IEM_MC_CALL_CIMPL_3(iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
1181	IEM_MC_END();
1182	}
1183	else
1184	{
1185	IEM_MC_BEGIN(3, 0);
1186	IEM_MC_ARG(uint8_t, iEffSeg, 0);
1187	IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
1188	IEM_MC_ARG(uint32_t, uInvpcidType, 2);
1189	IEM_MC_FETCH_GREG_U32(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1190	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
1191	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1192	IEM_MC_CALL_CIMPL_3(iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
1193	IEM_MC_END();
1194	}
1195	}
1196	Log(("iemOp_invpcid_Gy_Mdq: invalid encoding -> #UD\n"));
1197	return IEMOP_RAISE_INVALID_OPCODE();
1198	}
1199
1200
1201	/* Opcode 0x66 0x0f 0x38 0x83 - invalid. */
1202	/* Opcode 0x66 0x0f 0x38 0x84 - invalid. */
1203	/* Opcode 0x66 0x0f 0x38 0x85 - invalid. */
1204	/* Opcode 0x66 0x0f 0x38 0x86 - invalid. */
1205	/* Opcode 0x66 0x0f 0x38 0x87 - invalid. */
1206	/* Opcode 0x66 0x0f 0x38 0x88 - invalid. */
1207	/* Opcode 0x66 0x0f 0x38 0x89 - invalid. */
1208	/* Opcode 0x66 0x0f 0x38 0x8a - invalid. */
1209	/* Opcode 0x66 0x0f 0x38 0x8b - invalid. */
1210	/* Opcode 0x66 0x0f 0x38 0x8c - invalid (vex only). */
1211	/* Opcode 0x66 0x0f 0x38 0x8d - invalid. */
1212	/* Opcode 0x66 0x0f 0x38 0x8e - invalid (vex only). */
1213	/* Opcode 0x66 0x0f 0x38 0x8f - invalid. */
1214
1215	/* Opcode 0x66 0x0f 0x38 0x90 - invalid (vex only). */
1216	/* Opcode 0x66 0x0f 0x38 0x91 - invalid (vex only). */
1217	/* Opcode 0x66 0x0f 0x38 0x92 - invalid (vex only). */
1218	/* Opcode 0x66 0x0f 0x38 0x93 - invalid (vex only). */
1219	/* Opcode 0x66 0x0f 0x38 0x94 - invalid. */
1220	/* Opcode 0x66 0x0f 0x38 0x95 - invalid. */
1221	/* Opcode 0x66 0x0f 0x38 0x96 - invalid (vex only). */
1222	/* Opcode 0x66 0x0f 0x38 0x97 - invalid (vex only). */
1223	/* Opcode 0x66 0x0f 0x38 0x98 - invalid (vex only). */
1224	/* Opcode 0x66 0x0f 0x38 0x99 - invalid (vex only). */
1225	/* Opcode 0x66 0x0f 0x38 0x9a - invalid (vex only). */
1226	/* Opcode 0x66 0x0f 0x38 0x9b - invalid (vex only). */
1227	/* Opcode 0x66 0x0f 0x38 0x9c - invalid (vex only). */
1228	/* Opcode 0x66 0x0f 0x38 0x9d - invalid (vex only). */
1229	/* Opcode 0x66 0x0f 0x38 0x9e - invalid (vex only). */
1230	/* Opcode 0x66 0x0f 0x38 0x9f - invalid (vex only). */
1231
1232	/* Opcode 0x66 0x0f 0x38 0xa0 - invalid. */
1233	/* Opcode 0x66 0x0f 0x38 0xa1 - invalid. */
1234	/* Opcode 0x66 0x0f 0x38 0xa2 - invalid. */
1235	/* Opcode 0x66 0x0f 0x38 0xa3 - invalid. */
1236	/* Opcode 0x66 0x0f 0x38 0xa4 - invalid. */
1237	/* Opcode 0x66 0x0f 0x38 0xa5 - invalid. */
1238	/* Opcode 0x66 0x0f 0x38 0xa6 - invalid (vex only). */
1239	/* Opcode 0x66 0x0f 0x38 0xa7 - invalid (vex only). */
1240	/* Opcode 0x66 0x0f 0x38 0xa8 - invalid (vex only). */
1241	/* Opcode 0x66 0x0f 0x38 0xa9 - invalid (vex only). */
1242	/* Opcode 0x66 0x0f 0x38 0xaa - invalid (vex only). */
1243	/* Opcode 0x66 0x0f 0x38 0xab - invalid (vex only). */
1244	/* Opcode 0x66 0x0f 0x38 0xac - invalid (vex only). */
1245	/* Opcode 0x66 0x0f 0x38 0xad - invalid (vex only). */
1246	/* Opcode 0x66 0x0f 0x38 0xae - invalid (vex only). */
1247	/* Opcode 0x66 0x0f 0x38 0xaf - invalid (vex only). */
1248
1249	/* Opcode 0x66 0x0f 0x38 0xb0 - invalid. */
1250	/* Opcode 0x66 0x0f 0x38 0xb1 - invalid. */
1251	/* Opcode 0x66 0x0f 0x38 0xb2 - invalid. */
1252	/* Opcode 0x66 0x0f 0x38 0xb3 - invalid. */
1253	/* Opcode 0x66 0x0f 0x38 0xb4 - invalid. */
1254	/* Opcode 0x66 0x0f 0x38 0xb5 - invalid. */
1255	/* Opcode 0x66 0x0f 0x38 0xb6 - invalid (vex only). */
1256	/* Opcode 0x66 0x0f 0x38 0xb7 - invalid (vex only). */
1257	/* Opcode 0x66 0x0f 0x38 0xb8 - invalid (vex only). */
1258	/* Opcode 0x66 0x0f 0x38 0xb9 - invalid (vex only). */
1259	/* Opcode 0x66 0x0f 0x38 0xba - invalid (vex only). */
1260	/* Opcode 0x66 0x0f 0x38 0xbb - invalid (vex only). */
1261	/* Opcode 0x66 0x0f 0x38 0xbc - invalid (vex only). */
1262	/* Opcode 0x66 0x0f 0x38 0xbd - invalid (vex only). */
1263	/* Opcode 0x66 0x0f 0x38 0xbe - invalid (vex only). */
1264	/* Opcode 0x66 0x0f 0x38 0xbf - invalid (vex only). */
1265
1266	/* Opcode 0x0f 0x38 0xc0 - invalid. */
1267	/* Opcode 0x66 0x0f 0x38 0xc0 - invalid. */
1268	/* Opcode 0x0f 0x38 0xc1 - invalid. */
1269	/* Opcode 0x66 0x0f 0x38 0xc1 - invalid. */
1270	/* Opcode 0x0f 0x38 0xc2 - invalid. */
1271	/* Opcode 0x66 0x0f 0x38 0xc2 - invalid. */
1272	/* Opcode 0x0f 0x38 0xc3 - invalid. */
1273	/* Opcode 0x66 0x0f 0x38 0xc3 - invalid. */
1274	/* Opcode 0x0f 0x38 0xc4 - invalid. */
1275	/* Opcode 0x66 0x0f 0x38 0xc4 - invalid. */
1276	/* Opcode 0x0f 0x38 0xc5 - invalid. */
1277	/* Opcode 0x66 0x0f 0x38 0xc5 - invalid. */
1278	/* Opcode 0x0f 0x38 0xc6 - invalid. */
1279	/* Opcode 0x66 0x0f 0x38 0xc6 - invalid. */
1280	/* Opcode 0x0f 0x38 0xc7 - invalid. */
1281	/* Opcode 0x66 0x0f 0x38 0xc7 - invalid. */
1282	/** Opcode 0x0f 0x38 0xc8. */
1283	FNIEMOP_STUB(iemOp_sha1nexte_Vdq_Wdq);
1284	/* Opcode 0x66 0x0f 0x38 0xc8 - invalid. */
1285	/** Opcode 0x0f 0x38 0xc9. */
1286	FNIEMOP_STUB(iemOp_sha1msg1_Vdq_Wdq);
1287	/* Opcode 0x66 0x0f 0x38 0xc9 - invalid. */
1288	/** Opcode 0x0f 0x38 0xca. */
1289	FNIEMOP_STUB(iemOp_sha1msg2_Vdq_Wdq);
1290	/* Opcode 0x66 0x0f 0x38 0xca - invalid. */
1291	/** Opcode 0x0f 0x38 0xcb. */
1292	FNIEMOP_STUB(iemOp_sha256rnds2_Vdq_Wdq);
1293	/* Opcode 0x66 0x0f 0x38 0xcb - invalid. */
1294	/** Opcode 0x0f 0x38 0xcc. */
1295	FNIEMOP_STUB(iemOp_sha256msg1_Vdq_Wdq);
1296	/* Opcode 0x66 0x0f 0x38 0xcc - invalid. */
1297	/** Opcode 0x0f 0x38 0xcd. */
1298	FNIEMOP_STUB(iemOp_sha256msg2_Vdq_Wdq);
1299	/* Opcode 0x66 0x0f 0x38 0xcd - invalid. */
1300	/* Opcode 0x0f 0x38 0xce - invalid. */
1301	/* Opcode 0x66 0x0f 0x38 0xce - invalid. */
1302	/* Opcode 0x0f 0x38 0xcf - invalid. */
1303	/* Opcode 0x66 0x0f 0x38 0xcf - invalid. */
1304
1305	/* Opcode 0x66 0x0f 0x38 0xd0 - invalid. */
1306	/* Opcode 0x66 0x0f 0x38 0xd1 - invalid. */
1307	/* Opcode 0x66 0x0f 0x38 0xd2 - invalid. */
1308	/* Opcode 0x66 0x0f 0x38 0xd3 - invalid. */
1309	/* Opcode 0x66 0x0f 0x38 0xd4 - invalid. */
1310	/* Opcode 0x66 0x0f 0x38 0xd5 - invalid. */
1311	/* Opcode 0x66 0x0f 0x38 0xd6 - invalid. */
1312	/* Opcode 0x66 0x0f 0x38 0xd7 - invalid. */
1313	/* Opcode 0x66 0x0f 0x38 0xd8 - invalid. */
1314	/* Opcode 0x66 0x0f 0x38 0xd9 - invalid. */
1315	/* Opcode 0x66 0x0f 0x38 0xda - invalid. */
1316	/** Opcode 0x66 0x0f 0x38 0xdb. */
1317	FNIEMOP_STUB(iemOp_aesimc_Vdq_Wdq);
1318	/** Opcode 0x66 0x0f 0x38 0xdc. */
1319	FNIEMOP_STUB(iemOp_aesenc_Vdq_Wdq);
1320	/** Opcode 0x66 0x0f 0x38 0xdd. */
1321	FNIEMOP_STUB(iemOp_aesenclast_Vdq_Wdq);
1322	/** Opcode 0x66 0x0f 0x38 0xde. */
1323	FNIEMOP_STUB(iemOp_aesdec_Vdq_Wdq);
1324	/** Opcode 0x66 0x0f 0x38 0xdf. */
1325	FNIEMOP_STUB(iemOp_aesdeclast_Vdq_Wdq);
1326
1327	/* Opcode 0x66 0x0f 0x38 0xe0 - invalid. */
1328	/* Opcode 0x66 0x0f 0x38 0xe1 - invalid. */
1329	/* Opcode 0x66 0x0f 0x38 0xe2 - invalid. */
1330	/* Opcode 0x66 0x0f 0x38 0xe3 - invalid. */
1331	/* Opcode 0x66 0x0f 0x38 0xe4 - invalid. */
1332	/* Opcode 0x66 0x0f 0x38 0xe5 - invalid. */
1333	/* Opcode 0x66 0x0f 0x38 0xe6 - invalid. */
1334	/* Opcode 0x66 0x0f 0x38 0xe7 - invalid. */
1335	/* Opcode 0x66 0x0f 0x38 0xe8 - invalid. */
1336	/* Opcode 0x66 0x0f 0x38 0xe9 - invalid. */
1337	/* Opcode 0x66 0x0f 0x38 0xea - invalid. */
1338	/* Opcode 0x66 0x0f 0x38 0xeb - invalid. */
1339	/* Opcode 0x66 0x0f 0x38 0xec - invalid. */
1340	/* Opcode 0x66 0x0f 0x38 0xed - invalid. */
1341	/* Opcode 0x66 0x0f 0x38 0xee - invalid. */
1342	/* Opcode 0x66 0x0f 0x38 0xef - invalid. */
1343
1344
1345	/** Opcode 0x0f 0x38 0xf0. */
1346	FNIEMOP_STUB(iemOp_movbe_Gy_My);
1347	/** Opcode 0x66 0x0f 0x38 0xf0. */
1348	FNIEMOP_STUB(iemOp_movbe_Gw_Mw);
1349	/* Opcode 0xf3 0x0f 0x38 0xf0 - invalid. */
1350
1351
1352	/** Opcode 0xf2 0x0f 0x38 0xf0. */
1353	FNIEMOP_DEF(iemOp_crc32_Gd_Eb)
1354	{
1355	IEMOP_MNEMONIC2(RM, CRC32, crc32, Gd, Eb, DISOPTYPE_HARMLESS, 0);
1356	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42)
1357	return iemOp_InvalidNeedRM(pVCpu);
1358
1359	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1360	if (IEM_IS_MODRM_REG_MODE(bRm))
1361	{
1362	/*
1363	* Register, register.
1364	*/
1365	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1366	IEM_MC_BEGIN(2, 0);
1367	IEM_MC_ARG(uint32_t *, puDst, 0);
1368	IEM_MC_ARG(uint8_t, uSrc, 1);
1369	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1370	IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1371	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc);
1372	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1373	IEM_MC_ADVANCE_RIP();
1374	IEM_MC_END();
1375	}
1376	else
1377	{
1378	/*
1379	* Register, memory.
1380	*/
1381	IEM_MC_BEGIN(2, 1);
1382	IEM_MC_ARG(uint32_t *, puDst, 0);
1383	IEM_MC_ARG(uint8_t, uSrc, 1);
1384	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1385
1386	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1387	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1388	IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1389
1390	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1391	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc);
1392	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1393
1394	IEM_MC_ADVANCE_RIP();
1395	IEM_MC_END();
1396	}
1397	return VINF_SUCCESS;
1398	}
1399
1400
1401	/** Opcode 0x0f 0x38 0xf1. */
1402	FNIEMOP_STUB(iemOp_movbe_My_Gy);
1403	/** Opcode 0x66 0x0f 0x38 0xf1. */
1404	FNIEMOP_STUB(iemOp_movbe_Mw_Gw);
1405	/* Opcode 0xf3 0x0f 0x38 0xf1 - invalid. */
1406
1407
1408	/** Opcode 0xf2 0x0f 0x38 0xf1. */
1409	FNIEMOP_DEF(iemOp_crc32_Gv_Ev)
1410	{
1411	IEMOP_MNEMONIC2(RM, CRC32, crc32, Gd, Ev, DISOPTYPE_HARMLESS, 0);
1412	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42)
1413	return iemOp_InvalidNeedRM(pVCpu);
1414
1415	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1416	if (IEM_IS_MODRM_REG_MODE(bRm))
1417	{
1418	/*
1419	* Register, register.
1420	*/
1421	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1422	switch (pVCpu->iem.s.enmEffOpSize)
1423	{
1424	case IEMMODE_16BIT:
1425	IEM_MC_BEGIN(2, 0);
1426	IEM_MC_ARG(uint32_t *, puDst, 0);
1427	IEM_MC_ARG(uint16_t, uSrc, 1);
1428	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1429	IEM_MC_FETCH_GREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1430	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback),
1431	puDst, uSrc);
1432	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1433	IEM_MC_ADVANCE_RIP();
1434	IEM_MC_END();
1435	return VINF_SUCCESS;
1436
1437	case IEMMODE_32BIT:
1438	IEM_MC_BEGIN(2, 0);
1439	IEM_MC_ARG(uint32_t *, puDst, 0);
1440	IEM_MC_ARG(uint32_t, uSrc, 1);
1441	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1442	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1443	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback),
1444	puDst, uSrc);
1445	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1446	IEM_MC_ADVANCE_RIP();
1447	IEM_MC_END();
1448	return VINF_SUCCESS;
1449
1450	case IEMMODE_64BIT:
1451	IEM_MC_BEGIN(2, 0);
1452	IEM_MC_ARG(uint32_t *, puDst, 0);
1453	IEM_MC_ARG(uint64_t, uSrc, 1);
1454	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1455	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1456	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback),
1457	puDst, uSrc);
1458	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1459	IEM_MC_ADVANCE_RIP();
1460	IEM_MC_END();
1461	return VINF_SUCCESS;
1462
1463	IEM_NOT_REACHED_DEFAULT_CASE_RET();
1464	}
1465	}
1466	else
1467	{
1468	/*
1469	* Register, memory.
1470	*/
1471	switch (pVCpu->iem.s.enmEffOpSize)
1472	{
1473	case IEMMODE_16BIT:
1474	IEM_MC_BEGIN(2, 1);
1475	IEM_MC_ARG(uint32_t *, puDst, 0);
1476	IEM_MC_ARG(uint16_t, uSrc, 1);
1477	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1478
1479	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1480	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1481	IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1482
1483	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1484	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback),
1485	puDst, uSrc);
1486	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1487
1488	IEM_MC_ADVANCE_RIP();
1489	IEM_MC_END();
1490	return VINF_SUCCESS;
1491
1492	case IEMMODE_32BIT:
1493	IEM_MC_BEGIN(2, 1);
1494	IEM_MC_ARG(uint32_t *, puDst, 0);
1495	IEM_MC_ARG(uint32_t, uSrc, 1);
1496	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1497
1498	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1499	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1500	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1501
1502	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1503	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback),
1504	puDst, uSrc);
1505	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1506
1507	IEM_MC_ADVANCE_RIP();
1508	IEM_MC_END();
1509	return VINF_SUCCESS;
1510
1511	case IEMMODE_64BIT:
1512	IEM_MC_BEGIN(2, 1);
1513	IEM_MC_ARG(uint32_t *, puDst, 0);
1514	IEM_MC_ARG(uint64_t, uSrc, 1);
1515	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1516
1517	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1518	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1519	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1520
1521	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1522	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback),
1523	puDst, uSrc);
1524	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1525
1526	IEM_MC_ADVANCE_RIP();
1527	IEM_MC_END();
1528	return VINF_SUCCESS;
1529
1530	IEM_NOT_REACHED_DEFAULT_CASE_RET();
1531	}
1532	}
1533	}
1534
1535
1536	/* Opcode 0x0f 0x38 0xf2 - invalid (vex only). */
1537	/* Opcode 0x66 0x0f 0x38 0xf2 - invalid. */
1538	/* Opcode 0xf3 0x0f 0x38 0xf2 - invalid. */
1539	/* Opcode 0xf2 0x0f 0x38 0xf2 - invalid. */
1540
1541	/* Opcode 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1542	/* Opcode 0x66 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1543	/* Opcode 0xf3 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1544	/* Opcode 0xf2 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1545
1546	/* Opcode 0x0f 0x38 0xf4 - invalid. */
1547	/* Opcode 0x66 0x0f 0x38 0xf4 - invalid. */
1548	/* Opcode 0xf3 0x0f 0x38 0xf4 - invalid. */
1549	/* Opcode 0xf2 0x0f 0x38 0xf4 - invalid. */
1550
1551	/* Opcode 0x0f 0x38 0xf5 - invalid (vex only). */
1552	/* Opcode 0x66 0x0f 0x38 0xf5 - invalid. */
1553	/* Opcode 0xf3 0x0f 0x38 0xf5 - invalid (vex only). */
1554	/* Opcode 0xf2 0x0f 0x38 0xf5 - invalid (vex only). */
1555
1556	/* Opcode 0x0f 0x38 0xf6 - invalid. */
1557	/** Opcode 0x66 0x0f 0x38 0xf6. */
1558	FNIEMOP_STUB(iemOp_adcx_Gy_Ey);
1559	/** Opcode 0xf3 0x0f 0x38 0xf6. */
1560	FNIEMOP_STUB(iemOp_adox_Gy_Ey);
1561	/* Opcode 0xf2 0x0f 0x38 0xf6 - invalid (vex only). */
1562
1563	/* Opcode 0x0f 0x38 0xf7 - invalid (vex only). */
1564	/* Opcode 0x66 0x0f 0x38 0xf7 - invalid (vex only). */
1565	/* Opcode 0xf3 0x0f 0x38 0xf7 - invalid (vex only). */
1566	/* Opcode 0xf2 0x0f 0x38 0xf7 - invalid (vex only). */
1567
1568	/* Opcode 0x0f 0x38 0xf8 - invalid. */
1569	/* Opcode 0x66 0x0f 0x38 0xf8 - invalid. */
1570	/* Opcode 0xf3 0x0f 0x38 0xf8 - invalid. */
1571	/* Opcode 0xf2 0x0f 0x38 0xf8 - invalid. */
1572
1573	/* Opcode 0x0f 0x38 0xf9 - invalid. */
1574	/* Opcode 0x66 0x0f 0x38 0xf9 - invalid. */
1575	/* Opcode 0xf3 0x0f 0x38 0xf9 - invalid. */
1576	/* Opcode 0xf2 0x0f 0x38 0xf9 - invalid. */
1577
1578	/* Opcode 0x0f 0x38 0xfa - invalid. */
1579	/* Opcode 0x66 0x0f 0x38 0xfa - invalid. */
1580	/* Opcode 0xf3 0x0f 0x38 0xfa - invalid. */
1581	/* Opcode 0xf2 0x0f 0x38 0xfa - invalid. */
1582
1583	/* Opcode 0x0f 0x38 0xfb - invalid. */
1584	/* Opcode 0x66 0x0f 0x38 0xfb - invalid. */
1585	/* Opcode 0xf3 0x0f 0x38 0xfb - invalid. */
1586	/* Opcode 0xf2 0x0f 0x38 0xfb - invalid. */
1587
1588	/* Opcode 0x0f 0x38 0xfc - invalid. */
1589	/* Opcode 0x66 0x0f 0x38 0xfc - invalid. */
1590	/* Opcode 0xf3 0x0f 0x38 0xfc - invalid. */
1591	/* Opcode 0xf2 0x0f 0x38 0xfc - invalid. */
1592
1593	/* Opcode 0x0f 0x38 0xfd - invalid. */
1594	/* Opcode 0x66 0x0f 0x38 0xfd - invalid. */
1595	/* Opcode 0xf3 0x0f 0x38 0xfd - invalid. */
1596	/* Opcode 0xf2 0x0f 0x38 0xfd - invalid. */
1597
1598	/* Opcode 0x0f 0x38 0xfe - invalid. */
1599	/* Opcode 0x66 0x0f 0x38 0xfe - invalid. */
1600	/* Opcode 0xf3 0x0f 0x38 0xfe - invalid. */
1601	/* Opcode 0xf2 0x0f 0x38 0xfe - invalid. */
1602
1603	/* Opcode 0x0f 0x38 0xff - invalid. */
1604	/* Opcode 0x66 0x0f 0x38 0xff - invalid. */
1605	/* Opcode 0xf3 0x0f 0x38 0xff - invalid. */
1606	/* Opcode 0xf2 0x0f 0x38 0xff - invalid. */
1607
1608
1609	/**
1610	* Three byte opcode map, first two bytes are 0x0f 0x38.
1611	* @sa g_apfnVexMap2
1612	*/
1613	IEM_STATIC const PFNIEMOP g_apfnThreeByte0f38[] =
1614	{
1615	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1616	/* 0x00 */ iemOp_pshufb_Pq_Qq, iemOp_pshufb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1617	/* 0x01 */ iemOp_phaddw_Pq_Qq, iemOp_phaddw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1618	/* 0x02 */ iemOp_phaddd_Pq_Qq, iemOp_phaddd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1619	/* 0x03 */ iemOp_phaddsw_Pq_Qq, iemOp_phaddsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1620	/* 0x04 */ iemOp_pmaddubsw_Pq_Qq, iemOp_pmaddubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1621	/* 0x05 */ iemOp_phsubw_Pq_Qq, iemOp_phsubw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1622	/* 0x06 */ iemOp_phsubd_Pq_Qq, iemOp_phsubd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1623	/* 0x07 */ iemOp_phsubsw_Pq_Qq, iemOp_phsubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1624	/* 0x08 */ iemOp_psignb_Pq_Qq, iemOp_psignb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1625	/* 0x09 */ iemOp_psignw_Pq_Qq, iemOp_psignw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1626	/* 0x0a */ iemOp_psignd_Pq_Qq, iemOp_psignd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1627	/* 0x0b */ iemOp_pmulhrsw_Pq_Qq, iemOp_pmulhrsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1628	/* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
1629	/* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
1630	/* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
1631	/* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
1632
1633	/* 0x10 */ iemOp_InvalidNeedRM, iemOp_pblendvb_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1634	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1635	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1636	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1637	/* 0x14 */ iemOp_InvalidNeedRM, iemOp_blendvps_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1638	/* 0x15 */ iemOp_InvalidNeedRM, iemOp_blendvpd_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1639	/* 0x16 */ IEMOP_X4(iemOp_InvalidNeedRM),
1640	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_ptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1641	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
1642	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
1643	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
1644	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1645	/* 0x1c */ iemOp_pabsb_Pq_Qq, iemOp_pabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1646	/* 0x1d */ iemOp_pabsw_Pq_Qq, iemOp_pabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1647	/* 0x1e */ iemOp_pabsd_Pq_Qq, iemOp_pabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1648	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1649
1650	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_pmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1651	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_pmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1652	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_pmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1653	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_pmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1654	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_pmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1655	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_pmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1656	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1657	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1658	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_pmuldq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1659	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_pcmpeqq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1660	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_movntdqa_Vdq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1661	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_packusdw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1662	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRM),
1663	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRM),
1664	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRM),
1665	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRM),
1666
1667	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_pmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1668	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_pmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1669	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_pmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1670	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_pmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1671	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_pmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1672	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_pmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1673	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
1674	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_pcmpgtq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1675	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_pminsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1676	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_pminsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1677	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_pminuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1678	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_pminud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1679	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_pmaxsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1680	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_pmaxsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1681	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_pmaxuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1682	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_pmaxud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1683
1684	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_pmulld_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1685	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_phminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1686	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1687	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1688	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1689	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
1690	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
1691	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
1692	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1693	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1694	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1695	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1696	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1697	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1698	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1699	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1700
1701	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1702	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1703	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1704	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1705	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1706	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1707	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1708	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1709	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRM),
1710	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRM),
1711	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRM),
1712	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1713	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1714	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1715	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1716	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1717
1718	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1719	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1720	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1721	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1722	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1723	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1724	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1725	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1726	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1727	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1728	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1729	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1730	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1731	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1732	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1733	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1734
1735	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1736	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1737	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1738	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1739	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1740	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1741	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1742	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1743	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
1744	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
1745	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1746	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1747	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1748	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1749	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1750	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1751
1752	/* 0x80 */ iemOp_InvalidNeedRM, iemOp_invept_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1753	/* 0x81 */ iemOp_InvalidNeedRM, iemOp_invvpid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1754	/* 0x82 */ iemOp_InvalidNeedRM, iemOp_invpcid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1755	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1756	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1757	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1758	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1759	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1760	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1761	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1762	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1763	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1764	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
1765	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1766	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
1767	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1768
1769	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
1770	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
1771	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
1772	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
1773	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1774	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1775	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
1776	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
1777	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
1778	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
1779	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
1780	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
1781	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
1782	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
1783	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
1784	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
1785
1786	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1787	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1788	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1789	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1790	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1791	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1792	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1793	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1794	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1795	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1796	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
1797	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
1798	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
1799	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
1800	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRM),
1801	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
1802
1803	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1804	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1805	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1806	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1807	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1808	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1809	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1810	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1811	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1812	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1813	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
1814	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
1815	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
1816	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
1817	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
1818	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
1819
1820	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1821	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1822	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1823	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1824	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1825	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1826	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1827	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1828	/* 0xc8 */ iemOp_sha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1829	/* 0xc9 */ iemOp_sha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1830	/* 0xca */ iemOp_sha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1831	/* 0xcb */ iemOp_sha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1832	/* 0xcc */ iemOp_sha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1833	/* 0xcd */ iemOp_sha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1834	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1835	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1836
1837	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1838	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1839	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1840	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1841	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1842	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1843	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1844	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1845	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1846	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1847	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1848	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_aesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1849	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_aesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1850	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_aesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1851	/* 0xde */ iemOp_InvalidNeedRM, iemOp_aesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1852	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_aesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1853
1854	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1855	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1856	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1857	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1858	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1859	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1860	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1861	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1862	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1863	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1864	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1865	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1866	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1867	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1868	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1869	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1870
1871	/* 0xf0 */ iemOp_movbe_Gy_My, iemOp_movbe_Gw_Mw, iemOp_InvalidNeedRM, iemOp_crc32_Gd_Eb,
1872	/* 0xf1 */ iemOp_movbe_My_Gy, iemOp_movbe_Mw_Gw, iemOp_InvalidNeedRM, iemOp_crc32_Gv_Ev,
1873	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1874	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1875	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1876	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1877	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_adcx_Gy_Ey, iemOp_adox_Gy_Ey, iemOp_InvalidNeedRM,
1878	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1879	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1880	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1881	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1882	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1883	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1884	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1885	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1886	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1887	};
1888	AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f38) == 1024);
1889
1890	/** @} */
1891

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h@ 96438

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