IEMAllInstructionsThree0f38.cpp.h@ 96087

Last change on this file since 96087 was 96087, checked in by vboxsync, 3 years ago
VMM/IEM: Implement [v]pmulhrsw instructions, bugref:9898
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1	/* $Id: IEMAllInstructionsThree0f38.cpp.h 96087 2022-08-06 19:41:19Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstructionsVexMap2.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/** @name Three byte opcodes with first two bytes 0x0f 0x38
23	* @{
24	*/
25
26	FNIEMOP_DEF_2(iemOpCommonMmx_FullFull_To_Full_Ex, PFNIEMAIMPLMEDIAF2U64, pfnU64, bool, fSupported); /* in IEMAllInstructionsTwoByteOf.cpp.h */
27
28
29	/**
30	* Common worker for SSSE3 instructions on the forms:
31	* pxxx xmm1, xmm2/mem128
32	*
33	* Proper alignment of the 128-bit operand is enforced.
34	* Exceptions type 4. SSSE3 cpuid checks.
35	*
36	* @sa iemOpCommonSse2_FullFull_To_Full
37	*/
38	FNIEMOP_DEF_1(iemOpCommonSsse3_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
39	{
40	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
41	if (IEM_IS_MODRM_REG_MODE(bRm))
42	{
43	/*
44	* Register, register.
45	*/
46	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
47	IEM_MC_BEGIN(2, 0);
48	IEM_MC_ARG(PRTUINT128U, puDst, 0);
49	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
50	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
51	IEM_MC_PREPARE_SSE_USAGE();
52	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
53	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
54	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
55	IEM_MC_ADVANCE_RIP();
56	IEM_MC_END();
57	}
58	else
59	{
60	/*
61	* Register, memory.
62	*/
63	IEM_MC_BEGIN(2, 2);
64	IEM_MC_ARG(PRTUINT128U, puDst, 0);
65	IEM_MC_LOCAL(RTUINT128U, uSrc);
66	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
67	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
68
69	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
70	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
71	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
72	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
73
74	IEM_MC_PREPARE_SSE_USAGE();
75	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
76	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
77
78	IEM_MC_ADVANCE_RIP();
79	IEM_MC_END();
80	}
81	return VINF_SUCCESS;
82	}
83
84
85	/**
86	* Common worker for SSE4.1 instructions on the forms:
87	* pxxx xmm1, xmm2/mem128
88	*
89	* Proper alignment of the 128-bit operand is enforced.
90	* Exceptions type 4. SSE4.1 cpuid checks.
91	*
92	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
93	* iemOpCommonSse42_FullFull_To_Full
94	*/
95	FNIEMOP_DEF_1(iemOpCommonSse41_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
96	{
97	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
98	if (IEM_IS_MODRM_REG_MODE(bRm))
99	{
100	/*
101	* Register, register.
102	*/
103	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
104	IEM_MC_BEGIN(2, 0);
105	IEM_MC_ARG(PRTUINT128U, puDst, 0);
106	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
107	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
108	IEM_MC_PREPARE_SSE_USAGE();
109	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
110	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
111	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
112	IEM_MC_ADVANCE_RIP();
113	IEM_MC_END();
114	}
115	else
116	{
117	/*
118	* Register, memory.
119	*/
120	IEM_MC_BEGIN(2, 2);
121	IEM_MC_ARG(PRTUINT128U, puDst, 0);
122	IEM_MC_LOCAL(RTUINT128U, uSrc);
123	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
124	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
125
126	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
127	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
128	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
129	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
130
131	IEM_MC_PREPARE_SSE_USAGE();
132	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
133	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
134
135	IEM_MC_ADVANCE_RIP();
136	IEM_MC_END();
137	}
138	return VINF_SUCCESS;
139	}
140
141
142	/**
143	* Common worker for SSE4.1 instructions on the forms:
144	* pxxx xmm1, xmm2/mem128
145	*
146	* Proper alignment of the 128-bit operand is enforced.
147	* Exceptions type 4. SSE4.1 cpuid checks.
148	*
149	* Unlike iemOpCommonSse41_FullFull_To_Full, the @a pfnU128 worker function
150	* takes no FXSAVE state, just the operands.
151	*
152	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
153	* iemOpCommonSse41_FullFull_To_Full, iemOpCommonSse42_FullFull_To_Full
154	*/
155	FNIEMOP_DEF_1(iemOpCommonSse41Opt_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
156	{
157	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
158	if (IEM_IS_MODRM_REG_MODE(bRm))
159	{
160	/*
161	* Register, register.
162	*/
163	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
164	IEM_MC_BEGIN(2, 0);
165	IEM_MC_ARG(PRTUINT128U, puDst, 0);
166	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
167	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
168	IEM_MC_PREPARE_SSE_USAGE();
169	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
170	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
171	IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
172	IEM_MC_ADVANCE_RIP();
173	IEM_MC_END();
174	}
175	else
176	{
177	/*
178	* Register, memory.
179	*/
180	IEM_MC_BEGIN(2, 2);
181	IEM_MC_ARG(PRTUINT128U, puDst, 0);
182	IEM_MC_LOCAL(RTUINT128U, uSrc);
183	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
184	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
185
186	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
187	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
188	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
189	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
190
191	IEM_MC_PREPARE_SSE_USAGE();
192	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
193	IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
194
195	IEM_MC_ADVANCE_RIP();
196	IEM_MC_END();
197	}
198	return VINF_SUCCESS;
199	}
200
201
202	/**
203	* Common worker for SSE4.2 instructions on the forms:
204	* pxxx xmm1, xmm2/mem128
205	*
206	* Proper alignment of the 128-bit operand is enforced.
207	* Exceptions type 4. SSE4.2 cpuid checks.
208	*
209	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
210	* iemOpCommonSse41_FullFull_To_Full
211	*/
212	FNIEMOP_DEF_1(iemOpCommonSse42_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
213	{
214	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
215	if (IEM_IS_MODRM_REG_MODE(bRm))
216	{
217	/*
218	* Register, register.
219	*/
220	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
221	IEM_MC_BEGIN(2, 0);
222	IEM_MC_ARG(PRTUINT128U, puDst, 0);
223	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
224	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
225	IEM_MC_PREPARE_SSE_USAGE();
226	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
227	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
228	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
229	IEM_MC_ADVANCE_RIP();
230	IEM_MC_END();
231	}
232	else
233	{
234	/*
235	* Register, memory.
236	*/
237	IEM_MC_BEGIN(2, 2);
238	IEM_MC_ARG(PRTUINT128U, puDst, 0);
239	IEM_MC_LOCAL(RTUINT128U, uSrc);
240	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
241	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
242
243	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
244	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
245	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
246	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
247
248	IEM_MC_PREPARE_SSE_USAGE();
249	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
250	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
251
252	IEM_MC_ADVANCE_RIP();
253	IEM_MC_END();
254	}
255	return VINF_SUCCESS;
256	}
257
258
259	/** Opcode 0x0f 0x38 0x00. */
260	FNIEMOP_DEF(iemOp_pshufb_Pq_Qq)
261	{
262	IEMOP_MNEMONIC2(RM, PSHUFB, pshufb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
263	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
264	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pshufb_u64,&iemAImpl_pshufb_u64_fallback),
265	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
266	}
267
268
269	/** Opcode 0x66 0x0f 0x38 0x00. */
270	FNIEMOP_DEF(iemOp_pshufb_Vx_Wx)
271	{
272	IEMOP_MNEMONIC2(RM, PSHUFB, pshufb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
273	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
274	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback));
275
276	}
277
278
279	/* Opcode 0x0f 0x38 0x01. */
280	FNIEMOP_DEF(iemOp_phaddw_Pq_Qq)
281	{
282	IEMOP_MNEMONIC2(RM, PHADDW, phaddw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
283	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
284	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddw_u64,&iemAImpl_phaddw_u64_fallback),
285	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
286	}
287
288
289	/** Opcode 0x66 0x0f 0x38 0x01. */
290	FNIEMOP_DEF(iemOp_phaddw_Vx_Wx)
291	{
292	IEMOP_MNEMONIC2(RM, PHADDW, phaddw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
293	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
294	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback));
295
296	}
297
298
299	/** Opcode 0x0f 0x38 0x02. */
300	FNIEMOP_DEF(iemOp_phaddd_Pq_Qq)
301	{
302	IEMOP_MNEMONIC2(RM, PHADDD, phaddd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
303	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
304	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddd_u64,&iemAImpl_phaddd_u64_fallback),
305	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
306	}
307
308
309	/** Opcode 0x66 0x0f 0x38 0x02. */
310	FNIEMOP_DEF(iemOp_phaddd_Vx_Wx)
311	{
312	IEMOP_MNEMONIC2(RM, PHADDD, phaddd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
313	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
314	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback));
315
316	}
317
318
319	/** Opcode 0x0f 0x38 0x03. */
320	FNIEMOP_DEF(iemOp_phaddsw_Pq_Qq)
321	{
322	IEMOP_MNEMONIC2(RM, PHADDSW, phaddsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
323	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
324	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddsw_u64,&iemAImpl_phaddsw_u64_fallback),
325	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
326	}
327
328
329	/** Opcode 0x66 0x0f 0x38 0x03. */
330	FNIEMOP_DEF(iemOp_phaddsw_Vx_Wx)
331	{
332	IEMOP_MNEMONIC2(RM, PHADDSW, phaddsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
333	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
334	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback));
335
336	}
337
338
339	/** Opcode 0x0f 0x38 0x04. */
340	FNIEMOP_DEF(iemOp_pmaddubsw_Pq_Qq)
341	{
342	IEMOP_MNEMONIC2(RM, PMADDUBSW, pmaddubsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
343	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
344	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmaddubsw_u64, &iemAImpl_pmaddubsw_u64_fallback),
345	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
346	}
347
348
349	/** Opcode 0x66 0x0f 0x38 0x04. */
350	FNIEMOP_DEF(iemOp_pmaddubsw_Vx_Wx)
351	{
352	IEMOP_MNEMONIC2(RM, PMADDUBSW, pmaddubsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
353	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
354	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback));
355
356	}
357
358
359	/** Opcode 0x0f 0x38 0x05. */
360	FNIEMOP_DEF(iemOp_phsubw_Pq_Qq)
361	{
362	IEMOP_MNEMONIC2(RM, PHSUBW, phsubw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
363	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
364	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubw_u64,&iemAImpl_phsubw_u64_fallback),
365	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
366	}
367
368
369	/** Opcode 0x66 0x0f 0x38 0x05. */
370	FNIEMOP_DEF(iemOp_phsubw_Vx_Wx)
371	{
372	IEMOP_MNEMONIC2(RM, PHSUBW, phsubw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
373	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
374	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback));
375
376	}
377
378
379	/** Opcode 0x0f 0x38 0x06. */
380	FNIEMOP_DEF(iemOp_phsubd_Pq_Qq)
381	{
382	IEMOP_MNEMONIC2(RM, PHSUBD, phsubd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
383	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
384	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubd_u64,&iemAImpl_phsubd_u64_fallback),
385	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
386	}
387
388
389
390	/** Opcode 0x66 0x0f 0x38 0x06. */
391	FNIEMOP_DEF(iemOp_phsubd_Vx_Wx)
392	{
393	IEMOP_MNEMONIC2(RM, PHSUBD, phsubd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
394	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
395	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback));
396
397	}
398
399
400	/** Opcode 0x0f 0x38 0x07. */
401	FNIEMOP_DEF(iemOp_phsubsw_Pq_Qq)
402	{
403	IEMOP_MNEMONIC2(RM, PHSUBSW, phsubsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
404	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
405	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubsw_u64,&iemAImpl_phsubsw_u64_fallback),
406	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
407	}
408
409
410	/** Opcode 0x66 0x0f 0x38 0x07. */
411	FNIEMOP_DEF(iemOp_phsubsw_Vx_Wx)
412	{
413	IEMOP_MNEMONIC2(RM, PHSUBSW, phsubsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
414	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
415	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback));
416
417	}
418
419
420	/** Opcode 0x0f 0x38 0x08. */
421	FNIEMOP_DEF(iemOp_psignb_Pq_Qq)
422	{
423	IEMOP_MNEMONIC2(RM, PSIGNB, psignb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
424	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
425	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignb_u64, &iemAImpl_psignb_u64_fallback),
426	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
427	}
428
429
430	/** Opcode 0x66 0x0f 0x38 0x08. */
431	FNIEMOP_DEF(iemOp_psignb_Vx_Wx)
432	{
433	IEMOP_MNEMONIC2(RM, PSIGNB, psignb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
434	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
435	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback));
436
437	}
438
439
440	/** Opcode 0x0f 0x38 0x09. */
441	FNIEMOP_DEF(iemOp_psignw_Pq_Qq)
442	{
443	IEMOP_MNEMONIC2(RM, PSIGNW, psignw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
444	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
445	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignw_u64, &iemAImpl_psignw_u64_fallback),
446	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
447	}
448
449
450	/** Opcode 0x66 0x0f 0x38 0x09. */
451	FNIEMOP_DEF(iemOp_psignw_Vx_Wx)
452	{
453	IEMOP_MNEMONIC2(RM, PSIGNW, psignw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
454	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
455	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback));
456
457	}
458
459
460	/** Opcode 0x0f 0x38 0x0a. */
461	FNIEMOP_DEF(iemOp_psignd_Pq_Qq)
462	{
463	IEMOP_MNEMONIC2(RM, PSIGND, psignd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
464	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
465	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignd_u64, &iemAImpl_psignd_u64_fallback),
466	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
467	}
468
469
470	/** Opcode 0x66 0x0f 0x38 0x0a. */
471	FNIEMOP_DEF(iemOp_psignd_Vx_Wx)
472	{
473	IEMOP_MNEMONIC2(RM, PSIGND, psignd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
474	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
475	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback));
476
477	}
478
479
480	/** Opcode 0x0f 0x38 0x0b. */
481	FNIEMOP_DEF(iemOp_pmulhrsw_Pq_Qq)
482	{
483	IEMOP_MNEMONIC2(RM, PMULHRSW, pmulhrsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
484	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
485	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmulhrsw_u64, &iemAImpl_pmulhrsw_u64_fallback),
486	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
487	}
488
489
490	/** Opcode 0x66 0x0f 0x38 0x0b. */
491	FNIEMOP_DEF(iemOp_pmulhrsw_Vx_Wx)
492	{
493	IEMOP_MNEMONIC2(RM, PMULHRSW, pmulhrsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
494	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
495	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback));
496
497	}
498
499
500	/* Opcode 0x0f 0x38 0x0c - invalid. */
501	/* Opcode 0x66 0x0f 0x38 0x0c - invalid (vex only). */
502	/* Opcode 0x0f 0x38 0x0d - invalid. */
503	/* Opcode 0x66 0x0f 0x38 0x0d - invalid (vex only). */
504	/* Opcode 0x0f 0x38 0x0e - invalid. */
505	/* Opcode 0x66 0x0f 0x38 0x0e - invalid (vex only). */
506	/* Opcode 0x0f 0x38 0x0f - invalid. */
507	/* Opcode 0x66 0x0f 0x38 0x0f - invalid (vex only). */
508
509
510	/* Opcode 0x0f 0x38 0x10 - invalid */
511	/** Opcode 0x66 0x0f 0x38 0x10 (legacy only). */
512	FNIEMOP_STUB(iemOp_pblendvb_Vdq_Wdq);
513	/* Opcode 0x0f 0x38 0x11 - invalid */
514	/* Opcode 0x66 0x0f 0x38 0x11 - invalid */
515	/* Opcode 0x0f 0x38 0x12 - invalid */
516	/* Opcode 0x66 0x0f 0x38 0x12 - invalid */
517	/* Opcode 0x0f 0x38 0x13 - invalid */
518	/* Opcode 0x66 0x0f 0x38 0x13 - invalid (vex only). */
519	/* Opcode 0x0f 0x38 0x14 - invalid */
520	/** Opcode 0x66 0x0f 0x38 0x14 (legacy only). */
521	FNIEMOP_STUB(iemOp_blendvps_Vdq_Wdq);
522	/* Opcode 0x0f 0x38 0x15 - invalid */
523	/** Opcode 0x66 0x0f 0x38 0x15 (legacy only). */
524	FNIEMOP_STUB(iemOp_blendvpd_Vdq_Wdq);
525	/* Opcode 0x0f 0x38 0x16 - invalid */
526	/* Opcode 0x66 0x0f 0x38 0x16 - invalid (vex only). */
527	/* Opcode 0x0f 0x38 0x17 - invalid */
528
529
530	/** Opcode 0x66 0x0f 0x38 0x17 - invalid */
531	FNIEMOP_DEF(iemOp_ptest_Vx_Wx)
532	{
533	IEMOP_MNEMONIC2(RM, PTEST, ptest, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
534	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
535	if (IEM_IS_MODRM_REG_MODE(bRm))
536	{
537	/*
538	* Register, register.
539	*/
540	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
541	IEM_MC_BEGIN(3, 0);
542	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
543	IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
544	IEM_MC_ARG(uint32_t *, pEFlags, 2);
545	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
546	IEM_MC_PREPARE_SSE_USAGE();
547	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
548	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
549	IEM_MC_REF_EFLAGS(pEFlags);
550	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
551	IEM_MC_ADVANCE_RIP();
552	IEM_MC_END();
553	}
554	else
555	{
556	/*
557	* Register, memory.
558	*/
559	IEM_MC_BEGIN(3, 2);
560	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
561	IEM_MC_LOCAL(RTUINT128U, uSrc2);
562	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
563	IEM_MC_ARG(uint32_t *, pEFlags, 2);
564	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
565
566	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
567	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
568	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
569	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
570
571	IEM_MC_PREPARE_SSE_USAGE();
572	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
573	IEM_MC_REF_EFLAGS(pEFlags);
574	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
575
576	IEM_MC_ADVANCE_RIP();
577	IEM_MC_END();
578	}
579	return VINF_SUCCESS;
580	}
581
582
583	/* Opcode 0x0f 0x38 0x18 - invalid */
584	/* Opcode 0x66 0x0f 0x38 0x18 - invalid (vex only). */
585	/* Opcode 0x0f 0x38 0x19 - invalid */
586	/* Opcode 0x66 0x0f 0x38 0x19 - invalid (vex only). */
587	/* Opcode 0x0f 0x38 0x1a - invalid */
588	/* Opcode 0x66 0x0f 0x38 0x1a - invalid (vex only). */
589	/* Opcode 0x0f 0x38 0x1b - invalid */
590	/* Opcode 0x66 0x0f 0x38 0x1b - invalid */
591
592
593	/** Opcode 0x0f 0x38 0x1c. */
594	FNIEMOP_DEF(iemOp_pabsb_Pq_Qq)
595	{
596	IEMOP_MNEMONIC2(RM, PABSB, pabsb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
597	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
598	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsb_u64, &iemAImpl_pabsb_u64_fallback),
599	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
600	}
601
602
603	/** Opcode 0x66 0x0f 0x38 0x1c. */
604	FNIEMOP_DEF(iemOp_pabsb_Vx_Wx)
605	{
606	IEMOP_MNEMONIC2(RM, PABSB, pabsb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
607	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
608	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback));
609
610	}
611
612
613	/** Opcode 0x0f 0x38 0x1d. */
614	FNIEMOP_DEF(iemOp_pabsw_Pq_Qq)
615	{
616	IEMOP_MNEMONIC2(RM, PABSW, pabsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
617	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
618	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsw_u64, &iemAImpl_pabsw_u64_fallback),
619	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
620	}
621
622
623	/** Opcode 0x66 0x0f 0x38 0x1d. */
624	FNIEMOP_DEF(iemOp_pabsw_Vx_Wx)
625	{
626	IEMOP_MNEMONIC2(RM, PABSW, pabsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
627	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
628	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback));
629
630	}
631
632
633	/** Opcode 0x0f 0x38 0x1e. */
634	FNIEMOP_DEF(iemOp_pabsd_Pq_Qq)
635	{
636	IEMOP_MNEMONIC2(RM, PABSD, pabsd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
637	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
638	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsd_u64, &iemAImpl_pabsd_u64_fallback),
639	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
640	}
641
642
643	/** Opcode 0x66 0x0f 0x38 0x1e. */
644	FNIEMOP_DEF(iemOp_pabsd_Vx_Wx)
645	{
646	IEMOP_MNEMONIC2(RM, PABSD, pabsd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
647	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
648	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback));
649
650	}
651
652
653	/* Opcode 0x0f 0x38 0x1f - invalid */
654	/* Opcode 0x66 0x0f 0x38 0x1f - invalid */
655
656
657	/** Opcode 0x66 0x0f 0x38 0x20. */
658	FNIEMOP_STUB(iemOp_pmovsxbw_Vx_UxMq);
659	/** Opcode 0x66 0x0f 0x38 0x21. */
660	FNIEMOP_STUB(iemOp_pmovsxbd_Vx_UxMd);
661	/** Opcode 0x66 0x0f 0x38 0x22. */
662	FNIEMOP_STUB(iemOp_pmovsxbq_Vx_UxMw);
663	/** Opcode 0x66 0x0f 0x38 0x23. */
664	FNIEMOP_STUB(iemOp_pmovsxwd_Vx_UxMq);
665	/** Opcode 0x66 0x0f 0x38 0x24. */
666	FNIEMOP_STUB(iemOp_pmovsxwq_Vx_UxMd);
667	/** Opcode 0x66 0x0f 0x38 0x25. */
668	FNIEMOP_STUB(iemOp_pmovsxdq_Vx_UxMq);
669	/* Opcode 0x66 0x0f 0x38 0x26 - invalid */
670	/* Opcode 0x66 0x0f 0x38 0x27 - invalid */
671	/** Opcode 0x66 0x0f 0x38 0x28. */
672	FNIEMOP_STUB(iemOp_pmuldq_Vx_Wx);
673
674
675	/** Opcode 0x66 0x0f 0x38 0x29. */
676	FNIEMOP_DEF(iemOp_pcmpeqq_Vx_Wx)
677	{
678	IEMOP_MNEMONIC2(RM, PCMPEQQ, pcmpeqq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
679	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
680	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback));
681	}
682
683
684	/**
685	* @opcode 0x2a
686	* @opcodesub !11 mr/reg
687	* @oppfx 0x66
688	* @opcpuid sse4.1
689	* @opgroup og_sse41_cachect
690	* @opxcpttype 1
691	* @optest op1=-1 op2=2 -> op1=2
692	* @optest op1=0 op2=-42 -> op1=-42
693	*/
694	FNIEMOP_DEF(iemOp_movntdqa_Vdq_Mdq)
695	{
696	IEMOP_MNEMONIC2(RM_MEM, MOVNTDQA, movntdqa, Vdq_WO, Mdq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
697	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
698	if (IEM_IS_MODRM_MEM_MODE(bRm))
699	{
700	/* Register, memory. */
701	IEM_MC_BEGIN(0, 2);
702	IEM_MC_LOCAL(RTUINT128U, uSrc);
703	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
704
705	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
706	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
707	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
708	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
709
710	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
711	IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
712
713	IEM_MC_ADVANCE_RIP();
714	IEM_MC_END();
715	return VINF_SUCCESS;
716	}
717
718	/**
719	* @opdone
720	* @opmnemonic ud660f382areg
721	* @opcode 0x2a
722	* @opcodesub 11 mr/reg
723	* @oppfx 0x66
724	* @opunused immediate
725	* @opcpuid sse
726	* @optest ->
727	*/
728	return IEMOP_RAISE_INVALID_OPCODE();
729	}
730
731
732	/** Opcode 0x66 0x0f 0x38 0x2b. */
733	FNIEMOP_DEF(iemOp_packusdw_Vx_Wx)
734	{
735	IEMOP_MNEMONIC2(RM, PACKUSDW, packusdw, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
736	return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full, iemAImpl_packusdw_u128);
737	}
738
739
740	/* Opcode 0x66 0x0f 0x38 0x2c - invalid (vex only). */
741	/* Opcode 0x66 0x0f 0x38 0x2d - invalid (vex only). */
742	/* Opcode 0x66 0x0f 0x38 0x2e - invalid (vex only). */
743	/* Opcode 0x66 0x0f 0x38 0x2f - invalid (vex only). */
744
745	/** Opcode 0x66 0x0f 0x38 0x30. */
746	FNIEMOP_STUB(iemOp_pmovzxbw_Vx_UxMq);
747	/** Opcode 0x66 0x0f 0x38 0x31. */
748	FNIEMOP_STUB(iemOp_pmovzxbd_Vx_UxMd);
749	/** Opcode 0x66 0x0f 0x38 0x32. */
750	FNIEMOP_STUB(iemOp_pmovzxbq_Vx_UxMw);
751	/** Opcode 0x66 0x0f 0x38 0x33. */
752	FNIEMOP_STUB(iemOp_pmovzxwd_Vx_UxMq);
753	/** Opcode 0x66 0x0f 0x38 0x34. */
754	FNIEMOP_STUB(iemOp_pmovzxwq_Vx_UxMd);
755	/** Opcode 0x66 0x0f 0x38 0x35. */
756	FNIEMOP_STUB(iemOp_pmovzxdq_Vx_UxMq);
757	/* Opcode 0x66 0x0f 0x38 0x36 - invalid (vex only). */
758
759
760	/** Opcode 0x66 0x0f 0x38 0x37. */
761	FNIEMOP_DEF(iemOp_pcmpgtq_Vx_Wx)
762	{
763	IEMOP_MNEMONIC2(RM, PCMPGTQ, pcmpgtq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
764	return FNIEMOP_CALL_1(iemOpCommonSse42_FullFull_To_Full,
765	IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback));
766	}
767
768
769	/** Opcode 0x66 0x0f 0x38 0x38. */
770	FNIEMOP_DEF(iemOp_pminsb_Vx_Wx)
771	{
772	IEMOP_MNEMONIC2(RM, PMINSB, pminsb, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
773	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
774	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback));
775	}
776
777
778	/** Opcode 0x66 0x0f 0x38 0x39. */
779	FNIEMOP_DEF(iemOp_pminsd_Vx_Wx)
780	{
781	IEMOP_MNEMONIC2(RM, PMINSD, pminsd, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
782	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
783	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback));
784	}
785
786
787	/** Opcode 0x66 0x0f 0x38 0x3a. */
788	FNIEMOP_DEF(iemOp_pminuw_Vx_Wx)
789	{
790	IEMOP_MNEMONIC2(RM, PMINUW, pminuw, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
791	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
792	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback));
793	}
794
795
796	/** Opcode 0x66 0x0f 0x38 0x3b. */
797	FNIEMOP_DEF(iemOp_pminud_Vx_Wx)
798	{
799	IEMOP_MNEMONIC2(RM, PMINUD, pminud, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
800	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
801	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback));
802	}
803
804
805	/** Opcode 0x66 0x0f 0x38 0x3c. */
806	FNIEMOP_DEF(iemOp_pmaxsb_Vx_Wx)
807	{
808	IEMOP_MNEMONIC2(RM, PMAXSB, pmaxsb, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
809	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
810	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback));
811	}
812
813
814	/** Opcode 0x66 0x0f 0x38 0x3d. */
815	FNIEMOP_DEF(iemOp_pmaxsd_Vx_Wx)
816	{
817	IEMOP_MNEMONIC2(RM, PMAXSD, pmaxsd, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
818	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
819	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback));
820	}
821
822
823	/** Opcode 0x66 0x0f 0x38 0x3e. */
824	FNIEMOP_DEF(iemOp_pmaxuw_Vx_Wx)
825	{
826	IEMOP_MNEMONIC2(RM, PMAXUW, pmaxuw, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
827	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
828	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback));
829	}
830
831
832	/** Opcode 0x66 0x0f 0x38 0x3f. */
833	FNIEMOP_DEF(iemOp_pmaxud_Vx_Wx)
834	{
835	IEMOP_MNEMONIC2(RM, PMAXUD, pmaxud, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
836	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
837	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback));
838	}
839
840
841	/** Opcode 0x66 0x0f 0x38 0x40. */
842	FNIEMOP_DEF(iemOp_pmulld_Vx_Wx)
843	{
844	IEMOP_MNEMONIC2(RM, PMULLD, pmulld, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
845	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
846	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback));
847	}
848
849
850	/** Opcode 0x66 0x0f 0x38 0x41. */
851	FNIEMOP_STUB(iemOp_phminposuw_Vdq_Wdq);
852	/* Opcode 0x66 0x0f 0x38 0x42 - invalid. */
853	/* Opcode 0x66 0x0f 0x38 0x43 - invalid. */
854	/* Opcode 0x66 0x0f 0x38 0x44 - invalid. */
855	/* Opcode 0x66 0x0f 0x38 0x45 - invalid (vex only). */
856	/* Opcode 0x66 0x0f 0x38 0x46 - invalid (vex only). */
857	/* Opcode 0x66 0x0f 0x38 0x47 - invalid (vex only). */
858	/* Opcode 0x66 0x0f 0x38 0x48 - invalid. */
859	/* Opcode 0x66 0x0f 0x38 0x49 - invalid. */
860	/* Opcode 0x66 0x0f 0x38 0x4a - invalid. */
861	/* Opcode 0x66 0x0f 0x38 0x4b - invalid. */
862	/* Opcode 0x66 0x0f 0x38 0x4c - invalid. */
863	/* Opcode 0x66 0x0f 0x38 0x4d - invalid. */
864	/* Opcode 0x66 0x0f 0x38 0x4e - invalid. */
865	/* Opcode 0x66 0x0f 0x38 0x4f - invalid. */
866
867	/* Opcode 0x66 0x0f 0x38 0x50 - invalid. */
868	/* Opcode 0x66 0x0f 0x38 0x51 - invalid. */
869	/* Opcode 0x66 0x0f 0x38 0x52 - invalid. */
870	/* Opcode 0x66 0x0f 0x38 0x53 - invalid. */
871	/* Opcode 0x66 0x0f 0x38 0x54 - invalid. */
872	/* Opcode 0x66 0x0f 0x38 0x55 - invalid. */
873	/* Opcode 0x66 0x0f 0x38 0x56 - invalid. */
874	/* Opcode 0x66 0x0f 0x38 0x57 - invalid. */
875	/* Opcode 0x66 0x0f 0x38 0x58 - invalid (vex only). */
876	/* Opcode 0x66 0x0f 0x38 0x59 - invalid (vex only). */
877	/* Opcode 0x66 0x0f 0x38 0x5a - invalid (vex only). */
878	/* Opcode 0x66 0x0f 0x38 0x5b - invalid. */
879	/* Opcode 0x66 0x0f 0x38 0x5c - invalid. */
880	/* Opcode 0x66 0x0f 0x38 0x5d - invalid. */
881	/* Opcode 0x66 0x0f 0x38 0x5e - invalid. */
882	/* Opcode 0x66 0x0f 0x38 0x5f - invalid. */
883
884	/* Opcode 0x66 0x0f 0x38 0x60 - invalid. */
885	/* Opcode 0x66 0x0f 0x38 0x61 - invalid. */
886	/* Opcode 0x66 0x0f 0x38 0x62 - invalid. */
887	/* Opcode 0x66 0x0f 0x38 0x63 - invalid. */
888	/* Opcode 0x66 0x0f 0x38 0x64 - invalid. */
889	/* Opcode 0x66 0x0f 0x38 0x65 - invalid. */
890	/* Opcode 0x66 0x0f 0x38 0x66 - invalid. */
891	/* Opcode 0x66 0x0f 0x38 0x67 - invalid. */
892	/* Opcode 0x66 0x0f 0x38 0x68 - invalid. */
893	/* Opcode 0x66 0x0f 0x38 0x69 - invalid. */
894	/* Opcode 0x66 0x0f 0x38 0x6a - invalid. */
895	/* Opcode 0x66 0x0f 0x38 0x6b - invalid. */
896	/* Opcode 0x66 0x0f 0x38 0x6c - invalid. */
897	/* Opcode 0x66 0x0f 0x38 0x6d - invalid. */
898	/* Opcode 0x66 0x0f 0x38 0x6e - invalid. */
899	/* Opcode 0x66 0x0f 0x38 0x6f - invalid. */
900
901	/* Opcode 0x66 0x0f 0x38 0x70 - invalid. */
902	/* Opcode 0x66 0x0f 0x38 0x71 - invalid. */
903	/* Opcode 0x66 0x0f 0x38 0x72 - invalid. */
904	/* Opcode 0x66 0x0f 0x38 0x73 - invalid. */
905	/* Opcode 0x66 0x0f 0x38 0x74 - invalid. */
906	/* Opcode 0x66 0x0f 0x38 0x75 - invalid. */
907	/* Opcode 0x66 0x0f 0x38 0x76 - invalid. */
908	/* Opcode 0x66 0x0f 0x38 0x77 - invalid. */
909	/* Opcode 0x66 0x0f 0x38 0x78 - invalid (vex only). */
910	/* Opcode 0x66 0x0f 0x38 0x79 - invalid (vex only). */
911	/* Opcode 0x66 0x0f 0x38 0x7a - invalid. */
912	/* Opcode 0x66 0x0f 0x38 0x7b - invalid. */
913	/* Opcode 0x66 0x0f 0x38 0x7c - invalid. */
914	/* Opcode 0x66 0x0f 0x38 0x7d - invalid. */
915	/* Opcode 0x66 0x0f 0x38 0x7e - invalid. */
916	/* Opcode 0x66 0x0f 0x38 0x7f - invalid. */
917
918	/** Opcode 0x66 0x0f 0x38 0x80. */
919	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
920	FNIEMOP_DEF(iemOp_invept_Gy_Mdq)
921	{
922	IEMOP_MNEMONIC(invept, "invept Gy,Mdq");
923	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
924	IEMOP_HLP_IN_VMX_OPERATION("invept", kVmxVDiag_Invept);
925	IEMOP_HLP_VMX_INSTR("invept", kVmxVDiag_Invept);
926	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
927	if (IEM_IS_MODRM_MEM_MODE(bRm))
928	{
929	/* Register, memory. */
930	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
931	{
932	IEM_MC_BEGIN(3, 0);
933	IEM_MC_ARG(uint8_t, iEffSeg, 0);
934	IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
935	IEM_MC_ARG(uint64_t, uInveptType, 2);
936	IEM_MC_FETCH_GREG_U64(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
937	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
938	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
939	IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
940	IEM_MC_END();
941	}
942	else
943	{
944	IEM_MC_BEGIN(3, 0);
945	IEM_MC_ARG(uint8_t, iEffSeg, 0);
946	IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
947	IEM_MC_ARG(uint32_t, uInveptType, 2);
948	IEM_MC_FETCH_GREG_U32(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
949	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
950	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
951	IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
952	IEM_MC_END();
953	}
954	}
955	Log(("iemOp_invept_Gy_Mdq: invalid encoding -> #UD\n"));
956	return IEMOP_RAISE_INVALID_OPCODE();
957	}
958	#else
959	FNIEMOP_STUB(iemOp_invept_Gy_Mdq);
960	#endif
961
962	/** Opcode 0x66 0x0f 0x38 0x81. */
963	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
964	FNIEMOP_DEF(iemOp_invvpid_Gy_Mdq)
965	{
966	IEMOP_MNEMONIC(invvpid, "invvpid Gy,Mdq");
967	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
968	IEMOP_HLP_IN_VMX_OPERATION("invvpid", kVmxVDiag_Invvpid);
969	IEMOP_HLP_VMX_INSTR("invvpid", kVmxVDiag_Invvpid);
970	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
971	if (IEM_IS_MODRM_MEM_MODE(bRm))
972	{
973	/* Register, memory. */
974	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
975	{
976	IEM_MC_BEGIN(3, 0);
977	IEM_MC_ARG(uint8_t, iEffSeg, 0);
978	IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
979	IEM_MC_ARG(uint64_t, uInvvpidType, 2);
980	IEM_MC_FETCH_GREG_U64(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
981	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
982	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
983	IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
984	IEM_MC_END();
985	}
986	else
987	{
988	IEM_MC_BEGIN(3, 0);
989	IEM_MC_ARG(uint8_t, iEffSeg, 0);
990	IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
991	IEM_MC_ARG(uint32_t, uInvvpidType, 2);
992	IEM_MC_FETCH_GREG_U32(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
993	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
994	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
995	IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
996	IEM_MC_END();
997	}
998	}
999	Log(("iemOp_invvpid_Gy_Mdq: invalid encoding -> #UD\n"));
1000	return IEMOP_RAISE_INVALID_OPCODE();
1001	}
1002	#else
1003	FNIEMOP_STUB(iemOp_invvpid_Gy_Mdq);
1004	#endif
1005
1006	/** Opcode 0x66 0x0f 0x38 0x82. */
1007	FNIEMOP_DEF(iemOp_invpcid_Gy_Mdq)
1008	{
1009	IEMOP_MNEMONIC(invpcid, "invpcid Gy,Mdq");
1010	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1011	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1012	if (IEM_IS_MODRM_MEM_MODE(bRm))
1013	{
1014	/* Register, memory. */
1015	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
1016	{
1017	IEM_MC_BEGIN(3, 0);
1018	IEM_MC_ARG(uint8_t, iEffSeg, 0);
1019	IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
1020	IEM_MC_ARG(uint64_t, uInvpcidType, 2);
1021	IEM_MC_FETCH_GREG_U64(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1022	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
1023	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1024	IEM_MC_CALL_CIMPL_3(iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
1025	IEM_MC_END();
1026	}
1027	else
1028	{
1029	IEM_MC_BEGIN(3, 0);
1030	IEM_MC_ARG(uint8_t, iEffSeg, 0);
1031	IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
1032	IEM_MC_ARG(uint32_t, uInvpcidType, 2);
1033	IEM_MC_FETCH_GREG_U32(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1034	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
1035	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1036	IEM_MC_CALL_CIMPL_3(iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
1037	IEM_MC_END();
1038	}
1039	}
1040	Log(("iemOp_invpcid_Gy_Mdq: invalid encoding -> #UD\n"));
1041	return IEMOP_RAISE_INVALID_OPCODE();
1042	}
1043
1044
1045	/* Opcode 0x66 0x0f 0x38 0x83 - invalid. */
1046	/* Opcode 0x66 0x0f 0x38 0x84 - invalid. */
1047	/* Opcode 0x66 0x0f 0x38 0x85 - invalid. */
1048	/* Opcode 0x66 0x0f 0x38 0x86 - invalid. */
1049	/* Opcode 0x66 0x0f 0x38 0x87 - invalid. */
1050	/* Opcode 0x66 0x0f 0x38 0x88 - invalid. */
1051	/* Opcode 0x66 0x0f 0x38 0x89 - invalid. */
1052	/* Opcode 0x66 0x0f 0x38 0x8a - invalid. */
1053	/* Opcode 0x66 0x0f 0x38 0x8b - invalid. */
1054	/* Opcode 0x66 0x0f 0x38 0x8c - invalid (vex only). */
1055	/* Opcode 0x66 0x0f 0x38 0x8d - invalid. */
1056	/* Opcode 0x66 0x0f 0x38 0x8e - invalid (vex only). */
1057	/* Opcode 0x66 0x0f 0x38 0x8f - invalid. */
1058
1059	/* Opcode 0x66 0x0f 0x38 0x90 - invalid (vex only). */
1060	/* Opcode 0x66 0x0f 0x38 0x91 - invalid (vex only). */
1061	/* Opcode 0x66 0x0f 0x38 0x92 - invalid (vex only). */
1062	/* Opcode 0x66 0x0f 0x38 0x93 - invalid (vex only). */
1063	/* Opcode 0x66 0x0f 0x38 0x94 - invalid. */
1064	/* Opcode 0x66 0x0f 0x38 0x95 - invalid. */
1065	/* Opcode 0x66 0x0f 0x38 0x96 - invalid (vex only). */
1066	/* Opcode 0x66 0x0f 0x38 0x97 - invalid (vex only). */
1067	/* Opcode 0x66 0x0f 0x38 0x98 - invalid (vex only). */
1068	/* Opcode 0x66 0x0f 0x38 0x99 - invalid (vex only). */
1069	/* Opcode 0x66 0x0f 0x38 0x9a - invalid (vex only). */
1070	/* Opcode 0x66 0x0f 0x38 0x9b - invalid (vex only). */
1071	/* Opcode 0x66 0x0f 0x38 0x9c - invalid (vex only). */
1072	/* Opcode 0x66 0x0f 0x38 0x9d - invalid (vex only). */
1073	/* Opcode 0x66 0x0f 0x38 0x9e - invalid (vex only). */
1074	/* Opcode 0x66 0x0f 0x38 0x9f - invalid (vex only). */
1075
1076	/* Opcode 0x66 0x0f 0x38 0xa0 - invalid. */
1077	/* Opcode 0x66 0x0f 0x38 0xa1 - invalid. */
1078	/* Opcode 0x66 0x0f 0x38 0xa2 - invalid. */
1079	/* Opcode 0x66 0x0f 0x38 0xa3 - invalid. */
1080	/* Opcode 0x66 0x0f 0x38 0xa4 - invalid. */
1081	/* Opcode 0x66 0x0f 0x38 0xa5 - invalid. */
1082	/* Opcode 0x66 0x0f 0x38 0xa6 - invalid (vex only). */
1083	/* Opcode 0x66 0x0f 0x38 0xa7 - invalid (vex only). */
1084	/* Opcode 0x66 0x0f 0x38 0xa8 - invalid (vex only). */
1085	/* Opcode 0x66 0x0f 0x38 0xa9 - invalid (vex only). */
1086	/* Opcode 0x66 0x0f 0x38 0xaa - invalid (vex only). */
1087	/* Opcode 0x66 0x0f 0x38 0xab - invalid (vex only). */
1088	/* Opcode 0x66 0x0f 0x38 0xac - invalid (vex only). */
1089	/* Opcode 0x66 0x0f 0x38 0xad - invalid (vex only). */
1090	/* Opcode 0x66 0x0f 0x38 0xae - invalid (vex only). */
1091	/* Opcode 0x66 0x0f 0x38 0xaf - invalid (vex only). */
1092
1093	/* Opcode 0x66 0x0f 0x38 0xb0 - invalid. */
1094	/* Opcode 0x66 0x0f 0x38 0xb1 - invalid. */
1095	/* Opcode 0x66 0x0f 0x38 0xb2 - invalid. */
1096	/* Opcode 0x66 0x0f 0x38 0xb3 - invalid. */
1097	/* Opcode 0x66 0x0f 0x38 0xb4 - invalid. */
1098	/* Opcode 0x66 0x0f 0x38 0xb5 - invalid. */
1099	/* Opcode 0x66 0x0f 0x38 0xb6 - invalid (vex only). */
1100	/* Opcode 0x66 0x0f 0x38 0xb7 - invalid (vex only). */
1101	/* Opcode 0x66 0x0f 0x38 0xb8 - invalid (vex only). */
1102	/* Opcode 0x66 0x0f 0x38 0xb9 - invalid (vex only). */
1103	/* Opcode 0x66 0x0f 0x38 0xba - invalid (vex only). */
1104	/* Opcode 0x66 0x0f 0x38 0xbb - invalid (vex only). */
1105	/* Opcode 0x66 0x0f 0x38 0xbc - invalid (vex only). */
1106	/* Opcode 0x66 0x0f 0x38 0xbd - invalid (vex only). */
1107	/* Opcode 0x66 0x0f 0x38 0xbe - invalid (vex only). */
1108	/* Opcode 0x66 0x0f 0x38 0xbf - invalid (vex only). */
1109
1110	/* Opcode 0x0f 0x38 0xc0 - invalid. */
1111	/* Opcode 0x66 0x0f 0x38 0xc0 - invalid. */
1112	/* Opcode 0x0f 0x38 0xc1 - invalid. */
1113	/* Opcode 0x66 0x0f 0x38 0xc1 - invalid. */
1114	/* Opcode 0x0f 0x38 0xc2 - invalid. */
1115	/* Opcode 0x66 0x0f 0x38 0xc2 - invalid. */
1116	/* Opcode 0x0f 0x38 0xc3 - invalid. */
1117	/* Opcode 0x66 0x0f 0x38 0xc3 - invalid. */
1118	/* Opcode 0x0f 0x38 0xc4 - invalid. */
1119	/* Opcode 0x66 0x0f 0x38 0xc4 - invalid. */
1120	/* Opcode 0x0f 0x38 0xc5 - invalid. */
1121	/* Opcode 0x66 0x0f 0x38 0xc5 - invalid. */
1122	/* Opcode 0x0f 0x38 0xc6 - invalid. */
1123	/* Opcode 0x66 0x0f 0x38 0xc6 - invalid. */
1124	/* Opcode 0x0f 0x38 0xc7 - invalid. */
1125	/* Opcode 0x66 0x0f 0x38 0xc7 - invalid. */
1126	/** Opcode 0x0f 0x38 0xc8. */
1127	FNIEMOP_STUB(iemOp_sha1nexte_Vdq_Wdq);
1128	/* Opcode 0x66 0x0f 0x38 0xc8 - invalid. */
1129	/** Opcode 0x0f 0x38 0xc9. */
1130	FNIEMOP_STUB(iemOp_sha1msg1_Vdq_Wdq);
1131	/* Opcode 0x66 0x0f 0x38 0xc9 - invalid. */
1132	/** Opcode 0x0f 0x38 0xca. */
1133	FNIEMOP_STUB(iemOp_sha1msg2_Vdq_Wdq);
1134	/* Opcode 0x66 0x0f 0x38 0xca - invalid. */
1135	/** Opcode 0x0f 0x38 0xcb. */
1136	FNIEMOP_STUB(iemOp_sha256rnds2_Vdq_Wdq);
1137	/* Opcode 0x66 0x0f 0x38 0xcb - invalid. */
1138	/** Opcode 0x0f 0x38 0xcc. */
1139	FNIEMOP_STUB(iemOp_sha256msg1_Vdq_Wdq);
1140	/* Opcode 0x66 0x0f 0x38 0xcc - invalid. */
1141	/** Opcode 0x0f 0x38 0xcd. */
1142	FNIEMOP_STUB(iemOp_sha256msg2_Vdq_Wdq);
1143	/* Opcode 0x66 0x0f 0x38 0xcd - invalid. */
1144	/* Opcode 0x0f 0x38 0xce - invalid. */
1145	/* Opcode 0x66 0x0f 0x38 0xce - invalid. */
1146	/* Opcode 0x0f 0x38 0xcf - invalid. */
1147	/* Opcode 0x66 0x0f 0x38 0xcf - invalid. */
1148
1149	/* Opcode 0x66 0x0f 0x38 0xd0 - invalid. */
1150	/* Opcode 0x66 0x0f 0x38 0xd1 - invalid. */
1151	/* Opcode 0x66 0x0f 0x38 0xd2 - invalid. */
1152	/* Opcode 0x66 0x0f 0x38 0xd3 - invalid. */
1153	/* Opcode 0x66 0x0f 0x38 0xd4 - invalid. */
1154	/* Opcode 0x66 0x0f 0x38 0xd5 - invalid. */
1155	/* Opcode 0x66 0x0f 0x38 0xd6 - invalid. */
1156	/* Opcode 0x66 0x0f 0x38 0xd7 - invalid. */
1157	/* Opcode 0x66 0x0f 0x38 0xd8 - invalid. */
1158	/* Opcode 0x66 0x0f 0x38 0xd9 - invalid. */
1159	/* Opcode 0x66 0x0f 0x38 0xda - invalid. */
1160	/** Opcode 0x66 0x0f 0x38 0xdb. */
1161	FNIEMOP_STUB(iemOp_aesimc_Vdq_Wdq);
1162	/** Opcode 0x66 0x0f 0x38 0xdc. */
1163	FNIEMOP_STUB(iemOp_aesenc_Vdq_Wdq);
1164	/** Opcode 0x66 0x0f 0x38 0xdd. */
1165	FNIEMOP_STUB(iemOp_aesenclast_Vdq_Wdq);
1166	/** Opcode 0x66 0x0f 0x38 0xde. */
1167	FNIEMOP_STUB(iemOp_aesdec_Vdq_Wdq);
1168	/** Opcode 0x66 0x0f 0x38 0xdf. */
1169	FNIEMOP_STUB(iemOp_aesdeclast_Vdq_Wdq);
1170
1171	/* Opcode 0x66 0x0f 0x38 0xe0 - invalid. */
1172	/* Opcode 0x66 0x0f 0x38 0xe1 - invalid. */
1173	/* Opcode 0x66 0x0f 0x38 0xe2 - invalid. */
1174	/* Opcode 0x66 0x0f 0x38 0xe3 - invalid. */
1175	/* Opcode 0x66 0x0f 0x38 0xe4 - invalid. */
1176	/* Opcode 0x66 0x0f 0x38 0xe5 - invalid. */
1177	/* Opcode 0x66 0x0f 0x38 0xe6 - invalid. */
1178	/* Opcode 0x66 0x0f 0x38 0xe7 - invalid. */
1179	/* Opcode 0x66 0x0f 0x38 0xe8 - invalid. */
1180	/* Opcode 0x66 0x0f 0x38 0xe9 - invalid. */
1181	/* Opcode 0x66 0x0f 0x38 0xea - invalid. */
1182	/* Opcode 0x66 0x0f 0x38 0xeb - invalid. */
1183	/* Opcode 0x66 0x0f 0x38 0xec - invalid. */
1184	/* Opcode 0x66 0x0f 0x38 0xed - invalid. */
1185	/* Opcode 0x66 0x0f 0x38 0xee - invalid. */
1186	/* Opcode 0x66 0x0f 0x38 0xef - invalid. */
1187
1188
1189	/** Opcode 0x0f 0x38 0xf0. */
1190	FNIEMOP_STUB(iemOp_movbe_Gy_My);
1191	/** Opcode 0x66 0x0f 0x38 0xf0. */
1192	FNIEMOP_STUB(iemOp_movbe_Gw_Mw);
1193	/* Opcode 0xf3 0x0f 0x38 0xf0 - invalid. */
1194
1195
1196	/** Opcode 0xf2 0x0f 0x38 0xf0. */
1197	FNIEMOP_DEF(iemOp_crc32_Gd_Eb)
1198	{
1199	IEMOP_MNEMONIC2(RM, CRC32, crc32, Gd, Eb, DISOPTYPE_HARMLESS, 0);
1200	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42)
1201	return iemOp_InvalidNeedRM(pVCpu);
1202
1203	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1204	if (IEM_IS_MODRM_REG_MODE(bRm))
1205	{
1206	/*
1207	* Register, register.
1208	*/
1209	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1210	IEM_MC_BEGIN(2, 0);
1211	IEM_MC_ARG(uint32_t *, puDst, 0);
1212	IEM_MC_ARG(uint8_t, uSrc, 1);
1213	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1214	IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1215	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc);
1216	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1217	IEM_MC_ADVANCE_RIP();
1218	IEM_MC_END();
1219	}
1220	else
1221	{
1222	/*
1223	* Register, memory.
1224	*/
1225	IEM_MC_BEGIN(2, 1);
1226	IEM_MC_ARG(uint32_t *, puDst, 0);
1227	IEM_MC_ARG(uint8_t, uSrc, 1);
1228	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1229
1230	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1231	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1232	IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1233
1234	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1235	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc);
1236	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1237
1238	IEM_MC_ADVANCE_RIP();
1239	IEM_MC_END();
1240	}
1241	return VINF_SUCCESS;
1242	}
1243
1244
1245	/** Opcode 0x0f 0x38 0xf1. */
1246	FNIEMOP_STUB(iemOp_movbe_My_Gy);
1247	/** Opcode 0x66 0x0f 0x38 0xf1. */
1248	FNIEMOP_STUB(iemOp_movbe_Mw_Gw);
1249	/* Opcode 0xf3 0x0f 0x38 0xf1 - invalid. */
1250
1251
1252	/** Opcode 0xf2 0x0f 0x38 0xf1. */
1253	FNIEMOP_DEF(iemOp_crc32_Gv_Ev)
1254	{
1255	IEMOP_MNEMONIC2(RM, CRC32, crc32, Gd, Ev, DISOPTYPE_HARMLESS, 0);
1256	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42)
1257	return iemOp_InvalidNeedRM(pVCpu);
1258
1259	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1260	if (IEM_IS_MODRM_REG_MODE(bRm))
1261	{
1262	/*
1263	* Register, register.
1264	*/
1265	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1266	switch (pVCpu->iem.s.enmEffOpSize)
1267	{
1268	case IEMMODE_16BIT:
1269	IEM_MC_BEGIN(2, 0);
1270	IEM_MC_ARG(uint32_t *, puDst, 0);
1271	IEM_MC_ARG(uint16_t, uSrc, 1);
1272	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1273	IEM_MC_FETCH_GREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1274	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback),
1275	puDst, uSrc);
1276	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1277	IEM_MC_ADVANCE_RIP();
1278	IEM_MC_END();
1279	return VINF_SUCCESS;
1280
1281	case IEMMODE_32BIT:
1282	IEM_MC_BEGIN(2, 0);
1283	IEM_MC_ARG(uint32_t *, puDst, 0);
1284	IEM_MC_ARG(uint32_t, uSrc, 1);
1285	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1286	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1287	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback),
1288	puDst, uSrc);
1289	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1290	IEM_MC_ADVANCE_RIP();
1291	IEM_MC_END();
1292	return VINF_SUCCESS;
1293
1294	case IEMMODE_64BIT:
1295	IEM_MC_BEGIN(2, 0);
1296	IEM_MC_ARG(uint32_t *, puDst, 0);
1297	IEM_MC_ARG(uint64_t, uSrc, 1);
1298	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1299	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1300	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback),
1301	puDst, uSrc);
1302	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1303	IEM_MC_ADVANCE_RIP();
1304	IEM_MC_END();
1305	return VINF_SUCCESS;
1306
1307	IEM_NOT_REACHED_DEFAULT_CASE_RET();
1308	}
1309	}
1310	else
1311	{
1312	/*
1313	* Register, memory.
1314	*/
1315	switch (pVCpu->iem.s.enmEffOpSize)
1316	{
1317	case IEMMODE_16BIT:
1318	IEM_MC_BEGIN(2, 1);
1319	IEM_MC_ARG(uint32_t *, puDst, 0);
1320	IEM_MC_ARG(uint16_t, uSrc, 1);
1321	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1322
1323	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1324	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1325	IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1326
1327	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1328	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback),
1329	puDst, uSrc);
1330	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1331
1332	IEM_MC_ADVANCE_RIP();
1333	IEM_MC_END();
1334	return VINF_SUCCESS;
1335
1336	case IEMMODE_32BIT:
1337	IEM_MC_BEGIN(2, 1);
1338	IEM_MC_ARG(uint32_t *, puDst, 0);
1339	IEM_MC_ARG(uint32_t, uSrc, 1);
1340	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1341
1342	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1343	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1344	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1345
1346	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1347	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback),
1348	puDst, uSrc);
1349	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1350
1351	IEM_MC_ADVANCE_RIP();
1352	IEM_MC_END();
1353	return VINF_SUCCESS;
1354
1355	case IEMMODE_64BIT:
1356	IEM_MC_BEGIN(2, 1);
1357	IEM_MC_ARG(uint32_t *, puDst, 0);
1358	IEM_MC_ARG(uint64_t, uSrc, 1);
1359	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1360
1361	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1362	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1363	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1364
1365	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1366	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback),
1367	puDst, uSrc);
1368	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1369
1370	IEM_MC_ADVANCE_RIP();
1371	IEM_MC_END();
1372	return VINF_SUCCESS;
1373
1374	IEM_NOT_REACHED_DEFAULT_CASE_RET();
1375	}
1376	}
1377	}
1378
1379
1380	/* Opcode 0x0f 0x38 0xf2 - invalid (vex only). */
1381	/* Opcode 0x66 0x0f 0x38 0xf2 - invalid. */
1382	/* Opcode 0xf3 0x0f 0x38 0xf2 - invalid. */
1383	/* Opcode 0xf2 0x0f 0x38 0xf2 - invalid. */
1384
1385	/* Opcode 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1386	/* Opcode 0x66 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1387	/* Opcode 0xf3 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1388	/* Opcode 0xf2 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1389
1390	/* Opcode 0x0f 0x38 0xf4 - invalid. */
1391	/* Opcode 0x66 0x0f 0x38 0xf4 - invalid. */
1392	/* Opcode 0xf3 0x0f 0x38 0xf4 - invalid. */
1393	/* Opcode 0xf2 0x0f 0x38 0xf4 - invalid. */
1394
1395	/* Opcode 0x0f 0x38 0xf5 - invalid (vex only). */
1396	/* Opcode 0x66 0x0f 0x38 0xf5 - invalid. */
1397	/* Opcode 0xf3 0x0f 0x38 0xf5 - invalid (vex only). */
1398	/* Opcode 0xf2 0x0f 0x38 0xf5 - invalid (vex only). */
1399
1400	/* Opcode 0x0f 0x38 0xf6 - invalid. */
1401	/** Opcode 0x66 0x0f 0x38 0xf6. */
1402	FNIEMOP_STUB(iemOp_adcx_Gy_Ey);
1403	/** Opcode 0xf3 0x0f 0x38 0xf6. */
1404	FNIEMOP_STUB(iemOp_adox_Gy_Ey);
1405	/* Opcode 0xf2 0x0f 0x38 0xf6 - invalid (vex only). */
1406
1407	/* Opcode 0x0f 0x38 0xf7 - invalid (vex only). */
1408	/* Opcode 0x66 0x0f 0x38 0xf7 - invalid (vex only). */
1409	/* Opcode 0xf3 0x0f 0x38 0xf7 - invalid (vex only). */
1410	/* Opcode 0xf2 0x0f 0x38 0xf7 - invalid (vex only). */
1411
1412	/* Opcode 0x0f 0x38 0xf8 - invalid. */
1413	/* Opcode 0x66 0x0f 0x38 0xf8 - invalid. */
1414	/* Opcode 0xf3 0x0f 0x38 0xf8 - invalid. */
1415	/* Opcode 0xf2 0x0f 0x38 0xf8 - invalid. */
1416
1417	/* Opcode 0x0f 0x38 0xf9 - invalid. */
1418	/* Opcode 0x66 0x0f 0x38 0xf9 - invalid. */
1419	/* Opcode 0xf3 0x0f 0x38 0xf9 - invalid. */
1420	/* Opcode 0xf2 0x0f 0x38 0xf9 - invalid. */
1421
1422	/* Opcode 0x0f 0x38 0xfa - invalid. */
1423	/* Opcode 0x66 0x0f 0x38 0xfa - invalid. */
1424	/* Opcode 0xf3 0x0f 0x38 0xfa - invalid. */
1425	/* Opcode 0xf2 0x0f 0x38 0xfa - invalid. */
1426
1427	/* Opcode 0x0f 0x38 0xfb - invalid. */
1428	/* Opcode 0x66 0x0f 0x38 0xfb - invalid. */
1429	/* Opcode 0xf3 0x0f 0x38 0xfb - invalid. */
1430	/* Opcode 0xf2 0x0f 0x38 0xfb - invalid. */
1431
1432	/* Opcode 0x0f 0x38 0xfc - invalid. */
1433	/* Opcode 0x66 0x0f 0x38 0xfc - invalid. */
1434	/* Opcode 0xf3 0x0f 0x38 0xfc - invalid. */
1435	/* Opcode 0xf2 0x0f 0x38 0xfc - invalid. */
1436
1437	/* Opcode 0x0f 0x38 0xfd - invalid. */
1438	/* Opcode 0x66 0x0f 0x38 0xfd - invalid. */
1439	/* Opcode 0xf3 0x0f 0x38 0xfd - invalid. */
1440	/* Opcode 0xf2 0x0f 0x38 0xfd - invalid. */
1441
1442	/* Opcode 0x0f 0x38 0xfe - invalid. */
1443	/* Opcode 0x66 0x0f 0x38 0xfe - invalid. */
1444	/* Opcode 0xf3 0x0f 0x38 0xfe - invalid. */
1445	/* Opcode 0xf2 0x0f 0x38 0xfe - invalid. */
1446
1447	/* Opcode 0x0f 0x38 0xff - invalid. */
1448	/* Opcode 0x66 0x0f 0x38 0xff - invalid. */
1449	/* Opcode 0xf3 0x0f 0x38 0xff - invalid. */
1450	/* Opcode 0xf2 0x0f 0x38 0xff - invalid. */
1451
1452
1453	/**
1454	* Three byte opcode map, first two bytes are 0x0f 0x38.
1455	* @sa g_apfnVexMap2
1456	*/
1457	IEM_STATIC const PFNIEMOP g_apfnThreeByte0f38[] =
1458	{
1459	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1460	/* 0x00 */ iemOp_pshufb_Pq_Qq, iemOp_pshufb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1461	/* 0x01 */ iemOp_phaddw_Pq_Qq, iemOp_phaddw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1462	/* 0x02 */ iemOp_phaddd_Pq_Qq, iemOp_phaddd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1463	/* 0x03 */ iemOp_phaddsw_Pq_Qq, iemOp_phaddsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1464	/* 0x04 */ iemOp_pmaddubsw_Pq_Qq, iemOp_pmaddubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1465	/* 0x05 */ iemOp_phsubw_Pq_Qq, iemOp_phsubw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1466	/* 0x06 */ iemOp_phsubd_Pq_Qq, iemOp_phsubd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1467	/* 0x07 */ iemOp_phsubsw_Pq_Qq, iemOp_phsubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1468	/* 0x08 */ iemOp_psignb_Pq_Qq, iemOp_psignb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1469	/* 0x09 */ iemOp_psignw_Pq_Qq, iemOp_psignw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1470	/* 0x0a */ iemOp_psignd_Pq_Qq, iemOp_psignd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1471	/* 0x0b */ iemOp_pmulhrsw_Pq_Qq, iemOp_pmulhrsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1472	/* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
1473	/* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
1474	/* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
1475	/* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
1476
1477	/* 0x10 */ iemOp_InvalidNeedRM, iemOp_pblendvb_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1478	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1479	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1480	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1481	/* 0x14 */ iemOp_InvalidNeedRM, iemOp_blendvps_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1482	/* 0x15 */ iemOp_InvalidNeedRM, iemOp_blendvpd_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1483	/* 0x16 */ IEMOP_X4(iemOp_InvalidNeedRM),
1484	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_ptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1485	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
1486	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
1487	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
1488	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1489	/* 0x1c */ iemOp_pabsb_Pq_Qq, iemOp_pabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1490	/* 0x1d */ iemOp_pabsw_Pq_Qq, iemOp_pabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1491	/* 0x1e */ iemOp_pabsd_Pq_Qq, iemOp_pabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1492	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1493
1494	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_pmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1495	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_pmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1496	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_pmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1497	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_pmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1498	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_pmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1499	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_pmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1500	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1501	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1502	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_pmuldq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1503	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_pcmpeqq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1504	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_movntdqa_Vdq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1505	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_packusdw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1506	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRM),
1507	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRM),
1508	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRM),
1509	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRM),
1510
1511	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_pmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1512	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_pmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1513	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_pmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1514	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_pmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1515	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_pmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1516	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_pmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1517	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
1518	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_pcmpgtq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1519	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_pminsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1520	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_pminsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1521	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_pminuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1522	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_pminud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1523	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_pmaxsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1524	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_pmaxsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1525	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_pmaxuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1526	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_pmaxud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1527
1528	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_pmulld_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1529	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_phminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1530	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1531	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1532	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1533	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
1534	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
1535	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
1536	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1537	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1538	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1539	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1540	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1541	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1542	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1543	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1544
1545	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1546	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1547	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1548	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1549	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1550	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1551	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1552	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1553	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRM),
1554	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRM),
1555	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRM),
1556	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1557	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1558	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1559	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1560	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1561
1562	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1563	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1564	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1565	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1566	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1567	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1568	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1569	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1570	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1571	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1572	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1573	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1574	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1575	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1576	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1577	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1578
1579	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1580	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1581	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1582	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1583	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1584	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1585	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1586	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1587	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
1588	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
1589	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1590	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1591	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1592	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1593	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1594	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1595
1596	/* 0x80 */ iemOp_InvalidNeedRM, iemOp_invept_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1597	/* 0x81 */ iemOp_InvalidNeedRM, iemOp_invvpid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1598	/* 0x82 */ iemOp_InvalidNeedRM, iemOp_invpcid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1599	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1600	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1601	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1602	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1603	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1604	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1605	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1606	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1607	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1608	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
1609	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1610	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
1611	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1612
1613	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
1614	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
1615	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
1616	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
1617	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1618	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1619	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
1620	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
1621	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
1622	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
1623	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
1624	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
1625	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
1626	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
1627	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
1628	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
1629
1630	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1631	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1632	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1633	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1634	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1635	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1636	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1637	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1638	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1639	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1640	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
1641	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
1642	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
1643	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
1644	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRM),
1645	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
1646
1647	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1648	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1649	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1650	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1651	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1652	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1653	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1654	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1655	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1656	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1657	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
1658	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
1659	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
1660	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
1661	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
1662	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
1663
1664	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1665	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1666	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1667	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1668	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1669	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1670	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1671	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1672	/* 0xc8 */ iemOp_sha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1673	/* 0xc9 */ iemOp_sha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1674	/* 0xca */ iemOp_sha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1675	/* 0xcb */ iemOp_sha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1676	/* 0xcc */ iemOp_sha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1677	/* 0xcd */ iemOp_sha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1678	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1679	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1680
1681	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1682	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1683	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1684	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1685	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1686	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1687	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1688	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1689	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1690	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1691	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1692	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_aesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1693	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_aesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1694	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_aesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1695	/* 0xde */ iemOp_InvalidNeedRM, iemOp_aesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1696	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_aesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1697
1698	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1699	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1700	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1701	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1702	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1703	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1704	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1705	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1706	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1707	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1708	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1709	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1710	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1711	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1712	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1713	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1714
1715	/* 0xf0 */ iemOp_movbe_Gy_My, iemOp_movbe_Gw_Mw, iemOp_InvalidNeedRM, iemOp_crc32_Gd_Eb,
1716	/* 0xf1 */ iemOp_movbe_My_Gy, iemOp_movbe_Mw_Gw, iemOp_InvalidNeedRM, iemOp_crc32_Gv_Ev,
1717	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1718	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1719	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1720	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1721	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_adcx_Gy_Ey, iemOp_adox_Gy_Ey, iemOp_InvalidNeedRM,
1722	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1723	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1724	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1725	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1726	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1727	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1728	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1729	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1730	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1731	};
1732	AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f38) == 1024);
1733
1734	/** @} */
1735

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h@ 96087

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