VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py

Last change on this file was 104419, checked in by vboxsync, 4 weeks ago

VMM/IEM: Convert near return (retn) and relative/indirect call instructions to special IEM MC statements in order to be able to recompile them, bugref:10376
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1#!/usr/bin/env python
2# -*- coding: utf-8 -*-
3# $Id: IEMAllInstPython.py 104419 2024-04-24 14:32:29Z vboxsync $
4
5"""
6IEM instruction extractor.
7
8This script/module parses the IEMAllInstruction*.cpp.h files next to it and
9collects information about the instructions. It can then be used to generate
10disassembler tables and tests.
11"""
12
13from __future__ import print_function;
14
15__copyright__ = \
16"""
17Copyright (C) 2017-2023 Oracle and/or its affiliates.
18
19This file is part of VirtualBox base platform packages, as
20available from https://www.virtualbox.org.
21
22This program is free software; you can redistribute it and/or
23modify it under the terms of the GNU General Public License
24as published by the Free Software Foundation, in version 3 of the
25License.
26
27This program is distributed in the hope that it will be useful, but
28WITHOUT ANY WARRANTY; without even the implied warranty of
29MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
30General Public License for more details.
31
32You should have received a copy of the GNU General Public License
33along with this program; if not, see <https://www.gnu.org/licenses>.
34
35The contents of this file may alternatively be used under the terms
36of the Common Development and Distribution License Version 1.0
37(CDDL), a copy of it is provided in the "COPYING.CDDL" file included
38in the VirtualBox distribution, in which case the provisions of the
39CDDL are applicable instead of those of the GPL.
40
41You may elect to license modified versions of this file under the
42terms and conditions of either the GPL or the CDDL or both.
43
44SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
45"""
46__version__ = "$Revision: 104419 $"
47
48# pylint: disable=anomalous-backslash-in-string,too-many-lines
49
50# Standard python imports.
51import os;
52import re;
53import sys;
54import traceback;
55
56## Only the main script needs to modify the path.
57#g_ksValidationKitDir = os.path.join(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))),
58# 'ValidationKit');
59#sys.path.append(g_ksValidationKitDir);
60#
61#from common import utils; - Windows build boxes doesn't have pywin32.
62
63# Python 3 hacks:
64if sys.version_info[0] >= 3:
65 long = int; # pylint: disable=redefined-builtin,invalid-name
66
67
68g_kdX86EFlagsConstants = {
69 'X86_EFL_CF': 0x00000001, # RT_BIT_32(0)
70 'X86_EFL_1': 0x00000002, # RT_BIT_32(1)
71 'X86_EFL_PF': 0x00000004, # RT_BIT_32(2)
72 'X86_EFL_AF': 0x00000010, # RT_BIT_32(4)
73 'X86_EFL_ZF': 0x00000040, # RT_BIT_32(6)
74 'X86_EFL_SF': 0x00000080, # RT_BIT_32(7)
75 'X86_EFL_TF': 0x00000100, # RT_BIT_32(8)
76 'X86_EFL_IF': 0x00000200, # RT_BIT_32(9)
77 'X86_EFL_DF': 0x00000400, # RT_BIT_32(10)
78 'X86_EFL_OF': 0x00000800, # RT_BIT_32(11)
79 'X86_EFL_IOPL': 0x00003000, # (RT_BIT_32(12) | RT_BIT_32(13))
80 'X86_EFL_NT': 0x00004000, # RT_BIT_32(14)
81 'X86_EFL_RF': 0x00010000, # RT_BIT_32(16)
82 'X86_EFL_VM': 0x00020000, # RT_BIT_32(17)
83 'X86_EFL_AC': 0x00040000, # RT_BIT_32(18)
84 'X86_EFL_VIF': 0x00080000, # RT_BIT_32(19)
85 'X86_EFL_VIP': 0x00100000, # RT_BIT_32(20)
86 'X86_EFL_ID': 0x00200000, # RT_BIT_32(21)
87 'X86_EFL_LIVE_MASK': 0x003f7fd5, # UINT32_C(0x003f7fd5)
88 'X86_EFL_RA1_MASK': 0x00000002, # RT_BIT_32(1)
89};
90
91## EFlags values allowed in \@opfltest, \@opflmodify, \@opflundef, \@opflset, and \@opflclear.
92g_kdEFlagsMnemonics = {
93 # Debugger flag notation (sorted by value):
94 'cf': 'X86_EFL_CF', ##< Carry Flag.
95 'nc': '!X86_EFL_CF', ##< No Carry.
96
97 'po': 'X86_EFL_PF', ##< Parity Pdd.
98 'pe': '!X86_EFL_PF', ##< Parity Even.
99
100 'af': 'X86_EFL_AF', ##< Aux Flag.
101 'na': '!X86_EFL_AF', ##< No Aux.
102
103 'zr': 'X86_EFL_ZF', ##< ZeRo.
104 'nz': '!X86_EFL_ZF', ##< No Zero.
105
106 'ng': 'X86_EFL_SF', ##< NeGative (sign).
107 'pl': '!X86_EFL_SF', ##< PLuss (sign).
108
109 'tf': 'X86_EFL_TF', ##< Trap flag.
110
111 'ei': 'X86_EFL_IF', ##< Enabled Interrupts.
112 'di': '!X86_EFL_IF', ##< Disabled Interrupts.
113
114 'dn': 'X86_EFL_DF', ##< DowN (string op direction).
115 'up': '!X86_EFL_DF', ##< UP (string op direction).
116
117 'ov': 'X86_EFL_OF', ##< OVerflow.
118 'nv': '!X86_EFL_OF', ##< No Overflow.
119
120 'nt': 'X86_EFL_NT', ##< Nested Task.
121 'rf': 'X86_EFL_RF', ##< Resume Flag.
122 'vm': 'X86_EFL_VM', ##< Virtual-8086 Mode.
123 'ac': 'X86_EFL_AC', ##< Alignment Check.
124 'vif': 'X86_EFL_VIF', ##< Virtual Interrupt Flag.
125 'vip': 'X86_EFL_VIP', ##< Virtual Interrupt Pending.
126
127 # Reference manual notation not covered above (sorted by value):
128 'pf': 'X86_EFL_PF',
129 'zf': 'X86_EFL_ZF',
130 'sf': 'X86_EFL_SF',
131 'if': 'X86_EFL_IF',
132 'df': 'X86_EFL_DF',
133 'of': 'X86_EFL_OF',
134 'iopl': 'X86_EFL_IOPL',
135 'id': 'X86_EFL_ID',
136};
137
138## Constants and values for CR0.
139g_kdX86Cr0Constants = {
140 'X86_CR0_PE': 0x00000001, # RT_BIT_32(0)
141 'X86_CR0_MP': 0x00000002, # RT_BIT_32(1)
142 'X86_CR0_EM': 0x00000004, # RT_BIT_32(2)
143 'X86_CR0_TS': 0x00000008, # RT_BIT_32(3)
144 'X86_CR0_ET': 0x00000010, # RT_BIT_32(4)
145 'X86_CR0_NE': 0x00000020, # RT_BIT_32(5)
146 'X86_CR0_WP': 0x00010000, # RT_BIT_32(16)
147 'X86_CR0_AM': 0x00040000, # RT_BIT_32(18)
148 'X86_CR0_NW': 0x20000000, # RT_BIT_32(29)
149 'X86_CR0_CD': 0x40000000, # RT_BIT_32(30)
150 'X86_CR0_PG': 0x80000000, # RT_BIT_32(31)
151};
152
153## Constants and values for CR4.
154g_kdX86Cr4Constants = {
155 'X86_CR4_VME': 0x00000001, # RT_BIT_32(0)
156 'X86_CR4_PVI': 0x00000002, # RT_BIT_32(1)
157 'X86_CR4_TSD': 0x00000004, # RT_BIT_32(2)
158 'X86_CR4_DE': 0x00000008, # RT_BIT_32(3)
159 'X86_CR4_PSE': 0x00000010, # RT_BIT_32(4)
160 'X86_CR4_PAE': 0x00000020, # RT_BIT_32(5)
161 'X86_CR4_MCE': 0x00000040, # RT_BIT_32(6)
162 'X86_CR4_PGE': 0x00000080, # RT_BIT_32(7)
163 'X86_CR4_PCE': 0x00000100, # RT_BIT_32(8)
164 'X86_CR4_OSFXSR': 0x00000200, # RT_BIT_32(9)
165 'X86_CR4_OSXMMEEXCPT': 0x00000400, # RT_BIT_32(10)
166 'X86_CR4_VMXE': 0x00002000, # RT_BIT_32(13)
167 'X86_CR4_SMXE': 0x00004000, # RT_BIT_32(14)
168 'X86_CR4_PCIDE': 0x00020000, # RT_BIT_32(17)
169 'X86_CR4_OSXSAVE': 0x00040000, # RT_BIT_32(18)
170 'X86_CR4_SMEP': 0x00100000, # RT_BIT_32(20)
171 'X86_CR4_SMAP': 0x00200000, # RT_BIT_32(21)
172 'X86_CR4_PKE': 0x00400000, # RT_BIT_32(22)
173};
174
175## XSAVE components (XCR0).
176g_kdX86XSaveCConstants = {
177 'XSAVE_C_X87': 0x00000001,
178 'XSAVE_C_SSE': 0x00000002,
179 'XSAVE_C_YMM': 0x00000004,
180 'XSAVE_C_BNDREGS': 0x00000008,
181 'XSAVE_C_BNDCSR': 0x00000010,
182 'XSAVE_C_OPMASK': 0x00000020,
183 'XSAVE_C_ZMM_HI256': 0x00000040,
184 'XSAVE_C_ZMM_16HI': 0x00000080,
185 'XSAVE_C_PKRU': 0x00000200,
186 'XSAVE_C_LWP': 0x4000000000000000,
187 'XSAVE_C_X': 0x8000000000000000,
188 'XSAVE_C_ALL_AVX': 0x000000c4, # For clearing all AVX bits.
189 'XSAVE_C_ALL_AVX_SSE': 0x000000c6, # For clearing all AVX and SSE bits.
190};
191
192
193## \@op[1-4] locations
194g_kdOpLocations = {
195 'reg': [], ## modrm.reg
196 'rm': [], ## modrm.rm
197 'imm': [], ## immediate instruction data
198 'vvvv': [], ## VEX.vvvv
199 'imm8reg': [], ## byte immediate with register specified in bits 4 thru 7 (vpblendvb, vblendvps, vblendvpd).
200
201 # fixed registers.
202 'AL': [],
203 'rAX': [],
204 'rDX': [],
205 'CL': [],
206 'rSI': [],
207 'rDI': [],
208 'rFLAGS': [],
209 'CS': [],
210 'DS': [],
211 'ES': [],
212 'FS': [],
213 'GS': [],
214 'SS': [],
215 'XMM0': [],
216
217 # fixed valures.
218 '1': [],
219};
220
221## \@op[1-4] types
222##
223## Value fields:
224## - 0: the normal IDX_ParseXXX handler (IDX_UseModRM == IDX_ParseModRM).
225## - 1: the location (g_kdOpLocations).
226## - 2: disassembler format string version of the type.
227## - 3: disassembler OP_PARAM_XXX (XXX only).
228## - 4: IEM form matching instruction.
229##
230## Note! See the A.2.1 in SDM vol 2 for the type names.
231g_kdOpTypes = {
232 # Fixed addresses
233 'Ap': ( 'IDX_ParseImmAddrF', 'imm', '%Ap', 'Ap', 'FIXED', ),
234
235 # ModR/M.rm
236 'Eb': ( 'IDX_UseModRM', 'rm', '%Eb', 'Eb', 'RM', ),
237 'Ed': ( 'IDX_UseModRM', 'rm', '%Ed', 'Ed', 'RM', ),
238 'Ed_WO': ( 'IDX_UseModRM', 'rm', '%Ed', 'Ed', 'RM', ),
239 'Eq': ( 'IDX_UseModRM', 'rm', '%Eq', 'Eq', 'RM', ),
240 'Eq_WO': ( 'IDX_UseModRM', 'rm', '%Eq', 'Eq', 'RM', ),
241 'Ew': ( 'IDX_UseModRM', 'rm', '%Ew', 'Ew', 'RM', ),
242 'Ew_WO': ( 'IDX_UseModRM', 'rm', '%Ew', 'Ew', 'RM', ),
243 'Ev': ( 'IDX_UseModRM', 'rm', '%Ev', 'Ev', 'RM', ),
244 'Ey': ( 'IDX_UseModRM', 'rm', '%Ey', 'Ey', 'RM', ),
245 'Ey_WO': ( 'IDX_UseModRM', 'rm', '%Ey', 'Ey', 'RM', ),
246 'Qd': ( 'IDX_UseModRM', 'rm', '%Qd', 'Qd', 'RM', ),
247 'Qq': ( 'IDX_UseModRM', 'rm', '%Qq', 'Qq', 'RM', ),
248 'Qq_WO': ( 'IDX_UseModRM', 'rm', '%Qq', 'Qq', 'RM', ),
249 'Wss': ( 'IDX_UseModRM', 'rm', '%Wss', 'Wss', 'RM', ),
250 'Wss_WO': ( 'IDX_UseModRM', 'rm', '%Wss', 'Wss', 'RM', ),
251 'Wsd': ( 'IDX_UseModRM', 'rm', '%Wsd', 'Wsd', 'RM', ),
252 'Wsd_WO': ( 'IDX_UseModRM', 'rm', '%Wsd', 'Wsd', 'RM', ),
253 'Wps': ( 'IDX_UseModRM', 'rm', '%Wps', 'Wps', 'RM', ),
254 'Wps_WO': ( 'IDX_UseModRM', 'rm', '%Wps', 'Wps', 'RM', ),
255 'Wpd': ( 'IDX_UseModRM', 'rm', '%Wpd', 'Wpd', 'RM', ),
256 'Wpd_WO': ( 'IDX_UseModRM', 'rm', '%Wpd', 'Wpd', 'RM', ),
257 'Wdq': ( 'IDX_UseModRM', 'rm', '%Wdq', 'Wdq', 'RM', ),
258 'Wdq_WO': ( 'IDX_UseModRM', 'rm', '%Wdq', 'Wdq', 'RM', ),
259 'Wq': ( 'IDX_UseModRM', 'rm', '%Wq', 'Wq', 'RM', ),
260 'Wq_WO': ( 'IDX_UseModRM', 'rm', '%Wq', 'Wq', 'RM', ),
261 'WqZxReg_WO': ( 'IDX_UseModRM', 'rm', '%Wq', 'Wq', 'RM', ),
262 'Wqq': ( 'IDX_UseModRM', 'rm', '%Wqq', 'Wqq', 'RM', ),
263 'Wqq_WO': ( 'IDX_UseModRM', 'rm', '%Wqq', 'Wqq', 'RM', ),
264 'Wx': ( 'IDX_UseModRM', 'rm', '%Wx', 'Wx', 'RM', ),
265 'Wx_WO': ( 'IDX_UseModRM', 'rm', '%Wx', 'Wx', 'RM', ),
266
267 # ModR/M.rm - register only.
268 'Uq': ( 'IDX_UseModRM', 'rm', '%Uq', 'Uq', 'REG' ),
269 'UqHi': ( 'IDX_UseModRM', 'rm', '%Uq', 'UqHi', 'REG' ),
270 'Uqq': ( 'IDX_UseModRM', 'rm', '%Uqq', 'Uqq', 'REG' ),
271 'Uss': ( 'IDX_UseModRM', 'rm', '%Uss', 'Uss', 'REG' ),
272 'Uss_WO': ( 'IDX_UseModRM', 'rm', '%Uss', 'Uss', 'REG' ),
273 'Usd': ( 'IDX_UseModRM', 'rm', '%Usd', 'Usd', 'REG' ),
274 'Usd_WO': ( 'IDX_UseModRM', 'rm', '%Usd', 'Usd', 'REG' ),
275 'Ux': ( 'IDX_UseModRM', 'rm', '%Ux', 'Ux', 'REG' ),
276 'Nq': ( 'IDX_UseModRM', 'rm', '%Qq', 'Nq', 'REG' ),
277
278 # ModR/M.rm - memory only.
279 'Ma': ( 'IDX_UseModRM', 'rm', '%Ma', 'Ma', 'MEM', ), ##< Only used by BOUND.
280 'Mb_RO': ( 'IDX_UseModRM', 'rm', '%Mb', 'Mb', 'MEM', ),
281 'Md': ( 'IDX_UseModRM', 'rm', '%Md', 'Md', 'MEM', ),
282 'Md_RO': ( 'IDX_UseModRM', 'rm', '%Md', 'Md', 'MEM', ),
283 'Md_WO': ( 'IDX_UseModRM', 'rm', '%Md', 'Md', 'MEM', ),
284 'Mdq': ( 'IDX_UseModRM', 'rm', '%Mdq', 'Mdq', 'MEM', ),
285 'Mdq_WO': ( 'IDX_UseModRM', 'rm', '%Mdq', 'Mdq', 'MEM', ),
286 'Mq': ( 'IDX_UseModRM', 'rm', '%Mq', 'Mq', 'MEM', ),
287 'Mq_WO': ( 'IDX_UseModRM', 'rm', '%Mq', 'Mq', 'MEM', ),
288 'Mps_WO': ( 'IDX_UseModRM', 'rm', '%Mps', 'Mps', 'MEM', ),
289 'Mpd_WO': ( 'IDX_UseModRM', 'rm', '%Mpd', 'Mpd', 'MEM', ),
290 'Mx': ( 'IDX_UseModRM', 'rm', '%Mx', 'Mx', 'MEM', ),
291 'Mx_WO': ( 'IDX_UseModRM', 'rm', '%Mx', 'Mx', 'MEM', ),
292 'M_RO': ( 'IDX_UseModRM', 'rm', '%M', 'M', 'MEM', ),
293 'M_RW': ( 'IDX_UseModRM', 'rm', '%M', 'M', 'MEM', ),
294
295 # ModR/M.reg
296 'Gb': ( 'IDX_UseModRM', 'reg', '%Gb', 'Gb', '', ),
297 'Gw': ( 'IDX_UseModRM', 'reg', '%Gw', 'Gw', '', ),
298 'Gd': ( 'IDX_UseModRM', 'reg', '%Gd', 'Gd', '', ),
299 'Gv': ( 'IDX_UseModRM', 'reg', '%Gv', 'Gv', '', ),
300 'Gv_RO': ( 'IDX_UseModRM', 'reg', '%Gv', 'Gv', '', ),
301 'Gy': ( 'IDX_UseModRM', 'reg', '%Gy', 'Gy', '', ),
302 'Pd': ( 'IDX_UseModRM', 'reg', '%Pd', 'Pd', '', ),
303 'PdZx_WO': ( 'IDX_UseModRM', 'reg', '%Pd', 'PdZx', '', ),
304 'Pq': ( 'IDX_UseModRM', 'reg', '%Pq', 'Pq', '', ),
305 'Pq_WO': ( 'IDX_UseModRM', 'reg', '%Pq', 'Pq', '', ),
306 'Vd': ( 'IDX_UseModRM', 'reg', '%Vd', 'Vd', '', ),
307 'Vd_WO': ( 'IDX_UseModRM', 'reg', '%Vd', 'Vd', '', ),
308 'VdZx_WO': ( 'IDX_UseModRM', 'reg', '%Vd', 'Vd', '', ),
309 'Vdq': ( 'IDX_UseModRM', 'reg', '%Vdq', 'Vdq', '', ),
310 'Vss': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', '', ),
311 'Vss_WO': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', '', ),
312 'VssZx_WO': ( 'IDX_UseModRM', 'reg', '%Vss', 'Vss', '', ),
313 'Vsd': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', '', ),
314 'Vsd_WO': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', '', ),
315 'VsdZx_WO': ( 'IDX_UseModRM', 'reg', '%Vsd', 'Vsd', '', ),
316 'Vps': ( 'IDX_UseModRM', 'reg', '%Vps', 'Vps', '', ),
317 'Vps_WO': ( 'IDX_UseModRM', 'reg', '%Vps', 'Vps', '', ),
318 'Vpd': ( 'IDX_UseModRM', 'reg', '%Vpd', 'Vpd', '', ),
319 'Vpd_WO': ( 'IDX_UseModRM', 'reg', '%Vpd', 'Vpd', '', ),
320 'Vq': ( 'IDX_UseModRM', 'reg', '%Vq', 'Vq', '', ),
321 'Vq_WO': ( 'IDX_UseModRM', 'reg', '%Vq', 'Vq', '', ),
322 'Vdq_WO': ( 'IDX_UseModRM', 'reg', '%Vdq', 'Vdq', '', ),
323 'VqHi': ( 'IDX_UseModRM', 'reg', '%Vdq', 'VdqHi', '', ),
324 'VqHi_WO': ( 'IDX_UseModRM', 'reg', '%Vdq', 'VdqHi', '', ),
325 'VqZx_WO': ( 'IDX_UseModRM', 'reg', '%Vq', 'VqZx', '', ),
326 'Vqq': ( 'IDX_UseModRM', 'reg', '%Vqq', 'Vqq', '', ),
327 'Vqq_WO': ( 'IDX_UseModRM', 'reg', '%Vqq', 'Vqq', '', ),
328 'Vx': ( 'IDX_UseModRM', 'reg', '%Vx', 'Vx', '', ),
329 'Vx_WO': ( 'IDX_UseModRM', 'reg', '%Vx', 'Vx', '', ),
330
331 # VEX.vvvv
332 'By': ( 'IDX_UseModRM', 'vvvv', '%By', 'By', 'V', ),
333 'Hdq': ( 'IDX_UseModRM', 'vvvv', '%Hdq', 'Hdq', 'V', ),
334 'Hps': ( 'IDX_UseModRM', 'vvvv', '%Hps', 'Hps', 'V', ),
335 'Hpd': ( 'IDX_UseModRM', 'vvvv', '%Hpd', 'Hpd', 'V', ),
336 'HssHi': ( 'IDX_UseModRM', 'vvvv', '%Hx', 'HssHi', 'V', ),
337 'HsdHi': ( 'IDX_UseModRM', 'vvvv', '%Hx', 'HsdHi', 'V', ),
338 'Hq': ( 'IDX_UseModRM', 'vvvv', '%Hq', 'Hq', 'V', ),
339 'HqHi': ( 'IDX_UseModRM', 'vvvv', '%Hq', 'HqHi', 'V', ),
340 'Hqq': ( 'IDX_UseModRM', 'vvvv', '%Hqq', 'Hqq', 'V', ),
341 'Hx': ( 'IDX_UseModRM', 'vvvv', '%Hx', 'Hx', 'V', ),
342
343 # Immediate values.
344 'Ib': ( 'IDX_ParseImmByte', 'imm', '%Ib', 'Ib', '', ), ##< NB! Could be IDX_ParseImmByteSX for some instrs.
345 'Iw': ( 'IDX_ParseImmUshort', 'imm', '%Iw', 'Iw', '', ),
346 'Id': ( 'IDX_ParseImmUlong', 'imm', '%Id', 'Id', '', ),
347 'Iq': ( 'IDX_ParseImmQword', 'imm', '%Iq', 'Iq', '', ),
348 'Iv': ( 'IDX_ParseImmV', 'imm', '%Iv', 'Iv', '', ), ##< o16: word, o32: dword, o64: qword
349 'Iz': ( 'IDX_ParseImmZ', 'imm', '%Iz', 'Iz', '', ), ##< o16: word, o32|o64:dword
350
351 # Registers encoded as immediates.
352 'Lx': ( 'IDX_ParseImmByte', 'imm8reg', '%Lx', 'Lx', '', ),
353
354 # Address operands (no ModR/M).
355 'Ob': ( 'IDX_ParseImmAddr', 'imm', '%Ob', 'Ob', '', ),
356 'Ov': ( 'IDX_ParseImmAddr', 'imm', '%Ov', 'Ov', '', ),
357
358 # Relative jump targets
359 'Jb': ( 'IDX_ParseImmBRel', 'imm', '%Jb', 'Jb', '', ),
360 'Jv': ( 'IDX_ParseImmVRel', 'imm', '%Jv', 'Jv', '', ),
361
362 # DS:rSI
363 'Xb': ( 'IDX_ParseXb', 'rSI', '%eSI', 'Xb', '', ),
364 'Xv': ( 'IDX_ParseXv', 'rSI', '%eSI', 'Xv', '', ),
365 # ES:rDI
366 'Yb': ( 'IDX_ParseYb', 'rDI', '%eDI', 'Yb', '', ),
367 'Yv': ( 'IDX_ParseYv', 'rDI', '%eDI', 'Yv', '', ),
368
369 'Fv': ( 'IDX_ParseFixedReg', 'rFLAGS', '%Fv', 'Fv', '', ),
370
371 # Fixed registers.
372 'AL': ( 'IDX_ParseFixedReg', 'AL', 'al', 'REG_AL', '', ),
373 'REG_CL': ( 'IDX_ParseFixedReg', 'CL', 'cl', 'REG_CL', '', ),
374 'REG_XMM0': ( 'IDX_ParseFixedReg', 'XMM0', 'xmm0', 'REG_XMM0','', ),
375 'rAX': ( 'IDX_ParseFixedReg', 'rAX', '%eAX', 'REG_EAX', '', ),
376 'rDX': ( 'IDX_ParseFixedReg', 'rDX', '%eDX', 'REG_EDX', '', ),
377 'CS': ( 'IDX_ParseFixedReg', 'CS', 'cs', 'REG_CS', '', ), # 8086: push CS
378 'DS': ( 'IDX_ParseFixedReg', 'DS', 'ds', 'REG_DS', '', ),
379 'ES': ( 'IDX_ParseFixedReg', 'ES', 'es', 'REG_ES', '', ),
380 'FS': ( 'IDX_ParseFixedReg', 'FS', 'fs', 'REG_FS', '', ),
381 'GS': ( 'IDX_ParseFixedReg', 'GS', 'gs', 'REG_GS', '', ),
382 'SS': ( 'IDX_ParseFixedReg', 'SS', 'ss', 'REG_SS', '', ),
383
384 # Fixed values.
385 '1': ( '', '1', '1', '1', '', ),
386};
387
388# IDX_ParseFixedReg
389# IDX_ParseVexDest
390
391
392## IEMFORM_XXX mappings.
393g_kdIemForms = { # sEncoding, [ sWhere1, ... ] opcodesub ),
394 'RM': ( 'ModR/M', [ 'reg', 'rm' ], '', ),
395 'RM_REG': ( 'ModR/M', [ 'reg', 'rm' ], '11 mr/reg', ),
396 'RM_MEM': ( 'ModR/M', [ 'reg', 'rm' ], '!11 mr/reg', ),
397 'RMI': ( 'ModR/M', [ 'reg', 'rm', 'imm' ], '', ),
398 'RMI_REG': ( 'ModR/M', [ 'reg', 'rm', 'imm' ], '11 mr/reg', ),
399 'RMI_MEM': ( 'ModR/M', [ 'reg', 'rm', 'imm' ], '!11 mr/reg', ),
400 'RM0': ( 'ModR/M', [ 'reg', 'rm', 'XMM0' ], '', ),
401 'RM0_REG': ( 'ModR/M', [ 'reg', 'rm', 'XMM0' ], '11 mr/reg', ),
402 'RM0_MEM': ( 'ModR/M', [ 'reg', 'rm', 'XMM0' ], '!11 mr/reg', ),
403 'MR': ( 'ModR/M', [ 'rm', 'reg' ], '', ),
404 'MR_REG': ( 'ModR/M', [ 'rm', 'reg' ], '11 mr/reg', ),
405 'MR_MEM': ( 'ModR/M', [ 'rm', 'reg' ], '!11 mr/reg', ),
406 'MRI': ( 'ModR/M', [ 'rm', 'reg', 'imm' ], '', ),
407 'MRI_REG': ( 'ModR/M', [ 'rm', 'reg', 'imm' ], '11 mr/reg', ),
408 'MRI_MEM': ( 'ModR/M', [ 'rm', 'reg', 'imm' ], '!11 mr/reg', ),
409 'M': ( 'ModR/M', [ 'rm', ], '', ),
410 'M_REG': ( 'ModR/M', [ 'rm', ], '', ),
411 'M_MEM': ( 'ModR/M', [ 'rm', ], '', ),
412 'M1': ( 'ModR/M', [ 'rm', '1' ], '', ),
413 'M_CL': ( 'ModR/M', [ 'rm', 'CL' ], '', ), # shl/rcl/ror/++
414 'MI': ( 'ModR/M', [ 'rm', 'imm' ], '', ),
415 'MI_REG': ( 'ModR/M', [ 'rm', 'imm' ], '11 mr/reg', ),
416 'MI_MEM': ( 'ModR/M', [ 'rm', 'imm' ], '!11 mr/reg', ),
417 'R': ( 'ModR/M', [ 'reg', ], '', ),
418
419 'VEX_RM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], '', ),
420 'VEX_RM_REG': ( 'VEX.ModR/M', [ 'reg', 'rm' ], '11 mr/reg', ),
421 'VEX_RM_MEM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], '!11 mr/reg', ),
422 'VEX_MR': ( 'VEX.ModR/M', [ 'rm', 'reg' ], '', ),
423 'VEX_MR_REG': ( 'VEX.ModR/M', [ 'rm', 'reg' ], '11 mr/reg', ),
424 'VEX_MR_MEM': ( 'VEX.ModR/M', [ 'rm', 'reg' ], '!11 mr/reg', ),
425 'VEX_MRI': ( 'VEX.ModR/M', [ 'rm', 'reg', 'imm' ], '', ),
426 'VEX_MRI_REG': ( 'VEX.ModR/M', [ 'rm', 'reg', 'imm' ], '11 mr/reg', ),
427 'VEX_MRI_MEM': ( 'VEX.ModR/M', [ 'rm', 'reg', 'imm' ], '!11 mr/reg', ),
428 'VEX_M': ( 'VEX.ModR/M', [ 'rm', ], '' ),
429 'VEX_M_REG': ( 'VEX.ModR/M', [ 'rm', ], '' ),
430 'VEX_M_MEM': ( 'VEX.ModR/M', [ 'rm', ], '' ),
431 'VEX_R': ( 'VEX.ModR/M', [ 'reg', ], '' ),
432 'VEX_RVM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm' ], '', ),
433 'VEX_RVM_REG': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm' ], '11 mr/reg', ),
434 'VEX_RVM_MEM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm' ], '!11 mr/reg', ),
435 'VEX_RVMI': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm', 'imm' ], '', ),
436 'VEX_RVMI_REG': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm', 'imm' ], '11 mr/reg', ),
437 'VEX_RVMI_MEM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm', 'imm' ], '!11 mr/reg', ),
438 'VEX_RVMR': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm', 'imm8reg' ], '', ),
439 'VEX_RVMR_REG': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm', 'imm8reg' ], '11 mr/reg', ),
440 'VEX_RVMR_MEM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm', 'imm8reg' ], '!11 mr/reg', ),
441 'VEX_RMV': ( 'VEX.ModR/M', [ 'reg', 'rm', 'vvvv' ], '', ),
442 'VEX_RMV_REG': ( 'VEX.ModR/M', [ 'reg', 'rm', 'vvvv' ], '11 mr/reg', ),
443 'VEX_RMV_MEM': ( 'VEX.ModR/M', [ 'reg', 'rm', 'vvvv' ], '!11 mr/reg', ),
444 'VEX_RMI': ( 'VEX.ModR/M', [ 'reg', 'rm', 'imm' ], '', ),
445 'VEX_RMI_REG': ( 'VEX.ModR/M', [ 'reg', 'rm', 'imm' ], '11 mr/reg', ),
446 'VEX_RMI_MEM': ( 'VEX.ModR/M', [ 'reg', 'rm', 'imm' ], '!11 mr/reg', ),
447 'VEX_MVR': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg' ], '', ),
448 'VEX_MVR_REG': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg' ], '11 mr/reg', ),
449 'VEX_MVR_MEM': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg' ], '!11 mr/reg', ),
450
451 'VEX_VM': ( 'VEX.ModR/M', [ 'vvvv', 'rm' ], '', ),
452 'VEX_VM_REG': ( 'VEX.ModR/M', [ 'vvvv', 'rm' ], '11 mr/reg', ),
453 'VEX_VM_MEM': ( 'VEX.ModR/M', [ 'vvvv', 'rm' ], '!11 mr/reg', ),
454 'VEX_VMI': ( 'VEX.ModR/M', [ 'vvvv', 'rm', 'imm' ], '', ),
455 'VEX_VMI_REG': ( 'VEX.ModR/M', [ 'vvvv', 'rm', 'imm' ], '11 mr/reg', ),
456 'VEX_VMI_MEM': ( 'VEX.ModR/M', [ 'vvvv', 'rm', 'imm' ], '!11 mr/reg', ),
457
458 'FIXED': ( 'fixed', None, '', ),
459};
460
461## \@oppfx values.
462g_kdPrefixes = {
463 'none': [],
464 '0x66': [],
465 '0xf3': [],
466 '0xf2': [],
467 '!0xf3': [], # special case for bsf/tzcnt
468};
469
470## Special \@opcode tag values.
471g_kdSpecialOpcodes = {
472 '/reg': [],
473 'mr/reg': [],
474 '11 /reg': [],
475 '!11 /reg': [],
476 '11 mr/reg': [],
477 '!11 mr/reg': [],
478};
479
480## Special \@opcodesub tag values.
481## The first value is the real value for aliases.
482## The second value is for bs3cg1.
483g_kdSubOpcodes = {
484 'none': [ None, '', ],
485 '11 mr/reg': [ '11 mr/reg', '', ],
486 '11': [ '11 mr/reg', '', ], ##< alias
487 '!11 mr/reg': [ '!11 mr/reg', '', ],
488 '!11': [ '!11 mr/reg', '', ], ##< alias
489 'rex.w=0': [ 'rex.w=0', 'WZ', ],
490 'w=0': [ 'rex.w=0', '', ], ##< alias
491 'rex.w=1': [ 'rex.w=1', 'WNZ', ],
492 'w=1': [ 'rex.w=1', '', ], ##< alias
493 'vex.l=0': [ 'vex.l=0', 'L0', ],
494 'vex.l=1': [ 'vex.l=0', 'L1', ],
495 '11 mr/reg vex.l=0': [ '11 mr/reg vex.l=0', 'L0', ],
496 '11 mr/reg vex.l=1': [ '11 mr/reg vex.l=1', 'L1', ],
497 '!11 mr/reg vex.l=0': [ '!11 mr/reg vex.l=0', 'L0', ],
498 '!11 mr/reg vex.l=1': [ '!11 mr/reg vex.l=1', 'L1', ],
499 '!11 mr/reg rex.w=0': [ '!11 mr/reg rex.w=0', '', ],
500 '!11 mr/reg rex.w=1': [ '!11 mr/reg rex.w=1', '', ],
501};
502
503## Valid values for \@openc
504g_kdEncodings = {
505 'ModR/M': [ 'BS3CG1ENC_MODRM', ], ##< ModR/M
506 'VEX.ModR/M': [ 'BS3CG1ENC_VEX_MODRM', ], ##< VEX...ModR/M
507 'fixed': [ 'BS3CG1ENC_FIXED', ], ##< Fixed encoding (address, registers, unused, etc).
508 'VEX.fixed': [ 'BS3CG1ENC_VEX_FIXED', ], ##< VEX + fixed encoding (address, registers, unused, etc).
509 'prefix': [ None, ], ##< Prefix
510};
511
512## \@opunused, \@opinvalid, \@opinvlstyle
513g_kdInvalidStyles = {
514 'immediate': [], ##< CPU stops decoding immediately after the opcode.
515 'vex.modrm': [], ##< VEX+ModR/M, everyone.
516 'intel-modrm': [], ##< Intel decodes ModR/M.
517 'intel-modrm-imm8': [], ##< Intel decodes ModR/M and an 8-byte immediate.
518 'intel-opcode-modrm': [], ##< Intel decodes another opcode byte followed by ModR/M. (Unused extension tables.)
519 'intel-opcode-modrm-imm8': [], ##< Intel decodes another opcode byte followed by ModR/M and an 8-byte immediate.
520};
521
522g_kdCpuNames = {
523 '8086': (),
524 '80186': (),
525 '80286': (),
526 '80386': (),
527 '80486': (),
528};
529
530## \@opcpuid
531g_kdCpuIdFlags = {
532 'vme': 'X86_CPUID_FEATURE_EDX_VME',
533 'tsc': 'X86_CPUID_FEATURE_EDX_TSC',
534 'msr': 'X86_CPUID_FEATURE_EDX_MSR',
535 'cx8': 'X86_CPUID_FEATURE_EDX_CX8',
536 'sep': 'X86_CPUID_FEATURE_EDX_SEP',
537 'cmov': 'X86_CPUID_FEATURE_EDX_CMOV',
538 'clfsh': 'X86_CPUID_FEATURE_EDX_CLFSH',
539 'clflushopt': 'X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT',
540 'mmx': 'X86_CPUID_FEATURE_EDX_MMX',
541 'fxsr': 'X86_CPUID_FEATURE_EDX_FXSR',
542 'sse': 'X86_CPUID_FEATURE_EDX_SSE',
543 'sse2': 'X86_CPUID_FEATURE_EDX_SSE2',
544 'sse3': 'X86_CPUID_FEATURE_ECX_SSE3',
545 'pclmul': 'X86_CPUID_FEATURE_ECX_DTES64',
546 'monitor': 'X86_CPUID_FEATURE_ECX_CPLDS',
547 'vmx': 'X86_CPUID_FEATURE_ECX_VMX',
548 'smx': 'X86_CPUID_FEATURE_ECX_TM2',
549 'ssse3': 'X86_CPUID_FEATURE_ECX_SSSE3',
550 'fma': 'X86_CPUID_FEATURE_ECX_FMA',
551 'cx16': 'X86_CPUID_FEATURE_ECX_CX16',
552 'pcid': 'X86_CPUID_FEATURE_ECX_PCID',
553 'sse4.1': 'X86_CPUID_FEATURE_ECX_SSE4_1',
554 'sse4.2': 'X86_CPUID_FEATURE_ECX_SSE4_2',
555 'movbe': 'X86_CPUID_FEATURE_ECX_MOVBE',
556 'popcnt': 'X86_CPUID_FEATURE_ECX_POPCNT',
557 'aes': 'X86_CPUID_FEATURE_ECX_AES',
558 'xsave': 'X86_CPUID_FEATURE_ECX_XSAVE',
559 'avx': 'X86_CPUID_FEATURE_ECX_AVX',
560 'avx2': 'X86_CPUID_STEXT_FEATURE_EBX_AVX2',
561 'f16c': 'X86_CPUID_FEATURE_ECX_F16C',
562 'rdrand': 'X86_CPUID_FEATURE_ECX_RDRAND',
563
564 'axmmx': 'X86_CPUID_AMD_FEATURE_EDX_AXMMX',
565 '3dnowext': 'X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX',
566 '3dnow': 'X86_CPUID_AMD_FEATURE_EDX_3DNOW',
567 'svm': 'X86_CPUID_AMD_FEATURE_ECX_SVM',
568 'cr8l': 'X86_CPUID_AMD_FEATURE_ECX_CR8L',
569 'abm': 'X86_CPUID_AMD_FEATURE_ECX_ABM',
570 'sse4a': 'X86_CPUID_AMD_FEATURE_ECX_SSE4A',
571 '3dnowprf': 'X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF',
572 'xop': 'X86_CPUID_AMD_FEATURE_ECX_XOP',
573 'fma4': 'X86_CPUID_AMD_FEATURE_ECX_FMA4',
574};
575
576## \@ophints values.
577# pylint: disable=line-too-long
578g_kdHints = {
579 'invalid': 'DISOPTYPE_INVALID', ##<
580 'harmless': 'DISOPTYPE_HARMLESS', ##<
581 'controlflow': 'DISOPTYPE_CONTROLFLOW', ##<
582 'potentially_dangerous': 'DISOPTYPE_POTENTIALLY_DANGEROUS', ##<
583 'dangerous': 'DISOPTYPE_DANGEROUS', ##<
584 'portio': 'DISOPTYPE_PORTIO', ##<
585 'privileged': 'DISOPTYPE_PRIVILEGED', ##<
586 'privileged_notrap': 'DISOPTYPE_PRIVILEGED_NOTRAP', ##<
587 'uncond_controlflow': 'DISOPTYPE_UNCOND_CONTROLFLOW', ##<
588 'relative_controlflow': 'DISOPTYPE_RELATIVE_CONTROLFLOW', ##<
589 'cond_controlflow': 'DISOPTYPE_COND_CONTROLFLOW', ##<
590 'interrupt': 'DISOPTYPE_INTERRUPT', ##<
591 'illegal': 'DISOPTYPE_ILLEGAL', ##<
592 'rrm_dangerous': 'DISOPTYPE_RRM_DANGEROUS', ##< Some additional dangerous ones when recompiling raw r0.
593 'rrm_dangerous_16': 'DISOPTYPE_RRM_DANGEROUS_16', ##< Some additional dangerous ones when recompiling 16-bit raw r0.
594 'inhibit_irqs': 'DISOPTYPE_INHIBIT_IRQS', ##< Will or can inhibit irqs (sti, pop ss, mov ss) */
595 'x86_portio_read': 'DISOPTYPE_X86_PORTIO_READ', ##<
596 'x86_portio_write': 'DISOPTYPE_X86_PORTIO_WRITE', ##<
597 'x86_invalid_64': 'DISOPTYPE_X86_INVALID_64', ##< Invalid in 64 bits mode
598 'x86_only_64': 'DISOPTYPE_X86_ONLY_64', ##< Only valid in 64 bits mode
599 'x86_default_64_op_size': 'DISOPTYPE_X86_DEFAULT_64_OP_SIZE', ##< Default 64 bits operand size
600 'x86_forced_64_op_size': 'DISOPTYPE_X86_FORCED_64_OP_SIZE', ##< Forced 64 bits operand size; regardless of prefix bytes
601 'x86_rexb_extends_opreg': 'DISOPTYPE_X86_REXB_EXTENDS_OPREG', ##< REX.B extends the register field in the opcode byte
602 'x86_mod_fixed_11': 'DISOPTYPE_X86_MOD_FIXED_11', ##< modrm.mod is always 11b
603 'x86_forced_32_op_size_x86': 'DISOPTYPE_X86_FORCED_32_OP_SIZE_X86', ##< Forced 32 bits operand size; regardless of prefix bytes
604 ## (only in 16 & 32 bits mode!)
605 'x86_avx': 'DISOPTYPE_X86_AVX', ##< AVX,AVX2,++ instruction. Not implemented yet!
606 'x86_sse': 'DISOPTYPE_X86_SSE', ##< SSE,SSE2,SSE3,++ instruction. Not implemented yet!
607 'x86_mmx': 'DISOPTYPE_X86_MMX', ##< MMX,MMXExt,3DNow,++ instruction. Not implemented yet!
608 'x86_fpu': 'DISOPTYPE_X86_FPU', ##< FPU instruction. Not implemented yet!
609 'ignores_oz_pfx': '', ##< Ignores operand size prefix 66h.
610 'ignores_rexw': '', ##< Ignores REX.W.
611 'ignores_op_sizes': '', ##< Shorthand for "ignores_oz_pfx | ignores_op_sizes".
612 'vex_l_zero': '', ##< VEX.L must be 0.
613 'vex_l_one': '', ##< VEX.L must be 1.
614 'vex_l_ignored': '', ##< VEX.L is ignored.
615 'vex_v_zero': '', ##< VEX.V must be 0. (generate sub-table?)
616 'vex_w_zero': '', ##< REX.W/VEX.W must be 0.
617 'vex_w_one': '', ##< REX.W/VEX.W must be 1.
618 'rex_w_zero': '', ##< REX.W/VEX.W must be 0.
619 'rex_w_one': '', ##< REX.W/VEX.W must be 1.
620 'lock_allowed': '', ##< Lock prefix allowed.
621};
622# pylint: enable=line-too-long
623
624## \@opxcpttype values (see SDMv2 2.4, 2.7).
625g_kdXcptTypes = {
626 'none': [],
627 '1': [],
628 '2': [],
629 '3': [],
630 '4': [],
631 '4UA': [],
632 '5': [],
633 '5LZ': [], # LZ = VEX.L must be zero.
634 '6': [],
635 '7': [],
636 '7LZ': [],
637 '8': [],
638 '11': [],
639 '12': [],
640 'E1': [],
641 'E1NF': [],
642 'E2': [],
643 'E3': [],
644 'E3NF': [],
645 'E4': [],
646 'E4NF': [],
647 'E5': [],
648 'E5NF': [],
649 'E6': [],
650 'E6NF': [],
651 'E7NF': [],
652 'E9': [],
653 'E9NF': [],
654 'E10': [],
655 'E11': [],
656 'E12': [],
657 'E12NF': [],
658};
659
660
661def _isValidOpcodeByte(sOpcode):
662 """
663 Checks if sOpcode is a valid lower case opcode byte.
664 Returns true/false.
665 """
666 if len(sOpcode) == 4:
667 if sOpcode[:2] == '0x':
668 if sOpcode[2] in '0123456789abcdef':
669 if sOpcode[3] in '0123456789abcdef':
670 return True;
671 return False;
672
673
674class InstructionMap(object):
675 """
676 Instruction map.
677
678 The opcode map provides the lead opcode bytes (empty for the one byte
679 opcode map). An instruction can be member of multiple opcode maps as long
680 as it uses the same opcode value within the map (because of VEX).
681 """
682
683 kdEncodings = {
684 'legacy': [],
685 'vex1': [], ##< VEX or EVEX prefix with vvvvv = 1
686 'vex2': [], ##< VEX or EVEX prefix with vvvvv = 2
687 'vex3': [], ##< VEX or EVEX prefix with vvvvv = 3
688 'xop8': [], ##< XOP prefix with vvvvv = 8
689 'xop9': [], ##< XOP prefix with vvvvv = 9
690 'xop10': [], ##< XOP prefix with vvvvv = 10
691 };
692 ## Selectors.
693 ## 1. The first value is the number of table entries required by a
694 ## decoder or disassembler for this type of selector.
695 ## 2. The second value is how many entries per opcode byte if applicable.
696 kdSelectors = {
697 'byte': [ 256, 1, ], ##< next opcode byte selects the instruction (default).
698 'byte+pfx': [ 1024, 4, ], ##< next opcode byte selects the instruction together with the 0x66, 0xf2 and 0xf3 prefixes.
699 '/r': [ 8, 1, ], ##< modrm.reg selects the instruction.
700 'memreg /r':[ 16, 1, ], ##< modrm.reg and (modrm.mod == 3) selects the instruction.
701 'mod /r': [ 32, 1, ], ##< modrm.reg and modrm.mod selects the instruction.
702 '!11 /r': [ 8, 1, ], ##< modrm.reg selects the instruction with modrm.mod != 0y11.
703 '11 /r': [ 8, 1, ], ##< modrm.reg select the instruction with modrm.mod == 0y11.
704 '11': [ 64, 1, ], ##< modrm.reg and modrm.rm select the instruction with modrm.mod == 0y11.
705 };
706
707 ## Define the subentry number according to the Instruction::sPrefix
708 ## value for 'byte+pfx' selected tables.
709 kiPrefixOrder = {
710 'none': 0,
711 '0x66': 1,
712 '0xf3': 2,
713 '0xf2': 3,
714 };
715
716 def __init__(self, sName, sIemName = None, asLeadOpcodes = None, sSelector = 'byte+pfx',
717 sEncoding = 'legacy', sDisParse = None):
718 assert sSelector in self.kdSelectors;
719 assert sEncoding in self.kdEncodings;
720 if asLeadOpcodes is None:
721 asLeadOpcodes = [];
722 else:
723 for sOpcode in asLeadOpcodes:
724 assert _isValidOpcodeByte(sOpcode);
725 assert sDisParse is None or sDisParse.startswith('IDX_Parse');
726
727 self.sName = sName;
728 self.sIemName = sIemName;
729 self.asLeadOpcodes = asLeadOpcodes; ##< Lead opcode bytes formatted as hex strings like '0x0f'.
730 self.sSelector = sSelector; ##< The member selector, see kdSelectors.
731 self.sEncoding = sEncoding; ##< The encoding, see kdSelectors.
732 self.aoInstructions = [] # type: Instruction
733 self.sDisParse = sDisParse; ##< IDX_ParseXXX.
734
735 def copy(self, sNewName, sPrefixFilter = None):
736 """
737 Copies the table with filtering instruction by sPrefix if not None.
738 """
739 oCopy = InstructionMap(sNewName, sIemName = self.sIemName, asLeadOpcodes = self.asLeadOpcodes,
740 sSelector = 'byte' if sPrefixFilter is not None and self.sSelector == 'byte+pfx'
741 else self.sSelector,
742 sEncoding = self.sEncoding, sDisParse = self.sDisParse);
743 if sPrefixFilter is None:
744 oCopy.aoInstructions = list(self.aoInstructions);
745 else:
746 oCopy.aoInstructions = [oInstr for oInstr in self.aoInstructions if oInstr.sPrefix == sPrefixFilter];
747 return oCopy;
748
749 def getTableSize(self):
750 """
751 Number of table entries. This corresponds directly to the selector.
752 """
753 return self.kdSelectors[self.sSelector][0];
754
755 def getEntriesPerByte(self):
756 """
757 Number of table entries per opcode bytes.
758
759 This only really makes sense for the 'byte' and 'byte+pfx' selectors, for
760 the others it will just return 1.
761 """
762 return self.kdSelectors[self.sSelector][1];
763
764 def getInstructionIndex(self, oInstr):
765 """
766 Returns the table index for the instruction.
767 """
768 bOpcode = oInstr.getOpcodeByte();
769
770 # The byte selectors are simple. We need a full opcode byte and need just return it.
771 if self.sSelector == 'byte':
772 assert oInstr.sOpcode[:2] == '0x' and len(oInstr.sOpcode) == 4, str(oInstr);
773 return bOpcode;
774
775 # The byte + prefix selector is similarly simple, though requires a prefix as well as the full opcode.
776 if self.sSelector == 'byte+pfx':
777 assert oInstr.sOpcode[:2] == '0x' and len(oInstr.sOpcode) == 4, str(oInstr);
778 assert self.kiPrefixOrder.get(oInstr.sPrefix, -16384) >= 0;
779 return bOpcode * 4 + self.kiPrefixOrder.get(oInstr.sPrefix, -16384);
780
781 # The other selectors needs masking and shifting.
782 if self.sSelector == '/r':
783 return (bOpcode >> 3) & 0x7;
784
785 if self.sSelector == 'mod /r':
786 return (bOpcode >> 3) & 0x1f;
787
788 if self.sSelector == 'memreg /r':
789 return ((bOpcode >> 3) & 0x7) | (int((bOpcode >> 6) == 3) << 3);
790
791 if self.sSelector == '!11 /r':
792 assert (bOpcode & 0xc0) != 0xc, str(oInstr);
793 return (bOpcode >> 3) & 0x7;
794
795 if self.sSelector == '11 /r':
796 assert (bOpcode & 0xc0) == 0xc, str(oInstr);
797 return (bOpcode >> 3) & 0x7;
798
799 if self.sSelector == '11':
800 assert (bOpcode & 0xc0) == 0xc, str(oInstr);
801 return bOpcode & 0x3f;
802
803 assert False, self.sSelector;
804 return -1;
805
806 def getInstructionsInTableOrder(self):
807 """
808 Get instructions in table order.
809
810 Returns array of instructions. Normally there is exactly one
811 instruction per entry. However the entry could also be None if
812 not instruction was specified for that opcode value. Or there
813 could be a list of instructions to deal with special encodings
814 where for instance prefix (e.g. REX.W) encodes a different
815 instruction or different CPUs have different instructions or
816 prefixes in the same place.
817 """
818 # Start with empty table.
819 cTable = self.getTableSize();
820 aoTable = [None] * cTable;
821
822 # Insert the instructions.
823 for oInstr in self.aoInstructions:
824 if oInstr.sOpcode:
825 idxOpcode = self.getInstructionIndex(oInstr);
826 assert idxOpcode < cTable, str(idxOpcode);
827
828 oExisting = aoTable[idxOpcode];
829 if oExisting is None:
830 aoTable[idxOpcode] = oInstr;
831 elif not isinstance(oExisting, list):
832 aoTable[idxOpcode] = list([oExisting, oInstr]);
833 else:
834 oExisting.append(oInstr);
835
836 return aoTable;
837
838
839 def getDisasTableName(self):
840 """
841 Returns the disassembler table name for this map.
842 """
843 sName = 'g_aDisas';
844 for sWord in self.sName.split('_'):
845 if sWord == 'm': # suffix indicating modrm.mod==mem
846 sName += '_m';
847 elif sWord == 'r': # suffix indicating modrm.mod==reg
848 sName += '_r';
849 elif len(sWord) == 2 and re.match('^[a-f0-9][a-f0-9]$', sWord):
850 sName += '_' + sWord;
851 else:
852 sWord = sWord.replace('grp', 'Grp');
853 sWord = sWord.replace('map', 'Map');
854 sName += sWord[0].upper() + sWord[1:];
855 return sName;
856
857 def getDisasRangeName(self):
858 """
859 Returns the disassembler table range name for this map.
860 """
861 return self.getDisasTableName().replace('g_aDisas', 'g_Disas') + 'Range';
862
863 def isVexMap(self):
864 """ Returns True if a VEX map. """
865 return self.sEncoding.startswith('vex');
866
867
868class TestType(object):
869 """
870 Test value type.
871
872 This base class deals with integer like values. The fUnsigned constructor
873 parameter indicates the default stance on zero vs sign extending. It is
874 possible to override fUnsigned=True by prefixing the value with '+' or '-'.
875 """
876 def __init__(self, sName, acbSizes = None, fUnsigned = True):
877 self.sName = sName;
878 self.acbSizes = [1, 2, 4, 8, 16, 32] if acbSizes is None else acbSizes; # Normal sizes.
879 self.fUnsigned = fUnsigned;
880
881 class BadValue(Exception):
882 """ Bad value exception. """
883 def __init__(self, sMessage):
884 Exception.__init__(self, sMessage);
885 self.sMessage = sMessage;
886
887 ## For ascii ~ operator.
888 kdHexInv = {
889 '0': 'f',
890 '1': 'e',
891 '2': 'd',
892 '3': 'c',
893 '4': 'b',
894 '5': 'a',
895 '6': '9',
896 '7': '8',
897 '8': '7',
898 '9': '6',
899 'a': '5',
900 'b': '4',
901 'c': '3',
902 'd': '2',
903 'e': '1',
904 'f': '0',
905 };
906
907 def get(self, sValue):
908 """
909 Get the shortest normal sized byte representation of oValue.
910
911 Returns ((fSignExtend, bytearray), ) or ((fSignExtend, bytearray), (fSignExtend, bytearray), ).
912 The latter form is for AND+OR pairs where the first entry is what to
913 AND with the field and the second the one or OR with.
914
915 Raises BadValue if invalid value.
916 """
917 if not sValue:
918 raise TestType.BadValue('empty value');
919
920 # Deal with sign and detect hexadecimal or decimal.
921 fSignExtend = not self.fUnsigned;
922 if sValue[0] == '-' or sValue[0] == '+':
923 fSignExtend = True;
924 fHex = len(sValue) > 3 and sValue[1:3].lower() == '0x';
925 else:
926 fHex = len(sValue) > 2 and sValue[0:2].lower() == '0x';
927
928 # try convert it to long integer.
929 try:
930 iValue = long(sValue, 16 if fHex else 10);
931 except Exception as oXcpt:
932 raise TestType.BadValue('failed to convert "%s" to integer (%s)' % (sValue, oXcpt));
933
934 # Convert the hex string and pad it to a decent value. Negative values
935 # needs to be manually converted to something non-negative (~-n + 1).
936 if iValue >= 0:
937 sHex = hex(iValue);
938 if sys.version_info[0] < 3:
939 assert sHex[-1] == 'L';
940 sHex = sHex[:-1];
941 assert sHex[:2] == '0x';
942 sHex = sHex[2:];
943 else:
944 sHex = hex(-iValue - 1);
945 if sys.version_info[0] < 3:
946 assert sHex[-1] == 'L';
947 sHex = sHex[:-1];
948 assert sHex[:2] == '0x';
949 sHex = ''.join([self.kdHexInv[sDigit] for sDigit in sHex[2:]]);
950 if fSignExtend and sHex[0] not in [ '8', '9', 'a', 'b', 'c', 'd', 'e', 'f']:
951 sHex = 'f' + sHex;
952
953 cDigits = len(sHex);
954 if cDigits <= self.acbSizes[-1] * 2:
955 for cb in self.acbSizes:
956 cNaturalDigits = cb * 2;
957 if cDigits <= cNaturalDigits:
958 break;
959 else:
960 cNaturalDigits = self.acbSizes[-1] * 2;
961 cNaturalDigits = int((cDigits + cNaturalDigits - 1) / cNaturalDigits) * cNaturalDigits;
962 assert isinstance(cNaturalDigits, int)
963
964 if cNaturalDigits != cDigits:
965 cNeeded = cNaturalDigits - cDigits;
966 if iValue >= 0:
967 sHex = ('0' * cNeeded) + sHex;
968 else:
969 sHex = ('f' * cNeeded) + sHex;
970
971 # Invert and convert to bytearray and return it.
972 abValue = bytearray([int(sHex[offHex - 2 : offHex], 16) for offHex in range(len(sHex), 0, -2)]);
973
974 return ((fSignExtend, abValue),);
975
976 def validate(self, sValue):
977 """
978 Returns True if value is okay, error message on failure.
979 """
980 try:
981 self.get(sValue);
982 except TestType.BadValue as oXcpt:
983 return oXcpt.sMessage;
984 return True;
985
986 def isAndOrPair(self, sValue):
987 """
988 Checks if sValue is a pair.
989 """
990 _ = sValue;
991 return False;
992
993
994class TestTypeEflags(TestType):
995 """
996 Special value parsing for EFLAGS/RFLAGS/FLAGS.
997 """
998
999 kdZeroValueFlags = { 'nv': 0, 'pl': 0, 'nz': 0, 'na': 0, 'pe': 0, 'nc': 0, 'di': 0, 'up': 0 };
1000
1001 def __init__(self, sName):
1002 TestType.__init__(self, sName, acbSizes = [1, 2, 4, 8], fUnsigned = True);
1003
1004 def get(self, sValue):
1005 fClear = 0;
1006 fSet = 0;
1007 for sFlag in sValue.split(','):
1008 sConstant = g_kdEFlagsMnemonics.get(sFlag, None);
1009 if sConstant is None:
1010 raise self.BadValue('Unknown flag "%s" in "%s"' % (sFlag, sValue))
1011 if sConstant[0] == '!':
1012 fClear |= g_kdX86EFlagsConstants[sConstant[1:]];
1013 else:
1014 fSet |= g_kdX86EFlagsConstants[sConstant];
1015
1016 aoSet = TestType.get(self, '0x%x' % (fSet,));
1017 if fClear != 0:
1018 aoClear = TestType.get(self, '%#x' % (fClear,))
1019 assert self.isAndOrPair(sValue) is True;
1020 return (aoClear[0], aoSet[0]);
1021 assert self.isAndOrPair(sValue) is False;
1022 return aoSet;
1023
1024 def isAndOrPair(self, sValue):
1025 for sZeroFlag in self.kdZeroValueFlags:
1026 if sValue.find(sZeroFlag) >= 0:
1027 return True;
1028 return False;
1029
1030class TestTypeFromDict(TestType):
1031 """
1032 Special value parsing for CR0.
1033 """
1034
1035 kdZeroValueFlags = { 'nv': 0, 'pl': 0, 'nz': 0, 'na': 0, 'pe': 0, 'nc': 0, 'di': 0, 'up': 0 };
1036
1037 def __init__(self, sName, kdConstantsAndValues, sConstantPrefix):
1038 TestType.__init__(self, sName, acbSizes = [1, 2, 4, 8], fUnsigned = True);
1039 self.kdConstantsAndValues = kdConstantsAndValues;
1040 self.sConstantPrefix = sConstantPrefix;
1041
1042 def get(self, sValue):
1043 fValue = 0;
1044 for sFlag in sValue.split(','):
1045 fFlagValue = self.kdConstantsAndValues.get(self.sConstantPrefix + sFlag.upper(), None);
1046 if fFlagValue is None:
1047 raise self.BadValue('Unknown flag "%s" in "%s"' % (sFlag, sValue))
1048 fValue |= fFlagValue;
1049 return TestType.get(self, '0x%x' % (fValue,));
1050
1051
1052class TestInOut(object):
1053 """
1054 One input or output state modifier.
1055
1056 This should be thought as values to modify BS3REGCTX and extended (needs
1057 to be structured) state.
1058 """
1059 ## Assigned operators.
1060 kasOperators = [
1061 '&|=', # Special AND(INV)+OR operator for use with EFLAGS.
1062 '&~=',
1063 '&=',
1064 '|=',
1065 '='
1066 ];
1067 ## Types
1068 kdTypes = {
1069 'uint': TestType('uint', fUnsigned = True),
1070 'int': TestType('int'),
1071 'efl': TestTypeEflags('efl'),
1072 'cr0': TestTypeFromDict('cr0', g_kdX86Cr0Constants, 'X86_CR0_'),
1073 'cr4': TestTypeFromDict('cr4', g_kdX86Cr4Constants, 'X86_CR4_'),
1074 'xcr0': TestTypeFromDict('xcr0', g_kdX86XSaveCConstants, 'XSAVE_C_'),
1075 };
1076 ## CPU context fields.
1077 kdFields = {
1078 # name: ( default type, [both|input|output], )
1079 # Operands.
1080 'op1': ( 'uint', 'both', ), ## \@op1
1081 'op2': ( 'uint', 'both', ), ## \@op2
1082 'op3': ( 'uint', 'both', ), ## \@op3
1083 'op4': ( 'uint', 'both', ), ## \@op4
1084 # Flags.
1085 'efl': ( 'efl', 'both', ),
1086 'efl_undef': ( 'uint', 'output', ),
1087 # 8-bit GPRs.
1088 'al': ( 'uint', 'both', ),
1089 'cl': ( 'uint', 'both', ),
1090 'dl': ( 'uint', 'both', ),
1091 'bl': ( 'uint', 'both', ),
1092 'ah': ( 'uint', 'both', ),
1093 'ch': ( 'uint', 'both', ),
1094 'dh': ( 'uint', 'both', ),
1095 'bh': ( 'uint', 'both', ),
1096 'r8l': ( 'uint', 'both', ),
1097 'r9l': ( 'uint', 'both', ),
1098 'r10l': ( 'uint', 'both', ),
1099 'r11l': ( 'uint', 'both', ),
1100 'r12l': ( 'uint', 'both', ),
1101 'r13l': ( 'uint', 'both', ),
1102 'r14l': ( 'uint', 'both', ),
1103 'r15l': ( 'uint', 'both', ),
1104 # 16-bit GPRs.
1105 'ax': ( 'uint', 'both', ),
1106 'dx': ( 'uint', 'both', ),
1107 'cx': ( 'uint', 'both', ),
1108 'bx': ( 'uint', 'both', ),
1109 'sp': ( 'uint', 'both', ),
1110 'bp': ( 'uint', 'both', ),
1111 'si': ( 'uint', 'both', ),
1112 'di': ( 'uint', 'both', ),
1113 'r8w': ( 'uint', 'both', ),
1114 'r9w': ( 'uint', 'both', ),
1115 'r10w': ( 'uint', 'both', ),
1116 'r11w': ( 'uint', 'both', ),
1117 'r12w': ( 'uint', 'both', ),
1118 'r13w': ( 'uint', 'both', ),
1119 'r14w': ( 'uint', 'both', ),
1120 'r15w': ( 'uint', 'both', ),
1121 # 32-bit GPRs.
1122 'eax': ( 'uint', 'both', ),
1123 'edx': ( 'uint', 'both', ),
1124 'ecx': ( 'uint', 'both', ),
1125 'ebx': ( 'uint', 'both', ),
1126 'esp': ( 'uint', 'both', ),
1127 'ebp': ( 'uint', 'both', ),
1128 'esi': ( 'uint', 'both', ),
1129 'edi': ( 'uint', 'both', ),
1130 'r8d': ( 'uint', 'both', ),
1131 'r9d': ( 'uint', 'both', ),
1132 'r10d': ( 'uint', 'both', ),
1133 'r11d': ( 'uint', 'both', ),
1134 'r12d': ( 'uint', 'both', ),
1135 'r13d': ( 'uint', 'both', ),
1136 'r14d': ( 'uint', 'both', ),
1137 'r15d': ( 'uint', 'both', ),
1138 # 64-bit GPRs.
1139 'rax': ( 'uint', 'both', ),
1140 'rdx': ( 'uint', 'both', ),
1141 'rcx': ( 'uint', 'both', ),
1142 'rbx': ( 'uint', 'both', ),
1143 'rsp': ( 'uint', 'both', ),
1144 'rbp': ( 'uint', 'both', ),
1145 'rsi': ( 'uint', 'both', ),
1146 'rdi': ( 'uint', 'both', ),
1147 'r8': ( 'uint', 'both', ),
1148 'r9': ( 'uint', 'both', ),
1149 'r10': ( 'uint', 'both', ),
1150 'r11': ( 'uint', 'both', ),
1151 'r12': ( 'uint', 'both', ),
1152 'r13': ( 'uint', 'both', ),
1153 'r14': ( 'uint', 'both', ),
1154 'r15': ( 'uint', 'both', ),
1155 # 16-bit, 32-bit or 64-bit registers according to operand size.
1156 'oz.rax': ( 'uint', 'both', ),
1157 'oz.rdx': ( 'uint', 'both', ),
1158 'oz.rcx': ( 'uint', 'both', ),
1159 'oz.rbx': ( 'uint', 'both', ),
1160 'oz.rsp': ( 'uint', 'both', ),
1161 'oz.rbp': ( 'uint', 'both', ),
1162 'oz.rsi': ( 'uint', 'both', ),
1163 'oz.rdi': ( 'uint', 'both', ),
1164 'oz.r8': ( 'uint', 'both', ),
1165 'oz.r9': ( 'uint', 'both', ),
1166 'oz.r10': ( 'uint', 'both', ),
1167 'oz.r11': ( 'uint', 'both', ),
1168 'oz.r12': ( 'uint', 'both', ),
1169 'oz.r13': ( 'uint', 'both', ),
1170 'oz.r14': ( 'uint', 'both', ),
1171 'oz.r15': ( 'uint', 'both', ),
1172 # Control registers.
1173 'cr0': ( 'cr0', 'both', ),
1174 'cr4': ( 'cr4', 'both', ),
1175 'xcr0': ( 'xcr0', 'both', ),
1176 # FPU Registers
1177 'fcw': ( 'uint', 'both', ),
1178 'fsw': ( 'uint', 'both', ),
1179 'ftw': ( 'uint', 'both', ),
1180 'fop': ( 'uint', 'both', ),
1181 'fpuip': ( 'uint', 'both', ),
1182 'fpucs': ( 'uint', 'both', ),
1183 'fpudp': ( 'uint', 'both', ),
1184 'fpuds': ( 'uint', 'both', ),
1185 'mxcsr': ( 'uint', 'both', ),
1186 'st0': ( 'uint', 'both', ),
1187 'st1': ( 'uint', 'both', ),
1188 'st2': ( 'uint', 'both', ),
1189 'st3': ( 'uint', 'both', ),
1190 'st4': ( 'uint', 'both', ),
1191 'st5': ( 'uint', 'both', ),
1192 'st6': ( 'uint', 'both', ),
1193 'st7': ( 'uint', 'both', ),
1194 # MMX registers.
1195 'mm0': ( 'uint', 'both', ),
1196 'mm1': ( 'uint', 'both', ),
1197 'mm2': ( 'uint', 'both', ),
1198 'mm3': ( 'uint', 'both', ),
1199 'mm4': ( 'uint', 'both', ),
1200 'mm5': ( 'uint', 'both', ),
1201 'mm6': ( 'uint', 'both', ),
1202 'mm7': ( 'uint', 'both', ),
1203 # SSE registers.
1204 'xmm0': ( 'uint', 'both', ),
1205 'xmm1': ( 'uint', 'both', ),
1206 'xmm2': ( 'uint', 'both', ),
1207 'xmm3': ( 'uint', 'both', ),
1208 'xmm4': ( 'uint', 'both', ),
1209 'xmm5': ( 'uint', 'both', ),
1210 'xmm6': ( 'uint', 'both', ),
1211 'xmm7': ( 'uint', 'both', ),
1212 'xmm8': ( 'uint', 'both', ),
1213 'xmm9': ( 'uint', 'both', ),
1214 'xmm10': ( 'uint', 'both', ),
1215 'xmm11': ( 'uint', 'both', ),
1216 'xmm12': ( 'uint', 'both', ),
1217 'xmm13': ( 'uint', 'both', ),
1218 'xmm14': ( 'uint', 'both', ),
1219 'xmm15': ( 'uint', 'both', ),
1220 'xmm0.lo': ( 'uint', 'both', ),
1221 'xmm1.lo': ( 'uint', 'both', ),
1222 'xmm2.lo': ( 'uint', 'both', ),
1223 'xmm3.lo': ( 'uint', 'both', ),
1224 'xmm4.lo': ( 'uint', 'both', ),
1225 'xmm5.lo': ( 'uint', 'both', ),
1226 'xmm6.lo': ( 'uint', 'both', ),
1227 'xmm7.lo': ( 'uint', 'both', ),
1228 'xmm8.lo': ( 'uint', 'both', ),
1229 'xmm9.lo': ( 'uint', 'both', ),
1230 'xmm10.lo': ( 'uint', 'both', ),
1231 'xmm11.lo': ( 'uint', 'both', ),
1232 'xmm12.lo': ( 'uint', 'both', ),
1233 'xmm13.lo': ( 'uint', 'both', ),
1234 'xmm14.lo': ( 'uint', 'both', ),
1235 'xmm15.lo': ( 'uint', 'both', ),
1236 'xmm0.hi': ( 'uint', 'both', ),
1237 'xmm1.hi': ( 'uint', 'both', ),
1238 'xmm2.hi': ( 'uint', 'both', ),
1239 'xmm3.hi': ( 'uint', 'both', ),
1240 'xmm4.hi': ( 'uint', 'both', ),
1241 'xmm5.hi': ( 'uint', 'both', ),
1242 'xmm6.hi': ( 'uint', 'both', ),
1243 'xmm7.hi': ( 'uint', 'both', ),
1244 'xmm8.hi': ( 'uint', 'both', ),
1245 'xmm9.hi': ( 'uint', 'both', ),
1246 'xmm10.hi': ( 'uint', 'both', ),
1247 'xmm11.hi': ( 'uint', 'both', ),
1248 'xmm12.hi': ( 'uint', 'both', ),
1249 'xmm13.hi': ( 'uint', 'both', ),
1250 'xmm14.hi': ( 'uint', 'both', ),
1251 'xmm15.hi': ( 'uint', 'both', ),
1252 'xmm0.lo.zx': ( 'uint', 'both', ),
1253 'xmm1.lo.zx': ( 'uint', 'both', ),
1254 'xmm2.lo.zx': ( 'uint', 'both', ),
1255 'xmm3.lo.zx': ( 'uint', 'both', ),
1256 'xmm4.lo.zx': ( 'uint', 'both', ),
1257 'xmm5.lo.zx': ( 'uint', 'both', ),
1258 'xmm6.lo.zx': ( 'uint', 'both', ),
1259 'xmm7.lo.zx': ( 'uint', 'both', ),
1260 'xmm8.lo.zx': ( 'uint', 'both', ),
1261 'xmm9.lo.zx': ( 'uint', 'both', ),
1262 'xmm10.lo.zx': ( 'uint', 'both', ),
1263 'xmm11.lo.zx': ( 'uint', 'both', ),
1264 'xmm12.lo.zx': ( 'uint', 'both', ),
1265 'xmm13.lo.zx': ( 'uint', 'both', ),
1266 'xmm14.lo.zx': ( 'uint', 'both', ),
1267 'xmm15.lo.zx': ( 'uint', 'both', ),
1268 'xmm0.dw0': ( 'uint', 'both', ),
1269 'xmm1.dw0': ( 'uint', 'both', ),
1270 'xmm2.dw0': ( 'uint', 'both', ),
1271 'xmm3.dw0': ( 'uint', 'both', ),
1272 'xmm4.dw0': ( 'uint', 'both', ),
1273 'xmm5.dw0': ( 'uint', 'both', ),
1274 'xmm6.dw0': ( 'uint', 'both', ),
1275 'xmm7.dw0': ( 'uint', 'both', ),
1276 'xmm8.dw0': ( 'uint', 'both', ),
1277 'xmm9.dw0': ( 'uint', 'both', ),
1278 'xmm10.dw0': ( 'uint', 'both', ),
1279 'xmm11.dw0': ( 'uint', 'both', ),
1280 'xmm12.dw0': ( 'uint', 'both', ),
1281 'xmm13.dw0': ( 'uint', 'both', ),
1282 'xmm14.dw0': ( 'uint', 'both', ),
1283 'xmm15_dw0': ( 'uint', 'both', ),
1284 # AVX registers.
1285 'ymm0': ( 'uint', 'both', ),
1286 'ymm1': ( 'uint', 'both', ),
1287 'ymm2': ( 'uint', 'both', ),
1288 'ymm3': ( 'uint', 'both', ),
1289 'ymm4': ( 'uint', 'both', ),
1290 'ymm5': ( 'uint', 'both', ),
1291 'ymm6': ( 'uint', 'both', ),
1292 'ymm7': ( 'uint', 'both', ),
1293 'ymm8': ( 'uint', 'both', ),
1294 'ymm9': ( 'uint', 'both', ),
1295 'ymm10': ( 'uint', 'both', ),
1296 'ymm11': ( 'uint', 'both', ),
1297 'ymm12': ( 'uint', 'both', ),
1298 'ymm13': ( 'uint', 'both', ),
1299 'ymm14': ( 'uint', 'both', ),
1300 'ymm15': ( 'uint', 'both', ),
1301
1302 # Special ones.
1303 'value.xcpt': ( 'uint', 'output', ),
1304 };
1305
1306 def __init__(self, sField, sOp, sValue, sType):
1307 assert sField in self.kdFields;
1308 assert sOp in self.kasOperators;
1309 self.sField = sField;
1310 self.sOp = sOp;
1311 self.sValue = sValue;
1312 self.sType = sType;
1313 assert isinstance(sField, str);
1314 assert isinstance(sOp, str);
1315 assert isinstance(sType, str);
1316 assert isinstance(sValue, str);
1317
1318
1319class TestSelector(object):
1320 """
1321 One selector for an instruction test.
1322 """
1323 ## Selector compare operators.
1324 kasCompareOps = [ '==', '!=' ];
1325 ## Selector variables and their valid values.
1326 kdVariables = {
1327 # Operand size.
1328 'size': {
1329 'o16': 'size_o16',
1330 'o32': 'size_o32',
1331 'o64': 'size_o64',
1332 },
1333 # VEX.L value.
1334 'vex.l': {
1335 '0': 'vexl_0',
1336 '1': 'vexl_1',
1337 },
1338 # Execution ring.
1339 'ring': {
1340 '0': 'ring_0',
1341 '1': 'ring_1',
1342 '2': 'ring_2',
1343 '3': 'ring_3',
1344 '0..2': 'ring_0_thru_2',
1345 '1..3': 'ring_1_thru_3',
1346 },
1347 # Basic code mode.
1348 'codebits': {
1349 '64': 'code_64bit',
1350 '32': 'code_32bit',
1351 '16': 'code_16bit',
1352 },
1353 # cpu modes.
1354 'mode': {
1355 'real': 'mode_real',
1356 'prot': 'mode_prot',
1357 'long': 'mode_long',
1358 'v86': 'mode_v86',
1359 'smm': 'mode_smm',
1360 'vmx': 'mode_vmx',
1361 'svm': 'mode_svm',
1362 },
1363 # paging on/off
1364 'paging': {
1365 'on': 'paging_on',
1366 'off': 'paging_off',
1367 },
1368 # CPU vendor
1369 'vendor': {
1370 'amd': 'vendor_amd',
1371 'intel': 'vendor_intel',
1372 'via': 'vendor_via',
1373 },
1374 };
1375 ## Selector shorthand predicates.
1376 ## These translates into variable expressions.
1377 kdPredicates = {
1378 'o16': 'size==o16',
1379 'o32': 'size==o32',
1380 'o64': 'size==o64',
1381 'ring0': 'ring==0',
1382 '!ring0': 'ring==1..3',
1383 'ring1': 'ring==1',
1384 'ring2': 'ring==2',
1385 'ring3': 'ring==3',
1386 'user': 'ring==3',
1387 'supervisor': 'ring==0..2',
1388 '16-bit': 'codebits==16',
1389 '32-bit': 'codebits==32',
1390 '64-bit': 'codebits==64',
1391 'real': 'mode==real',
1392 'prot': 'mode==prot',
1393 'long': 'mode==long',
1394 'v86': 'mode==v86',
1395 'smm': 'mode==smm',
1396 'vmx': 'mode==vmx',
1397 'svm': 'mode==svm',
1398 'paging': 'paging==on',
1399 '!paging': 'paging==off',
1400 'amd': 'vendor==amd',
1401 '!amd': 'vendor!=amd',
1402 'intel': 'vendor==intel',
1403 '!intel': 'vendor!=intel',
1404 'via': 'vendor==via',
1405 '!via': 'vendor!=via',
1406 };
1407
1408 def __init__(self, sVariable, sOp, sValue):
1409 assert sVariable in self.kdVariables;
1410 assert sOp in self.kasCompareOps;
1411 assert sValue in self.kdVariables[sVariable];
1412 self.sVariable = sVariable;
1413 self.sOp = sOp;
1414 self.sValue = sValue;
1415
1416
1417class InstructionTest(object):
1418 """
1419 Instruction test.
1420 """
1421
1422 def __init__(self, oInstr): # type: (InstructionTest, Instruction)
1423 self.oInstr = oInstr # type: InstructionTest
1424 self.aoInputs = [] # type: List[TestInOut]
1425 self.aoOutputs = [] # type: List[TestInOut]
1426 self.aoSelectors = [] # type: List[TestSelector]
1427
1428 def toString(self, fRepr = False):
1429 """
1430 Converts it to string representation.
1431 """
1432 asWords = [];
1433 if self.aoSelectors:
1434 for oSelector in self.aoSelectors:
1435 asWords.append('%s%s%s' % (oSelector.sVariable, oSelector.sOp, oSelector.sValue,));
1436 asWords.append('/');
1437
1438 for oModifier in self.aoInputs:
1439 asWords.append('%s%s%s:%s' % (oModifier.sField, oModifier.sOp, oModifier.sValue, oModifier.sType,));
1440
1441 asWords.append('->');
1442
1443 for oModifier in self.aoOutputs:
1444 asWords.append('%s%s%s:%s' % (oModifier.sField, oModifier.sOp, oModifier.sValue, oModifier.sType,));
1445
1446 if fRepr:
1447 return '<' + ' '.join(asWords) + '>';
1448 return ' '.join(asWords);
1449
1450 def __str__(self):
1451 """ Provide string represenation. """
1452 return self.toString(False);
1453
1454 def __repr__(self):
1455 """ Provide unambigious string representation. """
1456 return self.toString(True);
1457
1458class Operand(object):
1459 """
1460 Instruction operand.
1461 """
1462
1463 def __init__(self, sWhere, sType):
1464 assert sWhere in g_kdOpLocations, sWhere;
1465 assert sType in g_kdOpTypes, sType;
1466 self.sWhere = sWhere; ##< g_kdOpLocations
1467 self.sType = sType; ##< g_kdOpTypes
1468
1469 def usesModRM(self):
1470 """ Returns True if using some form of ModR/M encoding. """
1471 return self.sType[0] in ['E', 'G', 'M'];
1472
1473
1474
1475class Instruction(object): # pylint: disable=too-many-instance-attributes
1476 """
1477 Instruction.
1478 """
1479
1480 def __init__(self, sSrcFile, iLine):
1481 ## @name Core attributes.
1482 ## @{
1483 self.oParent = None # type: Instruction
1484 self.sMnemonic = None;
1485 self.sBrief = None;
1486 self.asDescSections = [] # type: List[str]
1487 self.aoMaps = [] # type: List[InstructionMap]
1488 self.aoOperands = [] # type: List[Operand]
1489 self.sPrefix = None; ##< Single prefix: None, 'none', 0x66, 0xf3, 0xf2
1490 self.sOpcode = None # type: str
1491 self.sSubOpcode = None # type: str
1492 self.sEncoding = None;
1493 self.asFlTest = None;
1494 self.asFlModify = None;
1495 self.asFlUndefined = None;
1496 self.asFlSet = None;
1497 self.asFlClear = None;
1498 self.dHints = {}; ##< Dictionary of instruction hints, flags, whatnot. (Dictionary for speed; dummy value).
1499 self.sDisEnum = None; ##< OP_XXXX value. Default is based on the uppercased mnemonic.
1500 self.asCpuIds = []; ##< The CPUID feature bit names for this instruction. If multiple, assume AND.
1501 self.asReqFeatures = []; ##< Which features are required to be enabled to run this instruction.
1502 self.aoTests = [] # type: List[InstructionTest]
1503 self.sMinCpu = None; ##< Indicates the minimum CPU required for the instruction. Not set when oCpuExpr is.
1504 self.oCpuExpr = None; ##< Some CPU restriction expression...
1505 self.sGroup = None;
1506 self.fUnused = False; ##< Unused instruction.
1507 self.fInvalid = False; ##< Invalid instruction (like UD2).
1508 self.sInvalidStyle = None; ##< Invalid behviour style (g_kdInvalidStyles),
1509 self.sXcptType = None; ##< Exception type (g_kdXcptTypes).
1510 ## @}
1511
1512 ## @name Implementation attributes.
1513 ## @{
1514 self.sStats = None;
1515 self.sFunction = None;
1516 self.fStub = False;
1517 self.fUdStub = False;
1518 ## @}
1519
1520 ## @name Decoding info
1521 ## @{
1522 self.sSrcFile = sSrcFile;
1523 self.iLineCreated = iLine;
1524 self.iLineCompleted = None;
1525 self.cOpTags = 0;
1526 self.iLineFnIemOpMacro = -1;
1527 self.iLineMnemonicMacro = -1;
1528 ## @}
1529
1530 ## @name Intermediate input fields.
1531 ## @{
1532 self.sRawDisOpNo = None;
1533 self.asRawDisParams = [];
1534 self.sRawIemOpFlags = None;
1535 self.sRawOldOpcodes = None;
1536 self.asCopyTests = [];
1537 ## @}
1538
1539 ## All the MC blocks associated with this instruction.
1540 self.aoMcBlocks = [] # type: List[McBlock]
1541
1542 def toString(self, fRepr = False):
1543 """ Turn object into a string. """
1544 aasFields = [];
1545
1546 aasFields.append(['opcode', self.sOpcode]);
1547 if self.sPrefix:
1548 aasFields.append(['prefix', self.sPrefix]);
1549 aasFields.append(['mnemonic', self.sMnemonic]);
1550 for iOperand, oOperand in enumerate(self.aoOperands):
1551 aasFields.append(['op%u' % (iOperand + 1,), '%s:%s' % (oOperand.sWhere, oOperand.sType,)]);
1552 if self.aoMaps: aasFields.append(['maps', ','.join([oMap.sName for oMap in self.aoMaps])]);
1553 aasFields.append(['encoding', self.sEncoding]);
1554 if self.dHints: aasFields.append(['hints', ','.join(self.dHints.keys())]);
1555 aasFields.append(['disenum', self.sDisEnum]);
1556 if self.asCpuIds: aasFields.append(['cpuid', ','.join(self.asCpuIds)]);
1557 aasFields.append(['group', self.sGroup]);
1558 if self.fUnused: aasFields.append(['unused', 'True']);
1559 if self.fInvalid: aasFields.append(['invalid', 'True']);
1560 aasFields.append(['invlstyle', self.sInvalidStyle]);
1561 aasFields.append(['fltest', self.asFlTest]);
1562 aasFields.append(['flmodify', self.asFlModify]);
1563 aasFields.append(['flundef', self.asFlUndefined]);
1564 aasFields.append(['flset', self.asFlSet]);
1565 aasFields.append(['flclear', self.asFlClear]);
1566 aasFields.append(['mincpu', self.sMinCpu]);
1567 aasFields.append(['stats', self.sStats]);
1568 aasFields.append(['sFunction', self.sFunction]);
1569 if self.fStub: aasFields.append(['fStub', 'True']);
1570 if self.fUdStub: aasFields.append(['fUdStub', 'True']);
1571 if self.cOpTags: aasFields.append(['optags', str(self.cOpTags)]);
1572 if self.iLineFnIemOpMacro != -1: aasFields.append(['FNIEMOP_XXX', str(self.iLineFnIemOpMacro)]);
1573 if self.iLineMnemonicMacro != -1: aasFields.append(['IEMOP_MNEMMONICn', str(self.iLineMnemonicMacro)]);
1574
1575 sRet = '<' if fRepr else '';
1576 for sField, sValue in aasFields:
1577 if sValue is not None:
1578 if len(sRet) > 1:
1579 sRet += '; ';
1580 sRet += '%s=%s' % (sField, sValue,);
1581 if fRepr:
1582 sRet += '>';
1583
1584 return sRet;
1585
1586 def __str__(self):
1587 """ Provide string represenation. """
1588 return self.toString(False);
1589
1590 def __repr__(self):
1591 """ Provide unambigious string representation. """
1592 return self.toString(True);
1593
1594 def copy(self, oMap = None, sOpcode = None, sSubOpcode = None, sPrefix = None):
1595 """
1596 Makes a copy of the object for the purpose of putting in a different map
1597 or a different place in the current map.
1598 """
1599 oCopy = Instruction(self.sSrcFile, self.iLineCreated);
1600
1601 oCopy.oParent = self;
1602 oCopy.sMnemonic = self.sMnemonic;
1603 oCopy.sBrief = self.sBrief;
1604 oCopy.asDescSections = list(self.asDescSections);
1605 oCopy.aoMaps = [oMap,] if oMap else list(self.aoMaps);
1606 oCopy.aoOperands = list(self.aoOperands); ## Deeper copy?
1607 oCopy.sPrefix = sPrefix if sPrefix else self.sPrefix;
1608 oCopy.sOpcode = sOpcode if sOpcode else self.sOpcode;
1609 oCopy.sSubOpcode = sSubOpcode if sSubOpcode else self.sSubOpcode;
1610 oCopy.sEncoding = self.sEncoding;
1611 oCopy.asFlTest = self.asFlTest;
1612 oCopy.asFlModify = self.asFlModify;
1613 oCopy.asFlUndefined = self.asFlUndefined;
1614 oCopy.asFlSet = self.asFlSet;
1615 oCopy.asFlClear = self.asFlClear;
1616 oCopy.dHints = dict(self.dHints);
1617 oCopy.sDisEnum = self.sDisEnum;
1618 oCopy.asCpuIds = list(self.asCpuIds);
1619 oCopy.asReqFeatures = list(self.asReqFeatures);
1620 oCopy.aoTests = list(self.aoTests); ## Deeper copy?
1621 oCopy.sMinCpu = self.sMinCpu;
1622 oCopy.oCpuExpr = self.oCpuExpr;
1623 oCopy.sGroup = self.sGroup;
1624 oCopy.fUnused = self.fUnused;
1625 oCopy.fInvalid = self.fInvalid;
1626 oCopy.sInvalidStyle = self.sInvalidStyle;
1627 oCopy.sXcptType = self.sXcptType;
1628
1629 oCopy.sStats = self.sStats;
1630 oCopy.sFunction = self.sFunction;
1631 oCopy.fStub = self.fStub;
1632 oCopy.fUdStub = self.fUdStub;
1633
1634 oCopy.iLineCompleted = self.iLineCompleted;
1635 oCopy.cOpTags = self.cOpTags;
1636 oCopy.iLineFnIemOpMacro = self.iLineFnIemOpMacro;
1637 oCopy.iLineMnemonicMacro = self.iLineMnemonicMacro;
1638
1639 oCopy.sRawDisOpNo = self.sRawDisOpNo;
1640 oCopy.asRawDisParams = list(self.asRawDisParams);
1641 oCopy.sRawIemOpFlags = self.sRawIemOpFlags;
1642 oCopy.sRawOldOpcodes = self.sRawOldOpcodes;
1643 oCopy.asCopyTests = list(self.asCopyTests);
1644
1645 return oCopy;
1646
1647 def getOpcodeByte(self):
1648 """
1649 Decodes sOpcode into a byte range integer value.
1650 Raises exception if sOpcode is None or invalid.
1651 """
1652 if self.sOpcode is None:
1653 raise Exception('No opcode byte for %s!' % (self,));
1654 sOpcode = str(self.sOpcode); # pylint type confusion workaround.
1655
1656 # Full hex byte form.
1657 if sOpcode[:2] == '0x':
1658 return int(sOpcode, 16);
1659
1660 # The /r form:
1661 if len(sOpcode) == 2 and sOpcode[0] == '/' and sOpcode[1].isdigit():
1662 return int(sOpcode[1:]) << 3;
1663
1664 # The 11/r form:
1665 if len(sOpcode) == 4 and sOpcode.startswith('11/') and sOpcode[-1].isdigit():
1666 return (int(sOpcode[-1:]) << 3) | 0xc0;
1667
1668 # The !11/r form (returns mod=1):
1669 ## @todo this doesn't really work...
1670 if len(sOpcode) == 5 and sOpcode.startswith('!11/') and sOpcode[-1].isdigit():
1671 return (int(sOpcode[-1:]) << 3) | 0x80;
1672
1673 raise Exception('unsupported opcode byte spec "%s" for %s' % (sOpcode, self,));
1674
1675 @staticmethod
1676 def _flagsToIntegerMask(asFlags):
1677 """
1678 Returns the integer mask value for asFlags.
1679 """
1680 uRet = 0;
1681 if asFlags:
1682 for sFlag in asFlags:
1683 sConstant = g_kdEFlagsMnemonics[sFlag];
1684 assert sConstant[0] != '!', sConstant
1685 uRet |= g_kdX86EFlagsConstants[sConstant];
1686 return uRet;
1687
1688 def getTestedFlagsMask(self):
1689 """ Returns asFlTest into a integer mask value """
1690 return self._flagsToIntegerMask(self.asFlTest);
1691
1692 def getModifiedFlagsMask(self):
1693 """ Returns asFlModify into a integer mask value """
1694 return self._flagsToIntegerMask(self.asFlModify);
1695
1696 def getUndefinedFlagsMask(self):
1697 """ Returns asFlUndefined into a integer mask value """
1698 return self._flagsToIntegerMask(self.asFlUndefined);
1699
1700 def getSetFlagsMask(self):
1701 """ Returns asFlSet into a integer mask value """
1702 return self._flagsToIntegerMask(self.asFlSet);
1703
1704 def getClearedFlagsMask(self):
1705 """ Returns asFlClear into a integer mask value """
1706 return self._flagsToIntegerMask(self.asFlClear);
1707
1708 @staticmethod
1709 def _flagsToC(asFlags):
1710 """
1711 Returns asFlags converted to X86_EFL_XXX ored together C-style.
1712 """
1713 if asFlags:
1714 asRet = [];
1715 for sFlag in asFlags:
1716 sConstant = g_kdEFlagsMnemonics[sFlag];
1717 assert sConstant[0] != '!', sConstant
1718 asRet.append(sConstant);
1719 return ' | '.join(asRet);
1720 return '0';
1721
1722 def getTestedFlagsCStyle(self):
1723 """ Returns asFlTest as C constants ored together. """
1724 return self._flagsToC(self.asFlTest);
1725
1726 def getModifiedFlagsCStyle(self):
1727 """ Returns asFlModify as C constants ored together. """
1728 return self._flagsToC(self.asFlModify);
1729
1730 def getUndefinedFlagsCStyle(self):
1731 """ Returns asFlUndefined as C constants ored together. """
1732 return self._flagsToC(self.asFlUndefined);
1733
1734 def getSetFlagsCStyle(self):
1735 """ Returns asFlSet as C constants ored together. """
1736 return self._flagsToC(self.asFlSet);
1737
1738 def getClearedFlagsCStyle(self):
1739 """ Returns asFlClear as C constants ored together. """
1740 return self._flagsToC(self.asFlClear);
1741
1742 def onlyInVexMaps(self):
1743 """ Returns True if only in VEX maps, otherwise False. (No maps -> False) """
1744 if not self.aoMaps:
1745 return False;
1746 for oMap in self.aoMaps:
1747 if not oMap.isVexMap():
1748 return False;
1749 return True;
1750
1751
1752
1753## All the instructions.
1754g_aoAllInstructions = [] # type: List[Instruction]
1755
1756## All the instructions indexed by statistics name (opstat).
1757g_dAllInstructionsByStat = {} # type: Dict[Instruction]
1758
1759## All the instructions indexed by function name (opfunction).
1760g_dAllInstructionsByFunction = {} # type: Dict[List[Instruction]]
1761
1762## Instructions tagged by oponlytest
1763g_aoOnlyTestInstructions = [] # type: List[Instruction]
1764
1765## Instruction maps.
1766g_aoInstructionMaps = [
1767 InstructionMap('one', 'g_apfnOneByteMap', sSelector = 'byte'),
1768 InstructionMap('grp1_80', asLeadOpcodes = ['0x80',], sSelector = '/r'),
1769 InstructionMap('grp1_81', asLeadOpcodes = ['0x81',], sSelector = '/r'),
1770 InstructionMap('grp1_82', asLeadOpcodes = ['0x82',], sSelector = '/r'),
1771 InstructionMap('grp1_83', asLeadOpcodes = ['0x83',], sSelector = '/r'),
1772 InstructionMap('grp1a', asLeadOpcodes = ['0x8f',], sSelector = '/r'),
1773 InstructionMap('grp2_c0', asLeadOpcodes = ['0xc0',], sSelector = '/r'),
1774 InstructionMap('grp2_c1', asLeadOpcodes = ['0xc1',], sSelector = '/r'),
1775 InstructionMap('grp2_d0', asLeadOpcodes = ['0xd0',], sSelector = '/r'),
1776 InstructionMap('grp2_d1', asLeadOpcodes = ['0xd1',], sSelector = '/r'),
1777 InstructionMap('grp2_d2', asLeadOpcodes = ['0xd2',], sSelector = '/r'),
1778 InstructionMap('grp2_d3', asLeadOpcodes = ['0xd3',], sSelector = '/r'),
1779 ## @todo g_apfnEscF1_E0toFF
1780 InstructionMap('grp3_f6', asLeadOpcodes = ['0xf6',], sSelector = '/r'),
1781 InstructionMap('grp3_f7', asLeadOpcodes = ['0xf7',], sSelector = '/r'),
1782 InstructionMap('grp4', asLeadOpcodes = ['0xfe',], sSelector = '/r'),
1783 InstructionMap('grp5', asLeadOpcodes = ['0xff',], sSelector = '/r'),
1784 InstructionMap('grp11_c6_m', asLeadOpcodes = ['0xc6',], sSelector = '!11 /r'),
1785 InstructionMap('grp11_c6_r', asLeadOpcodes = ['0xc6',], sSelector = '11'), # xabort
1786 InstructionMap('grp11_c7_m', asLeadOpcodes = ['0xc7',], sSelector = '!11 /r'),
1787 InstructionMap('grp11_c7_r', asLeadOpcodes = ['0xc7',], sSelector = '11'), # xbegin
1788
1789 InstructionMap('two0f', 'g_apfnTwoByteMap', asLeadOpcodes = ['0x0f',], sDisParse = 'IDX_ParseTwoByteEsc'),
1790 InstructionMap('grp6', 'g_apfnGroup6', asLeadOpcodes = ['0x0f', '0x00',], sSelector = '/r'),
1791 InstructionMap('grp7_m', 'g_apfnGroup7Mem', asLeadOpcodes = ['0x0f', '0x01',], sSelector = '!11 /r'),
1792 InstructionMap('grp7_r', asLeadOpcodes = ['0x0f', '0x01',], sSelector = '11'),
1793 InstructionMap('grp8', asLeadOpcodes = ['0x0f', '0xba',], sSelector = '/r'),
1794 InstructionMap('grp9', 'g_apfnGroup9RegReg', asLeadOpcodes = ['0x0f', '0xc7',], sSelector = 'mod /r'),
1795 ## @todo What about g_apfnGroup9MemReg?
1796 InstructionMap('grp10', None, asLeadOpcodes = ['0x0f', '0xb9',], sSelector = '/r'), # UD1 /w modr/m
1797 InstructionMap('grp12', 'g_apfnGroup12RegReg', asLeadOpcodes = ['0x0f', '0x71',], sSelector = 'mod /r'),
1798 InstructionMap('grp13', 'g_apfnGroup13RegReg', asLeadOpcodes = ['0x0f', '0x72',], sSelector = 'mod /r'),
1799 InstructionMap('grp14', 'g_apfnGroup14RegReg', asLeadOpcodes = ['0x0f', '0x73',], sSelector = 'mod /r'),
1800 InstructionMap('grp15', 'g_apfnGroup15MemReg', asLeadOpcodes = ['0x0f', '0xae',], sSelector = 'memreg /r'),
1801 ## @todo What about g_apfnGroup15RegReg?
1802 InstructionMap('grp16', asLeadOpcodes = ['0x0f', '0x18',], sSelector = 'mod /r'),
1803 InstructionMap('grpA17', asLeadOpcodes = ['0x0f', '0x78',], sSelector = '/r'), # AMD: EXTRQ weirdness
1804 InstructionMap('grpP', asLeadOpcodes = ['0x0f', '0x0d',], sSelector = '/r'), # AMD: prefetch
1805
1806 InstructionMap('three0f38', 'g_apfnThreeByte0f38', asLeadOpcodes = ['0x0f', '0x38',]),
1807 InstructionMap('three0f3a', 'g_apfnThreeByte0f3a', asLeadOpcodes = ['0x0f', '0x3a',]),
1808
1809 InstructionMap('vexmap1', 'g_apfnVexMap1', sEncoding = 'vex1'),
1810 InstructionMap('vexgrp12', 'g_apfnVexGroup12RegReg', sEncoding = 'vex1', asLeadOpcodes = ['0x71',], sSelector = 'mod /r'),
1811 InstructionMap('vexgrp13', 'g_apfnVexGroup13RegReg', sEncoding = 'vex1', asLeadOpcodes = ['0x72',], sSelector = 'mod /r'),
1812 InstructionMap('vexgrp14', 'g_apfnVexGroup14RegReg', sEncoding = 'vex1', asLeadOpcodes = ['0x73',], sSelector = 'mod /r'),
1813 InstructionMap('vexgrp15', 'g_apfnVexGroup15MemReg', sEncoding = 'vex1', asLeadOpcodes = ['0xae',], sSelector = 'memreg /r'),
1814 InstructionMap('vexgrp17', 'g_apfnVexGroup17_f3', sEncoding = 'vex1', asLeadOpcodes = ['0xf3',], sSelector = '/r'),
1815
1816 InstructionMap('vexmap2', 'g_apfnVexMap2', sEncoding = 'vex2'),
1817 InstructionMap('vexmap3', 'g_apfnVexMap3', sEncoding = 'vex3'),
1818
1819 InstructionMap('3dnow', asLeadOpcodes = ['0x0f', '0x0f',]),
1820 InstructionMap('xopmap8', sEncoding = 'xop8'),
1821 InstructionMap('xopmap9', sEncoding = 'xop9'),
1822 InstructionMap('xopgrp1', sEncoding = 'xop9', asLeadOpcodes = ['0x01'], sSelector = '/r'),
1823 InstructionMap('xopgrp2', sEncoding = 'xop9', asLeadOpcodes = ['0x02'], sSelector = '/r'),
1824 InstructionMap('xopgrp3', sEncoding = 'xop9', asLeadOpcodes = ['0x12'], sSelector = '/r'),
1825 InstructionMap('xopmap10', sEncoding = 'xop10'),
1826 InstructionMap('xopgrp4', sEncoding = 'xop10', asLeadOpcodes = ['0x12'], sSelector = '/r'),
1827];
1828g_dInstructionMaps = { oMap.sName: oMap for oMap in g_aoInstructionMaps };
1829g_dInstructionMapsByIemName = { oMap.sIemName: oMap for oMap in g_aoInstructionMaps };
1830
1831
1832#
1833# Decoder functions.
1834#
1835
1836class DecoderFunction(object):
1837 """
1838 Decoder function.
1839
1840 This is mainly for searching for scoping searches for variables used in
1841 microcode blocks.
1842 """
1843 def __init__(self, sSrcFile, iBeginLine, sName, asDefArgs):
1844 self.sName = sName; ##< The function name.
1845 self.asDefArgs = asDefArgs; ##< The FNIEMOP*DEF/STUB* macro argument list, 0th element is the macro name.
1846 self.sSrcFile = sSrcFile; ##< The source file the function is defined in.
1847 self.iBeginLine = iBeginLine; ##< The start line.
1848 self.iEndLine = -1; ##< The line the function (probably) ends on.
1849 self.asLines = [] # type: List[str] ##< The raw lines the function is made up of.
1850
1851 def complete(self, iEndLine, asLines):
1852 """
1853 Completes the function.
1854 """
1855 assert self.iEndLine == -1;
1856 self.iEndLine = iEndLine;
1857 self.asLines = asLines;
1858
1859
1860#
1861# "Microcode" statements and blocks
1862#
1863
1864class McStmt(object):
1865 """
1866 Statement in a microcode block.
1867 """
1868 def __init__(self, sName, asParams):
1869 self.sName = sName; ##< 'IEM_MC_XXX' or 'C++'.
1870 self.asParams = asParams;
1871 self.oUser = None;
1872
1873 def renderCode(self, cchIndent = 0):
1874 """
1875 Renders the code for the statement.
1876 """
1877 return ' ' * cchIndent + self.sName + '(' + ', '.join(self.asParams) + ');\n';
1878
1879 @staticmethod
1880 def renderCodeForList(aoStmts, cchIndent = 0):
1881 """
1882 Renders a list of statements.
1883 """
1884 return ''.join([oStmt.renderCode(cchIndent) for oStmt in aoStmts]);
1885
1886 @staticmethod
1887 def findStmtByNames(aoStmts, dNames):
1888 """
1889 Returns first statement with any of the given names in from the list.
1890
1891 Note! The names are passed as a dictionary for quick lookup, the value
1892 does not matter.
1893 """
1894 for oStmt in aoStmts:
1895 if oStmt.sName in dNames:
1896 return oStmt;
1897 if isinstance(oStmt, McStmtCond):
1898 oHit = McStmt.findStmtByNames(oStmt.aoIfBranch, dNames);
1899 if not oHit:
1900 oHit = McStmt.findStmtByNames(oStmt.aoElseBranch, dNames);
1901 if oHit:
1902 return oHit;
1903 return None;
1904
1905 @staticmethod
1906 def countStmtsByName(aoStmts, dNames, dRet):
1907 """
1908 Searches the given list of statements for the names in the dictionary,
1909 adding each found to dRet with an occurnece count.
1910
1911 return total number of hits;
1912 """
1913 cHits = 0;
1914 for oStmt in aoStmts:
1915 if oStmt.sName in dNames:
1916 dRet[oStmt.sName] = dRet.get(oStmt.sName, 0) + 1;
1917 cHits += 1;
1918 if isinstance(oStmt, McStmtCond):
1919 cHits += McStmt.countStmtsByName(oStmt.aoIfBranch, dNames, dRet);
1920 cHits += McStmt.countStmtsByName(oStmt.aoElseBranch, dNames, dRet);
1921 return cHits;
1922
1923 def isCppStmt(self):
1924 """ Checks if this is a C++ statement. """
1925 return self.sName.startswith('C++');
1926
1927class McStmtCond(McStmt):
1928 """
1929 Base class for conditional statements (IEM_MC_IF_XXX, IEM_MC_NATIVE_IF).
1930 """
1931 def __init__(self, sName, asParams, aoIfBranch = None, aoElseBranch = None):
1932 McStmt.__init__(self, sName, asParams);
1933 self.aoIfBranch = [] if aoIfBranch is None else list(aoIfBranch);
1934 self.aoElseBranch = [] if aoElseBranch is None else list(aoElseBranch);
1935 self.oIfBranchAnnotation = None; ##< User specific IF-branch annotation.
1936 self.oElseBranchAnnotation = None; ##< User specific IF-branch annotation.
1937 self.sNativeInfix = '' if sName != 'IEM_MC_NATIVE_IF' else '_NATIVE';
1938
1939 def renderCode(self, cchIndent = 0):
1940 sRet = ' ' * cchIndent + self.sName + '(' + ', '.join(self.asParams) + ') {\n';
1941 sRet += self.renderCodeForList(self.aoIfBranch, cchIndent + 4);
1942 if self.aoElseBranch:
1943 sRet += ' ' * cchIndent + '} IEM_MC%s_ELSE() {\n' % (self.sNativeInfix,);
1944 sRet += self.renderCodeForList(self.aoElseBranch, cchIndent + 4);
1945 sRet += ' ' * cchIndent + '} IEM_MC%s_ENDIF();\n' % (self.sNativeInfix,);
1946 return sRet;
1947
1948class McStmtNativeIf(McStmtCond):
1949 """ IEM_MC_NATIVE_IF """
1950 def __init__(self, sName, asArchitectures):
1951 McStmtCond.__init__(self, sName, ['|'.join(asArchitectures) if asArchitectures else '0',]);
1952 self.asArchitectures = asArchitectures;
1953
1954class McStmtVar(McStmt):
1955 """ IEM_MC_LOCAL, IEM_MC_LOCAL_ASSIGN, IEM_MC_LOCAL_CONST """
1956 def __init__(self, sName, asParams, sType, sVarName, sValue = None):
1957 McStmt.__init__(self, sName, asParams);
1958 self.sType = sType;
1959 self.sVarName = sVarName;
1960 self.sValue = sValue; ##< None if no assigned / const value.
1961
1962class McStmtArg(McStmtVar):
1963 """ IEM_MC_ARG, IEM_MC_ARG_CONST, IEM_MC_ARG_LOCAL_REF """
1964 def __init__(self, sName, asParams, sType, sVarName, iArg, sConstValue = None, sRef = None, sRefType = 'none'):
1965 McStmtVar.__init__(self, sName, asParams, sType, sVarName, sConstValue);
1966 self.iArg = iArg;
1967 self.sRef = sRef; ##< The reference string (local variable, register).
1968 self.sRefType = sRefType; ##< The kind of reference: 'local', 'none'.
1969 assert sRefType in ('none', 'local');
1970
1971class McStmtCall(McStmt):
1972 """ IEM_MC_CALL_* """
1973 def __init__(self, sName, asParams, iFnParam, iRcNameParam = -1):
1974 McStmt.__init__(self, sName, asParams);
1975 self.idxFn = iFnParam;
1976 self.idxParams = iFnParam + 1;
1977 self.sFn = asParams[iFnParam];
1978 self.iRcName = None if iRcNameParam < 0 else asParams[iRcNameParam];
1979
1980class McStmtAssertEFlags(McStmt):
1981 """
1982 IEM_MC_ASSERT_EFLAGS
1983 """
1984 def __init__(self, oInstruction):
1985 McStmt.__init__(self, 'IEM_MC_ASSERT_EFLAGS',
1986 [oInstruction.getTestedFlagsCStyle(), oInstruction.getModifiedFlagsCStyle(),]);
1987
1988
1989class McCppGeneric(McStmt):
1990 """
1991 Generic C++/C statement.
1992 """
1993 def __init__(self, sCode, fDecode = True, sName = 'C++', cchIndent = 0):
1994 McStmt.__init__(self, sName, [sCode,]);
1995 self.fDecode = fDecode;
1996 self.cchIndent = cchIndent;
1997
1998 def renderCode(self, cchIndent = 0):
1999 cchIndent += self.cchIndent;
2000 sRet = ' ' * cchIndent + self.asParams[0] + '\n';
2001 if self.fDecode:
2002 sRet = sRet.replace('\n', ' // C++ decode\n');
2003 else:
2004 sRet = sRet.replace('\n', ' // C++ normal\n');
2005 return sRet;
2006
2007class McCppCall(McCppGeneric):
2008 """
2009 A generic C++/C call statement.
2010
2011 The sName is still 'C++', so the function name is in the first parameter
2012 and the the arguments in the subsequent ones.
2013 """
2014 def __init__(self, sFnName, asArgs, fDecode = True, cchIndent = 0):
2015 McCppGeneric.__init__(self, sFnName, fDecode = fDecode, cchIndent = cchIndent);
2016 self.asParams.extend(asArgs);
2017
2018 def renderCode(self, cchIndent = 0):
2019 cchIndent += self.cchIndent;
2020 sRet = ' ' * cchIndent + self.asParams[0] + '(' + ', '.join(self.asParams[1:]) + ');';
2021 if self.fDecode:
2022 sRet += ' // C++ decode\n';
2023 else:
2024 sRet += ' // C++ normal\n';
2025 return sRet;
2026
2027class McCppCond(McStmtCond):
2028 """
2029 C++/C 'if' statement.
2030 """
2031 def __init__(self, sCode, fDecode = True, aoIfBranch = None, aoElseBranch = None, cchIndent = 0):
2032 McStmtCond.__init__(self, 'C++/if', [sCode,], aoIfBranch, aoElseBranch);
2033 self.fDecode = fDecode;
2034 self.cchIndent = cchIndent;
2035
2036 def renderCode(self, cchIndent = 0):
2037 cchIndent += self.cchIndent;
2038 sAnnotation = '// C++ decode' if self.fDecode else '// C++ normal';
2039 sRet = ' ' * cchIndent + 'if (' + self.asParams[0] + ') ' + sAnnotation + '\n';
2040 sRet += ' ' * cchIndent + '{\n';
2041 sRet += self.renderCodeForList(self.aoIfBranch, cchIndent + 4);
2042 sRet += ' ' * cchIndent + '}\n';
2043 if self.aoElseBranch:
2044 sRet += ' ' * cchIndent + 'else ' + sAnnotation + '\n';
2045 sRet += ' ' * cchIndent + '{\n';
2046 sRet += self.renderCodeForList(self.aoElseBranch, cchIndent + 4);
2047 sRet += ' ' * cchIndent + '}\n';
2048 return sRet;
2049
2050class McCppPreProc(McCppGeneric):
2051 """
2052 C++/C Preprocessor directive.
2053 """
2054 def __init__(self, sCode):
2055 McCppGeneric.__init__(self, sCode, False, sName = 'C++/preproc');
2056
2057 def renderCode(self, cchIndent = 0):
2058 return self.asParams[0] + '\n';
2059
2060
2061## IEM_MC_F_XXX values.
2062g_kdMcFlags = {
2063 'IEM_MC_F_ONLY_8086': (),
2064 'IEM_MC_F_MIN_186': (),
2065 'IEM_MC_F_MIN_286': (),
2066 'IEM_MC_F_NOT_286_OR_OLDER': (),
2067 'IEM_MC_F_MIN_386': ('IEM_MC_F_NOT_286_OR_OLDER',),
2068 'IEM_MC_F_MIN_486': ('IEM_MC_F_NOT_286_OR_OLDER',),
2069 'IEM_MC_F_MIN_PENTIUM': ('IEM_MC_F_NOT_286_OR_OLDER',),
2070 'IEM_MC_F_MIN_PENTIUM_II': ('IEM_MC_F_NOT_286_OR_OLDER',),
2071 'IEM_MC_F_MIN_CORE': ('IEM_MC_F_NOT_286_OR_OLDER',),
2072 'IEM_MC_F_64BIT': ('IEM_MC_F_NOT_286_OR_OLDER',),
2073 'IEM_MC_F_NOT_64BIT': (),
2074};
2075## IEM_MC_F_XXX values.
2076g_kdCImplFlags = {
2077 'IEM_CIMPL_F_BRANCH_DIRECT': (),
2078 'IEM_CIMPL_F_BRANCH_INDIRECT': (),
2079 'IEM_CIMPL_F_BRANCH_RELATIVE': (),
2080 'IEM_CIMPL_F_BRANCH_CONDITIONAL': (),
2081 'IEM_CIMPL_F_BRANCH_FAR': (),
2082 'IEM_CIMPL_F_BRANCH_ANY': ('IEM_CIMPL_F_BRANCH_DIRECT', 'IEM_CIMPL_F_BRANCH_INDIRECT',
2083 'IEM_CIMPL_F_BRANCH_RELATIVE',),
2084 'IEM_CIMPL_F_BRANCH_STACK': (),
2085 'IEM_CIMPL_F_BRANCH_STACK_FAR': (),
2086 'IEM_CIMPL_F_MODE': (),
2087 'IEM_CIMPL_F_RFLAGS': (),
2088 'IEM_CIMPL_F_INHIBIT_SHADOW': (),
2089 'IEM_CIMPL_F_STATUS_FLAGS': (),
2090 'IEM_CIMPL_F_CHECK_IRQ_AFTER': (),
2091 'IEM_CIMPL_F_CHECK_IRQ_BEFORE': (),
2092 'IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER': ('IEM_CIMPL_F_CHECK_IRQ_BEFORE', 'IEM_CIMPL_F_CHECK_IRQ_AFTER',),
2093 'IEM_CIMPL_F_VMEXIT': (),
2094 'IEM_CIMPL_F_FPU': (),
2095 'IEM_CIMPL_F_REP': (),
2096 'IEM_CIMPL_F_IO': (),
2097 'IEM_CIMPL_F_END_TB': (),
2098 'IEM_CIMPL_F_XCPT': ('IEM_CIMPL_F_BRANCH_INDIRECT', 'IEM_CIMPL_F_BRANCH_FAR',
2099 'IEM_CIMPL_F_MODE', 'IEM_CIMPL_F_RFLAGS', 'IEM_CIMPL_F_VMEXIT', ),
2100 'IEM_CIMPL_F_CALLS_CIMPL': (),
2101 'IEM_CIMPL_F_CALLS_AIMPL': (),
2102 'IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE': (),
2103};
2104class McBlock(object):
2105 """
2106 Microcode block (IEM_MC_BEGIN ... IEM_MC_END, IEM_MC_DEFER_TO_CIMPL_x_RET).
2107 """
2108
2109 ## @name Macro expansion types.
2110 ## @{
2111 kiMacroExp_None = 0;
2112 kiMacroExp_Entire = 1; ##< Entire block (iBeginLine == iEndLine), original line may contain multiple blocks.
2113 kiMacroExp_Partial = 2; ##< Partial/mixed (cmpxchg16b), safe to assume single block.
2114 ## @}
2115
2116 def __init__(self, sSrcFile, iBeginLine, offBeginLine, oFunction, iInFunction,
2117 oInstruction = None, cchIndent = None, fDeferToCImpl = False):
2118 ## Set if IEM_MC_DEFER_TO_CIMPL_0_RET and friends, clear if IEM_MC_BEGIN/END block.
2119 self.fDeferToCImpl = fDeferToCImpl;
2120 ## The source file containing the block.
2121 self.sSrcFile = sSrcFile;
2122 ## The line with the IEM_MC_BEGIN/IEM_MC_DEFER_TO_CIMPL_X_RET statement.
2123 self.iBeginLine = iBeginLine;
2124 ## The offset of the IEM_MC_BEGIN/IEM_MC_DEFER_TO_CIMPL_X_RET statement within the line.
2125 self.offBeginLine = offBeginLine;
2126 ## The line with the IEM_MC_END statement / last line of IEM_MC_DEFER_TO_CIMPL_X_RET.
2127 self.iEndLine = -1;
2128 ## The offset of the IEM_MC_END statement within the line / semicolon offset for defer-to.
2129 self.offEndLine = 0;
2130 ## The offset following the IEM_MC_END/IEM_MC_DEFER_TO_CIMPL_X_RET semicolon.
2131 self.offAfterEnd = 0;
2132 ## The function the block resides in.
2133 self.oFunction = oFunction;
2134 ## The name of the function the block resides in. DEPRECATED.
2135 self.sFunction = oFunction.sName;
2136 ## The block number within the function.
2137 self.iInFunction = iInFunction;
2138 ## The instruction this block is associated with - can be None.
2139 self.oInstruction = oInstruction # type: Instruction
2140 ## Indentation level of the block.
2141 self.cchIndent = cchIndent if cchIndent else offBeginLine;
2142 ## The raw lines the block is made up of.
2143 self.asLines = [] # type: List[str]
2144 ## Indicates whether the block includes macro expansion parts (kiMacroExp_None,
2145 ## kiMacroExp_Entrie, kiMacroExp_Partial).
2146 self.iMacroExp = self.kiMacroExp_None;
2147 ## IEM_MC_ARG, IEM_MC_ARG_CONST, IEM_MC_ARG_LOCAL_REF, IEM_MC_ARG_LOCAL_EFLAGS.
2148 self.aoArgs = [] # type: List[McStmtArg]
2149 ## IEM_MC_LOCAL, IEM_MC_LOCAL_CONST, IEM_MC_ARG_LOCAL_EFLAGS.
2150 self.aoLocals = [] # type: List[McStmtVar]
2151 ## IEM_MC_BEGIN: IEM_MC_F_XXX dictionary
2152 self.dsMcFlags = {} # type: Dict[str, bool]
2153 ## IEM_MC_[DEFER_TO|CALL]_CIMPL_XXX: IEM_CIMPL_F_XXX dictionary
2154 self.dsCImplFlags = {} # type: Dict[str, bool]
2155 ## Decoded statements in the block.
2156 self.aoStmts = [] # type: List[McStmt]
2157
2158 def complete(self, iEndLine, offEndLine, offAfterEnd, asLines):
2159 """
2160 Completes the microcode block.
2161 """
2162 assert self.iEndLine == -1;
2163 self.iEndLine = iEndLine;
2164 self.offEndLine = offEndLine;
2165 self.offAfterEnd = offAfterEnd;
2166 self.asLines = asLines;
2167
2168 def raiseDecodeError(self, sRawCode, off, sMessage):
2169 """ Raises a decoding error. """
2170 offStartOfLine = sRawCode.rfind('\n', 0, off) + 1;
2171 iLine = sRawCode.count('\n', 0, off);
2172 raise ParserException('%s:%d:%d: parsing error: %s'
2173 % (self.sSrcFile, self.iBeginLine + iLine, off - offStartOfLine + 1, sMessage,));
2174
2175 def raiseStmtError(self, sName, sMessage):
2176 """ Raises a statement parser error. """
2177 raise ParserException('%s:%d: %s: parsing error: %s' % (self.sSrcFile, self.iBeginLine, sName, sMessage,));
2178
2179 def checkStmtParamCount(self, sName, asParams, cParamsExpected):
2180 """ Check the parameter count, raising an error it doesn't match. """
2181 if len(asParams) != cParamsExpected:
2182 raise ParserException('%s:%d: %s: Expected %s parameters, found %s!'
2183 % (self.sSrcFile, self.iBeginLine, sName, cParamsExpected, len(asParams),));
2184 return True;
2185
2186 @staticmethod
2187 def parseMcGeneric(oSelf, sName, asParams):
2188 """ Generic parser that returns a plain McStmt object. """
2189 _ = oSelf;
2190 return McStmt(sName, asParams);
2191
2192 @staticmethod
2193 def parseMcGenericCond(oSelf, sName, asParams):
2194 """ Generic parser that returns a plain McStmtCond object. """
2195 _ = oSelf;
2196 return McStmtCond(sName, asParams);
2197
2198 kdArchVals = {
2199 'RT_ARCH_VAL_X86': True,
2200 'RT_ARCH_VAL_AMD64': True,
2201 'RT_ARCH_VAL_ARM32': True,
2202 'RT_ARCH_VAL_ARM64': True,
2203 'RT_ARCH_VAL_SPARC32': True,
2204 'RT_ARCH_VAL_SPARC64': True,
2205 };
2206
2207 @staticmethod
2208 def parseMcNativeIf(oSelf, sName, asParams):
2209 """ IEM_MC_NATIVE_IF """
2210 oSelf.checkStmtParamCount(sName, asParams, 1);
2211 if asParams[0].strip() == '0':
2212 asArchitectures = [];
2213 else:
2214 asArchitectures = [sArch.strip() for sArch in asParams[0].split('|')];
2215 for sArch in asArchitectures:
2216 if sArch not in oSelf.kdArchVals:
2217 oSelf.raiseStmtError(sName, 'Unknown architecture: %s' % (sArch,));
2218 return McStmtNativeIf(sName, asArchitectures);
2219
2220 @staticmethod
2221 def parseMcBegin(oSelf, sName, asParams):
2222 """ IEM_MC_BEGIN """
2223 oSelf.checkStmtParamCount(sName, asParams, 2);
2224 if oSelf.dsMcFlags:
2225 oSelf.raiseStmtError(sName, 'Used more than once!');
2226
2227 if asParams[0] != '0':
2228 for sFlag in asParams[0].split('|'):
2229 sFlag = sFlag.strip();
2230 if sFlag not in g_kdMcFlags:
2231 oSelf.raiseStmtError(sName, 'Unknown flag: %s' % (sFlag, ));
2232 oSelf.dsMcFlags[sFlag] = True;
2233 for sFlag2 in g_kdMcFlags[sFlag]:
2234 oSelf.dsMcFlags[sFlag2] = True;
2235
2236 if asParams[1] != '0':
2237 oSelf.parseCImplFlags(sName, asParams[1]);
2238
2239 return McBlock.parseMcGeneric(oSelf, sName, asParams);
2240
2241 @staticmethod
2242 def parseMcArg(oSelf, sName, asParams):
2243 """ IEM_MC_ARG """
2244 oSelf.checkStmtParamCount(sName, asParams, 3);
2245 oStmt = McStmtArg(sName, asParams, asParams[0], asParams[1], int(asParams[2]));
2246 oSelf.aoArgs.append(oStmt);
2247 return oStmt;
2248
2249 @staticmethod
2250 def parseMcArgConst(oSelf, sName, asParams):
2251 """ IEM_MC_ARG_CONST """
2252 oSelf.checkStmtParamCount(sName, asParams, 4);
2253 oStmt = McStmtArg(sName, asParams, asParams[0], asParams[1], int(asParams[3]), sConstValue = asParams[2]);
2254 oSelf.aoArgs.append(oStmt);
2255 return oStmt;
2256
2257 @staticmethod
2258 def parseMcArgLocalRef(oSelf, sName, asParams):
2259 """ IEM_MC_ARG_LOCAL_REF """
2260 oSelf.checkStmtParamCount(sName, asParams, 4);
2261 oStmt = McStmtArg(sName, asParams, asParams[0], asParams[1], int(asParams[3]), sRef = asParams[2], sRefType = 'local');
2262 oSelf.aoArgs.append(oStmt);
2263 return oStmt;
2264
2265 @staticmethod
2266 def parseMcArgEFlags(oSelf, sName, asParams):
2267 """ IEM_MC_ARG_EFLAGS """
2268 oSelf.checkStmtParamCount(sName, asParams, 2);
2269 # Note! We split this one up into IEM_MC_ARG and IEM_MC_FETCH_EFLAGS.
2270 oStmtArg = McStmtArg('IEM_MC_ARG', ['uint32_t', asParams[0], asParams[1]], 'uint32_t', asParams[0], int(asParams[1]));
2271 oSelf.aoArgs.append(oStmtArg);
2272 oStmtFetch = McStmt('IEM_MC_FETCH_EFLAGS', [asParams[0]]);
2273 return (oStmtArg, oStmtFetch,);
2274
2275 @staticmethod
2276 def parseMcArgLocalEFlags(oSelf, sName, asParams):
2277 """ IEM_MC_ARG_LOCAL_EFLAGS """
2278 oSelf.checkStmtParamCount(sName, asParams, 3);
2279 # Note! We split this one up into IEM_MC_LOCAL_VAR, IEM_MC_ARG_LOCAL_REF and IEM_MC_FETCH_EFLAGS.
2280 oStmtLocal = McStmtVar('IEM_MC_LOCAL', ['uint32_t', asParams[1],], 'uint32_t', asParams[1]);
2281 oSelf.aoLocals.append(oStmtLocal);
2282 oStmtArg = McStmtArg('IEM_MC_ARG_LOCAL_REF', ['uint32_t *', asParams[0], asParams[1], asParams[2]],
2283 'uint32_t *', asParams[0], int(asParams[2]), sRef = asParams[1], sRefType = 'local');
2284 oSelf.aoArgs.append(oStmtArg);
2285 oStmtFetch = McStmt('IEM_MC_FETCH_EFLAGS', [asParams[1]]);
2286 return (oStmtLocal, oStmtArg, oStmtFetch,);
2287
2288 @staticmethod
2289 def parseMcLocal(oSelf, sName, asParams):
2290 """ IEM_MC_LOCAL """
2291 oSelf.checkStmtParamCount(sName, asParams, 2);
2292 oStmt = McStmtVar(sName, asParams, asParams[0], asParams[1]);
2293 oSelf.aoLocals.append(oStmt);
2294 return oStmt;
2295
2296 @staticmethod
2297 def parseMcLocalAssign(oSelf, sName, asParams):
2298 """ IEM_MC_LOCAL_ASSIGN """
2299 oSelf.checkStmtParamCount(sName, asParams, 3);
2300 oStmt = McStmtVar(sName, asParams, asParams[0], asParams[1], sValue = asParams[2]);
2301 oSelf.aoLocals.append(oStmt);
2302 return oStmt;
2303
2304 @staticmethod
2305 def parseMcLocalConst(oSelf, sName, asParams):
2306 """ IEM_MC_LOCAL_CONST """
2307 oSelf.checkStmtParamCount(sName, asParams, 3);
2308 oStmt = McStmtVar(sName, asParams, asParams[0], asParams[1], sValue = asParams[2]);
2309 oSelf.aoLocals.append(oStmt);
2310 return oStmt;
2311
2312 @staticmethod
2313 def parseMcLocalEFlags(oSelf, sName, asParams):
2314 """ IEM_MC_LOCAL_EFLAGS"""
2315 oSelf.checkStmtParamCount(sName, asParams, 1);
2316 # Note! We split this one up into IEM_MC_LOCAL_VAR and IEM_MC_FETCH_EFLAGS just like with IEM_MC_ARG_LOCAL_EFLAGS.
2317 oStmtLocal = McStmtVar('IEM_MC_LOCAL', ['uint32_t', asParams[0]], 'uint32_t', asParams[0]);
2318 oSelf.aoLocals.append(oStmtLocal);
2319 oStmtFetch = McStmt('IEM_MC_FETCH_EFLAGS', [asParams[0]]);
2320 return (oStmtLocal, oStmtFetch,);
2321
2322 @staticmethod
2323 def parseMcCallAImpl(oSelf, sName, asParams):
2324 """ IEM_MC_CALL_AIMPL_3|4 """
2325 cArgs = int(sName[-1]);
2326 oSelf.checkStmtParamCount(sName, asParams, 3 + cArgs);
2327 oSelf.aoLocals.append(McStmtVar('IEM_MC_LOCAL', [asParams[0], asParams[1]], asParams[0], asParams[1]));
2328 return McStmtCall(sName, asParams, 2, 1);
2329
2330 @staticmethod
2331 def parseMcCallVoidAImpl(oSelf, sName, asParams):
2332 """ IEM_MC_CALL_VOID_AIMPL_2|3 """
2333 cArgs = int(sName[-1]);
2334 oSelf.checkStmtParamCount(sName, asParams, 1 + cArgs);
2335 return McStmtCall(sName, asParams, 0);
2336
2337 @staticmethod
2338 def parseMcCallAvxAImpl(oSelf, sName, asParams):
2339 """ IEM_MC_CALL_AVX_AIMPL_2|3 """
2340 cArgs = int(sName[-1]);
2341 oSelf.checkStmtParamCount(sName, asParams, 1 + cArgs);
2342 return McStmtCall(sName, asParams, 0);
2343
2344 @staticmethod
2345 def parseMcCallFpuAImpl(oSelf, sName, asParams):
2346 """ IEM_MC_CALL_FPU_AIMPL_1|2|3 """
2347 cArgs = int(sName[-1]);
2348 oSelf.checkStmtParamCount(sName, asParams, 1 + cArgs);
2349 return McStmtCall(sName, asParams, 0);
2350
2351 @staticmethod
2352 def parseMcCallMmxAImpl(oSelf, sName, asParams):
2353 """ IEM_MC_CALL_MMX_AIMPL_2|3 """
2354 cArgs = int(sName[-1]);
2355 oSelf.checkStmtParamCount(sName, asParams, 1 + cArgs);
2356 return McStmtCall(sName, asParams, 0);
2357
2358 @staticmethod
2359 def parseMcCallSseAImpl(oSelf, sName, asParams):
2360 """ IEM_MC_CALL_SSE_AIMPL_2|3 """
2361 cArgs = int(sName[-1]);
2362 oSelf.checkStmtParamCount(sName, asParams, 1 + cArgs);
2363 return McStmtCall(sName, asParams, 0);
2364
2365 def parseCImplFlags(self, sName, sFlags):
2366 """
2367 Helper for parseMcCallCImpl and parseMcDeferToCImpl to validate and
2368 merge a bunch of IEM_CIMPL_F_XXX value into dsCImplFlags.
2369 """
2370 if sFlags != '0':
2371 sFlags = self.stripComments(sFlags);
2372 #print('debug: %s: %s' % (self.oFunction.sName,' | '.join(''.join(sFlags.split()).split('|')),));
2373 for sFlag in sFlags.split('|'):
2374 sFlag = sFlag.strip();
2375 if sFlag[0] == '(': sFlag = sFlag[1:].strip();
2376 if sFlag[-1] == ')': sFlag = sFlag[:-1].strip();
2377 #print('debug: %s' % sFlag)
2378 if sFlag not in g_kdCImplFlags:
2379 if sFlag == '0':
2380 continue;
2381 self.raiseStmtError(sName, 'Unknown flag: %s' % (sFlag, ));
2382 self.dsCImplFlags[sFlag] = True;
2383 for sFlag2 in g_kdCImplFlags[sFlag]:
2384 self.dsCImplFlags[sFlag2] = True;
2385 return None;
2386
2387 @staticmethod
2388 def parseMcCallCImpl(oSelf, sName, asParams):
2389 """ IEM_MC_CALL_CIMPL_0|1|2|3|4|5 """
2390 cArgs = int(sName[-1]);
2391 oSelf.checkStmtParamCount(sName, asParams, 3 + cArgs);
2392 oSelf.parseCImplFlags(sName, asParams[0]);
2393 return McStmtCall(sName, asParams, 2);
2394
2395 @staticmethod
2396 def parseMcDeferToCImpl(oSelf, sName, asParams):
2397 """ IEM_MC_DEFER_TO_CIMPL_[0|1|2|3]_RET """
2398 # Note! This code is called by workerIemMcDeferToCImplXRet.
2399 #print('debug: %s, %s,...' % (sName, asParams[0],));
2400 cArgs = int(sName[-5]);
2401 oSelf.checkStmtParamCount(sName, asParams, 3 + cArgs);
2402 oSelf.parseCImplFlags(sName, asParams[0]);
2403 return McStmtCall(sName, asParams, 2);
2404
2405 @staticmethod
2406 def stripComments(sCode):
2407 """ Returns sCode with comments removed. """
2408 off = 0;
2409 while off < len(sCode):
2410 off = sCode.find('/', off);
2411 if off < 0 or off + 1 >= len(sCode):
2412 break;
2413
2414 if sCode[off + 1] == '/':
2415 # C++ comment.
2416 offEnd = sCode.find('\n', off + 2);
2417 if offEnd < 0:
2418 return sCode[:off].rstrip();
2419 sCode = sCode[ : off] + sCode[offEnd : ];
2420 off += 1;
2421
2422 elif sCode[off + 1] == '*':
2423 # C comment
2424 offEnd = sCode.find('*/', off + 2);
2425 if offEnd < 0:
2426 return sCode[:off].rstrip();
2427 sSep = ' ';
2428 if (off > 0 and sCode[off - 1].isspace()) or (offEnd + 2 < len(sCode) and sCode[offEnd + 2].isspace()):
2429 sSep = '';
2430 sCode = sCode[ : off] + sSep + sCode[offEnd + 2 : ];
2431 off += len(sSep);
2432
2433 else:
2434 # Not a comment.
2435 off += 1;
2436 return sCode;
2437
2438 @staticmethod
2439 def extractParam(sCode, offParam):
2440 """
2441 Extracts the parameter value at offParam in sCode.
2442 Returns stripped value and the end offset of the terminating ',' or ')'.
2443 """
2444 # Extract it.
2445 cNesting = 0;
2446 offStart = offParam;
2447 while offParam < len(sCode):
2448 ch = sCode[offParam];
2449 if ch == '(':
2450 cNesting += 1;
2451 elif ch == ')':
2452 if cNesting == 0:
2453 break;
2454 cNesting -= 1;
2455 elif ch == ',' and cNesting == 0:
2456 break;
2457 offParam += 1;
2458 return (sCode[offStart : offParam].strip(), offParam);
2459
2460 @staticmethod
2461 def extractParams(sCode, offOpenParen):
2462 """
2463 Parses a parameter list.
2464 Returns the list of parameter values and the offset of the closing parentheses.
2465 Returns (None, len(sCode)) on if no closing parentheses was found.
2466 """
2467 assert sCode[offOpenParen] == '(';
2468 asParams = [];
2469 off = offOpenParen + 1;
2470 while off < len(sCode):
2471 ch = sCode[off];
2472 if ch.isspace():
2473 off += 1;
2474 elif ch != ')':
2475 (sParam, off) = McBlock.extractParam(sCode, off);
2476 asParams.append(sParam);
2477 assert off < len(sCode), 'off=%s sCode=%s:"%s"' % (off, len(sCode), sCode,);
2478 if sCode[off] == ',':
2479 off += 1;
2480 else:
2481 return (asParams, off);
2482 return (None, off);
2483
2484 @staticmethod
2485 def findClosingBraces(sCode, off, offStop):
2486 """
2487 Finds the matching '}' for the '{' at off in sCode.
2488 Returns offset of the matching '}' on success, otherwise -1.
2489
2490 Note! Does not take comments into account.
2491 """
2492 cDepth = 1;
2493 off += 1;
2494 while off < offStop:
2495 offClose = sCode.find('}', off, offStop);
2496 if offClose < 0:
2497 break;
2498 cDepth += sCode.count('{', off, offClose);
2499 cDepth -= 1;
2500 if cDepth == 0:
2501 return offClose;
2502 off = offClose + 1;
2503 return -1;
2504
2505 @staticmethod
2506 def countSpacesAt(sCode, off, offStop):
2507 """ Returns the number of space characters at off in sCode. """
2508 offStart = off;
2509 while off < offStop and sCode[off].isspace():
2510 off += 1;
2511 return off - offStart;
2512
2513 @staticmethod
2514 def skipSpacesAt(sCode, off, offStop):
2515 """ Returns first offset at or after off for a non-space character. """
2516 return off + McBlock.countSpacesAt(sCode, off, offStop);
2517
2518 @staticmethod
2519 def isSubstrAt(sStr, off, sSubStr):
2520 """ Returns true of sSubStr is found at off in sStr. """
2521 return sStr[off : off + len(sSubStr)] == sSubStr;
2522
2523 koReCppCtrlStmts = re.compile(r'\b(if\s*[(]|else\b|while\s*[(]|for\s*[(]|do\b)');
2524 koReIemDecoderVars = re.compile( r'iem\.s\.(fPrefixes|uRexReg|uRexB|uRexIndex|iEffSeg|offModRm|cbOpcode|offOpcode'
2525 + r'|enmEffOpSize|enmDefOpSize|enmDefAddrMode|enmEffAddrMode|idxPrefix'
2526 + r'|uVex3rdReg|uVexLength|fEvxStuff|uFpuOpcode|abOpcode'
2527 + r')');
2528
2529 kaasConditions = (
2530 ( 'IEM_MC_IF_', 'IEM_MC_ELSE', 'IEM_MC_ENDIF' ),
2531 ( 'IEM_MC_NATIVE_IF', 'IEM_MC_NATIVE_ELSE', 'IEM_MC_NATIVE_ENDIF' ),
2532 );
2533 def decodeCode(self, sRawCode, off = 0, offStop = -1, iLevel = 0): # pylint: disable=too-many-statements,too-many-branches
2534 """
2535 Decodes sRawCode[off : offStop].
2536
2537 Returns list of McStmt instances.
2538 Raises ParserException on failure.
2539 """
2540 if offStop < 0:
2541 offStop = len(sRawCode);
2542 aoStmts = [];
2543 while off < offStop:
2544 ch = sRawCode[off];
2545
2546 #
2547 # Skip spaces and comments.
2548 #
2549 if ch.isspace():
2550 off += 1;
2551
2552 elif ch == '/':
2553 ch = sRawCode[off + 1];
2554 if ch == '/': # C++ comment.
2555 off = sRawCode.find('\n', off + 2);
2556 if off < 0:
2557 break;
2558 off += 1;
2559 elif ch == '*': # C comment.
2560 off = sRawCode.find('*/', off + 2);
2561 if off < 0:
2562 break;
2563 off += 2;
2564 else:
2565 self.raiseDecodeError(sRawCode, off, 'Unexpected "/"');
2566
2567 #
2568 # Is it a MC statement.
2569 #
2570 elif ch == 'I' and sRawCode[off : off + len('IEM_MC_')] == 'IEM_MC_':
2571 # All MC statements ends with a semicolon, except for conditionals which ends with a '{'.
2572 # Extract it and strip comments from it.
2573 if self.isSubstrAt(sRawCode, off, self.kaasConditions[0][0]): iCond = 0;
2574 elif self.isSubstrAt(sRawCode, off, self.kaasConditions[1][0]): iCond = 1;
2575 else: iCond = -1;
2576 if iCond < 0:
2577 offEnd = sRawCode.find(';', off + len('IEM_MC_'));
2578 if offEnd <= off:
2579 self.raiseDecodeError(sRawCode, off, 'MC statement without a ";"');
2580 else:
2581 offEnd = sRawCode.find('{', off + len(self.kaasConditions[iCond][0]));
2582 if offEnd <= off:
2583 self.raiseDecodeError(sRawCode, off, 'MC conditional statement without a "{"');
2584 if sRawCode.find(';', off + len(self.kaasConditions[iCond][0]), offEnd) > off:
2585 self.raiseDecodeError(sRawCode, off, 'MC conditional statement without an immediate "{"');
2586 offEnd -= 1;
2587 while offEnd > off and sRawCode[offEnd - 1].isspace():
2588 offEnd -= 1;
2589
2590 sRawStmt = self.stripComments(sRawCode[off : offEnd]);
2591
2592 # Isolate the statement name.
2593 offOpenParen = sRawStmt.find('(');
2594 if offOpenParen < 0:
2595 self.raiseDecodeError(sRawCode, off, 'MC statement without a "("');
2596 sName = sRawStmt[: offOpenParen].strip();
2597
2598 # Extract the parameters.
2599 (asParams, offCloseParen) = self.extractParams(sRawStmt, offOpenParen);
2600 if asParams is None:
2601 self.raiseDecodeError(sRawCode, off, 'MC statement without a closing parenthesis');
2602 if offCloseParen + 1 != len(sRawStmt):
2603 self.raiseDecodeError(sRawCode, off,
2604 'Unexpected code following MC statement: %s' % (sRawStmt[offCloseParen + 1:]));
2605
2606 # Hand it to the handler.
2607 fnParser = g_dMcStmtParsers.get(sName);
2608 if not fnParser:
2609 self.raiseDecodeError(sRawCode, off, 'Unknown MC statement: %s' % (sName,));
2610 fnParser = fnParser[0];
2611 oStmt = fnParser(self, sName, asParams);
2612 if not isinstance(oStmt, (list, tuple)):
2613 aoStmts.append(oStmt);
2614 else:
2615 aoStmts.extend(oStmt);
2616
2617 #
2618 # If conditional, we need to parse the whole statement.
2619 #
2620 # For reasons of simplicity, we assume the following structure
2621 # and parse each branch in a recursive call:
2622 # IEM_MC_IF_XXX() {
2623 # IEM_MC_WHATEVER();
2624 # } IEM_MC_ELSE() {
2625 # IEM_MC_WHATEVER();
2626 # } IEM_MC_ENDIF();
2627 #
2628 if iCond >= 0:
2629 if iLevel > 1: ## @todo discount IEM_MC_NATIVE_IF.
2630 self.raiseDecodeError(sRawCode, off, 'Too deep nesting of conditionals.');
2631
2632 # Find start of the IF block:
2633 offBlock1 = self.skipSpacesAt(sRawCode, offEnd, offStop);
2634 if sRawCode[offBlock1] != '{':
2635 self.raiseDecodeError(sRawCode, offBlock1, 'Expected "{" following %s' % (sName,));
2636
2637 # Find the end of it.
2638 offBlock1End = self.findClosingBraces(sRawCode, offBlock1, offStop);
2639 if offBlock1End < 0:
2640 self.raiseDecodeError(sRawCode, offBlock1, 'No matching "}" closing IF block of %s' % (sName,));
2641
2642 oStmt.aoIfBranch = self.decodeCode(sRawCode, offBlock1 + 1, offBlock1End, iLevel + 1);
2643
2644 # Is there an else section?
2645 off = self.skipSpacesAt(sRawCode, offBlock1End + 1, offStop);
2646 sElseNm = self.kaasConditions[iCond][1];
2647 if self.isSubstrAt(sRawCode, off, sElseNm):
2648 off = self.skipSpacesAt(sRawCode, off + len(sElseNm), offStop);
2649 if sRawCode[off] != '(':
2650 self.raiseDecodeError(sRawCode, off, 'Expected "(" following %s"' % (sElseNm,));
2651 off = self.skipSpacesAt(sRawCode, off + 1, offStop);
2652 if sRawCode[off] != ')':
2653 self.raiseDecodeError(sRawCode, off, 'Expected ")" following %s("' % (sElseNm,));
2654
2655 # Find start of the ELSE block.
2656 offBlock2 = self.skipSpacesAt(sRawCode, off + 1, offStop);
2657 if sRawCode[offBlock2] != '{':
2658 self.raiseDecodeError(sRawCode, offBlock2, 'Expected "{" following %s()"' % (sElseNm,));
2659
2660 # Find the end of it.
2661 offBlock2End = self.findClosingBraces(sRawCode, offBlock2, offStop);
2662 if offBlock2End < 0:
2663 self.raiseDecodeError(sRawCode, offBlock2, 'No matching "}" closing ELSE block of %s' % (sName,));
2664
2665 oStmt.aoElseBranch = self.decodeCode(sRawCode, offBlock2 + 1, offBlock2End, iLevel + 1);
2666 off = self.skipSpacesAt(sRawCode, offBlock2End + 1, offStop);
2667
2668 # Parse past the endif statement.
2669 sEndIfNm = self.kaasConditions[iCond][2];
2670 if not self.isSubstrAt(sRawCode, off, sEndIfNm):
2671 self.raiseDecodeError(sRawCode, off, 'Expected %s for closing %s' % (sEndIfNm, sName,));
2672 off = self.skipSpacesAt(sRawCode, off + len(sEndIfNm), offStop);
2673 if sRawCode[off] != '(':
2674 self.raiseDecodeError(sRawCode, off, 'Expected "(" following %s"' % (sEndIfNm,));
2675 off = self.skipSpacesAt(sRawCode, off + 1, offStop);
2676 if sRawCode[off] != ')':
2677 self.raiseDecodeError(sRawCode, off, 'Expected ")" following %s("' % (sEndIfNm,));
2678 off = self.skipSpacesAt(sRawCode, off + 1, offStop);
2679 if sRawCode[off] != ';':
2680 self.raiseDecodeError(sRawCode, off, 'Expected ";" following %s()"' % (sEndIfNm,));
2681 off += 1;
2682
2683 else:
2684 # Advance.
2685 off = offEnd + 1;
2686
2687 #
2688 # Otherwise it must be a C/C++ statement of sorts.
2689 #
2690 else:
2691 # Find the end of the statement. if and else requires special handling.
2692 sCondExpr = None;
2693 oMatch = self.koReCppCtrlStmts.match(sRawCode, off);
2694 if oMatch:
2695 if oMatch.group(1)[-1] == '(':
2696 (sCondExpr, offEnd) = self.extractParam(sRawCode, oMatch.end());
2697 else:
2698 offEnd = oMatch.end();
2699 if not oMatch.group(1).startswith('if') and oMatch.group(1) != 'else':
2700 self.raiseDecodeError(sRawCode, off, 'Only if/else control statements allowed: %s' % (oMatch.group(1),));
2701 elif ch == '#':
2702 offEnd = sRawCode.find('\n', off, offStop);
2703 if offEnd < 0:
2704 offEnd = offStop;
2705 offEnd -= 1;
2706 while offEnd > off and sRawCode[offEnd - 1].isspace():
2707 offEnd -= 1;
2708 else:
2709 offEnd = sRawCode.find(';', off);
2710 if offEnd < 0:
2711 self.raiseDecodeError(sRawCode, off, 'C++ statement without a ";"');
2712
2713 # Check this and the following statement whether it might have
2714 # something to do with decoding. This is a statement filter
2715 # criteria when generating the threaded functions blocks.
2716 offNextEnd = sRawCode.find(';', offEnd + 1);
2717 fDecode = ( sRawCode.find('IEM_OPCODE_', off, max(offEnd, offNextEnd)) >= 0
2718 or sRawCode.find('IEMOP_HLP_DONE_', off, max(offEnd, offNextEnd)) >= 0
2719 or sRawCode.find('IEMOP_HLP_DECODED_', off, offEnd) >= 0
2720 or sRawCode.find('IEMOP_HLP_RAISE_UD_IF_MISSING_GUEST_FEATURE', off, offEnd) >= 0
2721 or sRawCode.find('IEMOP_HLP_VMX_INSTR', off, offEnd) >= 0
2722 or sRawCode.find('IEMOP_HLP_IN_VMX_OPERATION', off, offEnd) >= 0 ## @todo wrong
2723 );
2724
2725 if not oMatch:
2726 if ch != '#':
2727 aoStmts.append(McCppGeneric(sRawCode[off : offEnd + 1], fDecode));
2728 else:
2729 aoStmts.append(McCppPreProc(sRawCode[off : offEnd + 1]));
2730 off = offEnd + 1;
2731 elif oMatch.group(1).startswith('if'):
2732 #
2733 # if () xxx [else yyy] statement.
2734 #
2735 oStmt = McCppCond(sCondExpr, fDecode);
2736 aoStmts.append(oStmt);
2737 off = offEnd + 1;
2738
2739 # Following the if () we can either have a {} containing zero or more statements
2740 # or we have a single statement.
2741 offBlock1 = self.skipSpacesAt(sRawCode, offEnd + 1, offStop);
2742 if sRawCode[offBlock1] == '{':
2743 offBlock1End = self.findClosingBraces(sRawCode, offBlock1, offStop);
2744 if offBlock1End < 0:
2745 self.raiseDecodeError(sRawCode, offBlock1, 'No matching "}" closing if block');
2746 offBlock1 += 1;
2747 else:
2748 offBlock1End = sRawCode.find(';', offBlock1, offStop);
2749 if offBlock1End < 0:
2750 self.raiseDecodeError(sRawCode, off, 'Expected ";" terminating one-line if block"');
2751
2752 oStmt.aoIfBranch = self.decodeCode(sRawCode, offBlock1, offBlock1End, iLevel + 1);
2753
2754 # The else is optional and can likewise be followed by {} or a single statement.
2755 off = self.skipSpacesAt(sRawCode, offBlock1End + 1, offStop);
2756 if self.isSubstrAt(sRawCode, off, 'else') and sRawCode[off + len('else')].isspace():
2757 offBlock2 = self.skipSpacesAt(sRawCode, off + len('else'), offStop);
2758 if sRawCode[offBlock2] == '{':
2759 offBlock2End = self.findClosingBraces(sRawCode, offBlock2, offStop);
2760 if offBlock2End < 0:
2761 self.raiseDecodeError(sRawCode, offBlock2, 'No matching "}" closing else block');
2762 offBlock2 += 1;
2763 else:
2764 offBlock2End = sRawCode.find(';', offBlock2, offStop);
2765 if offBlock2End < 0:
2766 self.raiseDecodeError(sRawCode, off, 'Expected ";" terminating one-line else block"');
2767
2768 oStmt.aoElseBranch = self.decodeCode(sRawCode, offBlock2, offBlock2End, iLevel + 1);
2769 off = offBlock2End + 1;
2770
2771 elif oMatch.group(1) == 'else':
2772 # Problematic 'else' branch, typically involving #ifdefs.
2773 self.raiseDecodeError(sRawCode, off, 'Mixed up else/#ifdef or something confusing us.');
2774
2775 return aoStmts;
2776
2777 def decode(self):
2778 """
2779 Decodes the block, populating self.aoStmts if necessary.
2780 Returns the statement list.
2781 Raises ParserException on failure.
2782 """
2783 if not self.aoStmts:
2784 self.aoStmts = self.decodeCode(''.join(self.asLines));
2785 return self.aoStmts;
2786
2787
2788 def checkForTooEarlyEffSegUse(self, aoStmts):
2789 """
2790 Checks if iEffSeg is used before the effective address has been decoded.
2791 Returns None on success, error string on failure.
2792
2793 See r158454 for an example of this issue.
2794 """
2795
2796 # Locate the IEM_MC_CALC_RM_EFF_ADDR statement, if found, scan backwards
2797 # for IEMCPU::iEffSeg references. No need to check conditional branches,
2798 # as we're ASSUMING these will not occur before address calculation.
2799 for iStmt, oStmt in enumerate(aoStmts):
2800 if oStmt.sName == 'IEM_MC_CALC_RM_EFF_ADDR':
2801 while iStmt > 0:
2802 iStmt -= 1;
2803 oStmt = aoStmts[iStmt];
2804 for sArg in oStmt.asParams:
2805 if sArg.find('pVCpu->iem.s.iEffSeg') >= 0:
2806 return "statement #%u: pVCpu->iem.s.iEffSeg is used prior to IEM_MC_CALC_RM_EFF_ADDR!" % (iStmt + 1,);
2807 break;
2808 return None;
2809
2810 koReCppFirstWord = re.compile(r'^\s*(\w+)[ (;]');
2811 kdDecodeCppStmtOkayAfterDone = {
2812 'IEMOP_HLP_IN_VMX_OPERATION': True,
2813 'IEMOP_HLP_VMX_INSTR': True,
2814 };
2815
2816 def checkForDoneDecoding(self, aoStmts):
2817 """
2818 Checks that the block contains a IEMOP_HLP_DONE_*DECODING* macro
2819 invocation.
2820 Returns None on success, error string on failure.
2821
2822 This ensures safe instruction restarting in case the recompiler runs
2823 out of TB resources during recompilation (e.g. aRanges or aGCPhysPages
2824 entries).
2825 """
2826
2827 # The IEMOP_HLP_DONE_ stuff is not allowed inside conditionals, so we
2828 # don't need to look.
2829 cIemOpHlpDone = 0;
2830 for iStmt, oStmt in enumerate(aoStmts):
2831 if oStmt.isCppStmt():
2832 #print('dbg: #%u[%u]: %s %s (%s)'
2833 # % (iStmt + 1, cIemOpHlpDone, oStmt.sName, 'd' if oStmt.fDecode else 'r', oStmt.asParams[0],));
2834
2835 oMatch = self.koReCppFirstWord.match(oStmt.asParams[0]);
2836 if oMatch:
2837 sFirstWord = oMatch.group(1);
2838 if ( sFirstWord.startswith('IEMOP_HLP_DONE_')
2839 or sFirstWord.startswith('IEMOP_HLP_DECODED_')):
2840 cIemOpHlpDone += 1;
2841 elif cIemOpHlpDone > 0 and oStmt.fDecode and sFirstWord not in self.kdDecodeCppStmtOkayAfterDone:
2842 return "statement #%u: Decoding statement following IEMOP_HLP_DONE_*DECODING*!" % (iStmt + 1,);
2843 #else: print('dbg: #%u[%u]: %s' % (iStmt + 1, cIemOpHlpDone, oStmt.asParams[0]));
2844 else:
2845 #print('dbg: #%u[%u]: %s' % (iStmt + 1, cIemOpHlpDone, oStmt.sName));
2846 if oStmt.sName.startswith('IEM_MC_DEFER_TO_CIMPL_') and iStmt == 0: # implicit
2847 cIemOpHlpDone += 1;
2848 elif cIemOpHlpDone == 0 and g_dMcStmtParsers.get(oStmt.sName, (None, False))[1]:
2849 return "statement #%u: State modifying MC statement before IEMOP_HLP_DONE_*DECODING*!" % (iStmt + 1,);
2850 elif cIemOpHlpDone > 0 and oStmt.sName in ('IEM_MC_CALC_RM_EFF_ADDR',):
2851 return "statement #%u: Decoding statement following IEMOP_HLP_DONE_*DECODING*!" % (iStmt + 1,);
2852 if cIemOpHlpDone == 1:
2853 return None;
2854 if cIemOpHlpDone > 1:
2855 return "Block has more than one IEMOP_HLP_DONE_*DECODING* invocation!";
2856 return "Block is missing IEMOP_HLP_DONE_*DECODING* invocation!";
2857
2858 def checkForFetchAfterRef(self, aoStmts, asRegRefClasses):
2859 """
2860 Checks that the register references are placed after register fetches
2861 from the same register class.
2862 Returns None on success, error string on failure.
2863
2864 Example:
2865 SHL CH, CL
2866
2867 If the CH reference is created first, the fetching of CL will cause the
2868 RCX guest register to have an active shadow register when it's being
2869 updated. The shadow register will then be stale after the SHL operation
2870 completes, without us noticing.
2871
2872 It's easier to ensure we've got correct code than complicating the
2873 recompiler code with safeguards here.
2874 """
2875 for iStmt, oStmt in enumerate(aoStmts):
2876 if not oStmt.isCppStmt():
2877 offRef = oStmt.sName.find("_REF_");
2878 if offRef > 0:
2879 if oStmt.sName in ('IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80',
2880 'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80',
2881 'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST',):
2882 sClass = 'FPUREG';
2883 else:
2884 offUnderscore = oStmt.sName.find('_', offRef + 5);
2885 if offUnderscore > 0:
2886 assert offUnderscore > offRef;
2887 sClass = oStmt.sName[offRef + 5 : offUnderscore];
2888 else:
2889 sClass = oStmt.sName[offRef + 5];
2890 asRegRefClasses[sClass] = True;
2891 else:
2892 offFetch = oStmt.sName.find("_FETCH_");
2893 if offFetch > 0:
2894 sClass = oStmt.sName[offFetch + 7 : ];
2895 if not sClass.startswith("MEM"):
2896 offUnderscore = sClass.find('_');
2897 if offUnderscore >= 0:
2898 assert offUnderscore > 0;
2899 sClass = sClass[:offUnderscore];
2900 if sClass in asRegRefClasses:
2901 return "statement #%u: %s following REF! That'll mess up guest register shadowing" \
2902 % (iStmt + 1, oStmt.sName,);
2903
2904 # Go into branches.
2905 if isinstance(oStmt, McStmtCond):
2906 sRet = self.checkForFetchAfterRef(oStmt.aoIfBranch, asRegRefClasses);
2907 if sRet:
2908 return sRet;
2909 sRet = self.checkForFetchAfterRef(oStmt.aoElseBranch, asRegRefClasses);
2910 if sRet:
2911 return sRet;
2912 return None;
2913
2914 def check(self):
2915 """
2916 Performs some sanity checks on the block.
2917 Returns error string list, empty if all is fine.
2918 """
2919 aoStmts = self.decode();
2920 asRet = [];
2921
2922 sRet = self.checkForTooEarlyEffSegUse(aoStmts);
2923 if sRet:
2924 asRet.append(sRet);
2925
2926 sRet = self.checkForDoneDecoding(aoStmts);
2927 if sRet:
2928 asRet.append(sRet);
2929
2930 sRet = self.checkForFetchAfterRef(aoStmts, {});
2931 if sRet:
2932 asRet.append(sRet);
2933
2934 return asRet;
2935
2936
2937## Temporary flag for enabling / disabling experimental MCs depending on the
2938## SIMD register allocator.
2939g_fNativeSimd = True;
2940
2941## IEM_MC_XXX -> parser + info dictionary.
2942#
2943# The info columns:
2944# - col 1+0: boolean entry indicating whether the statement modifies state and
2945# must not be used before IEMOP_HL_DONE_*.
2946# - col 1+1: boolean entry indicating similar to the previous column but is
2947# used to decide when to emit calls for conditional jumps (Jmp/NoJmp).
2948# The difference is that most IEM_MC_IF_XXX entries are False here.
2949# - col 1+2: boolean entry indicating native recompiler support.
2950#
2951# The raw table was generated via the following command
2952# sed -n -e "s/^# *define *\(IEM_MC_[A-Z_0-9]*\)[ (].*$/ '\1': McBlock.parseMcGeneric,/p" include/IEMMc.h \
2953# | sort | uniq | gawk "{printf """ %%-60s (%%s, True)\n""", $1, $2}"
2954# pylint: disable=line-too-long
2955g_dMcStmtParsers = {
2956 'IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE': (McBlock.parseMcGeneric, False, False, True, ),
2957 'IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ': (McBlock.parseMcGeneric, False, False, True, ),
2958 'IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE': (McBlock.parseMcGeneric, False, False, True, ),
2959 'IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ': (McBlock.parseMcGeneric, False, False, True, ),
2960 'IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE': (McBlock.parseMcGeneric, False, False, True, ),
2961 'IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ': (McBlock.parseMcGeneric, False, False, True, ),
2962 'IEM_MC_ADD_GREG_U16': (McBlock.parseMcGeneric, True, True, True, ),
2963 'IEM_MC_ADD_GREG_U16_TO_LOCAL': (McBlock.parseMcGeneric, False, False, False, ),
2964 'IEM_MC_ADD_GREG_U32': (McBlock.parseMcGeneric, True, True, True, ),
2965 'IEM_MC_ADD_GREG_U32_TO_LOCAL': (McBlock.parseMcGeneric, False, False, False, ),
2966 'IEM_MC_ADD_GREG_U64': (McBlock.parseMcGeneric, True, True, True, ),
2967 'IEM_MC_ADD_GREG_U64_TO_LOCAL': (McBlock.parseMcGeneric, False, False, False, ),
2968 'IEM_MC_ADD_GREG_U8_TO_LOCAL': (McBlock.parseMcGeneric, False, False, False, ),
2969 'IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR': (McBlock.parseMcGeneric, True, True, True, ),
2970 'IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR': (McBlock.parseMcGeneric, True, True, True, ),
2971 'IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR': (McBlock.parseMcGeneric, True, True, True, ),
2972 'IEM_MC_ADVANCE_RIP_AND_FINISH': (McBlock.parseMcGeneric, True, True, True, ),
2973 'IEM_MC_AND_2LOCS_U32': (McBlock.parseMcGeneric, False, False, False, ),
2974 'IEM_MC_AND_ARG_U16': (McBlock.parseMcGeneric, False, False, True, ),
2975 'IEM_MC_AND_ARG_U32': (McBlock.parseMcGeneric, False, False, True, ),
2976 'IEM_MC_AND_ARG_U64': (McBlock.parseMcGeneric, False, False, True, ),
2977 'IEM_MC_AND_GREG_U16': (McBlock.parseMcGeneric, True, True, True, ),
2978 'IEM_MC_AND_GREG_U32': (McBlock.parseMcGeneric, True, True, True, ),
2979 'IEM_MC_AND_GREG_U64': (McBlock.parseMcGeneric, True, True, True, ),
2980 'IEM_MC_AND_GREG_U8': (McBlock.parseMcGeneric, True, True, True, ),
2981 'IEM_MC_AND_LOCAL_U16': (McBlock.parseMcGeneric, False, False, True, ),
2982 'IEM_MC_AND_LOCAL_U32': (McBlock.parseMcGeneric, False, False, True, ),
2983 'IEM_MC_AND_LOCAL_U64': (McBlock.parseMcGeneric, False, False, True, ),
2984 'IEM_MC_AND_LOCAL_U8': (McBlock.parseMcGeneric, False, False, True, ),
2985 'IEM_MC_ARG': (McBlock.parseMcArg, False, False, True, ),
2986 'IEM_MC_ARG_CONST': (McBlock.parseMcArgConst, False, False, True, ),
2987 'IEM_MC_ARG_EFLAGS': (McBlock.parseMcArgEFlags, False, False, True, ),
2988 'IEM_MC_ARG_LOCAL_EFLAGS': (McBlock.parseMcArgLocalEFlags, False, False, True, ),
2989 'IEM_MC_ARG_LOCAL_REF': (McBlock.parseMcArgLocalRef, False, False, True, ),
2990 'IEM_MC_ASSIGN_TO_SMALLER': (McBlock.parseMcGeneric, False, False, True, ),
2991 'IEM_MC_BEGIN': (McBlock.parseMcBegin, False, False, True, ),
2992 'IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
2993 'IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
2994 'IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
2995 'IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
2996 'IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
2997 'IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
2998 'IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
2999 'IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3000 'IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3001 'IEM_MC_BSWAP_LOCAL_U16': (McBlock.parseMcGeneric, False, False, True, ),
3002 'IEM_MC_BSWAP_LOCAL_U32': (McBlock.parseMcGeneric, False, False, True, ),
3003 'IEM_MC_BSWAP_LOCAL_U64': (McBlock.parseMcGeneric, False, False, True, ),
3004 'IEM_MC_CALC_RM_EFF_ADDR': (McBlock.parseMcGeneric, False, False, False, ),
3005 'IEM_MC_CALL_AIMPL_3': (McBlock.parseMcCallAImpl, True, True, True, ),
3006 'IEM_MC_CALL_AIMPL_4': (McBlock.parseMcCallAImpl, True, True, True, ),
3007 'IEM_MC_CALL_AVX_AIMPL_2': (McBlock.parseMcCallAvxAImpl, True, True, g_fNativeSimd),
3008 'IEM_MC_CALL_AVX_AIMPL_3': (McBlock.parseMcCallAvxAImpl, True, True, g_fNativeSimd),
3009 'IEM_MC_CALL_CIMPL_0': (McBlock.parseMcCallCImpl, True, True, False, ),
3010 'IEM_MC_CALL_CIMPL_1': (McBlock.parseMcCallCImpl, True, True, False, ),
3011 'IEM_MC_CALL_CIMPL_2': (McBlock.parseMcCallCImpl, True, True, False, ),
3012 'IEM_MC_CALL_CIMPL_3': (McBlock.parseMcCallCImpl, True, True, False, ),
3013 'IEM_MC_CALL_CIMPL_4': (McBlock.parseMcCallCImpl, True, True, False, ),
3014 'IEM_MC_CALL_CIMPL_5': (McBlock.parseMcCallCImpl, True, True, False, ),
3015 'IEM_MC_CALL_FPU_AIMPL_1': (McBlock.parseMcCallFpuAImpl, True, True, False, ),
3016 'IEM_MC_CALL_FPU_AIMPL_2': (McBlock.parseMcCallFpuAImpl, True, True, False, ),
3017 'IEM_MC_CALL_FPU_AIMPL_3': (McBlock.parseMcCallFpuAImpl, True, True, False, ),
3018 'IEM_MC_CALL_MMX_AIMPL_2': (McBlock.parseMcCallMmxAImpl, True, True, False, ),
3019 'IEM_MC_CALL_MMX_AIMPL_3': (McBlock.parseMcCallMmxAImpl, True, True, False, ),
3020 'IEM_MC_CALL_SSE_AIMPL_2': (McBlock.parseMcCallSseAImpl, True, True, g_fNativeSimd),
3021 'IEM_MC_CALL_SSE_AIMPL_3': (McBlock.parseMcCallSseAImpl, True, True, g_fNativeSimd),
3022 'IEM_MC_CALL_VOID_AIMPL_0': (McBlock.parseMcCallVoidAImpl, True, True, True, ),
3023 'IEM_MC_CALL_VOID_AIMPL_1': (McBlock.parseMcCallVoidAImpl, True, True, True, ),
3024 'IEM_MC_CALL_VOID_AIMPL_2': (McBlock.parseMcCallVoidAImpl, True, True, True, ),
3025 'IEM_MC_CALL_VOID_AIMPL_3': (McBlock.parseMcCallVoidAImpl, True, True, True, ),
3026 'IEM_MC_CALL_VOID_AIMPL_4': (McBlock.parseMcCallVoidAImpl, True, True, True, ),
3027 'IEM_MC_CLEAR_EFL_BIT': (McBlock.parseMcGeneric, True, True, True, ),
3028 'IEM_MC_CLEAR_FSW_EX': (McBlock.parseMcGeneric, True, True, False, ),
3029 'IEM_MC_CLEAR_HIGH_GREG_U64': (McBlock.parseMcGeneric, True, True, True, ),
3030 'IEM_MC_CLEAR_XREG_U32_MASK': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3031 'IEM_MC_CLEAR_YREG_128_UP': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3032 'IEM_MC_CLEAR_ZREG_256_UP': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3033 'IEM_MC_COMMIT_EFLAGS': (McBlock.parseMcGeneric, True, True, True, ),
3034 'IEM_MC_COMMIT_EFLAGS_OPT': (McBlock.parseMcGeneric, True, True, True, ),
3035 'IEM_MC_COPY_XREG_U128': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3036 'IEM_MC_COPY_YREG_U128_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3037 'IEM_MC_COPY_YREG_U256_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3038 'IEM_MC_COPY_YREG_U64_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, False, ),
3039 'IEM_MC_DEFER_TO_CIMPL_0_RET': (McBlock.parseMcDeferToCImpl, False, False, False, ),
3040 'IEM_MC_DEFER_TO_CIMPL_1_RET': (McBlock.parseMcDeferToCImpl, False, False, False, ),
3041 'IEM_MC_DEFER_TO_CIMPL_2_RET': (McBlock.parseMcDeferToCImpl, False, False, False, ),
3042 'IEM_MC_DEFER_TO_CIMPL_3_RET': (McBlock.parseMcDeferToCImpl, False, False, False, ),
3043 'IEM_MC_END': (McBlock.parseMcGeneric, True, True, True, ),
3044 'IEM_MC_FETCH_EFLAGS': (McBlock.parseMcGeneric, False, False, True, ),
3045 'IEM_MC_FETCH_EFLAGS_U8': (McBlock.parseMcGeneric, False, False, False, ),
3046 'IEM_MC_FETCH_FCW': (McBlock.parseMcGeneric, False, False, True, ),
3047 'IEM_MC_FETCH_FSW': (McBlock.parseMcGeneric, False, False, True, ),
3048 'IEM_MC_FETCH_GREG_U16': (McBlock.parseMcGeneric, False, False, True, ),
3049 'IEM_MC_FETCH_GREG_U16_SX_U32': (McBlock.parseMcGeneric, False, False, True, ),
3050 'IEM_MC_FETCH_GREG_U16_SX_U64': (McBlock.parseMcGeneric, False, False, True, ),
3051 'IEM_MC_FETCH_GREG_U16_ZX_U32': (McBlock.parseMcGeneric, False, False, True, ),
3052 'IEM_MC_FETCH_GREG_U16_ZX_U64': (McBlock.parseMcGeneric, False, False, True, ),
3053 'IEM_MC_FETCH_GREG_U32': (McBlock.parseMcGeneric, False, False, True, ),
3054 'IEM_MC_FETCH_GREG_U32_SX_U64': (McBlock.parseMcGeneric, False, False, True, ),
3055 'IEM_MC_FETCH_GREG_U32_ZX_U64': (McBlock.parseMcGeneric, False, False, True, ),
3056 'IEM_MC_FETCH_GREG_U64': (McBlock.parseMcGeneric, False, False, True, ),
3057 'IEM_MC_FETCH_GREG_U64_ZX_U64': (McBlock.parseMcGeneric, False, False, True, ),
3058 'IEM_MC_FETCH_GREG_U8': (McBlock.parseMcGeneric, False, False, True, ), # thrd var
3059 'IEM_MC_FETCH_GREG_U8_SX_U16': (McBlock.parseMcGeneric, False, False, True, ), # thrd var
3060 'IEM_MC_FETCH_GREG_U8_SX_U32': (McBlock.parseMcGeneric, False, False, True, ), # thrd var
3061 'IEM_MC_FETCH_GREG_U8_SX_U64': (McBlock.parseMcGeneric, False, False, True, ), # thrd var
3062 'IEM_MC_FETCH_GREG_U8_ZX_U16': (McBlock.parseMcGeneric, False, False, True, ), # thrd var
3063 'IEM_MC_FETCH_GREG_U8_ZX_U32': (McBlock.parseMcGeneric, False, False, True, ), # thrd var
3064 'IEM_MC_FETCH_GREG_U8_ZX_U64': (McBlock.parseMcGeneric, False, False, True, ), # thrd var
3065 'IEM_MC_FETCH_GREG_PAIR_U32': (McBlock.parseMcGeneric, False, False, False, ),
3066 'IEM_MC_FETCH_GREG_PAIR_U64': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3067 'IEM_MC_FETCH_MEM_D80': (McBlock.parseMcGeneric, True, True, False, ),
3068 'IEM_MC_FETCH_MEM_I16': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3069 'IEM_MC_FETCH_MEM_I32': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3070 'IEM_MC_FETCH_MEM_I64': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3071 'IEM_MC_FETCH_MEM_R32': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3072 'IEM_MC_FETCH_MEM_R64': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3073 'IEM_MC_FETCH_MEM_R80': (McBlock.parseMcGeneric, True, True, False, ),
3074 'IEM_MC_FETCH_MEM_U128': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3075 'IEM_MC_FETCH_MEM_U128_ALIGN_SSE': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3076 'IEM_MC_FETCH_MEM_U128_NO_AC': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3077 'IEM_MC_FETCH_MEM_U128_AND_XREG_U128': (McBlock.parseMcGeneric, True, True, False, ),
3078 'IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_RAX_RDX_U64': (McBlock.parseMcGeneric, True, True, False, ),
3079 'IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64':(McBlock.parseMcGeneric, True, True, False, ),
3080 'IEM_MC_FETCH_MEM_U16': (McBlock.parseMcGeneric, True, True, True, ),
3081 'IEM_MC_FETCH_MEM_U16_DISP': (McBlock.parseMcGeneric, True, True, True, ),
3082 'IEM_MC_FETCH_MEM_U16_SX_U32': (McBlock.parseMcGeneric, True, True, True, ), # movsx
3083 'IEM_MC_FETCH_MEM_U16_SX_U64': (McBlock.parseMcGeneric, True, True, True, ), # movsx
3084 'IEM_MC_FETCH_MEM_U16_ZX_U32': (McBlock.parseMcGeneric, True, True, True, ), # movzx
3085 'IEM_MC_FETCH_MEM_U16_ZX_U64': (McBlock.parseMcGeneric, True, True, True, ), # movzx
3086 'IEM_MC_FETCH_MEM_U256': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3087 'IEM_MC_FETCH_MEM_U256_ALIGN_AVX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3088 'IEM_MC_FETCH_MEM_U256_NO_AC': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3089 'IEM_MC_FETCH_MEM_U32': (McBlock.parseMcGeneric, True, True, True, ),
3090 'IEM_MC_FETCH_MEM_U32_DISP': (McBlock.parseMcGeneric, True, True, True, ), #bounds only
3091 'IEM_MC_FETCH_MEM_U32_SX_U64': (McBlock.parseMcGeneric, True, True, True, ), # movsx
3092 'IEM_MC_FETCH_MEM_U32_ZX_U64': (McBlock.parseMcGeneric, True, True, True, ), # movzx
3093 'IEM_MC_FETCH_MEM_U64': (McBlock.parseMcGeneric, True, True, True, ),
3094 'IEM_MC_FETCH_MEM_U64_ALIGN_U128': (McBlock.parseMcGeneric, True, True, False, ),
3095 'IEM_MC_FETCH_MEM_U8': (McBlock.parseMcGeneric, True, True, True, ),
3096 'IEM_MC_FETCH_MEM_U8_SX_U16': (McBlock.parseMcGeneric, True, True, True, ), # movsx
3097 'IEM_MC_FETCH_MEM_U8_SX_U32': (McBlock.parseMcGeneric, True, True, True, ), # movsx
3098 'IEM_MC_FETCH_MEM_U8_SX_U64': (McBlock.parseMcGeneric, True, True, True, ), # movsx
3099 'IEM_MC_FETCH_MEM_U8_ZX_U16': (McBlock.parseMcGeneric, True, True, True, ), # movzx
3100 'IEM_MC_FETCH_MEM_U8_ZX_U32': (McBlock.parseMcGeneric, True, True, True, ), # movzx
3101 'IEM_MC_FETCH_MEM_U8_ZX_U64': (McBlock.parseMcGeneric, True, True, True, ), # movzx
3102 'IEM_MC_FETCH_MEM_XMM': (McBlock.parseMcGeneric, True, True, False, ),
3103 'IEM_MC_FETCH_MEM_XMM_ALIGN_SSE': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3104 'IEM_MC_FETCH_MEM_XMM_NO_AC': (McBlock.parseMcGeneric, True, True, False, ),
3105 'IEM_MC_FETCH_MEM_XMM_ALIGN_SSE_AND_XREG_XMM': (McBlock.parseMcGeneric, True, True, False, ),
3106 'IEM_MC_FETCH_MEM_XMM_U32_AND_XREG_XMM': (McBlock.parseMcGeneric, True, True, False, ),
3107 'IEM_MC_FETCH_MEM_XMM_U64_AND_XREG_XMM': (McBlock.parseMcGeneric, True, True, False, ),
3108 'IEM_MC_FETCH_MEM_YMM': (McBlock.parseMcGeneric, True, True, False, ),
3109 'IEM_MC_FETCH_MEM_YMM_ALIGN_AVX': (McBlock.parseMcGeneric, True, True, False, ),
3110 'IEM_MC_FETCH_MEM_YMM_NO_AC': (McBlock.parseMcGeneric, True, True, False, ),
3111 'IEM_MC_FETCH_MEM16_U8': (McBlock.parseMcGeneric, True, True, False, ),
3112 'IEM_MC_FETCH_MEM32_U8': (McBlock.parseMcGeneric, True, True, False, ),
3113 'IEM_MC_FETCH_MREG_U8': (McBlock.parseMcGeneric, False, False, False, ),
3114 'IEM_MC_FETCH_MREG_U16': (McBlock.parseMcGeneric, False, False, False, ),
3115 'IEM_MC_FETCH_MREG_U32': (McBlock.parseMcGeneric, False, False, False, ),
3116 'IEM_MC_FETCH_MREG_U64': (McBlock.parseMcGeneric, False, False, False, ),
3117 'IEM_MC_FETCH_SREG_BASE_U32': (McBlock.parseMcGeneric, False, False, False, ),
3118 'IEM_MC_FETCH_SREG_BASE_U64': (McBlock.parseMcGeneric, False, False, False, ),
3119 'IEM_MC_FETCH_SREG_U16': (McBlock.parseMcGeneric, False, False, True, ),
3120 'IEM_MC_FETCH_SREG_ZX_U32': (McBlock.parseMcGeneric, False, False, True, ),
3121 'IEM_MC_FETCH_SREG_ZX_U64': (McBlock.parseMcGeneric, False, False, True, ),
3122 'IEM_MC_FETCH_XREG_R32': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3123 'IEM_MC_FETCH_XREG_R64': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3124 'IEM_MC_FETCH_XREG_U128': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3125 'IEM_MC_FETCH_XREG_U16': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3126 'IEM_MC_FETCH_XREG_U32': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3127 'IEM_MC_FETCH_XREG_U64': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3128 'IEM_MC_FETCH_XREG_U8': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3129 'IEM_MC_FETCH_XREG_XMM': (McBlock.parseMcGeneric, False, False, False, ),
3130 'IEM_MC_FETCH_XREG_PAIR_U128': (McBlock.parseMcGeneric, False, False, False, ),
3131 'IEM_MC_FETCH_XREG_PAIR_U128_AND_RAX_RDX_U64': (McBlock.parseMcGeneric, False, False, False, ),
3132 'IEM_MC_FETCH_XREG_PAIR_U128_AND_EAX_EDX_U32_SX_U64': (McBlock.parseMcGeneric, False, False, False, ),
3133 'IEM_MC_FETCH_XREG_PAIR_XMM': (McBlock.parseMcGeneric, False, False, False, ),
3134 'IEM_MC_FETCH_YREG_U128': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3135 'IEM_MC_FETCH_YREG_U256': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3136 'IEM_MC_FETCH_YREG_U32': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3137 'IEM_MC_FETCH_YREG_U64': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3138 'IEM_MC_FLIP_EFL_BIT': (McBlock.parseMcGeneric, True, True, True, ),
3139 'IEM_MC_FPU_FROM_MMX_MODE': (McBlock.parseMcGeneric, True, True, False, ),
3140 'IEM_MC_FPU_STACK_DEC_TOP': (McBlock.parseMcGeneric, True, True, False, ),
3141 'IEM_MC_FPU_STACK_FREE': (McBlock.parseMcGeneric, True, True, False, ),
3142 'IEM_MC_FPU_STACK_INC_TOP': (McBlock.parseMcGeneric, True, True, False, ),
3143 'IEM_MC_FPU_STACK_PUSH_OVERFLOW': (McBlock.parseMcGeneric, True, True, False, ),
3144 'IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP': (McBlock.parseMcGeneric, True, True, False, ),
3145 'IEM_MC_FPU_STACK_PUSH_UNDERFLOW': (McBlock.parseMcGeneric, True, True, False, ),
3146 'IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO': (McBlock.parseMcGeneric, True, True, False, ),
3147 'IEM_MC_FPU_STACK_UNDERFLOW': (McBlock.parseMcGeneric, True, True, False, ),
3148 'IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP': (McBlock.parseMcGeneric, True, True, False, ),
3149 'IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP': (McBlock.parseMcGeneric, True, True, False, ),
3150 'IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP': (McBlock.parseMcGeneric, True, True, False, ),
3151 'IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP': (McBlock.parseMcGeneric, True, True, False, ),
3152 'IEM_MC_FPU_TO_MMX_MODE': (McBlock.parseMcGeneric, True, True, False, ),
3153 'IEM_MC_HINT_FLUSH_GUEST_SHADOW': (McBlock.parseMcGeneric, True, True, True, ),
3154 'IEM_MC_IF_CX_IS_NZ': (McBlock.parseMcGenericCond, True, False, True, ),
3155 'IEM_MC_IF_CX_IS_NOT_ONE': (McBlock.parseMcGenericCond, True, False, True, ),
3156 'IEM_MC_IF_CX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3157 'IEM_MC_IF_CX_IS_NOT_ONE_AND_EFL_BIT_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3158 'IEM_MC_IF_ECX_IS_NZ': (McBlock.parseMcGenericCond, True, False, True, ),
3159 'IEM_MC_IF_ECX_IS_NOT_ONE': (McBlock.parseMcGenericCond, True, False, True, ),
3160 'IEM_MC_IF_ECX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3161 'IEM_MC_IF_ECX_IS_NOT_ONE_AND_EFL_BIT_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3162 'IEM_MC_IF_EFL_ANY_BITS_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3163 'IEM_MC_IF_EFL_BIT_NOT_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3164 'IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ': (McBlock.parseMcGenericCond, True, False, True, ),
3165 'IEM_MC_IF_EFL_BIT_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3166 'IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE': (McBlock.parseMcGenericCond, True, False, True, ),
3167 'IEM_MC_IF_EFL_BITS_EQ': (McBlock.parseMcGenericCond, True, False, True, ),
3168 'IEM_MC_IF_EFL_BITS_NE': (McBlock.parseMcGenericCond, True, False, True, ),
3169 'IEM_MC_IF_EFL_NO_BITS_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3170 'IEM_MC_IF_FCW_IM': (McBlock.parseMcGenericCond, True, True, False, ),
3171 'IEM_MC_IF_FPUREG_IS_EMPTY': (McBlock.parseMcGenericCond, True, True, False, ),
3172 'IEM_MC_IF_FPUREG_NOT_EMPTY': (McBlock.parseMcGenericCond, True, True, False, ),
3173 'IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80': (McBlock.parseMcGenericCond, True, True, False, ),
3174 'IEM_MC_IF_GREG_BIT_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3175 'IEM_MC_IF_LOCAL_IS_Z': (McBlock.parseMcGenericCond, True, False, True, ),
3176 'IEM_MC_IF_RCX_IS_NZ': (McBlock.parseMcGenericCond, True, False, True, ),
3177 'IEM_MC_IF_RCX_IS_NOT_ONE': (McBlock.parseMcGenericCond, True, False, True, ),
3178 'IEM_MC_IF_RCX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3179 'IEM_MC_IF_RCX_IS_NOT_ONE_AND_EFL_BIT_SET': (McBlock.parseMcGenericCond, True, False, True, ),
3180 'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80': (McBlock.parseMcGenericCond, True, True, False, ),
3181 'IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST': (McBlock.parseMcGenericCond, True, True, False, ),
3182 'IEM_MC_IND_CALL_U16_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3183 'IEM_MC_IND_CALL_U32_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3184 'IEM_MC_IND_CALL_U64_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3185 'IEM_MC_INT_CLEAR_ZMM_256_UP': (McBlock.parseMcGeneric, True, True, False, ),
3186 'IEM_MC_LOCAL': (McBlock.parseMcLocal, False, False, True, ),
3187 'IEM_MC_LOCAL_ASSIGN': (McBlock.parseMcLocalAssign, False, False, True, ),
3188 'IEM_MC_LOCAL_CONST': (McBlock.parseMcLocalConst, False, False, True, ),
3189 'IEM_MC_LOCAL_EFLAGS': (McBlock.parseMcLocalEFlags, True, True, True, ),
3190 'IEM_MC_NOREF': (McBlock.parseMcGeneric, False, False, True, ),
3191 'IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT': (McBlock.parseMcGeneric, True, True, True, ),
3192 'IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE': (McBlock.parseMcGeneric, True, True, True, ),
3193 'IEM_MC_MAYBE_RAISE_FPU_XCPT': (McBlock.parseMcGeneric, True, True, True, ),
3194 'IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT': (McBlock.parseMcGeneric, True, True, False, ),
3195 'IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT': (McBlock.parseMcGeneric, True, True, False, ),
3196 'IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0': (McBlock.parseMcGeneric, True, True, False, ),
3197 'IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3198 'IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT': (McBlock.parseMcGeneric, True, True, True, ),
3199 'IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE': (McBlock.parseMcGeneric, True, True, True, ),
3200 'IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC': (McBlock.parseMcGeneric, True, True, True, ),
3201 'IEM_MC_MEM_COMMIT_AND_UNMAP_RW': (McBlock.parseMcGeneric, True, True, True, ),
3202 'IEM_MC_MEM_COMMIT_AND_UNMAP_RO': (McBlock.parseMcGeneric, True, True, True, ),
3203 'IEM_MC_MEM_COMMIT_AND_UNMAP_WO': (McBlock.parseMcGeneric, True, True, True, ),
3204 'IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE_WO': (McBlock.parseMcGeneric, True, True, False, ),
3205 'IEM_MC_MEM_MAP_D80_WO': (McBlock.parseMcGeneric, True, True, True, ),
3206 'IEM_MC_MEM_MAP_I16_WO': (McBlock.parseMcGeneric, True, True, True, ),
3207 'IEM_MC_MEM_MAP_I32_WO': (McBlock.parseMcGeneric, True, True, True, ),
3208 'IEM_MC_MEM_MAP_I64_WO': (McBlock.parseMcGeneric, True, True, True, ),
3209 'IEM_MC_MEM_MAP_R32_WO': (McBlock.parseMcGeneric, True, True, True, ),
3210 'IEM_MC_MEM_MAP_R64_WO': (McBlock.parseMcGeneric, True, True, True, ),
3211 'IEM_MC_MEM_MAP_R80_WO': (McBlock.parseMcGeneric, True, True, True, ),
3212 'IEM_MC_MEM_MAP_U8_ATOMIC': (McBlock.parseMcGeneric, True, True, True, ),
3213 'IEM_MC_MEM_MAP_U8_RW': (McBlock.parseMcGeneric, True, True, True, ),
3214 'IEM_MC_MEM_MAP_U8_RO': (McBlock.parseMcGeneric, True, True, True, ),
3215 'IEM_MC_MEM_MAP_U8_WO': (McBlock.parseMcGeneric, True, True, True, ),
3216 'IEM_MC_MEM_MAP_U16_ATOMIC': (McBlock.parseMcGeneric, True, True, True, ),
3217 'IEM_MC_MEM_MAP_U16_RW': (McBlock.parseMcGeneric, True, True, True, ),
3218 'IEM_MC_MEM_MAP_U16_RO': (McBlock.parseMcGeneric, True, True, True, ),
3219 'IEM_MC_MEM_MAP_U16_WO': (McBlock.parseMcGeneric, True, True, True, ),
3220 'IEM_MC_MEM_MAP_U32_ATOMIC': (McBlock.parseMcGeneric, True, True, True, ),
3221 'IEM_MC_MEM_MAP_U32_RW': (McBlock.parseMcGeneric, True, True, True, ),
3222 'IEM_MC_MEM_MAP_U32_RO': (McBlock.parseMcGeneric, True, True, True, ),
3223 'IEM_MC_MEM_MAP_U32_WO': (McBlock.parseMcGeneric, True, True, True, ),
3224 'IEM_MC_MEM_MAP_U64_ATOMIC': (McBlock.parseMcGeneric, True, True, True, ),
3225 'IEM_MC_MEM_MAP_U64_RW': (McBlock.parseMcGeneric, True, True, True, ),
3226 'IEM_MC_MEM_MAP_U64_RO': (McBlock.parseMcGeneric, True, True, True, ),
3227 'IEM_MC_MEM_MAP_U64_WO': (McBlock.parseMcGeneric, True, True, True, ),
3228 'IEM_MC_MEM_MAP_U128_ATOMIC': (McBlock.parseMcGeneric, True, True, True, ),
3229 'IEM_MC_MEM_MAP_U128_RW': (McBlock.parseMcGeneric, True, True, True, ),
3230 'IEM_MC_MEM_MAP_U128_RO': (McBlock.parseMcGeneric, True, True, True, ),
3231 'IEM_MC_MEM_MAP_U128_WO': (McBlock.parseMcGeneric, True, True, True, ),
3232 'IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO': (McBlock.parseMcGeneric, True, True, True, ),
3233 'IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, False, ),
3234 'IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, False, ),
3235 'IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, False, ),
3236 'IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, False, ),
3237 'IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3238 'IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3239 'IEM_MC_MODIFIED_MREG': (McBlock.parseMcGeneric, True, True, False, ),
3240 'IEM_MC_MODIFIED_MREG_BY_REF': (McBlock.parseMcGeneric, True, True, False, ),
3241 'IEM_MC_NATIVE_EMIT_0': (McBlock.parseMcGeneric, True, True, True, ),
3242 'IEM_MC_NATIVE_EMIT_1': (McBlock.parseMcGeneric, True, True, True, ),
3243 'IEM_MC_NATIVE_EMIT_2': (McBlock.parseMcGeneric, True, True, True, ),
3244 'IEM_MC_NATIVE_EMIT_3': (McBlock.parseMcGeneric, True, True, True, ),
3245 'IEM_MC_NATIVE_EMIT_4': (McBlock.parseMcGeneric, True, True, True, ),
3246 'IEM_MC_NATIVE_EMIT_5': (McBlock.parseMcGeneric, True, True, True, ),
3247 'IEM_MC_NATIVE_EMIT_6': (McBlock.parseMcGeneric, True, True, True, ),
3248 'IEM_MC_NATIVE_EMIT_7': (McBlock.parseMcGeneric, True, True, True, ),
3249 'IEM_MC_NATIVE_IF': (McBlock.parseMcNativeIf, False, False, True, ),
3250 'IEM_MC_NATIVE_ELSE': (McBlock.parseMcGenericCond, False, False, True, ),
3251 'IEM_MC_NATIVE_ENDIF': (McBlock.parseMcGenericCond, False, False, True, ),
3252 'IEM_MC_NATIVE_SET_AMD64_HOST_REG_FOR_LOCAL': (McBlock.parseMcGeneric, False, False, True, ),
3253 'IEM_MC_OR_2LOCS_U32': (McBlock.parseMcGeneric, False, False, False, ),
3254 'IEM_MC_OR_GREG_U16': (McBlock.parseMcGeneric, True, True, True, ),
3255 'IEM_MC_OR_GREG_U32': (McBlock.parseMcGeneric, True, True, True, ),
3256 'IEM_MC_OR_GREG_U64': (McBlock.parseMcGeneric, True, True, True, ),
3257 'IEM_MC_OR_GREG_U8': (McBlock.parseMcGeneric, True, True, True, ),
3258 'IEM_MC_OR_LOCAL_U16': (McBlock.parseMcGeneric, False, False, True, ),
3259 'IEM_MC_OR_LOCAL_U32': (McBlock.parseMcGeneric, False, False, True, ),
3260 'IEM_MC_OR_LOCAL_U8': (McBlock.parseMcGeneric, False, False, True, ),
3261 'IEM_MC_POP_GREG_U16': (McBlock.parseMcGeneric, True, True, True, ),
3262 'IEM_MC_POP_GREG_U32': (McBlock.parseMcGeneric, True, True, True, ),
3263 'IEM_MC_POP_GREG_U64': (McBlock.parseMcGeneric, True, True, True, ),
3264 'IEM_MC_PREPARE_AVX_USAGE': (McBlock.parseMcGeneric, False, False, True),
3265 'IEM_MC_PREPARE_FPU_USAGE': (McBlock.parseMcGeneric, False, False, True),
3266 'IEM_MC_PREPARE_SSE_USAGE': (McBlock.parseMcGeneric, False, False, True),
3267 'IEM_MC_PUSH_FPU_RESULT': (McBlock.parseMcGeneric, True, True, False, ),
3268 'IEM_MC_PUSH_FPU_RESULT_MEM_OP': (McBlock.parseMcGeneric, True, True, False, ),
3269 'IEM_MC_PUSH_FPU_RESULT_TWO': (McBlock.parseMcGeneric, True, True, False, ),
3270 'IEM_MC_PUSH_U16': (McBlock.parseMcGeneric, True, True, True, ),
3271 'IEM_MC_PUSH_U32': (McBlock.parseMcGeneric, True, True, True, ),
3272 'IEM_MC_PUSH_U32_SREG': (McBlock.parseMcGeneric, True, True, True, ),
3273 'IEM_MC_PUSH_U64': (McBlock.parseMcGeneric, True, True, True, ),
3274 'IEM_MC_RAISE_DIVIDE_ERROR': (McBlock.parseMcGeneric, True, True, True, ),
3275 'IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO': (McBlock.parseMcGeneric, True, True, False, ),
3276 'IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED': (McBlock.parseMcGeneric, True, True, True, ),
3277 'IEM_MC_REF_EFLAGS': (McBlock.parseMcGeneric, False, False, True, ),
3278 'IEM_MC_REF_FPUREG': (McBlock.parseMcGeneric, False, False, False, ),
3279 'IEM_MC_REF_GREG_I32': (McBlock.parseMcGeneric, False, False, True, ),
3280 'IEM_MC_REF_GREG_I32_CONST': (McBlock.parseMcGeneric, False, False, True, ),
3281 'IEM_MC_REF_GREG_I64': (McBlock.parseMcGeneric, False, False, True, ),
3282 'IEM_MC_REF_GREG_I64_CONST': (McBlock.parseMcGeneric, False, False, True, ),
3283 'IEM_MC_REF_GREG_U16': (McBlock.parseMcGeneric, False, False, True, ),
3284 'IEM_MC_REF_GREG_U16_CONST': (McBlock.parseMcGeneric, False, False, True, ),
3285 'IEM_MC_REF_GREG_U32': (McBlock.parseMcGeneric, False, False, True, ),
3286 'IEM_MC_REF_GREG_U32_CONST': (McBlock.parseMcGeneric, False, False, True, ),
3287 'IEM_MC_REF_GREG_U64': (McBlock.parseMcGeneric, False, False, True, ),
3288 'IEM_MC_REF_GREG_U64_CONST': (McBlock.parseMcGeneric, False, False, True, ),
3289 'IEM_MC_REF_GREG_U8': (McBlock.parseMcGeneric, False, False, False, ), # threaded
3290 'IEM_MC_REF_GREG_U8_CONST': (McBlock.parseMcGeneric, False, False, False, ), # threaded
3291 'IEM_MC_REF_MREG_U32_CONST': (McBlock.parseMcGeneric, False, False, False, ),
3292 'IEM_MC_REF_MREG_U64': (McBlock.parseMcGeneric, False, False, False, ),
3293 'IEM_MC_REF_MREG_U64_CONST': (McBlock.parseMcGeneric, False, False, False, ),
3294 'IEM_MC_REF_XREG_R32_CONST': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3295 'IEM_MC_REF_XREG_R64_CONST': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3296 'IEM_MC_REF_XREG_U128': (McBlock.parseMcGeneric, False, False, True, ),
3297 'IEM_MC_REF_XREG_U128_CONST': (McBlock.parseMcGeneric, False, False, True, ),
3298 'IEM_MC_REF_XREG_U32_CONST': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3299 'IEM_MC_REF_XREG_U64_CONST': (McBlock.parseMcGeneric, False, False, g_fNativeSimd),
3300 'IEM_MC_REF_XREG_XMM_CONST': (McBlock.parseMcGeneric, False, False, True, ),
3301 'IEM_MC_REF_YREG_U128': (McBlock.parseMcGeneric, False, False, False, ),
3302 'IEM_MC_REF_YREG_U128_CONST': (McBlock.parseMcGeneric, False, False, False, ),
3303 'IEM_MC_REF_YREG_U64_CONST': (McBlock.parseMcGeneric, False, False, False, ),
3304 'IEM_MC_REL_CALL_S16_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3305 'IEM_MC_REL_CALL_S32_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3306 'IEM_MC_REL_CALL_S64_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3307 'IEM_MC_REL_JMP_S16_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3308 'IEM_MC_REL_JMP_S32_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3309 'IEM_MC_REL_JMP_S8_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3310 'IEM_MC_RETN_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3311 'IEM_MC_RETURN_ON_FAILURE': (McBlock.parseMcGeneric, False, False, False, ),
3312 'IEM_MC_SAR_LOCAL_S16': (McBlock.parseMcGeneric, False, False, True, ),
3313 'IEM_MC_SAR_LOCAL_S32': (McBlock.parseMcGeneric, False, False, True, ),
3314 'IEM_MC_SAR_LOCAL_S64': (McBlock.parseMcGeneric, False, False, True, ),
3315 'IEM_MC_SET_EFL_BIT': (McBlock.parseMcGeneric, True, True, True, ),
3316 'IEM_MC_SET_FPU_RESULT': (McBlock.parseMcGeneric, True, True, False, ),
3317 'IEM_MC_SET_RIP_U16_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3318 'IEM_MC_SET_RIP_U32_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3319 'IEM_MC_SET_RIP_U64_AND_FINISH': (McBlock.parseMcGeneric, True, True, False, ),
3320 'IEM_MC_SHL_LOCAL_S16': (McBlock.parseMcGeneric, False, False, True, ),
3321 'IEM_MC_SHL_LOCAL_S32': (McBlock.parseMcGeneric, False, False, True, ),
3322 'IEM_MC_SHL_LOCAL_S64': (McBlock.parseMcGeneric, False, False, True, ),
3323 'IEM_MC_SHR_LOCAL_U8': (McBlock.parseMcGeneric, False, False, False, ),
3324 'IEM_MC_SSE_UPDATE_MXCSR': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3325 'IEM_MC_STORE_FPU_RESULT': (McBlock.parseMcGeneric, True, True, False, ),
3326 'IEM_MC_STORE_FPU_RESULT_MEM_OP': (McBlock.parseMcGeneric, True, True, False, ),
3327 'IEM_MC_STORE_FPU_RESULT_THEN_POP': (McBlock.parseMcGeneric, True, True, False, ),
3328 'IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP': (McBlock.parseMcGeneric, True, True, False, ),
3329 'IEM_MC_STORE_FPUREG_R80_SRC_REF': (McBlock.parseMcGeneric, True, True, False, ),
3330 'IEM_MC_STORE_GREG_I64': (McBlock.parseMcGeneric, True, True, True, ),
3331 'IEM_MC_STORE_GREG_U16': (McBlock.parseMcGeneric, True, True, True, ),
3332 'IEM_MC_STORE_GREG_U16_CONST': (McBlock.parseMcGeneric, True, True, True, ),
3333 'IEM_MC_STORE_GREG_U32': (McBlock.parseMcGeneric, True, True, True, ),
3334 'IEM_MC_STORE_GREG_U32_CONST': (McBlock.parseMcGeneric, True, True, True, ),
3335 'IEM_MC_STORE_GREG_U64': (McBlock.parseMcGeneric, True, True, True, ),
3336 'IEM_MC_STORE_GREG_U64_CONST': (McBlock.parseMcGeneric, True, True, True, ),
3337 'IEM_MC_STORE_GREG_U8': (McBlock.parseMcGeneric, True, True, True, ), # thrd var
3338 'IEM_MC_STORE_GREG_U8_CONST': (McBlock.parseMcGeneric, True, True, True, ), # thrd var
3339 'IEM_MC_STORE_GREG_PAIR_U32': (McBlock.parseMcGeneric, True, True, False, ),
3340 'IEM_MC_STORE_GREG_PAIR_U64': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3341 'IEM_MC_STORE_MEM_I16_CONST_BY_REF': (McBlock.parseMcGeneric, True, True, False, ),
3342 'IEM_MC_STORE_MEM_I32_CONST_BY_REF': (McBlock.parseMcGeneric, True, True, False, ),
3343 'IEM_MC_STORE_MEM_I64_CONST_BY_REF': (McBlock.parseMcGeneric, True, True, False, ),
3344 'IEM_MC_STORE_MEM_I8_CONST_BY_REF': (McBlock.parseMcGeneric, True, True, False, ),
3345 'IEM_MC_STORE_MEM_INDEF_D80_BY_REF': (McBlock.parseMcGeneric, True, True, False, ),
3346 'IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF': (McBlock.parseMcGeneric, True, True, False, ),
3347 'IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF': (McBlock.parseMcGeneric, True, True, False, ),
3348 'IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF': (McBlock.parseMcGeneric, True, True, False, ),
3349 'IEM_MC_STORE_MEM_U128': (McBlock.parseMcGeneric, True, True, False, ),
3350 'IEM_MC_STORE_MEM_U128_NO_AC': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3351 'IEM_MC_STORE_MEM_U128_ALIGN_SSE': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3352 'IEM_MC_STORE_MEM_U16': (McBlock.parseMcGeneric, True, True, True, ),
3353 'IEM_MC_STORE_MEM_U16_CONST': (McBlock.parseMcGeneric, True, True, True, ),
3354 'IEM_MC_STORE_MEM_U256': (McBlock.parseMcGeneric, True, True, False, ),
3355 'IEM_MC_STORE_MEM_U256_NO_AC': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3356 'IEM_MC_STORE_MEM_U256_ALIGN_AVX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3357 'IEM_MC_STORE_MEM_U32': (McBlock.parseMcGeneric, True, True, True, ),
3358 'IEM_MC_STORE_MEM_U32_CONST': (McBlock.parseMcGeneric, True, True, True, ),
3359 'IEM_MC_STORE_MEM_U64': (McBlock.parseMcGeneric, True, True, True, ),
3360 'IEM_MC_STORE_MEM_U64_CONST': (McBlock.parseMcGeneric, True, True, True, ),
3361 'IEM_MC_STORE_MEM_U8': (McBlock.parseMcGeneric, True, True, True, ),
3362 'IEM_MC_STORE_MEM_U8_CONST': (McBlock.parseMcGeneric, True, True, True, ),
3363 'IEM_MC_STORE_MREG_U8': (McBlock.parseMcGeneric, True, True, False, ),
3364 'IEM_MC_STORE_MREG_U16': (McBlock.parseMcGeneric, True, True, False, ),
3365 'IEM_MC_STORE_MREG_U32': (McBlock.parseMcGeneric, True, True, False, ),
3366 'IEM_MC_STORE_MREG_U32_ZX_U64': (McBlock.parseMcGeneric, True, True, False, ),
3367 'IEM_MC_STORE_MREG_U64': (McBlock.parseMcGeneric, True, True, False, ),
3368 'IEM_MC_STORE_SREG_BASE_U32': (McBlock.parseMcGeneric, True, True, False, ),
3369 'IEM_MC_STORE_SREG_BASE_U64': (McBlock.parseMcGeneric, True, True, False, ),
3370 'IEM_MC_STORE_XREG_R32': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3371 'IEM_MC_STORE_XREG_R64': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3372 'IEM_MC_STORE_XREG_U128': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3373 'IEM_MC_STORE_XREG_U16': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3374 'IEM_MC_STORE_XREG_U32': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3375 'IEM_MC_STORE_XREG_U32_U128': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3376 'IEM_MC_STORE_XREG_U32_ZX_U128': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3377 'IEM_MC_STORE_XREG_U64': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3378 'IEM_MC_STORE_XREG_U64_ZX_U128': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3379 'IEM_MC_STORE_XREG_U8': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3380 'IEM_MC_STORE_XREG_XMM': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3381 'IEM_MC_STORE_XREG_XMM_U32': (McBlock.parseMcGeneric, True, True, False, ),
3382 'IEM_MC_STORE_XREG_XMM_U64': (McBlock.parseMcGeneric, True, True, False, ),
3383 'IEM_MC_STORE_YREG_U128': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3384 'IEM_MC_STORE_YREG_U128_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3385 'IEM_MC_STORE_YREG_U256_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3386 'IEM_MC_STORE_YREG_U32_U256': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3387 'IEM_MC_STORE_YREG_U32_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3388 'IEM_MC_STORE_YREG_U64': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3389 'IEM_MC_STORE_YREG_U64_U256': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3390 'IEM_MC_STORE_YREG_U64_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd),
3391 'IEM_MC_SUB_GREG_U16': (McBlock.parseMcGeneric, True, True, True, ),
3392 'IEM_MC_SUB_GREG_U32': (McBlock.parseMcGeneric, True, True, True, ),
3393 'IEM_MC_SUB_GREG_U64': (McBlock.parseMcGeneric, True, True, True, ),
3394 'IEM_MC_SUB_LOCAL_U16': (McBlock.parseMcGeneric, False, False, False, ),
3395 'IEM_MC_UPDATE_FPU_OPCODE_IP': (McBlock.parseMcGeneric, True, True, False, ),
3396 'IEM_MC_UPDATE_FSW': (McBlock.parseMcGeneric, True, True, False, ),
3397 'IEM_MC_UPDATE_FSW_CONST': (McBlock.parseMcGeneric, True, True, False, ),
3398 'IEM_MC_UPDATE_FSW_THEN_POP': (McBlock.parseMcGeneric, True, True, False, ),
3399 'IEM_MC_UPDATE_FSW_THEN_POP_POP': (McBlock.parseMcGeneric, True, True, False, ),
3400 'IEM_MC_UPDATE_FSW_WITH_MEM_OP': (McBlock.parseMcGeneric, True, True, False, ),
3401 'IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP': (McBlock.parseMcGeneric, True, True, False, ),
3402 'IEM_MC_NO_NATIVE_RECOMPILE': (McBlock.parseMcGeneric, False, False, False, ),
3403};
3404# pylint: enable=line-too-long
3405
3406## List of microcode blocks.
3407g_aoMcBlocks = [] # type: List[McBlock]
3408
3409
3410
3411class ParserException(Exception):
3412 """ Parser exception """
3413 def __init__(self, sMessage):
3414 Exception.__init__(self, sMessage);
3415
3416
3417class SimpleParser(object): # pylint: disable=too-many-instance-attributes
3418 """
3419 Parser of IEMAllInstruction*.cpp.h instruction specifications.
3420 """
3421
3422 ## @name Parser state.
3423 ## @{
3424 kiCode = 0;
3425 kiCommentMulti = 1;
3426 ## @}
3427
3428 class Macro(object):
3429 """ Macro """
3430 def __init__(self, sName, asArgs, sBody, iLine):
3431 self.sName = sName; ##< The macro name.
3432 self.asArgs = asArgs; ##< None if simple macro, list of parameters otherwise.
3433 self.sBody = sBody;
3434 self.iLine = iLine;
3435 self.oReArgMatch = re.compile(r'(\s*##\s*|\b)(' + '|'.join(asArgs) + r')(\s*##\s*|\b)') if asArgs else None;
3436
3437 @staticmethod
3438 def _needSpace(ch):
3439 """ This is just to make the expanded output a bit prettier. """
3440 return ch.isspace() and ch != '(';
3441
3442 def expandMacro(self, oParent, asArgs = None):
3443 """ Expands the macro body with the given arguments. """
3444 _ = oParent;
3445 sBody = self.sBody;
3446
3447 if self.oReArgMatch:
3448 assert len(asArgs) == len(self.asArgs);
3449 #oParent.debug('%s: %s' % (self.sName, self.oReArgMatch.pattern,));
3450
3451 dArgs = { self.asArgs[iArg]: sValue for iArg, sValue in enumerate(asArgs) };
3452 oMatch = self.oReArgMatch.search(sBody);
3453 while oMatch:
3454 sName = oMatch.group(2);
3455 #oParent.debug('%s %s..%s (%s)' % (sName, oMatch.start(), oMatch.end(),oMatch.group()));
3456 sValue = dArgs[sName];
3457 sPre = '';
3458 if not oMatch.group(1) and oMatch.start() > 0 and self._needSpace(sBody[oMatch.start()]):
3459 sPre = ' ';
3460 sPost = '';
3461 if not oMatch.group(3) and oMatch.end() < len(sBody) and self._needSpace(sBody[oMatch.end()]):
3462 sPost = ' ';
3463 sBody = sBody[ : oMatch.start()] + sPre + sValue + sPost + sBody[oMatch.end() : ];
3464 oMatch = self.oReArgMatch.search(sBody, oMatch.start() + len(sValue));
3465 else:
3466 assert not asArgs;
3467
3468 return sBody;
3469
3470 class PreprocessorConditional(object):
3471 """ Preprocessor conditional (#if/#ifdef/#ifndef/#elif/#else/#endif). """
3472
3473 ## Known defines.
3474 # - A value of 1 indicates that it's always defined.
3475 # - A value of 0 if it's always undefined
3476 # - A value of -1 if it's an arch and it depends of script parameters.
3477 # - A value of -2 if it's not recognized when filtering MC blocks.
3478 kdKnownDefines = {
3479 'IEM_WITH_ONE_BYTE_TABLE': 1,
3480 'IEM_WITH_TWO_BYTE_TABLE': 1,
3481 'IEM_WITH_THREE_0F_38': 1,
3482 'IEM_WITH_THREE_0F_3A': 1,
3483 'IEM_WITH_THREE_BYTE_TABLES': 1,
3484 'IEM_WITH_3DNOW': 1,
3485 'IEM_WITH_3DNOW_TABLE': 1,
3486 'IEM_WITH_VEX': 1,
3487 'IEM_WITH_VEX_TABLES': 1,
3488 'VBOX_WITH_NESTED_HWVIRT_VMX': 1,
3489 'VBOX_WITH_NESTED_HWVIRT_VMX_EPT': 1,
3490 'VBOX_WITH_NESTED_HWVIRT_SVM': 1,
3491 'LOG_ENABLED': 1,
3492 'RT_WITHOUT_PRAGMA_ONCE': 0,
3493 'TST_IEM_CHECK_MC': 0,
3494 'IEM_WITHOUT_ASSEMBLY': -2, ##< @todo ??
3495 'RT_ARCH_AMD64': -1,
3496 'RT_ARCH_ARM64': -1,
3497 'RT_ARCH_ARM32': -1,
3498 'RT_ARCH_X86': -1,
3499 'RT_ARCH_SPARC': -1,
3500 'RT_ARCH_SPARC64': -1,
3501 };
3502 kdBuildArchToIprt = {
3503 'amd64': 'RT_ARCH_AMD64',
3504 'arm64': 'RT_ARCH_ARM64',
3505 'sparc32': 'RT_ARCH_SPARC64',
3506 };
3507 ## For parsing the next defined(xxxx).
3508 koMatchDefined = re.compile(r'\s*defined\s*\(\s*([^ \t)]+)\s*\)\s*');
3509
3510 def __init__(self, sType, sExpr):
3511 self.sType = sType;
3512 self.sExpr = sExpr; ##< Expression without command and no leading or trailing spaces.
3513 self.aoElif = [] # type: List[PreprocessorConditional]
3514 self.fInElse = [];
3515 if sType in ('if', 'elif'):
3516 self.checkExpression(sExpr);
3517 else:
3518 self.checkSupportedDefine(sExpr)
3519
3520 @staticmethod
3521 def checkSupportedDefine(sDefine):
3522 """ Checks that sDefine is one that we support. Raises exception if unuspported. """
3523 #print('debug: checkSupportedDefine: %s' % (sDefine,), file = sys.stderr);
3524 if sDefine in SimpleParser.PreprocessorConditional.kdKnownDefines:
3525 return True;
3526 if sDefine.startswith('VMM_INCLUDED_') and sDefine.endswith('_h'):
3527 return True;
3528 raise Exception('Unsupported define: %s' % (sDefine,));
3529
3530 @staticmethod
3531 def checkExpression(sExpr):
3532 """ Check that the expression is supported. Raises exception if not. """
3533 #print('debug: checkExpression: %s' % (sExpr,), file = sys.stderr);
3534 if sExpr in ('0', '1'):
3535 return True;
3536
3537 off = 0;
3538 cParan = 0;
3539 while off < len(sExpr):
3540 ch = sExpr[off];
3541
3542 # Unary operator or parentheses:
3543 if ch in ('(', '!'):
3544 if ch == '(':
3545 cParan += 1;
3546 off += 1;
3547 else:
3548 # defined(xxxx)
3549 oMatch = SimpleParser.PreprocessorConditional.koMatchDefined.match(sExpr, off);
3550 if oMatch:
3551 SimpleParser.PreprocessorConditional.checkSupportedDefine(oMatch.group(1));
3552 elif sExpr[off:] != '1':
3553 raise Exception('Cannot grok: \'%s\' (at %u in: \'%s\')' % (sExpr[off:10], off + 1, sExpr,));
3554 off = oMatch.end();
3555
3556 # Look for closing parentheses.
3557 while off < len(sExpr) and sExpr[off].isspace():
3558 off += 1;
3559 if cParan > 0:
3560 while off < len(sExpr) and sExpr[off] == ')':
3561 if cParan <= 0:
3562 raise Exception('Unbalanced parentheses at %u in \'%s\'' % (off + 1, sExpr,));
3563 cParan -= 1;
3564 off += 1;
3565 while off < len(sExpr) and sExpr[off].isspace():
3566 off += 1;
3567
3568 # Look for binary operator.
3569 if off >= len(sExpr):
3570 break;
3571 if sExpr[off:off + 2] in ('||', '&&'):
3572 off += 2;
3573 else:
3574 raise Exception('Cannot grok operator: \'%s\' (at %u in: \'%s\')' % (sExpr[off:2], off + 1, sExpr,));
3575
3576 # Skip spaces.
3577 while off < len(sExpr) and sExpr[off].isspace():
3578 off += 1;
3579 if cParan != 0:
3580 raise Exception('Unbalanced parentheses at %u in \'%s\'' % (off + 1, sExpr,));
3581 return True;
3582
3583 @staticmethod
3584 def isArchIncludedInExpr(sExpr, sArch):
3585 """ Checks if sArch is included in the given expression. """
3586 # We only grok defined() [|| defined()...] and [1|0] at the moment.
3587 if sExpr == '0':
3588 return False;
3589 if sExpr == '1':
3590 return True;
3591 off = 0;
3592 while off < len(sExpr):
3593 # defined(xxxx)
3594 oMatch = SimpleParser.PreprocessorConditional.koMatchDefined.match(sExpr, off);
3595 if not oMatch:
3596 if sExpr[off:] == '1':
3597 return True;
3598 raise Exception('Cannot grok: %s (at %u in: %s)' % (sExpr[off:10], off + 1, sExpr,));
3599 if SimpleParser.PreprocessorConditional.matchDefined(oMatch.group(1), sArch):
3600 return True;
3601 off = oMatch.end();
3602
3603 # Look for OR operator.
3604 while off + 1 < len(sExpr) and sExpr[off + 1].isspace():
3605 off += 1;
3606 if off >= len(sExpr):
3607 break;
3608 if sExpr.startswith('||'):
3609 off += 2;
3610 else:
3611 raise Exception('Cannot grok: %s (at %u in: %s)' % (sExpr[off:10], off + 1, sExpr,));
3612
3613 return False;
3614
3615 @staticmethod
3616 def matchArch(sDefine, sArch):
3617 """ Compares sDefine (RT_ARCH_XXXX) and sArch (x86, amd64, arm64, ++). """
3618 return SimpleParser.PreprocessorConditional.kdBuildArchToIprt[sArch] == sDefine;
3619
3620 @staticmethod
3621 def matchDefined(sExpr, sArch):
3622 """ Check the result of an ifdef/ifndef expression, given sArch. """
3623 iDefine = SimpleParser.PreprocessorConditional.kdKnownDefines.get(sExpr, 0);
3624 if iDefine == -2:
3625 raise Exception('Unsupported define for MC block filtering: %s' % (sExpr,));
3626 return iDefine == 1 or (iDefine == -1 and SimpleParser.PreprocessorConditional.matchArch(sExpr, sArch));
3627
3628 def isArchIncludedInPrimaryBlock(self, sArch):
3629 """ Checks if sArch is included in the (primary) 'if' block. """
3630 if self.sType == 'ifdef':
3631 return self.matchDefined(self.sExpr, sArch);
3632 if self.sType == 'ifndef':
3633 return not self.matchDefined(self.sExpr, sArch);
3634 return self.isArchIncludedInExpr(self.sExpr, sArch);
3635
3636 @staticmethod
3637 def isInBlockForArch(aoCppCondStack, sArch, iLine):
3638 """ Checks if sArch is included in the current conditional block. """
3639 _ = iLine;
3640 #print('debug: isInBlockForArch(%s,%s); line %s' % (len(aoCppCondStack), sArch, iLine), file = sys.stderr);
3641 for oCond in aoCppCondStack:
3642 if oCond.isArchIncludedInPrimaryBlock(sArch):
3643 if oCond.aoElif or oCond.fInElse:
3644 #print('debug: isInBlockForArch -> False #1', file = sys.stderr);
3645 return False;
3646 #print('debug: isInBlockForArch(%s,%s): in IF-block' % (len(aoCppCondStack), sArch), file = sys.stderr);
3647 else:
3648 fFine = False;
3649 for oElifCond in oCond.aoElif:
3650 if oElifCond.isArchIncludedInPrimaryBlock(sArch):
3651 if oElifCond is not oCond.aoElif[-1] or oCond.fInElse:
3652 #print('debug: isInBlockForArch -> False #3', file = sys.stderr);
3653 return False;
3654 fFine = True;
3655 if not fFine and not oCond.fInElse:
3656 #print('debug: isInBlockForArch -> False #4', file = sys.stderr);
3657 return False;
3658 #print('debug: isInBlockForArch -> True', file = sys.stderr);
3659 return True;
3660
3661 def __init__(self, sSrcFile, asLines, sDefaultMap, sHostArch, oInheritMacrosFrom = None):
3662 self.sSrcFile = sSrcFile;
3663 self.asLines = asLines;
3664 self.iLine = 0;
3665 self.iState = self.kiCode;
3666 self.sComment = '';
3667 self.iCommentLine = 0;
3668 self.aoCurInstrs = [] # type: List[Instruction]
3669 self.oCurFunction = None # type: DecoderFunction
3670 self.iMcBlockInFunc = 0;
3671 self.oCurMcBlock = None # type: McBlock
3672 self.dMacros = {} # type: Dict[str, SimpleParser.Macro]
3673 self.oReMacros = None # type: re ##< Regular expression matching invocations of anything in self.dMacros.
3674 if oInheritMacrosFrom:
3675 self.dMacros = dict(oInheritMacrosFrom.dMacros);
3676 self.oReMacros = oInheritMacrosFrom.oReMacros;
3677 self.aoCppCondStack = [] # type: List[PreprocessorConditional] ##< Preprocessor conditional stack.
3678 self.sHostArch = sHostArch;
3679
3680 assert sDefaultMap in g_dInstructionMaps;
3681 self.oDefaultMap = g_dInstructionMaps[sDefaultMap];
3682
3683 self.cTotalInstr = 0;
3684 self.cTotalStubs = 0;
3685 self.cTotalTagged = 0;
3686 self.cTotalMcBlocks = 0;
3687
3688 self.oReMacroName = re.compile(r'^[A-Za-z_][A-Za-z0-9_]*$');
3689 self.oReMnemonic = re.compile(r'^[A-Za-z_][A-Za-z0-9_]*$');
3690 self.oReStatsName = re.compile(r'^[A-Za-z_][A-Za-z0-9_]*$');
3691 self.oReFunctionName= re.compile(r'^iemOp_[A-Za-z_][A-Za-z0-9_]*$');
3692 self.oReGroupName = re.compile(r'^og_[a-z0-9]+(|_[a-z0-9]+|_[a-z0-9]+_[a-z0-9]+)$');
3693 self.oReDisEnum = re.compile(r'^OP_[A-Z0-9_]+$');
3694 self.oReFunTable = re.compile(r'^(IEM_STATIC|static) +const +PFNIEMOP +g_apfn[A-Za-z0-9_]+ *\[ *\d* *\] *= *$');
3695 self.oReComment = re.compile(r'//.*?$|/\*.*?\*/'); ## Full comments.
3696 self.oReHashDefine2 = re.compile(r'(?s)\A\s*([A-Za-z_][A-Za-z0-9_]*)\(([^)]*)\)\s*(.*)\Z'); ##< With arguments.
3697 self.oReHashDefine3 = re.compile(r'(?s)\A\s*([A-Za-z_][A-Za-z0-9_]*)[^(]\s*(.*)\Z'); ##< Simple, no arguments.
3698 self.oReMcBeginEnd = re.compile(r'\bIEM_MC_(BEGIN|END|DEFER_TO_CIMPL_[1-5]_RET)\s*\('); ##> Not DEFER_TO_CIMPL_0_RET!
3699 self.fDebug = True;
3700 self.fDebugMc = False;
3701 self.fDebugPreproc = False;
3702
3703 self.dTagHandlers = {
3704 '@opbrief': self.parseTagOpBrief,
3705 '@opdesc': self.parseTagOpDesc,
3706 '@opmnemonic': self.parseTagOpMnemonic,
3707 '@op1': self.parseTagOpOperandN,
3708 '@op2': self.parseTagOpOperandN,
3709 '@op3': self.parseTagOpOperandN,
3710 '@op4': self.parseTagOpOperandN,
3711 '@oppfx': self.parseTagOpPfx,
3712 '@opmaps': self.parseTagOpMaps,
3713 '@opcode': self.parseTagOpcode,
3714 '@opcodesub': self.parseTagOpcodeSub,
3715 '@openc': self.parseTagOpEnc,
3716 #@opfltest: Lists all flags that will be used as input in some way.
3717 '@opfltest': self.parseTagOpEFlags,
3718 #@opflmodify: Lists all EFLAGS modified. Includes @opflset, @opflcleared and @opflundef (if applicable).
3719 '@opflmodify': self.parseTagOpEFlags,
3720 #@opflclear: Lists all flags that will be set (set to 1).
3721 '@opflset': self.parseTagOpEFlags,
3722 #@opflclear: Lists all flags that will be cleared (set to 0).
3723 '@opflclear': self.parseTagOpEFlags,
3724 #@opflundef: List of flag documented as undefined.
3725 '@opflundef': self.parseTagOpEFlags,
3726 #@opflclass: Shorthand for defining flag behaviour (@opfltest, @opfmodify, @opflset, @opflclear, @opflundef).
3727 '@opflclass': self.parseTagOpEFlagsClass,
3728 '@ophints': self.parseTagOpHints,
3729 '@opdisenum': self.parseTagOpDisEnum,
3730 '@opmincpu': self.parseTagOpMinCpu,
3731 '@opcpuid': self.parseTagOpCpuId,
3732 '@opgroup': self.parseTagOpGroup,
3733 '@opunused': self.parseTagOpUnusedInvalid,
3734 '@opinvalid': self.parseTagOpUnusedInvalid,
3735 '@opinvlstyle': self.parseTagOpUnusedInvalid,
3736 '@optest': self.parseTagOpTest,
3737 '@optestign': self.parseTagOpTestIgnore,
3738 '@optestignore': self.parseTagOpTestIgnore,
3739 '@opcopytests': self.parseTagOpCopyTests,
3740 '@oponly': self.parseTagOpOnlyTest,
3741 '@oponlytest': self.parseTagOpOnlyTest,
3742 '@opxcpttype': self.parseTagOpXcptType,
3743 '@opstats': self.parseTagOpStats,
3744 '@opfunction': self.parseTagOpFunction,
3745 '@opdone': self.parseTagOpDone,
3746 };
3747 for i in range(48):
3748 self.dTagHandlers['@optest%u' % (i,)] = self.parseTagOpTestNum;
3749 self.dTagHandlers['@optest[%u]' % (i,)] = self.parseTagOpTestNum;
3750
3751 self.asErrors = [];
3752
3753 def raiseError(self, sMessage):
3754 """
3755 Raise error prefixed with the source and line number.
3756 """
3757 raise ParserException("%s:%d: error: %s" % (self.sSrcFile, self.iLine, sMessage,));
3758
3759 def raiseCommentError(self, iLineInComment, sMessage):
3760 """
3761 Similar to raiseError, but the line number is iLineInComment + self.iCommentLine.
3762 """
3763 raise ParserException("%s:%d: error: %s" % (self.sSrcFile, self.iCommentLine + iLineInComment, sMessage,));
3764
3765 def error(self, sMessage):
3766 """
3767 Adds an error.
3768 returns False;
3769 """
3770 self.asErrors.append(u'%s:%d: error: %s\n' % (self.sSrcFile, self.iLine, sMessage,));
3771 return False;
3772
3773 def errorOnLine(self, iLine, sMessage):
3774 """
3775 Adds an error.
3776 returns False;
3777 """
3778 self.asErrors.append(u'%s:%d: error: %s\n' % (self.sSrcFile, iLine, sMessage,));
3779 return False;
3780
3781 def errorComment(self, iLineInComment, sMessage):
3782 """
3783 Adds a comment error.
3784 returns False;
3785 """
3786 self.asErrors.append(u'%s:%d: error: %s\n' % (self.sSrcFile, self.iCommentLine + iLineInComment, sMessage,));
3787 return False;
3788
3789 def printErrors(self):
3790 """
3791 Print the errors to stderr.
3792 Returns number of errors.
3793 """
3794 if self.asErrors:
3795 sys.stderr.write(u''.join(self.asErrors));
3796 return len(self.asErrors);
3797
3798 def debug(self, sMessage):
3799 """
3800 For debugging.
3801 """
3802 if self.fDebug:
3803 print('debug: %s' % (sMessage,), file = sys.stderr);
3804
3805 def stripComments(self, sLine):
3806 """
3807 Returns sLine with comments stripped.
3808
3809 Complains if traces of incomplete multi-line comments are encountered.
3810 """
3811 sLine = self.oReComment.sub(" ", sLine);
3812 if sLine.find('/*') >= 0 or sLine.find('*/') >= 0:
3813 self.error('Unexpected multi-line comment will not be handled correctly. Please simplify.');
3814 return sLine;
3815
3816 def parseFunctionTable(self, sLine):
3817 """
3818 Parses a PFNIEMOP table, updating/checking the @oppfx value.
3819
3820 Note! Updates iLine as it consumes the whole table.
3821 """
3822
3823 #
3824 # Extract the table name.
3825 #
3826 sName = re.search(r' *([a-zA-Z_0-9]+) *\[', sLine).group(1);
3827 oMap = g_dInstructionMapsByIemName.get(sName);
3828 if not oMap:
3829 self.debug('No map for PFNIEMOP table: %s' % (sName,));
3830 oMap = self.oDefaultMap; # This is wrong wrong wrong.
3831
3832 #
3833 # All but the g_apfnOneByteMap & g_apfnEscF1_E0toFF tables uses four
3834 # entries per byte:
3835 # no prefix, 066h prefix, f3h prefix, f2h prefix
3836 # Those tables has 256 & 32 entries respectively.
3837 #
3838 cEntriesPerByte = 4;
3839 cValidTableLength = 1024;
3840 asPrefixes = ('none', '0x66', '0xf3', '0xf2');
3841
3842 oEntriesMatch = re.search(r'\[ *(256|32) *\]', sLine);
3843 if oEntriesMatch:
3844 cEntriesPerByte = 1;
3845 cValidTableLength = int(oEntriesMatch.group(1));
3846 asPrefixes = (None,);
3847
3848 #
3849 # The next line should be '{' and nothing else.
3850 #
3851 if self.iLine >= len(self.asLines) or not re.match('^ *{ *$', self.asLines[self.iLine]):
3852 return self.errorOnLine(self.iLine + 1, 'Expected lone "{" on line following PFNIEMOP table %s start' % (sName, ));
3853 self.iLine += 1;
3854
3855 #
3856 # Parse till we find the end of the table.
3857 #
3858 iEntry = 0;
3859 while self.iLine < len(self.asLines):
3860 # Get the next line and strip comments and spaces (assumes no
3861 # multi-line comments).
3862 sLine = self.asLines[self.iLine];
3863 self.iLine += 1;
3864 sLine = self.stripComments(sLine).strip();
3865
3866 # Split the line up into entries, expanding IEMOP_X4 usage.
3867 asEntries = sLine.split(',');
3868 for i in range(len(asEntries) - 1, -1, -1):
3869 sEntry = asEntries[i].strip();
3870 if sEntry.startswith('IEMOP_X4(') and sEntry[-1] == ')':
3871 sEntry = (sEntry[len('IEMOP_X4('):-1]).strip();
3872 asEntries.insert(i + 1, sEntry);
3873 asEntries.insert(i + 1, sEntry);
3874 asEntries.insert(i + 1, sEntry);
3875 if sEntry:
3876 asEntries[i] = sEntry;
3877 else:
3878 del asEntries[i];
3879
3880 # Process the entries.
3881 for sEntry in asEntries:
3882 if sEntry in ('};', '}'):
3883 if iEntry != cValidTableLength:
3884 return self.error('Wrong table length for %s: %#x, expected %#x' % (sName, iEntry, cValidTableLength, ));
3885 return True;
3886 if sEntry.startswith('iemOp_Invalid'):
3887 pass; # skip
3888 else:
3889 # Look up matching instruction by function.
3890 sPrefix = asPrefixes[iEntry % cEntriesPerByte];
3891 sOpcode = '%#04x' % (iEntry // cEntriesPerByte);
3892 aoInstr = g_dAllInstructionsByFunction.get(sEntry);
3893 if aoInstr:
3894 if not isinstance(aoInstr, list):
3895 aoInstr = [aoInstr,];
3896 oInstr = None;
3897 for oCurInstr in aoInstr:
3898 if oCurInstr.sOpcode == sOpcode and oCurInstr.sPrefix == sPrefix:
3899 pass;
3900 elif oCurInstr.sOpcode == sOpcode and oCurInstr.sPrefix is None:
3901 oCurInstr.sPrefix = sPrefix;
3902 elif oCurInstr.sOpcode is None and oCurInstr.sPrefix is None:
3903 oCurInstr.sOpcode = sOpcode;
3904 oCurInstr.sPrefix = sPrefix;
3905 else:
3906 continue;
3907 oInstr = oCurInstr;
3908 break;
3909 if not oInstr:
3910 oInstr = aoInstr[0].copy(oMap = oMap, sOpcode = sOpcode, sPrefix = sPrefix);
3911 aoInstr.append(oInstr);
3912 g_dAllInstructionsByFunction[sEntry] = aoInstr;
3913 g_aoAllInstructions.append(oInstr);
3914 oMap.aoInstructions.append(oInstr);
3915 else:
3916 self.debug('Function "%s", entry %#04x / byte %#04x in %s, is not associated with an instruction.'
3917 % (sEntry, iEntry, iEntry // cEntriesPerByte, sName,));
3918 iEntry += 1;
3919
3920 return self.error('Unexpected end of file in PFNIEMOP table');
3921
3922 def addInstruction(self, iLine = None):
3923 """
3924 Adds an instruction.
3925 """
3926 oInstr = Instruction(self.sSrcFile, self.iLine if iLine is None else iLine);
3927 g_aoAllInstructions.append(oInstr);
3928 self.aoCurInstrs.append(oInstr);
3929 return oInstr;
3930
3931 def deriveMnemonicAndOperandsFromStats(self, oInstr, sStats):
3932 """
3933 Derives the mnemonic and operands from a IEM stats base name like string.
3934 """
3935 if oInstr.sMnemonic is None:
3936 asWords = sStats.split('_');
3937 oInstr.sMnemonic = asWords[0].lower();
3938 if len(asWords) > 1 and not oInstr.aoOperands:
3939 for sType in asWords[1:]:
3940 if sType in g_kdOpTypes:
3941 oInstr.aoOperands.append(Operand(g_kdOpTypes[sType][1], sType));
3942 else:
3943 #return self.error('unknown operand type: %s (instruction: %s)' % (sType, oInstr))
3944 return False;
3945 return True;
3946
3947 def doneInstructionOne(self, oInstr, iLine):
3948 """
3949 Complete the parsing by processing, validating and expanding raw inputs.
3950 """
3951 assert oInstr.iLineCompleted is None;
3952 oInstr.iLineCompleted = iLine;
3953
3954 #
3955 # Specified instructions.
3956 #
3957 if oInstr.cOpTags > 0:
3958 if oInstr.sStats is None:
3959 pass;
3960
3961 #
3962 # Unspecified legacy stuff. We generally only got a few things to go on here.
3963 # /** Opcode 0x0f 0x00 /0. */
3964 # FNIEMOPRM_DEF(iemOp_Grp6_sldt)
3965 #
3966 else:
3967 #if oInstr.sRawOldOpcodes:
3968 #
3969 #if oInstr.sMnemonic:
3970 pass;
3971
3972 #
3973 # Common defaults.
3974 #
3975
3976 # Guess mnemonic and operands from stats if the former is missing.
3977 if oInstr.sMnemonic is None:
3978 if oInstr.sStats is not None:
3979 self.deriveMnemonicAndOperandsFromStats(oInstr, oInstr.sStats);
3980 elif oInstr.sFunction is not None:
3981 self.deriveMnemonicAndOperandsFromStats(oInstr, oInstr.sFunction.replace('iemOp_', ''));
3982
3983 # Derive the disassembler op enum constant from the mnemonic.
3984 if oInstr.sDisEnum is None and oInstr.sMnemonic is not None:
3985 oInstr.sDisEnum = 'OP_' + oInstr.sMnemonic.upper();
3986
3987 # Derive the IEM statistics base name from mnemonic and operand types.
3988 if oInstr.sStats is None:
3989 if oInstr.sFunction is not None:
3990 oInstr.sStats = oInstr.sFunction.replace('iemOp_', '');
3991 elif oInstr.sMnemonic is not None:
3992 oInstr.sStats = oInstr.sMnemonic;
3993 for oOperand in oInstr.aoOperands:
3994 if oOperand.sType:
3995 oInstr.sStats += '_' + oOperand.sType;
3996
3997 # Derive the IEM function name from mnemonic and operand types.
3998 if oInstr.sFunction is None:
3999 if oInstr.sMnemonic is not None:
4000 oInstr.sFunction = 'iemOp_' + oInstr.sMnemonic;
4001 for oOperand in oInstr.aoOperands:
4002 if oOperand.sType:
4003 oInstr.sFunction += '_' + oOperand.sType;
4004 elif oInstr.sStats:
4005 oInstr.sFunction = 'iemOp_' + oInstr.sStats;
4006
4007 #
4008 # Apply default map and then add the instruction to all it's groups.
4009 #
4010 if not oInstr.aoMaps:
4011 oInstr.aoMaps = [ self.oDefaultMap, ];
4012 for oMap in oInstr.aoMaps:
4013 oMap.aoInstructions.append(oInstr);
4014
4015 #
4016 # Derive encoding from operands and maps.
4017 #
4018 if oInstr.sEncoding is None:
4019 if not oInstr.aoOperands:
4020 if oInstr.fUnused and oInstr.sSubOpcode:
4021 oInstr.sEncoding = 'VEX.ModR/M' if oInstr.onlyInVexMaps() else 'ModR/M';
4022 else:
4023 oInstr.sEncoding = 'VEX.fixed' if oInstr.onlyInVexMaps() else 'fixed';
4024 elif oInstr.aoOperands[0].usesModRM():
4025 if (len(oInstr.aoOperands) >= 2 and oInstr.aoOperands[1].sWhere == 'vvvv') \
4026 or oInstr.onlyInVexMaps():
4027 oInstr.sEncoding = 'VEX.ModR/M';
4028 else:
4029 oInstr.sEncoding = 'ModR/M';
4030
4031 #
4032 # Check the opstat value and add it to the opstat indexed dictionary.
4033 #
4034 if oInstr.sStats:
4035 if oInstr.sStats not in g_dAllInstructionsByStat:
4036 g_dAllInstructionsByStat[oInstr.sStats] = oInstr;
4037 else:
4038 self.error('Duplicate opstat value "%s"\nnew: %s\nold: %s'
4039 % (oInstr.sStats, oInstr, g_dAllInstructionsByStat[oInstr.sStats],));
4040
4041 #
4042 # Add to function indexed dictionary. We allow multiple instructions per function.
4043 #
4044 if oInstr.sFunction:
4045 if oInstr.sFunction not in g_dAllInstructionsByFunction:
4046 g_dAllInstructionsByFunction[oInstr.sFunction] = [oInstr,];
4047 else:
4048 g_dAllInstructionsByFunction[oInstr.sFunction].append(oInstr);
4049
4050 #self.debug('%d..%d: %s; %d @op tags' % (oInstr.iLineCreated, oInstr.iLineCompleted, oInstr.sFunction, oInstr.cOpTags));
4051 return True;
4052
4053 def doneInstructions(self, iLineInComment = None, fEndOfFunction = False):
4054 """
4055 Done with current instruction.
4056 """
4057 for oInstr in self.aoCurInstrs:
4058 self.doneInstructionOne(oInstr, self.iLine if iLineInComment is None else self.iCommentLine + iLineInComment);
4059 if oInstr.fStub:
4060 self.cTotalStubs += 1;
4061
4062 self.cTotalInstr += len(self.aoCurInstrs);
4063
4064 self.sComment = '';
4065 self.aoCurInstrs = [];
4066 if fEndOfFunction:
4067 #self.debug('%s: oCurFunction=None' % (self.iLine, ));
4068 if self.oCurFunction:
4069 self.oCurFunction.complete(self.iLine, self.asLines[self.oCurFunction.iBeginLine - 1 : self.iLine]);
4070 self.oCurFunction = None;
4071 self.iMcBlockInFunc = 0;
4072 return True;
4073
4074 def setInstrunctionAttrib(self, sAttrib, oValue, fOverwrite = False):
4075 """
4076 Sets the sAttrib of all current instruction to oValue. If fOverwrite
4077 is False, only None values and empty strings are replaced.
4078 """
4079 for oInstr in self.aoCurInstrs:
4080 if fOverwrite is not True:
4081 oOldValue = getattr(oInstr, sAttrib);
4082 if oOldValue is not None:
4083 continue;
4084 setattr(oInstr, sAttrib, oValue);
4085
4086 def setInstrunctionArrayAttrib(self, sAttrib, iEntry, oValue, fOverwrite = False):
4087 """
4088 Sets the iEntry of the array sAttrib of all current instruction to oValue.
4089 If fOverwrite is False, only None values and empty strings are replaced.
4090 """
4091 for oInstr in self.aoCurInstrs:
4092 aoArray = getattr(oInstr, sAttrib);
4093 while len(aoArray) <= iEntry:
4094 aoArray.append(None);
4095 if fOverwrite is True or aoArray[iEntry] is None:
4096 aoArray[iEntry] = oValue;
4097
4098 def parseCommentOldOpcode(self, asLines):
4099 """ Deals with 'Opcode 0xff /4' like comments """
4100 asWords = asLines[0].split();
4101 if len(asWords) >= 2 \
4102 and asWords[0] == 'Opcode' \
4103 and ( asWords[1].startswith('0x')
4104 or asWords[1].startswith('0X')):
4105 asWords = asWords[:1];
4106 for iWord, sWord in enumerate(asWords):
4107 if sWord.startswith('0X'):
4108 sWord = '0x' + sWord[:2];
4109 asWords[iWord] = asWords;
4110 self.setInstrunctionAttrib('sRawOldOpcodes', ' '.join(asWords));
4111
4112 return False;
4113
4114 def ensureInstructionForOpTag(self, iTagLine):
4115 """ Ensure there is an instruction for the op-tag being parsed. """
4116 if not self.aoCurInstrs:
4117 self.addInstruction(self.iCommentLine + iTagLine);
4118 for oInstr in self.aoCurInstrs:
4119 oInstr.cOpTags += 1;
4120 if oInstr.cOpTags == 1:
4121 self.cTotalTagged += 1;
4122 return self.aoCurInstrs[-1];
4123
4124 @staticmethod
4125 def flattenSections(aasSections):
4126 """
4127 Flattens multiline sections into stripped single strings.
4128 Returns list of strings, on section per string.
4129 """
4130 asRet = [];
4131 for asLines in aasSections:
4132 if asLines:
4133 asRet.append(' '.join([sLine.strip() for sLine in asLines]));
4134 return asRet;
4135
4136 @staticmethod
4137 def flattenAllSections(aasSections, sLineSep = ' ', sSectionSep = '\n'):
4138 """
4139 Flattens sections into a simple stripped string with newlines as
4140 section breaks. The final section does not sport a trailing newline.
4141 """
4142 # Typical: One section with a single line.
4143 if len(aasSections) == 1 and len(aasSections[0]) == 1:
4144 return aasSections[0][0].strip();
4145
4146 sRet = '';
4147 for iSection, asLines in enumerate(aasSections):
4148 if asLines:
4149 if iSection > 0:
4150 sRet += sSectionSep;
4151 sRet += sLineSep.join([sLine.strip() for sLine in asLines]);
4152 return sRet;
4153
4154
4155
4156 ## @name Tag parsers
4157 ## @{
4158
4159 def parseTagOpBrief(self, sTag, aasSections, iTagLine, iEndLine):
4160 """
4161 Tag: @opbrief
4162 Value: Text description, multiple sections, appended.
4163
4164 Brief description. If not given, it's the first sentence from @opdesc.
4165 """
4166 oInstr = self.ensureInstructionForOpTag(iTagLine);
4167
4168 # Flatten and validate the value.
4169 sBrief = self.flattenAllSections(aasSections);
4170 if not sBrief:
4171 return self.errorComment(iTagLine, '%s: value required' % (sTag,));
4172 if sBrief[-1] != '.':
4173 sBrief = sBrief + '.';
4174 if len(sBrief) > 180:
4175 return self.errorComment(iTagLine, '%s: value too long (max 180 chars): %s' % (sTag, sBrief));
4176 offDot = sBrief.find('.');
4177 while 0 <= offDot < len(sBrief) - 1 and sBrief[offDot + 1] != ' ':
4178 offDot = sBrief.find('.', offDot + 1);
4179 if offDot >= 0 and offDot != len(sBrief) - 1:
4180 return self.errorComment(iTagLine, '%s: only one sentence: %s' % (sTag, sBrief));
4181
4182 # Update the instruction.
4183 if oInstr.sBrief is not None:
4184 return self.errorComment(iTagLine, '%s: attempting to overwrite brief "%s" with "%s"'
4185 % (sTag, oInstr.sBrief, sBrief,));
4186 _ = iEndLine;
4187 return True;
4188
4189 def parseTagOpDesc(self, sTag, aasSections, iTagLine, iEndLine):
4190 """
4191 Tag: @opdesc
4192 Value: Text description, multiple sections, appended.
4193
4194 It is used to describe instructions.
4195 """
4196 oInstr = self.ensureInstructionForOpTag(iTagLine);
4197 if aasSections:
4198 oInstr.asDescSections.extend(self.flattenSections(aasSections));
4199 return True;
4200
4201 _ = sTag; _ = iEndLine;
4202 return True;
4203
4204 def parseTagOpMnemonic(self, sTag, aasSections, iTagLine, iEndLine):
4205 """
4206 Tag: @opmenmonic
4207 Value: mnemonic
4208
4209 The 'mnemonic' value must be a valid C identifier string. Because of
4210 prefixes, groups and whatnot, there times when the mnemonic isn't that
4211 of an actual assembler mnemonic.
4212 """
4213 oInstr = self.ensureInstructionForOpTag(iTagLine);
4214
4215 # Flatten and validate the value.
4216 sMnemonic = self.flattenAllSections(aasSections);
4217 if not self.oReMnemonic.match(sMnemonic):
4218 return self.errorComment(iTagLine, '%s: invalid menmonic name: "%s"' % (sTag, sMnemonic,));
4219 if oInstr.sMnemonic is not None:
4220 return self.errorComment(iTagLine, '%s: attempting to overwrite menmonic "%s" with "%s"'
4221 % (sTag, oInstr.sMnemonic, sMnemonic,));
4222 oInstr.sMnemonic = sMnemonic
4223
4224 _ = iEndLine;
4225 return True;
4226
4227 def parseTagOpOperandN(self, sTag, aasSections, iTagLine, iEndLine):
4228 """
4229 Tags: @op1, @op2, @op3, @op4
4230 Value: [where:]type
4231
4232 The 'where' value indicates where the operand is found, like the 'reg'
4233 part of the ModR/M encoding. See Instruction.kdOperandLocations for
4234 a list.
4235
4236 The 'type' value indicates the operand type. These follow the types
4237 given in the opcode tables in the CPU reference manuals.
4238 See Instruction.kdOperandTypes for a list.
4239
4240 """
4241 oInstr = self.ensureInstructionForOpTag(iTagLine);
4242 idxOp = int(sTag[-1]) - 1;
4243 assert 0 <= idxOp < 4;
4244
4245 # flatten, split up, and validate the "where:type" value.
4246 sFlattened = self.flattenAllSections(aasSections);
4247 asSplit = sFlattened.split(':');
4248 if len(asSplit) == 1:
4249 sType = asSplit[0];
4250 sWhere = None;
4251 elif len(asSplit) == 2:
4252 (sWhere, sType) = asSplit;
4253 else:
4254 return self.errorComment(iTagLine, 'expected %s value on format "[<where>:]<type>" not "%s"' % (sTag, sFlattened,));
4255
4256 if sType not in g_kdOpTypes:
4257 return self.errorComment(iTagLine, '%s: invalid where value "%s", valid: %s'
4258 % (sTag, sType, ', '.join(g_kdOpTypes.keys()),));
4259 if sWhere is None:
4260 sWhere = g_kdOpTypes[sType][1];
4261 elif sWhere not in g_kdOpLocations:
4262 return self.errorComment(iTagLine, '%s: invalid where value "%s", valid: %s'
4263 % (sTag, sWhere, ', '.join(g_kdOpLocations.keys()),));
4264
4265 # Insert the operand, refusing to overwrite an existing one.
4266 while idxOp >= len(oInstr.aoOperands):
4267 oInstr.aoOperands.append(None);
4268 if oInstr.aoOperands[idxOp] is not None:
4269 return self.errorComment(iTagLine, '%s: attempting to overwrite "%s:%s" with "%s:%s"'
4270 % ( sTag, oInstr.aoOperands[idxOp].sWhere, oInstr.aoOperands[idxOp].sType,
4271 sWhere, sType,));
4272 oInstr.aoOperands[idxOp] = Operand(sWhere, sType);
4273
4274 _ = iEndLine;
4275 return True;
4276
4277 def parseTagOpMaps(self, sTag, aasSections, iTagLine, iEndLine):
4278 """
4279 Tag: @opmaps
4280 Value: map[,map2]
4281
4282 Indicates which maps the instruction is in. There is a default map
4283 associated with each input file.
4284 """
4285 oInstr = self.ensureInstructionForOpTag(iTagLine);
4286
4287 # Flatten, split up and validate the value.
4288 sFlattened = self.flattenAllSections(aasSections, sLineSep = ',', sSectionSep = ',');
4289 asMaps = sFlattened.split(',');
4290 if not asMaps:
4291 return self.errorComment(iTagLine, '%s: value required' % (sTag,));
4292 for sMap in asMaps:
4293 if sMap not in g_dInstructionMaps:
4294 return self.errorComment(iTagLine, '%s: invalid map value: %s (valid values: %s)'
4295 % (sTag, sMap, ', '.join(g_dInstructionMaps.keys()),));
4296
4297 # Add the maps to the current list. Throw errors on duplicates.
4298 for oMap in oInstr.aoMaps:
4299 if oMap.sName in asMaps:
4300 return self.errorComment(iTagLine, '%s: duplicate map assignment: %s' % (sTag, oMap.sName));
4301
4302 for sMap in asMaps:
4303 oMap = g_dInstructionMaps[sMap];
4304 if oMap not in oInstr.aoMaps:
4305 oInstr.aoMaps.append(oMap);
4306 else:
4307 self.errorComment(iTagLine, '%s: duplicate map assignment (input): %s' % (sTag, sMap));
4308
4309 _ = iEndLine;
4310 return True;
4311
4312 def parseTagOpPfx(self, sTag, aasSections, iTagLine, iEndLine):
4313 """
4314 Tag: @oppfx
4315 Value: n/a|none|0x66|0xf3|0xf2|!0xf3
4316
4317 Required prefix for the instruction. (In a (E)VEX context this is the
4318 value of the 'pp' field rather than an actual prefix.)
4319 """
4320 oInstr = self.ensureInstructionForOpTag(iTagLine);
4321
4322 # Flatten and validate the value.
4323 sFlattened = self.flattenAllSections(aasSections);
4324 asPrefixes = sFlattened.split();
4325 if len(asPrefixes) > 1:
4326 return self.errorComment(iTagLine, '%s: max one prefix: %s' % (sTag, asPrefixes,));
4327
4328 sPrefix = asPrefixes[0].lower();
4329 if sPrefix == 'none':
4330 sPrefix = 'none';
4331 elif sPrefix == 'n/a':
4332 sPrefix = None;
4333 else:
4334 if len(sPrefix) == 2:
4335 sPrefix = '0x' + sPrefix;
4336 if not _isValidOpcodeByte(sPrefix):
4337 if sPrefix != '!0xf3':
4338 return self.errorComment(iTagLine, '%s: invalid prefix: %s' % (sTag, sPrefix,));
4339
4340 if sPrefix is not None and sPrefix not in g_kdPrefixes:
4341 return self.errorComment(iTagLine, '%s: invalid prefix: %s (valid %s)' % (sTag, sPrefix, g_kdPrefixes,));
4342
4343 # Set it.
4344 if oInstr.sPrefix is not None:
4345 return self.errorComment(iTagLine, '%s: attempting to overwrite "%s" with "%s"' % ( sTag, oInstr.sPrefix, sPrefix,));
4346 oInstr.sPrefix = sPrefix;
4347
4348 _ = iEndLine;
4349 return True;
4350
4351 def parseTagOpcode(self, sTag, aasSections, iTagLine, iEndLine):
4352 """
4353 Tag: @opcode
4354 Value: 0x?? | /reg (TODO: | mr/reg | 11 /reg | !11 /reg | 11 mr/reg | !11 mr/reg)
4355
4356 The opcode byte or sub-byte for the instruction in the context of a map.
4357 """
4358 oInstr = self.ensureInstructionForOpTag(iTagLine);
4359
4360 # Flatten and validate the value.
4361 sOpcode = self.flattenAllSections(aasSections);
4362 if _isValidOpcodeByte(sOpcode):
4363 pass;
4364 elif len(sOpcode) == 2 and sOpcode.startswith('/') and sOpcode[-1] in '012345678':
4365 pass;
4366 elif len(sOpcode) == 4 and sOpcode.startswith('11/') and sOpcode[-1] in '012345678':
4367 pass;
4368 elif len(sOpcode) == 5 and sOpcode.startswith('!11/') and sOpcode[-1] in '012345678':
4369 pass;
4370 else:
4371 return self.errorComment(iTagLine, '%s: invalid opcode: %s' % (sTag, sOpcode,));
4372
4373 # Set it.
4374 if oInstr.sOpcode is not None:
4375 return self.errorComment(iTagLine, '%s: attempting to overwrite "%s" with "%s"' % ( sTag, oInstr.sOpcode, sOpcode,));
4376 oInstr.sOpcode = sOpcode;
4377
4378 _ = iEndLine;
4379 return True;
4380
4381 def parseTagOpcodeSub(self, sTag, aasSections, iTagLine, iEndLine):
4382 """
4383 Tag: @opcodesub
4384 Value: none | 11 mr/reg | !11 mr/reg | rex.w=0 | rex.w=1 | vex.l=0 | vex.l=1
4385 | 11 mr/reg vex.l=0 | 11 mr/reg vex.l=1 | !11 mr/reg vex.l=0 | !11 mr/reg vex.l=1
4386 | !11 rex.w=0 | !11 mr/reg rex.w=0
4387 | !11 rex.w=1 | !11 mr/reg rex.w=1
4388
4389 This is a simple way of dealing with encodings where the mod=3 and mod!=3
4390 represents exactly two different instructions. The more proper way would
4391 be to go via maps with two members, but this is faster.
4392 """
4393 oInstr = self.ensureInstructionForOpTag(iTagLine);
4394
4395 # Flatten and validate the value.
4396 sSubOpcode = self.flattenAllSections(aasSections);
4397 if sSubOpcode not in g_kdSubOpcodes:
4398 return self.errorComment(iTagLine, '%s: invalid sub opcode: %s (valid: %s)'
4399 % (sTag, sSubOpcode, ', '.join(sorted(g_kdSubOpcodes.keys())),));
4400 sSubOpcode = g_kdSubOpcodes[sSubOpcode][0];
4401
4402 # Set it.
4403 if oInstr.sSubOpcode is not None:
4404 return self.errorComment(iTagLine, '%s: attempting to overwrite "%s" with "%s"'
4405 % ( sTag, oInstr.sSubOpcode, sSubOpcode,));
4406 oInstr.sSubOpcode = sSubOpcode;
4407
4408 _ = iEndLine;
4409 return True;
4410
4411 def parseTagOpEnc(self, sTag, aasSections, iTagLine, iEndLine):
4412 """
4413 Tag: @openc
4414 Value: ModR/M|fixed|prefix|<map name>
4415
4416 The instruction operand encoding style.
4417 """
4418 oInstr = self.ensureInstructionForOpTag(iTagLine);
4419
4420 # Flatten and validate the value.
4421 sEncoding = self.flattenAllSections(aasSections);
4422 if sEncoding in g_kdEncodings:
4423 pass;
4424 elif sEncoding in g_dInstructionMaps:
4425 pass;
4426 elif not _isValidOpcodeByte(sEncoding):
4427 return self.errorComment(iTagLine, '%s: invalid encoding: %s' % (sTag, sEncoding,));
4428
4429 # Set it.
4430 if oInstr.sEncoding is not None:
4431 return self.errorComment(iTagLine, '%s: attempting to overwrite "%s" with "%s"'
4432 % ( sTag, oInstr.sEncoding, sEncoding,));
4433 oInstr.sEncoding = sEncoding;
4434
4435 _ = iEndLine;
4436 return True;
4437
4438 ## EFlags tag to Instruction attribute name.
4439 kdOpFlagToAttr = {
4440 '@opfltest': 'asFlTest',
4441 '@opflmodify': 'asFlModify',
4442 '@opflundef': 'asFlUndefined',
4443 '@opflset': 'asFlSet',
4444 '@opflclear': 'asFlClear',
4445 };
4446
4447 def parseTagOpEFlags(self, sTag, aasSections, iTagLine, iEndLine):
4448 """
4449 Tags: @opfltest, @opflmodify, @opflundef, @opflset, @opflclear
4450 Value: <eflags specifier>
4451
4452 """
4453 oInstr = self.ensureInstructionForOpTag(iTagLine);
4454
4455 # Flatten, split up and validate the values.
4456 asFlags = self.flattenAllSections(aasSections, sLineSep = ',', sSectionSep = ',').split(',');
4457 if len(asFlags) == 1 and asFlags[0].lower() == 'none':
4458 asFlags = [];
4459 else:
4460 fRc = True;
4461 for iFlag, sFlag in enumerate(asFlags):
4462 if sFlag not in g_kdEFlagsMnemonics:
4463 if sFlag.strip() in g_kdEFlagsMnemonics:
4464 asFlags[iFlag] = sFlag.strip();
4465 else:
4466 fRc = self.errorComment(iTagLine, '%s: invalid EFLAGS value: %s' % (sTag, sFlag,));
4467 if not fRc:
4468 return False;
4469
4470 # Set them.
4471 asOld = getattr(oInstr, self.kdOpFlagToAttr[sTag]);
4472 if asOld is not None and len(asOld) > 0:
4473 return self.errorComment(iTagLine, '%s: attempting to overwrite "%s" with "%s"' % ( sTag, asOld, asFlags,));
4474 setattr(oInstr, self.kdOpFlagToAttr[sTag], asFlags);
4475
4476 _ = iEndLine;
4477 return True;
4478
4479 ## EFLAGS class definitions with their attribute lists.
4480 kdEFlagsClasses = {
4481 'arithmetic': { # add, sub, ...
4482 'asFlTest': [],
4483 'asFlModify': [ 'cf', 'pf', 'af', 'zf', 'sf', 'of', ],
4484 'asFlClear': [],
4485 'asFlSet': [],
4486 'asFlUndefined': [],
4487 },
4488 'arithmetic_carry': { # adc, sbb, ...
4489 'asFlTest': [ 'cf', ],
4490 'asFlModify': [ 'cf', 'pf', 'af', 'zf', 'sf', 'of', ],
4491 'asFlClear': [],
4492 'asFlSet': [],
4493 'asFlUndefined': [],
4494 },
4495 'incdec': {
4496 'asFlTest': [],
4497 'asFlModify': [ 'pf', 'af', 'zf', 'sf', 'of', ], # leaves CF alone
4498 'asFlClear': [],
4499 'asFlSet': [],
4500 'asFlUndefined': [],
4501 },
4502 'division': { ## @todo specify intel/amd differences...
4503 'asFlTest': [ 'pf', 'af', 'zf', 'sf', ], # Intel leaves all flags unchanged.
4504 'asFlModify': [ 'pf', 'af', 'zf', 'sf', ], # While AMD sets AF and clears PF, ZF & SF, leaving CF and OF alone.
4505 'asFlClear': [],
4506 'asFlSet': [],
4507 'asFlUndefined': [ 'cf', 'pf', 'af', 'zf', 'sf', 'of', ],
4508 },
4509 'multiply': { ## @todo specify intel/amd differences...
4510 'asFlTest': [ 'pf', 'af', 'zf', 'sf', ], # AMD leaves these unchanged, so we have to delcare them as inputs.
4511 'asFlModify': [ 'cf', 'pf', 'af', 'zf', 'sf', 'of' ], # Intel always modifies all flags, but how differs
4512 'asFlClear': [], # between IMUL and MUL.
4513 'asFlSet': [],
4514 'asFlUndefined': [ 'pf', 'af', 'zf', 'sf', ],
4515 },
4516 'logical': { # and, or, xor, ...
4517 'asFlTest': [],
4518 'asFlModify': [ 'cf', 'pf', 'af', 'zf', 'sf', 'of', ],
4519 'asFlClear': [ 'cf', 'af', 'of', ], # 'af' is undefined, but tstIEMAImpl indicates that it is cleared.
4520 'asFlSet': [],
4521 'asFlUndefined': [ 'af', ],
4522 },
4523 'rotate_1': { # rol and ror with fixed 1 shift count
4524 'asFlTest': [],
4525 'asFlModify': [ 'cf', 'of', ],
4526 'asFlClear': [],
4527 'asFlSet': [],
4528 'asFlUndefined': [],
4529 },
4530 'rotate_count': { # rol and ror w/o fixed 1 shift count
4531 'asFlTest': [ 'cf', 'of', ], # If the count is zero, nothing changes.
4532 'asFlModify': [ 'cf', 'of', ],
4533 'asFlClear': [],
4534 'asFlSet': [],
4535 'asFlUndefined': [ 'of', ],
4536 },
4537 'rotate_carry_1': { # rcl and rcr with fixed 1 shift count
4538 'asFlTest': [ 'cf', ],
4539 'asFlModify': [ 'cf', 'of', ],
4540 'asFlClear': [],
4541 'asFlSet': [],
4542 'asFlUndefined': [],
4543 },
4544 'rotate_carry_count': { # rcl and rcr w/o fixed 1 shift count
4545 'asFlTest': [ 'cf', 'of', ], # If the count is zero, nothing changes, so 'of' is also input.
4546 'asFlModify': [ 'cf', 'of', ],
4547 'asFlClear': [],
4548 'asFlSet': [],
4549 'asFlUndefined': [ 'of', ],
4550 },
4551 'shift_1': { # shl, shr or sar with fixed 1 count.
4552 'asFlTest': [],
4553 'asFlModify': [ 'cf', 'pf', 'af', 'zf', 'sf', 'of', ],
4554 'asFlClear': [],
4555 'asFlSet': [],
4556 'asFlUndefined': [ 'af', ],
4557 },
4558 'shift_count': { # shl, shr or sar w/o fixed 1 shift count
4559 'asFlTest': [ 'cf', 'pf', 'af', 'zf', 'sf', 'of', ], # If the count is zero, nothing is changed.
4560 'asFlModify': [ 'cf', 'pf', 'af', 'zf', 'sf', 'of', ],
4561 'asFlClear': [],
4562 'asFlSet': [],
4563 'asFlUndefined': [ 'af', 'of', ],
4564 },
4565 'bitmap': { # bt, btc, btr, btc
4566 'asFlTest': [],
4567 'asFlModify': [ 'cf', ],
4568 'asFlClear': [],
4569 'asFlSet': [],
4570 'asFlUndefined': [ 'pf', 'af', 'zf', 'sf', 'of', ], # tstIEMAImpl indicates that they aren't modified.
4571 },
4572 'unchanged': {
4573 'asFlTest': [],
4574 'asFlModify': [],
4575 'asFlClear': [],
4576 'asFlSet': [],
4577 'asFlUndefined': [],
4578 },
4579 };
4580 def parseTagOpEFlagsClass(self, sTag, aasSections, iTagLine, iEndLine):
4581 """
4582 Tags: @opflclass
4583 Value: arithmetic, logical, ...
4584
4585 """
4586 oInstr = self.ensureInstructionForOpTag(iTagLine);
4587
4588 # Flatten and validate the value.
4589 sClass = self.flattenAllSections(aasSections);
4590 kdAttribs = self.kdEFlagsClasses.get(sClass);
4591 if not kdAttribs:
4592 return self.errorComment(iTagLine, '%s: Unknown EFLAGS class: %s (valid: %s)'
4593 % (sTag, sClass, ', '.join(sorted(self.kdEFlagsClasses.keys())),));
4594
4595 # Set the attributes.
4596 for sAttrib, asFlags in kdAttribs.items():
4597 asOld = getattr(oInstr, sAttrib);
4598 if asOld is not None:
4599 return self.errorComment(iTagLine, '%s: attempting to overwrite "%s" with "%s" for %s'
4600 % (sTag, asOld, asFlags, sAttrib));
4601 setattr(oInstr, sAttrib, asFlags);
4602
4603 _ = iEndLine;
4604 return True;
4605
4606 def parseTagOpHints(self, sTag, aasSections, iTagLine, iEndLine):
4607 """
4608 Tag: @ophints
4609 Value: Comma or space separated list of flags and hints.
4610
4611 This covers the disassembler flags table and more.
4612 """
4613 oInstr = self.ensureInstructionForOpTag(iTagLine);
4614
4615 # Flatten as a space separated list, split it up and validate the values.
4616 asHints = self.flattenAllSections(aasSections, sLineSep = ' ', sSectionSep = ' ').replace(',', ' ').split();
4617 if len(asHints) == 1 and asHints[0].lower() == 'none':
4618 asHints = [];
4619 else:
4620 fRc = True;
4621 for iHint, sHint in enumerate(asHints):
4622 if sHint not in g_kdHints:
4623 if sHint.strip() in g_kdHints:
4624 sHint[iHint] = sHint.strip();
4625 else:
4626 fRc = self.errorComment(iTagLine, '%s: invalid hint value: %s' % (sTag, sHint,));
4627 if not fRc:
4628 return False;
4629
4630 # Append them.
4631 for sHint in asHints:
4632 if sHint not in oInstr.dHints:
4633 oInstr.dHints[sHint] = True; # (dummy value, using dictionary for speed)
4634 else:
4635 self.errorComment(iTagLine, '%s: duplicate hint: %s' % ( sTag, sHint,));
4636
4637 _ = iEndLine;
4638 return True;
4639
4640 def parseTagOpDisEnum(self, sTag, aasSections, iTagLine, iEndLine):
4641 """
4642 Tag: @opdisenum
4643 Value: OP_XXXX
4644
4645 This is for select a specific (legacy) disassembler enum value for the
4646 instruction.
4647 """
4648 oInstr = self.ensureInstructionForOpTag(iTagLine);
4649
4650 # Flatten and split.
4651 asWords = self.flattenAllSections(aasSections).split();
4652 if len(asWords) != 1:
4653 self.errorComment(iTagLine, '%s: expected exactly one value: %s' % (sTag, asWords,));
4654 if not asWords:
4655 return False;
4656 sDisEnum = asWords[0];
4657 if not self.oReDisEnum.match(sDisEnum):
4658 return self.errorComment(iTagLine, '%s: invalid disassembler OP_XXXX enum: %s (pattern: %s)'
4659 % (sTag, sDisEnum, self.oReDisEnum.pattern));
4660
4661 # Set it.
4662 if oInstr.sDisEnum is not None:
4663 return self.errorComment(iTagLine, '%s: attempting to overwrite "%s" with "%s"' % (sTag, oInstr.sDisEnum, sDisEnum,));
4664 oInstr.sDisEnum = sDisEnum;
4665
4666 _ = iEndLine;
4667 return True;
4668
4669 def parseTagOpMinCpu(self, sTag, aasSections, iTagLine, iEndLine):
4670 """
4671 Tag: @opmincpu
4672 Value: <simple CPU name>
4673
4674 Indicates when this instruction was introduced.
4675 """
4676 oInstr = self.ensureInstructionForOpTag(iTagLine);
4677
4678 # Flatten the value, split into words, make sure there's just one, valid it.
4679 asCpus = self.flattenAllSections(aasSections).split();
4680 if len(asCpus) > 1:
4681 self.errorComment(iTagLine, '%s: exactly one CPU name, please: %s' % (sTag, ' '.join(asCpus),));
4682
4683 sMinCpu = asCpus[0];
4684 if sMinCpu in g_kdCpuNames:
4685 oInstr.sMinCpu = sMinCpu;
4686 else:
4687 return self.errorComment(iTagLine, '%s: invalid CPU name: %s (names: %s)'
4688 % (sTag, sMinCpu, ','.join(sorted(g_kdCpuNames)),));
4689
4690 # Set it.
4691 if oInstr.sMinCpu is None:
4692 oInstr.sMinCpu = sMinCpu;
4693 elif oInstr.sMinCpu != sMinCpu:
4694 self.errorComment(iTagLine, '%s: attemting to overwrite "%s" with "%s"' % (sTag, oInstr.sMinCpu, sMinCpu,));
4695
4696 _ = iEndLine;
4697 return True;
4698
4699 def parseTagOpCpuId(self, sTag, aasSections, iTagLine, iEndLine):
4700 """
4701 Tag: @opcpuid
4702 Value: none | <CPUID flag specifier>
4703
4704 CPUID feature bit which is required for the instruction to be present.
4705 """
4706 oInstr = self.ensureInstructionForOpTag(iTagLine);
4707
4708 # Flatten as a space separated list, split it up and validate the values.
4709 asCpuIds = self.flattenAllSections(aasSections, sLineSep = ' ', sSectionSep = ' ').replace(',', ' ').split();
4710 if len(asCpuIds) == 1 and asCpuIds[0].lower() == 'none':
4711 asCpuIds = [];
4712 else:
4713 fRc = True;
4714 for iCpuId, sCpuId in enumerate(asCpuIds):
4715 if sCpuId not in g_kdCpuIdFlags:
4716 if sCpuId.strip() in g_kdCpuIdFlags:
4717 sCpuId[iCpuId] = sCpuId.strip();
4718 else:
4719 fRc = self.errorComment(iTagLine, '%s: invalid CPUID value: %s' % (sTag, sCpuId,));
4720 if not fRc:
4721 return False;
4722
4723 # Append them.
4724 for sCpuId in asCpuIds:
4725 if sCpuId not in oInstr.asCpuIds:
4726 oInstr.asCpuIds.append(sCpuId);
4727 else:
4728 self.errorComment(iTagLine, '%s: duplicate CPUID: %s' % ( sTag, sCpuId,));
4729
4730 _ = iEndLine;
4731 return True;
4732
4733 def parseTagOpGroup(self, sTag, aasSections, iTagLine, iEndLine):
4734 """
4735 Tag: @opgroup
4736 Value: op_grp1[_subgrp2[_subsubgrp3]]
4737
4738 Instruction grouping.
4739 """
4740 oInstr = self.ensureInstructionForOpTag(iTagLine);
4741
4742 # Flatten as a space separated list, split it up and validate the values.
4743 asGroups = self.flattenAllSections(aasSections).split();
4744 if len(asGroups) != 1:
4745 return self.errorComment(iTagLine, '%s: exactly one group, please: %s' % (sTag, asGroups,));
4746 sGroup = asGroups[0];
4747 if not self.oReGroupName.match(sGroup):
4748 return self.errorComment(iTagLine, '%s: invalid group name: %s (valid: %s)'
4749 % (sTag, sGroup, self.oReGroupName.pattern));
4750
4751 # Set it.
4752 if oInstr.sGroup is not None:
4753 return self.errorComment(iTagLine, '%s: attempting to overwrite "%s" with "%s"' % ( sTag, oInstr.sGroup, sGroup,));
4754 oInstr.sGroup = sGroup;
4755
4756 _ = iEndLine;
4757 return True;
4758
4759 def parseTagOpUnusedInvalid(self, sTag, aasSections, iTagLine, iEndLine):
4760 """
4761 Tag: @opunused, @opinvalid, @opinvlstyle
4762 Value: <invalid opcode behaviour style>
4763
4764 The @opunused indicates the specification is for a currently unused
4765 instruction encoding.
4766
4767 The @opinvalid indicates the specification is for an invalid currently
4768 instruction encoding (like UD2).
4769
4770 The @opinvlstyle just indicates how CPUs decode the instruction when
4771 not supported (@opcpuid, @opmincpu) or disabled.
4772 """
4773 oInstr = self.ensureInstructionForOpTag(iTagLine);
4774
4775 # Flatten as a space separated list, split it up and validate the values.
4776 asStyles = self.flattenAllSections(aasSections).split();
4777 if len(asStyles) != 1:
4778 return self.errorComment(iTagLine, '%s: exactly one invalid behviour style, please: %s' % (sTag, asStyles,));
4779 sStyle = asStyles[0];
4780 if sStyle not in g_kdInvalidStyles:
4781 return self.errorComment(iTagLine, '%s: invalid invalid behaviour style: %s (valid: %s)'
4782 % (sTag, sStyle, g_kdInvalidStyles.keys(),));
4783 # Set it.
4784 if oInstr.sInvalidStyle is not None:
4785 return self.errorComment(iTagLine,
4786 '%s: attempting to overwrite "%s" with "%s" (only one @opunused, @opinvalid, @opinvlstyle)'
4787 % ( sTag, oInstr.sInvalidStyle, sStyle,));
4788 oInstr.sInvalidStyle = sStyle;
4789 if sTag == '@opunused':
4790 oInstr.fUnused = True;
4791 elif sTag == '@opinvalid':
4792 oInstr.fInvalid = True;
4793
4794 _ = iEndLine;
4795 return True;
4796
4797 def parseTagOpTest(self, sTag, aasSections, iTagLine, iEndLine): # pylint: disable=too-many-locals
4798 """
4799 Tag: @optest
4800 Value: [<selectors>[ ]?] <inputs> -> <outputs>
4801 Example: mode==64bit / in1=0xfffffffe:dw in2=1:dw -> out1=0xffffffff:dw outfl=a?,p?
4802
4803 The main idea here is to generate basic instruction tests.
4804
4805 The probably simplest way of handling the diverse input, would be to use
4806 it to produce size optimized byte code for a simple interpreter that
4807 modifies the register input and output states.
4808
4809 An alternative to the interpreter would be creating multiple tables,
4810 but that becomes rather complicated wrt what goes where and then to use
4811 them in an efficient manner.
4812 """
4813 oInstr = self.ensureInstructionForOpTag(iTagLine);
4814
4815 #
4816 # Do it section by section.
4817 #
4818 for asSectionLines in aasSections:
4819 #
4820 # Sort the input into outputs, inputs and selector conditions.
4821 #
4822 sFlatSection = self.flattenAllSections([asSectionLines,]);
4823 if not sFlatSection:
4824 self.errorComment(iTagLine, '%s: missing value (dbg: aasSections=%s)' % ( sTag, aasSections));
4825 continue;
4826 oTest = InstructionTest(oInstr);
4827
4828 asSelectors = [];
4829 asInputs = [];
4830 asOutputs = [];
4831 asCur = asOutputs;
4832 fRc = True;
4833 asWords = sFlatSection.split();
4834 for iWord in range(len(asWords) - 1, -1, -1):
4835 sWord = asWords[iWord];
4836 # Check for array switchers.
4837 if sWord == '->':
4838 if asCur != asOutputs:
4839 fRc = self.errorComment(iTagLine, '%s: "->" shall only occure once: %s' % (sTag, sFlatSection,));
4840 break;
4841 asCur = asInputs;
4842 elif sWord == '/':
4843 if asCur != asInputs:
4844 fRc = self.errorComment(iTagLine, '%s: "/" shall only occure once: %s' % (sTag, sFlatSection,));
4845 break;
4846 asCur = asSelectors;
4847 else:
4848 asCur.insert(0, sWord);
4849
4850 #
4851 # Validate and add selectors.
4852 #
4853 for sCond in asSelectors:
4854 sCondExp = TestSelector.kdPredicates.get(sCond, sCond);
4855 oSelector = None;
4856 for sOp in TestSelector.kasCompareOps:
4857 off = sCondExp.find(sOp);
4858 if off >= 0:
4859 sVariable = sCondExp[:off];
4860 sValue = sCondExp[off + len(sOp):];
4861 if sVariable in TestSelector.kdVariables:
4862 if sValue in TestSelector.kdVariables[sVariable]:
4863 oSelector = TestSelector(sVariable, sOp, sValue);
4864 else:
4865 self.errorComment(iTagLine, '%s: invalid condition value "%s" in "%s" (valid: %s)'
4866 % ( sTag, sValue, sCond,
4867 TestSelector.kdVariables[sVariable].keys(),));
4868 else:
4869 self.errorComment(iTagLine, '%s: invalid condition variable "%s" in "%s" (valid: %s)'
4870 % ( sTag, sVariable, sCond, TestSelector.kdVariables.keys(),));
4871 break;
4872 if oSelector is not None:
4873 for oExisting in oTest.aoSelectors:
4874 if oExisting.sVariable == oSelector.sVariable:
4875 self.errorComment(iTagLine, '%s: already have a selector for variable "%s" (existing: %s, new: %s)'
4876 % ( sTag, oSelector.sVariable, oExisting, oSelector,));
4877 oTest.aoSelectors.append(oSelector);
4878 else:
4879 fRc = self.errorComment(iTagLine, '%s: failed to parse selector: %s' % ( sTag, sCond,));
4880
4881 #
4882 # Validate outputs and inputs, adding them to the test as we go along.
4883 #
4884 for asItems, sDesc, aoDst in [ (asInputs, 'input', oTest.aoInputs), (asOutputs, 'output', oTest.aoOutputs)]:
4885 asValidFieldKinds = [ 'both', sDesc, ];
4886 for sItem in asItems:
4887 oItem = None;
4888 for sOp in TestInOut.kasOperators:
4889 off = sItem.find(sOp);
4890 if off < 0:
4891 continue;
4892 sField = sItem[:off];
4893 sValueType = sItem[off + len(sOp):];
4894 if sField in TestInOut.kdFields \
4895 and TestInOut.kdFields[sField][1] in asValidFieldKinds:
4896 asSplit = sValueType.split(':', 1);
4897 sValue = asSplit[0];
4898 sType = asSplit[1] if len(asSplit) > 1 else TestInOut.kdFields[sField][0];
4899 if sType in TestInOut.kdTypes:
4900 oValid = TestInOut.kdTypes[sType].validate(sValue);
4901 if oValid is True:
4902 if not TestInOut.kdTypes[sType].isAndOrPair(sValue) or sOp == '&|=':
4903 oItem = TestInOut(sField, sOp, sValue, sType);
4904 else:
4905 self.errorComment(iTagLine, '%s: and-or %s value "%s" can only be used with "&|="'
4906 % ( sTag, sDesc, sItem, ));
4907 else:
4908 self.errorComment(iTagLine, '%s: invalid %s value "%s" in "%s" (type: %s): %s'
4909 % ( sTag, sDesc, sValue, sItem, sType, oValid, ));
4910 else:
4911 self.errorComment(iTagLine, '%s: invalid %s type "%s" in "%s" (valid types: %s)'
4912 % ( sTag, sDesc, sType, sItem, TestInOut.kdTypes.keys(),));
4913 else:
4914 self.errorComment(iTagLine, '%s: invalid %s field "%s" in "%s"\nvalid fields: %s'
4915 % ( sTag, sDesc, sField, sItem,
4916 ', '.join([sKey for sKey, asVal in TestInOut.kdFields.items()
4917 if asVal[1] in asValidFieldKinds]),));
4918 break;
4919 if oItem is not None:
4920 for oExisting in aoDst:
4921 if oExisting.sField == oItem.sField and oExisting.sOp == oItem.sOp:
4922 self.errorComment(iTagLine,
4923 '%s: already have a "%s" assignment for field "%s" (existing: %s, new: %s)'
4924 % ( sTag, oItem.sOp, oItem.sField, oExisting, oItem,));
4925 aoDst.append(oItem);
4926 else:
4927 fRc = self.errorComment(iTagLine, '%s: failed to parse assignment: %s' % ( sTag, sItem,));
4928
4929 #
4930 # .
4931 #
4932 if fRc:
4933 oInstr.aoTests.append(oTest);
4934 else:
4935 self.errorComment(iTagLine, '%s: failed to parse test: %s' % (sTag, ' '.join(asWords),));
4936 self.errorComment(iTagLine, '%s: asSelectors=%s / asInputs=%s -> asOutputs=%s'
4937 % (sTag, asSelectors, asInputs, asOutputs,));
4938
4939 _ = iEndLine;
4940 return True;
4941
4942 def parseTagOpTestNum(self, sTag, aasSections, iTagLine, iEndLine):
4943 """
4944 Numbered @optest tag. Either @optest42 or @optest[42].
4945 """
4946 oInstr = self.ensureInstructionForOpTag(iTagLine);
4947
4948 iTest = 0;
4949 if sTag[-1] == ']':
4950 iTest = int(sTag[8:-1]);
4951 else:
4952 iTest = int(sTag[7:]);
4953
4954 if iTest != len(oInstr.aoTests):
4955 self.errorComment(iTagLine, '%s: incorrect test number: %u, actual %u' % (sTag, iTest, len(oInstr.aoTests),));
4956 return self.parseTagOpTest(sTag, aasSections, iTagLine, iEndLine);
4957
4958 def parseTagOpTestIgnore(self, sTag, aasSections, iTagLine, iEndLine):
4959 """
4960 Tag: @optestign | @optestignore
4961 Value: <value is ignored>
4962
4963 This is a simple trick to ignore a test while debugging another.
4964
4965 See also @oponlytest.
4966 """
4967 _ = sTag; _ = aasSections; _ = iTagLine; _ = iEndLine;
4968 return True;
4969
4970 def parseTagOpCopyTests(self, sTag, aasSections, iTagLine, iEndLine):
4971 """
4972 Tag: @opcopytests
4973 Value: <opstat | function> [..]
4974 Example: @opcopytests add_Eb_Gb
4975
4976 Trick to avoid duplicating tests for different encodings of the same
4977 operation.
4978 """
4979 oInstr = self.ensureInstructionForOpTag(iTagLine);
4980
4981 # Flatten, validate and append the copy job to the instruction. We execute
4982 # them after parsing all the input so we can handle forward references.
4983 asToCopy = self.flattenAllSections(aasSections).split();
4984 if not asToCopy:
4985 return self.errorComment(iTagLine, '%s: requires at least on reference value' % (sTag,));
4986 for sToCopy in asToCopy:
4987 if sToCopy not in oInstr.asCopyTests:
4988 if self.oReStatsName.match(sToCopy) or self.oReFunctionName.match(sToCopy):
4989 oInstr.asCopyTests.append(sToCopy);
4990 else:
4991 self.errorComment(iTagLine, '%s: invalid instruction reference (opstat or function) "%s" (valid: %s or %s)'
4992 % (sTag, sToCopy, self.oReStatsName.pattern, self.oReFunctionName.pattern));
4993 else:
4994 self.errorComment(iTagLine, '%s: ignoring duplicate "%s"' % (sTag, sToCopy,));
4995
4996 _ = iEndLine;
4997 return True;
4998
4999 def parseTagOpOnlyTest(self, sTag, aasSections, iTagLine, iEndLine):
5000 """
5001 Tag: @oponlytest | @oponly
5002 Value: none
5003
5004 Only test instructions with this tag. This is a trick that is handy
5005 for singling out one or two new instructions or tests.
5006
5007 See also @optestignore.
5008 """
5009 oInstr = self.ensureInstructionForOpTag(iTagLine);
5010
5011 # Validate and add instruction to only test dictionary.
5012 sValue = self.flattenAllSections(aasSections).strip();
5013 if sValue:
5014 return self.errorComment(iTagLine, '%s: does not take any value: %s' % (sTag, sValue));
5015
5016 if oInstr not in g_aoOnlyTestInstructions:
5017 g_aoOnlyTestInstructions.append(oInstr);
5018
5019 _ = iEndLine;
5020 return True;
5021
5022 def parseTagOpXcptType(self, sTag, aasSections, iTagLine, iEndLine):
5023 """
5024 Tag: @opxcpttype
5025 Value: [none|1|2|3|4|4UA|5|6|7|8|11|12|E1|E1NF|E2|E3|E3NF|E4|E4NF|E5|E5NF|E6|E6NF|E7NF|E9|E9NF|E10|E11|E12|E12NF]
5026
5027 Sets the SSE or AVX exception type (see SDMv2 2.4, 2.7).
5028 """
5029 oInstr = self.ensureInstructionForOpTag(iTagLine);
5030
5031 # Flatten as a space separated list, split it up and validate the values.
5032 asTypes = self.flattenAllSections(aasSections).split();
5033 if len(asTypes) != 1:
5034 return self.errorComment(iTagLine, '%s: exactly one invalid exception type, please: %s' % (sTag, asTypes,));
5035 sType = asTypes[0];
5036 if sType not in g_kdXcptTypes:
5037 return self.errorComment(iTagLine, '%s: invalid invalid exception type: %s (valid: %s)'
5038 % (sTag, sType, sorted(g_kdXcptTypes.keys()),));
5039 # Set it.
5040 if oInstr.sXcptType is not None:
5041 return self.errorComment(iTagLine,
5042 '%s: attempting to overwrite "%s" with "%s" (only one @opxcpttype)'
5043 % ( sTag, oInstr.sXcptType, sType,));
5044 oInstr.sXcptType = sType;
5045
5046 _ = iEndLine;
5047 return True;
5048
5049 def parseTagOpFunction(self, sTag, aasSections, iTagLine, iEndLine):
5050 """
5051 Tag: @opfunction
5052 Value: <VMM function name>
5053
5054 This is for explicitly setting the IEM function name. Normally we pick
5055 this up from the FNIEMOP_XXX macro invocation after the description, or
5056 generate it from the mnemonic and operands.
5057
5058 It it thought it maybe necessary to set it when specifying instructions
5059 which implementation isn't following immediately or aren't implemented yet.
5060 """
5061 oInstr = self.ensureInstructionForOpTag(iTagLine);
5062
5063 # Flatten and validate the value.
5064 sFunction = self.flattenAllSections(aasSections);
5065 if not self.oReFunctionName.match(sFunction):
5066 return self.errorComment(iTagLine, '%s: invalid VMM function name: "%s" (valid: %s)'
5067 % (sTag, sFunction, self.oReFunctionName.pattern));
5068
5069 if oInstr.sFunction is not None:
5070 return self.errorComment(iTagLine, '%s: attempting to overwrite VMM function name "%s" with "%s"'
5071 % (sTag, oInstr.sFunction, sFunction,));
5072 oInstr.sFunction = sFunction;
5073
5074 _ = iEndLine;
5075 return True;
5076
5077 def parseTagOpStats(self, sTag, aasSections, iTagLine, iEndLine):
5078 """
5079 Tag: @opstats
5080 Value: <VMM statistics base name>
5081
5082 This is for explicitly setting the statistics name. Normally we pick
5083 this up from the IEMOP_MNEMONIC macro invocation, or generate it from
5084 the mnemonic and operands.
5085
5086 It it thought it maybe necessary to set it when specifying instructions
5087 which implementation isn't following immediately or aren't implemented yet.
5088 """
5089 oInstr = self.ensureInstructionForOpTag(iTagLine);
5090
5091 # Flatten and validate the value.
5092 sStats = self.flattenAllSections(aasSections);
5093 if not self.oReStatsName.match(sStats):
5094 return self.errorComment(iTagLine, '%s: invalid VMM statistics name: "%s" (valid: %s)'
5095 % (sTag, sStats, self.oReStatsName.pattern));
5096
5097 if oInstr.sStats is not None:
5098 return self.errorComment(iTagLine, '%s: attempting to overwrite VMM statistics base name "%s" with "%s"'
5099 % (sTag, oInstr.sStats, sStats,));
5100 oInstr.sStats = sStats;
5101
5102 _ = iEndLine;
5103 return True;
5104
5105 def parseTagOpDone(self, sTag, aasSections, iTagLine, iEndLine):
5106 """
5107 Tag: @opdone
5108 Value: none
5109
5110 Used to explictily flush the instructions that have been specified.
5111 """
5112 sFlattened = self.flattenAllSections(aasSections);
5113 if sFlattened != '':
5114 return self.errorComment(iTagLine, '%s: takes no value, found: "%s"' % (sTag, sFlattened,));
5115 _ = sTag; _ = iEndLine;
5116 return self.doneInstructions();
5117
5118 ## @}
5119
5120
5121 def parseComment(self):
5122 """
5123 Parse the current comment (self.sComment).
5124
5125 If it's a opcode specifiying comment, we reset the macro stuff.
5126 """
5127 #
5128 # Reject if comment doesn't seem to contain anything interesting.
5129 #
5130 if self.sComment.find('Opcode') < 0 \
5131 and self.sComment.find('@') < 0:
5132 return False;
5133
5134 #
5135 # Split the comment into lines, removing leading asterisks and spaces.
5136 # Also remove leading and trailing empty lines.
5137 #
5138 asLines = self.sComment.split('\n');
5139 for iLine, sLine in enumerate(asLines):
5140 asLines[iLine] = sLine.lstrip().lstrip('*').lstrip();
5141
5142 while asLines and not asLines[0]:
5143 self.iCommentLine += 1;
5144 asLines.pop(0);
5145
5146 while asLines and not asLines[-1]:
5147 asLines.pop(len(asLines) - 1);
5148
5149 #
5150 # Check for old style: Opcode 0x0f 0x12
5151 #
5152 if asLines[0].startswith('Opcode '):
5153 self.parseCommentOldOpcode(asLines);
5154
5155 #
5156 # Look for @op* tagged data.
5157 #
5158 cOpTags = 0;
5159 sFlatDefault = None;
5160 sCurTag = '@default';
5161 iCurTagLine = 0;
5162 asCurSection = [];
5163 aasSections = [ asCurSection, ];
5164 for iLine, sLine in enumerate(asLines):
5165 if not sLine.startswith('@'):
5166 if sLine:
5167 asCurSection.append(sLine);
5168 elif asCurSection:
5169 asCurSection = [];
5170 aasSections.append(asCurSection);
5171 else:
5172 #
5173 # Process the previous tag.
5174 #
5175 if not asCurSection and len(aasSections) > 1:
5176 aasSections.pop(-1);
5177 if sCurTag in self.dTagHandlers:
5178 self.dTagHandlers[sCurTag](sCurTag, aasSections, iCurTagLine, iLine);
5179 cOpTags += 1;
5180 elif sCurTag.startswith('@op'):
5181 self.errorComment(iCurTagLine, 'Unknown tag: %s' % (sCurTag));
5182 elif sCurTag == '@default':
5183 sFlatDefault = self.flattenAllSections(aasSections);
5184 elif '@op' + sCurTag[1:] in self.dTagHandlers:
5185 self.errorComment(iCurTagLine, 'Did you mean "@op%s" rather than "%s"?' % (sCurTag[1:], sCurTag));
5186 elif sCurTag in ['@encoding', '@opencoding']:
5187 self.errorComment(iCurTagLine, 'Did you mean "@openc" rather than "%s"?' % (sCurTag,));
5188
5189 #
5190 # New tag.
5191 #
5192 asSplit = sLine.split(None, 1);
5193 sCurTag = asSplit[0].lower();
5194 if len(asSplit) > 1:
5195 asCurSection = [asSplit[1],];
5196 else:
5197 asCurSection = [];
5198 aasSections = [asCurSection, ];
5199 iCurTagLine = iLine;
5200
5201 #
5202 # Process the final tag.
5203 #
5204 if not asCurSection and len(aasSections) > 1:
5205 aasSections.pop(-1);
5206 if sCurTag in self.dTagHandlers:
5207 self.dTagHandlers[sCurTag](sCurTag, aasSections, iCurTagLine, iLine);
5208 cOpTags += 1;
5209 elif sCurTag.startswith('@op'):
5210 self.errorComment(iCurTagLine, 'Unknown tag: %s' % (sCurTag));
5211 elif sCurTag == '@default':
5212 sFlatDefault = self.flattenAllSections(aasSections);
5213
5214 #
5215 # Don't allow default text in blocks containing @op*.
5216 #
5217 if cOpTags > 0 and sFlatDefault:
5218 self.errorComment(0, 'Untagged comment text is not allowed with @op*: %s' % (sFlatDefault,));
5219
5220 return True;
5221
5222 def parseMacroInvocation(self, sInvocation, offStartInvocation = 0):
5223 """
5224 Parses a macro invocation.
5225
5226 Returns three values:
5227 1. A list of macro arguments, where the zero'th is the macro name.
5228 2. The offset following the macro invocation, into sInvocation of
5229 this is on the same line or into the last line if it is on a
5230 different line.
5231 3. Number of additional lines the invocation spans (i.e. zero if
5232 it is all contained within sInvocation).
5233 """
5234 # First the name.
5235 offOpen = sInvocation.find('(', offStartInvocation);
5236 if offOpen <= offStartInvocation:
5237 self.raiseError("macro invocation open parenthesis not found");
5238 sName = sInvocation[offStartInvocation:offOpen].strip();
5239 if not self.oReMacroName.match(sName):
5240 self.raiseError("invalid macro name '%s'" % (sName,));
5241 asRet = [sName, ];
5242
5243 # Arguments.
5244 iLine = self.iLine;
5245 cDepth = 1;
5246 off = offOpen + 1;
5247 offStart = off;
5248 offCurLn = 0;
5249 chQuote = None;
5250 while cDepth > 0:
5251 if off >= len(sInvocation):
5252 if iLine >= len(self.asLines):
5253 self.error('macro invocation beyond end of file');
5254 return (asRet, off - offCurLn, iLine - self.iLine);
5255 offCurLn = off;
5256 sInvocation += self.asLines[iLine];
5257 iLine += 1;
5258 ch = sInvocation[off];
5259
5260 if chQuote:
5261 if ch == '\\' and off + 1 < len(sInvocation):
5262 off += 1;
5263 elif ch == chQuote:
5264 chQuote = None;
5265 elif ch in ('"', '\'',):
5266 chQuote = ch;
5267 elif ch in (',', ')',):
5268 if cDepth == 1:
5269 asRet.append(sInvocation[offStart:off].strip());
5270 offStart = off + 1;
5271 if ch == ')':
5272 cDepth -= 1;
5273 elif ch == '(':
5274 cDepth += 1;
5275 off += 1;
5276
5277 return (asRet, off - offCurLn, iLine - self.iLine);
5278
5279 def findAndParseMacroInvocationEx(self, sCode, sMacro, offStart = 0):
5280 """
5281 Returns (None, len(sCode), 0) if not found, otherwise the
5282 parseMacroInvocation() return value.
5283 """
5284 offHit = sCode.find(sMacro, offStart);
5285 if offHit >= 0 and sCode[offHit + len(sMacro):].strip()[0] == '(':
5286 return self.parseMacroInvocation(sCode, offHit);
5287 return (None, len(sCode), 0);
5288
5289 def findAndParseMacroInvocation(self, sCode, sMacro):
5290 """
5291 Returns None if not found, arguments as per parseMacroInvocation if found.
5292 """
5293 return self.findAndParseMacroInvocationEx(sCode, sMacro)[0];
5294
5295 def findAndParseFirstMacroInvocation(self, sCode, asMacro):
5296 """
5297 Returns same as findAndParseMacroInvocation.
5298 """
5299 for sMacro in asMacro:
5300 asRet = self.findAndParseMacroInvocation(sCode, sMacro);
5301 if asRet is not None:
5302 return asRet;
5303 return None;
5304
5305 def workerIemOpMnemonicEx(self, sMacro, sStats, sAsm, sForm, sUpper, sLower, # pylint: disable=too-many-arguments
5306 sDisHints, sIemHints, asOperands):
5307 """
5308 Processes one of the a IEMOP_MNEMONIC0EX, IEMOP_MNEMONIC1EX, IEMOP_MNEMONIC2EX,
5309 IEMOP_MNEMONIC3EX, and IEMOP_MNEMONIC4EX macros.
5310 """
5311 #
5312 # Some invocation checks.
5313 #
5314 if sUpper != sUpper.upper():
5315 self.error('%s: bad a_Upper parameter: %s' % (sMacro, sUpper,));
5316 if sLower != sLower.lower():
5317 self.error('%s: bad a_Lower parameter: %s' % (sMacro, sLower,));
5318 if sUpper.lower() != sLower:
5319 self.error('%s: a_Upper and a_Lower parameters does not match: %s vs %s' % (sMacro, sUpper, sLower,));
5320 if not self.oReMnemonic.match(sLower):
5321 self.error('%s: invalid a_Lower: %s (valid: %s)' % (sMacro, sLower, self.oReMnemonic.pattern,));
5322
5323 #
5324 # Check if sIemHints tells us to not consider this macro invocation.
5325 #
5326 if sIemHints.find('IEMOPHINT_SKIP_PYTHON') >= 0:
5327 return True;
5328
5329 # Apply to the last instruction only for now.
5330 if not self.aoCurInstrs:
5331 self.addInstruction();
5332 oInstr = self.aoCurInstrs[-1];
5333 if oInstr.iLineMnemonicMacro == -1:
5334 oInstr.iLineMnemonicMacro = self.iLine;
5335 else:
5336 self.error('%s: already saw a IEMOP_MNEMONIC* macro on line %u for this instruction'
5337 % (sMacro, oInstr.iLineMnemonicMacro,));
5338
5339 # Mnemonic
5340 if oInstr.sMnemonic is None:
5341 oInstr.sMnemonic = sLower;
5342 elif oInstr.sMnemonic != sLower:
5343 self.error('%s: current instruction and a_Lower does not match: %s vs %s' % (sMacro, oInstr.sMnemonic, sLower,));
5344
5345 # Process operands.
5346 if len(oInstr.aoOperands) not in [0, len(asOperands)]:
5347 self.error('%s: number of operands given by @opN does not match macro: %s vs %s'
5348 % (sMacro, len(oInstr.aoOperands), len(asOperands),));
5349 for iOperand, sType in enumerate(asOperands):
5350 sWhere = g_kdOpTypes.get(sType, [None, None])[1];
5351 if sWhere is None:
5352 self.error('%s: unknown a_Op%u value: %s' % (sMacro, iOperand + 1, sType));
5353 if iOperand < len(oInstr.aoOperands): # error recovery.
5354 sWhere = oInstr.aoOperands[iOperand].sWhere;
5355 sType = oInstr.aoOperands[iOperand].sType;
5356 else:
5357 sWhere = 'reg';
5358 sType = 'Gb';
5359 if iOperand == len(oInstr.aoOperands):
5360 oInstr.aoOperands.append(Operand(sWhere, sType))
5361 elif oInstr.aoOperands[iOperand].sWhere != sWhere or oInstr.aoOperands[iOperand].sType != sType:
5362 self.error('%s: @op%u and a_Op%u mismatch: %s:%s vs %s:%s'
5363 % (sMacro, iOperand + 1, iOperand + 1, oInstr.aoOperands[iOperand].sWhere,
5364 oInstr.aoOperands[iOperand].sType, sWhere, sType,));
5365
5366 # Encoding.
5367 if sForm not in g_kdIemForms:
5368 self.error('%s: unknown a_Form value: %s' % (sMacro, sForm,));
5369 else:
5370 if oInstr.sEncoding is None:
5371 oInstr.sEncoding = g_kdIemForms[sForm][0];
5372 elif g_kdIemForms[sForm][0] != oInstr.sEncoding:
5373 self.error('%s: current instruction @openc and a_Form does not match: %s vs %s (%s)'
5374 % (sMacro, oInstr.sEncoding, g_kdIemForms[sForm], sForm));
5375
5376 # Check the parameter locations for the encoding.
5377 if g_kdIemForms[sForm][1] is not None:
5378 if len(g_kdIemForms[sForm][1]) > len(oInstr.aoOperands):
5379 self.error('%s: The a_Form=%s has a different operand count: %s (form) vs %s'
5380 % (sMacro, sForm, len(g_kdIemForms[sForm][1]), len(oInstr.aoOperands) ));
5381 else:
5382 for iOperand, sWhere in enumerate(g_kdIemForms[sForm][1]):
5383 if oInstr.aoOperands[iOperand].sWhere != sWhere:
5384 self.error('%s: current instruction @op%u and a_Form location does not match: %s vs %s (%s)'
5385 % (sMacro, iOperand + 1, oInstr.aoOperands[iOperand].sWhere, sWhere, sForm,));
5386 sOpFormMatch = g_kdOpTypes[oInstr.aoOperands[iOperand].sType][4];
5387 if (sOpFormMatch in [ 'REG', 'MEM', ] and sForm.find('_' + sOpFormMatch) < 0) \
5388 or (sOpFormMatch in [ 'FIXED', ] and sForm.find(sOpFormMatch) < 0) \
5389 or (sOpFormMatch == 'RM' and (sForm.find('_MEM') > 0 or sForm.find('_REG') > 0) ) \
5390 or (sOpFormMatch == 'V' and ( not (sForm.find('VEX') > 0 or sForm.find('XOP')) \
5391 or sForm.replace('VEX','').find('V') < 0) ):
5392 self.error('%s: current instruction @op%u and a_Form type does not match: %s/%s vs %s'
5393 % (sMacro, iOperand + 1, oInstr.aoOperands[iOperand].sType, sOpFormMatch, sForm, ));
5394 if len(g_kdIemForms[sForm][1]) < len(oInstr.aoOperands):
5395 for iOperand in range(len(g_kdIemForms[sForm][1]), len(oInstr.aoOperands)):
5396 if oInstr.aoOperands[iOperand].sType != 'FIXED' \
5397 and g_kdOpTypes[oInstr.aoOperands[iOperand].sType][0] != 'IDX_ParseFixedReg':
5398 self.error('%s: Expected FIXED type operand #%u following operands given by a_Form=%s: %s (%s)'
5399 % (sMacro, iOperand, sForm, oInstr.aoOperands[iOperand].sType,
5400 oInstr.aoOperands[iOperand].sWhere));
5401
5402
5403 # Check @opcodesub
5404 if oInstr.sSubOpcode \
5405 and g_kdIemForms[sForm][2] \
5406 and oInstr.sSubOpcode.find(g_kdIemForms[sForm][2]) < 0:
5407 self.error('%s: current instruction @opcodesub and a_Form does not match: %s vs %s (%s)'
5408 % (sMacro, oInstr.sSubOpcode, g_kdIemForms[sForm][2], sForm,));
5409
5410 # Stats.
5411 if not self.oReStatsName.match(sStats):
5412 self.error('%s: invalid a_Stats value: %s' % (sMacro, sStats,));
5413 elif oInstr.sStats is None:
5414 oInstr.sStats = sStats;
5415 elif oInstr.sStats != sStats:
5416 self.error('%s: mismatching @opstats and a_Stats value: %s vs %s'
5417 % (sMacro, oInstr.sStats, sStats,));
5418
5419 # Process the hints (simply merge with @ophints w/o checking anything).
5420 for sHint in sDisHints.split('|'):
5421 sHint = sHint.strip();
5422 if sHint.startswith('DISOPTYPE_'):
5423 sShortHint = sHint[len('DISOPTYPE_'):].lower();
5424 if sShortHint in g_kdHints:
5425 oInstr.dHints[sShortHint] = True; # (dummy value, using dictionary for speed)
5426 else:
5427 self.error('%s: unknown a_fDisHints value: %s' % (sMacro, sHint,));
5428 elif sHint != '0':
5429 self.error('%s: expected a_fDisHints value: %s' % (sMacro, sHint,));
5430
5431 for sHint in sIemHints.split('|'):
5432 sHint = sHint.strip();
5433 if sHint.startswith('IEMOPHINT_'):
5434 sShortHint = sHint[len('IEMOPHINT_'):].lower();
5435 if sShortHint in g_kdHints:
5436 oInstr.dHints[sShortHint] = True; # (dummy value, using dictionary for speed)
5437 else:
5438 self.error('%s: unknown a_fIemHints value: %s' % (sMacro, sHint,));
5439 elif sHint != '0':
5440 self.error('%s: expected a_fIemHints value: %s' % (sMacro, sHint,));
5441
5442 _ = sAsm;
5443 return True;
5444
5445 def workerIemOpMnemonic(self, sMacro, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands):
5446 """
5447 Processes one of the a IEMOP_MNEMONIC0, IEMOP_MNEMONIC1, IEMOP_MNEMONIC2,
5448 IEMOP_MNEMONIC3, and IEMOP_MNEMONIC4 macros.
5449 """
5450 if not asOperands:
5451 return self.workerIemOpMnemonicEx(sMacro, sLower, sLower, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands);
5452 return self.workerIemOpMnemonicEx(sMacro, sLower + '_' + '_'.join(asOperands), sLower + ' ' + ','.join(asOperands),
5453 sForm, sUpper, sLower, sDisHints, sIemHints, asOperands);
5454
5455 def workerIemMcBegin(self, sCode, offBeginStatementInCodeStr, offBeginStatementInLine):
5456 """
5457 Process a IEM_MC_BEGIN macro invocation.
5458 """
5459 if self.fDebugMc:
5460 self.debug('IEM_MC_BEGIN on %s off %s' % (self.iLine, offBeginStatementInLine,));
5461 #self.debug('%s<eos>' % (sCode,));
5462
5463 # Check preconditions.
5464 if not self.oCurFunction:
5465 self.raiseError('IEM_MC_BEGIN w/o current function (%s)' % (sCode,));
5466 if self.oCurMcBlock:
5467 self.raiseError('IEM_MC_BEGIN before IEM_MC_END. Previous IEM_MC_BEGIN at line %u' % (self.oCurMcBlock.iBeginLine,));
5468
5469 # Figure out the indent level the block starts at, adjusting for expanded multiline macros.
5470 cchIndent = offBeginStatementInCodeStr;
5471 offPrevNewline = sCode.rfind('\n', 0, offBeginStatementInCodeStr);
5472 if offPrevNewline >= 0:
5473 cchIndent -= offPrevNewline + 1;
5474 #self.debug('cchIndent=%s offPrevNewline=%s sFunc=%s' % (cchIndent, offPrevNewline, self.oCurFunction.sName));
5475
5476 # Start a new block.
5477 # But don't add it to the list unless the context matches the host architecture.
5478 self.oCurMcBlock = McBlock(self.sSrcFile, self.iLine, offBeginStatementInLine, self.oCurFunction, self.iMcBlockInFunc,
5479 oInstruction = self.aoCurInstrs[-1] if self.aoCurInstrs else None,
5480 cchIndent = cchIndent);
5481 try:
5482 if ( not self.aoCppCondStack
5483 or not self.sHostArch
5484 or self.PreprocessorConditional.isInBlockForArch(self.aoCppCondStack, self.sHostArch, self.iLine)):
5485 g_aoMcBlocks.append(self.oCurMcBlock);
5486 self.cTotalMcBlocks += 1;
5487 except Exception as oXcpt:
5488 self.raiseError(oXcpt.args[0]);
5489
5490 if self.oCurMcBlock.oInstruction:
5491 self.oCurMcBlock.oInstruction.aoMcBlocks.append(self.oCurMcBlock);
5492 self.iMcBlockInFunc += 1;
5493 return True;
5494
5495 @staticmethod
5496 def extractLinesFromMacroExpansionLine(sRawLine, offBegin, offEnd, sBeginStmt = 'IEM_MC_BEGIN'):
5497 """
5498 Helper used by workerIemMcEnd and workerIemMcDeferToCImplXRet for
5499 extracting a statement block from a string that's the result of macro
5500 expansion and therefore contains multiple "sub-lines" as it were.
5501
5502 Returns list of lines covering offBegin thru offEnd in sRawLine.
5503 """
5504
5505 off = sRawLine.find('\n', offEnd);
5506 if off > 0:
5507 sRawLine = sRawLine[:off + 1];
5508
5509 off = sRawLine.rfind('\n', 0, offBegin) + 1;
5510 sRawLine = sRawLine[off:];
5511 if not sRawLine.strip().startswith(sBeginStmt):
5512 sRawLine = sRawLine[offBegin - off:]
5513
5514 return [sLine + '\n' for sLine in sRawLine.split('\n')];
5515
5516 def workerIemMcEnd(self, offEndStatementInLine):
5517 """
5518 Process a IEM_MC_END macro invocation.
5519 """
5520 if self.fDebugMc:
5521 self.debug('IEM_MC_END on %s off %s' % (self.iLine, offEndStatementInLine,));
5522
5523 # Check preconditions.
5524 if not self.oCurMcBlock:
5525 self.raiseError('IEM_MC_END w/o IEM_MC_BEGIN.');
5526
5527 #
5528 # HACK ALERT! For blocks originating from macro expansion the start and
5529 # end line will be the same, but the line has multiple
5530 # newlines inside it. So, we have to do some extra tricks
5531 # to get the lines out of there. We ASSUME macros aren't
5532 # messy, but keep IEM_MC_BEGIN/END on separate lines.
5533 #
5534 if self.iLine > self.oCurMcBlock.iBeginLine:
5535 asLines = self.asLines[self.oCurMcBlock.iBeginLine - 1 : self.iLine];
5536 if not asLines[0].strip().startswith('IEM_MC_BEGIN'):
5537 self.raiseError('IEM_MC_BEGIN is not the first word on the line');
5538
5539 # Hack alert! Detect mixed tail/head macros a la cmpxchg16b and split up the lines
5540 # so we can deal correctly with IEM_MC_END below and everything else.
5541 for sLine in asLines:
5542 cNewLines = sLine.count('\n');
5543 assert cNewLines > 0;
5544 if cNewLines > 1:
5545 asLines = self.extractLinesFromMacroExpansionLine(''.join(asLines),
5546 self.oCurMcBlock.offBeginLine,
5547 offEndStatementInLine
5548 + sum(len(s) for s in asLines)
5549 - len(asLines[-1]));
5550 self.oCurMcBlock.iMacroExp = McBlock.kiMacroExp_Partial;
5551 break;
5552 else:
5553 self.oCurMcBlock.iMacroExp = McBlock.kiMacroExp_Entire;
5554 asLines = self.extractLinesFromMacroExpansionLine(self.asLines[self.iLine - 1],
5555 self.oCurMcBlock.offBeginLine, offEndStatementInLine);
5556
5557 #
5558 # Strip anything following the IEM_MC_END(); statement in the final line,
5559 # so that we don't carry on any trailing 'break' after macro expansions
5560 # like for iemOp_movsb_Xb_Yb.
5561 #
5562 while asLines[-1].strip() == '':
5563 asLines.pop();
5564 sFinal = asLines[-1];
5565 offFinalEnd = sFinal.find('IEM_MC_END');
5566 offEndInFinal = offFinalEnd;
5567 if offFinalEnd < 0: self.raiseError('bogus IEM_MC_END: Not in final line: %s' % (sFinal,));
5568 offFinalEnd += len('IEM_MC_END');
5569
5570 while sFinal[offFinalEnd].isspace():
5571 offFinalEnd += 1;
5572 if sFinal[offFinalEnd] != '(': self.raiseError('bogus IEM_MC_END: Expected "(" at %s: %s' % (offFinalEnd, sFinal,));
5573 offFinalEnd += 1;
5574
5575 while sFinal[offFinalEnd].isspace():
5576 offFinalEnd += 1;
5577 if sFinal[offFinalEnd] != ')': self.raiseError('bogus IEM_MC_END: Expected ")" at %s: %s' % (offFinalEnd, sFinal,));
5578 offFinalEnd += 1;
5579
5580 while sFinal[offFinalEnd].isspace():
5581 offFinalEnd += 1;
5582 if sFinal[offFinalEnd] != ';': self.raiseError('bogus IEM_MC_END: Expected ";" at %s: %s' % (offFinalEnd, sFinal,));
5583 offFinalEnd += 1;
5584
5585 asLines[-1] = sFinal[: offFinalEnd];
5586
5587 #
5588 # Complete and discard the current block.
5589 #
5590 self.oCurMcBlock.complete(self.iLine, offEndStatementInLine,
5591 offEndStatementInLine + offFinalEnd - offEndInFinal, asLines);
5592 self.oCurMcBlock = None;
5593 return True;
5594
5595 def workerIemMcDeferToCImplXRet(self, sCode, offBeginStatementInCodeStr, offBeginStatementInLine, cParams):
5596 """
5597 Process a IEM_MC_DEFER_TO_CIMPL_[1-5]_RET macro invocation.
5598 """
5599 sStmt = 'IEM_MC_DEFER_TO_CIMPL_%d_RET' % (cParams,);
5600 if self.fDebugMc:
5601 self.debug('%s on %s off %s' % (sStmt, self.iLine, offBeginStatementInLine,));
5602 #self.debug('%s<eos>' % (sCode,));
5603
5604 # Check preconditions.
5605 if not self.oCurFunction:
5606 self.raiseError('%s w/o current function (%s)' % (sStmt, sCode,));
5607 if self.oCurMcBlock:
5608 self.raiseError('%s inside IEM_MC_BEGIN block starting at line %u' % (sStmt, self.oCurMcBlock.iBeginLine,));
5609
5610 # Figure out the indent level the block starts at, adjusting for expanded multiline macros.
5611 cchIndent = offBeginStatementInCodeStr;
5612 offPrevNewline = sCode.rfind('\n', 0, offBeginStatementInCodeStr);
5613 if offPrevNewline >= 0:
5614 cchIndent -= offPrevNewline + 1;
5615 #self.debug('cchIndent=%s offPrevNewline=%s sFunc=%s' % (cchIndent, offPrevNewline, self.oCurFunction.sName));
5616
5617 # Start a new block.
5618 oMcBlock = McBlock(self.sSrcFile, self.iLine, offBeginStatementInLine, self.oCurFunction, self.iMcBlockInFunc,
5619 oInstruction = self.aoCurInstrs[-1] if self.aoCurInstrs else None,
5620 cchIndent = cchIndent, fDeferToCImpl = True);
5621
5622 # Parse the statment.
5623 asArgs, offAfter, cLines = self.findAndParseMacroInvocationEx(sCode, sStmt, offBeginStatementInCodeStr);
5624 if asArgs is None:
5625 self.raiseError('%s: Closing parenthesis not found!' % (sStmt,));
5626 if len(asArgs) != cParams + 4:
5627 self.raiseError('%s: findAndParseMacroInvocationEx returns %s args, expected %s! (%s)'
5628 % (sStmt, len(asArgs), cParams + 4, asArgs));
5629
5630 oMcBlock.aoStmts = [ McBlock.parseMcDeferToCImpl(oMcBlock, asArgs[0], asArgs[1:]), ];
5631
5632 # These MCs are not typically part of macro expansions, but let's get
5633 # it out of the way immediately if it's the case.
5634 if cLines > 0 or self.asLines[oMcBlock.iBeginLine - 1].count('\n') <= 1:
5635 asLines = self.asLines[self.iLine - 1 : self.iLine - 1 + cLines + 1];
5636 assert offAfter < len(asLines[-1]) and asLines[-1][offAfter] == ';', \
5637 'iBeginLine=%d iLine=%d offAfter=%s line: "%s"' % (oMcBlock.iBeginLine, self.iLine, offAfter, asLines[-1],);
5638 asLines[-1] = asLines[-1][:offAfter + 1];
5639 else:
5640 asLines = self.extractLinesFromMacroExpansionLine(self.asLines[self.iLine - 1], offBeginStatementInCodeStr,
5641 offAfter, sStmt);
5642 assert asLines[-1].find(';') >= 0;
5643 asLines[-1] = asLines[-1][:asLines[-1].find(';') + 1];
5644
5645 assert asLines[0].find(sStmt) >= 0;
5646 #if not asLines[0].strip().startswith(sStmt):
5647 # self.raiseError('%s is not the first word on the line: %s' % (sStmt, asLines[0].strip()));
5648
5649 # Advance to the line with the closing ')'.
5650 self.iLine += cLines;
5651
5652 # Complete the block.
5653 oMcBlock.complete(self.iLine, 0 if cLines > 0 else offBeginStatementInCodeStr, offAfter + 1, asLines);
5654
5655 g_aoMcBlocks.append(oMcBlock);
5656 if oMcBlock.oInstruction:
5657 oMcBlock.oInstruction.aoMcBlocks.append(oMcBlock);
5658 self.cTotalMcBlocks += 1;
5659 self.iMcBlockInFunc += 1;
5660
5661 return True;
5662
5663 def workerStartFunction(self, asArgs):
5664 """
5665 Deals with the start of a decoder function.
5666
5667 These are all defined using one of the FNIEMOP*_DEF* and FNIEMOP_*STUB*
5668 macros, so we get a argument list for these where the 0th argument is the
5669 macro name.
5670 """
5671 # Complete any existing function.
5672 if self.oCurFunction:
5673 self.oCurFunction.complete(self.iLine - 1, self.asLines[self.oCurFunction.iBeginLine - 1 : self.iLine - 1]);
5674
5675 # Create the new function.
5676 self.oCurFunction = DecoderFunction(self.sSrcFile, self.iLine, asArgs[1], asArgs);
5677 return True;
5678
5679 def checkCodeForMacro(self, sCode, offLine):
5680 """
5681 Checks code for relevant macro invocation.
5682 """
5683
5684 #
5685 # Scan macro invocations.
5686 #
5687 if sCode.find('(') > 0:
5688 # Look for instruction decoder function definitions. ASSUME single line.
5689 asArgs = self.findAndParseFirstMacroInvocation(sCode,
5690 [ 'FNIEMOP_DEF',
5691 'FNIEMOPRM_DEF',
5692 'FNIEMOP_STUB',
5693 'FNIEMOP_STUB_1',
5694 'FNIEMOP_UD_STUB',
5695 'FNIEMOP_UD_STUB_1' ]);
5696 if asArgs is not None:
5697 self.workerStartFunction(asArgs);
5698 #self.debug('%s: oCurFunction=%s' % (self.iLine, self.oCurFunction.sName,));
5699
5700 if not self.aoCurInstrs:
5701 self.addInstruction();
5702 for oInstr in self.aoCurInstrs:
5703 if oInstr.iLineFnIemOpMacro == -1:
5704 oInstr.iLineFnIemOpMacro = self.iLine;
5705 else:
5706 self.error('%s: already seen a FNIEMOP_XXX macro for %s' % (asArgs[0], oInstr,) );
5707 self.setInstrunctionAttrib('sFunction', asArgs[1]);
5708 self.setInstrunctionAttrib('fStub', asArgs[0].find('STUB') > 0, fOverwrite = True);
5709 self.setInstrunctionAttrib('fUdStub', asArgs[0].find('UD_STUB') > 0, fOverwrite = True);
5710 if asArgs[0].find('STUB') > 0:
5711 self.doneInstructions(fEndOfFunction = True);
5712 return True;
5713
5714 # Check for worker function definitions, so we can get a context for MC blocks.
5715 asArgs = self.findAndParseFirstMacroInvocation(sCode,
5716 [ 'FNIEMOP_DEF_1',
5717 'FNIEMOP_DEF_2', ]);
5718 if asArgs is not None:
5719 self.workerStartFunction(asArgs);
5720 #self.debug('%s: oCurFunction=%s (%s)' % (self.iLine, self.oCurFunction.sName, asArgs[0]));
5721 return True;
5722
5723 # IEMOP_HLP_DONE_VEX_DECODING_*
5724 asArgs = self.findAndParseFirstMacroInvocation(sCode,
5725 [ 'IEMOP_HLP_DONE_VEX_DECODING',
5726 'IEMOP_HLP_DONE_VEX_DECODING_L0',
5727 'IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV',
5728 'IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV',
5729 ]);
5730 if asArgs is not None:
5731 sMacro = asArgs[0];
5732 if sMacro in ('IEMOP_HLP_DONE_VEX_DECODING_L0', 'IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV', ):
5733 for oInstr in self.aoCurInstrs:
5734 if 'vex_l_zero' not in oInstr.dHints:
5735 if oInstr.iLineMnemonicMacro >= 0:
5736 self.errorOnLine(oInstr.iLineMnemonicMacro,
5737 'Missing IEMOPHINT_VEX_L_ZERO! (%s on line %d)' % (sMacro, self.iLine,));
5738 oInstr.dHints['vex_l_zero'] = True;
5739
5740 #
5741 # IEMOP_MNEMONIC*
5742 #
5743 if sCode.find('IEMOP_MNEMONIC') >= 0:
5744 # IEMOP_MNEMONIC(a_Stats, a_szMnemonic) IEMOP_INC_STATS(a_Stats)
5745 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC');
5746 if asArgs is not None:
5747 if len(self.aoCurInstrs) == 1:
5748 oInstr = self.aoCurInstrs[0];
5749 if oInstr.sStats is None:
5750 oInstr.sStats = asArgs[1];
5751 self.deriveMnemonicAndOperandsFromStats(oInstr, asArgs[1]);
5752
5753 # IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints)
5754 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC0EX');
5755 if asArgs is not None:
5756 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[6],
5757 asArgs[7], []);
5758 # IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints)
5759 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC1EX');
5760 if asArgs is not None:
5761 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[7],
5762 asArgs[8], [asArgs[6],]);
5763 # IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints)
5764 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC2EX');
5765 if asArgs is not None:
5766 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[8],
5767 asArgs[9], [asArgs[6], asArgs[7]]);
5768 # IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints,
5769 # a_fIemHints)
5770 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC3EX');
5771 if asArgs is not None:
5772 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[9],
5773 asArgs[10], [asArgs[6], asArgs[7], asArgs[8],]);
5774 # IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints,
5775 # a_fIemHints)
5776 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC4EX');
5777 if asArgs is not None:
5778 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[10],
5779 asArgs[11], [asArgs[6], asArgs[7], asArgs[8], asArgs[9],]);
5780
5781 # IEMOP_MNEMONIC0(a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints)
5782 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC0');
5783 if asArgs is not None:
5784 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], []);
5785 # IEMOP_MNEMONIC1(a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints)
5786 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC1');
5787 if asArgs is not None:
5788 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[5], asArgs[6], [asArgs[4],]);
5789 # IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints)
5790 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC2');
5791 if asArgs is not None:
5792 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[6], asArgs[7],
5793 [asArgs[4], asArgs[5],]);
5794 # IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints)
5795 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC3');
5796 if asArgs is not None:
5797 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[7], asArgs[8],
5798 [asArgs[4], asArgs[5], asArgs[6],]);
5799 # IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints)
5800 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC4');
5801 if asArgs is not None:
5802 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[8], asArgs[9],
5803 [asArgs[4], asArgs[5], asArgs[6], asArgs[7],]);
5804
5805 #
5806 # IEM_MC_BEGIN + IEM_MC_END.
5807 # We must support multiple instances per code snippet.
5808 #
5809 offCode = sCode.find('IEM_MC_');
5810 if offCode >= 0:
5811 for oMatch in self.oReMcBeginEnd.finditer(sCode, offCode):
5812 if oMatch.group(1) == 'END':
5813 self.workerIemMcEnd(offLine + oMatch.start());
5814 elif oMatch.group(1) == 'BEGIN':
5815 self.workerIemMcBegin(sCode, oMatch.start(), offLine + oMatch.start());
5816 else:
5817 self.workerIemMcDeferToCImplXRet(sCode, oMatch.start(), offLine + oMatch.start(),
5818 int(oMatch.group(1)[len('DEFER_TO_CIMPL_')]));
5819 return True;
5820
5821 return False;
5822
5823 def workerPreprocessorRecreateMacroRegex(self):
5824 """
5825 Recreates self.oReMacros when self.dMacros changes.
5826 """
5827 if self.dMacros:
5828 sRegex = '';
5829 for sName, oMacro in self.dMacros.items():
5830 if sRegex:
5831 sRegex += r'|' + sName;
5832 else:
5833 sRegex = r'\b(' + sName;
5834 if oMacro.asArgs is not None:
5835 sRegex += r'\s*\(';
5836 else:
5837 sRegex += r'\b';
5838 sRegex += ')';
5839 self.oReMacros = re.compile(sRegex);
5840 else:
5841 self.oReMacros = None;
5842 return True;
5843
5844 def workerPreprocessorDefine(self, sRest):
5845 """
5846 Handles a macro #define, the sRest is what follows after the directive word.
5847 """
5848 assert sRest[-1] == '\n';
5849
5850 #
5851 # If using line continutation, just concat all the lines together,
5852 # preserving the newline character but not the escaping.
5853 #
5854 iLineStart = self.iLine;
5855 while sRest.endswith('\\\n') and self.iLine < len(self.asLines):
5856 sRest = sRest[0:-2].rstrip() + '\n' + self.asLines[self.iLine];
5857 self.iLine += 1;
5858 #self.debug('workerPreprocessorDefine: sRest=%s<EOS>' % (sRest,));
5859
5860 #
5861 # Use regex to split out the name, argument list and body.
5862 # If this fails, we assume it's a simple macro.
5863 #
5864 oMatch = self.oReHashDefine2.match(sRest);
5865 if oMatch:
5866 sAllArgs = oMatch.group(2).strip();
5867 asArgs = [sParam.strip() for sParam in sAllArgs.split(',')] if sAllArgs else None;
5868 sBody = oMatch.group(3);
5869 else:
5870 oMatch = self.oReHashDefine3.match(sRest);
5871 if not oMatch:
5872 self.debug('workerPreprocessorDefine: wtf? sRest=%s' % (sRest,));
5873 return self.error('bogus macro definition: %s' % (sRest,));
5874 asArgs = None;
5875 sBody = oMatch.group(2);
5876 sName = oMatch.group(1);
5877 assert sName == sName.strip();
5878 #self.debug('workerPreprocessorDefine: sName=%s asArgs=%s sBody=%s<EOS>' % (sName, asArgs, sBody));
5879
5880 #
5881 # Is this of any interest to us? We do NOT support MC blocks wihtin
5882 # nested macro expansion, just to avoid lots of extra work.
5883 #
5884 # There is only limited support for macros expanding to partial MC blocks.
5885 #
5886 # Note! IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX and other macros someone making
5887 # use of IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() will be ignored here and
5888 # dealt with by overriding IEMOP_RAISE_INVALID_LOCK_PREFIX_RET and its
5889 # siblings in the recompiler. This is a lot simpler than nested macro
5890 # expansion and lots of heuristics for locating all the relevant macros.
5891 # Also, this way we don't produce lots of unnecessary threaded functions.
5892 #
5893 if sBody.find("IEM_MC_BEGIN") < 0 and sBody.find("IEM_MC_END") < 0:
5894 #self.debug('workerPreprocessorDefine: irrelevant (%s: %s)' % (sName, sBody));
5895 return True;
5896
5897 #
5898 # Add the macro.
5899 #
5900 if self.fDebugPreproc:
5901 self.debug('#define %s on line %u' % (sName, self.iLine,));
5902 self.dMacros[sName] = SimpleParser.Macro(sName, asArgs, sBody.strip(), iLineStart);
5903 return self.workerPreprocessorRecreateMacroRegex();
5904
5905 def workerPreprocessorUndef(self, sRest):
5906 """
5907 Handles a macro #undef, the sRest is what follows after the directive word.
5908 """
5909 # Quick comment strip and isolate the name.
5910 offSlash = sRest.find('/');
5911 if offSlash > 0:
5912 sRest = sRest[:offSlash];
5913 sName = sRest.strip();
5914
5915 # Remove the macro if we're clocking it.
5916 if sName in self.dMacros:
5917 if self.fDebugPreproc:
5918 self.debug('#undef %s on line %u' % (sName, self.iLine,));
5919 del self.dMacros[sName];
5920 return self.workerPreprocessorRecreateMacroRegex();
5921
5922 return True;
5923
5924 def workerPreprocessorIfOrElif(self, sDirective, sRest):
5925 """
5926 Handles an #if, #ifdef, #ifndef or #elif directive.
5927 """
5928 #
5929 # Sanity check #elif.
5930 #
5931 if sDirective == 'elif':
5932 if len(self.aoCppCondStack) == 0:
5933 self.raiseError('#elif without #if');
5934 if self.aoCppCondStack[-1].fInElse:
5935 self.raiseError('#elif after #else');
5936
5937 #
5938 # If using line continutation, just concat all the lines together,
5939 # stripping both the newline and escape characters.
5940 #
5941 while sRest.endswith('\\\n') and self.iLine < len(self.asLines):
5942 sRest = sRest[0:-2].rstrip() + ' ' + self.asLines[self.iLine];
5943 self.iLine += 1;
5944
5945 # Strip it of all comments and leading and trailing blanks.
5946 sRest = self.stripComments(sRest).strip();
5947
5948 #
5949 # Stash it.
5950 #
5951 try:
5952 oPreprocCond = self.PreprocessorConditional(sDirective, sRest);
5953 except Exception as oXcpt:
5954 self.raiseError(oXcpt.args[0]);
5955
5956 if sDirective == 'elif':
5957 self.aoCppCondStack[-1].aoElif.append(oPreprocCond);
5958 else:
5959 self.aoCppCondStack.append(oPreprocCond);
5960
5961 return True;
5962
5963 def workerPreprocessorElse(self):
5964 """
5965 Handles an #else directive.
5966 """
5967 if len(self.aoCppCondStack) == 0:
5968 self.raiseError('#else without #if');
5969 if self.aoCppCondStack[-1].fInElse:
5970 self.raiseError('Another #else after #else');
5971
5972 self.aoCppCondStack[-1].fInElse = True;
5973 return True;
5974
5975 def workerPreprocessorEndif(self):
5976 """
5977 Handles an #endif directive.
5978 """
5979 if len(self.aoCppCondStack) == 0:
5980 self.raiseError('#endif without #if');
5981
5982 self.aoCppCondStack.pop();
5983 return True;
5984
5985 def checkPreprocessorDirective(self, sLine):
5986 """
5987 Handles a preprocessor directive.
5988 """
5989 # Skip past the preprocessor hash.
5990 off = sLine.find('#');
5991 assert off >= 0;
5992 off += 1;
5993 while off < len(sLine) and sLine[off].isspace():
5994 off += 1;
5995
5996 # Extract the directive.
5997 offDirective = off;
5998 while off < len(sLine) and not sLine[off].isspace():
5999 off += 1;
6000 sDirective = sLine[offDirective:off];
6001 if self.fDebugPreproc:
6002 self.debug('line %d: #%s...' % (self.iLine, sDirective));
6003
6004 # Skip spaces following it to where the arguments/whatever starts.
6005 while off + 1 < len(sLine) and sLine[off + 1].isspace():
6006 off += 1;
6007 sTail = sLine[off:];
6008
6009 # Handle the directive.
6010 if sDirective == 'define':
6011 return self.workerPreprocessorDefine(sTail);
6012 if sDirective == 'undef':
6013 return self.workerPreprocessorUndef(sTail);
6014 if sDirective in ('if', 'ifdef', 'ifndef', 'elif',):
6015 return self.workerPreprocessorIfOrElif(sDirective, sTail);
6016 if sDirective == 'else':
6017 return self.workerPreprocessorElse();
6018 if sDirective == 'endif':
6019 return self.workerPreprocessorEndif();
6020
6021 if self.fDebugPreproc:
6022 self.debug('line %d: Unknown preprocessor directive: %s' % (self.iLine, sDirective));
6023 return False;
6024
6025 def expandMacros(self, sLine, oMatch):
6026 """
6027 Expands macros we know about in the given line.
6028 Currently we ASSUME there is only one and that is what oMatch matched.
6029 """
6030 #
6031 # Get our bearings.
6032 #
6033 offMatch = oMatch.start();
6034 sName = oMatch.group(1);
6035 assert sName == sLine[oMatch.start() : oMatch.end()];
6036 fWithArgs = sName.endswith('(');
6037 if fWithArgs:
6038 sName = sName[:-1].strip();
6039 oMacro = self.dMacros[sName] # type: SimpleParser.Macro
6040
6041 #
6042 # Deal with simple macro invocations w/o parameters.
6043 #
6044 if not fWithArgs:
6045 if self.fDebugPreproc:
6046 self.debug('expanding simple macro %s on line %u' % (sName, self.iLine,));
6047 return sLine[:offMatch] + oMacro.expandMacro(self) + sLine[oMatch.end():];
6048
6049 #
6050 # Complicated macro with parameters.
6051 # Start by extracting the parameters. ASSUMES they are all on the same line!
6052 #
6053 cLevel = 1;
6054 offCur = oMatch.end();
6055 offCurArg = offCur;
6056 asArgs = [];
6057 while True:
6058 if offCur >= len(sLine):
6059 self.raiseError('expandMacros: Invocation of macro %s spans multiple lines!' % (sName,));
6060 ch = sLine[offCur];
6061 if ch == '(':
6062 cLevel += 1;
6063 elif ch == ')':
6064 cLevel -= 1;
6065 if cLevel == 0:
6066 asArgs.append(sLine[offCurArg:offCur].strip());
6067 break;
6068 elif ch == ',' and cLevel == 1:
6069 asArgs.append(sLine[offCurArg:offCur].strip());
6070 offCurArg = offCur + 1;
6071 offCur += 1;
6072 if len(oMacro.asArgs) == 0 and len(asArgs) == 1 and asArgs[0] == '': # trick for empty parameter list.
6073 asArgs = [];
6074 if len(oMacro.asArgs) != len(asArgs):
6075 self.raiseError('expandMacros: Argument mismatch in %s invocation' % (oMacro.sName,));
6076
6077 #
6078 # Do the expanding.
6079 #
6080 if self.fDebugPreproc:
6081 self.debug('expanding macro %s on line %u with arguments %s' % (sName, self.iLine, asArgs));
6082 return sLine[:offMatch] + oMacro.expandMacro(self, asArgs) + sLine[offCur + 1 :];
6083
6084 def parse(self):
6085 """
6086 Parses the given file.
6087
6088 Returns number or errors.
6089 Raises exception on fatal trouble.
6090 """
6091 #self.debug('Parsing %s' % (self.sSrcFile,));
6092
6093 #
6094 # Loop thru the lines.
6095 #
6096 # Please mind that self.iLine may be updated by checkCodeForMacro and
6097 # other worker methods.
6098 #
6099 while self.iLine < len(self.asLines):
6100 sLine = self.asLines[self.iLine];
6101 self.iLine += 1;
6102 #self.debug('line %u: %s' % (self.iLine, sLine[:-1]));
6103
6104 # Expand macros we know about if we're currently in code.
6105 if self.iState == self.kiCode and self.oReMacros:
6106 oMatch = self.oReMacros.search(sLine);
6107 if oMatch:
6108 sLine = self.expandMacros(sLine, oMatch);
6109 if self.fDebugPreproc:
6110 self.debug('line %d: expanded\n%s ==>\n%s' % (self.iLine, self.asLines[self.iLine - 1], sLine[:-1],));
6111 self.asLines[self.iLine - 1] = sLine;
6112
6113 # Check for preprocessor directives before comments and other stuff.
6114 # ASSUMES preprocessor directives doesn't end with multiline comments.
6115 if self.iState == self.kiCode and sLine.lstrip().startswith('#'):
6116 if self.fDebugPreproc:
6117 self.debug('line %d: preproc' % (self.iLine,));
6118 self.checkPreprocessorDirective(sLine);
6119 else:
6120 # Look for comments.
6121 offSlash = sLine.find('/');
6122 if offSlash >= 0:
6123 if offSlash + 1 >= len(sLine) or sLine[offSlash + 1] != '/' or self.iState != self.kiCode:
6124 offLine = 0;
6125 while offLine < len(sLine):
6126 if self.iState == self.kiCode:
6127 # Look for substantial multiline comment so we pass the following MC as a whole line:
6128 # IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
6129 # Note! We ignore C++ comments here, assuming these aren't used in lines with C-style comments.
6130 offHit = sLine.find('/*', offLine);
6131 while offHit >= 0:
6132 offEnd = sLine.find('*/', offHit + 2);
6133 if offEnd < 0 or offEnd - offHit >= 16: # 16 chars is a bit random.
6134 break;
6135 offHit = sLine.find('/*', offEnd);
6136
6137 if offHit >= 0:
6138 self.checkCodeForMacro(sLine[offLine:offHit], offLine);
6139 self.sComment = '';
6140 self.iCommentLine = self.iLine;
6141 self.iState = self.kiCommentMulti;
6142 offLine = offHit + 2;
6143 else:
6144 self.checkCodeForMacro(sLine[offLine:], offLine);
6145 offLine = len(sLine);
6146
6147 elif self.iState == self.kiCommentMulti:
6148 offHit = sLine.find('*/', offLine);
6149 if offHit >= 0:
6150 self.sComment += sLine[offLine:offHit];
6151 self.iState = self.kiCode;
6152 offLine = offHit + 2;
6153 self.parseComment();
6154 else:
6155 self.sComment += sLine[offLine:];
6156 offLine = len(sLine);
6157 else:
6158 assert False;
6159 # C++ line comment.
6160 elif offSlash > 0:
6161 self.checkCodeForMacro(sLine[:offSlash], 0);
6162
6163 # No slash, but append the line if in multi-line comment.
6164 elif self.iState == self.kiCommentMulti:
6165 #self.debug('line %d: multi' % (self.iLine,));
6166 self.sComment += sLine;
6167
6168 # No slash, but check code line for relevant macro.
6169 elif ( self.iState == self.kiCode
6170 and (sLine.find('IEMOP_') >= 0 or sLine.find('FNIEMOPRM_DEF') >= 0 or sLine.find('IEM_MC') >= 0)):
6171 #self.debug('line %d: macro' % (self.iLine,));
6172 self.checkCodeForMacro(sLine, 0);
6173
6174 # If the line is a '}' in the first position, complete the instructions.
6175 elif self.iState == self.kiCode and sLine[0] == '}':
6176 #self.debug('line %d: }' % (self.iLine,));
6177 self.doneInstructions(fEndOfFunction = True);
6178
6179 # Look for instruction table on the form 'IEM_STATIC const PFNIEMOP g_apfnVexMap3'
6180 # so we can check/add @oppfx info from it.
6181 elif self.iState == self.kiCode and sLine.find('PFNIEMOP') > 0 and self.oReFunTable.match(sLine):
6182 self.parseFunctionTable(sLine);
6183
6184 self.doneInstructions(fEndOfFunction = True);
6185 self.debug('%3s%% / %3s stubs out of %4s instructions and %4s MC blocks in %s'
6186 % (self.cTotalStubs * 100 // max(self.cTotalInstr, 1), self.cTotalStubs, self.cTotalInstr,
6187 self.cTotalMcBlocks, os.path.basename(self.sSrcFile),));
6188 return self.printErrors();
6189
6190# Some sanity checking.
6191def __sanityCheckEFlagsClasses():
6192 for sClass, dLists in SimpleParser.kdEFlagsClasses.items():
6193 for sAttrib, asFlags in dLists.items():
6194 for sFlag in asFlags:
6195 assert sFlag in g_kdEFlagsMnemonics, 'sClass=%s sAttrib=%s sFlag=%s' % (sClass, sAttrib, sFlag,);
6196__sanityCheckEFlagsClasses();
6197
6198## The parsed content of IEMAllInstCommonBodyMacros.h.
6199g_oParsedCommonBodyMacros = None # type: SimpleParser
6200
6201def __parseFileByName(sSrcFile, sDefaultMap, sHostArch):
6202 """
6203 Parses one source file for instruction specfications.
6204 """
6205 #
6206 # Read sSrcFile into a line array.
6207 #
6208 try:
6209 oFile = open(sSrcFile, "r"); # pylint: disable=consider-using-with,unspecified-encoding
6210 except Exception as oXcpt:
6211 raise Exception("failed to open %s for reading: %s" % (sSrcFile, oXcpt,));
6212 try:
6213 asLines = oFile.readlines();
6214 except Exception as oXcpt:
6215 raise Exception("failed to read %s: %s" % (sSrcFile, oXcpt,));
6216 finally:
6217 oFile.close();
6218
6219 #
6220 # On the first call, we parse IEMAllInstCommonBodyMacros.h so we
6221 # can use the macros from it when processing the other files.
6222 #
6223 global g_oParsedCommonBodyMacros;
6224 if g_oParsedCommonBodyMacros is None:
6225 # Locate the file.
6226 sCommonBodyMacros = os.path.join(os.path.split(sSrcFile)[0], 'IEMAllInstCommonBodyMacros.h');
6227 if not os.path.isfile(sCommonBodyMacros):
6228 sCommonBodyMacros = os.path.join(os.path.split(__file__)[0], 'IEMAllInstCommonBodyMacros.h');
6229
6230 # Read it.
6231 try:
6232 with open(sCommonBodyMacros, "r") as oIncFile: # pylint: disable=unspecified-encoding
6233 asIncFiles = oIncFile.readlines();
6234 except Exception as oXcpt:
6235 raise Exception("failed to open/read %s: %s" % (sCommonBodyMacros, oXcpt,));
6236
6237 # Parse it.
6238 try:
6239 oParser = SimpleParser(sCommonBodyMacros, asIncFiles, 'one', sHostArch);
6240 if oParser.parse() != 0:
6241 raise ParserException('%s: errors: See above' % (sCommonBodyMacros, ));
6242 if oParser.cTotalInstr != 0 or oParser.cTotalStubs != 0 or oParser.cTotalTagged != 0 or oParser.cTotalMcBlocks != 0:
6243 raise ParserException('%s: error: Unexpectedly found %u instr, %u tags, %u stubs and %u MCs, expecting zero. %s'
6244 % (sCommonBodyMacros, oParser.cTotalInstr, oParser.cTotalStubs, oParser.cTotalTagged,
6245 oParser.cTotalMcBlocks,
6246 ', '.join(sorted( [str(oMcBlock.iBeginLine) for oMcBlock in g_aoMcBlocks]
6247 + [str(oInstr.iLineCreated) for oInstr in g_aoAllInstructions])),));
6248 except ParserException as oXcpt:
6249 print(str(oXcpt), file = sys.stderr);
6250 raise;
6251 g_oParsedCommonBodyMacros = oParser;
6252
6253 #
6254 # Do the parsing.
6255 #
6256 try:
6257 oParser = SimpleParser(sSrcFile, asLines, sDefaultMap, sHostArch, g_oParsedCommonBodyMacros);
6258 return (oParser.parse(), oParser) ;
6259 except ParserException as oXcpt:
6260 print(str(oXcpt), file = sys.stderr);
6261 raise;
6262
6263
6264def __doTestCopying():
6265 """
6266 Executes the asCopyTests instructions.
6267 """
6268 asErrors = [];
6269 for oDstInstr in g_aoAllInstructions:
6270 if oDstInstr.asCopyTests:
6271 for sSrcInstr in oDstInstr.asCopyTests:
6272 oSrcInstr = g_dAllInstructionsByStat.get(sSrcInstr, None);
6273 if oSrcInstr:
6274 aoSrcInstrs = [oSrcInstr,];
6275 else:
6276 aoSrcInstrs = g_dAllInstructionsByFunction.get(sSrcInstr, []);
6277 if aoSrcInstrs:
6278 for oSrcInstr in aoSrcInstrs:
6279 if oSrcInstr != oDstInstr:
6280 oDstInstr.aoTests.extend(oSrcInstr.aoTests);
6281 else:
6282 asErrors.append('%s:%s: error: @opcopytests reference "%s" matches the destination\n'
6283 % ( oDstInstr.sSrcFile, oDstInstr.iLineCreated, sSrcInstr));
6284 else:
6285 asErrors.append('%s:%s: error: @opcopytests reference "%s" not found\n'
6286 % ( oDstInstr.sSrcFile, oDstInstr.iLineCreated, sSrcInstr));
6287
6288 if asErrors:
6289 sys.stderr.write(u''.join(asErrors));
6290 return len(asErrors);
6291
6292
6293def __applyOnlyTest():
6294 """
6295 If g_aoOnlyTestInstructions contains any instructions, drop aoTests from
6296 all other instructions so that only these get tested.
6297 """
6298 if g_aoOnlyTestInstructions:
6299 for oInstr in g_aoAllInstructions:
6300 if oInstr.aoTests:
6301 if oInstr not in g_aoOnlyTestInstructions:
6302 oInstr.aoTests = [];
6303 return 0;
6304
6305## List of all main instruction files, their default maps and file sets (-1 means included it all sets).
6306g_aaoAllInstrFilesAndDefaultMapAndSet = (
6307 ( 'IEMAllInstCommon.cpp.h', 'one', -1, ),
6308 ( 'IEMAllInstOneByte.cpp.h', 'one', 1, ),
6309 ( 'IEMAllInst3DNow.cpp.h', '3dnow', 2, ),
6310 ( 'IEMAllInstTwoByte0f.cpp.h', 'two0f', 2, ),
6311 ( 'IEMAllInstThree0f38.cpp.h', 'three0f38', 3, ),
6312 ( 'IEMAllInstThree0f3a.cpp.h', 'three0f3a', 3, ),
6313 ( 'IEMAllInstVexMap1.cpp.h', 'vexmap1', 4, ),
6314 ( 'IEMAllInstVexMap2.cpp.h', 'vexmap2', 4, ),
6315 ( 'IEMAllInstVexMap3.cpp.h', 'vexmap3', 4, ),
6316);
6317
6318def __parseFilesWorker(asFilesAndDefaultMap, sHostArch):
6319 """
6320 Parses all the IEMAllInstruction*.cpp.h files.
6321
6322 Returns a list of the parsers on success.
6323 Raises exception on failure.
6324 """
6325 sSrcDir = os.path.dirname(os.path.abspath(__file__));
6326 cErrors = 0;
6327 aoParsers = [];
6328 for sFilename, sDefaultMap in asFilesAndDefaultMap:
6329 if not os.path.split(sFilename)[0] and not os.path.exists(sFilename):
6330 sFilename = os.path.join(sSrcDir, sFilename);
6331 cThisErrors, oParser = __parseFileByName(sFilename, sDefaultMap, sHostArch);
6332 cErrors += cThisErrors;
6333 aoParsers.append(oParser);
6334 cErrors += __doTestCopying();
6335 cErrors += __applyOnlyTest();
6336
6337 # Total stub stats:
6338 cTotalStubs = 0;
6339 for oInstr in g_aoAllInstructions:
6340 cTotalStubs += oInstr.fStub;
6341 print('debug: %3s%% / %3s stubs out of %4s instructions and %4s MC blocks in total'
6342 % (cTotalStubs * 100 // len(g_aoAllInstructions), cTotalStubs, len(g_aoAllInstructions), len(g_aoMcBlocks),),
6343 file = sys.stderr);
6344
6345 if cErrors != 0:
6346 raise Exception('%d parse errors' % (cErrors,));
6347 return aoParsers;
6348
6349
6350def parseFiles(asFiles, sHostArch = None):
6351 """
6352 Parses a selection of IEMAllInstruction*.cpp.h files.
6353
6354 Returns a list of the parsers on success.
6355 Raises exception on failure.
6356 """
6357 # Look up default maps for the files and call __parseFilesWorker to do the job.
6358 asFilesAndDefaultMap = [];
6359 for sFilename in asFiles:
6360 sName = os.path.split(sFilename)[1].lower();
6361 sMap = None;
6362 for aoInfo in g_aaoAllInstrFilesAndDefaultMapAndSet:
6363 if aoInfo[0].lower() == sName:
6364 sMap = aoInfo[1];
6365 break;
6366 if not sMap:
6367 raise Exception('Unable to classify file: %s' % (sFilename,));
6368 asFilesAndDefaultMap.append((sFilename, sMap));
6369
6370 return __parseFilesWorker(asFilesAndDefaultMap, sHostArch);
6371
6372
6373def parseAll(sHostArch = None):
6374 """
6375 Parses all the IEMAllInstruction*.cpp.h files.
6376
6377 Returns a list of the parsers on success.
6378 Raises exception on failure.
6379 """
6380 return __parseFilesWorker([aoInfo[0:2] for aoInfo in g_aaoAllInstrFilesAndDefaultMapAndSet], sHostArch);
6381
6382
6383#
6384# Generators (may perhaps move later).
6385#
6386def __formatDisassemblerTableEntry(oInstr):
6387 """
6388 """
6389 sMacro = 'OP';
6390 cMaxOperands = 3;
6391 if len(oInstr.aoOperands) > 3:
6392 sMacro = 'OPVEX'
6393 cMaxOperands = 4;
6394 assert len(oInstr.aoOperands) <= cMaxOperands;
6395
6396 #
6397 # Format string.
6398 #
6399 sTmp = '%s("%s' % (sMacro, oInstr.sMnemonic,);
6400 for iOperand, oOperand in enumerate(oInstr.aoOperands):
6401 sTmp += ' ' if iOperand == 0 else ',';
6402 if g_kdOpTypes[oOperand.sType][2][0] != '%': ## @todo remove upper() later.
6403 sTmp += g_kdOpTypes[oOperand.sType][2].upper(); ## @todo remove upper() later.
6404 else:
6405 sTmp += g_kdOpTypes[oOperand.sType][2];
6406 sTmp += '",';
6407 asColumns = [ sTmp, ];
6408
6409 #
6410 # Decoders.
6411 #
6412 iStart = len(asColumns);
6413 if oInstr.sEncoding is None:
6414 pass;
6415 elif oInstr.sEncoding == 'ModR/M':
6416 # ASSUME the first operand is using the ModR/M encoding
6417 assert len(oInstr.aoOperands) >= 1 and oInstr.aoOperands[0].usesModRM(), "oInstr=%s" % (oInstr,);
6418 asColumns.append('IDX_ParseModRM,');
6419 elif oInstr.sEncoding in [ 'prefix', ]:
6420 for oOperand in oInstr.aoOperands:
6421 asColumns.append('0,');
6422 elif oInstr.sEncoding in [ 'fixed', 'VEX.fixed' ]:
6423 pass;
6424 elif oInstr.sEncoding == 'VEX.ModR/M':
6425 asColumns.append('IDX_ParseModRM,');
6426 elif oInstr.sEncoding == 'vex2':
6427 asColumns.append('IDX_ParseVex2b,')
6428 elif oInstr.sEncoding == 'vex3':
6429 asColumns.append('IDX_ParseVex3b,')
6430 elif oInstr.sEncoding in g_dInstructionMaps:
6431 asColumns.append(g_dInstructionMaps[oInstr.sEncoding].sDisParse + ',');
6432 else:
6433 ## @todo
6434 #IDX_ParseTwoByteEsc,
6435 #IDX_ParseGrp1,
6436 #IDX_ParseShiftGrp2,
6437 #IDX_ParseGrp3,
6438 #IDX_ParseGrp4,
6439 #IDX_ParseGrp5,
6440 #IDX_Parse3DNow,
6441 #IDX_ParseGrp6,
6442 #IDX_ParseGrp7,
6443 #IDX_ParseGrp8,
6444 #IDX_ParseGrp9,
6445 #IDX_ParseGrp10,
6446 #IDX_ParseGrp12,
6447 #IDX_ParseGrp13,
6448 #IDX_ParseGrp14,
6449 #IDX_ParseGrp15,
6450 #IDX_ParseGrp16,
6451 #IDX_ParseThreeByteEsc4,
6452 #IDX_ParseThreeByteEsc5,
6453 #IDX_ParseModFence,
6454 #IDX_ParseEscFP,
6455 #IDX_ParseNopPause,
6456 #IDX_ParseInvOpModRM,
6457 assert False, str(oInstr);
6458
6459 # Check for immediates and stuff in the remaining operands.
6460 for oOperand in oInstr.aoOperands[len(asColumns) - iStart:]:
6461 sIdx = g_kdOpTypes[oOperand.sType][0];
6462 #if sIdx != 'IDX_UseModRM':
6463 asColumns.append(sIdx + ',');
6464 asColumns.extend(['0,'] * (cMaxOperands - (len(asColumns) - iStart)));
6465
6466 #
6467 # Opcode and operands.
6468 #
6469 assert oInstr.sDisEnum, str(oInstr);
6470 asColumns.append(oInstr.sDisEnum + ',');
6471 iStart = len(asColumns)
6472 for oOperand in oInstr.aoOperands:
6473 asColumns.append('OP_PARM_' + g_kdOpTypes[oOperand.sType][3] + ',');
6474 asColumns.extend(['OP_PARM_NONE,'] * (cMaxOperands - (len(asColumns) - iStart)));
6475
6476 #
6477 # Flags.
6478 #
6479 sTmp = '';
6480 for sHint in sorted(oInstr.dHints.keys()):
6481 sDefine = g_kdHints[sHint];
6482 if sDefine.startswith('DISOPTYPE_'):
6483 if sTmp:
6484 sTmp += ' | ' + sDefine;
6485 else:
6486 sTmp += sDefine;
6487 if sTmp:
6488 sTmp += '),';
6489 else:
6490 sTmp += '0),';
6491 asColumns.append(sTmp);
6492
6493 #
6494 # Format the columns into a line.
6495 #
6496 aoffColumns = [4, 29, 49, 65, 77, 89, 109, 125, 141, 157, 183, 199];
6497 sLine = '';
6498 for i, s in enumerate(asColumns):
6499 if len(sLine) < aoffColumns[i]:
6500 sLine += ' ' * (aoffColumns[i] - len(sLine));
6501 else:
6502 sLine += ' ';
6503 sLine += s;
6504
6505 # OP("psrlw %Vdq,%Wdq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PSRLW, OP_PARM_Vdq, OP_PARM_Wdq, OP_PARM_NONE,
6506 # DISOPTYPE_HARMLESS),
6507 # define OP(pszOpcode, idxParse1, idxParse2, idxParse3, opcode, param1, param2, param3, optype) \
6508 # { pszOpcode, idxParse1, idxParse2, idxParse3, 0, opcode, param1, param2, param3, 0, 0, optype }
6509 return sLine;
6510
6511def __checkIfShortTable(aoTableOrdered, oMap):
6512 """
6513 Returns (iInstr, cInstructions, fShortTable)
6514 """
6515
6516 # Determin how much we can trim off.
6517 cInstructions = len(aoTableOrdered);
6518 while cInstructions > 0 and aoTableOrdered[cInstructions - 1] is None:
6519 cInstructions -= 1;
6520
6521 iInstr = 0;
6522 while iInstr < cInstructions and aoTableOrdered[iInstr] is None:
6523 iInstr += 1;
6524
6525 # If we can save more than 30%, we go for the short table version.
6526 if iInstr + len(aoTableOrdered) - cInstructions >= len(aoTableOrdered) // 30:
6527 return (iInstr, cInstructions, True);
6528 _ = oMap; # Use this for overriding.
6529
6530 # Output the full table.
6531 return (0, len(aoTableOrdered), False);
6532
6533def generateDisassemblerTables(oDstFile = sys.stdout):
6534 """
6535 Generates disassembler tables.
6536
6537 Returns exit code.
6538 """
6539
6540 #
6541 # Parse all.
6542 #
6543 try:
6544 parseAll();
6545 except Exception as oXcpt:
6546 print('error: parseAll failed: %s' % (oXcpt,), file = sys.stderr);
6547 traceback.print_exc(file = sys.stderr);
6548 return 1;
6549
6550
6551 #
6552 # The disassembler uses a slightly different table layout to save space,
6553 # since several of the prefix varia
6554 #
6555 aoDisasmMaps = [];
6556 for sName, oMap in sorted(iter(g_dInstructionMaps.items()),
6557 key = lambda aKV: aKV[1].sEncoding + ''.join(aKV[1].asLeadOpcodes)):
6558 if oMap.sSelector != 'byte+pfx':
6559 aoDisasmMaps.append(oMap);
6560 else:
6561 # Split the map by prefix.
6562 aoDisasmMaps.append(oMap.copy(oMap.sName, 'none'));
6563 aoDisasmMaps.append(oMap.copy(oMap.sName + '_66', '0x66'));
6564 aoDisasmMaps.append(oMap.copy(oMap.sName + '_F3', '0xf3'));
6565 aoDisasmMaps.append(oMap.copy(oMap.sName + '_F2', '0xf2'));
6566
6567 #
6568 # Dump each map.
6569 #
6570 asHeaderLines = [];
6571 print("debug: maps=%s\n" % (', '.join([oMap.sName for oMap in aoDisasmMaps]),), file = sys.stderr);
6572 for oMap in aoDisasmMaps:
6573 sName = oMap.sName;
6574
6575 if not sName.startswith("vex"): continue; # only looking at the vex maps at the moment.
6576
6577 #
6578 # Get the instructions for the map and see if we can do a short version or not.
6579 #
6580 aoTableOrder = oMap.getInstructionsInTableOrder();
6581 cEntriesPerByte = oMap.getEntriesPerByte();
6582 (iInstrStart, iInstrEnd, fShortTable) = __checkIfShortTable(aoTableOrder, oMap);
6583
6584 #
6585 # Output the table start.
6586 # Note! Short tables are static and only accessible via the map range record.
6587 #
6588 asLines = [];
6589 asLines.append('/* Generated from: %-11s Selector: %-7s Encoding: %-7s Lead bytes opcodes: %s */'
6590 % ( oMap.sName, oMap.sSelector, oMap.sEncoding, ' '.join(oMap.asLeadOpcodes), ));
6591 if fShortTable:
6592 asLines.append('%sconst DISOPCODE %s[] =' % ('static ' if fShortTable else '', oMap.getDisasTableName(),));
6593 else:
6594 asHeaderLines.append('extern const DISOPCODE %s[%d];' % (oMap.getDisasTableName(), iInstrEnd - iInstrStart,));
6595 asLines.append( 'const DISOPCODE %s[%d] =' % (oMap.getDisasTableName(), iInstrEnd - iInstrStart,));
6596 asLines.append('{');
6597
6598 if fShortTable and (iInstrStart & ((0x10 * cEntriesPerByte) - 1)) != 0:
6599 asLines.append(' /* %#04x: */' % (iInstrStart,));
6600
6601 #
6602 # Output the instructions.
6603 #
6604 iInstr = iInstrStart;
6605 while iInstr < iInstrEnd:
6606 oInstr = aoTableOrder[iInstr];
6607 if (iInstr & ((0x10 * cEntriesPerByte) - 1)) == 0:
6608 if iInstr != iInstrStart:
6609 asLines.append('');
6610 asLines.append(' /* %x */' % ((iInstr // cEntriesPerByte) >> 4,));
6611
6612 if oInstr is None:
6613 # Invalid. Optimize blocks of invalid instructions.
6614 cInvalidInstrs = 1;
6615 while iInstr + cInvalidInstrs < len(aoTableOrder) and aoTableOrder[iInstr + cInvalidInstrs] is None:
6616 cInvalidInstrs += 1;
6617 if (iInstr & (0x10 * cEntriesPerByte - 1)) == 0 and cInvalidInstrs >= 0x10 * cEntriesPerByte:
6618 asLines.append(' INVALID_OPCODE_BLOCK_%u,' % (0x10 * cEntriesPerByte,));
6619 iInstr += 0x10 * cEntriesPerByte - 1;
6620 elif cEntriesPerByte > 1:
6621 if (iInstr & (cEntriesPerByte - 1)) == 0 and cInvalidInstrs >= cEntriesPerByte:
6622 asLines.append(' INVALID_OPCODE_BLOCK_%u,' % (cEntriesPerByte,));
6623 iInstr += 3;
6624 else:
6625 asLines.append(' /* %#04x/%d */ INVALID_OPCODE,'
6626 % (iInstr // cEntriesPerByte, iInstr % cEntriesPerByte));
6627 else:
6628 asLines.append(' /* %#04x */ INVALID_OPCODE,' % (iInstr));
6629 elif isinstance(oInstr, list):
6630 if len(oInstr) != 0:
6631 asLines.append(' /* %#04x */ ComplicatedListStuffNeedingWrapper, /* \n -- %s */'
6632 % (iInstr, '\n -- '.join([str(oItem) for oItem in oInstr]),));
6633 else:
6634 asLines.append(__formatDisassemblerTableEntry(oInstr));
6635 else:
6636 asLines.append(__formatDisassemblerTableEntry(oInstr));
6637
6638 iInstr += 1;
6639
6640 if iInstrStart >= iInstrEnd:
6641 asLines.append(' /* dummy */ INVALID_OPCODE');
6642
6643 asLines.append('};');
6644 asLines.append('AssertCompile(RT_ELEMENTS(%s) == %s);' % (oMap.getDisasTableName(), iInstrEnd - iInstrStart,));
6645
6646 #
6647 # We always emit a map range record, assuming the linker will eliminate the unnecessary ones.
6648 #
6649 asHeaderLines.append('extern const DISOPMAPDESC %sRange;' % (oMap.getDisasRangeName()));
6650 asLines.append('const DISOPMAPDESC %s = { &%s[0], %#04x, RT_ELEMENTS(%s) };'
6651 % (oMap.getDisasRangeName(), oMap.getDisasTableName(), iInstrStart, oMap.getDisasTableName(),));
6652
6653 #
6654 # Write out the lines.
6655 #
6656 oDstFile.write('\n'.join(asLines));
6657 oDstFile.write('\n');
6658 oDstFile.write('\n');
6659 #break; #for now
6660 return 0;
6661
6662if __name__ == '__main__':
6663 sys.exit(generateDisassemblerTables());
6664
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