[36768] | 1 | /* $Id: IEMAllInstCommon.cpp.h 104206 2024-04-05 20:28:19Z vboxsync $ */
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| 2 | /** @file
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[98795] | 3 | * IEM - Instruction Decoding and Emulation, Common Bits.
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[36768] | 4 | */
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| 5 |
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| 6 | /*
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[98103] | 7 | * Copyright (C) 2011-2023 Oracle and/or its affiliates.
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[36768] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[36768] | 26 | */
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| 27 |
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[100740] | 28 | #ifndef VMM_INCLUDED_SRC_VMMAll_IEMAllInstCommon_cpp_h
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| 29 | #define VMM_INCLUDED_SRC_VMMAll_IEMAllInstCommon_cpp_h
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| 30 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 31 | # pragma once
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| 32 | #endif
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[36768] | 33 |
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[100740] | 34 |
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[94768] | 35 | /*********************************************************************************************************************************
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[98795] | 36 | * Defined Constants And Macros *
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[94768] | 37 | *********************************************************************************************************************************/
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[98795] | 38 | /** Repeats a_fn four times. For decoding tables. */
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| 39 | #define IEMOP_X4(a_fn) a_fn, a_fn, a_fn, a_fn
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[37002] | 40 |
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[94768] | 41 |
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| 42 | /*********************************************************************************************************************************
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| 43 | * Global Variables *
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| 44 | *********************************************************************************************************************************/
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| 45 | #ifndef TST_IEM_CHECK_MC
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| 46 |
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| 47 | /** Function table for the BSF instruction. */
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[104206] | 48 | IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf =
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[94768] | 49 | {
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| 50 | NULL, NULL,
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| 51 | iemAImpl_bsf_u16, NULL,
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| 52 | iemAImpl_bsf_u32, NULL,
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| 53 | iemAImpl_bsf_u64, NULL
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| 54 | };
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| 55 |
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| 56 | /** Function table for the BSF instruction, AMD EFLAGS variant. */
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[104206] | 57 | IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf_amd =
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[94768] | 58 | {
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| 59 | NULL, NULL,
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| 60 | iemAImpl_bsf_u16_amd, NULL,
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| 61 | iemAImpl_bsf_u32_amd, NULL,
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| 62 | iemAImpl_bsf_u64_amd, NULL
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| 63 | };
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| 64 |
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| 65 | /** Function table for the BSF instruction, Intel EFLAGS variant. */
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[104206] | 66 | IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf_intel =
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[94768] | 67 | {
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| 68 | NULL, NULL,
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| 69 | iemAImpl_bsf_u16_intel, NULL,
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| 70 | iemAImpl_bsf_u32_intel, NULL,
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| 71 | iemAImpl_bsf_u64_intel, NULL
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| 72 | };
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| 73 |
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| 74 | /** EFLAGS variation selection table for the BSF instruction. */
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[104206] | 75 | IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_bsf_eflags[] =
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[94768] | 76 | {
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| 77 | &g_iemAImpl_bsf,
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| 78 | &g_iemAImpl_bsf_intel,
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| 79 | &g_iemAImpl_bsf_amd,
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| 80 | &g_iemAImpl_bsf,
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| 81 | };
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| 82 |
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| 83 | /** Function table for the BSR instruction. */
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[104206] | 84 | IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr =
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[94768] | 85 | {
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| 86 | NULL, NULL,
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| 87 | iemAImpl_bsr_u16, NULL,
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| 88 | iemAImpl_bsr_u32, NULL,
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| 89 | iemAImpl_bsr_u64, NULL
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| 90 | };
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| 91 |
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| 92 | /** Function table for the BSR instruction, AMD EFLAGS variant. */
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[104206] | 93 | IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr_amd =
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[94768] | 94 | {
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| 95 | NULL, NULL,
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| 96 | iemAImpl_bsr_u16_amd, NULL,
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| 97 | iemAImpl_bsr_u32_amd, NULL,
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| 98 | iemAImpl_bsr_u64_amd, NULL
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| 99 | };
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| 100 |
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| 101 | /** Function table for the BSR instruction, Intel EFLAGS variant. */
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[104206] | 102 | IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr_intel =
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[94768] | 103 | {
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| 104 | NULL, NULL,
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| 105 | iemAImpl_bsr_u16_intel, NULL,
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| 106 | iemAImpl_bsr_u32_intel, NULL,
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| 107 | iemAImpl_bsr_u64_intel, NULL
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| 108 | };
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| 109 |
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| 110 | /** EFLAGS variation selection table for the BSR instruction. */
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[104206] | 111 | IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_bsr_eflags[] =
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[94768] | 112 | {
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| 113 | &g_iemAImpl_bsr,
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| 114 | &g_iemAImpl_bsr_intel,
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| 115 | &g_iemAImpl_bsr_amd,
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| 116 | &g_iemAImpl_bsr,
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| 117 | };
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| 118 |
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| 119 | /** Function table for the IMUL instruction. */
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[104206] | 120 | IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two =
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[94768] | 121 | {
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| 122 | NULL, NULL,
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| 123 | iemAImpl_imul_two_u16, NULL,
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| 124 | iemAImpl_imul_two_u32, NULL,
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| 125 | iemAImpl_imul_two_u64, NULL
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| 126 | };
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| 127 |
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| 128 | /** Function table for the IMUL instruction, AMD EFLAGS variant. */
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[104206] | 129 | IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two_amd =
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[94768] | 130 | {
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| 131 | NULL, NULL,
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| 132 | iemAImpl_imul_two_u16_amd, NULL,
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| 133 | iemAImpl_imul_two_u32_amd, NULL,
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| 134 | iemAImpl_imul_two_u64_amd, NULL
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| 135 | };
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| 136 |
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| 137 | /** Function table for the IMUL instruction, Intel EFLAGS variant. */
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[104206] | 138 | IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two_intel =
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[94768] | 139 | {
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| 140 | NULL, NULL,
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| 141 | iemAImpl_imul_two_u16_intel, NULL,
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| 142 | iemAImpl_imul_two_u32_intel, NULL,
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| 143 | iemAImpl_imul_two_u64_intel, NULL
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| 144 | };
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| 145 |
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| 146 | /** EFLAGS variation selection table for the IMUL instruction. */
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[104206] | 147 | IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_imul_two_eflags[] =
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[94768] | 148 | {
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| 149 | &g_iemAImpl_imul_two,
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| 150 | &g_iemAImpl_imul_two_intel,
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| 151 | &g_iemAImpl_imul_two_amd,
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| 152 | &g_iemAImpl_imul_two,
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| 153 | };
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| 154 |
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| 155 | /** EFLAGS variation selection table for the 16-bit IMUL instruction. */
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[104206] | 156 | IEM_STATIC PFNIEMAIMPLBINU16 const g_iemAImpl_imul_two_u16_eflags[] =
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[94768] | 157 | {
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| 158 | iemAImpl_imul_two_u16,
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| 159 | iemAImpl_imul_two_u16_intel,
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| 160 | iemAImpl_imul_two_u16_amd,
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| 161 | iemAImpl_imul_two_u16,
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| 162 | };
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| 163 |
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| 164 | /** EFLAGS variation selection table for the 32-bit IMUL instruction. */
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[104206] | 165 | IEM_STATIC PFNIEMAIMPLBINU32 const g_iemAImpl_imul_two_u32_eflags[] =
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[94768] | 166 | {
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| 167 | iemAImpl_imul_two_u32,
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| 168 | iemAImpl_imul_two_u32_intel,
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| 169 | iemAImpl_imul_two_u32_amd,
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| 170 | iemAImpl_imul_two_u32,
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| 171 | };
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| 172 |
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| 173 | /** EFLAGS variation selection table for the 64-bit IMUL instruction. */
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[104206] | 174 | IEM_STATIC PFNIEMAIMPLBINU64 const g_iemAImpl_imul_two_u64_eflags[] =
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[94768] | 175 | {
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| 176 | iemAImpl_imul_two_u64,
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| 177 | iemAImpl_imul_two_u64_intel,
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| 178 | iemAImpl_imul_two_u64_amd,
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| 179 | iemAImpl_imul_two_u64,
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| 180 | };
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| 181 |
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| 182 | /** Function table for the ROL instruction. */
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| 183 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rol =
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| 184 | {
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| 185 | iemAImpl_rol_u8,
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| 186 | iemAImpl_rol_u16,
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| 187 | iemAImpl_rol_u32,
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| 188 | iemAImpl_rol_u64
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| 189 | };
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| 190 |
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| 191 | /** Function table for the ROL instruction, AMD EFLAGS variant. */
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| 192 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rol_amd =
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| 193 | {
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| 194 | iemAImpl_rol_u8_amd,
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| 195 | iemAImpl_rol_u16_amd,
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| 196 | iemAImpl_rol_u32_amd,
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| 197 | iemAImpl_rol_u64_amd
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| 198 | };
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| 199 |
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| 200 | /** Function table for the ROL instruction, Intel EFLAGS variant. */
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| 201 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rol_intel =
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| 202 | {
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| 203 | iemAImpl_rol_u8_intel,
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| 204 | iemAImpl_rol_u16_intel,
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| 205 | iemAImpl_rol_u32_intel,
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| 206 | iemAImpl_rol_u64_intel
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| 207 | };
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| 208 |
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| 209 | /** EFLAGS variation selection table for the ROL instruction. */
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| 210 | IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_rol_eflags[] =
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| 211 | {
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| 212 | &g_iemAImpl_rol,
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| 213 | &g_iemAImpl_rol_intel,
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| 214 | &g_iemAImpl_rol_amd,
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| 215 | &g_iemAImpl_rol,
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| 216 | };
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| 217 |
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| 218 |
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| 219 | /** Function table for the ROR instruction. */
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| 220 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_ror =
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| 221 | {
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| 222 | iemAImpl_ror_u8,
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| 223 | iemAImpl_ror_u16,
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| 224 | iemAImpl_ror_u32,
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| 225 | iemAImpl_ror_u64
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| 226 | };
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| 227 |
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| 228 | /** Function table for the ROR instruction, AMD EFLAGS variant. */
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| 229 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_ror_amd =
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| 230 | {
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| 231 | iemAImpl_ror_u8_amd,
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| 232 | iemAImpl_ror_u16_amd,
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| 233 | iemAImpl_ror_u32_amd,
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| 234 | iemAImpl_ror_u64_amd
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| 235 | };
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| 236 |
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| 237 | /** Function table for the ROR instruction, Intel EFLAGS variant. */
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| 238 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_ror_intel =
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| 239 | {
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| 240 | iemAImpl_ror_u8_intel,
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| 241 | iemAImpl_ror_u16_intel,
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| 242 | iemAImpl_ror_u32_intel,
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| 243 | iemAImpl_ror_u64_intel
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| 244 | };
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| 245 |
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| 246 | /** EFLAGS variation selection table for the ROR instruction. */
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| 247 | IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_ror_eflags[] =
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| 248 | {
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| 249 | &g_iemAImpl_ror,
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| 250 | &g_iemAImpl_ror_intel,
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| 251 | &g_iemAImpl_ror_amd,
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| 252 | &g_iemAImpl_ror,
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| 253 | };
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| 254 |
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| 255 |
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| 256 | /** Function table for the RCL instruction. */
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| 257 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcl =
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| 258 | {
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| 259 | iemAImpl_rcl_u8,
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| 260 | iemAImpl_rcl_u16,
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| 261 | iemAImpl_rcl_u32,
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| 262 | iemAImpl_rcl_u64
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| 263 | };
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| 264 |
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| 265 | /** Function table for the RCL instruction, AMD EFLAGS variant. */
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| 266 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcl_amd =
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| 267 | {
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| 268 | iemAImpl_rcl_u8_amd,
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| 269 | iemAImpl_rcl_u16_amd,
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| 270 | iemAImpl_rcl_u32_amd,
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| 271 | iemAImpl_rcl_u64_amd
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| 272 | };
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| 273 |
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| 274 | /** Function table for the RCL instruction, Intel EFLAGS variant. */
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| 275 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcl_intel =
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| 276 | {
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| 277 | iemAImpl_rcl_u8_intel,
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| 278 | iemAImpl_rcl_u16_intel,
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| 279 | iemAImpl_rcl_u32_intel,
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| 280 | iemAImpl_rcl_u64_intel
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| 281 | };
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| 282 |
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| 283 | /** EFLAGS variation selection table for the RCL instruction. */
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| 284 | IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_rcl_eflags[] =
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| 285 | {
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| 286 | &g_iemAImpl_rcl,
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| 287 | &g_iemAImpl_rcl_intel,
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| 288 | &g_iemAImpl_rcl_amd,
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| 289 | &g_iemAImpl_rcl,
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| 290 | };
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| 291 |
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| 292 |
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| 293 | /** Function table for the RCR instruction. */
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| 294 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcr =
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| 295 | {
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| 296 | iemAImpl_rcr_u8,
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| 297 | iemAImpl_rcr_u16,
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| 298 | iemAImpl_rcr_u32,
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| 299 | iemAImpl_rcr_u64
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| 300 | };
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| 301 |
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| 302 | /** Function table for the RCR instruction, AMD EFLAGS variant. */
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| 303 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcr_amd =
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| 304 | {
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| 305 | iemAImpl_rcr_u8_amd,
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| 306 | iemAImpl_rcr_u16_amd,
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| 307 | iemAImpl_rcr_u32_amd,
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| 308 | iemAImpl_rcr_u64_amd
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| 309 | };
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| 310 |
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| 311 | /** Function table for the RCR instruction, Intel EFLAGS variant. */
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| 312 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcr_intel =
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| 313 | {
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| 314 | iemAImpl_rcr_u8_intel,
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| 315 | iemAImpl_rcr_u16_intel,
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| 316 | iemAImpl_rcr_u32_intel,
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| 317 | iemAImpl_rcr_u64_intel
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| 318 | };
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| 319 |
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| 320 | /** EFLAGS variation selection table for the RCR instruction. */
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| 321 | IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_rcr_eflags[] =
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| 322 | {
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| 323 | &g_iemAImpl_rcr,
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| 324 | &g_iemAImpl_rcr_intel,
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| 325 | &g_iemAImpl_rcr_amd,
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| 326 | &g_iemAImpl_rcr,
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| 327 | };
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| 328 |
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| 329 |
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| 330 | /** Function table for the SHL instruction. */
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| 331 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shl =
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| 332 | {
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| 333 | iemAImpl_shl_u8,
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| 334 | iemAImpl_shl_u16,
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| 335 | iemAImpl_shl_u32,
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| 336 | iemAImpl_shl_u64
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| 337 | };
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| 338 |
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| 339 | /** Function table for the SHL instruction, AMD EFLAGS variant. */
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| 340 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shl_amd =
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| 341 | {
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| 342 | iemAImpl_shl_u8_amd,
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| 343 | iemAImpl_shl_u16_amd,
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| 344 | iemAImpl_shl_u32_amd,
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| 345 | iemAImpl_shl_u64_amd
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| 346 | };
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| 347 |
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| 348 | /** Function table for the SHL instruction, Intel EFLAGS variant. */
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| 349 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shl_intel =
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| 350 | {
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| 351 | iemAImpl_shl_u8_intel,
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| 352 | iemAImpl_shl_u16_intel,
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| 353 | iemAImpl_shl_u32_intel,
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| 354 | iemAImpl_shl_u64_intel
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| 355 | };
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| 356 |
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| 357 | /** EFLAGS variation selection table for the SHL instruction. */
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| 358 | IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_shl_eflags[] =
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| 359 | {
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| 360 | &g_iemAImpl_shl,
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| 361 | &g_iemAImpl_shl_intel,
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| 362 | &g_iemAImpl_shl_amd,
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| 363 | &g_iemAImpl_shl,
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| 364 | };
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| 365 |
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| 366 |
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| 367 | /** Function table for the SHR instruction. */
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| 368 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shr =
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| 369 | {
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| 370 | iemAImpl_shr_u8,
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| 371 | iemAImpl_shr_u16,
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| 372 | iemAImpl_shr_u32,
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| 373 | iemAImpl_shr_u64
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| 374 | };
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| 375 |
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| 376 | /** Function table for the SHR instruction, AMD EFLAGS variant. */
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| 377 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shr_amd =
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| 378 | {
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| 379 | iemAImpl_shr_u8_amd,
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| 380 | iemAImpl_shr_u16_amd,
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| 381 | iemAImpl_shr_u32_amd,
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| 382 | iemAImpl_shr_u64_amd
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| 383 | };
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| 384 |
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| 385 | /** Function table for the SHR instruction, Intel EFLAGS variant. */
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| 386 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shr_intel =
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| 387 | {
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| 388 | iemAImpl_shr_u8_intel,
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| 389 | iemAImpl_shr_u16_intel,
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| 390 | iemAImpl_shr_u32_intel,
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| 391 | iemAImpl_shr_u64_intel
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---|
| 392 | };
|
---|
| 393 |
|
---|
| 394 | /** EFLAGS variation selection table for the SHR instruction. */
|
---|
| 395 | IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_shr_eflags[] =
|
---|
| 396 | {
|
---|
| 397 | &g_iemAImpl_shr,
|
---|
| 398 | &g_iemAImpl_shr_intel,
|
---|
| 399 | &g_iemAImpl_shr_amd,
|
---|
| 400 | &g_iemAImpl_shr,
|
---|
| 401 | };
|
---|
| 402 |
|
---|
| 403 |
|
---|
| 404 | /** Function table for the SAR instruction. */
|
---|
| 405 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_sar =
|
---|
| 406 | {
|
---|
| 407 | iemAImpl_sar_u8,
|
---|
| 408 | iemAImpl_sar_u16,
|
---|
| 409 | iemAImpl_sar_u32,
|
---|
| 410 | iemAImpl_sar_u64
|
---|
| 411 | };
|
---|
| 412 |
|
---|
| 413 | /** Function table for the SAR instruction, AMD EFLAGS variant. */
|
---|
| 414 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_sar_amd =
|
---|
| 415 | {
|
---|
| 416 | iemAImpl_sar_u8_amd,
|
---|
| 417 | iemAImpl_sar_u16_amd,
|
---|
| 418 | iemAImpl_sar_u32_amd,
|
---|
| 419 | iemAImpl_sar_u64_amd
|
---|
| 420 | };
|
---|
| 421 |
|
---|
| 422 | /** Function table for the SAR instruction, Intel EFLAGS variant. */
|
---|
| 423 | IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_sar_intel =
|
---|
| 424 | {
|
---|
| 425 | iemAImpl_sar_u8_intel,
|
---|
| 426 | iemAImpl_sar_u16_intel,
|
---|
| 427 | iemAImpl_sar_u32_intel,
|
---|
| 428 | iemAImpl_sar_u64_intel
|
---|
| 429 | };
|
---|
| 430 |
|
---|
| 431 | /** EFLAGS variation selection table for the SAR instruction. */
|
---|
| 432 | IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_sar_eflags[] =
|
---|
| 433 | {
|
---|
| 434 | &g_iemAImpl_sar,
|
---|
| 435 | &g_iemAImpl_sar_intel,
|
---|
| 436 | &g_iemAImpl_sar_amd,
|
---|
| 437 | &g_iemAImpl_sar,
|
---|
| 438 | };
|
---|
| 439 |
|
---|
| 440 |
|
---|
| 441 | /** Function table for the MUL instruction. */
|
---|
| 442 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_mul =
|
---|
| 443 | {
|
---|
| 444 | iemAImpl_mul_u8,
|
---|
| 445 | iemAImpl_mul_u16,
|
---|
| 446 | iemAImpl_mul_u32,
|
---|
| 447 | iemAImpl_mul_u64
|
---|
| 448 | };
|
---|
| 449 |
|
---|
| 450 | /** Function table for the MUL instruction, AMD EFLAGS variation. */
|
---|
| 451 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_mul_amd =
|
---|
| 452 | {
|
---|
| 453 | iemAImpl_mul_u8_amd,
|
---|
| 454 | iemAImpl_mul_u16_amd,
|
---|
| 455 | iemAImpl_mul_u32_amd,
|
---|
| 456 | iemAImpl_mul_u64_amd
|
---|
| 457 | };
|
---|
| 458 |
|
---|
| 459 | /** Function table for the MUL instruction, Intel EFLAGS variation. */
|
---|
| 460 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_mul_intel =
|
---|
| 461 | {
|
---|
| 462 | iemAImpl_mul_u8_intel,
|
---|
| 463 | iemAImpl_mul_u16_intel,
|
---|
| 464 | iemAImpl_mul_u32_intel,
|
---|
| 465 | iemAImpl_mul_u64_intel
|
---|
| 466 | };
|
---|
| 467 |
|
---|
| 468 | /** EFLAGS variation selection table for the MUL instruction. */
|
---|
| 469 | IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_mul_eflags[] =
|
---|
| 470 | {
|
---|
| 471 | &g_iemAImpl_mul,
|
---|
| 472 | &g_iemAImpl_mul_intel,
|
---|
| 473 | &g_iemAImpl_mul_amd,
|
---|
| 474 | &g_iemAImpl_mul,
|
---|
| 475 | };
|
---|
| 476 |
|
---|
| 477 | /** EFLAGS variation selection table for the 8-bit MUL instruction. */
|
---|
| 478 | IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_mul_u8_eflags[] =
|
---|
| 479 | {
|
---|
| 480 | iemAImpl_mul_u8,
|
---|
| 481 | iemAImpl_mul_u8_intel,
|
---|
| 482 | iemAImpl_mul_u8_amd,
|
---|
| 483 | iemAImpl_mul_u8
|
---|
| 484 | };
|
---|
| 485 |
|
---|
| 486 |
|
---|
| 487 | /** Function table for the IMUL instruction working implicitly on rAX. */
|
---|
| 488 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_imul =
|
---|
| 489 | {
|
---|
| 490 | iemAImpl_imul_u8,
|
---|
| 491 | iemAImpl_imul_u16,
|
---|
| 492 | iemAImpl_imul_u32,
|
---|
| 493 | iemAImpl_imul_u64
|
---|
| 494 | };
|
---|
| 495 |
|
---|
| 496 | /** Function table for the IMUL instruction working implicitly on rAX, AMD EFLAGS variation. */
|
---|
| 497 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_imul_amd =
|
---|
| 498 | {
|
---|
| 499 | iemAImpl_imul_u8_amd,
|
---|
| 500 | iemAImpl_imul_u16_amd,
|
---|
| 501 | iemAImpl_imul_u32_amd,
|
---|
| 502 | iemAImpl_imul_u64_amd
|
---|
| 503 | };
|
---|
| 504 |
|
---|
| 505 | /** Function table for the IMUL instruction working implicitly on rAX, Intel EFLAGS variation. */
|
---|
| 506 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_imul_intel =
|
---|
| 507 | {
|
---|
| 508 | iemAImpl_imul_u8_intel,
|
---|
| 509 | iemAImpl_imul_u16_intel,
|
---|
| 510 | iemAImpl_imul_u32_intel,
|
---|
| 511 | iemAImpl_imul_u64_intel
|
---|
| 512 | };
|
---|
| 513 |
|
---|
| 514 | /** EFLAGS variation selection table for the IMUL instruction. */
|
---|
| 515 | IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_imul_eflags[] =
|
---|
| 516 | {
|
---|
| 517 | &g_iemAImpl_imul,
|
---|
| 518 | &g_iemAImpl_imul_intel,
|
---|
| 519 | &g_iemAImpl_imul_amd,
|
---|
| 520 | &g_iemAImpl_imul,
|
---|
| 521 | };
|
---|
| 522 |
|
---|
| 523 | /** EFLAGS variation selection table for the 8-bit IMUL instruction. */
|
---|
| 524 | IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_imul_u8_eflags[] =
|
---|
| 525 | {
|
---|
| 526 | iemAImpl_imul_u8,
|
---|
| 527 | iemAImpl_imul_u8_intel,
|
---|
| 528 | iemAImpl_imul_u8_amd,
|
---|
| 529 | iemAImpl_imul_u8
|
---|
| 530 | };
|
---|
| 531 |
|
---|
| 532 |
|
---|
| 533 | /** Function table for the DIV instruction. */
|
---|
| 534 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_div =
|
---|
| 535 | {
|
---|
| 536 | iemAImpl_div_u8,
|
---|
| 537 | iemAImpl_div_u16,
|
---|
| 538 | iemAImpl_div_u32,
|
---|
| 539 | iemAImpl_div_u64
|
---|
| 540 | };
|
---|
| 541 |
|
---|
| 542 | /** Function table for the DIV instruction, AMD EFLAGS variation. */
|
---|
| 543 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_div_amd =
|
---|
| 544 | {
|
---|
| 545 | iemAImpl_div_u8_amd,
|
---|
| 546 | iemAImpl_div_u16_amd,
|
---|
| 547 | iemAImpl_div_u32_amd,
|
---|
| 548 | iemAImpl_div_u64_amd
|
---|
| 549 | };
|
---|
| 550 |
|
---|
| 551 | /** Function table for the DIV instruction, Intel EFLAGS variation. */
|
---|
| 552 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_div_intel =
|
---|
| 553 | {
|
---|
| 554 | iemAImpl_div_u8_intel,
|
---|
| 555 | iemAImpl_div_u16_intel,
|
---|
| 556 | iemAImpl_div_u32_intel,
|
---|
| 557 | iemAImpl_div_u64_intel
|
---|
| 558 | };
|
---|
| 559 |
|
---|
| 560 | /** EFLAGS variation selection table for the DIV instruction. */
|
---|
| 561 | IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_div_eflags[] =
|
---|
| 562 | {
|
---|
| 563 | &g_iemAImpl_div,
|
---|
| 564 | &g_iemAImpl_div_intel,
|
---|
| 565 | &g_iemAImpl_div_amd,
|
---|
| 566 | &g_iemAImpl_div,
|
---|
| 567 | };
|
---|
| 568 |
|
---|
| 569 | /** EFLAGS variation selection table for the 8-bit DIV instruction. */
|
---|
| 570 | IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_div_u8_eflags[] =
|
---|
| 571 | {
|
---|
| 572 | iemAImpl_div_u8,
|
---|
| 573 | iemAImpl_div_u8_intel,
|
---|
| 574 | iemAImpl_div_u8_amd,
|
---|
| 575 | iemAImpl_div_u8
|
---|
| 576 | };
|
---|
| 577 |
|
---|
| 578 |
|
---|
| 579 | /** Function table for the IDIV instruction. */
|
---|
| 580 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_idiv =
|
---|
| 581 | {
|
---|
| 582 | iemAImpl_idiv_u8,
|
---|
| 583 | iemAImpl_idiv_u16,
|
---|
| 584 | iemAImpl_idiv_u32,
|
---|
| 585 | iemAImpl_idiv_u64
|
---|
| 586 | };
|
---|
| 587 |
|
---|
| 588 | /** Function table for the IDIV instruction, AMD EFLAGS variation. */
|
---|
| 589 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_idiv_amd =
|
---|
| 590 | {
|
---|
| 591 | iemAImpl_idiv_u8_amd,
|
---|
| 592 | iemAImpl_idiv_u16_amd,
|
---|
| 593 | iemAImpl_idiv_u32_amd,
|
---|
| 594 | iemAImpl_idiv_u64_amd
|
---|
| 595 | };
|
---|
| 596 |
|
---|
| 597 | /** Function table for the IDIV instruction, Intel EFLAGS variation. */
|
---|
| 598 | IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_idiv_intel =
|
---|
| 599 | {
|
---|
| 600 | iemAImpl_idiv_u8_intel,
|
---|
| 601 | iemAImpl_idiv_u16_intel,
|
---|
| 602 | iemAImpl_idiv_u32_intel,
|
---|
| 603 | iemAImpl_idiv_u64_intel
|
---|
| 604 | };
|
---|
| 605 |
|
---|
| 606 | /** EFLAGS variation selection table for the IDIV instruction. */
|
---|
| 607 | IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_idiv_eflags[] =
|
---|
| 608 | {
|
---|
| 609 | &g_iemAImpl_idiv,
|
---|
| 610 | &g_iemAImpl_idiv_intel,
|
---|
| 611 | &g_iemAImpl_idiv_amd,
|
---|
| 612 | &g_iemAImpl_idiv,
|
---|
| 613 | };
|
---|
| 614 |
|
---|
| 615 | /** EFLAGS variation selection table for the 8-bit IDIV instruction. */
|
---|
| 616 | IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_idiv_u8_eflags[] =
|
---|
| 617 | {
|
---|
| 618 | iemAImpl_idiv_u8,
|
---|
| 619 | iemAImpl_idiv_u8_intel,
|
---|
| 620 | iemAImpl_idiv_u8_amd,
|
---|
| 621 | iemAImpl_idiv_u8
|
---|
| 622 | };
|
---|
| 623 |
|
---|
| 624 |
|
---|
| 625 | /** Function table for the SHLD instruction. */
|
---|
| 626 | IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shld =
|
---|
| 627 | {
|
---|
| 628 | iemAImpl_shld_u16,
|
---|
| 629 | iemAImpl_shld_u32,
|
---|
| 630 | iemAImpl_shld_u64,
|
---|
| 631 | };
|
---|
| 632 |
|
---|
| 633 | /** Function table for the SHLD instruction, AMD EFLAGS variation. */
|
---|
| 634 | IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shld_amd =
|
---|
| 635 | {
|
---|
| 636 | iemAImpl_shld_u16_amd,
|
---|
| 637 | iemAImpl_shld_u32_amd,
|
---|
| 638 | iemAImpl_shld_u64_amd
|
---|
| 639 | };
|
---|
| 640 |
|
---|
| 641 | /** Function table for the SHLD instruction, Intel EFLAGS variation. */
|
---|
| 642 | IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shld_intel =
|
---|
| 643 | {
|
---|
| 644 | iemAImpl_shld_u16_intel,
|
---|
| 645 | iemAImpl_shld_u32_intel,
|
---|
| 646 | iemAImpl_shld_u64_intel
|
---|
| 647 | };
|
---|
| 648 |
|
---|
| 649 | /** EFLAGS variation selection table for the SHLD instruction. */
|
---|
| 650 | IEM_STATIC const IEMOPSHIFTDBLSIZES * const g_iemAImpl_shld_eflags[] =
|
---|
| 651 | {
|
---|
| 652 | &g_iemAImpl_shld,
|
---|
| 653 | &g_iemAImpl_shld_intel,
|
---|
| 654 | &g_iemAImpl_shld_amd,
|
---|
| 655 | &g_iemAImpl_shld
|
---|
| 656 | };
|
---|
| 657 |
|
---|
| 658 | /** Function table for the SHRD instruction. */
|
---|
| 659 | IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd =
|
---|
| 660 | {
|
---|
| 661 | iemAImpl_shrd_u16,
|
---|
| 662 | iemAImpl_shrd_u32,
|
---|
| 663 | iemAImpl_shrd_u64
|
---|
| 664 | };
|
---|
| 665 |
|
---|
| 666 | /** Function table for the SHRD instruction, AMD EFLAGS variation. */
|
---|
| 667 | IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd_amd =
|
---|
| 668 | {
|
---|
| 669 | iemAImpl_shrd_u16_amd,
|
---|
| 670 | iemAImpl_shrd_u32_amd,
|
---|
| 671 | iemAImpl_shrd_u64_amd
|
---|
| 672 | };
|
---|
| 673 |
|
---|
| 674 | /** Function table for the SHRD instruction, Intel EFLAGS variation. */
|
---|
| 675 | IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd_intel =
|
---|
| 676 | {
|
---|
| 677 | iemAImpl_shrd_u16_intel,
|
---|
| 678 | iemAImpl_shrd_u32_intel,
|
---|
| 679 | iemAImpl_shrd_u64_intel
|
---|
| 680 | };
|
---|
| 681 |
|
---|
| 682 | /** EFLAGS variation selection table for the SHRD instruction. */
|
---|
| 683 | IEM_STATIC const IEMOPSHIFTDBLSIZES * const g_iemAImpl_shrd_eflags[] =
|
---|
| 684 | {
|
---|
| 685 | &g_iemAImpl_shrd,
|
---|
| 686 | &g_iemAImpl_shrd_intel,
|
---|
| 687 | &g_iemAImpl_shrd_amd,
|
---|
| 688 | &g_iemAImpl_shrd
|
---|
| 689 | };
|
---|
| 690 |
|
---|
| 691 |
|
---|
[95499] | 692 | # ifndef IEM_WITHOUT_ASSEMBLY
|
---|
[95403] | 693 | /** Function table for the VPXOR instruction */
|
---|
[104132] | 694 | IEM_STATIC const IEMOPMEDIAOPTF3 g_iemAImpl_vpand = { iemAImpl_vpand_u128, iemAImpl_vpand_u256 };
|
---|
[95441] | 695 | /** Function table for the VPXORN instruction */
|
---|
[104132] | 696 | IEM_STATIC const IEMOPMEDIAOPTF3 g_iemAImpl_vpandn = { iemAImpl_vpandn_u128, iemAImpl_vpandn_u256 };
|
---|
[95441] | 697 | /** Function table for the VPOR instruction */
|
---|
[104132] | 698 | IEM_STATIC const IEMOPMEDIAOPTF3 g_iemAImpl_vpor = { iemAImpl_vpor_u128, iemAImpl_vpor_u256 };
|
---|
[95441] | 699 | /** Function table for the VPXOR instruction */
|
---|
[104132] | 700 | IEM_STATIC const IEMOPMEDIAOPTF3 g_iemAImpl_vpxor = { iemAImpl_vpxor_u128, iemAImpl_vpxor_u256 };
|
---|
[95403] | 701 | # endif
|
---|
[95449] | 702 |
|
---|
[95441] | 703 | /** Function table for the VPAND instruction, software fallback. */
|
---|
[104132] | 704 | IEM_STATIC const IEMOPMEDIAOPTF3 g_iemAImpl_vpand_fallback = { iemAImpl_vpand_u128_fallback, iemAImpl_vpand_u256_fallback };
|
---|
[95441] | 705 | /** Function table for the VPANDN instruction, software fallback. */
|
---|
[104132] | 706 | IEM_STATIC const IEMOPMEDIAOPTF3 g_iemAImpl_vpandn_fallback= { iemAImpl_vpandn_u128_fallback, iemAImpl_vpandn_u256_fallback };
|
---|
[95441] | 707 | /** Function table for the VPOR instruction, software fallback. */
|
---|
[104132] | 708 | IEM_STATIC const IEMOPMEDIAOPTF3 g_iemAImpl_vpor_fallback = { iemAImpl_vpor_u128_fallback, iemAImpl_vpor_u256_fallback };
|
---|
[95403] | 709 | /** Function table for the VPXOR instruction, software fallback. */
|
---|
[104132] | 710 | IEM_STATIC const IEMOPMEDIAOPTF3 g_iemAImpl_vpxor_fallback = { iemAImpl_vpxor_u128_fallback, iemAImpl_vpxor_u256_fallback };
|
---|
[95403] | 711 |
|
---|
[94768] | 712 | #endif /* !TST_IEM_CHECK_MC */
|
---|
| 713 |
|
---|
| 714 |
|
---|
[36768] | 715 |
|
---|
[100740] | 716 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_ONE_BYTE_TABLE) || defined(IEM_WITH_TWO_BYTE_TABLE)
|
---|
[36768] | 717 | /** Opcodes 0xf1, 0xd6. */
|
---|
| 718 | FNIEMOP_DEF(iemOp_Invalid)
|
---|
| 719 | {
|
---|
[64545] | 720 | IEMOP_MNEMONIC(Invalid, "Invalid");
|
---|
[100072] | 721 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[36768] | 722 | }
|
---|
[100740] | 723 | #endif
|
---|
[36768] | 724 |
|
---|
| 725 |
|
---|
[100740] | 726 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_TWO_BYTE_TABLE) || defined(IEM_WITH_VEX_TABLES)
|
---|
[61885] | 727 | /** Invalid with RM byte . */
|
---|
| 728 | FNIEMOPRM_DEF(iemOp_InvalidWithRM)
|
---|
| 729 | {
|
---|
[62601] | 730 | RT_NOREF_PV(bRm);
|
---|
[64545] | 731 | IEMOP_MNEMONIC(InvalidWithRm, "InvalidWithRM");
|
---|
[100072] | 732 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[61885] | 733 | }
|
---|
[100740] | 734 | #endif
|
---|
[36768] | 735 |
|
---|
[61885] | 736 |
|
---|
[100740] | 737 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_TWO_BYTE_TABLE)
|
---|
[66810] | 738 | /** Invalid with RM byte where intel decodes any additional address encoding
|
---|
| 739 | * bytes. */
|
---|
| 740 | FNIEMOPRM_DEF(iemOp_InvalidWithRMNeedDecode)
|
---|
| 741 | {
|
---|
| 742 | IEMOP_MNEMONIC(InvalidWithRMNeedDecode, "InvalidWithRMNeedDecode");
|
---|
[100734] | 743 | if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL && IEM_IS_MODRM_MEM_MODE(bRm))
|
---|
| 744 | IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
|
---|
[66810] | 745 | IEMOP_HLP_DONE_DECODING();
|
---|
[100072] | 746 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[66810] | 747 | }
|
---|
[100740] | 748 | #endif
|
---|
[66810] | 749 |
|
---|
| 750 |
|
---|
[100740] | 751 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_TWO_BYTE_TABLE)
|
---|
[66463] | 752 | /** Invalid with RM byte where both AMD and Intel decodes any additional
|
---|
| 753 | * address encoding bytes. */
|
---|
| 754 | FNIEMOPRM_DEF(iemOp_InvalidWithRMAllNeeded)
|
---|
| 755 | {
|
---|
| 756 | IEMOP_MNEMONIC(InvalidWithRMAllNeeded, "InvalidWithRMAllNeeded");
|
---|
[95512] | 757 | if (IEM_IS_MODRM_MEM_MODE(bRm))
|
---|
[100734] | 758 | IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
|
---|
[66463] | 759 | IEMOP_HLP_DONE_DECODING();
|
---|
[100072] | 760 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[66463] | 761 | }
|
---|
[100740] | 762 | #endif
|
---|
[66463] | 763 |
|
---|
| 764 |
|
---|
[100740] | 765 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_TWO_BYTE_TABLE) || defined(IEM_WITH_VEX_TABLES)
|
---|
[65778] | 766 | /** Invalid with RM byte where intel requires 8-byte immediate.
|
---|
| 767 | * Intel will also need SIB and displacement if bRm indicates memory. */
|
---|
| 768 | FNIEMOPRM_DEF(iemOp_InvalidWithRMNeedImm8)
|
---|
| 769 | {
|
---|
| 770 | IEMOP_MNEMONIC(InvalidWithRMNeedImm8, "InvalidWithRMNeedImm8");
|
---|
| 771 | if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
|
---|
| 772 | {
|
---|
[95512] | 773 | if (IEM_IS_MODRM_MEM_MODE(bRm))
|
---|
[100734] | 774 | IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
|
---|
| 775 | uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8); RT_NOREF(bImm8);
|
---|
[65778] | 776 | }
|
---|
[66159] | 777 | IEMOP_HLP_DONE_DECODING();
|
---|
[100072] | 778 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[65778] | 779 | }
|
---|
[100740] | 780 | #endif
|
---|
[65778] | 781 |
|
---|
| 782 |
|
---|
[100740] | 783 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_TWO_BYTE_TABLE)
|
---|
[66336] | 784 | /** Invalid with RM byte where intel requires 8-byte immediate.
|
---|
| 785 | * Both AMD and Intel also needs SIB and displacement according to bRm. */
|
---|
| 786 | FNIEMOPRM_DEF(iemOp_InvalidWithRMAllNeedImm8)
|
---|
| 787 | {
|
---|
| 788 | IEMOP_MNEMONIC(InvalidWithRMAllNeedImm8, "InvalidWithRMAllNeedImm8");
|
---|
[95512] | 789 | if (IEM_IS_MODRM_MEM_MODE(bRm))
|
---|
[100734] | 790 | IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
|
---|
| 791 | uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8); RT_NOREF(bImm8);
|
---|
[66336] | 792 | IEMOP_HLP_DONE_DECODING();
|
---|
[100072] | 793 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[66336] | 794 | }
|
---|
[100740] | 795 | #endif
|
---|
[66336] | 796 |
|
---|
| 797 |
|
---|
[100740] | 798 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_TWO_BYTE_TABLE) || defined(IEM_WITH_THREE_BYTE_TABLES) || defined(IEM_WITH_VEX_TABLES)
|
---|
[65604] | 799 | /** Invalid opcode where intel requires Mod R/M sequence. */
|
---|
| 800 | FNIEMOP_DEF(iemOp_InvalidNeedRM)
|
---|
| 801 | {
|
---|
| 802 | IEMOP_MNEMONIC(InvalidNeedRM, "InvalidNeedRM");
|
---|
| 803 | if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
|
---|
| 804 | {
|
---|
| 805 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
|
---|
[95512] | 806 | if (IEM_IS_MODRM_MEM_MODE(bRm))
|
---|
[100734] | 807 | IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
|
---|
[65604] | 808 | }
|
---|
[66159] | 809 | IEMOP_HLP_DONE_DECODING();
|
---|
[100072] | 810 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[65604] | 811 | }
|
---|
[100740] | 812 | #endif
|
---|
[61885] | 813 |
|
---|
[65604] | 814 |
|
---|
[100740] | 815 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_ONE_BYTE_TABLE)
|
---|
[66463] | 816 | /** Invalid opcode where both AMD and Intel requires Mod R/M sequence. */
|
---|
| 817 | FNIEMOP_DEF(iemOp_InvalidAllNeedRM)
|
---|
| 818 | {
|
---|
| 819 | IEMOP_MNEMONIC(InvalidAllNeedRM, "InvalidAllNeedRM");
|
---|
| 820 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
|
---|
[95512] | 821 | if (IEM_IS_MODRM_MEM_MODE(bRm))
|
---|
[100734] | 822 | IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
|
---|
[66463] | 823 | IEMOP_HLP_DONE_DECODING();
|
---|
[100072] | 824 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[66463] | 825 | }
|
---|
[100740] | 826 | #endif
|
---|
[66463] | 827 |
|
---|
| 828 |
|
---|
[100740] | 829 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_TWO_BYTE_TABLE) || defined(IEM_WITH_THREE_BYTE_TABLES) || defined(IEM_WITH_VEX_TABLES)
|
---|
[65604] | 830 | /** Invalid opcode where intel requires Mod R/M sequence and 8-byte
|
---|
| 831 | * immediate. */
|
---|
| 832 | FNIEMOP_DEF(iemOp_InvalidNeedRMImm8)
|
---|
| 833 | {
|
---|
| 834 | IEMOP_MNEMONIC(InvalidNeedRMImm8, "InvalidNeedRMImm8");
|
---|
| 835 | if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
|
---|
| 836 | {
|
---|
| 837 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
|
---|
[95512] | 838 | if (IEM_IS_MODRM_MEM_MODE(bRm))
|
---|
[100734] | 839 | IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
|
---|
[65604] | 840 | uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); RT_NOREF(bImm);
|
---|
| 841 | }
|
---|
[66159] | 842 | IEMOP_HLP_DONE_DECODING();
|
---|
[100072] | 843 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[65604] | 844 | }
|
---|
[100740] | 845 | #endif
|
---|
[65604] | 846 |
|
---|
| 847 |
|
---|
[100740] | 848 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_TWO_BYTE_TABLE)
|
---|
[65604] | 849 | /** Invalid opcode where intel requires a 3rd escape byte and a Mod R/M
|
---|
| 850 | * sequence. */
|
---|
| 851 | FNIEMOP_DEF(iemOp_InvalidNeed3ByteEscRM)
|
---|
| 852 | {
|
---|
| 853 | IEMOP_MNEMONIC(InvalidNeed3ByteEscRM, "InvalidNeed3ByteEscRM");
|
---|
| 854 | if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
|
---|
| 855 | {
|
---|
| 856 | uint8_t b3rd; IEM_OPCODE_GET_NEXT_U8(&b3rd); RT_NOREF(b3rd);
|
---|
| 857 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
|
---|
[95512] | 858 | if (IEM_IS_MODRM_MEM_MODE(bRm))
|
---|
[100734] | 859 | IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
|
---|
[65604] | 860 | }
|
---|
[66159] | 861 | IEMOP_HLP_DONE_DECODING();
|
---|
[100072] | 862 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[65604] | 863 | }
|
---|
[100740] | 864 | #endif
|
---|
[65604] | 865 |
|
---|
| 866 |
|
---|
[100740] | 867 | #if defined(TST_IEM_CHECK_MC) || defined(IEM_WITH_TWO_BYTE_TABLE)
|
---|
[65604] | 868 | /** Invalid opcode where intel requires a 3rd escape byte, Mod R/M sequence, and
|
---|
| 869 | * a 8-byte immediate. */
|
---|
| 870 | FNIEMOP_DEF(iemOp_InvalidNeed3ByteEscRMImm8)
|
---|
| 871 | {
|
---|
| 872 | IEMOP_MNEMONIC(InvalidNeed3ByteEscRMImm8, "InvalidNeed3ByteEscRMImm8");
|
---|
| 873 | if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
|
---|
| 874 | {
|
---|
| 875 | uint8_t b3rd; IEM_OPCODE_GET_NEXT_U8(&b3rd); RT_NOREF(b3rd);
|
---|
| 876 | uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
|
---|
[95512] | 877 | if (IEM_IS_MODRM_MEM_MODE(bRm))
|
---|
[100734] | 878 | IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
|
---|
[65604] | 879 | uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); RT_NOREF(bImm);
|
---|
| 880 | }
|
---|
[100734] | 881 | IEMOP_HLP_DONE_DECODING();
|
---|
[100072] | 882 | IEMOP_RAISE_INVALID_OPCODE_RET();
|
---|
[65604] | 883 | }
|
---|
[100740] | 884 | #endif
|
---|
[65604] | 885 |
|
---|
[100740] | 886 | #if defined(IEM_WITH_ONE_BYTE_TABLE) || defined(IEM_WITH_TWO_BYTE_TABLE)
|
---|
| 887 |
|
---|
| 888 | /**
|
---|
| 889 | * Common 'push segment-register' helper.
|
---|
| 890 | */
|
---|
| 891 | FNIEMOP_DEF_1(iemOpCommonPushSReg, uint8_t, iReg)
|
---|
| 892 | {
|
---|
[102783] | 893 | Assert(iReg >= X86_SREG_FS || !IEM_IS_64BIT_CODE(pVCpu));
|
---|
[100740] | 894 | IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
|
---|
| 895 |
|
---|
| 896 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
| 897 | {
|
---|
| 898 | case IEMMODE_16BIT:
|
---|
[104018] | 899 | IEM_MC_BEGIN(0, 0);
|
---|
[100740] | 900 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
| 901 | IEM_MC_LOCAL(uint16_t, u16Value);
|
---|
| 902 | IEM_MC_FETCH_SREG_U16(u16Value, iReg);
|
---|
| 903 | IEM_MC_PUSH_U16(u16Value);
|
---|
| 904 | IEM_MC_ADVANCE_RIP_AND_FINISH();
|
---|
| 905 | IEM_MC_END();
|
---|
| 906 | break;
|
---|
| 907 |
|
---|
| 908 | case IEMMODE_32BIT:
|
---|
[104018] | 909 | IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0);
|
---|
[100740] | 910 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
| 911 | IEM_MC_LOCAL(uint32_t, u32Value);
|
---|
| 912 | IEM_MC_FETCH_SREG_ZX_U32(u32Value, iReg);
|
---|
[102783] | 913 | IEM_MC_PUSH_U32_SREG(u32Value); /* Intel CPUs do funny things with this instruction. */
|
---|
[100740] | 914 | IEM_MC_ADVANCE_RIP_AND_FINISH();
|
---|
| 915 | IEM_MC_END();
|
---|
| 916 | break;
|
---|
| 917 |
|
---|
| 918 | case IEMMODE_64BIT:
|
---|
[104018] | 919 | IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
|
---|
[100740] | 920 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
| 921 | IEM_MC_LOCAL(uint64_t, u64Value);
|
---|
| 922 | IEM_MC_FETCH_SREG_ZX_U64(u64Value, iReg);
|
---|
| 923 | IEM_MC_PUSH_U64(u64Value);
|
---|
| 924 | IEM_MC_ADVANCE_RIP_AND_FINISH();
|
---|
| 925 | IEM_MC_END();
|
---|
| 926 | break;
|
---|
| 927 |
|
---|
| 928 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
|
---|
| 929 | }
|
---|
| 930 | }
|
---|
| 931 |
|
---|
| 932 |
|
---|
| 933 | FNIEMOP_DEF_2(iemOpCommonLoadSRegAndGreg, uint8_t, iSegReg, uint8_t, bRm)
|
---|
| 934 | {
|
---|
| 935 | Assert(IEM_IS_MODRM_MEM_MODE(bRm)); /* Caller checks this */
|
---|
| 936 | uint8_t const iGReg = IEM_GET_MODRM_REG(pVCpu, bRm);
|
---|
| 937 |
|
---|
| 938 | switch (pVCpu->iem.s.enmEffOpSize)
|
---|
| 939 | {
|
---|
| 940 | case IEMMODE_16BIT:
|
---|
[101958] | 941 | if (iSegReg >= X86_SREG_FS || !IEM_IS_32BIT_CODE(pVCpu)) /* IEM_CIMPL_F_XXX flag are combined for whole MC block, */
|
---|
| 942 | { /* thus the duplication. */
|
---|
[104018] | 943 | IEM_MC_BEGIN(0, 0);
|
---|
[101958] | 944 | IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
|
---|
| 945 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
|
---|
| 946 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
| 947 | IEM_MC_ARG(uint16_t, offSeg, 1);
|
---|
| 948 | IEM_MC_FETCH_MEM_U16(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff); /** @todo check memory access pattern */
|
---|
| 949 | IEM_MC_ARG(uint16_t, uSel, 0);
|
---|
| 950 | IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 2);
|
---|
| 951 | IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
|
---|
| 952 | IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
|
---|
| 953 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
|
---|
[102011] | 954 | IEM_MC_CALL_CIMPL_5( 0,
|
---|
[102719] | 955 | RT_BIT_64(kIemNativeGstReg_GprFirst + iGReg)
|
---|
| 956 | | RT_BIT_64(kIemNativeGstReg_SegSelFirst + iSegReg)
|
---|
| 957 | | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + iSegReg)
|
---|
| 958 | | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + iSegReg)
|
---|
| 959 | | RT_BIT_64(kIemNativeGstReg_SegAttribFirst + iSegReg),
|
---|
[102011] | 960 | iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
|
---|
[101958] | 961 | IEM_MC_END();
|
---|
| 962 | }
|
---|
[100740] | 963 | else
|
---|
[101958] | 964 | {
|
---|
[104018] | 965 | IEM_MC_BEGIN(0, 0);
|
---|
[101958] | 966 | IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
|
---|
| 967 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
|
---|
| 968 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
| 969 | IEM_MC_ARG(uint16_t, offSeg, 1);
|
---|
| 970 | IEM_MC_FETCH_MEM_U16(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff); /** @todo check memory access pattern */
|
---|
| 971 | IEM_MC_ARG(uint16_t, uSel, 0);
|
---|
| 972 | IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 2);
|
---|
| 973 | IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
|
---|
| 974 | IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
|
---|
| 975 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
|
---|
[102011] | 976 | IEM_MC_CALL_CIMPL_5(IEM_CIMPL_F_MODE,
|
---|
[102719] | 977 | RT_BIT_64(kIemNativeGstReg_GprFirst + iGReg)
|
---|
| 978 | | RT_BIT_64(kIemNativeGstReg_SegSelFirst + iSegReg)
|
---|
| 979 | | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + iSegReg)
|
---|
| 980 | | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + iSegReg)
|
---|
| 981 | | RT_BIT_64(kIemNativeGstReg_SegAttribFirst + iSegReg),
|
---|
[102011] | 982 | iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
|
---|
[101958] | 983 | IEM_MC_END();
|
---|
| 984 | }
|
---|
[100740] | 985 |
|
---|
| 986 | case IEMMODE_32BIT:
|
---|
| 987 | if (iSegReg >= X86_SREG_FS || !IEM_IS_32BIT_CODE(pVCpu))
|
---|
[101958] | 988 | {
|
---|
[104018] | 989 | IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0);
|
---|
[101958] | 990 | IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
|
---|
| 991 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
|
---|
| 992 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
| 993 | IEM_MC_ARG(uint32_t, offSeg, 1); /** @todo check memory access pattern */
|
---|
| 994 | IEM_MC_FETCH_MEM_U32(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
|
---|
| 995 | IEM_MC_ARG(uint16_t, uSel, 0);
|
---|
| 996 | IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 4);
|
---|
| 997 | IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
|
---|
| 998 | IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
|
---|
| 999 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
|
---|
[102011] | 1000 | IEM_MC_CALL_CIMPL_5( 0,
|
---|
[102719] | 1001 | RT_BIT_64(kIemNativeGstReg_GprFirst + iGReg)
|
---|
| 1002 | | RT_BIT_64(kIemNativeGstReg_SegSelFirst + iSegReg)
|
---|
| 1003 | | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + iSegReg)
|
---|
| 1004 | | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + iSegReg)
|
---|
| 1005 | | RT_BIT_64(kIemNativeGstReg_SegAttribFirst + iSegReg),
|
---|
[102011] | 1006 | iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
|
---|
[101958] | 1007 | IEM_MC_END();
|
---|
| 1008 | }
|
---|
[100740] | 1009 | else
|
---|
[101958] | 1010 | {
|
---|
[104018] | 1011 | IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0);
|
---|
[101958] | 1012 | IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
|
---|
| 1013 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
|
---|
| 1014 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
|
---|
| 1015 | IEM_MC_ARG(uint32_t, offSeg, 1); /** @todo check memory access pattern */
|
---|
| 1016 | IEM_MC_FETCH_MEM_U32(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
|
---|
| 1017 | IEM_MC_ARG(uint16_t, uSel, 0);
|
---|
| 1018 | IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 4);
|
---|
| 1019 | IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
|
---|
| 1020 | IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
|
---|
| 1021 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
|
---|
[102011] | 1022 | IEM_MC_CALL_CIMPL_5(IEM_CIMPL_F_MODE,
|
---|
[102719] | 1023 | RT_BIT_64(kIemNativeGstReg_GprFirst + iGReg)
|
---|
| 1024 | | RT_BIT_64(kIemNativeGstReg_SegSelFirst + iSegReg)
|
---|
| 1025 | | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + iSegReg)
|
---|
| 1026 | | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + iSegReg)
|
---|
| 1027 | | RT_BIT_64(kIemNativeGstReg_SegAttribFirst + iSegReg),
|
---|
[102011] | 1028 | iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
|
---|
[101958] | 1029 | IEM_MC_END();
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| 1030 | }
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[100740] | 1031 |
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| 1032 | case IEMMODE_64BIT:
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[104018] | 1033 | IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
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[100740] | 1034 | IEM_MC_ARG(uint16_t, uSel, 0);
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| 1035 | IEM_MC_ARG(uint64_t, offSeg, 1);
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| 1036 | IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
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| 1037 | IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
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| 1038 | IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
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[102510] | 1039 | IEM_MC_NO_NATIVE_RECOMPILE(); /** @todo sort out the IEM_IS_GUEST_CPU_AMD stuff. */
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[100740] | 1040 | if (IEM_IS_GUEST_CPU_AMD(pVCpu)) /** @todo testcase: rev 3.15 of the amd manuals claims it only loads a 32-bit greg. */
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| 1041 | IEM_MC_FETCH_MEM_U32_SX_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
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| 1042 | else
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| 1043 | IEM_MC_FETCH_MEM_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
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| 1044 | IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 8);
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[101958] | 1045 | IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/*=*/iSegReg, 2);
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| 1046 | IEM_MC_ARG_CONST(uint8_t, iGRegArg, /*=*/iGReg, 3);
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| 1047 | IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/*=*/pVCpu->iem.s.enmEffOpSize, 4);
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[102011] | 1048 | IEM_MC_CALL_CIMPL_5(0,
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[102719] | 1049 | RT_BIT_64(kIemNativeGstReg_GprFirst + iGReg)
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| 1050 | | RT_BIT_64(kIemNativeGstReg_SegSelFirst + iSegReg)
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| 1051 | | RT_BIT_64(kIemNativeGstReg_SegBaseFirst + iSegReg)
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| 1052 | | RT_BIT_64(kIemNativeGstReg_SegLimitFirst + iSegReg)
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| 1053 | | RT_BIT_64(kIemNativeGstReg_SegAttribFirst + iSegReg),
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[102011] | 1054 | iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
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[100740] | 1055 | IEM_MC_END();
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| 1056 |
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| 1057 | IEM_NOT_REACHED_DEFAULT_CASE_RET();
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| 1058 | }
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| 1059 | }
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| 1060 |
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| 1061 | #endif
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| 1062 |
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| 1063 | #endif /* !VMM_INCLUDED_SRC_VMMAll_IEMAllInstCommon_cpp_h */
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