VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 99223

Last change on this file since 99223 was 99220, checked in by vboxsync, 2 years ago

Disassember,*: Start separating the disassembler into a architecture specific and common part, bugref:10394
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1/* $Id: IEMAllCImplVmxInstr.cpp 99220 2023-03-30 12:40:46Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM_VMX
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/apic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/dbgf.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/gim.h>
40#include <VBox/vmm/hm.h>
41#include <VBox/vmm/pgm.h>
42#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
43# include <VBox/vmm/hmvmxinline.h>
44#endif
45#include <VBox/vmm/tm.h>
46#include "IEMInternal.h"
47#include <VBox/vmm/vmcc.h>
48#include <VBox/log.h>
49#include <VBox/err.h>
50#include <VBox/param.h>
51#include <VBox/disopcode-x86-amd64.h>
52#include <iprt/asm-math.h>
53#include <iprt/assert.h>
54#include <iprt/string.h>
55#include <iprt/x86.h>
56
57#include "IEMInline.h"
58
59
60/*********************************************************************************************************************************
61* Defined Constants And Macros *
62*********************************************************************************************************************************/
63#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
64/**
65 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
66 * relative offsets.
67 */
68# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
69# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
70# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
71# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
72# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
73# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
75# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
76# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
77# if 0
78# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
79# endif
80# else /* !IEM_WITH_CODE_TLB */
81# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
82 do \
83 { \
84 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
86 } while (0)
87
88# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
89
90# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
91 do \
92 { \
93 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
94 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
95 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
96 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
97 } while (0)
98
99# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
100 do \
101 { \
102 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
103 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
104 } while (0)
105
106# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
107 do \
108 { \
109 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
110 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
111 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
112 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
113 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
114 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
115 } while (0)
116
117# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
118 do \
119 { \
120 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
121 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
122 } while (0)
123
124# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
125 do \
126 { \
127 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
128 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
129 } while (0)
130
131# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
132 do \
133 { \
134 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
135 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
136 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
137 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
138 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
139 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
140 } while (0)
141# endif /* !IEM_WITH_CODE_TLB */
142
143/** Check for VMX instructions requiring to be in VMX operation.
144 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
145# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
146 do \
147 { \
148 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
149 { /* likely */ } \
150 else \
151 { \
152 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
153 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
154 return iemRaiseUndefinedOpcode(a_pVCpu); \
155 } \
156 } while (0)
157
158/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
159# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
160 do \
161 { \
162 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
163 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
164 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
165 return VERR_VMX_VMENTRY_FAILED; \
166 } while (0)
167
168/** Marks a VM-exit failure with a diagnostic reason and logs. */
169# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
170 do \
171 { \
172 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
173 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
174 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
175 } while (0)
176
177/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
178# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
179 do \
180 { \
181 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
182 return VERR_VMX_VMEXIT_FAILED; \
183 } while (0)
184
185
186/*********************************************************************************************************************************
187* Global Variables *
188*********************************************************************************************************************************/
189/** @todo NSTVMX: The following VM-exit intercepts are pending:
190 * VMX_EXIT_IO_SMI
191 * VMX_EXIT_SMI
192 * VMX_EXIT_GETSEC
193 * VMX_EXIT_RSM
194 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
195 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
196 * VMX_EXIT_RDRAND
197 * VMX_EXIT_VMFUNC
198 * VMX_EXIT_ENCLS
199 * VMX_EXIT_RDSEED
200 * VMX_EXIT_PML_FULL
201 * VMX_EXIT_XSAVES
202 * VMX_EXIT_XRSTORS
203 */
204/**
205 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
206 *
207 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
208 * second dimension is the Index, see VMXVMCSFIELD.
209 */
210uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
211{
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u16HlatPrefixSize),
218 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
219 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
220 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
221 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
222 },
223 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
224 {
225 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
227 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
228 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
229 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
230 },
231 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
232 {
233 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
234 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
235 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
236 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
237 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
238 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
239 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
240 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
241 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
242 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
243 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
244 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
245 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 34 */ UINT16_MAX
247 },
248 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
249 {
250 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
251 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
252 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
253 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
254 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
255 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
256 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
257 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
258 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
259 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
260 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
261 },
262 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
263 {
264 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
265 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
266 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
267 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
268 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
269 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
270 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
271 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
272 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
273 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
274 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
275 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
276 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
277 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
278 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
279 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
280 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
281 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
282 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
283 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
284 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
285 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
286 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
287 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
288 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
289 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
290 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
291 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap),
292 /* 28 */ UINT16_MAX,
293 /* 29 */ UINT16_MAX,
294 /* 30 */ UINT16_MAX,
295 /* 31 */ RT_UOFFSETOF(VMXVVMCS, u64PconfigExitBitmap),
296 /* 32 */ RT_UOFFSETOF(VMXVVMCS, u64HlatPtr),
297 /* 33 */ UINT16_MAX,
298 /* 34 */ RT_UOFFSETOF(VMXVVMCS, u64ExitCtls2)
299 },
300 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
301 {
302 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
303 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
304 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
307 /* 33-34*/ UINT16_MAX, UINT16_MAX
308 },
309 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
310 {
311 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
312 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
313 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
314 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
315 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
316 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
317 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
318 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
319 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
320 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
321 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
322 /* 11 */ UINT16_MAX,
323 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
324 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
325 /* 21-28 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
326 /* 29-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
327 },
328 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
329 {
330 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
331 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
332 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
333 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
334 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
337 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
338 },
339 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
340 {
341 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
342 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
343 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
344 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
345 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
346 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
347 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
348 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
349 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
350 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
351 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
352 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
353 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
354 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
355 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
356 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
357 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
358 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
359 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
360 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
361 /* 34 */ UINT16_MAX
362 },
363 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
364 {
365 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
366 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
367 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
368 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
369 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
370 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
371 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
372 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
373 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
374 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
375 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
376 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
377 },
378 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
379 {
380 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
381 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
382 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
383 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
384 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
385 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
386 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
387 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
388 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
389 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
390 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
391 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
392 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
393 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
394 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
395 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
396 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
397 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
398 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
399 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
400 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
401 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
402 /* 22 */ UINT16_MAX,
403 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
404 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
410 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
411 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
412 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
413 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
414 /* 33-34 */ UINT16_MAX, UINT16_MAX
415 },
416 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
417 {
418 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
419 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
420 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
421 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
422 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
423 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
424 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
425 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
426 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
427 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
428 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
429 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
430 },
431 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
432 {
433 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
434 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
435 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
436 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
437 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
438 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
439 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
440 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
441 /* 22-29 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
442 /* 30-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
443 },
444 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
445 {
446 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
447 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
448 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
449 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
450 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
451 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
452 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
453 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
454 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
455 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
456 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
457 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
458 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
459 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
460 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
461 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
462 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
463 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
464 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
465 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
466 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
467 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
468 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
469 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
470 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
471 },
472 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
473 {
474 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
475 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
476 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
477 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
478 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
479 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
480 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
481 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
482 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
483 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
484 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
485 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
486 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
487 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
488 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
489 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
490 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
491 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
492 }
493};
494
495
496/**
497 * Gets a host selector from the VMCS.
498 *
499 * @param pVmcs Pointer to the virtual VMCS.
500 * @param iSelReg The index of the segment register (X86_SREG_XXX).
501 */
502DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
503{
504 Assert(iSegReg < X86_SREG_COUNT);
505 RTSEL HostSel;
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 HostSel = *(uint16_t *)pbField;
515 return HostSel;
516}
517
518
519/**
520 * Sets a guest segment register in the VMCS.
521 *
522 * @param pVmcs Pointer to the virtual VMCS.
523 * @param iSegReg The index of the segment register (X86_SREG_XXX).
524 * @param pSelReg Pointer to the segment register.
525 */
526static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
527{
528 Assert(pSelReg);
529 Assert(iSegReg < X86_SREG_COUNT);
530
531 /* Selector. */
532 {
533 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
534 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
535 uint8_t const uWidthType = (uWidth << 2) | uType;
536 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
537 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
538 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
539 uint8_t *pbVmcs = (uint8_t *)pVmcs;
540 uint8_t *pbField = pbVmcs + offField;
541 *(uint16_t *)pbField = pSelReg->Sel;
542 }
543
544 /* Limit. */
545 {
546 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
547 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
548 uint8_t const uWidthType = (uWidth << 2) | uType;
549 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
550 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
551 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
552 uint8_t *pbVmcs = (uint8_t *)pVmcs;
553 uint8_t *pbField = pbVmcs + offField;
554 *(uint32_t *)pbField = pSelReg->u32Limit;
555 }
556
557 /* Base. */
558 {
559 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
560 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
561 uint8_t const uWidthType = (uWidth << 2) | uType;
562 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
563 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
564 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
565 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
566 uint8_t const *pbField = pbVmcs + offField;
567 *(uint64_t *)pbField = pSelReg->u64Base;
568 }
569
570 /* Attributes. */
571 {
572 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
573 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
574 | X86DESCATTR_UNUSABLE;
575 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
576 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
577 uint8_t const uWidthType = (uWidth << 2) | uType;
578 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
579 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
580 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
581 uint8_t *pbVmcs = (uint8_t *)pVmcs;
582 uint8_t *pbField = pbVmcs + offField;
583 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
584 }
585}
586
587
588/**
589 * Gets a guest segment register from the VMCS.
590 *
591 * @returns VBox status code.
592 * @param pVmcs Pointer to the virtual VMCS.
593 * @param iSegReg The index of the segment register (X86_SREG_XXX).
594 * @param pSelReg Where to store the segment register (only updated when
595 * VINF_SUCCESS is returned).
596 *
597 * @remarks Warning! This does not validate the contents of the retrieved segment
598 * register.
599 */
600static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
601{
602 Assert(pSelReg);
603 Assert(iSegReg < X86_SREG_COUNT);
604
605 /* Selector. */
606 uint16_t u16Sel;
607 {
608 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
609 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
610 uint8_t const uWidthType = (uWidth << 2) | uType;
611 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
612 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
613 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
614 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
615 uint8_t const *pbField = pbVmcs + offField;
616 u16Sel = *(uint16_t *)pbField;
617 }
618
619 /* Limit. */
620 uint32_t u32Limit;
621 {
622 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
623 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
624 uint8_t const uWidthType = (uWidth << 2) | uType;
625 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
626 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
627 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
628 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
629 uint8_t const *pbField = pbVmcs + offField;
630 u32Limit = *(uint32_t *)pbField;
631 }
632
633 /* Base. */
634 uint64_t u64Base;
635 {
636 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
637 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
638 uint8_t const uWidthType = (uWidth << 2) | uType;
639 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
640 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
641 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
642 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
643 uint8_t const *pbField = pbVmcs + offField;
644 u64Base = *(uint64_t *)pbField;
645 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
646 }
647
648 /* Attributes. */
649 uint32_t u32Attr;
650 {
651 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
652 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
653 uint8_t const uWidthType = (uWidth << 2) | uType;
654 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
655 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
656 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
657 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
658 uint8_t const *pbField = pbVmcs + offField;
659 u32Attr = *(uint32_t *)pbField;
660 }
661
662 pSelReg->Sel = u16Sel;
663 pSelReg->ValidSel = u16Sel;
664 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
665 pSelReg->u32Limit = u32Limit;
666 pSelReg->u64Base = u64Base;
667 pSelReg->Attr.u = u32Attr;
668 return VINF_SUCCESS;
669}
670
671
672/**
673 * Converts an IEM exception event type to a VMX event type.
674 *
675 * @returns The VMX event type.
676 * @param uVector The interrupt / exception vector.
677 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
678 */
679DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
680{
681 /* Paranoia (callers may use these interchangeably). */
682 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
683 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
684 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
685 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
686 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
687 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
688 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
689 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
690 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
691 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
692 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
693 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
694
695 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
696 {
697 if (uVector == X86_XCPT_NMI)
698 return VMX_EXIT_INT_INFO_TYPE_NMI;
699 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
700 }
701
702 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
703 {
704 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
705 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
706 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
707 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
708 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
709 }
710
711 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
712 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
713}
714
715
716/**
717 * Determines whether the guest is using PAE paging given the VMCS.
718 *
719 * @returns @c true if PAE paging mode is used, @c false otherwise.
720 * @param pVmcs Pointer to the virtual VMCS.
721 *
722 * @warning Only use this prior to switching the guest-CPU state with the
723 * nested-guest CPU state!
724 */
725DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
726{
727 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
728 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
729 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
730}
731
732
733/**
734 * Sets the Exit qualification VMCS field.
735 *
736 * @param pVCpu The cross context virtual CPU structure.
737 * @param u64ExitQual The Exit qualification.
738 */
739DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
740{
741 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
742}
743
744
745/**
746 * Sets the VM-exit interruption information field.
747 *
748 * @param pVCpu The cross context virtual CPU structure.
749 * @param uExitIntInfo The VM-exit interruption information.
750 */
751DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
752{
753 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
754}
755
756
757/**
758 * Sets the VM-exit interruption error code.
759 *
760 * @param pVCpu The cross context virtual CPU structure.
761 * @param uErrCode The error code.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
764{
765 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
766}
767
768
769/**
770 * Sets the IDT-vectoring information field.
771 *
772 * @param pVCpu The cross context virtual CPU structure.
773 * @param uIdtVectorInfo The IDT-vectoring information.
774 */
775DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
776{
777 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
778}
779
780
781/**
782 * Sets the IDT-vectoring error code field.
783 *
784 * @param pVCpu The cross context virtual CPU structure.
785 * @param uErrCode The error code.
786 */
787DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
788{
789 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
790}
791
792
793/**
794 * Sets the VM-exit guest-linear address VMCS field.
795 *
796 * @param pVCpu The cross context virtual CPU structure.
797 * @param uGuestLinearAddr The VM-exit guest-linear address.
798 */
799DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
800{
801 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
802 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
803 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
804}
805
806
807/**
808 * Sets the VM-exit guest-physical address VMCS field.
809 *
810 * @param pVCpu The cross context virtual CPU structure.
811 * @param uGuestPhysAddr The VM-exit guest-physical address.
812 */
813DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
814{
815 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
816}
817
818
819/**
820 * Sets the VM-exit instruction length VMCS field.
821 *
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param cbInstr The VM-exit instruction length in bytes.
824 *
825 * @remarks Callers may clear this field to 0. Hence, this function does not check
826 * the validity of the instruction length.
827 */
828DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
829{
830 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
831}
832
833
834/**
835 * Sets the VM-exit instruction info. VMCS field.
836 *
837 * @param pVCpu The cross context virtual CPU structure.
838 * @param uExitInstrInfo The VM-exit instruction information.
839 */
840DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
841{
842 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
843}
844
845
846/**
847 * Sets the guest pending-debug exceptions field.
848 *
849 * @param pVCpu The cross context virtual CPU structure.
850 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
851 */
852DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
853{
854 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
855 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
856}
857
858
859/**
860 * Implements VMSucceed for VMX instruction success.
861 *
862 * @param pVCpu The cross context virtual CPU structure.
863 */
864DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
865{
866 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
867}
868
869
870/**
871 * Implements VMFailInvalid for VMX instruction failure.
872 *
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
876{
877 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
878}
879
880
881/**
882 * Implements VMFail for VMX instruction failure.
883 *
884 * @param pVCpu The cross context virtual CPU structure.
885 * @param enmInsErr The VM instruction error.
886 */
887DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
888{
889 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
890}
891
892
893/**
894 * Checks if the given auto-load/store MSR area count is valid for the
895 * implementation.
896 *
897 * @returns @c true if it's within the valid limit, @c false otherwise.
898 * @param pVCpu The cross context virtual CPU structure.
899 * @param uMsrCount The MSR area count to check.
900 */
901DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
902{
903 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
904 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
905 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
906 if (uMsrCount <= cMaxSupportedMsrs)
907 return true;
908 return false;
909}
910
911
912/**
913 * Flushes the current VMCS contents back to guest memory.
914 *
915 * @returns VBox status code.
916 * @param pVCpu The cross context virtual CPU structure.
917 */
918DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
919{
920 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
921 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
922 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
923 return rc;
924}
925
926
927/**
928 * Populates the current VMCS contents from guest memory.
929 *
930 * @returns VBox status code.
931 * @param pVCpu The cross context virtual CPU structure.
932 */
933DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
934{
935 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
936 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
937 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
938 return rc;
939}
940
941
942/**
943 * Gets the instruction diagnostic for segment base checks during VM-entry of a
944 * nested-guest.
945 *
946 * @param iSegReg The segment index (X86_SREG_XXX).
947 */
948static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
949{
950 switch (iSegReg)
951 {
952 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
953 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
954 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
955 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
956 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
957 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
958 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
959 }
960}
961
962
963/**
964 * Gets the instruction diagnostic for segment base checks during VM-entry of a
965 * nested-guest that is in Virtual-8086 mode.
966 *
967 * @param iSegReg The segment index (X86_SREG_XXX).
968 */
969static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
970{
971 switch (iSegReg)
972 {
973 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
974 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
975 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
976 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
977 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
978 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
979 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
980 }
981}
982
983
984/**
985 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
986 * nested-guest that is in Virtual-8086 mode.
987 *
988 * @param iSegReg The segment index (X86_SREG_XXX).
989 */
990static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
991{
992 switch (iSegReg)
993 {
994 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
995 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
996 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
997 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
998 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
999 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1000 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1001 }
1002}
1003
1004
1005/**
1006 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1007 * nested-guest that is in Virtual-8086 mode.
1008 *
1009 * @param iSegReg The segment index (X86_SREG_XXX).
1010 */
1011static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
1012{
1013 switch (iSegReg)
1014 {
1015 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1016 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1017 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1018 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1019 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1020 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1021 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1022 }
1023}
1024
1025
1026/**
1027 * Gets the instruction diagnostic for segment attributes reserved bits failure
1028 * during VM-entry of a nested-guest.
1029 *
1030 * @param iSegReg The segment index (X86_SREG_XXX).
1031 */
1032static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
1033{
1034 switch (iSegReg)
1035 {
1036 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1037 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1038 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1039 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1040 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1041 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1042 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1043 }
1044}
1045
1046
1047/**
1048 * Gets the instruction diagnostic for segment attributes descriptor-type
1049 * (code/segment or system) failure during VM-entry of a nested-guest.
1050 *
1051 * @param iSegReg The segment index (X86_SREG_XXX).
1052 */
1053static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1054{
1055 switch (iSegReg)
1056 {
1057 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1058 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1059 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1060 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1061 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1062 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1063 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1064 }
1065}
1066
1067
1068/**
1069 * Gets the instruction diagnostic for segment attributes descriptor-type
1070 * (code/segment or system) failure during VM-entry of a nested-guest.
1071 *
1072 * @param iSegReg The segment index (X86_SREG_XXX).
1073 */
1074static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1075{
1076 switch (iSegReg)
1077 {
1078 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1079 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1080 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1081 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1082 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1083 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1084 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1085 }
1086}
1087
1088
1089/**
1090 * Gets the instruction diagnostic for segment attribute granularity failure during
1091 * VM-entry of a nested-guest.
1092 *
1093 * @param iSegReg The segment index (X86_SREG_XXX).
1094 */
1095static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1096{
1097 switch (iSegReg)
1098 {
1099 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1100 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1101 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1102 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1103 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1104 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1105 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1106 }
1107}
1108
1109/**
1110 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1111 * VM-entry of a nested-guest.
1112 *
1113 * @param iSegReg The segment index (X86_SREG_XXX).
1114 */
1115static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1116{
1117 switch (iSegReg)
1118 {
1119 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1120 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1121 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1122 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1123 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1124 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1125 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1126 }
1127}
1128
1129
1130/**
1131 * Gets the instruction diagnostic for segment attribute type accessed failure
1132 * during VM-entry of a nested-guest.
1133 *
1134 * @param iSegReg The segment index (X86_SREG_XXX).
1135 */
1136static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1137{
1138 switch (iSegReg)
1139 {
1140 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1141 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1142 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1143 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1144 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1145 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1146 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1147 }
1148}
1149
1150
1151/**
1152 * Saves the guest control registers, debug registers and some MSRs are part of
1153 * VM-exit.
1154 *
1155 * @param pVCpu The cross context virtual CPU structure.
1156 */
1157static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1158{
1159 /*
1160 * Saves the guest control registers, debug registers and some MSRs.
1161 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1162 */
1163 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1164
1165 /* Save control registers. */
1166 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1167 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1168 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1169
1170 /* Save SYSENTER CS, ESP, EIP. */
1171 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1172 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1173 {
1174 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1175 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1176 }
1177 else
1178 {
1179 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1180 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1181 }
1182
1183 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1184 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1185 {
1186 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1187 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1188 }
1189
1190 /* Save PAT MSR. */
1191 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1192 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1193
1194 /* Save EFER MSR. */
1195 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1196 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1197
1198 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1199 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1200
1201 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1202}
1203
1204
1205/**
1206 * Saves the guest force-flags in preparation of entering the nested-guest.
1207 *
1208 * @param pVCpu The cross context virtual CPU structure.
1209 */
1210static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1211{
1212 /* We shouldn't be called multiple times during VM-entry. */
1213 Assert(pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit == 0);
1214
1215 /* MTF should not be set outside VMX non-root mode. */
1216 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1217
1218 /*
1219 * Preserve the required force-flags.
1220 *
1221 * We cache and clear force-flags that would affect the execution of the
1222 * nested-guest. Cached flags are then restored while returning to the guest
1223 * if necessary.
1224 *
1225 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1226 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1227 * instruction. Interrupt inhibition for any nested-guest instruction
1228 * is supplied by the guest-interruptibility state VMCS field and will
1229 * be set up as part of loading the guest state. Technically
1230 * blocking-by-STI is possible with VMLAUNCH/VMRESUME but we currently
1231 * disallow it since we can't distinguish it from blocking-by-MovSS
1232 * and no nested-hypervisor we care about uses STI immediately
1233 * followed by VMLAUNCH/VMRESUME.
1234 *
1235 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1236 * successful VM-entry (due to invalid guest-state) need to continue
1237 * blocking NMIs if it was in effect before VM-entry.
1238 *
1239 * - MTF need not be preserved as it's used only in VMX non-root mode and
1240 * is supplied through the VM-execution controls.
1241 *
1242 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1243 * we will be able to generate interrupts that may cause VM-exits for
1244 * the nested-guest.
1245 */
1246 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_INHIBIT_NMI;
1247}
1248
1249
1250/**
1251 * Restores the guest force-flags in preparation of exiting the nested-guest.
1252 *
1253 * @param pVCpu The cross context virtual CPU structure.
1254 */
1255static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1256{
1257 /** @todo r=bird: why aren't we clearing the nested guest flags first here?
1258 * If there is some other code doing that already, it would be great
1259 * to point to it here... */
1260 pVCpu->cpum.GstCtx.eflags.uBoth |= pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit;
1261 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = 0;
1262}
1263
1264
1265/**
1266 * Performs the VMX transition to/from VMX non-root mode.
1267 *
1268 * @param pVCpu The cross context virtual CPU structure.
1269*/
1270static int iemVmxTransition(PVMCPUCC pVCpu) RT_NOEXCEPT
1271{
1272 /*
1273 * Inform PGM about paging mode changes.
1274 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1275 * see comment in iemMemPageTranslateAndCheckAccess().
1276 */
1277 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1278 true /* fForce */);
1279 if (RT_SUCCESS(rc))
1280 { /* likely */ }
1281 else
1282 return rc;
1283
1284 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1285 IEMTlbInvalidateAll(pVCpu);
1286
1287 /* Inform CPUM (recompiler), can later be removed. */
1288 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1289
1290 /* Re-initialize IEM cache/state after the drastic mode switch. */
1291 iemReInitExec(pVCpu);
1292 return rc;
1293}
1294
1295
1296/**
1297 * Calculates the current VMX-preemption timer value.
1298 *
1299 * @returns The current VMX-preemption timer value.
1300 * @param pVCpu The cross context virtual CPU structure.
1301 */
1302static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1303{
1304 /*
1305 * Assume the following:
1306 * PreemptTimerShift = 5
1307 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1308 * EntryTick = 50000 (TSC at time of VM-entry)
1309 *
1310 * CurTick Delta PreemptTimerVal
1311 * ----------------------------------
1312 * 60000 10000 2
1313 * 80000 30000 1
1314 * 90000 40000 0 -> VM-exit.
1315 *
1316 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1317 * The saved VMX-preemption timer value is calculated as follows:
1318 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1319 * E.g.:
1320 * Delta = 10000
1321 * Tmp = 10000 / (2 * 10000) = 0.5
1322 * NewPt = 2 - 0.5 = 2
1323 * Delta = 30000
1324 * Tmp = 30000 / (2 * 10000) = 1.5
1325 * NewPt = 2 - 1.5 = 1
1326 * Delta = 40000
1327 * Tmp = 40000 / 20000 = 2
1328 * NewPt = 2 - 2 = 0
1329 */
1330 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1331 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1332 if (uVmcsPreemptVal > 0)
1333 {
1334 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1335 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1336 uint64_t const uDelta = uCurTick - uEntryTick;
1337 uint32_t const uPreemptTimer = uVmcsPreemptVal
1338 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1339 return uPreemptTimer;
1340 }
1341 return 0;
1342}
1343
1344
1345/**
1346 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1347 *
1348 * @param pVCpu The cross context virtual CPU structure.
1349 */
1350static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1351{
1352 /*
1353 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1354 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1355 */
1356 /* CS, SS, ES, DS, FS, GS. */
1357 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1358 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1359 {
1360 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1361 if (!pSelReg->Attr.n.u1Unusable)
1362 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1363 else
1364 {
1365 /*
1366 * For unusable segments the attributes are undefined except for CS and SS.
1367 * For the rest we don't bother preserving anything but the unusable bit.
1368 */
1369 switch (iSegReg)
1370 {
1371 case X86_SREG_CS:
1372 pVmcs->GuestCs = pSelReg->Sel;
1373 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1374 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1375 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1376 | X86DESCATTR_UNUSABLE);
1377 break;
1378
1379 case X86_SREG_SS:
1380 pVmcs->GuestSs = pSelReg->Sel;
1381 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1382 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1383 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1384 break;
1385
1386 case X86_SREG_DS:
1387 pVmcs->GuestDs = pSelReg->Sel;
1388 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1389 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1390 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1391 break;
1392
1393 case X86_SREG_ES:
1394 pVmcs->GuestEs = pSelReg->Sel;
1395 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1396 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1397 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1398 break;
1399
1400 case X86_SREG_FS:
1401 pVmcs->GuestFs = pSelReg->Sel;
1402 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1403 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1404 break;
1405
1406 case X86_SREG_GS:
1407 pVmcs->GuestGs = pSelReg->Sel;
1408 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1409 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1410 break;
1411 }
1412 }
1413 }
1414
1415 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1416 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1417 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1418 | X86DESCATTR_UNUSABLE;
1419 /* LDTR. */
1420 {
1421 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1422 pVmcs->GuestLdtr = pSelReg->Sel;
1423 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1424 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1425 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1426 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1427 }
1428
1429 /* TR. */
1430 {
1431 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1432 pVmcs->GuestTr = pSelReg->Sel;
1433 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1434 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1435 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1436 }
1437
1438 /* GDTR. */
1439 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1440 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1441
1442 /* IDTR. */
1443 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1444 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1445}
1446
1447
1448/**
1449 * Saves guest non-register state as part of VM-exit.
1450 *
1451 * @param pVCpu The cross context virtual CPU structure.
1452 * @param uExitReason The VM-exit reason.
1453 */
1454static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1455{
1456 /*
1457 * Save guest non-register state.
1458 * See Intel spec. 27.3.4 "Saving Non-Register State".
1459 */
1460 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1461
1462 /*
1463 * Activity state.
1464 * Most VM-exits will occur in the active state. However, if the first instruction
1465 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1466 * the VM-exit will be from the HLT activity state.
1467 *
1468 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1469 */
1470 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1471 * not? */
1472 EMSTATE const enmActivityState = EMGetState(pVCpu);
1473 switch (enmActivityState)
1474 {
1475 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1476 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1477 }
1478
1479 /*
1480 * Interruptibility-state.
1481 */
1482 /* NMI. */
1483 pVmcs->u32GuestIntrState = 0;
1484 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1485 {
1486 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1487 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1488 }
1489 else
1490 {
1491 if (CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx))
1492 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1493 }
1494
1495 /* Blocking-by-STI or blocking-by-MovSS. */
1496 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
1497 { /* probable */}
1498 else
1499 {
1500 if (pVCpu->cpum.GstCtx.rip == pVCpu->cpum.GstCtx.uRipInhibitInt)
1501 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS;
1502
1503 /* Clear inhibition unconditionally since we've ensured it isn't set prior to executing VMLAUNCH/VMRESUME. */
1504 CPUMClearInterruptShadow(&pVCpu->cpum.GstCtx);
1505 }
1506 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1507
1508 /*
1509 * Pending debug exceptions.
1510 *
1511 * For VM-exits where it is not applicable, we can safely zero out the field.
1512 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1513 */
1514 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1515 && uExitReason != VMX_EXIT_SMI
1516 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1517 && !VMXIsVmexitTrapLike(uExitReason))
1518 {
1519 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1520 * block-by-MovSS is in effect. */
1521 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1522 }
1523
1524 /*
1525 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1526 *
1527 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1528 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1529 */
1530 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1531 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1532 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1533
1534 /*
1535 * Save the guest PAE PDPTEs.
1536 */
1537 if ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
1538 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
1539 {
1540 /*
1541 * Without EPT or when the nested-guest is not using PAE paging, the values saved
1542 * in the VMCS during VM-exit are undefined. We zero them here for consistency.
1543 */
1544 pVmcs->u64GuestPdpte0.u = 0;
1545 pVmcs->u64GuestPdpte1.u = 0;
1546 pVmcs->u64GuestPdpte2.u = 0;
1547 pVmcs->u64GuestPdpte3.u = 0;
1548 }
1549 else
1550 {
1551 /*
1552 * With EPT and when the nested-guest is using PAE paging, we update the PDPTEs from
1553 * the nested-guest CPU context. Both IEM (Mov CRx) and hardware-assisted execution
1554 * of the nested-guest is expected to have updated them.
1555 */
1556 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1557 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1558 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1559 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1560 }
1561
1562 /* Clear PGM's copy of the EPT pointer for added safety. */
1563 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1564 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1565}
1566
1567
1568/**
1569 * Saves the guest-state as part of VM-exit.
1570 *
1571 * @returns VBox status code.
1572 * @param pVCpu The cross context virtual CPU structure.
1573 * @param uExitReason The VM-exit reason.
1574 */
1575static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1576{
1577 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1578 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1579
1580 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1581 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1582 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1583
1584 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1585}
1586
1587
1588/**
1589 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1590 *
1591 * @returns VBox status code.
1592 * @param pVCpu The cross context virtual CPU structure.
1593 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1594 */
1595static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1596{
1597 /*
1598 * Save guest MSRs.
1599 * See Intel spec. 27.4 "Saving MSRs".
1600 */
1601 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1602 const char * const pszFailure = "VMX-abort";
1603
1604 /*
1605 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1606 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1607 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1608 */
1609 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1610 if (!cMsrs)
1611 return VINF_SUCCESS;
1612
1613 /*
1614 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1615 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1616 * implementation causes a VMX-abort followed by a triple-fault.
1617 */
1618 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1619 if (fIsMsrCountValid)
1620 { /* likely */ }
1621 else
1622 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1623
1624 /*
1625 * Optimization if the nested hypervisor is using the same guest-physical page for both
1626 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1627 */
1628 PVMXAUTOMSR pMsrArea;
1629 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1630 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1631 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1632 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1633 else
1634 {
1635 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1636 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1637 if (RT_SUCCESS(rc))
1638 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1639 else
1640 {
1641 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1642 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1643 }
1644 }
1645
1646 /*
1647 * Update VM-exit MSR store area.
1648 */
1649 PVMXAUTOMSR pMsr = pMsrArea;
1650 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1651 {
1652 if ( !pMsr->u32Reserved
1653 && pMsr->u32Msr != MSR_IA32_SMBASE
1654 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1655 {
1656 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1657 if (rcStrict == VINF_SUCCESS)
1658 continue;
1659
1660 /*
1661 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1662 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1663 * recording the MSR index in the auxiliary info. field and indicated further by our
1664 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1665 * if possible, or come up with a better, generic solution.
1666 */
1667 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1668 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1669 ? kVmxVDiag_Vmexit_MsrStoreRing3
1670 : kVmxVDiag_Vmexit_MsrStore;
1671 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1672 }
1673 else
1674 {
1675 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1676 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1677 }
1678 }
1679
1680 /*
1681 * Commit the VM-exit MSR store are to guest memory.
1682 */
1683 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1684 if (RT_SUCCESS(rc))
1685 return VINF_SUCCESS;
1686
1687 NOREF(uExitReason);
1688 NOREF(pszFailure);
1689
1690 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1691 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1692}
1693
1694
1695/**
1696 * Performs a VMX abort (due to an fatal error during VM-exit).
1697 *
1698 * @returns Strict VBox status code.
1699 * @param pVCpu The cross context virtual CPU structure.
1700 * @param enmAbort The VMX abort reason.
1701 */
1702static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1703{
1704 /*
1705 * Perform the VMX abort.
1706 * See Intel spec. 27.7 "VMX Aborts".
1707 */
1708 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1709
1710 /* We don't support SMX yet. */
1711 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1712 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1713 {
1714 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1715 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1716 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1717 }
1718
1719 return VINF_EM_TRIPLE_FAULT;
1720}
1721
1722
1723/**
1724 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1725 *
1726 * @param pVCpu The cross context virtual CPU structure.
1727 */
1728static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1729{
1730 /*
1731 * Load host control registers, debug registers and MSRs.
1732 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1733 */
1734 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1735 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1736
1737 /* CR0. */
1738 {
1739 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1740 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK;
1741 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1742 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1743 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1744
1745 /* Verify we have not modified CR0 fixed bits in VMX operation. */
1746#ifdef VBOX_STRICT
1747 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
1748 bool const fUx = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1749 AssertMsg( (uValidHostCr0 & uCr0Mb1) == uCr0Mb1
1750 && (uValidHostCr0 & ~VMX_V_CR0_FIXED1) == 0,
1751 ("host=%#RX64 guest=%#RX64 mb1=%#RX64 valid_host_cr0=%#RX64 fUx=%RTbool\n",
1752 uHostCr0, uGuestCr0, uCr0Mb1, uValidHostCr0, fUx));
1753#endif
1754 Assert(!(uValidHostCr0 >> 32));
1755 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1756 }
1757
1758 /* CR4. */
1759 {
1760 /* CR4 fixed bits are not modified. */
1761 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1762 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1763 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1764 uint64_t uValidHostCr4 = (uHostCr4 & uCr4Mb0) | uCr4Mb1;
1765 if (fHostInLongMode)
1766 uValidHostCr4 |= X86_CR4_PAE;
1767 else
1768 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1769
1770 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1771 AssertMsg( (uValidHostCr4 & uCr4Mb1) == uCr4Mb1
1772 && (uValidHostCr4 & ~uCr4Mb0) == 0,
1773 ("host=%#RX64 guest=%#RX64, uCr4Mb1=%#RX64 uCr4Mb0=%#RX64 valid_host_cr4=%#RX64\n",
1774 uHostCr4, pVCpu->cpum.GstCtx.cr4, uCr4Mb1, uCr4Mb0, uValidHostCr4));
1775 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1776 }
1777
1778 /* CR3 (host value validated while checking host-state during VM-entry). */
1779 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1780
1781 /* DR7. */
1782 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1783
1784 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1785
1786 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1787 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1788 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1789 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1790
1791 /* FS, GS bases are loaded later while we load host segment registers. */
1792
1793 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1794 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1795 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1796 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1797 {
1798 if (fHostInLongMode)
1799 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1800 else
1801 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1802 }
1803
1804 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1805
1806 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1807 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1808 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1809
1810 /* We don't support IA32_BNDCFGS MSR yet. */
1811}
1812
1813
1814/**
1815 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1816 *
1817 * @param pVCpu The cross context virtual CPU structure.
1818 */
1819static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1820{
1821 /*
1822 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1823 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1824 *
1825 * Warning! Be careful to not touch fields that are reserved by VT-x,
1826 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1827 */
1828 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1829 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1830
1831 /* CS, SS, ES, DS, FS, GS. */
1832 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1833 {
1834 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1835 bool const fUnusable = RT_BOOL(HostSel == 0);
1836 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1837
1838 /* Selector. */
1839 pSelReg->Sel = HostSel;
1840 pSelReg->ValidSel = HostSel;
1841 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1842
1843 /* Limit. */
1844 pSelReg->u32Limit = 0xffffffff;
1845
1846 /* Base. */
1847 pSelReg->u64Base = 0;
1848
1849 /* Attributes. */
1850 if (iSegReg == X86_SREG_CS)
1851 {
1852 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1853 pSelReg->Attr.n.u1DescType = 1;
1854 pSelReg->Attr.n.u2Dpl = 0;
1855 pSelReg->Attr.n.u1Present = 1;
1856 pSelReg->Attr.n.u1Long = fHostInLongMode;
1857 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1858 pSelReg->Attr.n.u1Granularity = 1;
1859 Assert(!pSelReg->Attr.n.u1Unusable);
1860 Assert(!fUnusable);
1861 }
1862 else
1863 {
1864 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1865 pSelReg->Attr.n.u1DescType = 1;
1866 pSelReg->Attr.n.u2Dpl = 0;
1867 pSelReg->Attr.n.u1Present = 1;
1868 pSelReg->Attr.n.u1DefBig = 1;
1869 pSelReg->Attr.n.u1Granularity = 1;
1870 pSelReg->Attr.n.u1Unusable = fUnusable;
1871 }
1872 }
1873
1874 /* FS base. */
1875 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1876 || fHostInLongMode)
1877 {
1878 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1879 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1880 }
1881
1882 /* GS base. */
1883 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1884 || fHostInLongMode)
1885 {
1886 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1887 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1888 }
1889
1890 /* TR. */
1891 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1892 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1893 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1894 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1895 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1896 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1897 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1898 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1899 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1900 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1901 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1902 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1903 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1904
1905 /* LDTR (Warning! do not touch the base and limits here). */
1906 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1907 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1908 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1909 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1910
1911 /* GDTR. */
1912 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1913 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1914 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1915
1916 /* IDTR.*/
1917 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1918 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1919 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1920}
1921
1922
1923/**
1924 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1925 *
1926 * @returns VBox status code.
1927 * @param pVCpu The cross context virtual CPU structure.
1928 * @param uExitReason The VMX instruction name (for logging purposes).
1929 */
1930static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1931{
1932 /*
1933 * Load host MSRs.
1934 * See Intel spec. 27.6 "Loading MSRs".
1935 */
1936 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1937 const char * const pszFailure = "VMX-abort";
1938
1939 /*
1940 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1941 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1942 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1943 */
1944 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1945 if (!cMsrs)
1946 return VINF_SUCCESS;
1947
1948 /*
1949 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1950 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1951 * implementation causes a VMX-abort followed by a triple-fault.
1952 */
1953 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1954 if (fIsMsrCountValid)
1955 { /* likely */ }
1956 else
1957 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1958
1959 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1960 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1961 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1962 if (RT_SUCCESS(rc))
1963 {
1964 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1965 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1966 {
1967 if ( !pMsr->u32Reserved
1968 && pMsr->u32Msr != MSR_K8_FS_BASE
1969 && pMsr->u32Msr != MSR_K8_GS_BASE
1970 && pMsr->u32Msr != MSR_K6_EFER
1971 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1972 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1973 {
1974 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1975 if (rcStrict == VINF_SUCCESS)
1976 continue;
1977
1978 /*
1979 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1980 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1981 * recording the MSR index in the auxiliary info. field and indicated further by our
1982 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1983 * if possible, or come up with a better, generic solution.
1984 */
1985 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1986 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1987 ? kVmxVDiag_Vmexit_MsrLoadRing3
1988 : kVmxVDiag_Vmexit_MsrLoad;
1989 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1990 }
1991 else
1992 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1993 }
1994 }
1995 else
1996 {
1997 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1998 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1999 }
2000
2001 NOREF(uExitReason);
2002 NOREF(pszFailure);
2003 return VINF_SUCCESS;
2004}
2005
2006
2007/**
2008 * Loads the host state as part of VM-exit.
2009 *
2010 * @returns Strict VBox status code.
2011 * @param pVCpu The cross context virtual CPU structure.
2012 * @param uExitReason The VM-exit reason (for logging purposes).
2013 */
2014static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
2015{
2016 /*
2017 * Load host state.
2018 * See Intel spec. 27.5 "Loading Host State".
2019 */
2020 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2021 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2022
2023 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2024 if ( CPUMIsGuestInLongMode(pVCpu)
2025 && !fHostInLongMode)
2026 {
2027 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2028 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2029 }
2030
2031 /*
2032 * Check host PAE PDPTEs prior to loading the host state.
2033 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2034 */
2035 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2036 && !fHostInLongMode
2037 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2038 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2039 {
2040 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2041 if (RT_SUCCESS(rc))
2042 { /* likely*/ }
2043 else
2044 {
2045 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2046 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2047 }
2048 }
2049
2050 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2051 iemVmxVmexitLoadHostSegRegs(pVCpu);
2052
2053 /*
2054 * Load host RIP, RSP and RFLAGS.
2055 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2056 */
2057 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2058 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2059 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2060
2061 /* Clear address range monitoring. */
2062 EMMonitorWaitClear(pVCpu);
2063
2064 /* Perform the VMX transition (PGM updates). */
2065 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2066 if (rcStrict == VINF_SUCCESS)
2067 { /* likely */ }
2068 else if (RT_SUCCESS(rcStrict))
2069 {
2070 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2071 uExitReason));
2072 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2073 }
2074 else
2075 {
2076 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2077 return VBOXSTRICTRC_VAL(rcStrict);
2078 }
2079
2080 Assert(rcStrict == VINF_SUCCESS);
2081
2082 /* Load MSRs from the VM-exit auto-load MSR area. */
2083 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2084 if (RT_FAILURE(rc))
2085 {
2086 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2087 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2088 }
2089 return VINF_SUCCESS;
2090}
2091
2092
2093/**
2094 * Gets VM-exit instruction information along with any displacement for an
2095 * instruction VM-exit.
2096 *
2097 * @returns The VM-exit instruction information.
2098 * @param pVCpu The cross context virtual CPU structure.
2099 * @param uExitReason The VM-exit reason.
2100 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2101 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2102 * NULL.
2103 */
2104static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2105{
2106 RTGCPTR GCPtrDisp;
2107 VMXEXITINSTRINFO ExitInstrInfo;
2108 ExitInstrInfo.u = 0;
2109
2110 /*
2111 * Get and parse the ModR/M byte from our decoded opcodes.
2112 */
2113 uint8_t bRm;
2114 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2115 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2116 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2117 {
2118 /*
2119 * ModR/M indicates register addressing.
2120 *
2121 * The primary/secondary register operands are reported in the iReg1 or iReg2
2122 * fields depending on whether it is a read/write form.
2123 */
2124 uint8_t idxReg1;
2125 uint8_t idxReg2;
2126 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2127 {
2128 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2129 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2130 }
2131 else
2132 {
2133 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2134 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2135 }
2136 ExitInstrInfo.All.u2Scaling = 0;
2137 ExitInstrInfo.All.iReg1 = idxReg1;
2138 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2139 ExitInstrInfo.All.fIsRegOperand = 1;
2140 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2141 ExitInstrInfo.All.iSegReg = 0;
2142 ExitInstrInfo.All.iIdxReg = 0;
2143 ExitInstrInfo.All.fIdxRegInvalid = 1;
2144 ExitInstrInfo.All.iBaseReg = 0;
2145 ExitInstrInfo.All.fBaseRegInvalid = 1;
2146 ExitInstrInfo.All.iReg2 = idxReg2;
2147
2148 /* Displacement not applicable for register addressing. */
2149 GCPtrDisp = 0;
2150 }
2151 else
2152 {
2153 /*
2154 * ModR/M indicates memory addressing.
2155 */
2156 uint8_t uScale = 0;
2157 bool fBaseRegValid = false;
2158 bool fIdxRegValid = false;
2159 uint8_t iBaseReg = 0;
2160 uint8_t iIdxReg = 0;
2161 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2162 {
2163 /*
2164 * Parse the ModR/M, displacement for 16-bit addressing mode.
2165 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2166 */
2167 uint16_t u16Disp = 0;
2168 uint8_t const offDisp = offModRm + sizeof(bRm);
2169 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2170 {
2171 /* Displacement without any registers. */
2172 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2173 }
2174 else
2175 {
2176 /* Register (index and base). */
2177 switch (bRm & X86_MODRM_RM_MASK)
2178 {
2179 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2180 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2181 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2182 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2183 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2184 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2185 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2186 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2187 }
2188
2189 /* Register + displacement. */
2190 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2191 {
2192 case 0: break;
2193 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2194 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2195 default:
2196 {
2197 /* Register addressing, handled at the beginning. */
2198 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2199 break;
2200 }
2201 }
2202 }
2203
2204 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2205 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2206 }
2207 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2208 {
2209 /*
2210 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2211 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2212 */
2213 uint32_t u32Disp = 0;
2214 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2215 {
2216 /* Displacement without any registers. */
2217 uint8_t const offDisp = offModRm + sizeof(bRm);
2218 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2219 }
2220 else
2221 {
2222 /* Register (and perhaps scale, index and base). */
2223 uint8_t offDisp = offModRm + sizeof(bRm);
2224 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2225 if (iBaseReg == 4)
2226 {
2227 /* An SIB byte follows the ModR/M byte, parse it. */
2228 uint8_t bSib;
2229 uint8_t const offSib = offModRm + sizeof(bRm);
2230 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2231
2232 /* A displacement may follow SIB, update its offset. */
2233 offDisp += sizeof(bSib);
2234
2235 /* Get the scale. */
2236 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2237
2238 /* Get the index register. */
2239 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2240 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2241
2242 /* Get the base register. */
2243 iBaseReg = bSib & X86_SIB_BASE_MASK;
2244 fBaseRegValid = true;
2245 if (iBaseReg == 5)
2246 {
2247 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2248 {
2249 /* Mod is 0 implies a 32-bit displacement with no base. */
2250 fBaseRegValid = false;
2251 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2252 }
2253 else
2254 {
2255 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2256 iBaseReg = X86_GREG_xBP;
2257 }
2258 }
2259 }
2260
2261 /* Register + displacement. */
2262 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2263 {
2264 case 0: /* Handled above */ break;
2265 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2266 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2267 default:
2268 {
2269 /* Register addressing, handled at the beginning. */
2270 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2271 break;
2272 }
2273 }
2274 }
2275
2276 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2277 }
2278 else
2279 {
2280 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2281
2282 /*
2283 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2284 * See Intel instruction spec. 2.2 "IA-32e Mode".
2285 */
2286 uint64_t u64Disp = 0;
2287 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2288 if (fRipRelativeAddr)
2289 {
2290 /*
2291 * RIP-relative addressing mode.
2292 *
2293 * The displacement is 32-bit signed implying an offset range of +/-2G.
2294 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2295 */
2296 uint8_t const offDisp = offModRm + sizeof(bRm);
2297 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2298 }
2299 else
2300 {
2301 uint8_t offDisp = offModRm + sizeof(bRm);
2302
2303 /*
2304 * Register (and perhaps scale, index and base).
2305 *
2306 * REX.B extends the most-significant bit of the base register. However, REX.B
2307 * is ignored while determining whether an SIB follows the opcode. Hence, we
2308 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2309 *
2310 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2311 */
2312 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2313 if (iBaseReg == 4)
2314 {
2315 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2316 uint8_t bSib;
2317 uint8_t const offSib = offModRm + sizeof(bRm);
2318 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2319
2320 /* Displacement may follow SIB, update its offset. */
2321 offDisp += sizeof(bSib);
2322
2323 /* Get the scale. */
2324 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2325
2326 /* Get the index. */
2327 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2328 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2329
2330 /* Get the base. */
2331 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2332 fBaseRegValid = true;
2333 if (iBaseReg == 5)
2334 {
2335 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2336 {
2337 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2338 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2339 }
2340 else
2341 {
2342 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2343 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2344 }
2345 }
2346 }
2347 iBaseReg |= pVCpu->iem.s.uRexB;
2348
2349 /* Register + displacement. */
2350 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2351 {
2352 case 0: /* Handled above */ break;
2353 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2354 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2355 default:
2356 {
2357 /* Register addressing, handled at the beginning. */
2358 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2359 break;
2360 }
2361 }
2362 }
2363
2364 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2365 }
2366
2367 /*
2368 * The primary or secondary register operand is reported in iReg2 depending
2369 * on whether the primary operand is in read/write form.
2370 */
2371 uint8_t idxReg2;
2372 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2373 {
2374 idxReg2 = bRm & X86_MODRM_RM_MASK;
2375 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2376 idxReg2 |= pVCpu->iem.s.uRexB;
2377 }
2378 else
2379 {
2380 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2381 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2382 idxReg2 |= pVCpu->iem.s.uRexReg;
2383 }
2384 ExitInstrInfo.All.u2Scaling = uScale;
2385 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2386 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2387 ExitInstrInfo.All.fIsRegOperand = 0;
2388 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2389 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2390 ExitInstrInfo.All.iIdxReg = iIdxReg;
2391 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2392 ExitInstrInfo.All.iBaseReg = iBaseReg;
2393 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2394 ExitInstrInfo.All.iReg2 = idxReg2;
2395 }
2396
2397 /*
2398 * Handle exceptions to the norm for certain instructions.
2399 * (e.g. some instructions convey an instruction identity in place of iReg2).
2400 */
2401 switch (uExitReason)
2402 {
2403 case VMX_EXIT_GDTR_IDTR_ACCESS:
2404 {
2405 Assert(VMXINSTRID_IS_VALID(uInstrId));
2406 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2407 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2408 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2409 break;
2410 }
2411
2412 case VMX_EXIT_LDTR_TR_ACCESS:
2413 {
2414 Assert(VMXINSTRID_IS_VALID(uInstrId));
2415 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2416 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2417 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2418 break;
2419 }
2420
2421 case VMX_EXIT_RDRAND:
2422 case VMX_EXIT_RDSEED:
2423 {
2424 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2425 break;
2426 }
2427 }
2428
2429 /* Update displacement and return the constructed VM-exit instruction information field. */
2430 if (pGCPtrDisp)
2431 *pGCPtrDisp = GCPtrDisp;
2432
2433 return ExitInstrInfo.u;
2434}
2435
2436
2437/**
2438 * VMX VM-exit handler.
2439 *
2440 * @returns Strict VBox status code.
2441 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2442 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2443 * triple-fault.
2444 *
2445 * @param pVCpu The cross context virtual CPU structure.
2446 * @param uExitReason The VM-exit reason.
2447 * @param u64ExitQual The Exit qualification.
2448 *
2449 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2450 * called. Failures during VM-entry can cause VM-exits as well, so we
2451 * -cannot- assert we're in VMX non-root mode here.
2452 */
2453VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2454{
2455# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2456 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2457 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2458 return VERR_IEM_IPE_7;
2459# else
2460 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2461
2462 /* Just count this as an exit and be done with that. */
2463 pVCpu->iem.s.cPotentialExits++;
2464
2465 /*
2466 * Import all the guest-CPU state.
2467 *
2468 * HM on returning to guest execution would have to reset up a whole lot of state
2469 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2470 * the state and flag reloading the entire state on re-entry. So import the entire
2471 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2472 */
2473 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2474
2475 /*
2476 * Ensure VM-entry interruption information valid bit is cleared.
2477 *
2478 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2479 * by invalid-guest state or machine-check exceptions) also clear this bit.
2480 *
2481 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2482 */
2483 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2484 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2485
2486 /*
2487 * Update the VM-exit reason and Exit qualification.
2488 * Other VMCS read-only data fields are expected to be updated by the caller already.
2489 */
2490 pVmcs->u32RoExitReason = uExitReason;
2491 pVmcs->u64RoExitQual.u = u64ExitQual;
2492
2493 Log2(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 eflags=%#RX32\n", uExitReason,
2494 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2495 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.eflags.u));
2496
2497 /*
2498 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2499 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2500 */
2501 {
2502 uint8_t uVector;
2503 uint32_t fFlags;
2504 uint32_t uErrCode;
2505 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2506 if (fInEventDelivery)
2507 {
2508 /*
2509 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2510 * caused by a triple-fault or the original event results in a double-fault that
2511 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2512 * original event information into the IDT-vectoring information fields.
2513 *
2514 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2515 */
2516 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2517 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2518 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2519 {
2520 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2521 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2522 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2523 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2524 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2525 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2526 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2527 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2528 Log2(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2529 pVCpu->cpum.GstCtx.cr2));
2530 }
2531 }
2532 }
2533
2534 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2535 Assert(pVmcs->u64RoIoRcx.u == 0);
2536 Assert(pVmcs->u64RoIoRsi.u == 0);
2537 Assert(pVmcs->u64RoIoRdi.u == 0);
2538 Assert(pVmcs->u64RoIoRip.u == 0);
2539
2540 /*
2541 * Save the guest state back into the VMCS.
2542 * We only need to save the state when the VM-entry was successful.
2543 */
2544 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2545 if (!fVmentryFailed)
2546 {
2547 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2548 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2549 {
2550 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2551 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2552 }
2553
2554 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2555 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2556
2557 /*
2558 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2559 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2560 *
2561 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2562 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2563 * as guest-CPU state would not been modified. Hence for now, we do this only when
2564 * the VM-entry succeeded.
2565 */
2566 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2567 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2568 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2569 {
2570 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2571 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2572 else
2573 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2574 }
2575
2576 /*
2577 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2578 * occurs in enclave mode/SMM which we don't support yet.
2579 *
2580 * If we ever add support for it, we can pass just the lower bits to the functions
2581 * below, till then an assert should suffice.
2582 */
2583 Assert(!RT_HI_U16(uExitReason));
2584
2585 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2586 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2587 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2588 if (RT_SUCCESS(rc))
2589 { /* likely */ }
2590 else
2591 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2592
2593 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2594 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit &= ~CPUMCTX_INHIBIT_NMI;
2595 }
2596 else
2597 {
2598 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2599 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2600 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2601 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2602 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2603 }
2604
2605 /*
2606 * Stop any running VMX-preemption timer if necessary.
2607 */
2608 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2609 CPUMStopGuestVmxPremptTimer(pVCpu);
2610
2611 /*
2612 * Clear any pending VMX nested-guest force-flags.
2613 * These force-flags have no effect on (outer) guest execution and will
2614 * be re-evaluated and setup on the next nested-guest VM-entry.
2615 */
2616 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2617
2618 /*
2619 * We're no longer in nested-guest execution mode.
2620 *
2621 * It is important to do this prior to loading the host state because
2622 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2623 * second-level address translation while switching to host CR3.
2624 */
2625 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2626
2627 /* Restore the host (outer guest) state. */
2628 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2629 if (RT_SUCCESS(rcStrict))
2630 {
2631 Assert(rcStrict == VINF_SUCCESS);
2632 rcStrict = VINF_VMX_VMEXIT;
2633 }
2634 else
2635 Log(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2636
2637 /*
2638 * Restore non-zero Secondary-processor based VM-execution controls
2639 * when the "activate secondary controls" bit was not set.
2640 */
2641 if (pVmcs->u32RestoreProcCtls2)
2642 {
2643 Assert(!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS));
2644 pVmcs->u32ProcCtls2 = pVmcs->u32RestoreProcCtls2;
2645 pVmcs->u32RestoreProcCtls2 = 0;
2646 }
2647
2648 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2649 {
2650 /* Notify HM that the current VMCS fields have been modified. */
2651 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2652
2653 /* Notify HM that we've completed the VM-exit. */
2654 HMNotifyVmxNstGstVmexit(pVCpu);
2655 }
2656
2657# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2658 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2659 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2660 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2661 if (rcSched != VINF_SUCCESS)
2662 iemSetPassUpStatus(pVCpu, rcSched);
2663# endif
2664 return rcStrict;
2665# endif
2666}
2667
2668
2669/**
2670 * VMX VM-exit handler for VM-exits due to instruction execution.
2671 *
2672 * This is intended for instructions where the caller provides all the relevant
2673 * VM-exit information.
2674 *
2675 * @returns Strict VBox status code.
2676 * @param pVCpu The cross context virtual CPU structure.
2677 * @param pExitInfo Pointer to the VM-exit information.
2678 */
2679static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2680{
2681 /*
2682 * For instructions where any of the following fields are not applicable:
2683 * - Exit qualification must be cleared.
2684 * - VM-exit instruction info. is undefined.
2685 * - Guest-linear address is undefined.
2686 * - Guest-physical address is undefined.
2687 *
2688 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2689 * instruction execution. For VM-exits that are not due to instruction execution this
2690 * field is undefined.
2691 *
2692 * In our implementation in IEM, all undefined fields are generally cleared. However,
2693 * if the caller supplies information (from say the physical CPU directly) it is
2694 * then possible that the undefined fields are not cleared.
2695 *
2696 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2697 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2698 */
2699 Assert(pExitInfo);
2700 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2701 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2702 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2703
2704 /* Update all the relevant fields from the VM-exit instruction information struct. */
2705 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2706 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2707 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2708 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2709
2710 /* Perform the VM-exit. */
2711 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2712}
2713
2714
2715/**
2716 * VMX VM-exit handler for VM-exits due to instruction execution.
2717 *
2718 * This is intended for instructions that only provide the VM-exit instruction
2719 * length.
2720 *
2721 * @param pVCpu The cross context virtual CPU structure.
2722 * @param uExitReason The VM-exit reason.
2723 * @param cbInstr The instruction length in bytes.
2724 */
2725VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2726{
2727#ifdef VBOX_STRICT
2728 /*
2729 * To prevent us from shooting ourselves in the foot.
2730 * The follow instructions should convey more than just the instruction length.
2731 */
2732 switch (uExitReason)
2733 {
2734 case VMX_EXIT_INVEPT:
2735 case VMX_EXIT_INVPCID:
2736 case VMX_EXIT_INVVPID:
2737 case VMX_EXIT_LDTR_TR_ACCESS:
2738 case VMX_EXIT_GDTR_IDTR_ACCESS:
2739 case VMX_EXIT_VMCLEAR:
2740 case VMX_EXIT_VMPTRLD:
2741 case VMX_EXIT_VMPTRST:
2742 case VMX_EXIT_VMREAD:
2743 case VMX_EXIT_VMWRITE:
2744 case VMX_EXIT_VMXON:
2745 case VMX_EXIT_XRSTORS:
2746 case VMX_EXIT_XSAVES:
2747 case VMX_EXIT_RDRAND:
2748 case VMX_EXIT_RDSEED:
2749 case VMX_EXIT_IO_INSTR:
2750 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2751 break;
2752 }
2753#endif
2754
2755 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_INSTR_LEN(uExitReason, cbInstr);
2756 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2757}
2758
2759
2760/**
2761 * Interface for HM and EM to emulate VM-exit due to a triple-fault.
2762 *
2763 * @returns Strict VBox status code.
2764 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2765 * @thread EMT(pVCpu)
2766 */
2767VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2768{
2769 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2770 Assert(!pVCpu->iem.s.cActiveMappings);
2771 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2772}
2773
2774
2775/**
2776 * Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2777 *
2778 * @returns Strict VBox status code.
2779 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2780 * @param uVector The SIPI vector.
2781 * @thread EMT(pVCpu)
2782 */
2783VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2784{
2785 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2786 Assert(!pVCpu->iem.s.cActiveMappings);
2787 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2788}
2789
2790
2791/**
2792 * Interface for HM and EM to emulate a VM-exit.
2793 *
2794 * If a specialized version of a VM-exit handler exists, that must be used instead.
2795 *
2796 * @returns Strict VBox status code.
2797 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2798 * @param uExitReason The VM-exit reason.
2799 * @param u64ExitQual The Exit qualification.
2800 * @thread EMT(pVCpu)
2801 */
2802VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2803{
2804 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2805 Assert(!pVCpu->iem.s.cActiveMappings);
2806 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2807}
2808
2809
2810/**
2811 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2812 *
2813 * This is meant to be used for those instructions that VMX provides additional
2814 * decoding information beyond just the instruction length!
2815 *
2816 * @returns Strict VBox status code.
2817 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2818 * @param pExitInfo Pointer to the VM-exit information.
2819 * @thread EMT(pVCpu)
2820 */
2821VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2822{
2823 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2824 Assert(!pVCpu->iem.s.cActiveMappings);
2825 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2826}
2827
2828
2829/**
2830 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2831 *
2832 * This is meant to be used for those instructions that VMX provides only the
2833 * instruction length.
2834 *
2835 * @returns Strict VBox status code.
2836 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2837 * @param pExitInfo Pointer to the VM-exit information.
2838 * @param cbInstr The instruction length in bytes.
2839 * @thread EMT(pVCpu)
2840 */
2841VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2842{
2843 VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2844 Assert(!pVCpu->iem.s.cActiveMappings);
2845 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2846}
2847
2848
2849/**
2850 * VMX VM-exit handler for VM-exits due to instruction execution.
2851 *
2852 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2853 * instruction information and Exit qualification fields.
2854 *
2855 * @param pVCpu The cross context virtual CPU structure.
2856 * @param uExitReason The VM-exit reason.
2857 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2858 * @param cbInstr The instruction length in bytes.
2859 *
2860 * @remarks Do not use this for INS/OUTS instruction.
2861 */
2862VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2863{
2864#ifdef VBOX_STRICT
2865 /*
2866 * To prevent us from shooting ourselves in the foot.
2867 * The follow instructions convey specific info that require using their respective handlers.
2868 */
2869 switch (uExitReason)
2870 {
2871 case VMX_EXIT_INVEPT:
2872 case VMX_EXIT_INVPCID:
2873 case VMX_EXIT_INVVPID:
2874 case VMX_EXIT_LDTR_TR_ACCESS:
2875 case VMX_EXIT_GDTR_IDTR_ACCESS:
2876 case VMX_EXIT_VMCLEAR:
2877 case VMX_EXIT_VMPTRLD:
2878 case VMX_EXIT_VMPTRST:
2879 case VMX_EXIT_VMREAD:
2880 case VMX_EXIT_VMWRITE:
2881 case VMX_EXIT_VMXON:
2882 case VMX_EXIT_XRSTORS:
2883 case VMX_EXIT_XSAVES:
2884 case VMX_EXIT_RDRAND:
2885 case VMX_EXIT_RDSEED:
2886 break;
2887 default:
2888 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2889 break;
2890 }
2891#endif
2892
2893 /*
2894 * Update the Exit qualification field with displacement bytes.
2895 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2896 */
2897 /* Construct the VM-exit instruction information. */
2898 RTGCPTR GCPtrDisp;
2899 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2900
2901 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO(uExitReason, GCPtrDisp, uInstrInfo, cbInstr);
2902 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2903}
2904
2905
2906/**
2907 * VMX VM-exit handler for VM-exits due to INVLPG.
2908 *
2909 * @returns Strict VBox status code.
2910 * @param pVCpu The cross context virtual CPU structure.
2911 * @param GCPtrPage The guest-linear address of the page being invalidated.
2912 * @param cbInstr The instruction length in bytes.
2913 */
2914VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2915{
2916 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_INVLPG, GCPtrPage, cbInstr);
2917 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2918 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2919}
2920
2921
2922/**
2923 * VMX VM-exit handler for VM-exits due to LMSW.
2924 *
2925 * @returns Strict VBox status code.
2926 * @param pVCpu The cross context virtual CPU structure.
2927 * @param uGuestCr0 The current guest CR0.
2928 * @param pu16NewMsw The machine-status word specified in LMSW's source
2929 * operand. This will be updated depending on the VMX
2930 * guest/host CR0 mask if LMSW is not intercepted.
2931 * @param GCPtrEffDst The guest-linear address of the source operand in case
2932 * of a memory operand. For register operand, pass
2933 * NIL_RTGCPTR.
2934 * @param cbInstr The instruction length in bytes.
2935 */
2936VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2937 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2938{
2939 Assert(pu16NewMsw);
2940
2941 uint16_t const uNewMsw = *pu16NewMsw;
2942 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2943 {
2944 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2945 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2946 VMXVEXITINFO ExitInfo
2947 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2948 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2949 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2950 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw)
2951 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW),
2952 cbInstr);
2953 if (fMemOperand)
2954 {
2955 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2956 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2957 }
2958 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2959 }
2960
2961 /*
2962 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2963 * CR0 guest/host mask must be left unmodified.
2964 *
2965 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2966 */
2967 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2968 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2969 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2970
2971 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2972}
2973
2974
2975/**
2976 * VMX VM-exit handler for VM-exits due to CLTS.
2977 *
2978 * @returns Strict VBox status code.
2979 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2980 * VM-exit but must not modify the guest CR0.TS bit.
2981 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2982 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2983 * CR0 fixed bits in VMX operation).
2984 * @param pVCpu The cross context virtual CPU structure.
2985 * @param cbInstr The instruction length in bytes.
2986 */
2987VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2988{
2989 /*
2990 * If CR0.TS is owned by the host:
2991 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2992 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2993 * CLTS instruction completes without clearing CR0.TS.
2994 *
2995 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2996 */
2997 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2998 if (fGstHostMask & X86_CR0_TS)
2999 {
3000 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u & X86_CR0_TS)
3001 {
3002 Log2(("clts: Guest intercept -> VM-exit\n"));
3003 VMXVEXITINFO const ExitInfo
3004 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3005 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3006 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3007 VMX_EXIT_QUAL_CRX_ACCESS_CLTS),
3008 cbInstr);
3009 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3010 }
3011 return VINF_VMX_MODIFIES_BEHAVIOR;
3012 }
3013
3014 /*
3015 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3016 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3017 */
3018 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3019}
3020
3021
3022/**
3023 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3024 * (CR0/CR4 write).
3025 *
3026 * @returns Strict VBox status code.
3027 * @param pVCpu The cross context virtual CPU structure.
3028 * @param iCrReg The control register (either CR0 or CR4).
3029 * @param uGuestCrX The current guest CR0/CR4.
3030 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
3031 * VM-exit is caused.
3032 * @param iGReg The general register from which the CR0/CR4 value is being
3033 * loaded.
3034 * @param cbInstr The instruction length in bytes.
3035 */
3036VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
3037 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3038{
3039 Assert(puNewCrX);
3040 Assert(iCrReg == 0 || iCrReg == 4);
3041 Assert(iGReg < X86_GREG_COUNT);
3042
3043 uint64_t const uNewCrX = *puNewCrX;
3044 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3045 {
3046 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3047 VMXVEXITINFO const ExitInfo
3048 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3049 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3050 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3051 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3052 cbInstr);
3053 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3054 }
3055
3056 /*
3057 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3058 * must not be modified the instruction.
3059 *
3060 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3061 */
3062 uint64_t uGuestCrX;
3063 uint64_t fGstHostMask;
3064 if (iCrReg == 0)
3065 {
3066 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3067 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3068 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3069 }
3070 else
3071 {
3072 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3073 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3074 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3075 }
3076
3077 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3078 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3079}
3080
3081
3082/**
3083 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3084 *
3085 * @returns VBox strict status code.
3086 * @param pVCpu The cross context virtual CPU structure.
3087 * @param iGReg The general register to which the CR3 value is being stored.
3088 * @param cbInstr The instruction length in bytes.
3089 */
3090VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3091{
3092 Assert(iGReg < X86_GREG_COUNT);
3093 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3094
3095 /*
3096 * If the CR3-store exiting control is set, we must cause a VM-exit.
3097 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3098 */
3099 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3100 {
3101 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3102 VMXVEXITINFO const ExitInfo
3103 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3104 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3105 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3106 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3107 cbInstr);
3108 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3109 }
3110 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3111}
3112
3113
3114/**
3115 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3116 *
3117 * @returns VBox strict status code.
3118 * @param pVCpu The cross context virtual CPU structure.
3119 * @param uNewCr3 The new CR3 value.
3120 * @param iGReg The general register from which the CR3 value is being
3121 * loaded.
3122 * @param cbInstr The instruction length in bytes.
3123 */
3124VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3125{
3126 Assert(iGReg < X86_GREG_COUNT);
3127
3128 /*
3129 * If the CR3-load exiting control is set and the new CR3 value does not
3130 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3131 *
3132 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3133 */
3134 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3135 {
3136 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3137 VMXVEXITINFO const ExitInfo
3138 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3139 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3140 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3141 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3142 VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3143 cbInstr);
3144 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3145 }
3146 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3147}
3148
3149
3150/**
3151 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3152 *
3153 * @returns VBox strict status code.
3154 * @param pVCpu The cross context virtual CPU structure.
3155 * @param iGReg The general register to which the CR8 value is being stored.
3156 * @param cbInstr The instruction length in bytes.
3157 */
3158VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3159{
3160 Assert(iGReg < X86_GREG_COUNT);
3161
3162 /*
3163 * If the CR8-store exiting control is set, we must cause a VM-exit.
3164 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3165 */
3166 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3167 {
3168 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3169 VMXVEXITINFO const ExitInfo
3170 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3171 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3172 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3173 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3174 cbInstr);
3175 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3176 }
3177 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3178}
3179
3180
3181/**
3182 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3183 *
3184 * @returns VBox strict status code.
3185 * @param pVCpu The cross context virtual CPU structure.
3186 * @param iGReg The general register from which the CR8 value is being
3187 * loaded.
3188 * @param cbInstr The instruction length in bytes.
3189 */
3190VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3191{
3192 Assert(iGReg < X86_GREG_COUNT);
3193
3194 /*
3195 * If the CR8-load exiting control is set, we must cause a VM-exit.
3196 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3197 */
3198 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3199 {
3200 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3201 VMXVEXITINFO const ExitInfo
3202 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3203 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3204 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3205 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3206 cbInstr);
3207 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3208 }
3209 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3210}
3211
3212
3213/**
3214 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3215 * GReg,DRx' (DRx read).
3216 *
3217 * @returns VBox strict status code.
3218 * @param pVCpu The cross context virtual CPU structure.
3219 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3220 * VMXINSTRID_MOV_FROM_DRX).
3221 * @param iDrReg The debug register being accessed.
3222 * @param iGReg The general register to/from which the DRx value is being
3223 * store/loaded.
3224 * @param cbInstr The instruction length in bytes.
3225 */
3226VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3227 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3228{
3229 Assert(iDrReg <= 7);
3230 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3231 Assert(iGReg < X86_GREG_COUNT);
3232
3233 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3234 {
3235 VMXVEXITINFO const ExitInfo
3236 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_DRX,
3237 RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3238 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg)
3239 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION,
3240 uInstrId == VMXINSTRID_MOV_TO_DRX
3241 ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3242 : VMX_EXIT_QUAL_DRX_DIRECTION_READ),
3243 cbInstr);
3244 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3245 }
3246
3247 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3248}
3249
3250
3251/**
3252 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3253 *
3254 * @returns VBox strict status code.
3255 * @param pVCpu The cross context virtual CPU structure.
3256 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3257 * VMXINSTRID_IO_OUT).
3258 * @param u16Port The I/O port being accessed.
3259 * @param fImm Whether the I/O port was encoded using an immediate operand
3260 * or the implicit DX register.
3261 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3262 * @param cbInstr The instruction length in bytes.
3263 */
3264VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3265 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3266{
3267 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3268 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3269
3270 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3271 {
3272 VMXVEXITINFO const ExitInfo
3273 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_IO_INSTR,
3274 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3275 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3276 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port)
3277 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION,
3278 uInstrId == VMXINSTRID_IO_IN
3279 ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3280 : VMX_EXIT_QUAL_IO_DIRECTION_OUT),
3281 cbInstr);
3282 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3283 }
3284 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3285}
3286
3287
3288/**
3289 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3290 *
3291 * @returns VBox strict status code.
3292 * @param pVCpu The cross context virtual CPU structure.
3293 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3294 * VMXINSTRID_IO_OUTS).
3295 * @param u16Port The I/O port being accessed.
3296 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3297 * @param fRep Whether the instruction has a REP prefix or not.
3298 * @param ExitInstrInfo The VM-exit instruction info. field.
3299 * @param cbInstr The instruction length in bytes.
3300 */
3301VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3302 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3303{
3304 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3305 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3306 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3307 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3308 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3309
3310 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3311 {
3312 /*
3313 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3314 */
3315 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3316 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3317 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3318 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3319 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3320
3321 uint32_t uDirection;
3322 uint64_t uGuestLinearAddr;
3323 if (uInstrId == VMXINSTRID_IO_INS)
3324 {
3325 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3326 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3327 }
3328 else
3329 {
3330 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3331 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3332 }
3333
3334 /*
3335 * If the segment is unusable, the guest-linear address in undefined.
3336 * We shall clear it for consistency.
3337 *
3338 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3339 */
3340 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3341 uGuestLinearAddr = 0;
3342
3343 VMXVEXITINFO const ExitInfo
3344 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR(VMX_EXIT_IO_INSTR,
3345 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3346 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3347 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3348 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3349 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING,
3350 VMX_EXIT_QUAL_IO_ENCODING_DX)
3351 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port),
3352 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo
3353 ? ExitInstrInfo.u : 0,
3354 cbInstr,
3355 uGuestLinearAddr);
3356 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3357 }
3358
3359 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3360}
3361
3362
3363/**
3364 * VMX VM-exit handler for VM-exits due to MWAIT.
3365 *
3366 * @returns VBox strict status code.
3367 * @param pVCpu The cross context virtual CPU structure.
3368 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3369 * @param cbInstr The instruction length in bytes.
3370 */
3371VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3372{
3373 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MWAIT, fMonitorHwArmed, cbInstr);
3374 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3375}
3376
3377
3378/**
3379 * VMX VM-exit handler for VM-exits due to PAUSE.
3380 *
3381 * @returns VBox strict status code.
3382 * @param pVCpu The cross context virtual CPU structure.
3383 * @param cbInstr The instruction length in bytes.
3384 */
3385static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3386{
3387 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3388
3389 /*
3390 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3391 * "PAUSE-loop exiting" control.
3392 *
3393 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3394 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3395 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3396 * a VM-exit.
3397 *
3398 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3399 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3400 */
3401 bool fIntercept = false;
3402 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3403 fIntercept = true;
3404 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3405 && pVCpu->iem.s.uCpl == 0)
3406 {
3407 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3408
3409 /*
3410 * A previous-PAUSE-tick value of 0 is used to identify the first time
3411 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3412 * consider this to be the first execution of PAUSE in a loop according
3413 * to the Intel.
3414 *
3415 * All subsequent records for the previous-PAUSE-tick we ensure that it
3416 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3417 */
3418 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3419 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3420 uint64_t const uTick = TMCpuTickGet(pVCpu);
3421 uint32_t const uPleGap = pVmcs->u32PleGap;
3422 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3423 if ( *puPrevPauseTick == 0
3424 || uTick - *puPrevPauseTick > uPleGap)
3425 *puFirstPauseLoopTick = uTick;
3426 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3427 fIntercept = true;
3428
3429 *puPrevPauseTick = uTick | 1;
3430 }
3431
3432 if (fIntercept)
3433 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3434
3435 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3436}
3437
3438
3439/**
3440 * VMX VM-exit handler for VM-exits due to task switches.
3441 *
3442 * @returns VBox strict status code.
3443 * @param pVCpu The cross context virtual CPU structure.
3444 * @param enmTaskSwitch The cause of the task switch.
3445 * @param SelNewTss The selector of the new TSS.
3446 * @param cbInstr The instruction length in bytes.
3447 */
3448VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3449{
3450 /*
3451 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3452 *
3453 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3454 * instruction or delivery of the exception generated by one of these instructions
3455 * lead to a task switch through a task gate in the IDT, we need to provide the
3456 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3457 * leaves the VM-exit instruction length field undefined.
3458 *
3459 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3460 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3461 */
3462 Assert(cbInstr <= 15);
3463
3464 uint8_t uType;
3465 switch (enmTaskSwitch)
3466 {
3467 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3468 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3469 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3470 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3471 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3472 }
3473
3474 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3475 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3476 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3477 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3478}
3479
3480
3481/**
3482 * VMX VM-exit handler for trap-like VM-exits.
3483 *
3484 * @returns VBox strict status code.
3485 * @param pVCpu The cross context virtual CPU structure.
3486 * @param pExitInfo Pointer to the VM-exit information.
3487 * @param pExitEventInfo Pointer to the VM-exit event information.
3488 */
3489static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3490{
3491 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3492 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3493 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3494}
3495
3496
3497/**
3498 * Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3499 * Virtualized-EOI, TPR-below threshold).
3500 *
3501 * @returns Strict VBox status code.
3502 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3503 * @param pExitInfo Pointer to the VM-exit information.
3504 * @thread EMT(pVCpu)
3505 */
3506VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3507{
3508 Assert(pExitInfo);
3509 VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3510 Assert(!pVCpu->iem.s.cActiveMappings);
3511 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3512}
3513
3514
3515/**
3516 * VMX VM-exit handler for VM-exits due to task switches.
3517 *
3518 * This is intended for task switches where the caller provides all the relevant
3519 * VM-exit information.
3520 *
3521 * @returns VBox strict status code.
3522 * @param pVCpu The cross context virtual CPU structure.
3523 * @param pExitInfo Pointer to the VM-exit information.
3524 * @param pExitEventInfo Pointer to the VM-exit event information.
3525 */
3526static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3527 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3528{
3529 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3530 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3531 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3532 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3533 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3534}
3535
3536
3537/**
3538 * Interface for HM and EM to emulate a VM-exit due to a task switch.
3539 *
3540 * @returns Strict VBox status code.
3541 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3542 * @param pExitInfo Pointer to the VM-exit information.
3543 * @param pExitEventInfo Pointer to the VM-exit event information.
3544 * @thread EMT(pVCpu)
3545 */
3546VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3547{
3548 Assert(pExitInfo);
3549 Assert(pExitEventInfo);
3550 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3551 VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3552 Assert(!pVCpu->iem.s.cActiveMappings);
3553 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3554}
3555
3556
3557/**
3558 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3559 *
3560 * @returns VBox strict status code.
3561 * @param pVCpu The cross context virtual CPU structure.
3562 */
3563VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3564{
3565 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3566 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3567
3568 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3569 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3570
3571 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3572 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3573 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3574
3575 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3576 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3577}
3578
3579
3580/**
3581 * Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3582 *
3583 * @returns Strict VBox status code.
3584 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3585 * @thread EMT(pVCpu)
3586 */
3587VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3588{
3589 VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3590 Assert(!pVCpu->iem.s.cActiveMappings);
3591 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3592}
3593
3594
3595/**
3596 * VMX VM-exit handler for VM-exits due to external interrupts.
3597 *
3598 * @returns VBox strict status code.
3599 * @param pVCpu The cross context virtual CPU structure.
3600 * @param uVector The external interrupt vector (pass 0 if the interrupt
3601 * is still pending since we typically won't know the
3602 * vector).
3603 * @param fIntPending Whether the external interrupt is pending or
3604 * acknowledged in the interrupt controller.
3605 */
3606static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3607{
3608 Assert(!fIntPending || uVector == 0);
3609
3610 /* The VM-exit is subject to "External interrupt exiting" being set. */
3611 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3612 {
3613 if (fIntPending)
3614 {
3615 /*
3616 * If the interrupt is pending and we don't need to acknowledge the
3617 * interrupt on VM-exit, cause the VM-exit immediately.
3618 *
3619 * See Intel spec 25.2 "Other Causes Of VM Exits".
3620 */
3621 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3622 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3623
3624 /*
3625 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3626 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3627 * acknowledged that the interrupt has been consumed. Callers would have to call
3628 * us again after getting the vector (and ofc, with fIntPending with false).
3629 */
3630 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3631 }
3632
3633 /*
3634 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3635 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3636 * all set, we need to record the vector of the external interrupt in the
3637 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3638 *
3639 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3640 */
3641 uint32_t uExitIntInfo;
3642 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3643 {
3644 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3645 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3646 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3647 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3648 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3649 }
3650 else
3651 uExitIntInfo = 0;
3652 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3653
3654 /*
3655 * Cause the VM-exit whether or not the vector has been stored
3656 * in the VM-exit interruption-information field.
3657 */
3658 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3659 }
3660
3661 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3662}
3663
3664
3665/**
3666 * Interface for HM and EM to emulate VM-exit due to external interrupts.
3667 *
3668 * @returns Strict VBox status code.
3669 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3670 * @param uVector The external interrupt vector (pass 0 if the external
3671 * interrupt is still pending).
3672 * @param fIntPending Whether the external interrupt is pending or
3673 * acknowdledged in the interrupt controller.
3674 * @thread EMT(pVCpu)
3675 */
3676VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3677{
3678 VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3679 Assert(!pVCpu->iem.s.cActiveMappings);
3680 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3681}
3682
3683
3684/**
3685 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3686 * an event.
3687 *
3688 * @returns VBox strict status code.
3689 * @param pVCpu The cross context virtual CPU structure.
3690 */
3691VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3692{
3693 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3694 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3695 {
3696 /*
3697 * The NMI-unblocking due to IRET field need not be set for double faults.
3698 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3699 */
3700 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3701 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3702 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3703 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3704 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3705 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3706 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3707 }
3708
3709 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3710}
3711
3712
3713/**
3714 * VMX VM-exit handler for VM-exit due to delivery of an events.
3715 *
3716 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3717 * all the relevant VM-exit information.
3718 *
3719 * @returns VBox strict status code.
3720 * @param pVCpu The cross context virtual CPU structure.
3721 * @param pExitInfo Pointer to the VM-exit information.
3722 * @param pExitEventInfo Pointer to the VM-exit event information.
3723 */
3724static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3725{
3726 Assert(pExitInfo);
3727 Assert(pExitEventInfo);
3728 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3729 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3730
3731 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3732 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3733 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3734 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3735 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3736 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3737}
3738
3739
3740/**
3741 * Interface for HM and EM to emulate VM-exit due to NMIs.
3742 *
3743 * @returns Strict VBox status code.
3744 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3745 * @thread EMT(pVCpu)
3746 */
3747VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3748{
3749 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_ONLY_REASON(VMX_EXIT_XCPT_OR_NMI);
3750 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_INT( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3751 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE,
3752 VMX_EXIT_INT_INFO_TYPE_NMI)
3753 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR,
3754 X86_XCPT_NMI),
3755 0);
3756 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3757 Assert(!pVCpu->iem.s.cActiveMappings);
3758 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3759}
3760
3761
3762/**
3763 * Interface for HM and EM to emulate VM-exit due to exceptions.
3764 *
3765 * Exception includes NMIs, software exceptions (those generated by INT3 or
3766 * INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3767 *
3768 * @returns Strict VBox status code.
3769 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3770 * @param pExitInfo Pointer to the VM-exit information.
3771 * @param pExitEventInfo Pointer to the VM-exit event information.
3772 * @thread EMT(pVCpu)
3773 */
3774VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3775{
3776 Assert(pExitInfo);
3777 Assert(pExitEventInfo);
3778 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3779 Assert(!pVCpu->iem.s.cActiveMappings);
3780 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3781}
3782
3783
3784/**
3785 * VMX VM-exit handler for VM-exits due to delivery of an event.
3786 *
3787 * @returns VBox strict status code.
3788 * @param pVCpu The cross context virtual CPU structure.
3789 * @param uVector The interrupt / exception vector.
3790 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3791 * @param uErrCode The error code associated with the event.
3792 * @param uCr2 The CR2 value in case of a \#PF exception.
3793 * @param cbInstr The instruction length in bytes.
3794 */
3795VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3796 uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3797{
3798 /*
3799 * If the event is being injected as part of VM-entry, it is -not- subject to event
3800 * intercepts in the nested-guest. However, secondary exceptions that occur during
3801 * injection of any event -are- subject to event interception.
3802 *
3803 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3804 */
3805 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3806 {
3807 /*
3808 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3809 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3810 *
3811 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3812 */
3813 if ( uVector == X86_XCPT_NMI
3814 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3815 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3816 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3817 else
3818 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3819
3820 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3821 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3822 }
3823
3824 /*
3825 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3826 * If not, the caller will continue delivery of the external interrupt as it would
3827 * normally. The interrupt is no longer pending in the interrupt controller at this
3828 * point.
3829 */
3830 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3831 {
3832 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3833 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3834 }
3835
3836 /*
3837 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3838 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3839 * interrupts.
3840 */
3841 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3842 bool fIntercept;
3843 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3844 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3845 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3846 else
3847 {
3848 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3849 fIntercept = false;
3850 }
3851
3852 /*
3853 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3854 * relevant VM-exit information and cause the VM-exit.
3855 */
3856 if (fIntercept)
3857 {
3858 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3859
3860 /* Construct the rest of the event related information fields and cause the VM-exit. */
3861 uint64_t u64ExitQual;
3862 if (uVector == X86_XCPT_PF)
3863 {
3864 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3865 u64ExitQual = uCr2;
3866 }
3867 else if (uVector == X86_XCPT_DB)
3868 {
3869 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3870 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3871 }
3872 else
3873 u64ExitQual = 0;
3874
3875 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3876 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3877 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3878 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3879 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3880 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3881 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3882 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3883 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3884 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3885
3886 /*
3887 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3888 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3889 * length.
3890 */
3891 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3892 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3893 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3894 else
3895 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3896
3897 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3898 }
3899
3900 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3901}
3902
3903
3904/**
3905 * VMX VM-exit handler for EPT misconfiguration.
3906 *
3907 * @param pVCpu The cross context virtual CPU structure.
3908 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3909 * This need not be page aligned (e.g. nested-guest in real
3910 * mode).
3911 */
3912static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3913{
3914 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3915 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3916}
3917
3918
3919/**
3920 * VMX VM-exit handler for EPT misconfiguration.
3921 *
3922 * This is intended for EPT misconfigurations where the caller provides all the
3923 * relevant VM-exit information.
3924 *
3925 * @param pVCpu The cross context virtual CPU structure.
3926 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3927 * This need not be page aligned (e.g. nested-guest in real
3928 * mode).
3929 * @param pExitEventInfo Pointer to the VM-exit event information.
3930 */
3931static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3932{
3933 Assert(pExitEventInfo);
3934 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3935 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3936 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3937 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3938 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3939}
3940
3941
3942/**
3943 * Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3944 *
3945 * @returns Strict VBox status code.
3946 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3947 * @param GCPhysAddr The nested-guest physical address causing the EPT
3948 * misconfiguration.
3949 * @param pExitEventInfo Pointer to the VM-exit event information.
3950 * @thread EMT(pVCpu)
3951 */
3952VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3953{
3954 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
3955
3956 iemInitExec(pVCpu, false /*fBypassHandlers*/);
3957 VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
3958 Assert(!pVCpu->iem.s.cActiveMappings);
3959 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
3960}
3961
3962
3963/**
3964 * VMX VM-exit handler for EPT violation.
3965 *
3966 * @param pVCpu The cross context virtual CPU structure.
3967 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3968 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3969 * @param fEptAccess The EPT paging structure bits.
3970 * @param GCPhysAddr The physical address causing the EPT violation. This
3971 * need not be page aligned (e.g. nested-guest in real
3972 * mode).
3973 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3974 * EPT violation. If @c false, GCPtrAddr must be 0.
3975 * @param GCPtrAddr The linear address causing the EPT violation.
3976 * @param cbInstr The VM-exit instruction length.
3977 */
3978static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
3979 uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
3980 uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
3981{
3982 /*
3983 * If the linear address isn't valid (can happen when loading PDPTEs
3984 * as part of MOV CR execution) the linear address field is undefined.
3985 * While we can leave it this way, it's preferrable to zero it for consistency.
3986 */
3987 Assert(fIsLinearAddrValid || GCPtrAddr == 0);
3988
3989 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3990 bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
3991
3992 uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_READ;
3993 uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_WRITE;
3994 uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_EXEC;
3995 bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3996 bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) | fSupportsAccessDirty;
3997 bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
3998 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3999 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
4000 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
4001 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4002 bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
4003
4004 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
4005 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
4006 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
4007 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
4008 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
4009 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
4010 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
4011 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
4012 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
4013
4014#ifdef VBOX_STRICT
4015 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
4016 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
4017 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
4018 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
4019 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
4020 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
4021#endif
4022
4023 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
4024 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
4025 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4026
4027 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
4028}
4029
4030
4031/**
4032 * VMX VM-exit handler for EPT violation.
4033 *
4034 * This is intended for EPT violations where the caller provides all the
4035 * relevant VM-exit information.
4036 *
4037 * @returns VBox strict status code.
4038 * @param pVCpu The cross context virtual CPU structure.
4039 * @param pExitInfo Pointer to the VM-exit information.
4040 * @param pExitEventInfo Pointer to the VM-exit event information.
4041 */
4042static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4043 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4044{
4045 Assert(pExitInfo);
4046 Assert(pExitEventInfo);
4047 Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4048 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4049
4050 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4051 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4052
4053 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4054 if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4055 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4056 else
4057 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4058 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4059 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4060}
4061
4062
4063/**
4064 * Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4065 *
4066 * @returns Strict VBox status code.
4067 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4068 * @param pExitInfo Pointer to the VM-exit information.
4069 * @param pExitEventInfo Pointer to the VM-exit event information.
4070 * @thread EMT(pVCpu)
4071 */
4072VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4073 PCVMXVEXITEVENTINFO pExitEventInfo)
4074{
4075 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
4076
4077 iemInitExec(pVCpu, false /*fBypassHandlers*/);
4078 VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4079 Assert(!pVCpu->iem.s.cActiveMappings);
4080 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4081}
4082
4083
4084/**
4085 * VMX VM-exit handler for EPT-induced VM-exits.
4086 *
4087 * @param pVCpu The cross context virtual CPU structure.
4088 * @param pWalk The page walk info.
4089 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4090 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4091 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4092 * applicable.
4093 */
4094VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4095{
4096 Assert(pWalk->fIsSlat);
4097 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4098 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4099 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4100
4101 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4102 {
4103 LogFlow(("EptViolation: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4104 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4105 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4106 pWalk->GCPtr, cbInstr);
4107 }
4108
4109 LogFlow(("EptMisconfig: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4110 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4111 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4112}
4113
4114
4115/**
4116 * VMX VM-exit handler for APIC accesses.
4117 *
4118 * @param pVCpu The cross context virtual CPU structure.
4119 * @param offAccess The offset of the register being accessed.
4120 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4121 */
4122static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4123{
4124 VMXAPICACCESS enmAccess;
4125 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4126 if (fInEventDelivery)
4127 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4128 else if ((fAccess & (IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4129 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4130 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4131 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4132 else
4133 enmAccess = VMXAPICACCESS_LINEAR_READ;
4134
4135 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4136 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4137 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4138}
4139
4140
4141/**
4142 * VMX VM-exit handler for APIC accesses.
4143 *
4144 * This is intended for APIC accesses where the caller provides all the
4145 * relevant VM-exit information.
4146 *
4147 * @returns VBox strict status code.
4148 * @param pVCpu The cross context virtual CPU structure.
4149 * @param pExitInfo Pointer to the VM-exit information.
4150 * @param pExitEventInfo Pointer to the VM-exit event information.
4151 */
4152static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4153 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4154{
4155 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4156 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4157 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4158 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4159 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4160 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4161 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4162 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4163 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4164}
4165
4166
4167/**
4168 * Interface for HM and EM to virtualize memory-mapped APIC accesses.
4169 *
4170 * @returns Strict VBox status code.
4171 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4172 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4173 *
4174 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4175 * @param pExitInfo Pointer to the VM-exit information.
4176 * @param pExitEventInfo Pointer to the VM-exit event information.
4177 * @thread EMT(pVCpu)
4178 */
4179VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4180{
4181 Assert(pExitInfo);
4182 Assert(pExitEventInfo);
4183 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4184 Assert(!pVCpu->iem.s.cActiveMappings);
4185 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4186}
4187
4188
4189/**
4190 * VMX VM-exit handler for APIC-write VM-exits.
4191 *
4192 * @param pVCpu The cross context virtual CPU structure.
4193 * @param offApic The write to the virtual-APIC page offset that caused this
4194 * VM-exit.
4195 */
4196static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4197{
4198 Assert(offApic < XAPIC_OFF_END + 4);
4199 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4200 offApic &= UINT16_C(0xfff);
4201 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4202}
4203
4204
4205/**
4206 * Clears any pending virtual-APIC write emulation.
4207 *
4208 * @returns The virtual-APIC offset that was written before clearing it.
4209 * @param pVCpu The cross context virtual CPU structure.
4210 */
4211DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4212{
4213 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4214 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4215 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4216 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4217 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4218 return offVirtApicWrite;
4219}
4220
4221
4222/**
4223 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4224 *
4225 * @returns The register from the virtual-APIC page.
4226 * @param pVCpu The cross context virtual CPU structure.
4227 * @param offReg The offset of the register being read.
4228 */
4229uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4230{
4231 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4232
4233 uint32_t uReg = 0;
4234 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4235 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4236 AssertMsgStmt(RT_SUCCESS(rc),
4237 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4238 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4239 uReg = 0);
4240 return uReg;
4241}
4242
4243
4244/**
4245 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4246 *
4247 * @returns The register from the virtual-APIC page.
4248 * @param pVCpu The cross context virtual CPU structure.
4249 * @param offReg The offset of the register being read.
4250 */
4251static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4252{
4253 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4254
4255 uint64_t uReg = 0;
4256 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4257 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4258 AssertMsgStmt(RT_SUCCESS(rc),
4259 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4260 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4261 uReg = 0);
4262 return uReg;
4263}
4264
4265
4266/**
4267 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4268 *
4269 * @param pVCpu The cross context virtual CPU structure.
4270 * @param offReg The offset of the register being written.
4271 * @param uReg The register value to write.
4272 */
4273void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4274{
4275 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4276
4277 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4278 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4279 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4280 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4281}
4282
4283
4284/**
4285 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4286 *
4287 * @param pVCpu The cross context virtual CPU structure.
4288 * @param offReg The offset of the register being written.
4289 * @param uReg The register value to write.
4290 */
4291static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4292{
4293 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4294
4295 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4296 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4297 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4298 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4299}
4300
4301
4302/**
4303 * Sets the vector in a virtual-APIC 256-bit sparse register.
4304 *
4305 * @param pVCpu The cross context virtual CPU structure.
4306 * @param offReg The offset of the 256-bit spare register.
4307 * @param uVector The vector to set.
4308 *
4309 * @remarks This is based on our APIC device code.
4310 */
4311static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4312{
4313 /* Determine the vector offset within the chunk. */
4314 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4315
4316 /* Read the chunk at the offset. */
4317 uint32_t uReg;
4318 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4319 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4320 if (RT_SUCCESS(rc))
4321 {
4322 /* Modify the chunk. */
4323 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4324 uReg |= RT_BIT(idxVectorBit);
4325
4326 /* Write the chunk. */
4327 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4328 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4329 uVector, offReg, GCPhysVirtApic, rc));
4330 }
4331 else
4332 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4333 uVector, offReg, GCPhysVirtApic, rc));
4334}
4335
4336
4337/**
4338 * Clears the vector in a virtual-APIC 256-bit sparse register.
4339 *
4340 * @param pVCpu The cross context virtual CPU structure.
4341 * @param offReg The offset of the 256-bit spare register.
4342 * @param uVector The vector to clear.
4343 *
4344 * @remarks This is based on our APIC device code.
4345 */
4346static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4347{
4348 /* Determine the vector offset within the chunk. */
4349 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4350
4351 /* Read the chunk at the offset. */
4352 uint32_t uReg;
4353 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4354 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4355 if (RT_SUCCESS(rc))
4356 {
4357 /* Modify the chunk. */
4358 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4359 uReg &= ~RT_BIT(idxVectorBit);
4360
4361 /* Write the chunk. */
4362 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4363 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4364 uVector, offReg, GCPhysVirtApic, rc));
4365 }
4366 else
4367 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4368 uVector, offReg, GCPhysVirtApic, rc));
4369}
4370
4371
4372/**
4373 * Checks if a memory access to the APIC-access page must causes an APIC-access
4374 * VM-exit.
4375 *
4376 * @param pVCpu The cross context virtual CPU structure.
4377 * @param offAccess The offset of the register being accessed.
4378 * @param cbAccess The size of the access in bytes.
4379 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4380 *
4381 * @remarks This must not be used for MSR-based APIC-access page accesses!
4382 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4383 */
4384static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4385{
4386 Assert(cbAccess > 0);
4387 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4388
4389 /*
4390 * We must cause a VM-exit if any of the following are true:
4391 * - TPR shadowing isn't active.
4392 * - The access size exceeds 32-bits.
4393 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4394 *
4395 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4396 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4397 */
4398 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4399 || cbAccess > sizeof(uint32_t)
4400 || ((offAccess + cbAccess - 1) & 0xc)
4401 || offAccess >= XAPIC_OFF_END + 4)
4402 return true;
4403
4404 /*
4405 * If the access is part of an operation where we have already
4406 * virtualized a virtual-APIC write, we must cause a VM-exit.
4407 */
4408 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4409 return true;
4410
4411 /*
4412 * Check write accesses to the APIC-access page that cause VM-exits.
4413 */
4414 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4415 {
4416 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4417 {
4418 /*
4419 * With APIC-register virtualization, a write access to any of the
4420 * following registers are virtualized. Accessing any other register
4421 * causes a VM-exit.
4422 */
4423 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4424 switch (offAlignedAccess)
4425 {
4426 case XAPIC_OFF_ID:
4427 case XAPIC_OFF_TPR:
4428 case XAPIC_OFF_EOI:
4429 case XAPIC_OFF_LDR:
4430 case XAPIC_OFF_DFR:
4431 case XAPIC_OFF_SVR:
4432 case XAPIC_OFF_ESR:
4433 case XAPIC_OFF_ICR_LO:
4434 case XAPIC_OFF_ICR_HI:
4435 case XAPIC_OFF_LVT_TIMER:
4436 case XAPIC_OFF_LVT_THERMAL:
4437 case XAPIC_OFF_LVT_PERF:
4438 case XAPIC_OFF_LVT_LINT0:
4439 case XAPIC_OFF_LVT_LINT1:
4440 case XAPIC_OFF_LVT_ERROR:
4441 case XAPIC_OFF_TIMER_ICR:
4442 case XAPIC_OFF_TIMER_DCR:
4443 break;
4444 default:
4445 return true;
4446 }
4447 }
4448 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4449 {
4450 /*
4451 * With virtual-interrupt delivery, a write access to any of the
4452 * following registers are virtualized. Accessing any other register
4453 * causes a VM-exit.
4454 *
4455 * Note! The specification does not allow writing to offsets in-between
4456 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4457 */
4458 switch (offAccess)
4459 {
4460 case XAPIC_OFF_TPR:
4461 case XAPIC_OFF_EOI:
4462 case XAPIC_OFF_ICR_LO:
4463 break;
4464 default:
4465 return true;
4466 }
4467 }
4468 else
4469 {
4470 /*
4471 * Without APIC-register virtualization or virtual-interrupt delivery,
4472 * only TPR accesses are virtualized.
4473 */
4474 if (offAccess == XAPIC_OFF_TPR)
4475 { /* likely */ }
4476 else
4477 return true;
4478 }
4479 }
4480 else
4481 {
4482 /*
4483 * Check read accesses to the APIC-access page that cause VM-exits.
4484 */
4485 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4486 {
4487 /*
4488 * With APIC-register virtualization, a read access to any of the
4489 * following registers are virtualized. Accessing any other register
4490 * causes a VM-exit.
4491 */
4492 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4493 switch (offAlignedAccess)
4494 {
4495 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4496 case XAPIC_OFF_ID:
4497 case XAPIC_OFF_VERSION:
4498 case XAPIC_OFF_TPR:
4499 case XAPIC_OFF_EOI:
4500 case XAPIC_OFF_LDR:
4501 case XAPIC_OFF_DFR:
4502 case XAPIC_OFF_SVR:
4503 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4504 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4505 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4506 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4507 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4508 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4509 case XAPIC_OFF_ESR:
4510 case XAPIC_OFF_ICR_LO:
4511 case XAPIC_OFF_ICR_HI:
4512 case XAPIC_OFF_LVT_TIMER:
4513 case XAPIC_OFF_LVT_THERMAL:
4514 case XAPIC_OFF_LVT_PERF:
4515 case XAPIC_OFF_LVT_LINT0:
4516 case XAPIC_OFF_LVT_LINT1:
4517 case XAPIC_OFF_LVT_ERROR:
4518 case XAPIC_OFF_TIMER_ICR:
4519 case XAPIC_OFF_TIMER_DCR:
4520 break;
4521 default:
4522 return true;
4523 }
4524 }
4525 else
4526 {
4527 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4528 if (offAccess == XAPIC_OFF_TPR)
4529 { /* likely */ }
4530 else
4531 return true;
4532 }
4533 }
4534
4535 /* The APIC access is virtualized, does not cause a VM-exit. */
4536 return false;
4537}
4538
4539
4540/**
4541 * Virtualizes a memory-based APIC access by certain instructions even though they
4542 * do not use the address to access memory.
4543 *
4544 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4545 * page-faults but do not use the address to access memory.
4546 *
4547 * @param pVCpu The cross context virtual CPU structure.
4548 * @param pGCPhysAccess Pointer to the guest-physical address accessed.
4549 * @param cbAccess The size of the access in bytes.
4550 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4551 */
4552VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4553{
4554 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4555 Assert(pGCPhysAccess);
4556
4557 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4558 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4559 Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4560
4561 if (GCPhysAccess == GCPhysApic)
4562 {
4563 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4564 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4565 if (fIntercept)
4566 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4567
4568 *pGCPhysAccess = GCPhysApic | offAccess;
4569 return VINF_VMX_MODIFIES_BEHAVIOR;
4570 }
4571
4572 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4573}
4574
4575
4576/**
4577 * Virtualizes a memory-based APIC access.
4578 *
4579 * @returns VBox strict status code.
4580 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4581 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4582 *
4583 * @param pVCpu The cross context virtual CPU structure.
4584 * @param offAccess The offset of the register being accessed (within the
4585 * APIC-access page).
4586 * @param cbAccess The size of the access in bytes.
4587 * @param pvData Pointer to the data being written or where to store the data
4588 * being read.
4589 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4590 */
4591static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4592 void *pvData, uint32_t fAccess) RT_NOEXCEPT
4593{
4594 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4595 Assert(pvData);
4596
4597 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4598 if (fIntercept)
4599 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4600
4601 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4602 {
4603 /*
4604 * A write access to the APIC-access page that is virtualized (rather than
4605 * causing a VM-exit) writes data to the virtual-APIC page.
4606 */
4607 uint32_t const u32Data = *(uint32_t *)pvData;
4608 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4609
4610 /*
4611 * Record the currently updated APIC offset, as we need this later for figuring
4612 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4613 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4614 *
4615 * After completion of the current operation, we need to perform TPR virtualization,
4616 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4617 *
4618 * The current operation may be a REP-prefixed string instruction, execution of any
4619 * other instruction, or delivery of an event through the IDT.
4620 *
4621 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4622 * performed now but later after completion of the current operation.
4623 *
4624 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4625 */
4626 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4627
4628 LogFlowFunc(("Write access at offset %#x not intercepted -> Wrote %#RX32\n", offAccess, u32Data));
4629 }
4630 else
4631 {
4632 /*
4633 * A read access from the APIC-access page that is virtualized (rather than
4634 * causing a VM-exit) returns data from the virtual-APIC page.
4635 *
4636 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4637 */
4638 Assert(fAccess & IEM_ACCESS_TYPE_READ);
4639
4640 Assert(cbAccess <= 4);
4641 Assert(offAccess < XAPIC_OFF_END + 4);
4642 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4643
4644 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4645 u32Data &= s_auAccessSizeMasks[cbAccess];
4646 *(uint32_t *)pvData = u32Data;
4647
4648 LogFlowFunc(("Read access at offset %#x not intercepted -> Read %#RX32\n", offAccess, u32Data));
4649 }
4650
4651 return VINF_VMX_MODIFIES_BEHAVIOR;
4652}
4653
4654
4655/**
4656 * Virtualizes an MSR-based APIC read access.
4657 *
4658 * @returns VBox strict status code.
4659 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4660 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4661 * handled by the x2APIC device.
4662 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4663 * not within the range of valid MSRs, caller must raise \#GP(0).
4664 * @param pVCpu The cross context virtual CPU structure.
4665 * @param idMsr The x2APIC MSR being read.
4666 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4667 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4668 */
4669static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4670{
4671 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4672 Assert(pu64Value);
4673
4674 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4675 {
4676 if ( idMsr >= MSR_IA32_X2APIC_START
4677 && idMsr <= MSR_IA32_X2APIC_END)
4678 {
4679 uint16_t const offReg = (idMsr & 0xff) << 4;
4680 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4681 *pu64Value = u64Value;
4682 return VINF_VMX_MODIFIES_BEHAVIOR;
4683 }
4684 return VERR_OUT_OF_RANGE;
4685 }
4686
4687 if (idMsr == MSR_IA32_X2APIC_TPR)
4688 {
4689 uint16_t const offReg = (idMsr & 0xff) << 4;
4690 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4691 *pu64Value = u64Value;
4692 return VINF_VMX_MODIFIES_BEHAVIOR;
4693 }
4694
4695 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4696}
4697
4698
4699/**
4700 * Virtualizes an MSR-based APIC write access.
4701 *
4702 * @returns VBox strict status code.
4703 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4704 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4705 * not within the range of valid MSRs, caller must raise \#GP(0).
4706 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4707 *
4708 * @param pVCpu The cross context virtual CPU structure.
4709 * @param idMsr The x2APIC MSR being written.
4710 * @param u64Value The value of the x2APIC MSR being written.
4711 */
4712static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4713{
4714 /*
4715 * Check if the access is to be virtualized.
4716 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4717 */
4718 if ( idMsr == MSR_IA32_X2APIC_TPR
4719 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4720 && ( idMsr == MSR_IA32_X2APIC_EOI
4721 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4722 {
4723 /* Validate the MSR write depending on the register. */
4724 switch (idMsr)
4725 {
4726 case MSR_IA32_X2APIC_TPR:
4727 case MSR_IA32_X2APIC_SELF_IPI:
4728 {
4729 if (u64Value & UINT64_C(0xffffffffffffff00))
4730 return VERR_OUT_OF_RANGE;
4731 break;
4732 }
4733 case MSR_IA32_X2APIC_EOI:
4734 {
4735 if (u64Value != 0)
4736 return VERR_OUT_OF_RANGE;
4737 break;
4738 }
4739 }
4740
4741 /* Write the MSR to the virtual-APIC page. */
4742 uint16_t const offReg = (idMsr & 0xff) << 4;
4743 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4744
4745 /*
4746 * Record the currently updated APIC offset, as we need this later for figuring
4747 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4748 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4749 */
4750 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4751
4752 return VINF_VMX_MODIFIES_BEHAVIOR;
4753 }
4754
4755 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4756}
4757
4758
4759/**
4760 * Interface for HM and EM to virtualize x2APIC MSR accesses.
4761 *
4762 * @returns Strict VBox status code.
4763 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4764 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4765 * the x2APIC device.
4766 * @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4767 *
4768 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4769 * @param idMsr The MSR being read.
4770 * @param pu64Value Pointer to the value being written or where to store the
4771 * value being read.
4772 * @param fWrite Whether this is an MSR write or read access.
4773 * @thread EMT(pVCpu)
4774 */
4775VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4776{
4777 Assert(pu64Value);
4778
4779 VBOXSTRICTRC rcStrict;
4780 if (fWrite)
4781 rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4782 else
4783 rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4784 Assert(!pVCpu->iem.s.cActiveMappings);
4785 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4786
4787}
4788
4789
4790/**
4791 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4792 *
4793 * @returns VBox status code.
4794 * @retval VINF_SUCCESS when the highest set bit is found.
4795 * @retval VERR_NOT_FOUND when no bit is set.
4796 *
4797 * @param pVCpu The cross context virtual CPU structure.
4798 * @param offReg The offset of the APIC 256-bit sparse register.
4799 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4800 * set in the register. Only valid when VINF_SUCCESS is
4801 * returned.
4802 *
4803 * @remarks The format of the 256-bit sparse register here mirrors that found in
4804 * real APIC hardware.
4805 */
4806static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4807{
4808 Assert(offReg < XAPIC_OFF_END + 4);
4809 Assert(pidxHighestBit);
4810
4811 /*
4812 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4813 * However, in each fragment only the first 4 bytes are used.
4814 */
4815 uint8_t const cFrags = 8;
4816 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4817 {
4818 uint16_t const offFrag = iFrag * 16;
4819 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4820 if (!u32Frag)
4821 continue;
4822
4823 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4824 Assert(idxHighestBit > 0);
4825 --idxHighestBit;
4826 Assert(idxHighestBit <= UINT8_MAX);
4827 *pidxHighestBit = idxHighestBit;
4828 return VINF_SUCCESS;
4829 }
4830 return VERR_NOT_FOUND;
4831}
4832
4833
4834/**
4835 * Evaluates pending virtual interrupts.
4836 *
4837 * @param pVCpu The cross context virtual CPU structure.
4838 */
4839static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4840{
4841 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4842
4843 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4844 {
4845 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4846 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4847
4848 if ((uRvi >> 4) > (uPpr >> 4))
4849 {
4850 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4851 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4852 }
4853 else
4854 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4855 }
4856}
4857
4858
4859/**
4860 * Performs PPR virtualization.
4861 *
4862 * @returns VBox strict status code.
4863 * @param pVCpu The cross context virtual CPU structure.
4864 */
4865static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4866{
4867 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4868 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4869
4870 /*
4871 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4872 * or EOI-virtualization.
4873 *
4874 * See Intel spec. 29.1.3 "PPR Virtualization".
4875 */
4876 uint8_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4877 uint8_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus) & 0xf0;
4878
4879 uint32_t uPpr;
4880 if ((uTpr & 0xf0) >= uSvi)
4881 uPpr = uTpr;
4882 else
4883 uPpr = uSvi;
4884
4885 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4886 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4887}
4888
4889
4890/**
4891 * Performs VMX TPR virtualization.
4892 *
4893 * @returns VBox strict status code.
4894 * @param pVCpu The cross context virtual CPU structure.
4895 */
4896static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4897{
4898 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4899
4900 /*
4901 * We should have already performed the virtual-APIC write to the TPR offset
4902 * in the virtual-APIC page. We now perform TPR virtualization.
4903 *
4904 * See Intel spec. 29.1.2 "TPR Virtualization".
4905 */
4906 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4907 {
4908 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4909 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4910
4911 /*
4912 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4913 * See Intel spec. 29.1.2 "TPR Virtualization".
4914 */
4915 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4916 {
4917 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4918 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4919 }
4920 }
4921 else
4922 {
4923 iemVmxPprVirtualization(pVCpu);
4924 iemVmxEvalPendingVirtIntrs(pVCpu);
4925 }
4926
4927 return VINF_SUCCESS;
4928}
4929
4930
4931/**
4932 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4933 * not.
4934 *
4935 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4936 * @param pVCpu The cross context virtual CPU structure.
4937 * @param uVector The interrupt that was acknowledged using an EOI.
4938 */
4939static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4940{
4941 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4942 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4943
4944 if (uVector < 64)
4945 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4946 if (uVector < 128)
4947 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4948 if (uVector < 192)
4949 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4950 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4951}
4952
4953
4954/**
4955 * Performs EOI virtualization.
4956 *
4957 * @returns VBox strict status code.
4958 * @param pVCpu The cross context virtual CPU structure.
4959 */
4960static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4961{
4962 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4963 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4964
4965 /*
4966 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4967 * and get the next guest-interrupt that's in-service (if any).
4968 *
4969 * See Intel spec. 29.1.4 "EOI Virtualization".
4970 */
4971 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4972 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4973 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4974
4975 uint8_t uVector = uSvi;
4976 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4977
4978 uVector = 0;
4979 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4980
4981 if (uVector)
4982 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4983 else
4984 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4985
4986 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4987 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4988
4989 iemVmxPprVirtualization(pVCpu);
4990 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4991 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4992 iemVmxEvalPendingVirtIntrs(pVCpu);
4993 return VINF_SUCCESS;
4994}
4995
4996
4997/**
4998 * Performs self-IPI virtualization.
4999 *
5000 * @returns VBox strict status code.
5001 * @param pVCpu The cross context virtual CPU structure.
5002 */
5003static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
5004{
5005 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5006 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5007
5008 /*
5009 * We should have already performed the virtual-APIC write to the self-IPI offset
5010 * in the virtual-APIC page. We now perform self-IPI virtualization.
5011 *
5012 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5013 */
5014 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5015 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5016 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5017 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5018 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5019 if (uVector > uRvi)
5020 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5021 iemVmxEvalPendingVirtIntrs(pVCpu);
5022 return VINF_SUCCESS;
5023}
5024
5025
5026/**
5027 * Performs VMX APIC-write emulation.
5028 *
5029 * @returns VBox strict status code.
5030 * @param pVCpu The cross context virtual CPU structure.
5031 */
5032VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
5033{
5034 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5035
5036 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5037 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5038
5039 /*
5040 * Perform APIC-write emulation based on the virtual-APIC register written.
5041 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5042 */
5043 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5044 VBOXSTRICTRC rcStrict;
5045 switch (offApicWrite)
5046 {
5047 case XAPIC_OFF_TPR:
5048 {
5049 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5050 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5051 uTpr &= UINT32_C(0x000000ff);
5052 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5053 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5054 rcStrict = iemVmxTprVirtualization(pVCpu);
5055 break;
5056 }
5057
5058 case XAPIC_OFF_EOI:
5059 {
5060 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5061 {
5062 /* Clear VEOI and perform EOI virtualization. */
5063 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5064 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5065 rcStrict = iemVmxEoiVirtualization(pVCpu);
5066 }
5067 else
5068 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5069 break;
5070 }
5071
5072 case XAPIC_OFF_ICR_LO:
5073 {
5074 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5075 {
5076 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5077 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5078 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5079 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5080 if ( !(uIcrLo & fIcrLoMb0)
5081 && (uIcrLo & fIcrLoMb1))
5082 {
5083 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5084 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5085 }
5086 else
5087 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5088 }
5089 else
5090 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5091 break;
5092 }
5093
5094 case XAPIC_OFF_ICR_HI:
5095 {
5096 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5097 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5098 uIcrHi &= UINT32_C(0xff000000);
5099 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5100 rcStrict = VINF_SUCCESS;
5101 break;
5102 }
5103
5104 default:
5105 {
5106 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5107 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5108 break;
5109 }
5110 }
5111
5112 return rcStrict;
5113}
5114
5115
5116/**
5117 * Interface for HM and EM to perform an APIC-write emulation which may cause a
5118 * VM-exit.
5119 *
5120 * @returns Strict VBox status code.
5121 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
5122 * @thread EMT(pVCpu)
5123 */
5124VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5125{
5126 VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5127 Assert(!pVCpu->iem.s.cActiveMappings);
5128 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5129}
5130
5131
5132/**
5133 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5134 *
5135 * @param pVCpu The cross context virtual CPU structure.
5136 * @param pszInstr The VMX instruction name (for logging purposes).
5137 */
5138DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5139{
5140 /*
5141 * Guest Control Registers, Debug Registers, and MSRs.
5142 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5143 */
5144 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5145 const char * const pszFailure = "VM-exit";
5146 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5147
5148 /* CR0 reserved bits. */
5149 {
5150 /* CR0 MB1 bits. */
5151 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
5152 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5153 { /* likely */ }
5154 else
5155 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5156
5157 /* CR0 MBZ bits. */
5158 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5159 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5160 { /* likely */ }
5161 else
5162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5163
5164 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5165 if ( !fUnrestrictedGuest
5166 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5167 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5168 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5169 }
5170
5171 /* CR4 reserved bits. */
5172 {
5173 /* CR4 MB1 bits. */
5174 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5175 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5176 { /* likely */ }
5177 else
5178 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5179
5180 /* CR4 MBZ bits. */
5181 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5182 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5183 { /* likely */ }
5184 else
5185 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5186 }
5187
5188 /* DEBUGCTL MSR. */
5189 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5190 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5191 { /* likely */ }
5192 else
5193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5194
5195 /* 64-bit CPU checks. */
5196 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5197 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5198 {
5199 if (fGstInLongMode)
5200 {
5201 /* PAE must be set. */
5202 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5203 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5204 { /* likely */ }
5205 else
5206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5207 }
5208 else
5209 {
5210 /* PCIDE should not be set. */
5211 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5212 { /* likely */ }
5213 else
5214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5215 }
5216
5217 /* CR3. */
5218 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5219 { /* likely */ }
5220 else
5221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5222
5223 /* DR7. */
5224 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5225 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5226 { /* likely */ }
5227 else
5228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5229
5230 /* SYSENTER ESP and SYSENTER EIP. */
5231 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5232 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5233 { /* likely */ }
5234 else
5235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5236 }
5237
5238 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5239 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5240
5241 /* PAT MSR. */
5242 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5243 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5244 { /* likely */ }
5245 else
5246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5247
5248 /* EFER MSR. */
5249 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5250 {
5251 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5252 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5253 { /* likely */ }
5254 else
5255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5256
5257 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5258 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5259 if ( fGstLma == fGstInLongMode
5260 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5261 || fGstLma == fGstLme))
5262 { /* likely */ }
5263 else
5264 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5265 }
5266
5267 /* We don't support IA32_BNDCFGS MSR yet. */
5268 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5269
5270 NOREF(pszInstr);
5271 NOREF(pszFailure);
5272 return VINF_SUCCESS;
5273}
5274
5275
5276/**
5277 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5278 *
5279 * @param pVCpu The cross context virtual CPU structure.
5280 * @param pszInstr The VMX instruction name (for logging purposes).
5281 */
5282DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5283{
5284 /*
5285 * Segment registers.
5286 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5287 */
5288 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5289 const char * const pszFailure = "VM-exit";
5290 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5291 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5292 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5293
5294 /* Selectors. */
5295 if ( !fGstInV86Mode
5296 && !fUnrestrictedGuest
5297 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5299
5300 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5301 {
5302 CPUMSELREG SelReg;
5303 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5304 if (RT_LIKELY(rc == VINF_SUCCESS))
5305 { /* likely */ }
5306 else
5307 return rc;
5308
5309 /*
5310 * Virtual-8086 mode checks.
5311 */
5312 if (fGstInV86Mode)
5313 {
5314 /* Base address. */
5315 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5316 { /* likely */ }
5317 else
5318 {
5319 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5320 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5321 }
5322
5323 /* Limit. */
5324 if (SelReg.u32Limit == 0xffff)
5325 { /* likely */ }
5326 else
5327 {
5328 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5329 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5330 }
5331
5332 /* Attribute. */
5333 if (SelReg.Attr.u == 0xf3)
5334 { /* likely */ }
5335 else
5336 {
5337 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5338 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5339 }
5340
5341 /* We're done; move to checking the next segment. */
5342 continue;
5343 }
5344
5345 /* Checks done by 64-bit CPUs. */
5346 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5347 {
5348 /* Base address. */
5349 if ( iSegReg == X86_SREG_FS
5350 || iSegReg == X86_SREG_GS)
5351 {
5352 if (X86_IS_CANONICAL(SelReg.u64Base))
5353 { /* likely */ }
5354 else
5355 {
5356 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5357 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5358 }
5359 }
5360 else if (iSegReg == X86_SREG_CS)
5361 {
5362 if (!RT_HI_U32(SelReg.u64Base))
5363 { /* likely */ }
5364 else
5365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5366 }
5367 else
5368 {
5369 if ( SelReg.Attr.n.u1Unusable
5370 || !RT_HI_U32(SelReg.u64Base))
5371 { /* likely */ }
5372 else
5373 {
5374 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5375 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5376 }
5377 }
5378 }
5379
5380 /*
5381 * Checks outside Virtual-8086 mode.
5382 */
5383 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5384 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5385 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5386 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5387 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5388 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5389 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5390 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5391
5392 /* Code or usable segment. */
5393 if ( iSegReg == X86_SREG_CS
5394 || fUsable)
5395 {
5396 /* Reserved bits (bits 31:17 and bits 11:8). */
5397 if (!(SelReg.Attr.u & 0xfffe0f00))
5398 { /* likely */ }
5399 else
5400 {
5401 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5402 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5403 }
5404
5405 /* Descriptor type. */
5406 if (fCodeDataSeg)
5407 { /* likely */ }
5408 else
5409 {
5410 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5411 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5412 }
5413
5414 /* Present. */
5415 if (fPresent)
5416 { /* likely */ }
5417 else
5418 {
5419 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5420 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5421 }
5422
5423 /* Granularity. */
5424 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5425 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5426 { /* likely */ }
5427 else
5428 {
5429 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5430 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5431 }
5432 }
5433
5434 if (iSegReg == X86_SREG_CS)
5435 {
5436 /* Segment Type and DPL. */
5437 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5438 && fUnrestrictedGuest)
5439 {
5440 if (uDpl == 0)
5441 { /* likely */ }
5442 else
5443 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5444 }
5445 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5446 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5447 {
5448 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5449 if (uDpl == AttrSs.n.u2Dpl)
5450 { /* likely */ }
5451 else
5452 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5453 }
5454 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5455 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5456 {
5457 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5458 if (uDpl <= AttrSs.n.u2Dpl)
5459 { /* likely */ }
5460 else
5461 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5462 }
5463 else
5464 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5465
5466 /* Def/Big. */
5467 if ( fGstInLongMode
5468 && fSegLong)
5469 {
5470 if (uDefBig == 0)
5471 { /* likely */ }
5472 else
5473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5474 }
5475 }
5476 else if (iSegReg == X86_SREG_SS)
5477 {
5478 /* Segment Type. */
5479 if ( !fUsable
5480 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5481 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5482 { /* likely */ }
5483 else
5484 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5485
5486 /* DPL. */
5487 if (!fUnrestrictedGuest)
5488 {
5489 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5490 { /* likely */ }
5491 else
5492 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5493 }
5494 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5495 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5496 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5497 {
5498 if (uDpl == 0)
5499 { /* likely */ }
5500 else
5501 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5502 }
5503 }
5504 else
5505 {
5506 /* DS, ES, FS, GS. */
5507 if (fUsable)
5508 {
5509 /* Segment type. */
5510 if (uSegType & X86_SEL_TYPE_ACCESSED)
5511 { /* likely */ }
5512 else
5513 {
5514 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5515 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5516 }
5517
5518 if ( !(uSegType & X86_SEL_TYPE_CODE)
5519 || (uSegType & X86_SEL_TYPE_READ))
5520 { /* likely */ }
5521 else
5522 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5523
5524 /* DPL. */
5525 if ( !fUnrestrictedGuest
5526 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5527 {
5528 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5529 { /* likely */ }
5530 else
5531 {
5532 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5533 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5534 }
5535 }
5536 }
5537 }
5538 }
5539
5540 /*
5541 * LDTR.
5542 */
5543 {
5544 CPUMSELREG Ldtr;
5545 Ldtr.Sel = pVmcs->GuestLdtr;
5546 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5547 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5548 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5549
5550 if (!Ldtr.Attr.n.u1Unusable)
5551 {
5552 /* Selector. */
5553 if (!(Ldtr.Sel & X86_SEL_LDT))
5554 { /* likely */ }
5555 else
5556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5557
5558 /* Base. */
5559 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5560 {
5561 if (X86_IS_CANONICAL(Ldtr.u64Base))
5562 { /* likely */ }
5563 else
5564 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5565 }
5566
5567 /* Attributes. */
5568 /* Reserved bits (bits 31:17 and bits 11:8). */
5569 if (!(Ldtr.Attr.u & 0xfffe0f00))
5570 { /* likely */ }
5571 else
5572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5573
5574 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5575 { /* likely */ }
5576 else
5577 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5578
5579 if (!Ldtr.Attr.n.u1DescType)
5580 { /* likely */ }
5581 else
5582 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5583
5584 if (Ldtr.Attr.n.u1Present)
5585 { /* likely */ }
5586 else
5587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5588
5589 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5590 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5591 { /* likely */ }
5592 else
5593 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5594 }
5595 }
5596
5597 /*
5598 * TR.
5599 */
5600 {
5601 CPUMSELREG Tr;
5602 Tr.Sel = pVmcs->GuestTr;
5603 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5604 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5605 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5606
5607 /* Selector. */
5608 if (!(Tr.Sel & X86_SEL_LDT))
5609 { /* likely */ }
5610 else
5611 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5612
5613 /* Base. */
5614 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5615 {
5616 if (X86_IS_CANONICAL(Tr.u64Base))
5617 { /* likely */ }
5618 else
5619 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5620 }
5621
5622 /* Attributes. */
5623 /* Reserved bits (bits 31:17 and bits 11:8). */
5624 if (!(Tr.Attr.u & 0xfffe0f00))
5625 { /* likely */ }
5626 else
5627 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5628
5629 if (!Tr.Attr.n.u1Unusable)
5630 { /* likely */ }
5631 else
5632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5633
5634 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5635 || ( !fGstInLongMode
5636 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5637 { /* likely */ }
5638 else
5639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5640
5641 if (!Tr.Attr.n.u1DescType)
5642 { /* likely */ }
5643 else
5644 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5645
5646 if (Tr.Attr.n.u1Present)
5647 { /* likely */ }
5648 else
5649 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5650
5651 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5652 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5653 { /* likely */ }
5654 else
5655 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5656 }
5657
5658 NOREF(pszInstr);
5659 NOREF(pszFailure);
5660 return VINF_SUCCESS;
5661}
5662
5663
5664/**
5665 * Checks guest GDTR and IDTR as part of VM-entry.
5666 *
5667 * @param pVCpu The cross context virtual CPU structure.
5668 * @param pszInstr The VMX instruction name (for logging purposes).
5669 */
5670DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5671{
5672 /*
5673 * GDTR and IDTR.
5674 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5675 */
5676 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5677 const char *const pszFailure = "VM-exit";
5678
5679 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5680 {
5681 /* Base. */
5682 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5683 { /* likely */ }
5684 else
5685 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5686
5687 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5688 { /* likely */ }
5689 else
5690 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5691 }
5692
5693 /* Limit. */
5694 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5695 { /* likely */ }
5696 else
5697 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5698
5699 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5700 { /* likely */ }
5701 else
5702 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5703
5704 NOREF(pszInstr);
5705 NOREF(pszFailure);
5706 return VINF_SUCCESS;
5707}
5708
5709
5710/**
5711 * Checks guest RIP and RFLAGS as part of VM-entry.
5712 *
5713 * @param pVCpu The cross context virtual CPU structure.
5714 * @param pszInstr The VMX instruction name (for logging purposes).
5715 */
5716DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5717{
5718 /*
5719 * RIP and RFLAGS.
5720 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5721 */
5722 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5723 const char *const pszFailure = "VM-exit";
5724 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5725
5726 /* RIP. */
5727 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5728 {
5729 X86DESCATTR AttrCs;
5730 AttrCs.u = pVmcs->u32GuestCsAttr;
5731 if ( !fGstInLongMode
5732 || !AttrCs.n.u1Long)
5733 {
5734 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5735 { /* likely */ }
5736 else
5737 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5738 }
5739
5740 if ( fGstInLongMode
5741 && AttrCs.n.u1Long)
5742 {
5743 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5744 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5745 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5746 { /* likely */ }
5747 else
5748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5749 }
5750 }
5751
5752 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5753 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5754 : pVmcs->u64GuestRFlags.s.Lo;
5755 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5756 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5757 { /* likely */ }
5758 else
5759 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5760
5761 if (!(uGuestRFlags & X86_EFL_VM))
5762 { /* likely */ }
5763 else
5764 {
5765 if ( fGstInLongMode
5766 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5767 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5768 }
5769
5770 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5771 {
5772 if (uGuestRFlags & X86_EFL_IF)
5773 { /* likely */ }
5774 else
5775 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5776 }
5777
5778 NOREF(pszInstr);
5779 NOREF(pszFailure);
5780 return VINF_SUCCESS;
5781}
5782
5783
5784/**
5785 * Checks guest non-register state as part of VM-entry.
5786 *
5787 * @param pVCpu The cross context virtual CPU structure.
5788 * @param pszInstr The VMX instruction name (for logging purposes).
5789 */
5790DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5791{
5792 /*
5793 * Guest non-register state.
5794 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5795 */
5796 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5797 const char *const pszFailure = "VM-exit";
5798
5799 /*
5800 * Activity state.
5801 */
5802 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5803 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5804 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5805 { /* likely */ }
5806 else
5807 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5808
5809 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5810 if ( !AttrSs.n.u2Dpl
5811 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5812 { /* likely */ }
5813 else
5814 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5815
5816 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5817 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5818 {
5819 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5820 { /* likely */ }
5821 else
5822 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5823 }
5824
5825 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5826 {
5827 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5828 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5829 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5830 switch (pVmcs->u32GuestActivityState)
5831 {
5832 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5833 {
5834 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5835 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5836 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5837 && ( uVector == X86_XCPT_DB
5838 || uVector == X86_XCPT_MC))
5839 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5840 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5841 { /* likely */ }
5842 else
5843 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5844 break;
5845 }
5846
5847 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5848 {
5849 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5850 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5851 && uVector == X86_XCPT_MC))
5852 { /* likely */ }
5853 else
5854 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5855 break;
5856 }
5857
5858 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5859 default:
5860 break;
5861 }
5862 }
5863
5864 /*
5865 * Interruptibility state.
5866 */
5867 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5868 { /* likely */ }
5869 else
5870 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5871
5872 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5873 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5874 { /* likely */ }
5875 else
5876 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5877
5878 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5879 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5880 { /* likely */ }
5881 else
5882 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5883
5884 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5885 {
5886 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5887 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5888 {
5889 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5890 { /* likely */ }
5891 else
5892 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5893 }
5894 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5895 {
5896 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5897 { /* likely */ }
5898 else
5899 {
5900 /*
5901 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5902 * We update the Exit qualification only when blocking-by-STI is set
5903 * without blocking-by-MovSS being set. Although in practise it does not
5904 * make much difference since the order of checks are implementation defined.
5905 */
5906 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5907 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5908 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5909 }
5910
5911 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5912 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5913 { /* likely */ }
5914 else
5915 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5916 }
5917 }
5918
5919 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5920 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5921 { /* likely */ }
5922 else
5923 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5924
5925 /* We don't support SGX yet. So enclave-interruption must not be set. */
5926 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5927 { /* likely */ }
5928 else
5929 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5930
5931 /*
5932 * Pending debug exceptions.
5933 */
5934 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5935 ? pVmcs->u64GuestPendingDbgXcpts.u
5936 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5937 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5938 { /* likely */ }
5939 else
5940 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5941
5942 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5943 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5944 {
5945 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5946 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5947 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5948 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5949
5950 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5951 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5952 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5953 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5954 }
5955
5956 /* We don't support RTM (Real-time Transactional Memory) yet. */
5957 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5958 { /* likely */ }
5959 else
5960 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5961
5962 /*
5963 * VMCS link pointer.
5964 */
5965 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5966 {
5967 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5968 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5969 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5970 { /* likely */ }
5971 else
5972 {
5973 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5974 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5975 }
5976
5977 /* Validate the address. */
5978 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5979 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5980 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5981 { /* likely */ }
5982 else
5983 {
5984 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5985 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5986 }
5987 }
5988
5989 NOREF(pszInstr);
5990 NOREF(pszFailure);
5991 return VINF_SUCCESS;
5992}
5993
5994
5995#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5996/**
5997 * Checks guest PDPTEs as part of VM-entry.
5998 *
5999 * @param pVCpu The cross context virtual CPU structure.
6000 * @param pszInstr The VMX instruction name (for logging purposes).
6001 */
6002static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6003{
6004 /*
6005 * Guest PDPTEs.
6006 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6007 */
6008 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6009 const char * const pszFailure = "VM-exit";
6010
6011 /*
6012 * When EPT is used, we need to validate the PAE PDPTEs provided in the VMCS.
6013 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
6014 */
6015 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
6016 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
6017 {
6018 /* Get PDPTEs from the VMCS. */
6019 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6020 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6021 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6022 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6023 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6024
6025 /* Check validity of the PDPTEs. */
6026 if (PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]))
6027 { /* likely */ }
6028 else
6029 {
6030 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6031 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6032 }
6033 }
6034
6035 NOREF(pszFailure);
6036 NOREF(pszInstr);
6037 return VINF_SUCCESS;
6038}
6039#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6040
6041
6042/**
6043 * Checks guest-state as part of VM-entry.
6044 *
6045 * @returns VBox status code.
6046 * @param pVCpu The cross context virtual CPU structure.
6047 * @param pszInstr The VMX instruction name (for logging purposes).
6048 */
6049static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6050{
6051 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6052 if (RT_SUCCESS(rc))
6053 {
6054 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6055 if (RT_SUCCESS(rc))
6056 {
6057 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6058 if (RT_SUCCESS(rc))
6059 {
6060 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6061 if (RT_SUCCESS(rc))
6062 {
6063 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6064#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6065 if (RT_SUCCESS(rc))
6066 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6067#endif
6068 }
6069 }
6070 }
6071 }
6072 return rc;
6073}
6074
6075
6076/**
6077 * Checks host-state as part of VM-entry.
6078 *
6079 * @returns VBox status code.
6080 * @param pVCpu The cross context virtual CPU structure.
6081 * @param pszInstr The VMX instruction name (for logging purposes).
6082 */
6083static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6084{
6085 /*
6086 * Host Control Registers and MSRs.
6087 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6088 */
6089 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6090 const char * const pszFailure = "VMFail";
6091
6092 /* CR0 reserved bits. */
6093 {
6094 /* CR0 MB1 bits. */
6095 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
6096 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6097 { /* likely */ }
6098 else
6099 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6100
6101 /* CR0 MBZ bits. */
6102 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6103 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6104 { /* likely */ }
6105 else
6106 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6107 }
6108
6109 /* CR4 reserved bits. */
6110 {
6111 /* CR4 MB1 bits. */
6112 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6113 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6114 { /* likely */ }
6115 else
6116 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6117
6118 /* CR4 MBZ bits. */
6119 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6120 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6121 { /* likely */ }
6122 else
6123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6124 }
6125
6126 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6127 {
6128 /* CR3 reserved bits. */
6129 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6130 { /* likely */ }
6131 else
6132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6133
6134 /* SYSENTER ESP and SYSENTER EIP. */
6135 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6136 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6137 { /* likely */ }
6138 else
6139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6140 }
6141
6142 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6143 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6144
6145 /* PAT MSR. */
6146 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6147 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6148 { /* likely */ }
6149 else
6150 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6151
6152 /* EFER MSR. */
6153 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6154 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6155 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6156 {
6157 if (!(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6158 { /* likely */ }
6159 else
6160 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6161
6162 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6163 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6164 if ( fHostInLongMode == fHostLma
6165 && fHostInLongMode == fHostLme)
6166 { /* likely */ }
6167 else
6168 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6169 }
6170
6171 /*
6172 * Host Segment and Descriptor-Table Registers.
6173 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6174 */
6175 /* Selector RPL and TI. */
6176 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6177 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6178 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6179 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6180 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6181 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6182 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6183 { /* likely */ }
6184 else
6185 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6186
6187 /* CS and TR selectors cannot be 0. */
6188 if ( pVmcs->HostCs
6189 && pVmcs->HostTr)
6190 { /* likely */ }
6191 else
6192 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6193
6194 /* SS cannot be 0 if 32-bit host. */
6195 if ( fHostInLongMode
6196 || pVmcs->HostSs)
6197 { /* likely */ }
6198 else
6199 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6200
6201 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6202 {
6203 /* FS, GS, GDTR, IDTR, TR base address. */
6204 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6205 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6206 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6207 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6208 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6209 { /* likely */ }
6210 else
6211 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6212 }
6213
6214 /*
6215 * Host address-space size for 64-bit CPUs.
6216 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6217 */
6218 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6219 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6220 {
6221 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6222
6223 /* Logical processor in IA-32e mode. */
6224 if (fCpuInLongMode)
6225 {
6226 if (fHostInLongMode)
6227 {
6228 /* PAE must be set. */
6229 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6230 { /* likely */ }
6231 else
6232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6233
6234 /* RIP must be canonical. */
6235 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6236 { /* likely */ }
6237 else
6238 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6239 }
6240 else
6241 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6242 }
6243 else
6244 {
6245 /* Logical processor is outside IA-32e mode. */
6246 if ( !fGstInLongMode
6247 && !fHostInLongMode)
6248 {
6249 /* PCIDE should not be set. */
6250 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6251 { /* likely */ }
6252 else
6253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6254
6255 /* The high 32-bits of RIP MBZ. */
6256 if (!pVmcs->u64HostRip.s.Hi)
6257 { /* likely */ }
6258 else
6259 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6260 }
6261 else
6262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6263 }
6264 }
6265 else
6266 {
6267 /* Host address-space size for 32-bit CPUs. */
6268 if ( !fGstInLongMode
6269 && !fHostInLongMode)
6270 { /* likely */ }
6271 else
6272 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6273 }
6274
6275 NOREF(pszInstr);
6276 NOREF(pszFailure);
6277 return VINF_SUCCESS;
6278}
6279
6280
6281#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6282/**
6283 * Checks the EPT pointer VMCS field as part of VM-entry.
6284 *
6285 * @returns VBox status code.
6286 * @param pVCpu The cross context virtual CPU structure.
6287 * @param uEptPtr The EPT pointer to check.
6288 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
6289 * updated on success). Optional, can be NULL.
6290 */
6291static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6292{
6293 VMXVDIAG enmVmxDiag;
6294
6295 /* Reserved bits. */
6296 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6297 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6298 if (uEptPtr & fValidMask)
6299 {
6300 /* Memory Type. */
6301 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6302 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6303 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6304 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6305 || ( fMemType == VMX_EPTP_MEMTYPE_UC
6306 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6307 {
6308 /*
6309 * Page walk length (PML4).
6310 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6311 * of 5 but that seems to be removed from the latest specs. leaving only PML4
6312 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6313 */
6314 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6315 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6316 {
6317 /* Access and dirty bits support in EPT structures. */
6318 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6319 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6320 return VINF_SUCCESS;
6321
6322 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6323 }
6324 else
6325 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6326 }
6327 else
6328 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6329 }
6330 else
6331 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6332
6333 if (penmVmxDiag)
6334 *penmVmxDiag = enmVmxDiag;
6335 return VERR_VMX_VMENTRY_FAILED;
6336}
6337#endif
6338
6339
6340/**
6341 * Checks VMCS controls fields as part of VM-entry.
6342 *
6343 * @returns VBox status code.
6344 * @param pVCpu The cross context virtual CPU structure.
6345 * @param pszInstr The VMX instruction name (for logging purposes).
6346 *
6347 * @remarks This may update secondary-processor based VM-execution control fields
6348 * in the current VMCS if necessary.
6349 */
6350static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6351{
6352 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6353 const char * const pszFailure = "VMFail";
6354 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6355
6356 /*
6357 * VM-execution controls.
6358 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6359 */
6360 {
6361 /* Pin-based VM-execution controls. */
6362 {
6363 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6364 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6365 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6366 { /* likely */ }
6367 else
6368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6369
6370 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6371 { /* likely */ }
6372 else
6373 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6374 }
6375
6376 /* Processor-based VM-execution controls. */
6377 {
6378 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6379 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6380 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6381 { /* likely */ }
6382 else
6383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6384
6385 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6386 { /* likely */ }
6387 else
6388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6389 }
6390
6391 /* Secondary processor-based VM-execution controls. */
6392 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6393 {
6394 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6395 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6396 { /* likely */ }
6397 else
6398 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6399
6400 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6401 { /* likely */ }
6402 else
6403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6404 }
6405 else if (pVmcs->u32ProcCtls2)
6406 {
6407 /*
6408 * If the "activate secondary controls" is clear, then the secondary processor-based VM-execution controls
6409 * is treated as 0.
6410 *
6411 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6412 *
6413 * Since this is a rather rare occurrence (only observed for a few VM-entries with Microsoft Hyper-V
6414 * enabled Windows Server 2008 R2 guest), it's not worth changing every place that reads this control to
6415 * also check the "activate secondary controls" bit. Instead, we temporarily save the guest programmed
6416 * control here, zero out the value the rest of our code uses and restore the guest programmed value
6417 * on VM-exit.
6418 */
6419 pVmcs->u32RestoreProcCtls2 = pVmcs->u32ProcCtls2;
6420 pVmcs->u32ProcCtls2 = 0;
6421 }
6422
6423 /* CR3-target count. */
6424 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6425 { /* likely */ }
6426 else
6427 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6428
6429 /* I/O bitmaps physical addresses. */
6430 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6431 {
6432 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6433 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6434 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6435 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6436 { /* likely */ }
6437 else
6438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6439
6440 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6441 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6442 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6443 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6444 { /* likely */ }
6445 else
6446 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6447 }
6448
6449 /* MSR bitmap physical address. */
6450 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6451 {
6452 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6453 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6454 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6455 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6456 { /* likely */ }
6457 else
6458 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6459 }
6460
6461 /* TPR shadow related controls. */
6462 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6463 {
6464 /* Virtual-APIC page physical address. */
6465 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6466 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6467 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6468 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6469 { /* likely */ }
6470 else
6471 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6472
6473 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6474 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6475 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6476 { /* likely */ }
6477 else
6478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6479
6480 /* The rest done XXX document */
6481 }
6482 else
6483 {
6484 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6485 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6486 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6487 { /* likely */ }
6488 else
6489 {
6490 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6491 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6492 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6493 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6494 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6496 }
6497 }
6498
6499 /* NMI exiting and virtual-NMIs. */
6500 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6501 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6502 { /* likely */ }
6503 else
6504 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6505
6506 /* Virtual-NMIs and NMI-window exiting. */
6507 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6508 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6509 { /* likely */ }
6510 else
6511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6512
6513 /* Virtualize APIC accesses. */
6514 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6515 {
6516 /* APIC-access physical address. */
6517 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6518 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6519 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6520 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6521 { /* likely */ }
6522 else
6523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6524
6525 /*
6526 * Disallow APIC-access page and virtual-APIC page from being the same address.
6527 * Note! This is not an Intel requirement, but one imposed by our implementation.
6528 */
6529 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6530 * redirecting accesses between the APIC-access page and the virtual-APIC
6531 * page. If any nested hypervisor requires this, we can implement it later. */
6532 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6533 {
6534 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6535 if (GCPhysVirtApic != GCPhysApicAccess)
6536 { /* likely */ }
6537 else
6538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6539 }
6540 }
6541
6542 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6543 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6544 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6545 { /* likely */ }
6546 else
6547 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6548
6549 /* Virtual-interrupt delivery requires external interrupt exiting. */
6550 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6551 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6552 { /* likely */ }
6553 else
6554 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6555
6556 /* VPID. */
6557 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6558 || pVmcs->u16Vpid != 0)
6559 { /* likely */ }
6560 else
6561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6562
6563#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6564 /* Extended-Page-Table Pointer (EPTP). */
6565 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6566 {
6567 VMXVDIAG enmVmxDiag;
6568 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6569 if (RT_SUCCESS(rc))
6570 { /* likely */ }
6571 else
6572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6573 }
6574#else
6575 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6576 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6577#endif
6578 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6579 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6580 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6581 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6582 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6583
6584 /* VMCS shadowing. */
6585 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6586 {
6587 /* VMREAD-bitmap physical address. */
6588 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6589 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6590 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6591 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6592 { /* likely */ }
6593 else
6594 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6595
6596 /* VMWRITE-bitmap physical address. */
6597 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6598 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6599 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6600 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6601 { /* likely */ }
6602 else
6603 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6604 }
6605 }
6606
6607 /*
6608 * VM-exit controls.
6609 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6610 */
6611 {
6612 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6613 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6614 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6615 { /* likely */ }
6616 else
6617 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6618
6619 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6620 { /* likely */ }
6621 else
6622 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6623
6624 /* Save preemption timer without activating it. */
6625 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6626 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6627 { /* likely */ }
6628 else
6629 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6630
6631 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6632 if (pVmcs->u32ExitMsrStoreCount)
6633 {
6634 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6635 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6636 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6637 { /* likely */ }
6638 else
6639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6640 }
6641
6642 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6643 if (pVmcs->u32ExitMsrLoadCount)
6644 {
6645 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6646 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6647 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6648 { /* likely */ }
6649 else
6650 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6651 }
6652 }
6653
6654 /*
6655 * VM-entry controls.
6656 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6657 */
6658 {
6659 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6660 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6661 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6662 { /* likely */ }
6663 else
6664 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6665
6666 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6667 { /* likely */ }
6668 else
6669 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6670
6671 /* Event injection. */
6672 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6673 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6674 {
6675 /* Type and vector. */
6676 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6677 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6678 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6679 if ( !uRsvd
6680 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6681 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6682 { /* likely */ }
6683 else
6684 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6685
6686 /* Exception error code. */
6687 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6688 {
6689 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6690 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6691 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6692 { /* likely */ }
6693 else
6694 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6695
6696 /* Exceptions that provide an error code. */
6697 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6698 && ( uVector == X86_XCPT_DF
6699 || uVector == X86_XCPT_TS
6700 || uVector == X86_XCPT_NP
6701 || uVector == X86_XCPT_SS
6702 || uVector == X86_XCPT_GP
6703 || uVector == X86_XCPT_PF
6704 || uVector == X86_XCPT_AC))
6705 { /* likely */ }
6706 else
6707 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6708
6709 /* Exception error-code reserved bits. */
6710 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6711 { /* likely */ }
6712 else
6713 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6714
6715 /* Injecting a software interrupt, software exception or privileged software exception. */
6716 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6717 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6718 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6719 {
6720 /* Instruction length must be in the range 0-15. */
6721 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6722 { /* likely */ }
6723 else
6724 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6725
6726 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6727 if ( pVmcs->u32EntryInstrLen != 0
6728 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6729 { /* likely */ }
6730 else
6731 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6732 }
6733 }
6734 }
6735
6736 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6737 if (pVmcs->u32EntryMsrLoadCount)
6738 {
6739 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6740 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6741 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6742 { /* likely */ }
6743 else
6744 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6745 }
6746
6747 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6748 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6749 }
6750
6751 NOREF(pszInstr);
6752 NOREF(pszFailure);
6753 return VINF_SUCCESS;
6754}
6755
6756
6757/**
6758 * Loads the guest control registers, debug register and some MSRs as part of
6759 * VM-entry.
6760 *
6761 * @param pVCpu The cross context virtual CPU structure.
6762 */
6763static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6764{
6765 /*
6766 * Load guest control registers, debug registers and MSRs.
6767 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6768 */
6769 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6770
6771 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6772 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6773 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6774 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6775 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6776 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6777
6778 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6779 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6780
6781 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6782 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6783 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6784
6785 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6786 {
6787 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6788
6789 /* EFER MSR. */
6790 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6791 {
6792 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6793 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6794 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6795 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6796 if (fGstInLongMode)
6797 {
6798 /* If the nested-guest is in long mode, LMA and LME are both set. */
6799 Assert(fGstPaging);
6800 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6801 }
6802 else
6803 {
6804 /*
6805 * If the nested-guest is outside long mode:
6806 * - With paging: LMA is cleared, LME is cleared.
6807 * - Without paging: LMA is cleared, LME is left unmodified.
6808 */
6809 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6810 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6811 }
6812 }
6813 /* else: see below. */
6814 }
6815
6816 /* PAT MSR. */
6817 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6818 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6819
6820 /* EFER MSR. */
6821 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6822 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6823
6824 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6825 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6826
6827 /* We don't support IA32_BNDCFGS MSR yet. */
6828 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6829
6830 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6831}
6832
6833
6834/**
6835 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6836 *
6837 * @param pVCpu The cross context virtual CPU structure.
6838 */
6839static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6840{
6841 /*
6842 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6843 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6844 */
6845 /* CS, SS, ES, DS, FS, GS. */
6846 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6847 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6848 {
6849 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6850 CPUMSELREG VmcsSelReg;
6851 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6852 AssertRC(rc); NOREF(rc);
6853 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6854 {
6855 pGstSelReg->Sel = VmcsSelReg.Sel;
6856 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6857 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6858 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6859 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6860 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6861 }
6862 else
6863 {
6864 pGstSelReg->Sel = VmcsSelReg.Sel;
6865 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6866 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6867 switch (iSegReg)
6868 {
6869 case X86_SREG_CS:
6870 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6871 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6872 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6873 break;
6874
6875 case X86_SREG_SS:
6876 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6877 pGstSelReg->u32Limit = 0;
6878 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6879 break;
6880
6881 case X86_SREG_ES:
6882 case X86_SREG_DS:
6883 pGstSelReg->u64Base = 0;
6884 pGstSelReg->u32Limit = 0;
6885 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6886 break;
6887
6888 case X86_SREG_FS:
6889 case X86_SREG_GS:
6890 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6891 pGstSelReg->u32Limit = 0;
6892 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6893 break;
6894 }
6895 Assert(pGstSelReg->Attr.n.u1Unusable);
6896 }
6897 }
6898
6899 /* LDTR. */
6900 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6901 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6902 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6903 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6904 {
6905 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6906 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6907 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6908 }
6909 else
6910 {
6911 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6912 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6913 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6914 }
6915
6916 /* TR. */
6917 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6918 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6919 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6920 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6921 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6922 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6923 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6924
6925 /* GDTR. */
6926 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6927 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6928
6929 /* IDTR. */
6930 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6931 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6932}
6933
6934
6935/**
6936 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6937 *
6938 * @returns VBox status code.
6939 * @param pVCpu The cross context virtual CPU structure.
6940 * @param pszInstr The VMX instruction name (for logging purposes).
6941 */
6942static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6943{
6944 /*
6945 * Load guest MSRs.
6946 * See Intel spec. 26.4 "Loading MSRs".
6947 */
6948 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6949 const char *const pszFailure = "VM-exit";
6950
6951 /*
6952 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6953 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6954 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6955 */
6956 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6957 if (!cMsrs)
6958 return VINF_SUCCESS;
6959
6960 /*
6961 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6962 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6963 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6964 */
6965 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6966 if (fIsMsrCountValid)
6967 { /* likely */ }
6968 else
6969 {
6970 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6972 }
6973
6974 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6975 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6976 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6977 if (RT_SUCCESS(rc))
6978 {
6979 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6980 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6981 {
6982 if ( !pMsr->u32Reserved
6983 && pMsr->u32Msr != MSR_K8_FS_BASE
6984 && pMsr->u32Msr != MSR_K8_GS_BASE
6985 && pMsr->u32Msr != MSR_K6_EFER
6986 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6987 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6988 {
6989 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6990 if (rcStrict == VINF_SUCCESS)
6991 continue;
6992
6993 /*
6994 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6995 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6996 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6997 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6998 * MSR in ring-0 if possible, or come up with a better, generic solution.
6999 */
7000 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7001 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7002 ? kVmxVDiag_Vmentry_MsrLoadRing3
7003 : kVmxVDiag_Vmentry_MsrLoad;
7004 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7005 }
7006 else
7007 {
7008 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7009 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7010 }
7011 }
7012 }
7013 else
7014 {
7015 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7016 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7017 }
7018
7019 NOREF(pszInstr);
7020 NOREF(pszFailure);
7021 return VINF_SUCCESS;
7022}
7023
7024
7025/**
7026 * Loads the guest-state non-register state as part of VM-entry.
7027 *
7028 * @returns VBox status code.
7029 * @param pVCpu The cross context virtual CPU structure.
7030 * @param pszInstr The VMX instruction name (for logging purposes).
7031 *
7032 * @remarks This must be called only after loading the nested-guest register state
7033 * (especially nested-guest RIP).
7034 */
7035static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7036{
7037 /*
7038 * Load guest non-register state.
7039 * See Intel spec. 26.6 "Special Features of VM Entry"
7040 */
7041 const char *const pszFailure = "VM-exit";
7042 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7043
7044 /*
7045 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7046 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7047 *
7048 * See Intel spec. 26.6.1 "Interruptibility State".
7049 */
7050 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7051 if ( !fEntryVectoring
7052 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7053 CPUMSetInInterruptShadowEx(&pVCpu->cpum.GstCtx, pVmcs->u64GuestRip.u);
7054 else
7055 Assert(!CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx));
7056
7057 /* NMI blocking. */
7058 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7059 {
7060 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7061 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7062 else
7063 {
7064 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7065 CPUMSetInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx);
7066 }
7067 }
7068 else
7069 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7070
7071 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7072
7073 /*
7074 * Set PGM's copy of the EPT pointer.
7075 * The EPTP has already been validated while checking guest state.
7076 *
7077 * It is important to do this prior to mapping PAE PDPTEs (below).
7078 */
7079 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7080 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7081
7082 /*
7083 * Load the guest's PAE PDPTEs.
7084 */
7085 if (!iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7086 {
7087 /*
7088 * When PAE paging is not used we clear the PAE PDPTEs for safety
7089 * in case we might be switching from a PAE host to a non-PAE guest.
7090 */
7091 pVCpu->cpum.GstCtx.aPaePdpes[0].u = 0;
7092 pVCpu->cpum.GstCtx.aPaePdpes[1].u = 0;
7093 pVCpu->cpum.GstCtx.aPaePdpes[2].u = 0;
7094 pVCpu->cpum.GstCtx.aPaePdpes[3].u = 0;
7095 }
7096 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7097 {
7098 /*
7099 * With EPT and the nested-guest using PAE paging, we've already validated the PAE PDPTEs
7100 * while checking the guest state. We can load them into the nested-guest CPU state now.
7101 * They'll later be used while mapping CR3 and the PAE PDPTEs.
7102 */
7103 pVCpu->cpum.GstCtx.aPaePdpes[0].u = pVmcs->u64GuestPdpte0.u;
7104 pVCpu->cpum.GstCtx.aPaePdpes[1].u = pVmcs->u64GuestPdpte1.u;
7105 pVCpu->cpum.GstCtx.aPaePdpes[2].u = pVmcs->u64GuestPdpte2.u;
7106 pVCpu->cpum.GstCtx.aPaePdpes[3].u = pVmcs->u64GuestPdpte3.u;
7107 }
7108 else
7109 {
7110 /*
7111 * Without EPT and the nested-guest using PAE paging, we must load the PAE PDPTEs
7112 * referenced by CR3. This involves loading (and mapping) CR3 and validating them now.
7113 */
7114 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7115 if (RT_SUCCESS(rc))
7116 { /* likely */ }
7117 else
7118 {
7119 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7120 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
7121 }
7122 }
7123
7124 /* VPID is irrelevant. We don't support VPID yet. */
7125
7126 /* Clear address-range monitoring. */
7127 EMMonitorWaitClear(pVCpu);
7128
7129 return VINF_SUCCESS;
7130}
7131
7132
7133/**
7134 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7135 *
7136 * @param pVCpu The cross context virtual CPU structure.
7137 * @param pszInstr The VMX instruction name (for logging purposes).
7138 *
7139 * @remarks This assumes various VMCS related data structure pointers have already
7140 * been verified prior to calling this function.
7141 */
7142static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7143{
7144 const char *const pszFailure = "VM-exit";
7145 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7146
7147 /*
7148 * Virtualize APIC accesses.
7149 */
7150 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7151 {
7152 /* APIC-access physical address. */
7153 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7154
7155 /*
7156 * Register the handler for the APIC-access page.
7157 *
7158 * We don't deregister the APIC-access page handler during the VM-exit as a different
7159 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
7160 *
7161 * We leave the page registered until the first access that happens outside VMX non-root
7162 * mode. Guest software is allowed to access structures such as the APIC-access page
7163 * only when no logical processor with a current VMCS references it in VMX non-root mode,
7164 * otherwise it can lead to unpredictable behavior including guest triple-faults.
7165 *
7166 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7167 */
7168 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
7169 {
7170 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7171 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess | X86_PAGE_4K_OFFSET_MASK,
7172 pVM->iem.s.hVmxApicAccessPage, 0 /*uUser*/, NULL /*pszDesc*/);
7173 if (RT_SUCCESS(rc))
7174 { /* likely */ }
7175 else
7176 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
7177 }
7178 }
7179
7180 /*
7181 * VMCS shadowing.
7182 */
7183 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7184 {
7185 /* Read the VMREAD-bitmap. */
7186 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7187 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7188 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7189 if (RT_SUCCESS(rc))
7190 { /* likely */ }
7191 else
7192 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
7193
7194 /* Read the VMWRITE-bitmap. */
7195 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7196 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7197 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7198 if (RT_SUCCESS(rc))
7199 { /* likely */ }
7200 else
7201 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
7202 }
7203
7204 /*
7205 * I/O bitmaps.
7206 */
7207 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7208 {
7209 /* Read the IO bitmap A. */
7210 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7211 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7212 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7213 if (RT_SUCCESS(rc))
7214 { /* likely */ }
7215 else
7216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
7217
7218 /* Read the IO bitmap B. */
7219 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7220 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7221 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7222 if (RT_SUCCESS(rc))
7223 { /* likely */ }
7224 else
7225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
7226 }
7227
7228 /*
7229 * TPR shadow and Virtual-APIC page.
7230 */
7231 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7232 {
7233 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7234 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7235 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7236 {
7237 /* Read the VTPR from the virtual-APIC page. */
7238 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7239 uint8_t u8VTpr;
7240 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7241 if (RT_SUCCESS(rc))
7242 { /* likely */ }
7243 else
7244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
7245
7246 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7247 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7248 { /* likely */ }
7249 else
7250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7251 }
7252 }
7253
7254 /*
7255 * VMCS link pointer.
7256 */
7257 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7258 {
7259 /* Read the VMCS-link pointer from guest memory. */
7260 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7261 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7262 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7263 if (RT_SUCCESS(rc))
7264 { /* likely */ }
7265 else
7266 {
7267 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7268 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
7269 }
7270
7271 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7272 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7273 { /* likely */ }
7274 else
7275 {
7276 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7277 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7278 }
7279
7280 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
7281 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7282 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7283 { /* likely */ }
7284 else
7285 {
7286 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7288 }
7289
7290 /* Update our cache of the guest physical address of the shadow VMCS. */
7291 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7292 }
7293
7294 /*
7295 * MSR bitmap.
7296 */
7297 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7298 {
7299 /* Read the MSR bitmap. */
7300 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7301 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7302 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7303 if (RT_SUCCESS(rc))
7304 { /* likely */ }
7305 else
7306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
7307 }
7308
7309 NOREF(pszFailure);
7310 NOREF(pszInstr);
7311 return VINF_SUCCESS;
7312}
7313
7314
7315/**
7316 * Loads the guest-state as part of VM-entry.
7317 *
7318 * @returns VBox status code.
7319 * @param pVCpu The cross context virtual CPU structure.
7320 * @param pszInstr The VMX instruction name (for logging purposes).
7321 *
7322 * @remarks This must be done after all the necessary steps prior to loading of
7323 * guest-state (e.g. checking various VMCS state).
7324 */
7325static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7326{
7327 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
7328 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7329
7330 /* Load guest segment registers. */
7331 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7332
7333 /*
7334 * Load guest RIP, RSP and RFLAGS.
7335 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7336 */
7337 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7338 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7339 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7340 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7341
7342 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7343 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7344 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7345
7346 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7347 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7348 if (rc == VINF_SUCCESS)
7349 { /* likely */ }
7350 else
7351 return rc;
7352
7353 /* Load VMX related structures and state referenced by the VMCS. */
7354 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7355 if (rc == VINF_SUCCESS)
7356 { /* likely */ }
7357 else
7358 return rc;
7359
7360 NOREF(pszInstr);
7361 return VINF_SUCCESS;
7362}
7363
7364
7365/**
7366 * Returns whether there are is a pending debug exception on VM-entry.
7367 *
7368 * @param pVCpu The cross context virtual CPU structure.
7369 * @param pszInstr The VMX instruction name (for logging purposes).
7370 */
7371static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7372{
7373 /*
7374 * Pending debug exceptions.
7375 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7376 */
7377 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7378 Assert(pVmcs);
7379
7380 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7381 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7382 if (fPendingDbgXcpt)
7383 {
7384 uint8_t uEntryIntInfoType;
7385 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7386 if (fEntryVectoring)
7387 {
7388 switch (uEntryIntInfoType)
7389 {
7390 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7391 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7392 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7393 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7394 fPendingDbgXcpt = false;
7395 break;
7396
7397 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7398 {
7399 /*
7400 * Whether the pending debug exception for software exceptions other than
7401 * #BP and #OF is delivered after injecting the exception or is discard
7402 * is CPU implementation specific. We will discard them (easier).
7403 */
7404 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7405 if ( uVector != X86_XCPT_BP
7406 && uVector != X86_XCPT_OF)
7407 fPendingDbgXcpt = false;
7408 RT_FALL_THRU();
7409 }
7410 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7411 {
7412 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7413 fPendingDbgXcpt = false;
7414 break;
7415 }
7416 }
7417 }
7418 else
7419 {
7420 /*
7421 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7422 * pending debug exception is held pending or is discarded is CPU implementation
7423 * specific. We will discard them (easier).
7424 */
7425 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7426 fPendingDbgXcpt = false;
7427
7428 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7429 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7430 fPendingDbgXcpt = false;
7431 }
7432 }
7433
7434 NOREF(pszInstr);
7435 return fPendingDbgXcpt;
7436}
7437
7438
7439/**
7440 * Set up the monitor-trap flag (MTF).
7441 *
7442 * @param pVCpu The cross context virtual CPU structure.
7443 * @param pszInstr The VMX instruction name (for logging purposes).
7444 */
7445static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7446{
7447 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7448 Assert(pVmcs);
7449 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7450 {
7451 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7452 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7453 }
7454 else
7455 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7456 NOREF(pszInstr);
7457}
7458
7459
7460/**
7461 * Sets up NMI-window exiting.
7462 *
7463 * @param pVCpu The cross context virtual CPU structure.
7464 * @param pszInstr The VMX instruction name (for logging purposes).
7465 */
7466static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7467{
7468 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7469 Assert(pVmcs);
7470 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7471 {
7472 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7473 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7474 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7475 }
7476 else
7477 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7478 NOREF(pszInstr);
7479}
7480
7481
7482/**
7483 * Sets up interrupt-window exiting.
7484 *
7485 * @param pVCpu The cross context virtual CPU structure.
7486 * @param pszInstr The VMX instruction name (for logging purposes).
7487 */
7488static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7489{
7490 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7491 Assert(pVmcs);
7492 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7493 {
7494 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7495 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7496 }
7497 else
7498 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7499 NOREF(pszInstr);
7500}
7501
7502
7503/**
7504 * Set up the VMX-preemption timer.
7505 *
7506 * @param pVCpu The cross context virtual CPU structure.
7507 * @param pszInstr The VMX instruction name (for logging purposes).
7508 */
7509static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7510{
7511 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7512 Assert(pVmcs);
7513 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7514 {
7515 /*
7516 * If the timer is 0, we must cause a VM-exit before executing the first
7517 * nested-guest instruction. So we can flag as though the timer has already
7518 * expired and we will check and cause a VM-exit at the right priority elsewhere
7519 * in the code.
7520 */
7521 uint64_t uEntryTick;
7522 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7523 if (uPreemptTimer)
7524 {
7525 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7526 AssertRC(rc);
7527 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7528 }
7529 else
7530 {
7531 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7532 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7533 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7534 }
7535
7536 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7537 }
7538 else
7539 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7540
7541 NOREF(pszInstr);
7542}
7543
7544
7545/**
7546 * Injects an event using TRPM given a VM-entry interruption info and related
7547 * fields.
7548 *
7549 * @param pVCpu The cross context virtual CPU structure.
7550 * @param pszInstr The VMX instruction name (for logging purposes).
7551 * @param uEntryIntInfo The VM-entry interruption info.
7552 * @param uErrCode The error code associated with the event if any.
7553 * @param cbInstr The VM-entry instruction length (for software
7554 * interrupts and software exceptions). Pass 0
7555 * otherwise.
7556 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7557 */
7558static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7559 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7560{
7561 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7562
7563 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7564 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7565 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7566
7567 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7568
7569 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7570 AssertRC(rc);
7571 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7572
7573 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7574 {
7575 TRPMSetErrorCode(pVCpu, uErrCode);
7576 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7577 }
7578
7579 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7580 {
7581 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7582 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7583 }
7584 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7585 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7586 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7587 {
7588 TRPMSetInstrLength(pVCpu, cbInstr);
7589 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7590 }
7591
7592 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7593 {
7594 TRPMSetTrapDueToIcebp(pVCpu);
7595 Log(("%s: Injecting: icebp\n", pszInstr));
7596 }
7597
7598 NOREF(pszInstr);
7599}
7600
7601
7602/**
7603 * Performs event injection (if any) as part of VM-entry.
7604 *
7605 * @param pVCpu The cross context virtual CPU structure.
7606 * @param pszInstr The VMX instruction name (for logging purposes).
7607 */
7608static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7609{
7610 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7611
7612 /*
7613 * Inject events.
7614 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7615 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7616 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7617 * the actually delivery of this event.
7618 *
7619 * See Intel spec. 26.5 "Event Injection".
7620 */
7621 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7622 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7623
7624 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7625 if (fEntryIntInfoValid)
7626 {
7627 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7628 {
7629 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7630 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7631 }
7632 else
7633 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7634 pVCpu->cpum.GstCtx.cr2);
7635
7636 /*
7637 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7638 *
7639 * However, we do it here on VM-entry as well because while it isn't visible to guest
7640 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7641 * execution using hardware-assisted VMX, it will not try to inject the event again.
7642 *
7643 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7644 */
7645 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7646 }
7647 else
7648 {
7649 /*
7650 * Inject any pending guest debug exception.
7651 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7652 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7653 */
7654 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7655 if (fPendingDbgXcpt)
7656 {
7657 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7658 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7659 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7660 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7661 0 /* GCPtrFaultAddress */);
7662 }
7663 }
7664
7665 NOREF(pszInstr);
7666}
7667
7668
7669/**
7670 * Initializes all read-only VMCS fields as part of VM-entry.
7671 *
7672 * @param pVCpu The cross context virtual CPU structure.
7673 */
7674static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7675{
7676 /*
7677 * Any VMCS field which we do not establish on every VM-exit but may potentially
7678 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7679 * specified to be undefined, needs to be initialized here.
7680 *
7681 * Thus, it is especially important to clear the Exit qualification field
7682 * since it must be zero for VM-exits where it is not used. Similarly, the
7683 * VM-exit interruption information field's valid bit needs to be cleared for
7684 * the same reasons.
7685 */
7686 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7687 Assert(pVmcs);
7688
7689 /* 16-bit (none currently). */
7690 /* 32-bit. */
7691 pVmcs->u32RoVmInstrError = 0;
7692 pVmcs->u32RoExitReason = 0;
7693 pVmcs->u32RoExitIntInfo = 0;
7694 pVmcs->u32RoExitIntErrCode = 0;
7695 pVmcs->u32RoIdtVectoringInfo = 0;
7696 pVmcs->u32RoIdtVectoringErrCode = 0;
7697 pVmcs->u32RoExitInstrLen = 0;
7698 pVmcs->u32RoExitInstrInfo = 0;
7699
7700 /* 64-bit. */
7701 pVmcs->u64RoGuestPhysAddr.u = 0;
7702
7703 /* Natural-width. */
7704 pVmcs->u64RoExitQual.u = 0;
7705 pVmcs->u64RoIoRcx.u = 0;
7706 pVmcs->u64RoIoRsi.u = 0;
7707 pVmcs->u64RoIoRdi.u = 0;
7708 pVmcs->u64RoIoRip.u = 0;
7709 pVmcs->u64RoGuestLinearAddr.u = 0;
7710}
7711
7712
7713/**
7714 * VMLAUNCH/VMRESUME instruction execution worker.
7715 *
7716 * @returns Strict VBox status code.
7717 * @param pVCpu The cross context virtual CPU structure.
7718 * @param cbInstr The instruction length in bytes.
7719 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7720 * VMXINSTRID_VMRESUME).
7721 *
7722 * @remarks Common VMX instruction checks are already expected to by the caller,
7723 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7724 */
7725static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7726{
7727# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7728 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7729 return VINF_EM_RAW_EMULATE_INSTR;
7730# else
7731 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7732 || uInstrId == VMXINSTRID_VMRESUME);
7733 const char * const pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7734
7735 /* Nested-guest intercept. */
7736 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7737 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7738
7739 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7740
7741 /*
7742 * Basic VM-entry checks.
7743 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7744 * The checks following that do not have to follow a specific order.
7745 *
7746 * See Intel spec. 26.1 "Basic VM-entry Checks".
7747 */
7748
7749 /* CPL. */
7750 if (pVCpu->iem.s.uCpl == 0)
7751 { /* likely */ }
7752 else
7753 {
7754 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7755 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7756 return iemRaiseGeneralProtectionFault0(pVCpu);
7757 }
7758
7759 /* Current VMCS valid. */
7760 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7761 { /* likely */ }
7762 else
7763 {
7764 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7765 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7766 iemVmxVmFailInvalid(pVCpu);
7767 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7768 }
7769
7770 /* Current VMCS is not a shadow VMCS. */
7771 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7772 { /* likely */ }
7773 else
7774 {
7775 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7776 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7777 iemVmxVmFailInvalid(pVCpu);
7778 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7779 }
7780
7781 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7782 * use block-by-STI here which is not quite correct. */
7783 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
7784 { /* likely */ }
7785 else
7786 {
7787 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7788 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7789 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7790 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7791 }
7792
7793 if (uInstrId == VMXINSTRID_VMLAUNCH)
7794 {
7795 /* VMLAUNCH with non-clear VMCS. */
7796 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7797 { /* likely */ }
7798 else
7799 {
7800 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7801 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7802 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7803 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7804 }
7805 }
7806 else
7807 {
7808 /* VMRESUME with non-launched VMCS. */
7809 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7810 { /* likely */ }
7811 else
7812 {
7813 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7814 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7815 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7816 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7817 }
7818 }
7819
7820 /*
7821 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7822 * while entering VMX non-root mode. We do some of this while checking VM-execution
7823 * controls. The nested hypervisor should not make assumptions and cannot expect
7824 * predictable behavior if changes to these structures are made in guest memory while
7825 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7826 * modify them anyway as we cache them in host memory.
7827 *
7828 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7829 */
7830 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7831
7832 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7833 if (RT_SUCCESS(rc))
7834 {
7835 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7836 if (RT_SUCCESS(rc))
7837 {
7838 /*
7839 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7840 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7841 * ones that may occur during VM-entry below).
7842 */
7843 iemVmxVmentryInitReadOnlyFields(pVCpu);
7844
7845 /*
7846 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7847 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7848 * VM-exit when required.
7849 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7850 */
7851 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7852
7853 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7854 Assert(pVmcs);
7855
7856 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7857 if (RT_SUCCESS(rc))
7858 {
7859 /*
7860 * We've now entered nested-guest execution.
7861 *
7862 * It is important do this prior to loading the guest state because
7863 * as part of loading the guest state, PGM (and perhaps other components
7864 * in the future) relies on detecting whether VMX non-root mode has been
7865 * entered.
7866 */
7867 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7868
7869 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7870 if (RT_SUCCESS(rc))
7871 {
7872 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7873 if (RT_SUCCESS(rc))
7874 {
7875 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7876
7877 /* VMLAUNCH instruction must update the VMCS launch state. */
7878 if (uInstrId == VMXINSTRID_VMLAUNCH)
7879 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7880
7881 /* Perform the VMX transition (PGM updates). */
7882 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7883 if (rcStrict == VINF_SUCCESS)
7884 { /* likely */ }
7885 else if (RT_SUCCESS(rcStrict))
7886 {
7887 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7888 VBOXSTRICTRC_VAL(rcStrict)));
7889 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7890 }
7891 else
7892 {
7893 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7894 return rcStrict;
7895 }
7896
7897 /* Paranoia. */
7898 Assert(rcStrict == VINF_SUCCESS);
7899
7900 /*
7901 * The priority of potential VM-exits during VM-entry is important.
7902 * The priorities of VM-exits and events are listed from highest
7903 * to lowest as follows:
7904 *
7905 * 1. Event injection.
7906 * 2. Trap on task-switch (T flag set in TSS).
7907 * 3. TPR below threshold / APIC-write.
7908 * 4. SMI, INIT.
7909 * 5. MTF exit.
7910 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7911 * 7. VMX-preemption timer.
7912 * 9. NMI-window exit.
7913 * 10. NMI injection.
7914 * 11. Interrupt-window exit.
7915 * 12. Virtual-interrupt injection.
7916 * 13. Interrupt injection.
7917 * 14. Process next instruction (fetch, decode, execute).
7918 */
7919
7920 /* Setup VMX-preemption timer. */
7921 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7922
7923 /* Setup monitor-trap flag. */
7924 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7925
7926 /* Setup NMI-window exiting. */
7927 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7928
7929 /* Setup interrupt-window exiting. */
7930 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7931
7932 /*
7933 * Inject any event that the nested hypervisor wants to inject.
7934 * Note! We cannot immediately perform the event injection here as we may have
7935 * pending PGM operations to perform due to switching page tables and/or
7936 * mode.
7937 */
7938 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7939
7940# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7941 /* Reschedule to IEM-only execution of the nested-guest. */
7942 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7943 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7944 if (rcSched != VINF_SUCCESS)
7945 iemSetPassUpStatus(pVCpu, rcSched);
7946# endif
7947
7948 /* Finally, done. */
7949 Log2(("vmentry: %s: cs:rip=%04x:%08RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
7950 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7951 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7952 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
7953 return VINF_SUCCESS;
7954 }
7955 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7956 }
7957 }
7958 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7959 }
7960
7961 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7962 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7963 }
7964
7965 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7966 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7967# endif
7968}
7969
7970
7971/**
7972 * Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
7973 *
7974 * @returns Strict VBox status code.
7975 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7976 * @param cbInstr The instruction length in bytes.
7977 * @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
7978 * VMXINSTRID_VMRESUME).
7979 * @thread EMT(pVCpu)
7980 */
7981VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7982{
7983 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
7984 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
7985
7986 iemInitExec(pVCpu, false /*fBypassHandlers*/);
7987 VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
7988 Assert(!pVCpu->iem.s.cActiveMappings);
7989 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
7990}
7991
7992
7993/**
7994 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7995 * (causes a VM-exit) or not.
7996 *
7997 * @returns @c true if the instruction is intercepted, @c false otherwise.
7998 * @param pVCpu The cross context virtual CPU structure.
7999 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
8000 * VMX_EXIT_WRMSR).
8001 * @param idMsr The MSR.
8002 */
8003bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
8004{
8005 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
8006 Assert( uExitReason == VMX_EXIT_RDMSR
8007 || uExitReason == VMX_EXIT_WRMSR);
8008
8009 /* Consult the MSR bitmap if the feature is supported. */
8010 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
8011 Assert(pVmcs);
8012 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
8013 {
8014 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
8015 if (uExitReason == VMX_EXIT_RDMSR)
8016 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
8017 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
8018 }
8019
8020 /* Without MSR bitmaps, all MSR accesses are intercepted. */
8021 return true;
8022}
8023
8024
8025/**
8026 * VMREAD instruction execution worker that does not perform any validation checks.
8027 *
8028 * Callers are expected to have performed the necessary checks and to ensure the
8029 * VMREAD will succeed.
8030 *
8031 * @param pVmcs Pointer to the virtual VMCS.
8032 * @param pu64Dst Where to write the VMCS value.
8033 * @param u64VmcsField The VMCS field.
8034 *
8035 * @remarks May be called with interrupts disabled.
8036 */
8037static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
8038{
8039 VMXVMCSFIELD VmcsField;
8040 VmcsField.u = u64VmcsField;
8041 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8042 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8043 uint8_t const uWidthType = (uWidth << 2) | uType;
8044 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8045 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8046 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8047 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8048 uWidth, uType, uIndex, uIndex));
8049 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8050
8051 /*
8052 * Read the VMCS component based on the field's effective width.
8053 *
8054 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8055 * indicates high bits (little endian).
8056 *
8057 * Note! The caller is responsible to trim the result and update registers
8058 * or memory locations are required. Here we just zero-extend to the largest
8059 * type (i.e. 64-bits).
8060 */
8061 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
8062 uint8_t const *pbField = pbVmcs + offField;
8063 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8064 switch (uEffWidth)
8065 {
8066 case VMX_VMCSFIELD_WIDTH_64BIT:
8067 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
8068 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
8069 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
8070 }
8071}
8072
8073
8074/**
8075 * Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8076 *
8077 * It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8078 * are performed. Bounds checks are strict builds only.
8079 *
8080 * @param pVmcs Pointer to the virtual VMCS.
8081 * @param u64VmcsField The VMCS field.
8082 * @param pu64Dst Where to store the VMCS value.
8083 *
8084 * @remarks May be called with interrupts disabled.
8085 * @todo This should probably be moved to CPUM someday.
8086 */
8087VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8088{
8089 AssertPtr(pVmcs);
8090 AssertPtr(pu64Dst);
8091 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8092}
8093
8094
8095/**
8096 * VMREAD common (memory/register) instruction execution worker.
8097 *
8098 * @returns Strict VBox status code.
8099 * @param pVCpu The cross context virtual CPU structure.
8100 * @param cbInstr The instruction length in bytes.
8101 * @param pu64Dst Where to write the VMCS value (only updated when
8102 * VINF_SUCCESS is returned).
8103 * @param u64VmcsField The VMCS field.
8104 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8105 * NULL.
8106 */
8107static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8108 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8109{
8110 /* Nested-guest intercept. */
8111 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8112 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8113 {
8114 if (pExitInfo)
8115 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8116 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8117 }
8118
8119 /* CPL. */
8120 if (pVCpu->iem.s.uCpl == 0)
8121 { /* likely */ }
8122 else
8123 {
8124 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8125 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8126 return iemRaiseGeneralProtectionFault0(pVCpu);
8127 }
8128
8129 pVCpu->iem.s.cPotentialExits++;
8130
8131 /* VMCS pointer in root mode. */
8132 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8133 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8134 { /* likely */ }
8135 else
8136 {
8137 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8138 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8139 iemVmxVmFailInvalid(pVCpu);
8140 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8141 }
8142
8143 /* VMCS-link pointer in non-root mode. */
8144 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8145 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8146 { /* likely */ }
8147 else
8148 {
8149 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8150 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8151 iemVmxVmFailInvalid(pVCpu);
8152 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8153 }
8154
8155 /* Supported VMCS field. */
8156 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8157 { /* likely */ }
8158 else
8159 {
8160 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8161 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8162 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8163 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8164 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8165 }
8166
8167 /*
8168 * Reading from the current or shadow VMCS.
8169 */
8170 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8171 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8172 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8173 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8174 Log4(("vmread %#RX64 => %#RX64\n", u64VmcsField, *pu64Dst));
8175 return VINF_SUCCESS;
8176}
8177
8178
8179/**
8180 * VMREAD (64-bit register) instruction execution worker.
8181 *
8182 * @returns Strict VBox status code.
8183 * @param pVCpu The cross context virtual CPU structure.
8184 * @param cbInstr The instruction length in bytes.
8185 * @param pu64Dst Where to store the VMCS field's value.
8186 * @param u64VmcsField The VMCS field.
8187 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8188 * NULL.
8189 */
8190static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8191 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8192{
8193 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8194 if (rcStrict == VINF_SUCCESS)
8195 {
8196 iemVmxVmSucceed(pVCpu);
8197 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8198 }
8199
8200 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8201 return rcStrict;
8202}
8203
8204
8205/**
8206 * VMREAD (32-bit register) instruction execution worker.
8207 *
8208 * @returns Strict VBox status code.
8209 * @param pVCpu The cross context virtual CPU structure.
8210 * @param cbInstr The instruction length in bytes.
8211 * @param pu32Dst Where to store the VMCS field's value.
8212 * @param u32VmcsField The VMCS field.
8213 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8214 * NULL.
8215 */
8216static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8217 uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8218{
8219 uint64_t u64Dst;
8220 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8221 if (rcStrict == VINF_SUCCESS)
8222 {
8223 *pu32Dst = u64Dst;
8224 iemVmxVmSucceed(pVCpu);
8225 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8226 }
8227
8228 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8229 return rcStrict;
8230}
8231
8232
8233/**
8234 * VMREAD (memory) instruction execution worker.
8235 *
8236 * @returns Strict VBox status code.
8237 * @param pVCpu The cross context virtual CPU structure.
8238 * @param cbInstr The instruction length in bytes.
8239 * @param iEffSeg The effective segment register to use with @a u64Val.
8240 * Pass UINT8_MAX if it is a register access.
8241 * @param GCPtrDst The guest linear address to store the VMCS field's
8242 * value.
8243 * @param u64VmcsField The VMCS field.
8244 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8245 * NULL.
8246 */
8247static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8248 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8249{
8250 uint64_t u64Dst;
8251 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8252 if (rcStrict == VINF_SUCCESS)
8253 {
8254 /*
8255 * Write the VMCS field's value to the location specified in guest-memory.
8256 */
8257 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8258 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8259 else
8260 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8261 if (rcStrict == VINF_SUCCESS)
8262 {
8263 iemVmxVmSucceed(pVCpu);
8264 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8265 }
8266
8267 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8268 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8269 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8270 return rcStrict;
8271 }
8272
8273 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8274 return rcStrict;
8275}
8276
8277
8278/**
8279 * Interface for HM and EM to emulate the VMREAD instruction.
8280 *
8281 * @returns Strict VBox status code.
8282 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8283 * @param pExitInfo Pointer to the VM-exit information.
8284 * @thread EMT(pVCpu)
8285 */
8286VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8287{
8288 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8289 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8290 Assert(pExitInfo);
8291
8292 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8293
8294 VBOXSTRICTRC rcStrict;
8295 uint8_t const cbInstr = pExitInfo->cbInstr;
8296 bool const fIs64BitMode = RT_BOOL(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
8297 uint64_t const u64FieldEnc = fIs64BitMode
8298 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8299 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8300 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8301 {
8302 if (fIs64BitMode)
8303 {
8304 uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8305 rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8306 }
8307 else
8308 {
8309 uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8310 rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8311 }
8312 }
8313 else
8314 {
8315 RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8316 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8317 rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8318 }
8319 Assert(!pVCpu->iem.s.cActiveMappings);
8320 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8321}
8322
8323
8324/**
8325 * VMWRITE instruction execution worker that does not perform any validation
8326 * checks.
8327 *
8328 * Callers are expected to have performed the necessary checks and to ensure the
8329 * VMWRITE will succeed.
8330 *
8331 * @param pVmcs Pointer to the virtual VMCS.
8332 * @param u64Val The value to write.
8333 * @param u64VmcsField The VMCS field.
8334 *
8335 * @remarks May be called with interrupts disabled.
8336 */
8337static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8338{
8339 VMXVMCSFIELD VmcsField;
8340 VmcsField.u = u64VmcsField;
8341 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8342 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8343 uint8_t const uWidthType = (uWidth << 2) | uType;
8344 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8345 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8346 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8347 Assert(offField < VMX_V_VMCS_SIZE);
8348 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8349
8350 /*
8351 * Write the VMCS component based on the field's effective width.
8352 *
8353 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8354 * indicates high bits (little endian).
8355 */
8356 uint8_t *pbVmcs = (uint8_t *)pVmcs;
8357 uint8_t *pbField = pbVmcs + offField;
8358 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8359 switch (uEffWidth)
8360 {
8361 case VMX_VMCSFIELD_WIDTH_64BIT:
8362 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8363 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8364 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8365 }
8366}
8367
8368
8369/**
8370 * Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8371 *
8372 * It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8373 * are performed. Bounds checks are strict builds only.
8374 *
8375 * @param pVmcs Pointer to the virtual VMCS.
8376 * @param u64VmcsField The VMCS field.
8377 * @param u64Val The value to write.
8378 *
8379 * @remarks May be called with interrupts disabled.
8380 * @todo This should probably be moved to CPUM someday.
8381 */
8382VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8383{
8384 AssertPtr(pVmcs);
8385 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8386}
8387
8388
8389/**
8390 * VMWRITE instruction execution worker.
8391 *
8392 * @returns Strict VBox status code.
8393 * @param pVCpu The cross context virtual CPU structure.
8394 * @param cbInstr The instruction length in bytes.
8395 * @param iEffSeg The effective segment register to use with @a u64Val.
8396 * Pass UINT8_MAX if it is a register access.
8397 * @param u64Val The value to write (or guest linear address to the
8398 * value), @a iEffSeg will indicate if it's a memory
8399 * operand.
8400 * @param u64VmcsField The VMCS field.
8401 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8402 * NULL.
8403 */
8404static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8405 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8406{
8407 /* Nested-guest intercept. */
8408 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8409 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8410 {
8411 if (pExitInfo)
8412 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8413 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8414 }
8415
8416 /* CPL. */
8417 if (pVCpu->iem.s.uCpl == 0)
8418 { /* likely */ }
8419 else
8420 {
8421 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8422 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8423 return iemRaiseGeneralProtectionFault0(pVCpu);
8424 }
8425
8426 pVCpu->iem.s.cPotentialExits++;
8427
8428 /* VMCS pointer in root mode. */
8429 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8430 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8431 { /* likely */ }
8432 else
8433 {
8434 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8435 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8436 iemVmxVmFailInvalid(pVCpu);
8437 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8438 }
8439
8440 /* VMCS-link pointer in non-root mode. */
8441 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8442 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8443 { /* likely */ }
8444 else
8445 {
8446 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8447 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8448 iemVmxVmFailInvalid(pVCpu);
8449 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8450 }
8451
8452 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8453 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8454 if (!fIsRegOperand)
8455 {
8456 /* Read the value from the specified guest memory location. */
8457 VBOXSTRICTRC rcStrict;
8458 RTGCPTR const GCPtrVal = u64Val;
8459 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8460 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8461 else
8462 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8463 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8464 {
8465 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8466 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8467 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8468 return rcStrict;
8469 }
8470 }
8471 else
8472 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8473
8474 /* Supported VMCS field. */
8475 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8476 { /* likely */ }
8477 else
8478 {
8479 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8480 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8481 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8482 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8483 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8484 }
8485
8486 /* Read-only VMCS field. */
8487 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8488 if ( !fIsFieldReadOnly
8489 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8490 { /* likely */ }
8491 else
8492 {
8493 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8494 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8495 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8496 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8497 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8498 }
8499
8500 /*
8501 * Write to the current or shadow VMCS.
8502 */
8503 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8504 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8505 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8506 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8507 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8508 Log4(("vmwrite %#RX64 <= %#RX64\n", u64VmcsField, u64Val));
8509
8510 if ( !fInVmxNonRootMode
8511 && VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8512 {
8513 /* Notify HM that the VMCS content might have changed. */
8514 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8515 }
8516
8517 iemVmxVmSucceed(pVCpu);
8518 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8519}
8520
8521
8522/**
8523 * Interface for HM and EM to emulate the VMWRITE instruction.
8524 *
8525 * @returns Strict VBox status code.
8526 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8527 * @param pExitInfo Pointer to the VM-exit information.
8528 * @thread EMT(pVCpu)
8529 */
8530VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8531{
8532 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8533 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8534 Assert(pExitInfo);
8535
8536 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8537
8538 uint64_t u64Val;
8539 uint8_t iEffSeg;
8540 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8541 {
8542 u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8543 iEffSeg = UINT8_MAX;
8544 }
8545 else
8546 {
8547 u64Val = pExitInfo->GCPtrEffAddr;
8548 iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8549 }
8550 uint8_t const cbInstr = pExitInfo->cbInstr;
8551 uint64_t const u64FieldEnc = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
8552 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8553 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8554 VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8555 Assert(!pVCpu->iem.s.cActiveMappings);
8556 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8557}
8558
8559
8560/**
8561 * VMCLEAR instruction execution worker.
8562 *
8563 * @returns Strict VBox status code.
8564 * @param pVCpu The cross context virtual CPU structure.
8565 * @param cbInstr The instruction length in bytes.
8566 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8567 * @param GCPtrVmcs The linear address of the VMCS pointer.
8568 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8569 *
8570 * @remarks Common VMX instruction checks are already expected to by the caller,
8571 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8572 */
8573static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8574 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8575{
8576 /* Nested-guest intercept. */
8577 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8578 {
8579 if (pExitInfo)
8580 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8581 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8582 }
8583
8584 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8585
8586 /* CPL. */
8587 if (pVCpu->iem.s.uCpl == 0)
8588 { /* likely */ }
8589 else
8590 {
8591 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8592 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8593 return iemRaiseGeneralProtectionFault0(pVCpu);
8594 }
8595
8596 /* Get the VMCS pointer from the location specified by the source memory operand. */
8597 RTGCPHYS GCPhysVmcs;
8598 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8599 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8600 { /* likely */ }
8601 else
8602 {
8603 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8604 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8605 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8606 return rcStrict;
8607 }
8608
8609 /* VMCS pointer alignment. */
8610 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8611 { /* likely */ }
8612 else
8613 {
8614 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8615 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8616 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8617 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8618 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8619 }
8620
8621 /* VMCS physical-address width limits. */
8622 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8623 { /* likely */ }
8624 else
8625 {
8626 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8627 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8628 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8629 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8630 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8631 }
8632
8633 /* VMCS is not the VMXON region. */
8634 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8635 { /* likely */ }
8636 else
8637 {
8638 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8639 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8640 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8641 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8642 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8643 }
8644
8645 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8646 restriction imposed by our implementation. */
8647 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8648 { /* likely */ }
8649 else
8650 {
8651 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8652 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8653 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8654 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8655 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8656 }
8657
8658 /*
8659 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8660 *
8661 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8662 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8663 * to 'clear'.
8664 */
8665 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8666 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8667 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8668 {
8669 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8670 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8671 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8672 }
8673 else
8674 {
8675 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8676 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8677 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8678 if (RT_FAILURE(rcStrict))
8679 return rcStrict;
8680 }
8681
8682 iemVmxVmSucceed(pVCpu);
8683 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8684}
8685
8686
8687/**
8688 * Interface for HM and EM to emulate the VMCLEAR instruction.
8689 *
8690 * @returns Strict VBox status code.
8691 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8692 * @param pExitInfo Pointer to the VM-exit information.
8693 * @thread EMT(pVCpu)
8694 */
8695VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8696{
8697 Assert(pExitInfo);
8698 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8699 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8700
8701 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8702
8703 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8704 uint8_t const cbInstr = pExitInfo->cbInstr;
8705 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8706 VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8707 Assert(!pVCpu->iem.s.cActiveMappings);
8708 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8709}
8710
8711
8712/**
8713 * VMPTRST instruction execution worker.
8714 *
8715 * @returns Strict VBox status code.
8716 * @param pVCpu The cross context virtual CPU structure.
8717 * @param cbInstr The instruction length in bytes.
8718 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8719 * @param GCPtrVmcs The linear address of where to store the current VMCS
8720 * pointer.
8721 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8722 *
8723 * @remarks Common VMX instruction checks are already expected to by the caller,
8724 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8725 */
8726static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8727 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8728{
8729 /* Nested-guest intercept. */
8730 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8731 {
8732 if (pExitInfo)
8733 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8734 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8735 }
8736
8737 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8738
8739 /* CPL. */
8740 if (pVCpu->iem.s.uCpl == 0)
8741 { /* likely */ }
8742 else
8743 {
8744 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8745 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8746 return iemRaiseGeneralProtectionFault0(pVCpu);
8747 }
8748
8749 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8750 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8751 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8752 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8753 {
8754 iemVmxVmSucceed(pVCpu);
8755 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8756 }
8757
8758 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8759 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8760 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8761 return rcStrict;
8762}
8763
8764
8765/**
8766 * Interface for HM and EM to emulate the VMPTRST instruction.
8767 *
8768 * @returns Strict VBox status code.
8769 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8770 * @param pExitInfo Pointer to the VM-exit information.
8771 * @thread EMT(pVCpu)
8772 */
8773VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8774{
8775 Assert(pExitInfo);
8776 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8777 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8778
8779 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8780
8781 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8782 uint8_t const cbInstr = pExitInfo->cbInstr;
8783 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8784 VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8785 Assert(!pVCpu->iem.s.cActiveMappings);
8786 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8787}
8788
8789
8790/**
8791 * VMPTRLD instruction execution worker.
8792 *
8793 * @returns Strict VBox status code.
8794 * @param pVCpu The cross context virtual CPU structure.
8795 * @param cbInstr The instruction length in bytes.
8796 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8797 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8798 *
8799 * @remarks Common VMX instruction checks are already expected to by the caller,
8800 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8801 */
8802static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8803 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8804{
8805 /* Nested-guest intercept. */
8806 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8807 {
8808 if (pExitInfo)
8809 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8810 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8811 }
8812
8813 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8814
8815 /* CPL. */
8816 if (pVCpu->iem.s.uCpl == 0)
8817 { /* likely */ }
8818 else
8819 {
8820 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8821 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8822 return iemRaiseGeneralProtectionFault0(pVCpu);
8823 }
8824
8825 /* Get the VMCS pointer from the location specified by the source memory operand. */
8826 RTGCPHYS GCPhysVmcs;
8827 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8828 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8829 { /* likely */ }
8830 else
8831 {
8832 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8833 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8834 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8835 return rcStrict;
8836 }
8837
8838 /* VMCS pointer alignment. */
8839 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8840 { /* likely */ }
8841 else
8842 {
8843 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8844 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8845 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8846 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8847 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8848 }
8849
8850 /* VMCS physical-address width limits. */
8851 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8852 { /* likely */ }
8853 else
8854 {
8855 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8856 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8857 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8858 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8859 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8860 }
8861
8862 /* VMCS is not the VMXON region. */
8863 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8864 { /* likely */ }
8865 else
8866 {
8867 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8868 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8869 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8870 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8871 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8872 }
8873
8874 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8875 restriction imposed by our implementation. */
8876 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8877 { /* likely */ }
8878 else
8879 {
8880 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8881 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8882 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8883 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8884 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8885 }
8886
8887 /* Read just the VMCS revision from the VMCS. */
8888 VMXVMCSREVID VmcsRevId;
8889 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8890 if (RT_SUCCESS(rc))
8891 { /* likely */ }
8892 else
8893 {
8894 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8895 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8896 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8897 return rc;
8898 }
8899
8900 /*
8901 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8902 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8903 */
8904 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8905 && ( !VmcsRevId.n.fIsShadowVmcs
8906 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8907 { /* likely */ }
8908 else
8909 {
8910 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8911 {
8912 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8913 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8914 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8915 }
8916 else
8917 {
8918 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8919 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8920 }
8921 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8922 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8923 }
8924
8925 /*
8926 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8927 * the cache of an existing, current VMCS back to guest memory before loading a new,
8928 * different current VMCS.
8929 */
8930 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8931 {
8932 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8933 {
8934 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8935 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8936 }
8937
8938 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8939 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8940 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8941 if (RT_SUCCESS(rc))
8942 {
8943 /* Notify HM that a new, current VMCS is loaded. */
8944 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8945 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8946 }
8947 else
8948 {
8949 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8950 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8951 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8952 return rc;
8953 }
8954 }
8955
8956 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8957 iemVmxVmSucceed(pVCpu);
8958 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8959}
8960
8961
8962/**
8963 * Interface for HM and EM to emulate the VMPTRLD instruction.
8964 *
8965 * @returns Strict VBox status code.
8966 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8967 * @param pExitInfo Pointer to the VM-exit information.
8968 * @thread EMT(pVCpu)
8969 */
8970VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8971{
8972 Assert(pExitInfo);
8973 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8974 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8975
8976 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8977
8978 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8979 uint8_t const cbInstr = pExitInfo->cbInstr;
8980 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8981 VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8982 Assert(!pVCpu->iem.s.cActiveMappings);
8983 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8984}
8985
8986
8987/**
8988 * INVVPID instruction execution worker.
8989 *
8990 * @returns Strict VBox status code.
8991 * @param pVCpu The cross context virtual CPU structure.
8992 * @param cbInstr The instruction length in bytes.
8993 * @param iEffSeg The segment of the invvpid descriptor.
8994 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8995 * @param u64InvvpidType The invalidation type.
8996 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8997 * NULL.
8998 *
8999 * @remarks Common VMX instruction checks are already expected to by the caller,
9000 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9001 */
9002VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
9003 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9004{
9005 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
9006 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
9007 return iemRaiseUndefinedOpcode(pVCpu);
9008
9009 /* Nested-guest intercept. */
9010 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9011 {
9012 if (pExitInfo)
9013 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9014 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
9015 }
9016
9017 /* CPL. */
9018 if (pVCpu->iem.s.uCpl != 0)
9019 {
9020 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
9021 return iemRaiseGeneralProtectionFault0(pVCpu);
9022 }
9023
9024 /*
9025 * Validate INVVPID invalidation type.
9026 *
9027 * The instruction specifies exactly ONE of the supported invalidation types.
9028 *
9029 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9030 * supported. In theory, it's possible for a CPU to not support flushing individual
9031 * addresses but all the other types or any other combination. We do not take any
9032 * shortcuts here by assuming the types we currently expose to the guest.
9033 */
9034 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9035 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9036 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9037 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9038 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9039 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9040
9041 bool afSupportedTypes[4];
9042 afSupportedTypes[0] = fTypeIndivAddr;
9043 afSupportedTypes[1] = fTypeSingleCtx;
9044 afSupportedTypes[2] = fTypeAllCtx;
9045 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9046
9047 if ( fInvvpidSupported
9048 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9049 && afSupportedTypes[u64InvvpidType & 3])
9050 { /* likely */ }
9051 else
9052 {
9053 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9054 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9055 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9056 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9057 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9058 }
9059
9060 /*
9061 * Fetch the invvpid descriptor from guest memory.
9062 */
9063 RTUINT128U uDesc;
9064 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9065 if (rcStrict == VINF_SUCCESS)
9066 {
9067 /*
9068 * Validate the descriptor.
9069 */
9070 if (uDesc.s.Lo <= 0xffff)
9071 { /* likely */ }
9072 else
9073 {
9074 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9075 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9076 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9077 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9078 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9079 }
9080
9081 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9082 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9083 uint16_t const uVpid = uDesc.Words.w0;
9084 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9085 switch (u64InvvpidType)
9086 {
9087 case VMXTLBFLUSHVPID_INDIV_ADDR:
9088 {
9089 if (uVpid != 0)
9090 {
9091 if (IEM_IS_CANONICAL(GCPtrInvAddr))
9092 {
9093 /* Invalidate mappings for the linear address tagged with VPID. */
9094 /** @todo PGM support for VPID? Currently just flush everything. */
9095 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9096 iemVmxVmSucceed(pVCpu);
9097 }
9098 else
9099 {
9100 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9101 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9102 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9103 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9104 }
9105 }
9106 else
9107 {
9108 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9109 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9110 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9111 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9112 }
9113 break;
9114 }
9115
9116 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9117 {
9118 if (uVpid != 0)
9119 {
9120 /* Invalidate all mappings with VPID. */
9121 /** @todo PGM support for VPID? Currently just flush everything. */
9122 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9123 iemVmxVmSucceed(pVCpu);
9124 }
9125 else
9126 {
9127 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9128 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9129 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9130 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9131 }
9132 break;
9133 }
9134
9135 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9136 {
9137 /* Invalidate all mappings with non-zero VPIDs. */
9138 /** @todo PGM support for VPID? Currently just flush everything. */
9139 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9140 iemVmxVmSucceed(pVCpu);
9141 break;
9142 }
9143
9144 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9145 {
9146 if (uVpid != 0)
9147 {
9148 /* Invalidate all mappings with VPID except global translations. */
9149 /** @todo PGM support for VPID? Currently just flush everything. */
9150 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9151 iemVmxVmSucceed(pVCpu);
9152 }
9153 else
9154 {
9155 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9156 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9157 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9158 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9159 }
9160 break;
9161 }
9162 IEM_NOT_REACHED_DEFAULT_CASE_RET();
9163 }
9164 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9165 }
9166 return rcStrict;
9167}
9168
9169
9170/**
9171 * Interface for HM and EM to emulate the INVVPID instruction.
9172 *
9173 * @returns Strict VBox status code.
9174 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9175 * @param pExitInfo Pointer to the VM-exit information.
9176 * @thread EMT(pVCpu)
9177 */
9178VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9179{
9180 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9181 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9182 Assert(pExitInfo);
9183
9184 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9185
9186 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9187 uint8_t const cbInstr = pExitInfo->cbInstr;
9188 RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9189 uint64_t const u64InvvpidType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9190 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9191 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9192 VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9193 Assert(!pVCpu->iem.s.cActiveMappings);
9194 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9195}
9196
9197#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9198
9199/**
9200 * INVEPT instruction execution worker.
9201 *
9202 * @returns Strict VBox status code.
9203 * @param pVCpu The cross context virtual CPU structure.
9204 * @param cbInstr The instruction length in bytes.
9205 * @param iEffSeg The segment of the invept descriptor.
9206 * @param GCPtrInveptDesc The address of invept descriptor.
9207 * @param u64InveptType The invalidation type.
9208 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9209 * NULL.
9210 *
9211 * @remarks Common VMX instruction checks are already expected to by the caller,
9212 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9213 */
9214static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9215 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9216{
9217 /* Check if EPT is supported, otherwise raise #UD. */
9218 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9219 return iemRaiseUndefinedOpcode(pVCpu);
9220
9221 /* Nested-guest intercept. */
9222 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9223 {
9224 if (pExitInfo)
9225 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9226 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9227 }
9228
9229 /* CPL. */
9230 if (pVCpu->iem.s.uCpl != 0)
9231 {
9232 Log(("invept: CPL != 0 -> #GP(0)\n"));
9233 return iemRaiseGeneralProtectionFault0(pVCpu);
9234 }
9235
9236 /*
9237 * Validate INVEPT invalidation type.
9238 *
9239 * The instruction specifies exactly ONE of the supported invalidation types.
9240 *
9241 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9242 * supported. In theory, it's possible for a CPU to not support flushing individual
9243 * addresses but all the other types or any other combination. We do not take any
9244 * shortcuts here by assuming the types we currently expose to the guest.
9245 */
9246 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9247 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9248 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9249 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9250
9251 bool afSupportedTypes[4];
9252 afSupportedTypes[0] = false;
9253 afSupportedTypes[1] = fTypeSingleCtx;
9254 afSupportedTypes[2] = fTypeAllCtx;
9255 afSupportedTypes[3] = false;
9256
9257 if ( fInveptSupported
9258 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9259 && afSupportedTypes[u64InveptType & 3])
9260 { /* likely */ }
9261 else
9262 {
9263 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9264 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9265 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9266 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9267 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9268 }
9269
9270 /*
9271 * Fetch the invept descriptor from guest memory.
9272 */
9273 RTUINT128U uDesc;
9274 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9275 if (rcStrict == VINF_SUCCESS)
9276 {
9277 /*
9278 * Validate the descriptor.
9279 *
9280 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9281 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9282 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9283 * better to be strict in our emulation until proven otherwise.
9284 */
9285 if (uDesc.s.Hi)
9286 {
9287 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9288 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9289 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9290 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9291 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9292 }
9293
9294 /*
9295 * Flush TLB mappings based on the EPT type.
9296 */
9297 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9298 {
9299 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9300 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9301 if (RT_SUCCESS(rc))
9302 { /* likely */ }
9303 else
9304 {
9305 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9306 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9307 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9308 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9309 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9310 }
9311 }
9312
9313 /** @todo PGM support for EPT tags? Currently just flush everything. */
9314 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9315 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9316 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9317
9318 iemVmxVmSucceed(pVCpu);
9319 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9320 }
9321
9322 return rcStrict;
9323}
9324
9325
9326/**
9327 * Interface for HM and EM to emulate the INVEPT instruction.
9328 *
9329 * @returns Strict VBox status code.
9330 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9331 * @param pExitInfo Pointer to the VM-exit information.
9332 * @thread EMT(pVCpu)
9333 */
9334VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9335{
9336 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9337 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9338 Assert(pExitInfo);
9339
9340 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9341
9342 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9343 uint8_t const cbInstr = pExitInfo->cbInstr;
9344 RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9345 uint64_t const u64InveptType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9346 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9347 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9348 VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9349 Assert(!pVCpu->iem.s.cActiveMappings);
9350 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9351}
9352
9353#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9354
9355/**
9356 * VMXON instruction execution worker.
9357 *
9358 * @returns Strict VBox status code.
9359 * @param pVCpu The cross context virtual CPU structure.
9360 * @param cbInstr The instruction length in bytes.
9361 * @param iEffSeg The effective segment register to use with @a
9362 * GCPtrVmxon.
9363 * @param GCPtrVmxon The linear address of the VMXON pointer.
9364 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9365 *
9366 * @remarks Common VMX instruction checks are already expected to by the caller,
9367 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9368 */
9369static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9370 RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9371{
9372 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9373 {
9374 /* CPL. */
9375 if (pVCpu->iem.s.uCpl == 0)
9376 { /* likely */ }
9377 else
9378 {
9379 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9380 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9381 return iemRaiseGeneralProtectionFault0(pVCpu);
9382 }
9383
9384 /* A20M (A20 Masked) mode. */
9385 if (PGMPhysIsA20Enabled(pVCpu))
9386 { /* likely */ }
9387 else
9388 {
9389 Log(("vmxon: A20M mode -> #GP(0)\n"));
9390 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9391 return iemRaiseGeneralProtectionFault0(pVCpu);
9392 }
9393
9394 /* CR0. */
9395 {
9396 /*
9397 * CR0 MB1 bits.
9398 *
9399 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9400 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9401 * when the guest running in VMX non-root mode with unrestricted-guest control
9402 * enabled in the VMCS.
9403 */
9404 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9405 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9406 { /* likely */ }
9407 else
9408 {
9409 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9410 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9411 return iemRaiseGeneralProtectionFault0(pVCpu);
9412 }
9413
9414 /* CR0 MBZ bits. */
9415 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9416 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9417 { /* likely */ }
9418 else
9419 {
9420 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9421 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9422 return iemRaiseGeneralProtectionFault0(pVCpu);
9423 }
9424 }
9425
9426 /* CR4. */
9427 {
9428 /* CR4 MB1 bits. */
9429 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9430 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9431 { /* likely */ }
9432 else
9433 {
9434 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9435 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9436 return iemRaiseGeneralProtectionFault0(pVCpu);
9437 }
9438
9439 /* CR4 MBZ bits. */
9440 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9441 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9442 { /* likely */ }
9443 else
9444 {
9445 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9446 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9447 return iemRaiseGeneralProtectionFault0(pVCpu);
9448 }
9449 }
9450
9451 /* Feature control MSR's LOCK and VMXON bits. */
9452 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9453 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9454 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9455 { /* likely */ }
9456 else
9457 {
9458 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9459 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9460 return iemRaiseGeneralProtectionFault0(pVCpu);
9461 }
9462
9463 /* Get the VMXON pointer from the location specified by the source memory operand. */
9464 RTGCPHYS GCPhysVmxon;
9465 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9466 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9467 { /* likely */ }
9468 else
9469 {
9470 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9471 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9472 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9473 return rcStrict;
9474 }
9475
9476 /* VMXON region pointer alignment. */
9477 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9478 { /* likely */ }
9479 else
9480 {
9481 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9482 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9483 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9484 iemVmxVmFailInvalid(pVCpu);
9485 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9486 }
9487
9488 /* VMXON physical-address width limits. */
9489 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9490 { /* likely */ }
9491 else
9492 {
9493 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9494 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9495 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9496 iemVmxVmFailInvalid(pVCpu);
9497 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9498 }
9499
9500 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9501 restriction imposed by our implementation. */
9502 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9503 { /* likely */ }
9504 else
9505 {
9506 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9507 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9508 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9509 iemVmxVmFailInvalid(pVCpu);
9510 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9511 }
9512
9513 /* Read the VMCS revision ID from the VMXON region. */
9514 VMXVMCSREVID VmcsRevId;
9515 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9516 if (RT_SUCCESS(rc))
9517 { /* likely */ }
9518 else
9519 {
9520 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9521 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9522 return rc;
9523 }
9524
9525 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9526 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9527 { /* likely */ }
9528 else
9529 {
9530 /* Revision ID mismatch. */
9531 if (!VmcsRevId.n.fIsShadowVmcs)
9532 {
9533 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9534 VmcsRevId.n.u31RevisionId));
9535 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9536 iemVmxVmFailInvalid(pVCpu);
9537 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9538 }
9539
9540 /* Shadow VMCS disallowed. */
9541 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9542 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9543 iemVmxVmFailInvalid(pVCpu);
9544 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9545 }
9546
9547 /*
9548 * Record that we're in VMX operation, block INIT, block and disable A20M.
9549 */
9550 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9551 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9552 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9553
9554 /* Clear address-range monitoring. */
9555 EMMonitorWaitClear(pVCpu);
9556 /** @todo NSTVMX: Intel PT. */
9557
9558 iemVmxVmSucceed(pVCpu);
9559 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9560 }
9561 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9562 {
9563 /* Nested-guest intercept. */
9564 if (pExitInfo)
9565 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9566 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9567 }
9568
9569 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9570
9571 /* CPL. */
9572 if (pVCpu->iem.s.uCpl > 0)
9573 {
9574 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9575 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9576 return iemRaiseGeneralProtectionFault0(pVCpu);
9577 }
9578
9579 /* VMXON when already in VMX root mode. */
9580 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9581 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9582 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9583}
9584
9585
9586/**
9587 * Interface for HM and EM to emulate the VMXON instruction.
9588 *
9589 * @returns Strict VBox status code.
9590 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9591 * @param pExitInfo Pointer to the VM-exit information.
9592 * @thread EMT(pVCpu)
9593 */
9594VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9595{
9596 Assert(pExitInfo);
9597 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9598 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9599
9600 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9601
9602 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9603 uint8_t const cbInstr = pExitInfo->cbInstr;
9604 RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9605 VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9606 Assert(!pVCpu->iem.s.cActiveMappings);
9607 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9608}
9609
9610
9611/**
9612 * Implements 'VMXOFF'.
9613 *
9614 * @remarks Common VMX instruction checks are already expected to by the caller,
9615 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9616 */
9617IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9618{
9619 /* Nested-guest intercept. */
9620 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9621 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9622
9623 /* CPL. */
9624 if (pVCpu->iem.s.uCpl == 0)
9625 { /* likely */ }
9626 else
9627 {
9628 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9629 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9630 return iemRaiseGeneralProtectionFault0(pVCpu);
9631 }
9632
9633 /* Dual monitor treatment of SMIs and SMM. */
9634 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9635 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9636 { /* likely */ }
9637 else
9638 {
9639 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9640 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9641 }
9642
9643 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9644 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9645 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9646
9647 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9648 { /** @todo NSTVMX: Unblock SMI. */ }
9649
9650 EMMonitorWaitClear(pVCpu);
9651 /** @todo NSTVMX: Unblock and enable A20M. */
9652
9653 iemVmxVmSucceed(pVCpu);
9654 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9655}
9656
9657
9658/**
9659 * Interface for HM and EM to emulate the VMXOFF instruction.
9660 *
9661 * @returns Strict VBox status code.
9662 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9663 * @param cbInstr The instruction length in bytes.
9664 * @thread EMT(pVCpu)
9665 */
9666VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9667{
9668 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9669 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9670
9671 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9672 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9673 Assert(!pVCpu->iem.s.cActiveMappings);
9674 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9675}
9676
9677
9678/**
9679 * Implements 'VMXON'.
9680 */
9681IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9682{
9683 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9684}
9685
9686
9687/**
9688 * Implements 'VMLAUNCH'.
9689 */
9690IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9691{
9692 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9693}
9694
9695
9696/**
9697 * Implements 'VMRESUME'.
9698 */
9699IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9700{
9701 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9702}
9703
9704
9705/**
9706 * Implements 'VMPTRLD'.
9707 */
9708IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9709{
9710 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9711}
9712
9713
9714/**
9715 * Implements 'VMPTRST'.
9716 */
9717IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9718{
9719 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9720}
9721
9722
9723/**
9724 * Implements 'VMCLEAR'.
9725 */
9726IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9727{
9728 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9729}
9730
9731
9732/**
9733 * Implements 'VMWRITE' register.
9734 */
9735IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9736{
9737 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9738}
9739
9740
9741/**
9742 * Implements 'VMWRITE' memory.
9743 */
9744IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9745{
9746 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9747}
9748
9749
9750/**
9751 * Implements 'VMREAD' register (64-bit).
9752 */
9753IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9754{
9755 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9756}
9757
9758
9759/**
9760 * Implements 'VMREAD' register (32-bit).
9761 */
9762IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint64_t *, pu64Dst, uint32_t, u32VmcsField)
9763{
9764 VBOXSTRICTRC const rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, (uint32_t *)pu64Dst, u32VmcsField, NULL /* pExitInfo */);
9765 /* Zero the high part of the register on success. */
9766 if (rcStrict == VINF_SUCCESS)
9767 *pu64Dst = (uint32_t)*pu64Dst;
9768 return rcStrict;
9769}
9770
9771
9772/**
9773 * Implements 'VMREAD' memory, 64-bit register.
9774 */
9775IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9776{
9777 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9778}
9779
9780
9781/**
9782 * Implements 'VMREAD' memory, 32-bit register.
9783 */
9784IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9785{
9786 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9787}
9788
9789
9790/**
9791 * Implements 'INVVPID'.
9792 */
9793IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9794{
9795 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9796}
9797
9798
9799#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9800/**
9801 * Implements 'INVEPT'.
9802 */
9803IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9804{
9805 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9806}
9807#endif
9808
9809
9810/**
9811 * Implements VMX's implementation of PAUSE.
9812 */
9813IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9814{
9815 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9816 {
9817 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9818 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9819 return rcStrict;
9820 }
9821
9822 /*
9823 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9824 * a VM-exit, the instruction operates normally.
9825 */
9826 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9827}
9828
9829#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9830
9831
9832/**
9833 * Implements 'VMCALL'.
9834 */
9835IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9836{
9837 pVCpu->iem.s.cPotentialExits++;
9838
9839#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9840 /* Nested-guest intercept. */
9841 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9842 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9843#endif
9844
9845 /* Join forces with vmmcall. */
9846 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9847}
9848
9849
9850#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9851
9852/**
9853 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9854 *
9855 * @remarks The @a uUser argument is currently unused.
9856 */
9857DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9858 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9859 PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9860{
9861 RT_NOREF3(pvPhys, enmOrigin, uUser);
9862
9863 RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9864 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9865 {
9866 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9867 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9868
9869 uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9870 uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9871
9872 LogFlowFunc(("Fault at %#RGp (cbBuf=%u fAccess=%#x)\n", GCPhysFault, cbBuf, fAccess));
9873 VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9874 if (RT_FAILURE(rcStrict))
9875 return rcStrict;
9876
9877 /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9878 return VINF_SUCCESS;
9879 }
9880
9881 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9882 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9883 if (RT_FAILURE(rc))
9884 return rc;
9885
9886 /* Instruct the caller of this handler to perform the read/write as normal memory. */
9887 return VINF_PGM_HANDLER_DO_DEFAULT;
9888}
9889
9890
9891# ifndef IN_RING3
9892/**
9893 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9894 * \#PF access handler callback for guest VMX APIC-access page.}
9895 */
9896DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
9897 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9898
9899{
9900 RT_NOREF3(pVM, pCtx, uUser);
9901
9902 /*
9903 * Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9904 * Otherwise we must deregister the page and allow regular RAM access.
9905 * Failing to do so lands us with endless EPT VM-exits.
9906 */
9907 RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9908 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9909 {
9910 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9911 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9912
9913 /*
9914 * Check if the access causes an APIC-access VM-exit.
9915 */
9916 uint32_t fAccess;
9917 if (uErr & X86_TRAP_PF_ID)
9918 fAccess = IEM_ACCESS_INSTRUCTION;
9919 else if (uErr & X86_TRAP_PF_RW)
9920 fAccess = IEM_ACCESS_DATA_W;
9921 else
9922 fAccess = IEM_ACCESS_DATA_R;
9923
9924 RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
9925 uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
9926 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
9927 LogFlowFunc(("#PF at %#RGp (GCPhysNestedFault=%#RGp offAccess=%#x)\n", GCPhysFault, GCPhysNestedFault, offAccess));
9928 if (fIntercept)
9929 {
9930 /*
9931 * Query the source VM-exit (from the execution engine) that caused this access
9932 * within the APIC-access page. Currently only HM is supported.
9933 */
9934 AssertMsg(VM_IS_HM_ENABLED(pVM),
9935 ("VM-exit auxiliary info. fetching not supported for execution engine %d\n", pVM->bMainExecutionEngine));
9936
9937 HMEXITAUX HmExitAux;
9938 RT_ZERO(HmExitAux);
9939 int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
9940 | HMVMX_READ_EXIT_QUALIFICATION
9941 | HMVMX_READ_IDT_VECTORING_INFO
9942 | HMVMX_READ_IDT_VECTORING_ERROR_CODE);
9943 AssertRC(rc);
9944
9945 /*
9946 * Verify the VM-exit reason must be an EPT violation.
9947 * Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
9948 * Refer to @bugref{10092#c33s} for a more detailed explanation.
9949 */
9950 AssertMsgReturn(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
9951 ("Unexpected call to APIC-access page #PF handler for %#RGp offAcesss=%u uErr=%#RGx uReason=%u\n",
9952 GCPhysPage, offAccess, uErr, HmExitAux.Vmx.uReason), VERR_IEM_IPE_7);
9953
9954 /*
9955 * Construct the virtual APIC-access VM-exit.
9956 */
9957 VMXAPICACCESS enmAccess;
9958 if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
9959 {
9960 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9961 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
9962 else if (fAccess == IEM_ACCESS_INSTRUCTION)
9963 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
9964 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
9965 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
9966 else
9967 enmAccess = VMXAPICACCESS_LINEAR_READ;
9968
9969 /* For linear-address accesss the instruction length must be valid. */
9970 AssertMsg(HmExitAux.Vmx.cbInstr > 0,
9971 ("Invalid APIC-access VM-exit instruction length. cbInstr=%u\n", HmExitAux.Vmx.cbInstr));
9972 }
9973 else
9974 {
9975 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9976 enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
9977 else
9978 {
9979 /** @todo How to distinguish between monitoring/trace vs other instructions
9980 * here? */
9981 enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
9982 }
9983
9984 /* For physical accesses the instruction length is undefined, we zero it for safety and consistency. */
9985 HmExitAux.Vmx.cbInstr = 0;
9986 }
9987
9988 /*
9989 * Raise the APIC-access VM-exit.
9990 */
9991 LogFlowFunc(("Raising APIC-access VM-exit from #PF handler at offset %#x\n", offAccess));
9992 VMXVEXITINFO const ExitInfo
9993 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_APIC_ACCESS,
9994 RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
9995 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess),
9996 HmExitAux.Vmx.cbInstr);
9997 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_IDT(HmExitAux.Vmx.uIdtVectoringInfo,
9998 HmExitAux.Vmx.uIdtVectoringErrCode);
9999 VBOXSTRICTRC const rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
10000 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
10001 }
10002
10003 /*
10004 * The access isn't intercepted, which means it needs to be virtualized.
10005 *
10006 * This requires emulating the instruction because we need the bytes being
10007 * read/written by the instruction not just the offset being accessed within
10008 * the APIC-access page (which we derive from the faulting address).
10009 */
10010 LogFlowFunc(("Access at offset %#x not intercepted -> VINF_EM_RAW_EMULATE_INSTR\n", offAccess));
10011 return VINF_EM_RAW_EMULATE_INSTR;
10012 }
10013
10014 /** @todo This isn't ideal but works for now as nested-hypervisors generally play
10015 * nice because the spec states that this page should be modified only when
10016 * no CPU refers to it VMX non-root mode. Nonetheless, we could use an atomic
10017 * reference counter to ensure the aforementioned condition before
10018 * de-registering the page. */
10019 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
10020 int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
10021 if (RT_FAILURE(rc))
10022 return rc;
10023
10024 return VINF_SUCCESS;
10025}
10026# endif /* !IN_RING3 */
10027
10028#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10029
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