VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 96860

Last change on this file since 96860 was 96823, checked in by vboxsync, 20 months ago

VMM/IEM: Nested VMX: bugref:10092 Restricted iemVmxVmexitInstrNeedsInfo's checking of allowed instructions to debug builds since no call is dependent on runtime info.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 403.0 KB
Line 
1/* $Id: IEMAllCImplVmxInstr.cpp 96823 2022-09-22 05:08:44Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM_VMX
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/cpum.h>
36#include <VBox/vmm/apic.h>
37#include <VBox/vmm/pgm.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/hm.h>
40#include <VBox/vmm/gim.h>
41#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
42# include <VBox/vmm/hmvmxinline.h>
43#endif
44#include <VBox/vmm/tm.h>
45#include "IEMInternal.h"
46#include <VBox/vmm/vmcc.h>
47#include <VBox/log.h>
48#include <VBox/err.h>
49#include <VBox/param.h>
50#include <VBox/disopcode.h>
51#include <iprt/asm-math.h>
52#include <iprt/assert.h>
53#include <iprt/string.h>
54#include <iprt/x86.h>
55
56#include "IEMInline.h"
57
58
59/*********************************************************************************************************************************
60* Defined Constants And Macros *
61*********************************************************************************************************************************/
62#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
63/**
64 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
65 * relative offsets.
66 */
67# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
68# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
69# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
70# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
71# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
72# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
73# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
74# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
75# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
76# if 0
77# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
78# endif
79# else /* !IEM_WITH_CODE_TLB */
80# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
81 do \
82 { \
83 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
84 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
85 } while (0)
86
87# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
88
89# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
90 do \
91 { \
92 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
93 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
94 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
95 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
96 } while (0)
97
98# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
99 do \
100 { \
101 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
102 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
103 } while (0)
104
105# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
106 do \
107 { \
108 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
109 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
110 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
111 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
112 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
113 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
114 } while (0)
115
116# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
117 do \
118 { \
119 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
120 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
121 } while (0)
122
123# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
124 do \
125 { \
126 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
127 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
128 } while (0)
129
130# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
131 do \
132 { \
133 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
134 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
135 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
136 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
137 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
138 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
139 } while (0)
140# endif /* !IEM_WITH_CODE_TLB */
141
142/** Check for VMX instructions requiring to be in VMX operation.
143 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
144# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
145 do \
146 { \
147 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
148 { /* likely */ } \
149 else \
150 { \
151 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
152 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
153 return iemRaiseUndefinedOpcode(a_pVCpu); \
154 } \
155 } while (0)
156
157/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
158# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
159 do \
160 { \
161 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
162 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
163 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
164 return VERR_VMX_VMENTRY_FAILED; \
165 } while (0)
166
167/** Marks a VM-exit failure with a diagnostic reason and logs. */
168# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
169 do \
170 { \
171 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
172 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
173 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
174 } while (0)
175
176/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
177# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
178 do \
179 { \
180 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
181 return VERR_VMX_VMEXIT_FAILED; \
182 } while (0)
183
184
185/*********************************************************************************************************************************
186* Global Variables *
187*********************************************************************************************************************************/
188/** @todo NSTVMX: The following VM-exit intercepts are pending:
189 * VMX_EXIT_IO_SMI
190 * VMX_EXIT_SMI
191 * VMX_EXIT_GETSEC
192 * VMX_EXIT_RSM
193 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
194 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
195 * VMX_EXIT_RDRAND
196 * VMX_EXIT_VMFUNC
197 * VMX_EXIT_ENCLS
198 * VMX_EXIT_RDSEED
199 * VMX_EXIT_PML_FULL
200 * VMX_EXIT_XSAVES
201 * VMX_EXIT_XRSTORS
202 */
203/**
204 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
205 *
206 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
207 * second dimension is the Index, see VMXVMCSFIELD.
208 */
209uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
210{
211 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
212 {
213 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
214 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
215 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
216 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
217 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
218 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
219 /* 27 */ UINT16_MAX,
220 },
221 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
222 {
223 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
224 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
237 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
238 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
239 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
240 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
241 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
242 /* 26-27 */ UINT16_MAX, UINT16_MAX
243 },
244 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
245 {
246 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
247 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
248 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
249 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
250 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
251 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
252 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
253 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
254 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
255 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
256 },
257 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
258 {
259 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
260 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
261 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
262 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
263 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
264 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
265 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
266 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
267 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
268 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
269 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
270 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
271 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
272 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
273 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
274 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
275 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
276 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
277 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
278 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
279 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
280 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
281 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
282 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
283 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
284 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
285 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
286 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
287 },
288 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
289 {
290 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
291 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
292 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
293 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
294 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
295 },
296 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
297 {
298 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
299 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
300 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
301 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
302 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
303 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
304 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
305 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
306 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
307 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
308 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
309 /* 11 */ UINT16_MAX,
310 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
311 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
312 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
313 },
314 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
315 {
316 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
317 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
318 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
319 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
320 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
321 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
322 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
334 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
335 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
336 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
337 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
338 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
339 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
340 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
341 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
342 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
343 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
344 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
345 /* 26-27 */ UINT16_MAX, UINT16_MAX
346 },
347 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
348 {
349 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
350 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
351 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
352 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
353 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
354 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
355 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
356 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
357 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
358 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
359 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
360 },
361 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
362 {
363 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
364 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
365 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
366 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
367 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
368 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
369 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
370 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
371 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
372 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
373 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
374 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
375 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
376 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
377 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
378 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
379 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
380 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
381 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
382 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
383 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
384 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
385 /* 22 */ UINT16_MAX,
386 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
387 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
388 },
389 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
390 {
391 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
392 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
394 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
395 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
396 },
397 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
398 {
399 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
400 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
401 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
402 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
403 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
404 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
405 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
406 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
407 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
408 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
409 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
410 },
411 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
412 {
413 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
414 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
415 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
416 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
417 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
418 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
419 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
420 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
421 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
437 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
438 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
439 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
440 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
441 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
442 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
443 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
444 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
445 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
446 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
447 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
448 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
449 },
450 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
451 {
452 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
453 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
454 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
455 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
456 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
457 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
458 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
459 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
460 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
461 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
462 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
463 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
464 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
465 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
466 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
467 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
468 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
469 }
470};
471
472
473/**
474 * Gets a host selector from the VMCS.
475 *
476 * @param pVmcs Pointer to the virtual VMCS.
477 * @param iSelReg The index of the segment register (X86_SREG_XXX).
478 */
479DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
480{
481 Assert(iSegReg < X86_SREG_COUNT);
482 RTSEL HostSel;
483 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
484 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
485 uint8_t const uWidthType = (uWidth << 2) | uType;
486 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
487 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
488 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
489 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
490 uint8_t const *pbField = pbVmcs + offField;
491 HostSel = *(uint16_t *)pbField;
492 return HostSel;
493}
494
495
496/**
497 * Sets a guest segment register in the VMCS.
498 *
499 * @param pVmcs Pointer to the virtual VMCS.
500 * @param iSegReg The index of the segment register (X86_SREG_XXX).
501 * @param pSelReg Pointer to the segment register.
502 */
503static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
504{
505 Assert(pSelReg);
506 Assert(iSegReg < X86_SREG_COUNT);
507
508 /* Selector. */
509 {
510 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
511 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
512 uint8_t const uWidthType = (uWidth << 2) | uType;
513 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
514 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
515 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
516 uint8_t *pbVmcs = (uint8_t *)pVmcs;
517 uint8_t *pbField = pbVmcs + offField;
518 *(uint16_t *)pbField = pSelReg->Sel;
519 }
520
521 /* Limit. */
522 {
523 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
524 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
525 uint8_t const uWidthType = (uWidth << 2) | uType;
526 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
527 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
528 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
529 uint8_t *pbVmcs = (uint8_t *)pVmcs;
530 uint8_t *pbField = pbVmcs + offField;
531 *(uint32_t *)pbField = pSelReg->u32Limit;
532 }
533
534 /* Base. */
535 {
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t const *pbField = pbVmcs + offField;
544 *(uint64_t *)pbField = pSelReg->u64Base;
545 }
546
547 /* Attributes. */
548 {
549 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
550 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
551 | X86DESCATTR_UNUSABLE;
552 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
553 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
554 uint8_t const uWidthType = (uWidth << 2) | uType;
555 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
556 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
557 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
558 uint8_t *pbVmcs = (uint8_t *)pVmcs;
559 uint8_t *pbField = pbVmcs + offField;
560 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
561 }
562}
563
564
565/**
566 * Gets a guest segment register from the VMCS.
567 *
568 * @returns VBox status code.
569 * @param pVmcs Pointer to the virtual VMCS.
570 * @param iSegReg The index of the segment register (X86_SREG_XXX).
571 * @param pSelReg Where to store the segment register (only updated when
572 * VINF_SUCCESS is returned).
573 *
574 * @remarks Warning! This does not validate the contents of the retrieved segment
575 * register.
576 */
577static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
578{
579 Assert(pSelReg);
580 Assert(iSegReg < X86_SREG_COUNT);
581
582 /* Selector. */
583 uint16_t u16Sel;
584 {
585 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
586 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
587 uint8_t const uWidthType = (uWidth << 2) | uType;
588 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
589 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
590 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
591 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
592 uint8_t const *pbField = pbVmcs + offField;
593 u16Sel = *(uint16_t *)pbField;
594 }
595
596 /* Limit. */
597 uint32_t u32Limit;
598 {
599 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
600 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
601 uint8_t const uWidthType = (uWidth << 2) | uType;
602 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
603 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
604 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
605 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
606 uint8_t const *pbField = pbVmcs + offField;
607 u32Limit = *(uint32_t *)pbField;
608 }
609
610 /* Base. */
611 uint64_t u64Base;
612 {
613 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
614 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
615 uint8_t const uWidthType = (uWidth << 2) | uType;
616 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
617 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
618 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
619 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
620 uint8_t const *pbField = pbVmcs + offField;
621 u64Base = *(uint64_t *)pbField;
622 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
623 }
624
625 /* Attributes. */
626 uint32_t u32Attr;
627 {
628 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
629 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
630 uint8_t const uWidthType = (uWidth << 2) | uType;
631 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
632 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
633 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
634 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
635 uint8_t const *pbField = pbVmcs + offField;
636 u32Attr = *(uint32_t *)pbField;
637 }
638
639 pSelReg->Sel = u16Sel;
640 pSelReg->ValidSel = u16Sel;
641 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
642 pSelReg->u32Limit = u32Limit;
643 pSelReg->u64Base = u64Base;
644 pSelReg->Attr.u = u32Attr;
645 return VINF_SUCCESS;
646}
647
648
649/**
650 * Converts an IEM exception event type to a VMX event type.
651 *
652 * @returns The VMX event type.
653 * @param uVector The interrupt / exception vector.
654 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
655 */
656DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
657{
658 /* Paranoia (callers may use these interchangeably). */
659 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
660 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
661 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
662 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
663 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
664 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
665 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
666 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
667 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
668 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
669 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
670 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
671
672 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
673 {
674 if (uVector == X86_XCPT_NMI)
675 return VMX_EXIT_INT_INFO_TYPE_NMI;
676 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
677 }
678
679 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
680 {
681 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
682 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
683 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
684 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
685 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
686 }
687
688 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
689 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
690}
691
692
693/**
694 * Determines whether the guest is using PAE paging given the VMCS.
695 *
696 * @returns @c true if PAE paging mode is used, @c false otherwise.
697 * @param pVmcs Pointer to the virtual VMCS.
698 */
699DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
700{
701 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
702 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
703 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
704}
705
706
707/**
708 * Sets the Exit qualification VMCS field.
709 *
710 * @param pVCpu The cross context virtual CPU structure.
711 * @param u64ExitQual The Exit qualification.
712 */
713DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
714{
715 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
716}
717
718
719/**
720 * Sets the VM-exit interruption information field.
721 *
722 * @param pVCpu The cross context virtual CPU structure.
723 * @param uExitIntInfo The VM-exit interruption information.
724 */
725DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
726{
727 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
728}
729
730
731/**
732 * Sets the VM-exit interruption error code.
733 *
734 * @param pVCpu The cross context virtual CPU structure.
735 * @param uErrCode The error code.
736 */
737DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
738{
739 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
740}
741
742
743/**
744 * Sets the IDT-vectoring information field.
745 *
746 * @param pVCpu The cross context virtual CPU structure.
747 * @param uIdtVectorInfo The IDT-vectoring information.
748 */
749DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
750{
751 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
752}
753
754
755/**
756 * Sets the IDT-vectoring error code field.
757 *
758 * @param pVCpu The cross context virtual CPU structure.
759 * @param uErrCode The error code.
760 */
761DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
762{
763 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
764}
765
766
767/**
768 * Sets the VM-exit guest-linear address VMCS field.
769 *
770 * @param pVCpu The cross context virtual CPU structure.
771 * @param uGuestLinearAddr The VM-exit guest-linear address.
772 */
773DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
774{
775 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
776 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
777 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
778}
779
780
781/**
782 * Sets the VM-exit guest-physical address VMCS field.
783 *
784 * @param pVCpu The cross context virtual CPU structure.
785 * @param uGuestPhysAddr The VM-exit guest-physical address.
786 */
787DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
788{
789 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
790}
791
792
793/**
794 * Sets the VM-exit instruction length VMCS field.
795 *
796 * @param pVCpu The cross context virtual CPU structure.
797 * @param cbInstr The VM-exit instruction length in bytes.
798 *
799 * @remarks Callers may clear this field to 0. Hence, this function does not check
800 * the validity of the instruction length.
801 */
802DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
803{
804 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
805}
806
807
808/**
809 * Sets the VM-exit instruction info. VMCS field.
810 *
811 * @param pVCpu The cross context virtual CPU structure.
812 * @param uExitInstrInfo The VM-exit instruction information.
813 */
814DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
815{
816 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
817}
818
819
820/**
821 * Sets the guest pending-debug exceptions field.
822 *
823 * @param pVCpu The cross context virtual CPU structure.
824 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
825 */
826DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
827{
828 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
829 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
830}
831
832
833/**
834 * Implements VMSucceed for VMX instruction success.
835 *
836 * @param pVCpu The cross context virtual CPU structure.
837 */
838DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
839{
840 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
841}
842
843
844/**
845 * Implements VMFailInvalid for VMX instruction failure.
846 *
847 * @param pVCpu The cross context virtual CPU structure.
848 */
849DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
850{
851 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
852}
853
854
855/**
856 * Implements VMFail for VMX instruction failure.
857 *
858 * @param pVCpu The cross context virtual CPU structure.
859 * @param enmInsErr The VM instruction error.
860 */
861DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
862{
863 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
864}
865
866
867/**
868 * Checks if the given auto-load/store MSR area count is valid for the
869 * implementation.
870 *
871 * @returns @c true if it's within the valid limit, @c false otherwise.
872 * @param pVCpu The cross context virtual CPU structure.
873 * @param uMsrCount The MSR area count to check.
874 */
875DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
876{
877 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
878 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
879 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
880 if (uMsrCount <= cMaxSupportedMsrs)
881 return true;
882 return false;
883}
884
885
886/**
887 * Flushes the current VMCS contents back to guest memory.
888 *
889 * @returns VBox status code.
890 * @param pVCpu The cross context virtual CPU structure.
891 */
892DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
893{
894 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
895 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
896 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
897 return rc;
898}
899
900
901/**
902 * Populates the current VMCS contents from guest memory.
903 *
904 * @returns VBox status code.
905 * @param pVCpu The cross context virtual CPU structure.
906 */
907DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
908{
909 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
910 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
911 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
912 return rc;
913}
914
915
916/**
917 * Gets the instruction diagnostic for segment base checks during VM-entry of a
918 * nested-guest.
919 *
920 * @param iSegReg The segment index (X86_SREG_XXX).
921 */
922static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
923{
924 switch (iSegReg)
925 {
926 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
927 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
928 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
929 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
930 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
931 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
932 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
933 }
934}
935
936
937/**
938 * Gets the instruction diagnostic for segment base checks during VM-entry of a
939 * nested-guest that is in Virtual-8086 mode.
940 *
941 * @param iSegReg The segment index (X86_SREG_XXX).
942 */
943static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
944{
945 switch (iSegReg)
946 {
947 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
948 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
949 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
950 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
951 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
952 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
953 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
954 }
955}
956
957
958/**
959 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
960 * nested-guest that is in Virtual-8086 mode.
961 *
962 * @param iSegReg The segment index (X86_SREG_XXX).
963 */
964static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
965{
966 switch (iSegReg)
967 {
968 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
969 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
970 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
971 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
972 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
973 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
974 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
975 }
976}
977
978
979/**
980 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
981 * nested-guest that is in Virtual-8086 mode.
982 *
983 * @param iSegReg The segment index (X86_SREG_XXX).
984 */
985static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
986{
987 switch (iSegReg)
988 {
989 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
990 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
991 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
992 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
993 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
994 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
995 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
996 }
997}
998
999
1000/**
1001 * Gets the instruction diagnostic for segment attributes reserved bits failure
1002 * during VM-entry of a nested-guest.
1003 *
1004 * @param iSegReg The segment index (X86_SREG_XXX).
1005 */
1006static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
1007{
1008 switch (iSegReg)
1009 {
1010 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1011 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1012 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1013 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1014 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1015 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1016 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1017 }
1018}
1019
1020
1021/**
1022 * Gets the instruction diagnostic for segment attributes descriptor-type
1023 * (code/segment or system) failure during VM-entry of a nested-guest.
1024 *
1025 * @param iSegReg The segment index (X86_SREG_XXX).
1026 */
1027static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1028{
1029 switch (iSegReg)
1030 {
1031 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1032 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1033 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1034 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1035 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1036 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1037 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1038 }
1039}
1040
1041
1042/**
1043 * Gets the instruction diagnostic for segment attributes descriptor-type
1044 * (code/segment or system) failure during VM-entry of a nested-guest.
1045 *
1046 * @param iSegReg The segment index (X86_SREG_XXX).
1047 */
1048static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1049{
1050 switch (iSegReg)
1051 {
1052 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1053 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1054 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1055 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1056 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1057 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1058 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1059 }
1060}
1061
1062
1063/**
1064 * Gets the instruction diagnostic for segment attribute granularity failure during
1065 * VM-entry of a nested-guest.
1066 *
1067 * @param iSegReg The segment index (X86_SREG_XXX).
1068 */
1069static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1070{
1071 switch (iSegReg)
1072 {
1073 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1074 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1075 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1076 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1077 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1078 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1079 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1080 }
1081}
1082
1083/**
1084 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1085 * VM-entry of a nested-guest.
1086 *
1087 * @param iSegReg The segment index (X86_SREG_XXX).
1088 */
1089static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1090{
1091 switch (iSegReg)
1092 {
1093 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1094 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1095 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1096 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1097 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1098 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1099 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1100 }
1101}
1102
1103
1104/**
1105 * Gets the instruction diagnostic for segment attribute type accessed failure
1106 * during VM-entry of a nested-guest.
1107 *
1108 * @param iSegReg The segment index (X86_SREG_XXX).
1109 */
1110static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1111{
1112 switch (iSegReg)
1113 {
1114 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1115 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1116 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1117 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1118 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1119 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1120 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1121 }
1122}
1123
1124
1125/**
1126 * Saves the guest control registers, debug registers and some MSRs are part of
1127 * VM-exit.
1128 *
1129 * @param pVCpu The cross context virtual CPU structure.
1130 */
1131static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1132{
1133 /*
1134 * Saves the guest control registers, debug registers and some MSRs.
1135 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1136 */
1137 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1138
1139 /* Save control registers. */
1140 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1141 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1142 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1143
1144 /* Save SYSENTER CS, ESP, EIP. */
1145 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1146 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1147 {
1148 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1149 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1150 }
1151 else
1152 {
1153 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1154 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1155 }
1156
1157 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1158 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1159 {
1160 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1161 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1162 }
1163
1164 /* Save PAT MSR. */
1165 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1166 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1167
1168 /* Save EFER MSR. */
1169 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1170 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1171
1172 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1173 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1174
1175 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1176}
1177
1178
1179/**
1180 * Saves the guest force-flags in preparation of entering the nested-guest.
1181 *
1182 * @param pVCpu The cross context virtual CPU structure.
1183 */
1184static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1185{
1186 /* We shouldn't be called multiple times during VM-entry. */
1187 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1188
1189 /* MTF should not be set outside VMX non-root mode. */
1190 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1191
1192 /*
1193 * Preserve the required force-flags.
1194 *
1195 * We cache and clear force-flags that would affect the execution of the
1196 * nested-guest. Cached flags are then restored while returning to the guest
1197 * if necessary.
1198 *
1199 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1200 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1201 * instruction. Interrupt inhibition for any nested-guest instruction
1202 * is supplied by the guest-interruptibility state VMCS field and will
1203 * be set up as part of loading the guest state. Technically
1204 * blocking-by-STI is possible with VMLAUNCH/VMRESUME but we currently
1205 * disallow it since we can't distinguish it from blocking-by-MovSS
1206 * and no nested-hypervisor we care about uses STI immediately
1207 * followed by VMLAUNCH/VMRESUME.
1208 *
1209 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1210 * successful VM-entry (due to invalid guest-state) need to continue
1211 * blocking NMIs if it was in effect before VM-entry.
1212 *
1213 * - MTF need not be preserved as it's used only in VMX non-root mode and
1214 * is supplied through the VM-execution controls.
1215 *
1216 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1217 * we will be able to generate interrupts that may cause VM-exits for
1218 * the nested-guest.
1219 */
1220 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1221}
1222
1223
1224/**
1225 * Restores the guest force-flags in preparation of exiting the nested-guest.
1226 *
1227 * @param pVCpu The cross context virtual CPU structure.
1228 */
1229static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1230{
1231 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1232 {
1233 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1234 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1235 }
1236}
1237
1238
1239/**
1240 * Performs the VMX transition to/from VMX non-root mode.
1241 *
1242 * @param pVCpu The cross context virtual CPU structure.
1243*/
1244static int iemVmxTransition(PVMCPUCC pVCpu) RT_NOEXCEPT
1245{
1246 /*
1247 * Inform PGM about paging mode changes.
1248 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1249 * see comment in iemMemPageTranslateAndCheckAccess().
1250 */
1251 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1252 true /* fForce */);
1253 if (RT_SUCCESS(rc))
1254 { /* likely */ }
1255 else
1256 return rc;
1257
1258 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1259 IEMTlbInvalidateAll(pVCpu);
1260
1261 /* Inform CPUM (recompiler), can later be removed. */
1262 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1263
1264 /* Re-initialize IEM cache/state after the drastic mode switch. */
1265 iemReInitExec(pVCpu);
1266 return rc;
1267}
1268
1269
1270/**
1271 * Calculates the current VMX-preemption timer value.
1272 *
1273 * @returns The current VMX-preemption timer value.
1274 * @param pVCpu The cross context virtual CPU structure.
1275 */
1276static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1277{
1278 /*
1279 * Assume the following:
1280 * PreemptTimerShift = 5
1281 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1282 * EntryTick = 50000 (TSC at time of VM-entry)
1283 *
1284 * CurTick Delta PreemptTimerVal
1285 * ----------------------------------
1286 * 60000 10000 2
1287 * 80000 30000 1
1288 * 90000 40000 0 -> VM-exit.
1289 *
1290 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1291 * The saved VMX-preemption timer value is calculated as follows:
1292 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1293 * E.g.:
1294 * Delta = 10000
1295 * Tmp = 10000 / (2 * 10000) = 0.5
1296 * NewPt = 2 - 0.5 = 2
1297 * Delta = 30000
1298 * Tmp = 30000 / (2 * 10000) = 1.5
1299 * NewPt = 2 - 1.5 = 1
1300 * Delta = 40000
1301 * Tmp = 40000 / 20000 = 2
1302 * NewPt = 2 - 2 = 0
1303 */
1304 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1305 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1306 if (uVmcsPreemptVal > 0)
1307 {
1308 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1309 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1310 uint64_t const uDelta = uCurTick - uEntryTick;
1311 uint32_t const uPreemptTimer = uVmcsPreemptVal
1312 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1313 return uPreemptTimer;
1314 }
1315 return 0;
1316}
1317
1318
1319/**
1320 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1321 *
1322 * @param pVCpu The cross context virtual CPU structure.
1323 */
1324static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1325{
1326 /*
1327 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1328 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1329 */
1330 /* CS, SS, ES, DS, FS, GS. */
1331 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1332 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1333 {
1334 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1335 if (!pSelReg->Attr.n.u1Unusable)
1336 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1337 else
1338 {
1339 /*
1340 * For unusable segments the attributes are undefined except for CS and SS.
1341 * For the rest we don't bother preserving anything but the unusable bit.
1342 */
1343 switch (iSegReg)
1344 {
1345 case X86_SREG_CS:
1346 pVmcs->GuestCs = pSelReg->Sel;
1347 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1348 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1349 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1350 | X86DESCATTR_UNUSABLE);
1351 break;
1352
1353 case X86_SREG_SS:
1354 pVmcs->GuestSs = pSelReg->Sel;
1355 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1356 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1357 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1358 break;
1359
1360 case X86_SREG_DS:
1361 pVmcs->GuestDs = pSelReg->Sel;
1362 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1363 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1364 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1365 break;
1366
1367 case X86_SREG_ES:
1368 pVmcs->GuestEs = pSelReg->Sel;
1369 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1370 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1371 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1372 break;
1373
1374 case X86_SREG_FS:
1375 pVmcs->GuestFs = pSelReg->Sel;
1376 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1377 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1378 break;
1379
1380 case X86_SREG_GS:
1381 pVmcs->GuestGs = pSelReg->Sel;
1382 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1383 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1384 break;
1385 }
1386 }
1387 }
1388
1389 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1390 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1391 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1392 | X86DESCATTR_UNUSABLE;
1393 /* LDTR. */
1394 {
1395 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1396 pVmcs->GuestLdtr = pSelReg->Sel;
1397 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1398 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1399 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1400 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1401 }
1402
1403 /* TR. */
1404 {
1405 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1406 pVmcs->GuestTr = pSelReg->Sel;
1407 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1408 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1409 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1410 }
1411
1412 /* GDTR. */
1413 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1414 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1415
1416 /* IDTR. */
1417 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1418 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1419}
1420
1421
1422/**
1423 * Saves guest non-register state as part of VM-exit.
1424 *
1425 * @param pVCpu The cross context virtual CPU structure.
1426 * @param uExitReason The VM-exit reason.
1427 */
1428static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1429{
1430 /*
1431 * Save guest non-register state.
1432 * See Intel spec. 27.3.4 "Saving Non-Register State".
1433 */
1434 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1435
1436 /*
1437 * Activity state.
1438 * Most VM-exits will occur in the active state. However, if the first instruction
1439 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1440 * the VM-exit will be from the HLT activity state.
1441 *
1442 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1443 */
1444 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1445 * not? */
1446 EMSTATE const enmActivityState = EMGetState(pVCpu);
1447 switch (enmActivityState)
1448 {
1449 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1450 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1451 }
1452
1453 /*
1454 * Interruptibility-state.
1455 */
1456 /* NMI. */
1457 pVmcs->u32GuestIntrState = 0;
1458 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1459 {
1460 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1461 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1462 }
1463 else
1464 {
1465 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1466 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1467 }
1468
1469 /* Blocking-by-STI. */
1470 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1471 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1472 {
1473 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1474 * currently. */
1475 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1476
1477 /* Clear inhibition unconditionally since we've ensured it isn't set prior to executing VMLAUNCH/VMRESUME. */
1478 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1479 }
1480 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1481
1482 /*
1483 * Pending debug exceptions.
1484 *
1485 * For VM-exits where it is not applicable, we can safely zero out the field.
1486 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1487 */
1488 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1489 && uExitReason != VMX_EXIT_SMI
1490 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1491 && !VMXIsVmexitTrapLike(uExitReason))
1492 {
1493 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1494 * block-by-MovSS is in effect. */
1495 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1496 }
1497
1498 /*
1499 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1500 *
1501 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1502 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1503 */
1504 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1505 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1506 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1507
1508 /*
1509 * PAE PDPTEs.
1510 *
1511 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1512 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1513 * we zero them for consistency.
1514 */
1515 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1516 {
1517 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1518 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1519 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1520 {
1521 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1522 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1523 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1524 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1525 }
1526 else
1527 {
1528 pVmcs->u64GuestPdpte0.u = 0;
1529 pVmcs->u64GuestPdpte1.u = 0;
1530 pVmcs->u64GuestPdpte2.u = 0;
1531 pVmcs->u64GuestPdpte3.u = 0;
1532 }
1533
1534 /* Clear PGM's copy of the EPT pointer for added safety. */
1535 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1536 }
1537 else
1538 {
1539 pVmcs->u64GuestPdpte0.u = 0;
1540 pVmcs->u64GuestPdpte1.u = 0;
1541 pVmcs->u64GuestPdpte2.u = 0;
1542 pVmcs->u64GuestPdpte3.u = 0;
1543 }
1544}
1545
1546
1547/**
1548 * Saves the guest-state as part of VM-exit.
1549 *
1550 * @returns VBox status code.
1551 * @param pVCpu The cross context virtual CPU structure.
1552 * @param uExitReason The VM-exit reason.
1553 */
1554static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1555{
1556 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1557 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1558
1559 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1560 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1561 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1562
1563 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1564}
1565
1566
1567/**
1568 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1569 *
1570 * @returns VBox status code.
1571 * @param pVCpu The cross context virtual CPU structure.
1572 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1573 */
1574static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1575{
1576 /*
1577 * Save guest MSRs.
1578 * See Intel spec. 27.4 "Saving MSRs".
1579 */
1580 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1581 const char * const pszFailure = "VMX-abort";
1582
1583 /*
1584 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1585 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1586 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1587 */
1588 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1589 if (!cMsrs)
1590 return VINF_SUCCESS;
1591
1592 /*
1593 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1594 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1595 * implementation causes a VMX-abort followed by a triple-fault.
1596 */
1597 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1598 if (fIsMsrCountValid)
1599 { /* likely */ }
1600 else
1601 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1602
1603 /*
1604 * Optimization if the nested hypervisor is using the same guest-physical page for both
1605 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1606 */
1607 PVMXAUTOMSR pMsrArea;
1608 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1609 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1610 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1611 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1612 else
1613 {
1614 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1615 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1616 if (RT_SUCCESS(rc))
1617 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1618 else
1619 {
1620 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1621 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1622 }
1623 }
1624
1625 /*
1626 * Update VM-exit MSR store area.
1627 */
1628 PVMXAUTOMSR pMsr = pMsrArea;
1629 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1630 {
1631 if ( !pMsr->u32Reserved
1632 && pMsr->u32Msr != MSR_IA32_SMBASE
1633 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1634 {
1635 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1636 if (rcStrict == VINF_SUCCESS)
1637 continue;
1638
1639 /*
1640 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1641 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1642 * recording the MSR index in the auxiliary info. field and indicated further by our
1643 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1644 * if possible, or come up with a better, generic solution.
1645 */
1646 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1647 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1648 ? kVmxVDiag_Vmexit_MsrStoreRing3
1649 : kVmxVDiag_Vmexit_MsrStore;
1650 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1651 }
1652 else
1653 {
1654 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1655 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1656 }
1657 }
1658
1659 /*
1660 * Commit the VM-exit MSR store are to guest memory.
1661 */
1662 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1663 if (RT_SUCCESS(rc))
1664 return VINF_SUCCESS;
1665
1666 NOREF(uExitReason);
1667 NOREF(pszFailure);
1668
1669 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1670 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1671}
1672
1673
1674/**
1675 * Performs a VMX abort (due to an fatal error during VM-exit).
1676 *
1677 * @returns Strict VBox status code.
1678 * @param pVCpu The cross context virtual CPU structure.
1679 * @param enmAbort The VMX abort reason.
1680 */
1681static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1682{
1683 /*
1684 * Perform the VMX abort.
1685 * See Intel spec. 27.7 "VMX Aborts".
1686 */
1687 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1688
1689 /* We don't support SMX yet. */
1690 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1691 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1692 {
1693 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1694 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1695 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1696 }
1697
1698 return VINF_EM_TRIPLE_FAULT;
1699}
1700
1701
1702/**
1703 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1704 *
1705 * @param pVCpu The cross context virtual CPU structure.
1706 */
1707static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1708{
1709 /*
1710 * Load host control registers, debug registers and MSRs.
1711 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1712 */
1713 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1714 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1715
1716 /* CR0. */
1717 {
1718 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1719 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu);
1720 uint64_t const uCr0Mb0 = VMX_V_CR0_FIXED1;
1721 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1722 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1723 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1724 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1725
1726 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1727 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1728 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1729 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1730 }
1731
1732 /* CR4. */
1733 {
1734 /* CR4 fixed bits are not modified. */
1735 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1736 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1737 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1738 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1739 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1740 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1741 if (fHostInLongMode)
1742 uValidHostCr4 |= X86_CR4_PAE;
1743 else
1744 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1745
1746 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1747 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1748 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1749 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1750 }
1751
1752 /* CR3 (host value validated while checking host-state during VM-entry). */
1753 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1754
1755 /* DR7. */
1756 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1757
1758 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1759
1760 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1761 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1762 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1763 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1764
1765 /* FS, GS bases are loaded later while we load host segment registers. */
1766
1767 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1768 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1769 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1770 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1771 {
1772 if (fHostInLongMode)
1773 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1774 else
1775 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1776 }
1777
1778 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1779
1780 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1781 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1782 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1783
1784 /* We don't support IA32_BNDCFGS MSR yet. */
1785}
1786
1787
1788/**
1789 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1790 *
1791 * @param pVCpu The cross context virtual CPU structure.
1792 */
1793static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1794{
1795 /*
1796 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1797 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1798 *
1799 * Warning! Be careful to not touch fields that are reserved by VT-x,
1800 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1801 */
1802 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1803 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1804
1805 /* CS, SS, ES, DS, FS, GS. */
1806 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1807 {
1808 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1809 bool const fUnusable = RT_BOOL(HostSel == 0);
1810 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1811
1812 /* Selector. */
1813 pSelReg->Sel = HostSel;
1814 pSelReg->ValidSel = HostSel;
1815 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1816
1817 /* Limit. */
1818 pSelReg->u32Limit = 0xffffffff;
1819
1820 /* Base. */
1821 pSelReg->u64Base = 0;
1822
1823 /* Attributes. */
1824 if (iSegReg == X86_SREG_CS)
1825 {
1826 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1827 pSelReg->Attr.n.u1DescType = 1;
1828 pSelReg->Attr.n.u2Dpl = 0;
1829 pSelReg->Attr.n.u1Present = 1;
1830 pSelReg->Attr.n.u1Long = fHostInLongMode;
1831 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1832 pSelReg->Attr.n.u1Granularity = 1;
1833 Assert(!pSelReg->Attr.n.u1Unusable);
1834 Assert(!fUnusable);
1835 }
1836 else
1837 {
1838 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1839 pSelReg->Attr.n.u1DescType = 1;
1840 pSelReg->Attr.n.u2Dpl = 0;
1841 pSelReg->Attr.n.u1Present = 1;
1842 pSelReg->Attr.n.u1DefBig = 1;
1843 pSelReg->Attr.n.u1Granularity = 1;
1844 pSelReg->Attr.n.u1Unusable = fUnusable;
1845 }
1846 }
1847
1848 /* FS base. */
1849 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1850 || fHostInLongMode)
1851 {
1852 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1853 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1854 }
1855
1856 /* GS base. */
1857 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1858 || fHostInLongMode)
1859 {
1860 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1861 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1862 }
1863
1864 /* TR. */
1865 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1866 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1867 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1868 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1869 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1870 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1871 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1872 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1873 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1874 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1875 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1876 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1877 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1878
1879 /* LDTR (Warning! do not touch the base and limits here). */
1880 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1881 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1882 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1883 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1884
1885 /* GDTR. */
1886 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1887 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1888 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1889
1890 /* IDTR.*/
1891 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1892 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1893 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1894}
1895
1896
1897/**
1898 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1899 *
1900 * @returns VBox status code.
1901 * @param pVCpu The cross context virtual CPU structure.
1902 * @param uExitReason The VMX instruction name (for logging purposes).
1903 */
1904static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1905{
1906 /*
1907 * Load host MSRs.
1908 * See Intel spec. 27.6 "Loading MSRs".
1909 */
1910 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1911 const char * const pszFailure = "VMX-abort";
1912
1913 /*
1914 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1915 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1916 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1917 */
1918 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1919 if (!cMsrs)
1920 return VINF_SUCCESS;
1921
1922 /*
1923 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1924 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1925 * implementation causes a VMX-abort followed by a triple-fault.
1926 */
1927 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1928 if (fIsMsrCountValid)
1929 { /* likely */ }
1930 else
1931 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1932
1933 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1934 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1935 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1936 if (RT_SUCCESS(rc))
1937 {
1938 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1939 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1940 {
1941 if ( !pMsr->u32Reserved
1942 && pMsr->u32Msr != MSR_K8_FS_BASE
1943 && pMsr->u32Msr != MSR_K8_GS_BASE
1944 && pMsr->u32Msr != MSR_K6_EFER
1945 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1946 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1947 {
1948 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1949 if (rcStrict == VINF_SUCCESS)
1950 continue;
1951
1952 /*
1953 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1954 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1955 * recording the MSR index in the auxiliary info. field and indicated further by our
1956 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1957 * if possible, or come up with a better, generic solution.
1958 */
1959 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1960 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1961 ? kVmxVDiag_Vmexit_MsrLoadRing3
1962 : kVmxVDiag_Vmexit_MsrLoad;
1963 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1964 }
1965 else
1966 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1967 }
1968 }
1969 else
1970 {
1971 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1972 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1973 }
1974
1975 NOREF(uExitReason);
1976 NOREF(pszFailure);
1977 return VINF_SUCCESS;
1978}
1979
1980
1981/**
1982 * Loads the host state as part of VM-exit.
1983 *
1984 * @returns Strict VBox status code.
1985 * @param pVCpu The cross context virtual CPU structure.
1986 * @param uExitReason The VM-exit reason (for logging purposes).
1987 */
1988static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1989{
1990 /*
1991 * Load host state.
1992 * See Intel spec. 27.5 "Loading Host State".
1993 */
1994 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1995 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1996
1997 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1998 if ( CPUMIsGuestInLongMode(pVCpu)
1999 && !fHostInLongMode)
2000 {
2001 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2002 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2003 }
2004
2005 /*
2006 * Check host PAE PDPTEs prior to loading the host state.
2007 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2008 */
2009 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2010 && !fHostInLongMode
2011 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2012 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2013 {
2014 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2015 if (RT_SUCCESS(rc))
2016 { /* likely*/ }
2017 else
2018 {
2019 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2020 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2021 }
2022 }
2023
2024 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2025 iemVmxVmexitLoadHostSegRegs(pVCpu);
2026
2027 /*
2028 * Load host RIP, RSP and RFLAGS.
2029 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2030 */
2031 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2032 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2033 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2034
2035 /* Clear address range monitoring. */
2036 EMMonitorWaitClear(pVCpu);
2037
2038 /* Perform the VMX transition (PGM updates). */
2039 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2040 if (rcStrict == VINF_SUCCESS)
2041 { /* likely */ }
2042 else if (RT_SUCCESS(rcStrict))
2043 {
2044 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2045 uExitReason));
2046 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2047 }
2048 else
2049 {
2050 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2051 return VBOXSTRICTRC_VAL(rcStrict);
2052 }
2053
2054 Assert(rcStrict == VINF_SUCCESS);
2055
2056 /* Load MSRs from the VM-exit auto-load MSR area. */
2057 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2058 if (RT_FAILURE(rc))
2059 {
2060 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2061 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2062 }
2063 return VINF_SUCCESS;
2064}
2065
2066
2067/**
2068 * Gets VM-exit instruction information along with any displacement for an
2069 * instruction VM-exit.
2070 *
2071 * @returns The VM-exit instruction information.
2072 * @param pVCpu The cross context virtual CPU structure.
2073 * @param uExitReason The VM-exit reason.
2074 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2075 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2076 * NULL.
2077 */
2078static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2079{
2080 RTGCPTR GCPtrDisp;
2081 VMXEXITINSTRINFO ExitInstrInfo;
2082 ExitInstrInfo.u = 0;
2083
2084 /*
2085 * Get and parse the ModR/M byte from our decoded opcodes.
2086 */
2087 uint8_t bRm;
2088 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2089 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2090 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2091 {
2092 /*
2093 * ModR/M indicates register addressing.
2094 *
2095 * The primary/secondary register operands are reported in the iReg1 or iReg2
2096 * fields depending on whether it is a read/write form.
2097 */
2098 uint8_t idxReg1;
2099 uint8_t idxReg2;
2100 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2101 {
2102 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2103 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2104 }
2105 else
2106 {
2107 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2108 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2109 }
2110 ExitInstrInfo.All.u2Scaling = 0;
2111 ExitInstrInfo.All.iReg1 = idxReg1;
2112 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2113 ExitInstrInfo.All.fIsRegOperand = 1;
2114 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2115 ExitInstrInfo.All.iSegReg = 0;
2116 ExitInstrInfo.All.iIdxReg = 0;
2117 ExitInstrInfo.All.fIdxRegInvalid = 1;
2118 ExitInstrInfo.All.iBaseReg = 0;
2119 ExitInstrInfo.All.fBaseRegInvalid = 1;
2120 ExitInstrInfo.All.iReg2 = idxReg2;
2121
2122 /* Displacement not applicable for register addressing. */
2123 GCPtrDisp = 0;
2124 }
2125 else
2126 {
2127 /*
2128 * ModR/M indicates memory addressing.
2129 */
2130 uint8_t uScale = 0;
2131 bool fBaseRegValid = false;
2132 bool fIdxRegValid = false;
2133 uint8_t iBaseReg = 0;
2134 uint8_t iIdxReg = 0;
2135 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2136 {
2137 /*
2138 * Parse the ModR/M, displacement for 16-bit addressing mode.
2139 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2140 */
2141 uint16_t u16Disp = 0;
2142 uint8_t const offDisp = offModRm + sizeof(bRm);
2143 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2144 {
2145 /* Displacement without any registers. */
2146 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2147 }
2148 else
2149 {
2150 /* Register (index and base). */
2151 switch (bRm & X86_MODRM_RM_MASK)
2152 {
2153 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2154 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2155 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2156 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2157 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2158 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2159 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2160 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2161 }
2162
2163 /* Register + displacement. */
2164 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2165 {
2166 case 0: break;
2167 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2168 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2169 default:
2170 {
2171 /* Register addressing, handled at the beginning. */
2172 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2173 break;
2174 }
2175 }
2176 }
2177
2178 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2179 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2180 }
2181 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2182 {
2183 /*
2184 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2185 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2186 */
2187 uint32_t u32Disp = 0;
2188 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2189 {
2190 /* Displacement without any registers. */
2191 uint8_t const offDisp = offModRm + sizeof(bRm);
2192 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2193 }
2194 else
2195 {
2196 /* Register (and perhaps scale, index and base). */
2197 uint8_t offDisp = offModRm + sizeof(bRm);
2198 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2199 if (iBaseReg == 4)
2200 {
2201 /* An SIB byte follows the ModR/M byte, parse it. */
2202 uint8_t bSib;
2203 uint8_t const offSib = offModRm + sizeof(bRm);
2204 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2205
2206 /* A displacement may follow SIB, update its offset. */
2207 offDisp += sizeof(bSib);
2208
2209 /* Get the scale. */
2210 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2211
2212 /* Get the index register. */
2213 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2214 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2215
2216 /* Get the base register. */
2217 iBaseReg = bSib & X86_SIB_BASE_MASK;
2218 fBaseRegValid = true;
2219 if (iBaseReg == 5)
2220 {
2221 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2222 {
2223 /* Mod is 0 implies a 32-bit displacement with no base. */
2224 fBaseRegValid = false;
2225 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2226 }
2227 else
2228 {
2229 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2230 iBaseReg = X86_GREG_xBP;
2231 }
2232 }
2233 }
2234
2235 /* Register + displacement. */
2236 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2237 {
2238 case 0: /* Handled above */ break;
2239 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2240 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2241 default:
2242 {
2243 /* Register addressing, handled at the beginning. */
2244 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2245 break;
2246 }
2247 }
2248 }
2249
2250 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2251 }
2252 else
2253 {
2254 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2255
2256 /*
2257 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2258 * See Intel instruction spec. 2.2 "IA-32e Mode".
2259 */
2260 uint64_t u64Disp = 0;
2261 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2262 if (fRipRelativeAddr)
2263 {
2264 /*
2265 * RIP-relative addressing mode.
2266 *
2267 * The displacement is 32-bit signed implying an offset range of +/-2G.
2268 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2269 */
2270 uint8_t const offDisp = offModRm + sizeof(bRm);
2271 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2272 }
2273 else
2274 {
2275 uint8_t offDisp = offModRm + sizeof(bRm);
2276
2277 /*
2278 * Register (and perhaps scale, index and base).
2279 *
2280 * REX.B extends the most-significant bit of the base register. However, REX.B
2281 * is ignored while determining whether an SIB follows the opcode. Hence, we
2282 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2283 *
2284 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2285 */
2286 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2287 if (iBaseReg == 4)
2288 {
2289 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2290 uint8_t bSib;
2291 uint8_t const offSib = offModRm + sizeof(bRm);
2292 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2293
2294 /* Displacement may follow SIB, update its offset. */
2295 offDisp += sizeof(bSib);
2296
2297 /* Get the scale. */
2298 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2299
2300 /* Get the index. */
2301 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2302 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2303
2304 /* Get the base. */
2305 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2306 fBaseRegValid = true;
2307 if (iBaseReg == 5)
2308 {
2309 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2310 {
2311 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2312 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2313 }
2314 else
2315 {
2316 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2317 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2318 }
2319 }
2320 }
2321 iBaseReg |= pVCpu->iem.s.uRexB;
2322
2323 /* Register + displacement. */
2324 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2325 {
2326 case 0: /* Handled above */ break;
2327 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2328 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2329 default:
2330 {
2331 /* Register addressing, handled at the beginning. */
2332 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2333 break;
2334 }
2335 }
2336 }
2337
2338 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2339 }
2340
2341 /*
2342 * The primary or secondary register operand is reported in iReg2 depending
2343 * on whether the primary operand is in read/write form.
2344 */
2345 uint8_t idxReg2;
2346 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2347 {
2348 idxReg2 = bRm & X86_MODRM_RM_MASK;
2349 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2350 idxReg2 |= pVCpu->iem.s.uRexB;
2351 }
2352 else
2353 {
2354 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2355 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2356 idxReg2 |= pVCpu->iem.s.uRexReg;
2357 }
2358 ExitInstrInfo.All.u2Scaling = uScale;
2359 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2360 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2361 ExitInstrInfo.All.fIsRegOperand = 0;
2362 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2363 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2364 ExitInstrInfo.All.iIdxReg = iIdxReg;
2365 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2366 ExitInstrInfo.All.iBaseReg = iBaseReg;
2367 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2368 ExitInstrInfo.All.iReg2 = idxReg2;
2369 }
2370
2371 /*
2372 * Handle exceptions to the norm for certain instructions.
2373 * (e.g. some instructions convey an instruction identity in place of iReg2).
2374 */
2375 switch (uExitReason)
2376 {
2377 case VMX_EXIT_GDTR_IDTR_ACCESS:
2378 {
2379 Assert(VMXINSTRID_IS_VALID(uInstrId));
2380 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2381 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2382 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2383 break;
2384 }
2385
2386 case VMX_EXIT_LDTR_TR_ACCESS:
2387 {
2388 Assert(VMXINSTRID_IS_VALID(uInstrId));
2389 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2390 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2391 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2392 break;
2393 }
2394
2395 case VMX_EXIT_RDRAND:
2396 case VMX_EXIT_RDSEED:
2397 {
2398 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2399 break;
2400 }
2401 }
2402
2403 /* Update displacement and return the constructed VM-exit instruction information field. */
2404 if (pGCPtrDisp)
2405 *pGCPtrDisp = GCPtrDisp;
2406
2407 return ExitInstrInfo.u;
2408}
2409
2410
2411/**
2412 * VMX VM-exit handler.
2413 *
2414 * @returns Strict VBox status code.
2415 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2416 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2417 * triple-fault.
2418 *
2419 * @param pVCpu The cross context virtual CPU structure.
2420 * @param uExitReason The VM-exit reason.
2421 * @param u64ExitQual The Exit qualification.
2422 *
2423 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2424 * called. Failures during VM-entry can cause VM-exits as well, so we
2425 * -cannot- assert we're in VMX non-root mode here.
2426 */
2427VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2428{
2429# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2430 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2431 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2432 return VERR_IEM_IPE_7;
2433# else
2434 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2435
2436 /*
2437 * Import all the guest-CPU state.
2438 *
2439 * HM on returning to guest execution would have to reset up a whole lot of state
2440 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2441 * the state and flag reloading the entire state on re-entry. So import the entire
2442 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2443 */
2444 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2445
2446 /*
2447 * Ensure VM-entry interruption information valid bit is cleared.
2448 *
2449 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2450 * by invalid-guest state or machine-check exceptions) also clear this bit.
2451 *
2452 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2453 */
2454 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2455 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2456
2457 /*
2458 * Update the VM-exit reason and Exit qualification.
2459 * Other VMCS read-only data fields are expected to be updated by the caller already.
2460 */
2461 pVmcs->u32RoExitReason = uExitReason;
2462 pVmcs->u64RoExitQual.u = u64ExitQual;
2463
2464 Log2(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 eflags=%#RX32\n", uExitReason,
2465 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2466 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.eflags.u32));
2467
2468 /*
2469 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2470 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2471 */
2472 {
2473 uint8_t uVector;
2474 uint32_t fFlags;
2475 uint32_t uErrCode;
2476 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2477 if (fInEventDelivery)
2478 {
2479 /*
2480 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2481 * caused by a triple-fault or the original event results in a double-fault that
2482 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2483 * original event information into the IDT-vectoring information fields.
2484 *
2485 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2486 */
2487 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2488 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2489 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2490 {
2491 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2492 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2493 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2494 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2495 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2496 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2497 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2498 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2499 Log2(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2500 pVCpu->cpum.GstCtx.cr2));
2501 }
2502 }
2503 }
2504
2505 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2506 Assert(pVmcs->u64RoIoRcx.u == 0);
2507 Assert(pVmcs->u64RoIoRsi.u == 0);
2508 Assert(pVmcs->u64RoIoRdi.u == 0);
2509 Assert(pVmcs->u64RoIoRip.u == 0);
2510
2511 /*
2512 * Save the guest state back into the VMCS.
2513 * We only need to save the state when the VM-entry was successful.
2514 */
2515 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2516 if (!fVmentryFailed)
2517 {
2518 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2519 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2520 {
2521 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2522 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2523 }
2524
2525 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2526 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2527
2528 /*
2529 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2530 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2531 *
2532 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2533 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2534 * as guest-CPU state would not been modified. Hence for now, we do this only when
2535 * the VM-entry succeeded.
2536 */
2537 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2538 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2539 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2540 {
2541 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2542 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2543 else
2544 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2545 }
2546
2547 /*
2548 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2549 * occurs in enclave mode/SMM which we don't support yet.
2550 *
2551 * If we ever add support for it, we can pass just the lower bits to the functions
2552 * below, till then an assert should suffice.
2553 */
2554 Assert(!RT_HI_U16(uExitReason));
2555
2556 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2557 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2558 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2559 if (RT_SUCCESS(rc))
2560 { /* likely */ }
2561 else
2562 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2563
2564 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2565 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2566 }
2567 else
2568 {
2569 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2570 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2571 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2572 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2573 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2574 }
2575
2576 /*
2577 * Stop any running VMX-preemption timer if necessary.
2578 */
2579 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2580 CPUMStopGuestVmxPremptTimer(pVCpu);
2581
2582 /*
2583 * Clear any pending VMX nested-guest force-flags.
2584 * These force-flags have no effect on (outer) guest execution and will
2585 * be re-evaluated and setup on the next nested-guest VM-entry.
2586 */
2587 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2588
2589 /*
2590 * We're no longer in nested-guest execution mode.
2591 *
2592 * It is important to do this prior to loading the host state because
2593 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2594 * second-level address translation while switching to host CR3.
2595 */
2596 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2597
2598 /* Restore the host (outer guest) state. */
2599 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2600 if (RT_SUCCESS(rcStrict))
2601 {
2602 Assert(rcStrict == VINF_SUCCESS);
2603 rcStrict = VINF_VMX_VMEXIT;
2604 }
2605 else
2606 Log(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2607
2608 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2609 {
2610 /* Notify HM that the current VMCS fields have been modified. */
2611 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2612
2613 /* Notify HM that we've completed the VM-exit. */
2614 HMNotifyVmxNstGstVmexit(pVCpu);
2615 }
2616
2617# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2618 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2619 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2620 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2621 if (rcSched != VINF_SUCCESS)
2622 iemSetPassUpStatus(pVCpu, rcSched);
2623# endif
2624 return rcStrict;
2625# endif
2626}
2627
2628
2629/**
2630 * VMX VM-exit handler for VM-exits due to instruction execution.
2631 *
2632 * This is intended for instructions where the caller provides all the relevant
2633 * VM-exit information.
2634 *
2635 * @returns Strict VBox status code.
2636 * @param pVCpu The cross context virtual CPU structure.
2637 * @param pExitInfo Pointer to the VM-exit information.
2638 */
2639static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2640{
2641 /*
2642 * For instructions where any of the following fields are not applicable:
2643 * - Exit qualification must be cleared.
2644 * - VM-exit instruction info. is undefined.
2645 * - Guest-linear address is undefined.
2646 * - Guest-physical address is undefined.
2647 *
2648 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2649 * instruction execution. For VM-exits that are not due to instruction execution this
2650 * field is undefined.
2651 *
2652 * In our implementation in IEM, all undefined fields are generally cleared. However,
2653 * if the caller supplies information (from say the physical CPU directly) it is
2654 * then possible that the undefined fields are not cleared.
2655 *
2656 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2657 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2658 */
2659 Assert(pExitInfo);
2660 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2661 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2662 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2663
2664 /* Update all the relevant fields from the VM-exit instruction information struct. */
2665 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2666 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2667 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2668 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2669
2670 /* Perform the VM-exit. */
2671 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2672}
2673
2674
2675/**
2676 * VMX VM-exit handler for VM-exits due to instruction execution.
2677 *
2678 * This is intended for instructions that only provide the VM-exit instruction
2679 * length.
2680 *
2681 * @param pVCpu The cross context virtual CPU structure.
2682 * @param uExitReason The VM-exit reason.
2683 * @param cbInstr The instruction length in bytes.
2684 */
2685VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2686{
2687 VMXVEXITINFO ExitInfo;
2688 RT_ZERO(ExitInfo);
2689 ExitInfo.uReason = uExitReason;
2690 ExitInfo.cbInstr = cbInstr;
2691
2692#ifdef VBOX_STRICT
2693 /*
2694 * To prevent us from shooting ourselves in the foot.
2695 * The follow instructions should convey more than just the instruction length.
2696 */
2697 switch (uExitReason)
2698 {
2699 case VMX_EXIT_INVEPT:
2700 case VMX_EXIT_INVPCID:
2701 case VMX_EXIT_INVVPID:
2702 case VMX_EXIT_LDTR_TR_ACCESS:
2703 case VMX_EXIT_GDTR_IDTR_ACCESS:
2704 case VMX_EXIT_VMCLEAR:
2705 case VMX_EXIT_VMPTRLD:
2706 case VMX_EXIT_VMPTRST:
2707 case VMX_EXIT_VMREAD:
2708 case VMX_EXIT_VMWRITE:
2709 case VMX_EXIT_VMXON:
2710 case VMX_EXIT_XRSTORS:
2711 case VMX_EXIT_XSAVES:
2712 case VMX_EXIT_RDRAND:
2713 case VMX_EXIT_RDSEED:
2714 case VMX_EXIT_IO_INSTR:
2715 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2716 break;
2717 }
2718#endif
2719
2720 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2721}
2722
2723
2724/**
2725 * Interface for HM and EM to emulate VM-exit due to a triple-fault.
2726 *
2727 * @returns Strict VBox status code.
2728 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2729 * @thread EMT(pVCpu)
2730 */
2731VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2732{
2733 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2734 Assert(!pVCpu->iem.s.cActiveMappings);
2735 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2736}
2737
2738
2739/**
2740 * Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2741 *
2742 * @returns Strict VBox status code.
2743 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2744 * @param uVector The SIPI vector.
2745 * @thread EMT(pVCpu)
2746 */
2747VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2748{
2749 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2750 Assert(!pVCpu->iem.s.cActiveMappings);
2751 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2752}
2753
2754
2755/**
2756 * Interface for HM and EM to emulate a VM-exit.
2757 *
2758 * If a specialized version of a VM-exit handler exists, that must be used instead.
2759 *
2760 * @returns Strict VBox status code.
2761 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2762 * @param uExitReason The VM-exit reason.
2763 * @param u64ExitQual The Exit qualification.
2764 * @thread EMT(pVCpu)
2765 */
2766VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2767{
2768 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2769 Assert(!pVCpu->iem.s.cActiveMappings);
2770 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2771}
2772
2773
2774/**
2775 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2776 *
2777 * This is meant to be used for those instructions that VMX provides additional
2778 * decoding information beyond just the instruction length!
2779 *
2780 * @returns Strict VBox status code.
2781 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2782 * @param pExitInfo Pointer to the VM-exit information.
2783 * @thread EMT(pVCpu)
2784 */
2785VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2786{
2787 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2788 Assert(!pVCpu->iem.s.cActiveMappings);
2789 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2790}
2791
2792
2793/**
2794 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2795 *
2796 * This is meant to be used for those instructions that VMX provides only the
2797 * instruction length.
2798 *
2799 * @returns Strict VBox status code.
2800 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2801 * @param pExitInfo Pointer to the VM-exit information.
2802 * @param cbInstr The instruction length in bytes.
2803 * @thread EMT(pVCpu)
2804 */
2805VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2806{
2807 VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2808 Assert(!pVCpu->iem.s.cActiveMappings);
2809 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2810}
2811
2812
2813/**
2814 * VMX VM-exit handler for VM-exits due to instruction execution.
2815 *
2816 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2817 * instruction information and Exit qualification fields.
2818 *
2819 * @param pVCpu The cross context virtual CPU structure.
2820 * @param uExitReason The VM-exit reason.
2821 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2822 * @param cbInstr The instruction length in bytes.
2823 *
2824 * @remarks Do not use this for INS/OUTS instruction.
2825 */
2826VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2827{
2828 VMXVEXITINFO ExitInfo;
2829 RT_ZERO(ExitInfo);
2830 ExitInfo.uReason = uExitReason;
2831 ExitInfo.cbInstr = cbInstr;
2832
2833#ifdef VBOX_STRICT
2834 /*
2835 * To prevent us from shooting ourselves in the foot.
2836 * The follow instructions convey specific info that require using their respective handlers.
2837 */
2838 switch (uExitReason)
2839 {
2840 case VMX_EXIT_INVEPT:
2841 case VMX_EXIT_INVPCID:
2842 case VMX_EXIT_INVVPID:
2843 case VMX_EXIT_LDTR_TR_ACCESS:
2844 case VMX_EXIT_GDTR_IDTR_ACCESS:
2845 case VMX_EXIT_VMCLEAR:
2846 case VMX_EXIT_VMPTRLD:
2847 case VMX_EXIT_VMPTRST:
2848 case VMX_EXIT_VMREAD:
2849 case VMX_EXIT_VMWRITE:
2850 case VMX_EXIT_VMXON:
2851 case VMX_EXIT_XRSTORS:
2852 case VMX_EXIT_XSAVES:
2853 case VMX_EXIT_RDRAND:
2854 case VMX_EXIT_RDSEED:
2855 break;
2856 default:
2857 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2858 break;
2859 }
2860#endif
2861
2862 /*
2863 * Update the Exit qualification field with displacement bytes.
2864 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2865 */
2866 /* Construct the VM-exit instruction information. */
2867 RTGCPTR GCPtrDisp;
2868 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2869
2870 /* Update the VM-exit instruction information. */
2871 ExitInfo.InstrInfo.u = uInstrInfo;
2872
2873 /* Update the Exit qualification. */
2874 ExitInfo.u64Qual = GCPtrDisp;
2875
2876 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2877}
2878
2879
2880/**
2881 * VMX VM-exit handler for VM-exits due to INVLPG.
2882 *
2883 * @returns Strict VBox status code.
2884 * @param pVCpu The cross context virtual CPU structure.
2885 * @param GCPtrPage The guest-linear address of the page being invalidated.
2886 * @param cbInstr The instruction length in bytes.
2887 */
2888VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2889{
2890 VMXVEXITINFO ExitInfo;
2891 RT_ZERO(ExitInfo);
2892 ExitInfo.uReason = VMX_EXIT_INVLPG;
2893 ExitInfo.cbInstr = cbInstr;
2894 ExitInfo.u64Qual = GCPtrPage;
2895 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2896
2897 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2898}
2899
2900
2901/**
2902 * VMX VM-exit handler for VM-exits due to LMSW.
2903 *
2904 * @returns Strict VBox status code.
2905 * @param pVCpu The cross context virtual CPU structure.
2906 * @param uGuestCr0 The current guest CR0.
2907 * @param pu16NewMsw The machine-status word specified in LMSW's source
2908 * operand. This will be updated depending on the VMX
2909 * guest/host CR0 mask if LMSW is not intercepted.
2910 * @param GCPtrEffDst The guest-linear address of the source operand in case
2911 * of a memory operand. For register operand, pass
2912 * NIL_RTGCPTR.
2913 * @param cbInstr The instruction length in bytes.
2914 */
2915VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2916 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2917{
2918 Assert(pu16NewMsw);
2919
2920 uint16_t const uNewMsw = *pu16NewMsw;
2921 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2922 {
2923 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2924
2925 VMXVEXITINFO ExitInfo;
2926 RT_ZERO(ExitInfo);
2927 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2928 ExitInfo.cbInstr = cbInstr;
2929
2930 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2931 if (fMemOperand)
2932 {
2933 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2934 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2935 }
2936
2937 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2938 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2939 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2940 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2941
2942 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2943 }
2944
2945 /*
2946 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2947 * CR0 guest/host mask must be left unmodified.
2948 *
2949 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2950 */
2951 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2952 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2953 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2954
2955 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2956}
2957
2958
2959/**
2960 * VMX VM-exit handler for VM-exits due to CLTS.
2961 *
2962 * @returns Strict VBox status code.
2963 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2964 * VM-exit but must not modify the guest CR0.TS bit.
2965 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2966 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2967 * CR0 fixed bits in VMX operation).
2968 * @param pVCpu The cross context virtual CPU structure.
2969 * @param cbInstr The instruction length in bytes.
2970 */
2971VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2972{
2973 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2974 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2975
2976 /*
2977 * If CR0.TS is owned by the host:
2978 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2979 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2980 * CLTS instruction completes without clearing CR0.TS.
2981 *
2982 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2983 */
2984 if (fGstHostMask & X86_CR0_TS)
2985 {
2986 if (fReadShadow & X86_CR0_TS)
2987 {
2988 Log2(("clts: Guest intercept -> VM-exit\n"));
2989
2990 VMXVEXITINFO ExitInfo;
2991 RT_ZERO(ExitInfo);
2992 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2993 ExitInfo.cbInstr = cbInstr;
2994 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2995 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2996 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2997 }
2998
2999 return VINF_VMX_MODIFIES_BEHAVIOR;
3000 }
3001
3002 /*
3003 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3004 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3005 */
3006 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3007}
3008
3009
3010/**
3011 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3012 * (CR0/CR4 write).
3013 *
3014 * @returns Strict VBox status code.
3015 * @param pVCpu The cross context virtual CPU structure.
3016 * @param iCrReg The control register (either CR0 or CR4).
3017 * @param uGuestCrX The current guest CR0/CR4.
3018 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
3019 * VM-exit is caused.
3020 * @param iGReg The general register from which the CR0/CR4 value is being
3021 * loaded.
3022 * @param cbInstr The instruction length in bytes.
3023 */
3024VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
3025 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3026{
3027 Assert(puNewCrX);
3028 Assert(iCrReg == 0 || iCrReg == 4);
3029 Assert(iGReg < X86_GREG_COUNT);
3030
3031 uint64_t const uNewCrX = *puNewCrX;
3032 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3033 {
3034 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3035
3036 VMXVEXITINFO ExitInfo;
3037 RT_ZERO(ExitInfo);
3038 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3039 ExitInfo.cbInstr = cbInstr;
3040 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3041 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3042 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3043 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3044 }
3045
3046 /*
3047 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3048 * must not be modified the instruction.
3049 *
3050 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3051 */
3052 uint64_t uGuestCrX;
3053 uint64_t fGstHostMask;
3054 if (iCrReg == 0)
3055 {
3056 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3057 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3058 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3059 }
3060 else
3061 {
3062 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3063 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3064 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3065 }
3066
3067 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3068 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3069}
3070
3071
3072/**
3073 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3074 *
3075 * @returns VBox strict status code.
3076 * @param pVCpu The cross context virtual CPU structure.
3077 * @param iGReg The general register to which the CR3 value is being stored.
3078 * @param cbInstr The instruction length in bytes.
3079 */
3080VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3081{
3082 Assert(iGReg < X86_GREG_COUNT);
3083 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3084
3085 /*
3086 * If the CR3-store exiting control is set, we must cause a VM-exit.
3087 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3088 */
3089 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3090 {
3091 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3092
3093 VMXVEXITINFO ExitInfo;
3094 RT_ZERO(ExitInfo);
3095 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3096 ExitInfo.cbInstr = cbInstr;
3097 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3098 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3099 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3100 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3101 }
3102
3103 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3104}
3105
3106
3107/**
3108 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3109 *
3110 * @returns VBox strict status code.
3111 * @param pVCpu The cross context virtual CPU structure.
3112 * @param uNewCr3 The new CR3 value.
3113 * @param iGReg The general register from which the CR3 value is being
3114 * loaded.
3115 * @param cbInstr The instruction length in bytes.
3116 */
3117VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3118{
3119 Assert(iGReg < X86_GREG_COUNT);
3120
3121 /*
3122 * If the CR3-load exiting control is set and the new CR3 value does not
3123 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3124 *
3125 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3126 */
3127 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3128 {
3129 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3130
3131 VMXVEXITINFO ExitInfo;
3132 RT_ZERO(ExitInfo);
3133 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3134 ExitInfo.cbInstr = cbInstr;
3135 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3136 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3137 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3138 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3139 }
3140
3141 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3142}
3143
3144
3145/**
3146 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3147 *
3148 * @returns VBox strict status code.
3149 * @param pVCpu The cross context virtual CPU structure.
3150 * @param iGReg The general register to which the CR8 value is being stored.
3151 * @param cbInstr The instruction length in bytes.
3152 */
3153VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3154{
3155 Assert(iGReg < X86_GREG_COUNT);
3156
3157 /*
3158 * If the CR8-store exiting control is set, we must cause a VM-exit.
3159 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3160 */
3161 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3162 {
3163 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3164
3165 VMXVEXITINFO ExitInfo;
3166 RT_ZERO(ExitInfo);
3167 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3168 ExitInfo.cbInstr = cbInstr;
3169 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3170 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3171 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3172 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3173 }
3174
3175 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3176}
3177
3178
3179/**
3180 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3181 *
3182 * @returns VBox strict status code.
3183 * @param pVCpu The cross context virtual CPU structure.
3184 * @param iGReg The general register from which the CR8 value is being
3185 * loaded.
3186 * @param cbInstr The instruction length in bytes.
3187 */
3188VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3189{
3190 Assert(iGReg < X86_GREG_COUNT);
3191
3192 /*
3193 * If the CR8-load exiting control is set, we must cause a VM-exit.
3194 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3195 */
3196 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3197 {
3198 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3199
3200 VMXVEXITINFO ExitInfo;
3201 RT_ZERO(ExitInfo);
3202 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3203 ExitInfo.cbInstr = cbInstr;
3204 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3205 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3206 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3207 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3208 }
3209
3210 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3211}
3212
3213
3214/**
3215 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3216 * GReg,DRx' (DRx read).
3217 *
3218 * @returns VBox strict status code.
3219 * @param pVCpu The cross context virtual CPU structure.
3220 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3221 * VMXINSTRID_MOV_FROM_DRX).
3222 * @param iDrReg The debug register being accessed.
3223 * @param iGReg The general register to/from which the DRx value is being
3224 * store/loaded.
3225 * @param cbInstr The instruction length in bytes.
3226 */
3227VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3228 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3229{
3230 Assert(iDrReg <= 7);
3231 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3232 Assert(iGReg < X86_GREG_COUNT);
3233
3234 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3235 {
3236 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3237 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3238 VMXVEXITINFO ExitInfo;
3239 RT_ZERO(ExitInfo);
3240 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3241 ExitInfo.cbInstr = cbInstr;
3242 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3243 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3244 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3245 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3246 }
3247
3248 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3249}
3250
3251
3252/**
3253 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3254 *
3255 * @returns VBox strict status code.
3256 * @param pVCpu The cross context virtual CPU structure.
3257 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3258 * VMXINSTRID_IO_OUT).
3259 * @param u16Port The I/O port being accessed.
3260 * @param fImm Whether the I/O port was encoded using an immediate operand
3261 * or the implicit DX register.
3262 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3263 * @param cbInstr The instruction length in bytes.
3264 */
3265VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3266 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3267{
3268 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3269 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3270
3271 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3272 if (fIntercept)
3273 {
3274 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3275 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3276 VMXVEXITINFO ExitInfo;
3277 RT_ZERO(ExitInfo);
3278 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3279 ExitInfo.cbInstr = cbInstr;
3280 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3281 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3282 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3283 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3284 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3285 }
3286
3287 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3288}
3289
3290
3291/**
3292 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3293 *
3294 * @returns VBox strict status code.
3295 * @param pVCpu The cross context virtual CPU structure.
3296 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3297 * VMXINSTRID_IO_OUTS).
3298 * @param u16Port The I/O port being accessed.
3299 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3300 * @param fRep Whether the instruction has a REP prefix or not.
3301 * @param ExitInstrInfo The VM-exit instruction info. field.
3302 * @param cbInstr The instruction length in bytes.
3303 */
3304VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3305 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3306{
3307 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3308 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3309 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3310 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3311 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3312
3313 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3314 if (fIntercept)
3315 {
3316 /*
3317 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3318 */
3319 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3320 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3321 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3322 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3323 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3324
3325 uint32_t uDirection;
3326 uint64_t uGuestLinearAddr;
3327 if (uInstrId == VMXINSTRID_IO_INS)
3328 {
3329 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3330 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3331 }
3332 else
3333 {
3334 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3335 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3336 }
3337
3338 /*
3339 * If the segment is unusable, the guest-linear address in undefined.
3340 * We shall clear it for consistency.
3341 *
3342 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3343 */
3344 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3345 uGuestLinearAddr = 0;
3346
3347 VMXVEXITINFO ExitInfo;
3348 RT_ZERO(ExitInfo);
3349 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3350 ExitInfo.cbInstr = cbInstr;
3351 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3352 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3353 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3354 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3355 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3356 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3357 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3358 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3359 ExitInfo.InstrInfo = ExitInstrInfo;
3360 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3361 }
3362
3363 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3364}
3365
3366
3367/**
3368 * VMX VM-exit handler for VM-exits due to MWAIT.
3369 *
3370 * @returns VBox strict status code.
3371 * @param pVCpu The cross context virtual CPU structure.
3372 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3373 * @param cbInstr The instruction length in bytes.
3374 */
3375VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3376{
3377 VMXVEXITINFO ExitInfo;
3378 RT_ZERO(ExitInfo);
3379 ExitInfo.uReason = VMX_EXIT_MWAIT;
3380 ExitInfo.cbInstr = cbInstr;
3381 ExitInfo.u64Qual = fMonitorHwArmed;
3382 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3383}
3384
3385
3386/**
3387 * VMX VM-exit handler for VM-exits due to PAUSE.
3388 *
3389 * @returns VBox strict status code.
3390 * @param pVCpu The cross context virtual CPU structure.
3391 * @param cbInstr The instruction length in bytes.
3392 */
3393static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3394{
3395 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3396
3397 /*
3398 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3399 * "PAUSE-loop exiting" control.
3400 *
3401 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3402 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3403 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3404 * a VM-exit.
3405 *
3406 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3407 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3408 */
3409 bool fIntercept = false;
3410 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3411 fIntercept = true;
3412 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3413 && pVCpu->iem.s.uCpl == 0)
3414 {
3415 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3416
3417 /*
3418 * A previous-PAUSE-tick value of 0 is used to identify the first time
3419 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3420 * consider this to be the first execution of PAUSE in a loop according
3421 * to the Intel.
3422 *
3423 * All subsequent records for the previous-PAUSE-tick we ensure that it
3424 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3425 */
3426 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3427 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3428 uint64_t const uTick = TMCpuTickGet(pVCpu);
3429 uint32_t const uPleGap = pVmcs->u32PleGap;
3430 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3431 if ( *puPrevPauseTick == 0
3432 || uTick - *puPrevPauseTick > uPleGap)
3433 *puFirstPauseLoopTick = uTick;
3434 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3435 fIntercept = true;
3436
3437 *puPrevPauseTick = uTick | 1;
3438 }
3439
3440 if (fIntercept)
3441 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3442
3443 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3444}
3445
3446
3447/**
3448 * VMX VM-exit handler for VM-exits due to task switches.
3449 *
3450 * @returns VBox strict status code.
3451 * @param pVCpu The cross context virtual CPU structure.
3452 * @param enmTaskSwitch The cause of the task switch.
3453 * @param SelNewTss The selector of the new TSS.
3454 * @param cbInstr The instruction length in bytes.
3455 */
3456VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3457{
3458 /*
3459 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3460 *
3461 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3462 * instruction or delivery of the exception generated by one of these instructions
3463 * lead to a task switch through a task gate in the IDT, we need to provide the
3464 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3465 * leaves the VM-exit instruction length field undefined.
3466 *
3467 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3468 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3469 */
3470 Assert(cbInstr <= 15);
3471
3472 uint8_t uType;
3473 switch (enmTaskSwitch)
3474 {
3475 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3476 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3477 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3478 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3479 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3480 }
3481
3482 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3483 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3484 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3485 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3486}
3487
3488
3489/**
3490 * VMX VM-exit handler for trap-like VM-exits.
3491 *
3492 * @returns VBox strict status code.
3493 * @param pVCpu The cross context virtual CPU structure.
3494 * @param pExitInfo Pointer to the VM-exit information.
3495 * @param pExitEventInfo Pointer to the VM-exit event information.
3496 */
3497static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3498{
3499 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3500 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3501 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3502}
3503
3504
3505/**
3506 * Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3507 * Virtualized-EOI, TPR-below threshold).
3508 *
3509 * @returns Strict VBox status code.
3510 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3511 * @param pExitInfo Pointer to the VM-exit information.
3512 * @thread EMT(pVCpu)
3513 */
3514VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3515{
3516 Assert(pExitInfo);
3517 VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3518 Assert(!pVCpu->iem.s.cActiveMappings);
3519 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3520}
3521
3522
3523/**
3524 * VMX VM-exit handler for VM-exits due to task switches.
3525 *
3526 * This is intended for task switches where the caller provides all the relevant
3527 * VM-exit information.
3528 *
3529 * @returns VBox strict status code.
3530 * @param pVCpu The cross context virtual CPU structure.
3531 * @param pExitInfo Pointer to the VM-exit information.
3532 * @param pExitEventInfo Pointer to the VM-exit event information.
3533 */
3534static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3535 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3536{
3537 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3538 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3539 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3540 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3541 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3542}
3543
3544
3545/**
3546 * Interface for HM and EM to emulate a VM-exit due to a task switch.
3547 *
3548 * @returns Strict VBox status code.
3549 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3550 * @param pExitInfo Pointer to the VM-exit information.
3551 * @param pExitEventInfo Pointer to the VM-exit event information.
3552 * @thread EMT(pVCpu)
3553 */
3554VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3555{
3556 Assert(pExitInfo);
3557 Assert(pExitEventInfo);
3558 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3559 VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3560 Assert(!pVCpu->iem.s.cActiveMappings);
3561 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3562}
3563
3564
3565/**
3566 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3567 *
3568 * @returns VBox strict status code.
3569 * @param pVCpu The cross context virtual CPU structure.
3570 */
3571VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3572{
3573 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3574 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3575
3576 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3577 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3578
3579 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3580 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3581 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3582
3583 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3584 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3585}
3586
3587
3588/**
3589 * Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3590 *
3591 * @returns Strict VBox status code.
3592 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3593 * @thread EMT(pVCpu)
3594 */
3595VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3596{
3597 VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3598 Assert(!pVCpu->iem.s.cActiveMappings);
3599 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3600}
3601
3602
3603/**
3604 * VMX VM-exit handler for VM-exits due to external interrupts.
3605 *
3606 * @returns VBox strict status code.
3607 * @param pVCpu The cross context virtual CPU structure.
3608 * @param uVector The external interrupt vector (pass 0 if the interrupt
3609 * is still pending since we typically won't know the
3610 * vector).
3611 * @param fIntPending Whether the external interrupt is pending or
3612 * acknowledged in the interrupt controller.
3613 */
3614static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3615{
3616 Assert(!fIntPending || uVector == 0);
3617
3618 /* The VM-exit is subject to "External interrupt exiting" being set. */
3619 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3620 {
3621 if (fIntPending)
3622 {
3623 /*
3624 * If the interrupt is pending and we don't need to acknowledge the
3625 * interrupt on VM-exit, cause the VM-exit immediately.
3626 *
3627 * See Intel spec 25.2 "Other Causes Of VM Exits".
3628 */
3629 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3630 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3631
3632 /*
3633 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3634 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3635 * acknowledged that the interrupt has been consumed. Callers would have to call
3636 * us again after getting the vector (and ofc, with fIntPending with false).
3637 */
3638 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3639 }
3640
3641 /*
3642 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3643 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3644 * all set, we need to record the vector of the external interrupt in the
3645 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3646 *
3647 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3648 */
3649 uint32_t uExitIntInfo;
3650 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3651 {
3652 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3653 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3654 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3655 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3656 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3657 }
3658 else
3659 uExitIntInfo = 0;
3660 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3661
3662 /*
3663 * Cause the VM-exit whether or not the vector has been stored
3664 * in the VM-exit interruption-information field.
3665 */
3666 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3667 }
3668
3669 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3670}
3671
3672
3673/**
3674 * Interface for HM and EM to emulate VM-exit due to external interrupts.
3675 *
3676 * @returns Strict VBox status code.
3677 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3678 * @param uVector The external interrupt vector (pass 0 if the external
3679 * interrupt is still pending).
3680 * @param fIntPending Whether the external interrupt is pending or
3681 * acknowdledged in the interrupt controller.
3682 * @thread EMT(pVCpu)
3683 */
3684VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3685{
3686 VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3687 Assert(!pVCpu->iem.s.cActiveMappings);
3688 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3689}
3690
3691
3692/**
3693 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3694 * an event.
3695 *
3696 * @returns VBox strict status code.
3697 * @param pVCpu The cross context virtual CPU structure.
3698 */
3699VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3700{
3701 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3702 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3703 {
3704 /*
3705 * The NMI-unblocking due to IRET field need not be set for double faults.
3706 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3707 */
3708 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3709 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3710 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3711 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3712 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3713 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3714 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3715 }
3716
3717 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3718}
3719
3720
3721/**
3722 * VMX VM-exit handler for VM-exit due to delivery of an events.
3723 *
3724 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3725 * all the relevant VM-exit information.
3726 *
3727 * @returns VBox strict status code.
3728 * @param pVCpu The cross context virtual CPU structure.
3729 * @param pExitInfo Pointer to the VM-exit information.
3730 * @param pExitEventInfo Pointer to the VM-exit event information.
3731 */
3732static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3733{
3734 Assert(pExitInfo);
3735 Assert(pExitEventInfo);
3736 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3737 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3738
3739 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3740 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3741 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3742 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3743 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3744 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3745}
3746
3747
3748/**
3749 * Interface for HM and EM to emulate VM-exit due to NMIs.
3750 *
3751 * @returns Strict VBox status code.
3752 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3753 * @thread EMT(pVCpu)
3754 */
3755VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3756{
3757 VMXVEXITINFO ExitInfo;
3758 RT_ZERO(ExitInfo);
3759 ExitInfo.uReason = VMX_EXIT_XCPT_OR_NMI;
3760
3761 VMXVEXITEVENTINFO ExitEventInfo;
3762 RT_ZERO(ExitEventInfo);
3763 ExitEventInfo.uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3764 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI)
3765 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI);
3766
3767 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3768 Assert(!pVCpu->iem.s.cActiveMappings);
3769 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3770}
3771
3772
3773/**
3774 * Interface for HM and EM to emulate VM-exit due to exceptions.
3775 *
3776 * Exception includes NMIs, software exceptions (those generated by INT3 or
3777 * INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3778 *
3779 * @returns Strict VBox status code.
3780 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3781 * @param pExitInfo Pointer to the VM-exit information.
3782 * @param pExitEventInfo Pointer to the VM-exit event information.
3783 * @thread EMT(pVCpu)
3784 */
3785VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3786{
3787 Assert(pExitInfo);
3788 Assert(pExitEventInfo);
3789 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3790 Assert(!pVCpu->iem.s.cActiveMappings);
3791 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3792}
3793
3794
3795/**
3796 * VMX VM-exit handler for VM-exits due to delivery of an event.
3797 *
3798 * @returns VBox strict status code.
3799 * @param pVCpu The cross context virtual CPU structure.
3800 * @param uVector The interrupt / exception vector.
3801 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3802 * @param uErrCode The error code associated with the event.
3803 * @param uCr2 The CR2 value in case of a \#PF exception.
3804 * @param cbInstr The instruction length in bytes.
3805 */
3806VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3807 uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3808{
3809 /*
3810 * If the event is being injected as part of VM-entry, it is -not- subject to event
3811 * intercepts in the nested-guest. However, secondary exceptions that occur during
3812 * injection of any event -are- subject to event interception.
3813 *
3814 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3815 */
3816 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3817 {
3818 /*
3819 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3820 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3821 *
3822 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3823 */
3824 if ( uVector == X86_XCPT_NMI
3825 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3826 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3827 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3828 else
3829 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3830
3831 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3832 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3833 }
3834
3835 /*
3836 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3837 * If not, the caller will continue delivery of the external interrupt as it would
3838 * normally. The interrupt is no longer pending in the interrupt controller at this
3839 * point.
3840 */
3841 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3842 {
3843 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3844 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3845 }
3846
3847 /*
3848 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3849 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3850 * interrupts.
3851 */
3852 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3853 bool fIntercept;
3854 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3855 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3856 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3857 else
3858 {
3859 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3860 fIntercept = false;
3861 }
3862
3863 /*
3864 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3865 * relevant VM-exit information and cause the VM-exit.
3866 */
3867 if (fIntercept)
3868 {
3869 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3870
3871 /* Construct the rest of the event related information fields and cause the VM-exit. */
3872 uint64_t u64ExitQual;
3873 if (uVector == X86_XCPT_PF)
3874 {
3875 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3876 u64ExitQual = uCr2;
3877 }
3878 else if (uVector == X86_XCPT_DB)
3879 {
3880 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3881 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3882 }
3883 else
3884 u64ExitQual = 0;
3885
3886 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3887 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3888 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3889 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3890 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3891 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3892 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3893 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3894 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3895 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3896
3897 /*
3898 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3899 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3900 * length.
3901 */
3902 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3903 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3904 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3905 else
3906 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3907
3908 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3909 }
3910
3911 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3912}
3913
3914
3915/**
3916 * VMX VM-exit handler for EPT misconfiguration.
3917 *
3918 * @param pVCpu The cross context virtual CPU structure.
3919 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3920 * This need not be page aligned (e.g. nested-guest in real
3921 * mode).
3922 */
3923static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3924{
3925 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3926 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3927}
3928
3929
3930/**
3931 * VMX VM-exit handler for EPT misconfiguration.
3932 *
3933 * This is intended for EPT misconfigurations where the caller provides all the
3934 * relevant VM-exit information.
3935 *
3936 * @param pVCpu The cross context virtual CPU structure.
3937 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3938 * This need not be page aligned (e.g. nested-guest in real
3939 * mode).
3940 * @param pExitEventInfo Pointer to the VM-exit event information.
3941 */
3942static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3943{
3944 Assert(pExitEventInfo);
3945 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3946 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3947 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3948 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3949 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3950}
3951
3952
3953/**
3954 * Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3955 *
3956 * @returns Strict VBox status code.
3957 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3958 * @param GCPhysAddr The nested-guest physical address causing the EPT
3959 * misconfiguration.
3960 * @param pExitEventInfo Pointer to the VM-exit event information.
3961 * @thread EMT(pVCpu)
3962 */
3963VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3964{
3965 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
3966
3967 iemInitExec(pVCpu, false /*fBypassHandlers*/);
3968 VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
3969 Assert(!pVCpu->iem.s.cActiveMappings);
3970 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
3971}
3972
3973
3974/**
3975 * VMX VM-exit handler for EPT violation.
3976 *
3977 * @param pVCpu The cross context virtual CPU structure.
3978 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3979 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3980 * @param fEptAccess The EPT paging structure bits.
3981 * @param GCPhysAddr The physical address causing the EPT violation. This
3982 * need not be page aligned (e.g. nested-guest in real
3983 * mode).
3984 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3985 * EPT violation. If @c false, GCPtrAddr must be 0.
3986 * @param GCPtrAddr The linear address causing the EPT violation.
3987 * @param cbInstr The VM-exit instruction length.
3988 */
3989static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
3990 uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
3991 uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
3992{
3993 /*
3994 * If the linear address isn't valid (can happen when loading PDPTEs
3995 * as part of MOV CR execution) the linear address field is undefined.
3996 * While we can leave it this way, it's preferrable to zero it for consistency.
3997 */
3998 Assert(fIsLinearAddrValid || GCPtrAddr == 0);
3999
4000 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
4001 bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
4002
4003 uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_READ;
4004 uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_WRITE;
4005 uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_EXEC;
4006 bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
4007 bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) | fSupportsAccessDirty;
4008 bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
4009 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
4010 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
4011 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
4012 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4013 bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
4014
4015 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
4016 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
4017 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
4018 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
4019 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
4020 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
4021 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
4022 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
4023 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
4024
4025#ifdef VBOX_STRICT
4026 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
4027 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
4028 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
4029 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
4030 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
4031 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
4032#endif
4033
4034 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
4035 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
4036 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4037
4038 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
4039}
4040
4041
4042/**
4043 * VMX VM-exit handler for EPT violation.
4044 *
4045 * This is intended for EPT violations where the caller provides all the
4046 * relevant VM-exit information.
4047 *
4048 * @returns VBox strict status code.
4049 * @param pVCpu The cross context virtual CPU structure.
4050 * @param pExitInfo Pointer to the VM-exit information.
4051 * @param pExitEventInfo Pointer to the VM-exit event information.
4052 */
4053static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4054 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4055{
4056 Assert(pExitInfo);
4057 Assert(pExitEventInfo);
4058 Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4059 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4060
4061 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4062 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4063
4064 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4065 if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4066 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4067 else
4068 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4069 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4070 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4071}
4072
4073
4074/**
4075 * Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4076 *
4077 * @returns Strict VBox status code.
4078 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4079 * @param pExitInfo Pointer to the VM-exit information.
4080 * @param pExitEventInfo Pointer to the VM-exit event information.
4081 * @thread EMT(pVCpu)
4082 */
4083VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4084 PCVMXVEXITEVENTINFO pExitEventInfo)
4085{
4086 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
4087
4088 iemInitExec(pVCpu, false /*fBypassHandlers*/);
4089 VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4090 Assert(!pVCpu->iem.s.cActiveMappings);
4091 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4092}
4093
4094
4095/**
4096 * VMX VM-exit handler for EPT-induced VM-exits.
4097 *
4098 * @param pVCpu The cross context virtual CPU structure.
4099 * @param pWalk The page walk info.
4100 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4101 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4102 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4103 * applicable.
4104 */
4105VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4106{
4107 Assert(pWalk->fIsSlat);
4108 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4109 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4110 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4111
4112 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4113 {
4114 Log(("EptViolation: cs:rip=%x:%#RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4115 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4116 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4117 pWalk->GCPtr, cbInstr);
4118 }
4119
4120 Log(("EptMisconfig: cs:rip=%x:%#RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4121 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4122 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4123}
4124
4125
4126/**
4127 * VMX VM-exit handler for APIC accesses.
4128 *
4129 * @param pVCpu The cross context virtual CPU structure.
4130 * @param offAccess The offset of the register being accessed.
4131 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4132 */
4133static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4134{
4135 VMXAPICACCESS enmAccess;
4136 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4137 if (fInEventDelivery)
4138 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4139 else if ((fAccess & (IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4140 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4141 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4142 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4143 else
4144 enmAccess = VMXAPICACCESS_LINEAR_READ;
4145
4146 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4147 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4148 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4149}
4150
4151
4152/**
4153 * VMX VM-exit handler for APIC accesses.
4154 *
4155 * This is intended for APIC accesses where the caller provides all the
4156 * relevant VM-exit information.
4157 *
4158 * @returns VBox strict status code.
4159 * @param pVCpu The cross context virtual CPU structure.
4160 * @param pExitInfo Pointer to the VM-exit information.
4161 * @param pExitEventInfo Pointer to the VM-exit event information.
4162 */
4163static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4164 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4165{
4166 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4167 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4168 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4169 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4170 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4171 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4172 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4173 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4174 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4175}
4176
4177
4178/**
4179 * Interface for HM and EM to virtualize memory-mapped APIC accesses.
4180 *
4181 * @returns Strict VBox status code.
4182 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4183 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4184 *
4185 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4186 * @param pExitInfo Pointer to the VM-exit information.
4187 * @param pExitEventInfo Pointer to the VM-exit event information.
4188 * @thread EMT(pVCpu)
4189 */
4190VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4191{
4192 Assert(pExitInfo);
4193 Assert(pExitEventInfo);
4194 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4195 Assert(!pVCpu->iem.s.cActiveMappings);
4196 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4197}
4198
4199
4200/**
4201 * VMX VM-exit handler for APIC-write VM-exits.
4202 *
4203 * @param pVCpu The cross context virtual CPU structure.
4204 * @param offApic The write to the virtual-APIC page offset that caused this
4205 * VM-exit.
4206 */
4207static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4208{
4209 Assert(offApic < XAPIC_OFF_END + 4);
4210 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4211 offApic &= UINT16_C(0xfff);
4212 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4213}
4214
4215
4216/**
4217 * Clears any pending virtual-APIC write emulation.
4218 *
4219 * @returns The virtual-APIC offset that was written before clearing it.
4220 * @param pVCpu The cross context virtual CPU structure.
4221 */
4222DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4223{
4224 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4225 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4226 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4227 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4228 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4229 return offVirtApicWrite;
4230}
4231
4232
4233/**
4234 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4235 *
4236 * @returns The register from the virtual-APIC page.
4237 * @param pVCpu The cross context virtual CPU structure.
4238 * @param offReg The offset of the register being read.
4239 */
4240uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4241{
4242 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4243
4244 uint32_t uReg = 0;
4245 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4246 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4247 AssertMsgStmt(RT_SUCCESS(rc),
4248 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4249 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4250 uReg = 0);
4251 return uReg;
4252}
4253
4254
4255/**
4256 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4257 *
4258 * @returns The register from the virtual-APIC page.
4259 * @param pVCpu The cross context virtual CPU structure.
4260 * @param offReg The offset of the register being read.
4261 */
4262static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4263{
4264 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4265
4266 uint64_t uReg = 0;
4267 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4268 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4269 AssertMsgStmt(RT_SUCCESS(rc),
4270 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4271 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4272 uReg = 0);
4273 return uReg;
4274}
4275
4276
4277/**
4278 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4279 *
4280 * @param pVCpu The cross context virtual CPU structure.
4281 * @param offReg The offset of the register being written.
4282 * @param uReg The register value to write.
4283 */
4284void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4285{
4286 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4287
4288 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4289 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4290 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4291 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4292}
4293
4294
4295/**
4296 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4297 *
4298 * @param pVCpu The cross context virtual CPU structure.
4299 * @param offReg The offset of the register being written.
4300 * @param uReg The register value to write.
4301 */
4302static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4303{
4304 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4305
4306 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4307 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4308 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4309 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4310}
4311
4312
4313/**
4314 * Sets the vector in a virtual-APIC 256-bit sparse register.
4315 *
4316 * @param pVCpu The cross context virtual CPU structure.
4317 * @param offReg The offset of the 256-bit spare register.
4318 * @param uVector The vector to set.
4319 *
4320 * @remarks This is based on our APIC device code.
4321 */
4322static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4323{
4324 /* Determine the vector offset within the chunk. */
4325 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4326
4327 /* Read the chunk at the offset. */
4328 uint32_t uReg;
4329 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4330 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4331 if (RT_SUCCESS(rc))
4332 {
4333 /* Modify the chunk. */
4334 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4335 uReg |= RT_BIT(idxVectorBit);
4336
4337 /* Write the chunk. */
4338 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4339 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4340 uVector, offReg, GCPhysVirtApic, rc));
4341 }
4342 else
4343 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4344 uVector, offReg, GCPhysVirtApic, rc));
4345}
4346
4347
4348/**
4349 * Clears the vector in a virtual-APIC 256-bit sparse register.
4350 *
4351 * @param pVCpu The cross context virtual CPU structure.
4352 * @param offReg The offset of the 256-bit spare register.
4353 * @param uVector The vector to clear.
4354 *
4355 * @remarks This is based on our APIC device code.
4356 */
4357static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4358{
4359 /* Determine the vector offset within the chunk. */
4360 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4361
4362 /* Read the chunk at the offset. */
4363 uint32_t uReg;
4364 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4365 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4366 if (RT_SUCCESS(rc))
4367 {
4368 /* Modify the chunk. */
4369 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4370 uReg &= ~RT_BIT(idxVectorBit);
4371
4372 /* Write the chunk. */
4373 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4374 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4375 uVector, offReg, GCPhysVirtApic, rc));
4376 }
4377 else
4378 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4379 uVector, offReg, GCPhysVirtApic, rc));
4380}
4381
4382
4383/**
4384 * Checks if a memory access to the APIC-access page must causes an APIC-access
4385 * VM-exit.
4386 *
4387 * @param pVCpu The cross context virtual CPU structure.
4388 * @param offAccess The offset of the register being accessed.
4389 * @param cbAccess The size of the access in bytes.
4390 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4391 *
4392 * @remarks This must not be used for MSR-based APIC-access page accesses!
4393 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4394 */
4395static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4396{
4397 Assert(cbAccess > 0);
4398 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4399
4400 /*
4401 * We must cause a VM-exit if any of the following are true:
4402 * - TPR shadowing isn't active.
4403 * - The access size exceeds 32-bits.
4404 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4405 *
4406 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4407 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4408 */
4409 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4410 || cbAccess > sizeof(uint32_t)
4411 || ((offAccess + cbAccess - 1) & 0xc)
4412 || offAccess >= XAPIC_OFF_END + 4)
4413 return true;
4414
4415 /*
4416 * If the access is part of an operation where we have already
4417 * virtualized a virtual-APIC write, we must cause a VM-exit.
4418 */
4419 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4420 return true;
4421
4422 /*
4423 * Check write accesses to the APIC-access page that cause VM-exits.
4424 */
4425 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4426 {
4427 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4428 {
4429 /*
4430 * With APIC-register virtualization, a write access to any of the
4431 * following registers are virtualized. Accessing any other register
4432 * causes a VM-exit.
4433 */
4434 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4435 switch (offAlignedAccess)
4436 {
4437 case XAPIC_OFF_ID:
4438 case XAPIC_OFF_TPR:
4439 case XAPIC_OFF_EOI:
4440 case XAPIC_OFF_LDR:
4441 case XAPIC_OFF_DFR:
4442 case XAPIC_OFF_SVR:
4443 case XAPIC_OFF_ESR:
4444 case XAPIC_OFF_ICR_LO:
4445 case XAPIC_OFF_ICR_HI:
4446 case XAPIC_OFF_LVT_TIMER:
4447 case XAPIC_OFF_LVT_THERMAL:
4448 case XAPIC_OFF_LVT_PERF:
4449 case XAPIC_OFF_LVT_LINT0:
4450 case XAPIC_OFF_LVT_LINT1:
4451 case XAPIC_OFF_LVT_ERROR:
4452 case XAPIC_OFF_TIMER_ICR:
4453 case XAPIC_OFF_TIMER_DCR:
4454 break;
4455 default:
4456 return true;
4457 }
4458 }
4459 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4460 {
4461 /*
4462 * With virtual-interrupt delivery, a write access to any of the
4463 * following registers are virtualized. Accessing any other register
4464 * causes a VM-exit.
4465 *
4466 * Note! The specification does not allow writing to offsets in-between
4467 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4468 */
4469 switch (offAccess)
4470 {
4471 case XAPIC_OFF_TPR:
4472 case XAPIC_OFF_EOI:
4473 case XAPIC_OFF_ICR_LO:
4474 break;
4475 default:
4476 return true;
4477 }
4478 }
4479 else
4480 {
4481 /*
4482 * Without APIC-register virtualization or virtual-interrupt delivery,
4483 * only TPR accesses are virtualized.
4484 */
4485 if (offAccess == XAPIC_OFF_TPR)
4486 { /* likely */ }
4487 else
4488 return true;
4489 }
4490 }
4491 else
4492 {
4493 /*
4494 * Check read accesses to the APIC-access page that cause VM-exits.
4495 */
4496 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4497 {
4498 /*
4499 * With APIC-register virtualization, a read access to any of the
4500 * following registers are virtualized. Accessing any other register
4501 * causes a VM-exit.
4502 */
4503 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4504 switch (offAlignedAccess)
4505 {
4506 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4507 case XAPIC_OFF_ID:
4508 case XAPIC_OFF_VERSION:
4509 case XAPIC_OFF_TPR:
4510 case XAPIC_OFF_EOI:
4511 case XAPIC_OFF_LDR:
4512 case XAPIC_OFF_DFR:
4513 case XAPIC_OFF_SVR:
4514 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4515 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4516 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4517 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4518 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4519 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4520 case XAPIC_OFF_ESR:
4521 case XAPIC_OFF_ICR_LO:
4522 case XAPIC_OFF_ICR_HI:
4523 case XAPIC_OFF_LVT_TIMER:
4524 case XAPIC_OFF_LVT_THERMAL:
4525 case XAPIC_OFF_LVT_PERF:
4526 case XAPIC_OFF_LVT_LINT0:
4527 case XAPIC_OFF_LVT_LINT1:
4528 case XAPIC_OFF_LVT_ERROR:
4529 case XAPIC_OFF_TIMER_ICR:
4530 case XAPIC_OFF_TIMER_DCR:
4531 break;
4532 default:
4533 return true;
4534 }
4535 }
4536 else
4537 {
4538 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4539 if (offAccess == XAPIC_OFF_TPR)
4540 { /* likely */ }
4541 else
4542 return true;
4543 }
4544 }
4545
4546 /* The APIC access is virtualized, does not cause a VM-exit. */
4547 return false;
4548}
4549
4550
4551/**
4552 * Virtualizes a memory-based APIC access by certain instructions even though they
4553 * do not use the address to access memory.
4554 *
4555 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4556 * page-faults but do not use the address to access memory.
4557 *
4558 * @param pVCpu The cross context virtual CPU structure.
4559 * @param pGCPhysAccess Pointer to the guest-physical address accessed.
4560 * @param cbAccess The size of the access in bytes.
4561 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4562 */
4563VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4564{
4565 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4566 Assert(pGCPhysAccess);
4567
4568 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4569 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4570 Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4571
4572 if (GCPhysAccess == GCPhysApic)
4573 {
4574 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4575 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4576 if (fIntercept)
4577 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4578
4579 *pGCPhysAccess = GCPhysApic | offAccess;
4580 return VINF_VMX_MODIFIES_BEHAVIOR;
4581 }
4582
4583 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4584}
4585
4586
4587/**
4588 * Virtualizes a memory-based APIC access.
4589 *
4590 * @returns VBox strict status code.
4591 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4592 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4593 *
4594 * @param pVCpu The cross context virtual CPU structure.
4595 * @param offAccess The offset of the register being accessed (within the
4596 * APIC-access page).
4597 * @param cbAccess The size of the access in bytes.
4598 * @param pvData Pointer to the data being written or where to store the data
4599 * being read.
4600 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4601 */
4602static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4603 void *pvData, uint32_t fAccess) RT_NOEXCEPT
4604{
4605 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4606 Assert(pvData);
4607
4608 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4609 if (fIntercept)
4610 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4611
4612 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4613 {
4614 /*
4615 * A write access to the APIC-access page that is virtualized (rather than
4616 * causing a VM-exit) writes data to the virtual-APIC page.
4617 */
4618 uint32_t const u32Data = *(uint32_t *)pvData;
4619 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4620
4621 /*
4622 * Record the currently updated APIC offset, as we need this later for figuring
4623 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4624 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4625 *
4626 * After completion of the current operation, we need to perform TPR virtualization,
4627 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4628 *
4629 * The current operation may be a REP-prefixed string instruction, execution of any
4630 * other instruction, or delivery of an event through the IDT.
4631 *
4632 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4633 * performed now but later after completion of the current operation.
4634 *
4635 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4636 */
4637 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4638
4639 LogFlowFunc(("Write access at offset %#x not intercepted -> Wrote %#RX32\n", offAccess, u32Data));
4640 }
4641 else
4642 {
4643 /*
4644 * A read access from the APIC-access page that is virtualized (rather than
4645 * causing a VM-exit) returns data from the virtual-APIC page.
4646 *
4647 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4648 */
4649 Assert(fAccess & IEM_ACCESS_TYPE_READ);
4650
4651 Assert(cbAccess <= 4);
4652 Assert(offAccess < XAPIC_OFF_END + 4);
4653 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4654
4655 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4656 u32Data &= s_auAccessSizeMasks[cbAccess];
4657 *(uint32_t *)pvData = u32Data;
4658
4659 LogFlowFunc(("Read access at offset %#x not intercepted -> Read %#RX32\n", offAccess, u32Data));
4660 }
4661
4662 return VINF_VMX_MODIFIES_BEHAVIOR;
4663}
4664
4665
4666/**
4667 * Virtualizes an MSR-based APIC read access.
4668 *
4669 * @returns VBox strict status code.
4670 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4671 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4672 * handled by the x2APIC device.
4673 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4674 * not within the range of valid MSRs, caller must raise \#GP(0).
4675 * @param pVCpu The cross context virtual CPU structure.
4676 * @param idMsr The x2APIC MSR being read.
4677 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4678 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4679 */
4680static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4681{
4682 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4683 Assert(pu64Value);
4684
4685 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4686 {
4687 if ( idMsr >= MSR_IA32_X2APIC_START
4688 && idMsr <= MSR_IA32_X2APIC_END)
4689 {
4690 uint16_t const offReg = (idMsr & 0xff) << 4;
4691 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4692 *pu64Value = u64Value;
4693 return VINF_VMX_MODIFIES_BEHAVIOR;
4694 }
4695 return VERR_OUT_OF_RANGE;
4696 }
4697
4698 if (idMsr == MSR_IA32_X2APIC_TPR)
4699 {
4700 uint16_t const offReg = (idMsr & 0xff) << 4;
4701 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4702 *pu64Value = u64Value;
4703 return VINF_VMX_MODIFIES_BEHAVIOR;
4704 }
4705
4706 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4707}
4708
4709
4710/**
4711 * Virtualizes an MSR-based APIC write access.
4712 *
4713 * @returns VBox strict status code.
4714 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4715 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4716 * not within the range of valid MSRs, caller must raise \#GP(0).
4717 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4718 *
4719 * @param pVCpu The cross context virtual CPU structure.
4720 * @param idMsr The x2APIC MSR being written.
4721 * @param u64Value The value of the x2APIC MSR being written.
4722 */
4723static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4724{
4725 /*
4726 * Check if the access is to be virtualized.
4727 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4728 */
4729 if ( idMsr == MSR_IA32_X2APIC_TPR
4730 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4731 && ( idMsr == MSR_IA32_X2APIC_EOI
4732 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4733 {
4734 /* Validate the MSR write depending on the register. */
4735 switch (idMsr)
4736 {
4737 case MSR_IA32_X2APIC_TPR:
4738 case MSR_IA32_X2APIC_SELF_IPI:
4739 {
4740 if (u64Value & UINT64_C(0xffffffffffffff00))
4741 return VERR_OUT_OF_RANGE;
4742 break;
4743 }
4744 case MSR_IA32_X2APIC_EOI:
4745 {
4746 if (u64Value != 0)
4747 return VERR_OUT_OF_RANGE;
4748 break;
4749 }
4750 }
4751
4752 /* Write the MSR to the virtual-APIC page. */
4753 uint16_t const offReg = (idMsr & 0xff) << 4;
4754 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4755
4756 /*
4757 * Record the currently updated APIC offset, as we need this later for figuring
4758 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4759 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4760 */
4761 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4762
4763 return VINF_VMX_MODIFIES_BEHAVIOR;
4764 }
4765
4766 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4767}
4768
4769
4770/**
4771 * Interface for HM and EM to virtualize x2APIC MSR accesses.
4772 *
4773 * @returns Strict VBox status code.
4774 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4775 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4776 * the x2APIC device.
4777 * @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4778 *
4779 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4780 * @param idMsr The MSR being read.
4781 * @param pu64Value Pointer to the value being written or where to store the
4782 * value being read.
4783 * @param fWrite Whether this is an MSR write or read access.
4784 * @thread EMT(pVCpu)
4785 */
4786VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4787{
4788 Assert(pu64Value);
4789
4790 VBOXSTRICTRC rcStrict;
4791 if (fWrite)
4792 rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4793 else
4794 rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4795 Assert(!pVCpu->iem.s.cActiveMappings);
4796 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4797
4798}
4799
4800
4801/**
4802 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4803 *
4804 * @returns VBox status code.
4805 * @retval VINF_SUCCESS when the highest set bit is found.
4806 * @retval VERR_NOT_FOUND when no bit is set.
4807 *
4808 * @param pVCpu The cross context virtual CPU structure.
4809 * @param offReg The offset of the APIC 256-bit sparse register.
4810 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4811 * set in the register. Only valid when VINF_SUCCESS is
4812 * returned.
4813 *
4814 * @remarks The format of the 256-bit sparse register here mirrors that found in
4815 * real APIC hardware.
4816 */
4817static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4818{
4819 Assert(offReg < XAPIC_OFF_END + 4);
4820 Assert(pidxHighestBit);
4821
4822 /*
4823 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4824 * However, in each fragment only the first 4 bytes are used.
4825 */
4826 uint8_t const cFrags = 8;
4827 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4828 {
4829 uint16_t const offFrag = iFrag * 16;
4830 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4831 if (!u32Frag)
4832 continue;
4833
4834 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4835 Assert(idxHighestBit > 0);
4836 --idxHighestBit;
4837 Assert(idxHighestBit <= UINT8_MAX);
4838 *pidxHighestBit = idxHighestBit;
4839 return VINF_SUCCESS;
4840 }
4841 return VERR_NOT_FOUND;
4842}
4843
4844
4845/**
4846 * Evaluates pending virtual interrupts.
4847 *
4848 * @param pVCpu The cross context virtual CPU structure.
4849 */
4850static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4851{
4852 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4853
4854 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4855 {
4856 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4857 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4858
4859 if ((uRvi >> 4) > (uPpr >> 4))
4860 {
4861 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4862 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4863 }
4864 else
4865 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4866 }
4867}
4868
4869
4870/**
4871 * Performs PPR virtualization.
4872 *
4873 * @returns VBox strict status code.
4874 * @param pVCpu The cross context virtual CPU structure.
4875 */
4876static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4877{
4878 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4879 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4880
4881 /*
4882 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4883 * or EOI-virtualization.
4884 *
4885 * See Intel spec. 29.1.3 "PPR Virtualization".
4886 */
4887 uint8_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4888 uint8_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus) & 0xf0;
4889
4890 uint32_t uPpr;
4891 if ((uTpr & 0xf0) >= uSvi)
4892 uPpr = uTpr;
4893 else
4894 uPpr = uSvi;
4895
4896 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4897 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4898}
4899
4900
4901/**
4902 * Performs VMX TPR virtualization.
4903 *
4904 * @returns VBox strict status code.
4905 * @param pVCpu The cross context virtual CPU structure.
4906 */
4907static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4908{
4909 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4910
4911 /*
4912 * We should have already performed the virtual-APIC write to the TPR offset
4913 * in the virtual-APIC page. We now perform TPR virtualization.
4914 *
4915 * See Intel spec. 29.1.2 "TPR Virtualization".
4916 */
4917 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4918 {
4919 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4920 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4921
4922 /*
4923 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4924 * See Intel spec. 29.1.2 "TPR Virtualization".
4925 */
4926 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4927 {
4928 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4929 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4930 }
4931 }
4932 else
4933 {
4934 iemVmxPprVirtualization(pVCpu);
4935 iemVmxEvalPendingVirtIntrs(pVCpu);
4936 }
4937
4938 return VINF_SUCCESS;
4939}
4940
4941
4942/**
4943 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4944 * not.
4945 *
4946 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4947 * @param pVCpu The cross context virtual CPU structure.
4948 * @param uVector The interrupt that was acknowledged using an EOI.
4949 */
4950static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4951{
4952 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4953 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4954
4955 if (uVector < 64)
4956 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4957 if (uVector < 128)
4958 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4959 if (uVector < 192)
4960 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4961 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4962}
4963
4964
4965/**
4966 * Performs EOI virtualization.
4967 *
4968 * @returns VBox strict status code.
4969 * @param pVCpu The cross context virtual CPU structure.
4970 */
4971static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4972{
4973 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4974 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4975
4976 /*
4977 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4978 * and get the next guest-interrupt that's in-service (if any).
4979 *
4980 * See Intel spec. 29.1.4 "EOI Virtualization".
4981 */
4982 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4983 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4984 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4985
4986 uint8_t uVector = uSvi;
4987 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4988
4989 uVector = 0;
4990 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4991
4992 if (uVector)
4993 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4994 else
4995 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4996
4997 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4998 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4999
5000 iemVmxPprVirtualization(pVCpu);
5001 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
5002 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
5003 iemVmxEvalPendingVirtIntrs(pVCpu);
5004 return VINF_SUCCESS;
5005}
5006
5007
5008/**
5009 * Performs self-IPI virtualization.
5010 *
5011 * @returns VBox strict status code.
5012 * @param pVCpu The cross context virtual CPU structure.
5013 */
5014static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
5015{
5016 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5017 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5018
5019 /*
5020 * We should have already performed the virtual-APIC write to the self-IPI offset
5021 * in the virtual-APIC page. We now perform self-IPI virtualization.
5022 *
5023 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5024 */
5025 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5026 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5027 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5028 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5029 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5030 if (uVector > uRvi)
5031 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5032 iemVmxEvalPendingVirtIntrs(pVCpu);
5033 return VINF_SUCCESS;
5034}
5035
5036
5037/**
5038 * Performs VMX APIC-write emulation.
5039 *
5040 * @returns VBox strict status code.
5041 * @param pVCpu The cross context virtual CPU structure.
5042 */
5043VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
5044{
5045 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5046
5047 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5048 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5049
5050 /*
5051 * Perform APIC-write emulation based on the virtual-APIC register written.
5052 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5053 */
5054 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5055 VBOXSTRICTRC rcStrict;
5056 switch (offApicWrite)
5057 {
5058 case XAPIC_OFF_TPR:
5059 {
5060 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5061 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5062 uTpr &= UINT32_C(0x000000ff);
5063 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5064 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5065 rcStrict = iemVmxTprVirtualization(pVCpu);
5066 break;
5067 }
5068
5069 case XAPIC_OFF_EOI:
5070 {
5071 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5072 {
5073 /* Clear VEOI and perform EOI virtualization. */
5074 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5075 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5076 rcStrict = iemVmxEoiVirtualization(pVCpu);
5077 }
5078 else
5079 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5080 break;
5081 }
5082
5083 case XAPIC_OFF_ICR_LO:
5084 {
5085 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5086 {
5087 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5088 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5089 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5090 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5091 if ( !(uIcrLo & fIcrLoMb0)
5092 && (uIcrLo & fIcrLoMb1))
5093 {
5094 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5095 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5096 }
5097 else
5098 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5099 }
5100 else
5101 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5102 break;
5103 }
5104
5105 case XAPIC_OFF_ICR_HI:
5106 {
5107 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5108 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5109 uIcrHi &= UINT32_C(0xff000000);
5110 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5111 rcStrict = VINF_SUCCESS;
5112 break;
5113 }
5114
5115 default:
5116 {
5117 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5118 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5119 break;
5120 }
5121 }
5122
5123 return rcStrict;
5124}
5125
5126
5127/**
5128 * Interface for HM and EM to perform an APIC-write emulation which may cause a
5129 * VM-exit.
5130 *
5131 * @returns Strict VBox status code.
5132 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
5133 * @thread EMT(pVCpu)
5134 */
5135VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5136{
5137 VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5138 Assert(!pVCpu->iem.s.cActiveMappings);
5139 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5140}
5141
5142
5143/**
5144 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5145 *
5146 * @param pVCpu The cross context virtual CPU structure.
5147 * @param pszInstr The VMX instruction name (for logging purposes).
5148 */
5149DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5150{
5151 /*
5152 * Guest Control Registers, Debug Registers, and MSRs.
5153 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5154 */
5155 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5156 const char * const pszFailure = "VM-exit";
5157 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5158
5159 /* CR0 reserved bits. */
5160 {
5161 /* CR0 MB1 bits. */
5162 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
5163 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5164 { /* likely */ }
5165 else
5166 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5167
5168 /* CR0 MBZ bits. */
5169 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5170 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5171 { /* likely */ }
5172 else
5173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5174
5175 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5176 if ( !fUnrestrictedGuest
5177 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5178 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5180 }
5181
5182 /* CR4 reserved bits. */
5183 {
5184 /* CR4 MB1 bits. */
5185 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5186 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5187 { /* likely */ }
5188 else
5189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5190
5191 /* CR4 MBZ bits. */
5192 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5193 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5194 { /* likely */ }
5195 else
5196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5197 }
5198
5199 /* DEBUGCTL MSR. */
5200 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5201 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5202 { /* likely */ }
5203 else
5204 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5205
5206 /* 64-bit CPU checks. */
5207 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5208 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5209 {
5210 if (fGstInLongMode)
5211 {
5212 /* PAE must be set. */
5213 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5214 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5215 { /* likely */ }
5216 else
5217 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5218 }
5219 else
5220 {
5221 /* PCIDE should not be set. */
5222 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5223 { /* likely */ }
5224 else
5225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5226 }
5227
5228 /* CR3. */
5229 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5230 { /* likely */ }
5231 else
5232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5233
5234 /* DR7. */
5235 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5236 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5237 { /* likely */ }
5238 else
5239 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5240
5241 /* SYSENTER ESP and SYSENTER EIP. */
5242 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5243 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5244 { /* likely */ }
5245 else
5246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5247 }
5248
5249 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5250 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5251
5252 /* PAT MSR. */
5253 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5254 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5255 { /* likely */ }
5256 else
5257 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5258
5259 /* EFER MSR. */
5260 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5261 {
5262 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5263 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5264 { /* likely */ }
5265 else
5266 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5267
5268 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5269 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5270 if ( fGstLma == fGstInLongMode
5271 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5272 || fGstLma == fGstLme))
5273 { /* likely */ }
5274 else
5275 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5276 }
5277
5278 /* We don't support IA32_BNDCFGS MSR yet. */
5279 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5280
5281 NOREF(pszInstr);
5282 NOREF(pszFailure);
5283 return VINF_SUCCESS;
5284}
5285
5286
5287/**
5288 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5289 *
5290 * @param pVCpu The cross context virtual CPU structure.
5291 * @param pszInstr The VMX instruction name (for logging purposes).
5292 */
5293DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5294{
5295 /*
5296 * Segment registers.
5297 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5298 */
5299 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5300 const char * const pszFailure = "VM-exit";
5301 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5302 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5303 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5304
5305 /* Selectors. */
5306 if ( !fGstInV86Mode
5307 && !fUnrestrictedGuest
5308 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5309 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5310
5311 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5312 {
5313 CPUMSELREG SelReg;
5314 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5315 if (RT_LIKELY(rc == VINF_SUCCESS))
5316 { /* likely */ }
5317 else
5318 return rc;
5319
5320 /*
5321 * Virtual-8086 mode checks.
5322 */
5323 if (fGstInV86Mode)
5324 {
5325 /* Base address. */
5326 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5327 { /* likely */ }
5328 else
5329 {
5330 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5331 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5332 }
5333
5334 /* Limit. */
5335 if (SelReg.u32Limit == 0xffff)
5336 { /* likely */ }
5337 else
5338 {
5339 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5341 }
5342
5343 /* Attribute. */
5344 if (SelReg.Attr.u == 0xf3)
5345 { /* likely */ }
5346 else
5347 {
5348 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5350 }
5351
5352 /* We're done; move to checking the next segment. */
5353 continue;
5354 }
5355
5356 /* Checks done by 64-bit CPUs. */
5357 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5358 {
5359 /* Base address. */
5360 if ( iSegReg == X86_SREG_FS
5361 || iSegReg == X86_SREG_GS)
5362 {
5363 if (X86_IS_CANONICAL(SelReg.u64Base))
5364 { /* likely */ }
5365 else
5366 {
5367 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5369 }
5370 }
5371 else if (iSegReg == X86_SREG_CS)
5372 {
5373 if (!RT_HI_U32(SelReg.u64Base))
5374 { /* likely */ }
5375 else
5376 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5377 }
5378 else
5379 {
5380 if ( SelReg.Attr.n.u1Unusable
5381 || !RT_HI_U32(SelReg.u64Base))
5382 { /* likely */ }
5383 else
5384 {
5385 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5386 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5387 }
5388 }
5389 }
5390
5391 /*
5392 * Checks outside Virtual-8086 mode.
5393 */
5394 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5395 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5396 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5397 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5398 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5399 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5400 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5401 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5402
5403 /* Code or usable segment. */
5404 if ( iSegReg == X86_SREG_CS
5405 || fUsable)
5406 {
5407 /* Reserved bits (bits 31:17 and bits 11:8). */
5408 if (!(SelReg.Attr.u & 0xfffe0f00))
5409 { /* likely */ }
5410 else
5411 {
5412 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5414 }
5415
5416 /* Descriptor type. */
5417 if (fCodeDataSeg)
5418 { /* likely */ }
5419 else
5420 {
5421 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5423 }
5424
5425 /* Present. */
5426 if (fPresent)
5427 { /* likely */ }
5428 else
5429 {
5430 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5431 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5432 }
5433
5434 /* Granularity. */
5435 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5436 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5437 { /* likely */ }
5438 else
5439 {
5440 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5441 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5442 }
5443 }
5444
5445 if (iSegReg == X86_SREG_CS)
5446 {
5447 /* Segment Type and DPL. */
5448 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5449 && fUnrestrictedGuest)
5450 {
5451 if (uDpl == 0)
5452 { /* likely */ }
5453 else
5454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5455 }
5456 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5457 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5458 {
5459 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5460 if (uDpl == AttrSs.n.u2Dpl)
5461 { /* likely */ }
5462 else
5463 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5464 }
5465 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5466 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5467 {
5468 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5469 if (uDpl <= AttrSs.n.u2Dpl)
5470 { /* likely */ }
5471 else
5472 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5473 }
5474 else
5475 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5476
5477 /* Def/Big. */
5478 if ( fGstInLongMode
5479 && fSegLong)
5480 {
5481 if (uDefBig == 0)
5482 { /* likely */ }
5483 else
5484 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5485 }
5486 }
5487 else if (iSegReg == X86_SREG_SS)
5488 {
5489 /* Segment Type. */
5490 if ( !fUsable
5491 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5492 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5493 { /* likely */ }
5494 else
5495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5496
5497 /* DPL. */
5498 if (!fUnrestrictedGuest)
5499 {
5500 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5501 { /* likely */ }
5502 else
5503 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5504 }
5505 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5506 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5507 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5508 {
5509 if (uDpl == 0)
5510 { /* likely */ }
5511 else
5512 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5513 }
5514 }
5515 else
5516 {
5517 /* DS, ES, FS, GS. */
5518 if (fUsable)
5519 {
5520 /* Segment type. */
5521 if (uSegType & X86_SEL_TYPE_ACCESSED)
5522 { /* likely */ }
5523 else
5524 {
5525 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5526 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5527 }
5528
5529 if ( !(uSegType & X86_SEL_TYPE_CODE)
5530 || (uSegType & X86_SEL_TYPE_READ))
5531 { /* likely */ }
5532 else
5533 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5534
5535 /* DPL. */
5536 if ( !fUnrestrictedGuest
5537 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5538 {
5539 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5540 { /* likely */ }
5541 else
5542 {
5543 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5544 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5545 }
5546 }
5547 }
5548 }
5549 }
5550
5551 /*
5552 * LDTR.
5553 */
5554 {
5555 CPUMSELREG Ldtr;
5556 Ldtr.Sel = pVmcs->GuestLdtr;
5557 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5558 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5559 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5560
5561 if (!Ldtr.Attr.n.u1Unusable)
5562 {
5563 /* Selector. */
5564 if (!(Ldtr.Sel & X86_SEL_LDT))
5565 { /* likely */ }
5566 else
5567 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5568
5569 /* Base. */
5570 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5571 {
5572 if (X86_IS_CANONICAL(Ldtr.u64Base))
5573 { /* likely */ }
5574 else
5575 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5576 }
5577
5578 /* Attributes. */
5579 /* Reserved bits (bits 31:17 and bits 11:8). */
5580 if (!(Ldtr.Attr.u & 0xfffe0f00))
5581 { /* likely */ }
5582 else
5583 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5584
5585 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5586 { /* likely */ }
5587 else
5588 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5589
5590 if (!Ldtr.Attr.n.u1DescType)
5591 { /* likely */ }
5592 else
5593 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5594
5595 if (Ldtr.Attr.n.u1Present)
5596 { /* likely */ }
5597 else
5598 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5599
5600 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5601 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5602 { /* likely */ }
5603 else
5604 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5605 }
5606 }
5607
5608 /*
5609 * TR.
5610 */
5611 {
5612 CPUMSELREG Tr;
5613 Tr.Sel = pVmcs->GuestTr;
5614 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5615 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5616 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5617
5618 /* Selector. */
5619 if (!(Tr.Sel & X86_SEL_LDT))
5620 { /* likely */ }
5621 else
5622 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5623
5624 /* Base. */
5625 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5626 {
5627 if (X86_IS_CANONICAL(Tr.u64Base))
5628 { /* likely */ }
5629 else
5630 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5631 }
5632
5633 /* Attributes. */
5634 /* Reserved bits (bits 31:17 and bits 11:8). */
5635 if (!(Tr.Attr.u & 0xfffe0f00))
5636 { /* likely */ }
5637 else
5638 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5639
5640 if (!Tr.Attr.n.u1Unusable)
5641 { /* likely */ }
5642 else
5643 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5644
5645 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5646 || ( !fGstInLongMode
5647 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5648 { /* likely */ }
5649 else
5650 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5651
5652 if (!Tr.Attr.n.u1DescType)
5653 { /* likely */ }
5654 else
5655 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5656
5657 if (Tr.Attr.n.u1Present)
5658 { /* likely */ }
5659 else
5660 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5661
5662 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5663 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5664 { /* likely */ }
5665 else
5666 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5667 }
5668
5669 NOREF(pszInstr);
5670 NOREF(pszFailure);
5671 return VINF_SUCCESS;
5672}
5673
5674
5675/**
5676 * Checks guest GDTR and IDTR as part of VM-entry.
5677 *
5678 * @param pVCpu The cross context virtual CPU structure.
5679 * @param pszInstr The VMX instruction name (for logging purposes).
5680 */
5681DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5682{
5683 /*
5684 * GDTR and IDTR.
5685 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5686 */
5687 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5688 const char *const pszFailure = "VM-exit";
5689
5690 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5691 {
5692 /* Base. */
5693 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5694 { /* likely */ }
5695 else
5696 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5697
5698 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5699 { /* likely */ }
5700 else
5701 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5702 }
5703
5704 /* Limit. */
5705 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5706 { /* likely */ }
5707 else
5708 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5709
5710 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5711 { /* likely */ }
5712 else
5713 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5714
5715 NOREF(pszInstr);
5716 NOREF(pszFailure);
5717 return VINF_SUCCESS;
5718}
5719
5720
5721/**
5722 * Checks guest RIP and RFLAGS as part of VM-entry.
5723 *
5724 * @param pVCpu The cross context virtual CPU structure.
5725 * @param pszInstr The VMX instruction name (for logging purposes).
5726 */
5727DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5728{
5729 /*
5730 * RIP and RFLAGS.
5731 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5732 */
5733 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5734 const char *const pszFailure = "VM-exit";
5735 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5736
5737 /* RIP. */
5738 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5739 {
5740 X86DESCATTR AttrCs;
5741 AttrCs.u = pVmcs->u32GuestCsAttr;
5742 if ( !fGstInLongMode
5743 || !AttrCs.n.u1Long)
5744 {
5745 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5746 { /* likely */ }
5747 else
5748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5749 }
5750
5751 if ( fGstInLongMode
5752 && AttrCs.n.u1Long)
5753 {
5754 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5755 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5756 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5757 { /* likely */ }
5758 else
5759 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5760 }
5761 }
5762
5763 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5764 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5765 : pVmcs->u64GuestRFlags.s.Lo;
5766 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5767 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5768 { /* likely */ }
5769 else
5770 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5771
5772 if (!(uGuestRFlags & X86_EFL_VM))
5773 { /* likely */ }
5774 else
5775 {
5776 if ( fGstInLongMode
5777 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5778 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5779 }
5780
5781 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5782 {
5783 if (uGuestRFlags & X86_EFL_IF)
5784 { /* likely */ }
5785 else
5786 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5787 }
5788
5789 NOREF(pszInstr);
5790 NOREF(pszFailure);
5791 return VINF_SUCCESS;
5792}
5793
5794
5795/**
5796 * Checks guest non-register state as part of VM-entry.
5797 *
5798 * @param pVCpu The cross context virtual CPU structure.
5799 * @param pszInstr The VMX instruction name (for logging purposes).
5800 */
5801DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5802{
5803 /*
5804 * Guest non-register state.
5805 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5806 */
5807 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5808 const char *const pszFailure = "VM-exit";
5809
5810 /*
5811 * Activity state.
5812 */
5813 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5814 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5815 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5816 { /* likely */ }
5817 else
5818 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5819
5820 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5821 if ( !AttrSs.n.u2Dpl
5822 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5823 { /* likely */ }
5824 else
5825 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5826
5827 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5828 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5829 {
5830 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5831 { /* likely */ }
5832 else
5833 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5834 }
5835
5836 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5837 {
5838 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5839 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5840 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5841 switch (pVmcs->u32GuestActivityState)
5842 {
5843 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5844 {
5845 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5846 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5847 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5848 && ( uVector == X86_XCPT_DB
5849 || uVector == X86_XCPT_MC))
5850 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5851 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5852 { /* likely */ }
5853 else
5854 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5855 break;
5856 }
5857
5858 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5859 {
5860 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5861 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5862 && uVector == X86_XCPT_MC))
5863 { /* likely */ }
5864 else
5865 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5866 break;
5867 }
5868
5869 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5870 default:
5871 break;
5872 }
5873 }
5874
5875 /*
5876 * Interruptibility state.
5877 */
5878 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5879 { /* likely */ }
5880 else
5881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5882
5883 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5884 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5885 { /* likely */ }
5886 else
5887 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5888
5889 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5890 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5891 { /* likely */ }
5892 else
5893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5894
5895 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5896 {
5897 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5898 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5899 {
5900 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5901 { /* likely */ }
5902 else
5903 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5904 }
5905 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5906 {
5907 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5908 { /* likely */ }
5909 else
5910 {
5911 /*
5912 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5913 * We update the Exit qualification only when blocking-by-STI is set
5914 * without blocking-by-MovSS being set. Although in practise it does not
5915 * make much difference since the order of checks are implementation defined.
5916 */
5917 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5918 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5919 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5920 }
5921
5922 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5923 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5924 { /* likely */ }
5925 else
5926 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5927 }
5928 }
5929
5930 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5931 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5932 { /* likely */ }
5933 else
5934 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5935
5936 /* We don't support SGX yet. So enclave-interruption must not be set. */
5937 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5938 { /* likely */ }
5939 else
5940 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5941
5942 /*
5943 * Pending debug exceptions.
5944 */
5945 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5946 ? pVmcs->u64GuestPendingDbgXcpts.u
5947 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5948 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5949 { /* likely */ }
5950 else
5951 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5952
5953 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5954 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5955 {
5956 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5957 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5958 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5959 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5960
5961 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5962 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5963 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5964 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5965 }
5966
5967 /* We don't support RTM (Real-time Transactional Memory) yet. */
5968 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5969 { /* likely */ }
5970 else
5971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5972
5973 /*
5974 * VMCS link pointer.
5975 */
5976 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5977 {
5978 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5979 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5980 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5981 { /* likely */ }
5982 else
5983 {
5984 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5985 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5986 }
5987
5988 /* Validate the address. */
5989 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5990 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5991 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5992 { /* likely */ }
5993 else
5994 {
5995 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5996 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5997 }
5998 }
5999
6000 NOREF(pszInstr);
6001 NOREF(pszFailure);
6002 return VINF_SUCCESS;
6003}
6004
6005
6006#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6007/**
6008 * Checks guest PDPTEs as part of VM-entry.
6009 *
6010 * @param pVCpu The cross context virtual CPU structure.
6011 * @param pszInstr The VMX instruction name (for logging purposes).
6012 */
6013static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6014{
6015 /*
6016 * Guest PDPTEs.
6017 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6018 */
6019 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6020 const char * const pszFailure = "VM-exit";
6021
6022 /*
6023 * When EPT is used, we only validate the PAE PDPTEs provided in the VMCS.
6024 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
6025 */
6026 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
6027 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
6028 {
6029 /* Get PDPTEs from the VMCS. */
6030 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6031 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6032 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6033 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6034 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6035
6036 /* Check validity of the PDPTEs. */
6037 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
6038 if (fValid)
6039 { /* likely */ }
6040 else
6041 {
6042 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6043 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6044 }
6045 }
6046
6047 NOREF(pszFailure);
6048 NOREF(pszInstr);
6049 return VINF_SUCCESS;
6050}
6051#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6052
6053
6054/**
6055 * Checks guest-state as part of VM-entry.
6056 *
6057 * @returns VBox status code.
6058 * @param pVCpu The cross context virtual CPU structure.
6059 * @param pszInstr The VMX instruction name (for logging purposes).
6060 */
6061static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6062{
6063 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6064 if (RT_SUCCESS(rc))
6065 {
6066 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6067 if (RT_SUCCESS(rc))
6068 {
6069 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6070 if (RT_SUCCESS(rc))
6071 {
6072 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6073 if (RT_SUCCESS(rc))
6074 {
6075 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6076#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6077 if (RT_SUCCESS(rc))
6078 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6079#endif
6080 }
6081 }
6082 }
6083 }
6084 return rc;
6085}
6086
6087
6088/**
6089 * Checks host-state as part of VM-entry.
6090 *
6091 * @returns VBox status code.
6092 * @param pVCpu The cross context virtual CPU structure.
6093 * @param pszInstr The VMX instruction name (for logging purposes).
6094 */
6095static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6096{
6097 /*
6098 * Host Control Registers and MSRs.
6099 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6100 */
6101 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6102 const char * const pszFailure = "VMFail";
6103
6104 /* CR0 reserved bits. */
6105 {
6106 /* CR0 MB1 bits. */
6107 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
6108 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6109 { /* likely */ }
6110 else
6111 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6112
6113 /* CR0 MBZ bits. */
6114 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6115 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6116 { /* likely */ }
6117 else
6118 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6119 }
6120
6121 /* CR4 reserved bits. */
6122 {
6123 /* CR4 MB1 bits. */
6124 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6125 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6126 { /* likely */ }
6127 else
6128 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6129
6130 /* CR4 MBZ bits. */
6131 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6132 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6133 { /* likely */ }
6134 else
6135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6136 }
6137
6138 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6139 {
6140 /* CR3 reserved bits. */
6141 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6142 { /* likely */ }
6143 else
6144 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6145
6146 /* SYSENTER ESP and SYSENTER EIP. */
6147 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6148 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6149 { /* likely */ }
6150 else
6151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6152 }
6153
6154 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6155 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6156
6157 /* PAT MSR. */
6158 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6159 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6160 { /* likely */ }
6161 else
6162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6163
6164 /* EFER MSR. */
6165 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6166 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6167 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6168 { /* likely */ }
6169 else
6170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6171
6172 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6173 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6174 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6175 if ( fHostInLongMode == fHostLma
6176 && fHostInLongMode == fHostLme)
6177 { /* likely */ }
6178 else
6179 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6180
6181 /*
6182 * Host Segment and Descriptor-Table Registers.
6183 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6184 */
6185 /* Selector RPL and TI. */
6186 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6187 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6188 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6189 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6190 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6191 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6192 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6193 { /* likely */ }
6194 else
6195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6196
6197 /* CS and TR selectors cannot be 0. */
6198 if ( pVmcs->HostCs
6199 && pVmcs->HostTr)
6200 { /* likely */ }
6201 else
6202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6203
6204 /* SS cannot be 0 if 32-bit host. */
6205 if ( fHostInLongMode
6206 || pVmcs->HostSs)
6207 { /* likely */ }
6208 else
6209 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6210
6211 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6212 {
6213 /* FS, GS, GDTR, IDTR, TR base address. */
6214 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6215 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6216 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6217 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6218 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6219 { /* likely */ }
6220 else
6221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6222 }
6223
6224 /*
6225 * Host address-space size for 64-bit CPUs.
6226 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6227 */
6228 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6229 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6230 {
6231 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6232
6233 /* Logical processor in IA-32e mode. */
6234 if (fCpuInLongMode)
6235 {
6236 if (fHostInLongMode)
6237 {
6238 /* PAE must be set. */
6239 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6240 { /* likely */ }
6241 else
6242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6243
6244 /* RIP must be canonical. */
6245 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6246 { /* likely */ }
6247 else
6248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6249 }
6250 else
6251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6252 }
6253 else
6254 {
6255 /* Logical processor is outside IA-32e mode. */
6256 if ( !fGstInLongMode
6257 && !fHostInLongMode)
6258 {
6259 /* PCIDE should not be set. */
6260 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6261 { /* likely */ }
6262 else
6263 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6264
6265 /* The high 32-bits of RIP MBZ. */
6266 if (!pVmcs->u64HostRip.s.Hi)
6267 { /* likely */ }
6268 else
6269 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6270 }
6271 else
6272 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6273 }
6274 }
6275 else
6276 {
6277 /* Host address-space size for 32-bit CPUs. */
6278 if ( !fGstInLongMode
6279 && !fHostInLongMode)
6280 { /* likely */ }
6281 else
6282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6283 }
6284
6285 NOREF(pszInstr);
6286 NOREF(pszFailure);
6287 return VINF_SUCCESS;
6288}
6289
6290
6291#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6292/**
6293 * Checks the EPT pointer VMCS field as part of VM-entry.
6294 *
6295 * @returns VBox status code.
6296 * @param pVCpu The cross context virtual CPU structure.
6297 * @param uEptPtr The EPT pointer to check.
6298 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
6299 * updated on success). Optional, can be NULL.
6300 */
6301static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6302{
6303 VMXVDIAG enmVmxDiag;
6304
6305 /* Reserved bits. */
6306 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6307 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6308 if (uEptPtr & fValidMask)
6309 {
6310 /* Memory Type. */
6311 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6312 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6313 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6314 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6315 || ( fMemType == VMX_EPTP_MEMTYPE_UC
6316 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6317 {
6318 /*
6319 * Page walk length (PML4).
6320 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6321 * of 5 but that seems to be removed from the latest specs. leaving only PML4
6322 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6323 */
6324 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6325 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6326 {
6327 /* Access and dirty bits support in EPT structures. */
6328 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6329 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6330 return VINF_SUCCESS;
6331
6332 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6333 }
6334 else
6335 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6336 }
6337 else
6338 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6339 }
6340 else
6341 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6342
6343 if (penmVmxDiag)
6344 *penmVmxDiag = enmVmxDiag;
6345 return VERR_VMX_VMENTRY_FAILED;
6346}
6347#endif
6348
6349
6350/**
6351 * Checks VMCS controls fields as part of VM-entry.
6352 *
6353 * @returns VBox status code.
6354 * @param pVCpu The cross context virtual CPU structure.
6355 * @param pszInstr The VMX instruction name (for logging purposes).
6356 *
6357 * @remarks This may update secondary-processor based VM-execution control fields
6358 * in the current VMCS if necessary.
6359 */
6360static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6361{
6362 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6363 const char * const pszFailure = "VMFail";
6364 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6365
6366 /*
6367 * VM-execution controls.
6368 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6369 */
6370 {
6371 /* Pin-based VM-execution controls. */
6372 {
6373 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6374 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6375 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6376 { /* likely */ }
6377 else
6378 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6379
6380 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6381 { /* likely */ }
6382 else
6383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6384 }
6385
6386 /* Processor-based VM-execution controls. */
6387 {
6388 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6389 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6390 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6391 { /* likely */ }
6392 else
6393 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6394
6395 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6396 { /* likely */ }
6397 else
6398 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6399 }
6400
6401 /* Secondary processor-based VM-execution controls. */
6402 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6403 {
6404 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6405 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6406 { /* likely */ }
6407 else
6408 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6409
6410 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6411 { /* likely */ }
6412 else
6413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6414 }
6415 else
6416 Assert(!pVmcs->u32ProcCtls2);
6417
6418 /* CR3-target count. */
6419 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6420 { /* likely */ }
6421 else
6422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6423
6424 /* I/O bitmaps physical addresses. */
6425 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6426 {
6427 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6428 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6429 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6430 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6431 { /* likely */ }
6432 else
6433 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6434
6435 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6436 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6437 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6438 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6439 { /* likely */ }
6440 else
6441 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6442 }
6443
6444 /* MSR bitmap physical address. */
6445 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6446 {
6447 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6448 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6449 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6450 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6451 { /* likely */ }
6452 else
6453 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6454 }
6455
6456 /* TPR shadow related controls. */
6457 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6458 {
6459 /* Virtual-APIC page physical address. */
6460 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6461 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6462 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6463 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6464 { /* likely */ }
6465 else
6466 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6467
6468 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6469 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6470 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6471 { /* likely */ }
6472 else
6473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6474
6475 /* The rest done XXX document */
6476 }
6477 else
6478 {
6479 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6480 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6481 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6482 { /* likely */ }
6483 else
6484 {
6485 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6486 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6487 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6489 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6490 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6491 }
6492 }
6493
6494 /* NMI exiting and virtual-NMIs. */
6495 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6496 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6497 { /* likely */ }
6498 else
6499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6500
6501 /* Virtual-NMIs and NMI-window exiting. */
6502 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6503 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6504 { /* likely */ }
6505 else
6506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6507
6508 /* Virtualize APIC accesses. */
6509 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6510 {
6511 /* APIC-access physical address. */
6512 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6513 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6514 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6515 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6516 { /* likely */ }
6517 else
6518 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6519
6520 /*
6521 * Disallow APIC-access page and virtual-APIC page from being the same address.
6522 * Note! This is not an Intel requirement, but one imposed by our implementation.
6523 */
6524 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6525 * redirecting accesses between the APIC-access page and the virtual-APIC
6526 * page. If any nested hypervisor requires this, we can implement it later. */
6527 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6528 {
6529 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6530 if (GCPhysVirtApic != GCPhysApicAccess)
6531 { /* likely */ }
6532 else
6533 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6534 }
6535 }
6536
6537 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6538 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6539 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6540 { /* likely */ }
6541 else
6542 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6543
6544 /* Virtual-interrupt delivery requires external interrupt exiting. */
6545 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6546 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6547 { /* likely */ }
6548 else
6549 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6550
6551 /* VPID. */
6552 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6553 || pVmcs->u16Vpid != 0)
6554 { /* likely */ }
6555 else
6556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6557
6558#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6559 /* Extended-Page-Table Pointer (EPTP). */
6560 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6561 {
6562 VMXVDIAG enmVmxDiag;
6563 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6564 if (RT_SUCCESS(rc))
6565 { /* likely */ }
6566 else
6567 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6568 }
6569#else
6570 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6571 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6572#endif
6573 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6574 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6575 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6576 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6577 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6578 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6579
6580 /* VMCS shadowing. */
6581 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6582 {
6583 /* VMREAD-bitmap physical address. */
6584 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6585 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6586 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6587 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6588 { /* likely */ }
6589 else
6590 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6591
6592 /* VMWRITE-bitmap physical address. */
6593 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6594 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6595 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6596 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6597 { /* likely */ }
6598 else
6599 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6600 }
6601 }
6602
6603 /*
6604 * VM-exit controls.
6605 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6606 */
6607 {
6608 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6609 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6610 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6611 { /* likely */ }
6612 else
6613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6614
6615 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6616 { /* likely */ }
6617 else
6618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6619
6620 /* Save preemption timer without activating it. */
6621 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6622 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6623 { /* likely */ }
6624 else
6625 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6626
6627 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6628 if (pVmcs->u32ExitMsrStoreCount)
6629 {
6630 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6631 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6632 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6633 { /* likely */ }
6634 else
6635 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6636 }
6637
6638 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6639 if (pVmcs->u32ExitMsrLoadCount)
6640 {
6641 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6642 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6643 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6644 { /* likely */ }
6645 else
6646 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6647 }
6648 }
6649
6650 /*
6651 * VM-entry controls.
6652 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6653 */
6654 {
6655 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6656 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6657 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6658 { /* likely */ }
6659 else
6660 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6661
6662 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6663 { /* likely */ }
6664 else
6665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6666
6667 /* Event injection. */
6668 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6669 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6670 {
6671 /* Type and vector. */
6672 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6673 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6674 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6675 if ( !uRsvd
6676 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6677 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6678 { /* likely */ }
6679 else
6680 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6681
6682 /* Exception error code. */
6683 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6684 {
6685 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6686 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6687 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6688 { /* likely */ }
6689 else
6690 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6691
6692 /* Exceptions that provide an error code. */
6693 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6694 && ( uVector == X86_XCPT_DF
6695 || uVector == X86_XCPT_TS
6696 || uVector == X86_XCPT_NP
6697 || uVector == X86_XCPT_SS
6698 || uVector == X86_XCPT_GP
6699 || uVector == X86_XCPT_PF
6700 || uVector == X86_XCPT_AC))
6701 { /* likely */ }
6702 else
6703 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6704
6705 /* Exception error-code reserved bits. */
6706 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6707 { /* likely */ }
6708 else
6709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6710
6711 /* Injecting a software interrupt, software exception or privileged software exception. */
6712 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6713 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6714 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6715 {
6716 /* Instruction length must be in the range 0-15. */
6717 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6718 { /* likely */ }
6719 else
6720 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6721
6722 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6723 if ( pVmcs->u32EntryInstrLen != 0
6724 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6725 { /* likely */ }
6726 else
6727 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6728 }
6729 }
6730 }
6731
6732 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6733 if (pVmcs->u32EntryMsrLoadCount)
6734 {
6735 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6736 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6737 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6738 { /* likely */ }
6739 else
6740 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6741 }
6742
6743 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6744 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6745 }
6746
6747 NOREF(pszInstr);
6748 NOREF(pszFailure);
6749 return VINF_SUCCESS;
6750}
6751
6752
6753/**
6754 * Loads the guest control registers, debug register and some MSRs as part of
6755 * VM-entry.
6756 *
6757 * @param pVCpu The cross context virtual CPU structure.
6758 */
6759static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6760{
6761 /*
6762 * Load guest control registers, debug registers and MSRs.
6763 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6764 */
6765 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6766
6767 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6768 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6769 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6770 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6771 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6772 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6773
6774 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6775 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6776
6777 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6778 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6779 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6780
6781 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6782 {
6783 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6784
6785 /* EFER MSR. */
6786 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6787 {
6788 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6789 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6790 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6791 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6792 if (fGstInLongMode)
6793 {
6794 /* If the nested-guest is in long mode, LMA and LME are both set. */
6795 Assert(fGstPaging);
6796 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6797 }
6798 else
6799 {
6800 /*
6801 * If the nested-guest is outside long mode:
6802 * - With paging: LMA is cleared, LME is cleared.
6803 * - Without paging: LMA is cleared, LME is left unmodified.
6804 */
6805 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6806 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6807 }
6808 }
6809 /* else: see below. */
6810 }
6811
6812 /* PAT MSR. */
6813 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6814 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6815
6816 /* EFER MSR. */
6817 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6818 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6819
6820 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6821 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6822
6823 /* We don't support IA32_BNDCFGS MSR yet. */
6824 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6825
6826 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6827}
6828
6829
6830/**
6831 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6832 *
6833 * @param pVCpu The cross context virtual CPU structure.
6834 */
6835static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6836{
6837 /*
6838 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6839 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6840 */
6841 /* CS, SS, ES, DS, FS, GS. */
6842 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6843 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6844 {
6845 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6846 CPUMSELREG VmcsSelReg;
6847 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6848 AssertRC(rc); NOREF(rc);
6849 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6850 {
6851 pGstSelReg->Sel = VmcsSelReg.Sel;
6852 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6853 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6854 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6855 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6856 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6857 }
6858 else
6859 {
6860 pGstSelReg->Sel = VmcsSelReg.Sel;
6861 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6862 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6863 switch (iSegReg)
6864 {
6865 case X86_SREG_CS:
6866 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6867 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6868 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6869 break;
6870
6871 case X86_SREG_SS:
6872 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6873 pGstSelReg->u32Limit = 0;
6874 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6875 break;
6876
6877 case X86_SREG_ES:
6878 case X86_SREG_DS:
6879 pGstSelReg->u64Base = 0;
6880 pGstSelReg->u32Limit = 0;
6881 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6882 break;
6883
6884 case X86_SREG_FS:
6885 case X86_SREG_GS:
6886 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6887 pGstSelReg->u32Limit = 0;
6888 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6889 break;
6890 }
6891 Assert(pGstSelReg->Attr.n.u1Unusable);
6892 }
6893 }
6894
6895 /* LDTR. */
6896 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6897 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6898 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6899 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6900 {
6901 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6902 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6903 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6904 }
6905 else
6906 {
6907 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6908 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6909 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6910 }
6911
6912 /* TR. */
6913 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6914 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6915 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6916 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6917 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6918 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6919 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6920
6921 /* GDTR. */
6922 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6923 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6924
6925 /* IDTR. */
6926 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6927 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6928}
6929
6930
6931/**
6932 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6933 *
6934 * @returns VBox status code.
6935 * @param pVCpu The cross context virtual CPU structure.
6936 * @param pszInstr The VMX instruction name (for logging purposes).
6937 */
6938static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6939{
6940 /*
6941 * Load guest MSRs.
6942 * See Intel spec. 26.4 "Loading MSRs".
6943 */
6944 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6945 const char *const pszFailure = "VM-exit";
6946
6947 /*
6948 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6949 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6950 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6951 */
6952 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6953 if (!cMsrs)
6954 return VINF_SUCCESS;
6955
6956 /*
6957 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6958 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6959 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6960 */
6961 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6962 if (fIsMsrCountValid)
6963 { /* likely */ }
6964 else
6965 {
6966 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6967 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6968 }
6969
6970 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6971 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6972 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6973 if (RT_SUCCESS(rc))
6974 {
6975 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6976 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6977 {
6978 if ( !pMsr->u32Reserved
6979 && pMsr->u32Msr != MSR_K8_FS_BASE
6980 && pMsr->u32Msr != MSR_K8_GS_BASE
6981 && pMsr->u32Msr != MSR_K6_EFER
6982 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6983 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6984 {
6985 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6986 if (rcStrict == VINF_SUCCESS)
6987 continue;
6988
6989 /*
6990 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6991 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6992 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6993 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6994 * MSR in ring-0 if possible, or come up with a better, generic solution.
6995 */
6996 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6997 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6998 ? kVmxVDiag_Vmentry_MsrLoadRing3
6999 : kVmxVDiag_Vmentry_MsrLoad;
7000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7001 }
7002 else
7003 {
7004 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7005 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7006 }
7007 }
7008 }
7009 else
7010 {
7011 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7012 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7013 }
7014
7015 NOREF(pszInstr);
7016 NOREF(pszFailure);
7017 return VINF_SUCCESS;
7018}
7019
7020
7021/**
7022 * Loads the guest-state non-register state as part of VM-entry.
7023 *
7024 * @returns VBox status code.
7025 * @param pVCpu The cross context virtual CPU structure.
7026 * @param pszInstr The VMX instruction name (for logging purposes).
7027 *
7028 * @remarks This must be called only after loading the nested-guest register state
7029 * (especially nested-guest RIP).
7030 */
7031static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7032{
7033 /*
7034 * Load guest non-register state.
7035 * See Intel spec. 26.6 "Special Features of VM Entry"
7036 */
7037 const char *const pszFailure = "VM-exit";
7038 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7039
7040 /*
7041 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7042 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7043 *
7044 * See Intel spec. 26.6.1 "Interruptibility State".
7045 */
7046 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7047 if ( !fEntryVectoring
7048 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7049 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7050 else
7051 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
7052
7053 /* NMI blocking. */
7054 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7055 {
7056 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7057 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7058 else
7059 {
7060 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7061 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7062 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7063 }
7064 }
7065 else
7066 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7067
7068 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7069
7070 /*
7071 * Set PGM's copy of the EPT pointer.
7072 * The EPTP has already been validated while checking guest state.
7073 *
7074 * It is important to do this prior to mapping PAE PDPTEs (below).
7075 */
7076 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7077 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7078
7079 /*
7080 * Load the guest's PAE PDPTEs.
7081 */
7082 if (iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7083 {
7084 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7085 {
7086 /*
7087 * With EPT, we've already validated these while checking the guest state.
7088 * Just load them directly from the VMCS here.
7089 */
7090 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
7091 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
7092 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
7093 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
7094 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
7095 AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
7096 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
7097 pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
7098 }
7099 else
7100 {
7101 /*
7102 * Without EPT, we must load the PAE PDPTEs referenced by CR3.
7103 * This involves loading (and mapping) CR3 and validating them now.
7104 */
7105 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7106 if (RT_SUCCESS(rc))
7107 { /* likely */ }
7108 else
7109 {
7110 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7111 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
7112 }
7113 }
7114 }
7115
7116 /* VPID is irrelevant. We don't support VPID yet. */
7117
7118 /* Clear address-range monitoring. */
7119 EMMonitorWaitClear(pVCpu);
7120
7121 return VINF_SUCCESS;
7122}
7123
7124
7125/**
7126 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7127 *
7128 * @param pVCpu The cross context virtual CPU structure.
7129 * @param pszInstr The VMX instruction name (for logging purposes).
7130 *
7131 * @remarks This assumes various VMCS related data structure pointers have already
7132 * been verified prior to calling this function.
7133 */
7134static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7135{
7136 const char *const pszFailure = "VM-exit";
7137 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7138
7139 /*
7140 * Virtualize APIC accesses.
7141 */
7142 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7143 {
7144 /* APIC-access physical address. */
7145 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7146
7147 /*
7148 * Register the handler for the APIC-access page.
7149 *
7150 * We don't deregister the APIC-access page handler during the VM-exit as a different
7151 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
7152 *
7153 * We leave the page registered until the first access that happens outside VMX non-root
7154 * mode. Guest software is allowed to access structures such as the APIC-access page
7155 * only when no logical processor with a current VMCS references it in VMX non-root mode,
7156 * otherwise it can lead to unpredictable behavior including guest triple-faults.
7157 *
7158 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7159 */
7160 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
7161 {
7162 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7163 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess | X86_PAGE_4K_OFFSET_MASK,
7164 pVM->iem.s.hVmxApicAccessPage, 0 /*uUser*/, NULL /*pszDesc*/);
7165 if (RT_SUCCESS(rc))
7166 { /* likely */ }
7167 else
7168 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
7169 }
7170 }
7171
7172 /*
7173 * VMCS shadowing.
7174 */
7175 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7176 {
7177 /* Read the VMREAD-bitmap. */
7178 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7179 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7180 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7181 if (RT_SUCCESS(rc))
7182 { /* likely */ }
7183 else
7184 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
7185
7186 /* Read the VMWRITE-bitmap. */
7187 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7188 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7189 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7190 if (RT_SUCCESS(rc))
7191 { /* likely */ }
7192 else
7193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
7194 }
7195
7196 /*
7197 * I/O bitmaps.
7198 */
7199 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7200 {
7201 /* Read the IO bitmap A. */
7202 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7203 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7204 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7205 if (RT_SUCCESS(rc))
7206 { /* likely */ }
7207 else
7208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
7209
7210 /* Read the IO bitmap B. */
7211 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7212 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7213 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7214 if (RT_SUCCESS(rc))
7215 { /* likely */ }
7216 else
7217 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
7218 }
7219
7220 /*
7221 * TPR shadow and Virtual-APIC page.
7222 */
7223 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7224 {
7225 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7226 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7227 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7228 {
7229 /* Read the VTPR from the virtual-APIC page. */
7230 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7231 uint8_t u8VTpr;
7232 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7233 if (RT_SUCCESS(rc))
7234 { /* likely */ }
7235 else
7236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
7237
7238 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7239 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7240 { /* likely */ }
7241 else
7242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7243 }
7244 }
7245
7246 /*
7247 * VMCS link pointer.
7248 */
7249 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7250 {
7251 /* Read the VMCS-link pointer from guest memory. */
7252 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7253 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7254 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7255 if (RT_SUCCESS(rc))
7256 { /* likely */ }
7257 else
7258 {
7259 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
7261 }
7262
7263 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7264 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7265 { /* likely */ }
7266 else
7267 {
7268 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7269 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7270 }
7271
7272 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
7273 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7274 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7275 { /* likely */ }
7276 else
7277 {
7278 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7280 }
7281
7282 /* Update our cache of the guest physical address of the shadow VMCS. */
7283 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7284 }
7285
7286 /*
7287 * MSR bitmap.
7288 */
7289 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7290 {
7291 /* Read the MSR bitmap. */
7292 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7293 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7294 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7295 if (RT_SUCCESS(rc))
7296 { /* likely */ }
7297 else
7298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
7299 }
7300
7301 NOREF(pszFailure);
7302 NOREF(pszInstr);
7303 return VINF_SUCCESS;
7304}
7305
7306
7307/**
7308 * Loads the guest-state as part of VM-entry.
7309 *
7310 * @returns VBox status code.
7311 * @param pVCpu The cross context virtual CPU structure.
7312 * @param pszInstr The VMX instruction name (for logging purposes).
7313 *
7314 * @remarks This must be done after all the necessary steps prior to loading of
7315 * guest-state (e.g. checking various VMCS state).
7316 */
7317static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7318{
7319 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
7320 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7321
7322 /* Load guest segment registers. */
7323 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7324
7325 /*
7326 * Load guest RIP, RSP and RFLAGS.
7327 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7328 */
7329 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7330 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7331 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7332 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7333
7334 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7335 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7336 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7337
7338 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7339 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7340 if (rc == VINF_SUCCESS)
7341 { /* likely */ }
7342 else
7343 return rc;
7344
7345 /* Load VMX related structures and state referenced by the VMCS. */
7346 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7347 if (rc == VINF_SUCCESS)
7348 { /* likely */ }
7349 else
7350 return rc;
7351
7352 NOREF(pszInstr);
7353 return VINF_SUCCESS;
7354}
7355
7356
7357/**
7358 * Returns whether there are is a pending debug exception on VM-entry.
7359 *
7360 * @param pVCpu The cross context virtual CPU structure.
7361 * @param pszInstr The VMX instruction name (for logging purposes).
7362 */
7363static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7364{
7365 /*
7366 * Pending debug exceptions.
7367 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7368 */
7369 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7370 Assert(pVmcs);
7371
7372 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7373 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7374 if (fPendingDbgXcpt)
7375 {
7376 uint8_t uEntryIntInfoType;
7377 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7378 if (fEntryVectoring)
7379 {
7380 switch (uEntryIntInfoType)
7381 {
7382 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7383 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7384 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7385 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7386 fPendingDbgXcpt = false;
7387 break;
7388
7389 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7390 {
7391 /*
7392 * Whether the pending debug exception for software exceptions other than
7393 * #BP and #OF is delivered after injecting the exception or is discard
7394 * is CPU implementation specific. We will discard them (easier).
7395 */
7396 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7397 if ( uVector != X86_XCPT_BP
7398 && uVector != X86_XCPT_OF)
7399 fPendingDbgXcpt = false;
7400 RT_FALL_THRU();
7401 }
7402 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7403 {
7404 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7405 fPendingDbgXcpt = false;
7406 break;
7407 }
7408 }
7409 }
7410 else
7411 {
7412 /*
7413 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7414 * pending debug exception is held pending or is discarded is CPU implementation
7415 * specific. We will discard them (easier).
7416 */
7417 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7418 fPendingDbgXcpt = false;
7419
7420 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7421 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7422 fPendingDbgXcpt = false;
7423 }
7424 }
7425
7426 NOREF(pszInstr);
7427 return fPendingDbgXcpt;
7428}
7429
7430
7431/**
7432 * Set up the monitor-trap flag (MTF).
7433 *
7434 * @param pVCpu The cross context virtual CPU structure.
7435 * @param pszInstr The VMX instruction name (for logging purposes).
7436 */
7437static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7438{
7439 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7440 Assert(pVmcs);
7441 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7442 {
7443 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7444 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7445 }
7446 else
7447 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7448 NOREF(pszInstr);
7449}
7450
7451
7452/**
7453 * Sets up NMI-window exiting.
7454 *
7455 * @param pVCpu The cross context virtual CPU structure.
7456 * @param pszInstr The VMX instruction name (for logging purposes).
7457 */
7458static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7459{
7460 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7461 Assert(pVmcs);
7462 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7463 {
7464 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7465 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7466 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7467 }
7468 else
7469 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7470 NOREF(pszInstr);
7471}
7472
7473
7474/**
7475 * Sets up interrupt-window exiting.
7476 *
7477 * @param pVCpu The cross context virtual CPU structure.
7478 * @param pszInstr The VMX instruction name (for logging purposes).
7479 */
7480static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7481{
7482 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7483 Assert(pVmcs);
7484 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7485 {
7486 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7487 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7488 }
7489 else
7490 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7491 NOREF(pszInstr);
7492}
7493
7494
7495/**
7496 * Set up the VMX-preemption timer.
7497 *
7498 * @param pVCpu The cross context virtual CPU structure.
7499 * @param pszInstr The VMX instruction name (for logging purposes).
7500 */
7501static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7502{
7503 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7504 Assert(pVmcs);
7505 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7506 {
7507 /*
7508 * If the timer is 0, we must cause a VM-exit before executing the first
7509 * nested-guest instruction. So we can flag as though the timer has already
7510 * expired and we will check and cause a VM-exit at the right priority elsewhere
7511 * in the code.
7512 */
7513 uint64_t uEntryTick;
7514 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7515 if (uPreemptTimer)
7516 {
7517 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7518 AssertRC(rc);
7519 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7520 }
7521 else
7522 {
7523 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7524 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7525 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7526 }
7527
7528 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7529 }
7530 else
7531 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7532
7533 NOREF(pszInstr);
7534}
7535
7536
7537/**
7538 * Injects an event using TRPM given a VM-entry interruption info. and related
7539 * fields.
7540 *
7541 * @param pVCpu The cross context virtual CPU structure.
7542 * @param pszInstr The VMX instruction name (for logging purposes).
7543 * @param uEntryIntInfo The VM-entry interruption info.
7544 * @param uErrCode The error code associated with the event if any.
7545 * @param cbInstr The VM-entry instruction length (for software
7546 * interrupts and software exceptions). Pass 0
7547 * otherwise.
7548 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7549 */
7550static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7551 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7552{
7553 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7554
7555 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7556 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7557 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7558
7559 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7560
7561 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7562 AssertRC(rc);
7563 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7564
7565 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7566 {
7567 TRPMSetErrorCode(pVCpu, uErrCode);
7568 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7569 }
7570
7571 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7572 {
7573 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7574 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7575 }
7576 else
7577 {
7578 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7579 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7580 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7581 {
7582 TRPMSetInstrLength(pVCpu, cbInstr);
7583 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7584 }
7585 }
7586
7587 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7588 {
7589 TRPMSetTrapDueToIcebp(pVCpu);
7590 Log(("%s: Injecting: icebp\n", pszInstr));
7591 }
7592
7593 NOREF(pszInstr);
7594}
7595
7596
7597/**
7598 * Performs event injection (if any) as part of VM-entry.
7599 *
7600 * @param pVCpu The cross context virtual CPU structure.
7601 * @param pszInstr The VMX instruction name (for logging purposes).
7602 */
7603static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7604{
7605 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7606
7607 /*
7608 * Inject events.
7609 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7610 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7611 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7612 * the actually delivery of this event.
7613 *
7614 * See Intel spec. 26.5 "Event Injection".
7615 */
7616 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7617 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7618
7619 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7620 if (fEntryIntInfoValid)
7621 {
7622 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7623 {
7624 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7625 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7626 }
7627 else
7628 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7629 pVCpu->cpum.GstCtx.cr2);
7630
7631 /*
7632 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7633 *
7634 * However, we do it here on VM-entry as well because while it isn't visible to guest
7635 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7636 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7637 *
7638 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7639 */
7640 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7641 }
7642 else
7643 {
7644 /*
7645 * Inject any pending guest debug exception.
7646 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7647 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7648 */
7649 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7650 if (fPendingDbgXcpt)
7651 {
7652 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7653 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7654 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7655 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7656 0 /* GCPtrFaultAddress */);
7657 }
7658 }
7659
7660 NOREF(pszInstr);
7661}
7662
7663
7664/**
7665 * Initializes all read-only VMCS fields as part of VM-entry.
7666 *
7667 * @param pVCpu The cross context virtual CPU structure.
7668 */
7669static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7670{
7671 /*
7672 * Any VMCS field which we do not establish on every VM-exit but may potentially
7673 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7674 * specified to be undefined, needs to be initialized here.
7675 *
7676 * Thus, it is especially important to clear the Exit qualification field
7677 * since it must be zero for VM-exits where it is not used. Similarly, the
7678 * VM-exit interruption information field's valid bit needs to be cleared for
7679 * the same reasons.
7680 */
7681 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7682 Assert(pVmcs);
7683
7684 /* 16-bit (none currently). */
7685 /* 32-bit. */
7686 pVmcs->u32RoVmInstrError = 0;
7687 pVmcs->u32RoExitReason = 0;
7688 pVmcs->u32RoExitIntInfo = 0;
7689 pVmcs->u32RoExitIntErrCode = 0;
7690 pVmcs->u32RoIdtVectoringInfo = 0;
7691 pVmcs->u32RoIdtVectoringErrCode = 0;
7692 pVmcs->u32RoExitInstrLen = 0;
7693 pVmcs->u32RoExitInstrInfo = 0;
7694
7695 /* 64-bit. */
7696 pVmcs->u64RoGuestPhysAddr.u = 0;
7697
7698 /* Natural-width. */
7699 pVmcs->u64RoExitQual.u = 0;
7700 pVmcs->u64RoIoRcx.u = 0;
7701 pVmcs->u64RoIoRsi.u = 0;
7702 pVmcs->u64RoIoRdi.u = 0;
7703 pVmcs->u64RoIoRip.u = 0;
7704 pVmcs->u64RoGuestLinearAddr.u = 0;
7705}
7706
7707
7708/**
7709 * VMLAUNCH/VMRESUME instruction execution worker.
7710 *
7711 * @returns Strict VBox status code.
7712 * @param pVCpu The cross context virtual CPU structure.
7713 * @param cbInstr The instruction length in bytes.
7714 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7715 * VMXINSTRID_VMRESUME).
7716 *
7717 * @remarks Common VMX instruction checks are already expected to by the caller,
7718 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7719 */
7720static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7721{
7722# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7723 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7724 return VINF_EM_RAW_EMULATE_INSTR;
7725# else
7726 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7727 || uInstrId == VMXINSTRID_VMRESUME);
7728 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7729
7730 /* Nested-guest intercept. */
7731 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7732 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7733
7734 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7735
7736 /*
7737 * Basic VM-entry checks.
7738 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7739 * The checks following that do not have to follow a specific order.
7740 *
7741 * See Intel spec. 26.1 "Basic VM-entry Checks".
7742 */
7743
7744 /* CPL. */
7745 if (pVCpu->iem.s.uCpl == 0)
7746 { /* likely */ }
7747 else
7748 {
7749 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7750 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7751 return iemRaiseGeneralProtectionFault0(pVCpu);
7752 }
7753
7754 /* Current VMCS valid. */
7755 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7756 { /* likely */ }
7757 else
7758 {
7759 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7760 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7761 iemVmxVmFailInvalid(pVCpu);
7762 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7763 return VINF_SUCCESS;
7764 }
7765
7766 /* Current VMCS is not a shadow VMCS. */
7767 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7768 { /* likely */ }
7769 else
7770 {
7771 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7772 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7773 iemVmxVmFailInvalid(pVCpu);
7774 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7775 return VINF_SUCCESS;
7776 }
7777
7778 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7779 * use block-by-STI here which is not quite correct. */
7780 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7781 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7782 { /* likely */ }
7783 else
7784 {
7785 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7786 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7787 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7788 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7789 return VINF_SUCCESS;
7790 }
7791
7792 if (uInstrId == VMXINSTRID_VMLAUNCH)
7793 {
7794 /* VMLAUNCH with non-clear VMCS. */
7795 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7796 { /* likely */ }
7797 else
7798 {
7799 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7800 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7801 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7802 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7803 return VINF_SUCCESS;
7804 }
7805 }
7806 else
7807 {
7808 /* VMRESUME with non-launched VMCS. */
7809 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7810 { /* likely */ }
7811 else
7812 {
7813 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7814 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7815 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7816 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7817 return VINF_SUCCESS;
7818 }
7819 }
7820
7821 /*
7822 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7823 * while entering VMX non-root mode. We do some of this while checking VM-execution
7824 * controls. The nested hypervisor should not make assumptions and cannot expect
7825 * predictable behavior if changes to these structures are made in guest memory while
7826 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7827 * modify them anyway as we cache them in host memory.
7828 *
7829 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7830 */
7831 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7832 Assert(pVmcs);
7833 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7834
7835 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7836 if (RT_SUCCESS(rc))
7837 {
7838 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7839 if (RT_SUCCESS(rc))
7840 {
7841 /*
7842 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7843 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7844 * ones that may occur during VM-entry below).
7845 */
7846 iemVmxVmentryInitReadOnlyFields(pVCpu);
7847
7848 /*
7849 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7850 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7851 * VM-exit when required.
7852 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7853 */
7854 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7855
7856 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7857 if (RT_SUCCESS(rc))
7858 {
7859 /*
7860 * We've now entered nested-guest execution.
7861 *
7862 * It is important do this prior to loading the guest state because
7863 * as part of loading the guest state, PGM (and perhaps other components
7864 * in the future) relies on detecting whether VMX non-root mode has been
7865 * entered.
7866 */
7867 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7868
7869 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7870 if (RT_SUCCESS(rc))
7871 {
7872 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7873 if (RT_SUCCESS(rc))
7874 {
7875 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7876
7877 /* VMLAUNCH instruction must update the VMCS launch state. */
7878 if (uInstrId == VMXINSTRID_VMLAUNCH)
7879 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7880
7881 /* Perform the VMX transition (PGM updates). */
7882 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7883 if (rcStrict == VINF_SUCCESS)
7884 { /* likely */ }
7885 else if (RT_SUCCESS(rcStrict))
7886 {
7887 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7888 VBOXSTRICTRC_VAL(rcStrict)));
7889 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7890 }
7891 else
7892 {
7893 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7894 return rcStrict;
7895 }
7896
7897 /* Paranoia. */
7898 Assert(rcStrict == VINF_SUCCESS);
7899
7900 /*
7901 * The priority of potential VM-exits during VM-entry is important.
7902 * The priorities of VM-exits and events are listed from highest
7903 * to lowest as follows:
7904 *
7905 * 1. Event injection.
7906 * 2. Trap on task-switch (T flag set in TSS).
7907 * 3. TPR below threshold / APIC-write.
7908 * 4. SMI, INIT.
7909 * 5. MTF exit.
7910 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7911 * 7. VMX-preemption timer.
7912 * 9. NMI-window exit.
7913 * 10. NMI injection.
7914 * 11. Interrupt-window exit.
7915 * 12. Virtual-interrupt injection.
7916 * 13. Interrupt injection.
7917 * 14. Process next instruction (fetch, decode, execute).
7918 */
7919
7920 /* Setup VMX-preemption timer. */
7921 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7922
7923 /* Setup monitor-trap flag. */
7924 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7925
7926 /* Setup NMI-window exiting. */
7927 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7928
7929 /* Setup interrupt-window exiting. */
7930 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7931
7932 /*
7933 * Inject any event that the nested hypervisor wants to inject.
7934 * Note! We cannot immediately perform the event injection here as we may have
7935 * pending PGM operations to perform due to switching page tables and/or
7936 * mode.
7937 */
7938 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7939
7940# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7941 /* Reschedule to IEM-only execution of the nested-guest. */
7942 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7943 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7944 if (rcSched != VINF_SUCCESS)
7945 iemSetPassUpStatus(pVCpu, rcSched);
7946# endif
7947
7948 /* Finally, done. */
7949 LogFlow(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
7950 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7951 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7952 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
7953 return VINF_SUCCESS;
7954 }
7955 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7956 }
7957 }
7958 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7959 }
7960
7961 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7962 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7963 return VINF_SUCCESS;
7964 }
7965
7966 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7967 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7968 return VINF_SUCCESS;
7969# endif
7970}
7971
7972
7973/**
7974 * Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
7975 *
7976 * @returns Strict VBox status code.
7977 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7978 * @param cbInstr The instruction length in bytes.
7979 * @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
7980 * VMXINSTRID_VMRESUME).
7981 * @thread EMT(pVCpu)
7982 */
7983VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7984{
7985 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
7986 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
7987
7988 iemInitExec(pVCpu, false /*fBypassHandlers*/);
7989 VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
7990 Assert(!pVCpu->iem.s.cActiveMappings);
7991 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
7992}
7993
7994
7995/**
7996 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7997 * (causes a VM-exit) or not.
7998 *
7999 * @returns @c true if the instruction is intercepted, @c false otherwise.
8000 * @param pVCpu The cross context virtual CPU structure.
8001 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
8002 * VMX_EXIT_WRMSR).
8003 * @param idMsr The MSR.
8004 */
8005bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
8006{
8007 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
8008 Assert( uExitReason == VMX_EXIT_RDMSR
8009 || uExitReason == VMX_EXIT_WRMSR);
8010
8011 /* Consult the MSR bitmap if the feature is supported. */
8012 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
8013 Assert(pVmcs);
8014 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
8015 {
8016 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
8017 if (uExitReason == VMX_EXIT_RDMSR)
8018 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
8019 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
8020 }
8021
8022 /* Without MSR bitmaps, all MSR accesses are intercepted. */
8023 return true;
8024}
8025
8026
8027/**
8028 * VMREAD instruction execution worker that does not perform any validation checks.
8029 *
8030 * Callers are expected to have performed the necessary checks and to ensure the
8031 * VMREAD will succeed.
8032 *
8033 * @param pVmcs Pointer to the virtual VMCS.
8034 * @param pu64Dst Where to write the VMCS value.
8035 * @param u64VmcsField The VMCS field.
8036 *
8037 * @remarks May be called with interrupts disabled.
8038 */
8039static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
8040{
8041 VMXVMCSFIELD VmcsField;
8042 VmcsField.u = u64VmcsField;
8043 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8044 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8045 uint8_t const uWidthType = (uWidth << 2) | uType;
8046 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8047 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8048 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8049 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8050 uWidth, uType, uIndex, uIndex));
8051 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8052
8053 /*
8054 * Read the VMCS component based on the field's effective width.
8055 *
8056 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8057 * indicates high bits (little endian).
8058 *
8059 * Note! The caller is responsible to trim the result and update registers
8060 * or memory locations are required. Here we just zero-extend to the largest
8061 * type (i.e. 64-bits).
8062 */
8063 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
8064 uint8_t const *pbField = pbVmcs + offField;
8065 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8066 switch (uEffWidth)
8067 {
8068 case VMX_VMCSFIELD_WIDTH_64BIT:
8069 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
8070 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
8071 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
8072 }
8073}
8074
8075/**
8076 * Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8077 *
8078 * It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8079 * are performed. Bounds checks are strict builds only.
8080 *
8081 * @param pVmcs Pointer to the virtual VMCS.
8082 * @param u64VmcsField The VMCS field.
8083 * @param pu64Dst Where to store the VMCS value.
8084 *
8085 * @remarks May be called with interrupts disabled.
8086 * @todo This should probably be moved to CPUM someday.
8087 */
8088VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8089{
8090 AssertPtr(pVmcs);
8091 AssertPtr(pu64Dst);
8092 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8093}
8094
8095
8096/**
8097 * VMREAD common (memory/register) instruction execution worker.
8098 *
8099 * @returns Strict VBox status code.
8100 * @param pVCpu The cross context virtual CPU structure.
8101 * @param cbInstr The instruction length in bytes.
8102 * @param pu64Dst Where to write the VMCS value (only updated when
8103 * VINF_SUCCESS is returned).
8104 * @param u64VmcsField The VMCS field.
8105 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8106 * NULL.
8107 */
8108static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8109 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8110{
8111 /* Nested-guest intercept. */
8112 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8113 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8114 {
8115 if (pExitInfo)
8116 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8117 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8118 }
8119
8120 /* CPL. */
8121 if (pVCpu->iem.s.uCpl == 0)
8122 { /* likely */ }
8123 else
8124 {
8125 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8126 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8127 return iemRaiseGeneralProtectionFault0(pVCpu);
8128 }
8129
8130 /* VMCS pointer in root mode. */
8131 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8132 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8133 { /* likely */ }
8134 else
8135 {
8136 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8137 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8138 iemVmxVmFailInvalid(pVCpu);
8139 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8140 return VINF_SUCCESS;
8141 }
8142
8143 /* VMCS-link pointer in non-root mode. */
8144 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8145 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8146 { /* likely */ }
8147 else
8148 {
8149 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8150 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8151 iemVmxVmFailInvalid(pVCpu);
8152 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8153 return VINF_SUCCESS;
8154 }
8155
8156 /* Supported VMCS field. */
8157 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8158 { /* likely */ }
8159 else
8160 {
8161 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8162 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8163 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8164 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8165 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8166 return VINF_SUCCESS;
8167 }
8168
8169 /*
8170 * Reading from the current or shadow VMCS.
8171 */
8172 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8173 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8174 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8175 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8176 return VINF_SUCCESS;
8177}
8178
8179
8180/**
8181 * VMREAD (64-bit register) instruction execution worker.
8182 *
8183 * @returns Strict VBox status code.
8184 * @param pVCpu The cross context virtual CPU structure.
8185 * @param cbInstr The instruction length in bytes.
8186 * @param pu64Dst Where to store the VMCS field's value.
8187 * @param u64VmcsField The VMCS field.
8188 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8189 * NULL.
8190 */
8191static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8192 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8193{
8194 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8195 if (rcStrict == VINF_SUCCESS)
8196 {
8197 iemVmxVmSucceed(pVCpu);
8198 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8199 return VINF_SUCCESS;
8200 }
8201
8202 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8203 return rcStrict;
8204}
8205
8206
8207/**
8208 * VMREAD (32-bit register) instruction execution worker.
8209 *
8210 * @returns Strict VBox status code.
8211 * @param pVCpu The cross context virtual CPU structure.
8212 * @param cbInstr The instruction length in bytes.
8213 * @param pu32Dst Where to store the VMCS field's value.
8214 * @param u32VmcsField The VMCS field.
8215 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8216 * NULL.
8217 */
8218static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8219 uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8220{
8221 uint64_t u64Dst;
8222 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8223 if (rcStrict == VINF_SUCCESS)
8224 {
8225 *pu32Dst = u64Dst;
8226 iemVmxVmSucceed(pVCpu);
8227 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8228 return VINF_SUCCESS;
8229 }
8230
8231 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8232 return rcStrict;
8233}
8234
8235
8236/**
8237 * VMREAD (memory) instruction execution worker.
8238 *
8239 * @returns Strict VBox status code.
8240 * @param pVCpu The cross context virtual CPU structure.
8241 * @param cbInstr The instruction length in bytes.
8242 * @param iEffSeg The effective segment register to use with @a u64Val.
8243 * Pass UINT8_MAX if it is a register access.
8244 * @param GCPtrDst The guest linear address to store the VMCS field's
8245 * value.
8246 * @param u64VmcsField The VMCS field.
8247 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8248 * NULL.
8249 */
8250static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8251 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8252{
8253 uint64_t u64Dst;
8254 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8255 if (rcStrict == VINF_SUCCESS)
8256 {
8257 /*
8258 * Write the VMCS field's value to the location specified in guest-memory.
8259 */
8260 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8261 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8262 else
8263 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8264 if (rcStrict == VINF_SUCCESS)
8265 {
8266 iemVmxVmSucceed(pVCpu);
8267 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8268 return VINF_SUCCESS;
8269 }
8270
8271 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8272 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8273 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8274 return rcStrict;
8275 }
8276
8277 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8278 return rcStrict;
8279}
8280
8281
8282/**
8283 * Interface for HM and EM to emulate the VMREAD instruction.
8284 *
8285 * @returns Strict VBox status code.
8286 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8287 * @param pExitInfo Pointer to the VM-exit information.
8288 * @thread EMT(pVCpu)
8289 */
8290VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8291{
8292 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8293 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8294 Assert(pExitInfo);
8295
8296 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8297
8298 VBOXSTRICTRC rcStrict;
8299 uint8_t const cbInstr = pExitInfo->cbInstr;
8300 bool const fIs64BitMode = RT_BOOL(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
8301 uint64_t const u64FieldEnc = fIs64BitMode
8302 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8303 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8304 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8305 {
8306 if (fIs64BitMode)
8307 {
8308 uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8309 rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8310 }
8311 else
8312 {
8313 uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8314 rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8315 }
8316 }
8317 else
8318 {
8319 RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8320 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8321 rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8322 }
8323 Assert(!pVCpu->iem.s.cActiveMappings);
8324 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8325}
8326
8327
8328/**
8329 * VMWRITE instruction execution worker that does not perform any validation
8330 * checks.
8331 *
8332 * Callers are expected to have performed the necessary checks and to ensure the
8333 * VMWRITE will succeed.
8334 *
8335 * @param pVmcs Pointer to the virtual VMCS.
8336 * @param u64Val The value to write.
8337 * @param u64VmcsField The VMCS field.
8338 *
8339 * @remarks May be called with interrupts disabled.
8340 */
8341static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8342{
8343 VMXVMCSFIELD VmcsField;
8344 VmcsField.u = u64VmcsField;
8345 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8346 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8347 uint8_t const uWidthType = (uWidth << 2) | uType;
8348 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8349 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8350 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8351 Assert(offField < VMX_V_VMCS_SIZE);
8352 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8353
8354 /*
8355 * Write the VMCS component based on the field's effective width.
8356 *
8357 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8358 * indicates high bits (little endian).
8359 */
8360 uint8_t *pbVmcs = (uint8_t *)pVmcs;
8361 uint8_t *pbField = pbVmcs + offField;
8362 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8363 switch (uEffWidth)
8364 {
8365 case VMX_VMCSFIELD_WIDTH_64BIT:
8366 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8367 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8368 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8369 }
8370}
8371
8372
8373/**
8374 * Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8375 *
8376 * It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8377 * are performed. Bounds checks are strict builds only.
8378 *
8379 * @param pVmcs Pointer to the virtual VMCS.
8380 * @param u64VmcsField The VMCS field.
8381 * @param u64Val The value to write.
8382 *
8383 * @remarks May be called with interrupts disabled.
8384 * @todo This should probably be moved to CPUM someday.
8385 */
8386VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8387{
8388 AssertPtr(pVmcs);
8389 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8390}
8391
8392
8393/**
8394 * VMWRITE instruction execution worker.
8395 *
8396 * @returns Strict VBox status code.
8397 * @param pVCpu The cross context virtual CPU structure.
8398 * @param cbInstr The instruction length in bytes.
8399 * @param iEffSeg The effective segment register to use with @a u64Val.
8400 * Pass UINT8_MAX if it is a register access.
8401 * @param u64Val The value to write (or guest linear address to the
8402 * value), @a iEffSeg will indicate if it's a memory
8403 * operand.
8404 * @param u64VmcsField The VMCS field.
8405 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8406 * NULL.
8407 */
8408static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8409 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8410{
8411 /* Nested-guest intercept. */
8412 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8413 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8414 {
8415 if (pExitInfo)
8416 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8417 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8418 }
8419
8420 /* CPL. */
8421 if (pVCpu->iem.s.uCpl == 0)
8422 { /* likely */ }
8423 else
8424 {
8425 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8426 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8427 return iemRaiseGeneralProtectionFault0(pVCpu);
8428 }
8429
8430 /* VMCS pointer in root mode. */
8431 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8432 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8433 { /* likely */ }
8434 else
8435 {
8436 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8437 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8438 iemVmxVmFailInvalid(pVCpu);
8439 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8440 return VINF_SUCCESS;
8441 }
8442
8443 /* VMCS-link pointer in non-root mode. */
8444 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8445 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8446 { /* likely */ }
8447 else
8448 {
8449 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8450 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8451 iemVmxVmFailInvalid(pVCpu);
8452 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8453 return VINF_SUCCESS;
8454 }
8455
8456 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8457 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8458 if (!fIsRegOperand)
8459 {
8460 /* Read the value from the specified guest memory location. */
8461 VBOXSTRICTRC rcStrict;
8462 RTGCPTR const GCPtrVal = u64Val;
8463 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8464 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8465 else
8466 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8467 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8468 {
8469 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8470 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8471 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8472 return rcStrict;
8473 }
8474 }
8475 else
8476 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8477
8478 /* Supported VMCS field. */
8479 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8480 { /* likely */ }
8481 else
8482 {
8483 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8484 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8485 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8486 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8487 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8488 return VINF_SUCCESS;
8489 }
8490
8491 /* Read-only VMCS field. */
8492 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8493 if ( !fIsFieldReadOnly
8494 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8495 { /* likely */ }
8496 else
8497 {
8498 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8499 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8500 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8501 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8502 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8503 return VINF_SUCCESS;
8504 }
8505
8506 /*
8507 * Write to the current or shadow VMCS.
8508 */
8509 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8510 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8511 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8512 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8513 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8514
8515 if ( !fInVmxNonRootMode
8516 && VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8517 {
8518 /* Notify HM that the VMCS content might have changed. */
8519 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8520 }
8521
8522 iemVmxVmSucceed(pVCpu);
8523 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8524 return VINF_SUCCESS;
8525}
8526
8527
8528/**
8529 * Interface for HM and EM to emulate the VMWRITE instruction.
8530 *
8531 * @returns Strict VBox status code.
8532 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8533 * @param pExitInfo Pointer to the VM-exit information.
8534 * @thread EMT(pVCpu)
8535 */
8536VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8537{
8538 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8539 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8540 Assert(pExitInfo);
8541
8542 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8543
8544 uint64_t u64Val;
8545 uint8_t iEffSeg;
8546 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8547 {
8548 u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8549 iEffSeg = UINT8_MAX;
8550 }
8551 else
8552 {
8553 u64Val = pExitInfo->GCPtrEffAddr;
8554 iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8555 }
8556 uint8_t const cbInstr = pExitInfo->cbInstr;
8557 uint64_t const u64FieldEnc = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
8558 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8559 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8560 VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8561 Assert(!pVCpu->iem.s.cActiveMappings);
8562 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8563}
8564
8565
8566/**
8567 * VMCLEAR instruction execution worker.
8568 *
8569 * @returns Strict VBox status code.
8570 * @param pVCpu The cross context virtual CPU structure.
8571 * @param cbInstr The instruction length in bytes.
8572 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8573 * @param GCPtrVmcs The linear address of the VMCS pointer.
8574 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8575 *
8576 * @remarks Common VMX instruction checks are already expected to by the caller,
8577 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8578 */
8579static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8580 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8581{
8582 /* Nested-guest intercept. */
8583 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8584 {
8585 if (pExitInfo)
8586 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8587 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8588 }
8589
8590 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8591
8592 /* CPL. */
8593 if (pVCpu->iem.s.uCpl == 0)
8594 { /* likely */ }
8595 else
8596 {
8597 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8598 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8599 return iemRaiseGeneralProtectionFault0(pVCpu);
8600 }
8601
8602 /* Get the VMCS pointer from the location specified by the source memory operand. */
8603 RTGCPHYS GCPhysVmcs;
8604 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8605 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8606 { /* likely */ }
8607 else
8608 {
8609 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8610 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8611 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8612 return rcStrict;
8613 }
8614
8615 /* VMCS pointer alignment. */
8616 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8617 { /* likely */ }
8618 else
8619 {
8620 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8621 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8622 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8623 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8624 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8625 return VINF_SUCCESS;
8626 }
8627
8628 /* VMCS physical-address width limits. */
8629 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8630 { /* likely */ }
8631 else
8632 {
8633 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8634 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8635 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8636 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8637 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8638 return VINF_SUCCESS;
8639 }
8640
8641 /* VMCS is not the VMXON region. */
8642 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8643 { /* likely */ }
8644 else
8645 {
8646 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8647 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8648 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8649 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8650 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8651 return VINF_SUCCESS;
8652 }
8653
8654 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8655 restriction imposed by our implementation. */
8656 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8657 { /* likely */ }
8658 else
8659 {
8660 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8661 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8662 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8663 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8664 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8665 return VINF_SUCCESS;
8666 }
8667
8668 /*
8669 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8670 *
8671 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8672 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8673 * to 'clear'.
8674 */
8675 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8676 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8677 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8678 {
8679 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8680 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8681 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8682 }
8683 else
8684 {
8685 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8686 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8687 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8688 if (RT_FAILURE(rcStrict))
8689 return rcStrict;
8690 }
8691
8692 iemVmxVmSucceed(pVCpu);
8693 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8694 return VINF_SUCCESS;
8695}
8696
8697
8698/**
8699 * Interface for HM and EM to emulate the VMCLEAR instruction.
8700 *
8701 * @returns Strict VBox status code.
8702 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8703 * @param pExitInfo Pointer to the VM-exit information.
8704 * @thread EMT(pVCpu)
8705 */
8706VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8707{
8708 Assert(pExitInfo);
8709 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8710 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8711
8712 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8713
8714 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8715 uint8_t const cbInstr = pExitInfo->cbInstr;
8716 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8717 VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8718 Assert(!pVCpu->iem.s.cActiveMappings);
8719 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8720}
8721
8722
8723/**
8724 * VMPTRST instruction execution worker.
8725 *
8726 * @returns Strict VBox status code.
8727 * @param pVCpu The cross context virtual CPU structure.
8728 * @param cbInstr The instruction length in bytes.
8729 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8730 * @param GCPtrVmcs The linear address of where to store the current VMCS
8731 * pointer.
8732 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8733 *
8734 * @remarks Common VMX instruction checks are already expected to by the caller,
8735 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8736 */
8737static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8738 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8739{
8740 /* Nested-guest intercept. */
8741 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8742 {
8743 if (pExitInfo)
8744 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8745 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8746 }
8747
8748 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8749
8750 /* CPL. */
8751 if (pVCpu->iem.s.uCpl == 0)
8752 { /* likely */ }
8753 else
8754 {
8755 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8756 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8757 return iemRaiseGeneralProtectionFault0(pVCpu);
8758 }
8759
8760 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8761 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8762 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8763 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8764 {
8765 iemVmxVmSucceed(pVCpu);
8766 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8767 return rcStrict;
8768 }
8769
8770 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8771 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8772 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8773 return rcStrict;
8774}
8775
8776
8777/**
8778 * Interface for HM and EM to emulate the VMPTRST instruction.
8779 *
8780 * @returns Strict VBox status code.
8781 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8782 * @param pExitInfo Pointer to the VM-exit information.
8783 * @thread EMT(pVCpu)
8784 */
8785VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8786{
8787 Assert(pExitInfo);
8788 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8789 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8790
8791 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8792
8793 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8794 uint8_t const cbInstr = pExitInfo->cbInstr;
8795 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8796 VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8797 Assert(!pVCpu->iem.s.cActiveMappings);
8798 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8799}
8800
8801
8802/**
8803 * VMPTRLD instruction execution worker.
8804 *
8805 * @returns Strict VBox status code.
8806 * @param pVCpu The cross context virtual CPU structure.
8807 * @param cbInstr The instruction length in bytes.
8808 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8809 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8810 *
8811 * @remarks Common VMX instruction checks are already expected to by the caller,
8812 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8813 */
8814static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8815 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8816{
8817 /* Nested-guest intercept. */
8818 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8819 {
8820 if (pExitInfo)
8821 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8822 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8823 }
8824
8825 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8826
8827 /* CPL. */
8828 if (pVCpu->iem.s.uCpl == 0)
8829 { /* likely */ }
8830 else
8831 {
8832 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8833 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8834 return iemRaiseGeneralProtectionFault0(pVCpu);
8835 }
8836
8837 /* Get the VMCS pointer from the location specified by the source memory operand. */
8838 RTGCPHYS GCPhysVmcs;
8839 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8840 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8841 { /* likely */ }
8842 else
8843 {
8844 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8845 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8846 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8847 return rcStrict;
8848 }
8849
8850 /* VMCS pointer alignment. */
8851 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8852 { /* likely */ }
8853 else
8854 {
8855 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8856 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8857 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8858 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8859 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8860 return VINF_SUCCESS;
8861 }
8862
8863 /* VMCS physical-address width limits. */
8864 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8865 { /* likely */ }
8866 else
8867 {
8868 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8869 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8870 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8871 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8872 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8873 return VINF_SUCCESS;
8874 }
8875
8876 /* VMCS is not the VMXON region. */
8877 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8878 { /* likely */ }
8879 else
8880 {
8881 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8882 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8883 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8884 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8885 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8886 return VINF_SUCCESS;
8887 }
8888
8889 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8890 restriction imposed by our implementation. */
8891 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8892 { /* likely */ }
8893 else
8894 {
8895 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8896 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8897 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8898 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8899 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8900 return VINF_SUCCESS;
8901 }
8902
8903 /* Read just the VMCS revision from the VMCS. */
8904 VMXVMCSREVID VmcsRevId;
8905 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8906 if (RT_SUCCESS(rc))
8907 { /* likely */ }
8908 else
8909 {
8910 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8911 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8912 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8913 return rc;
8914 }
8915
8916 /*
8917 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8918 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8919 */
8920 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8921 && ( !VmcsRevId.n.fIsShadowVmcs
8922 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8923 { /* likely */ }
8924 else
8925 {
8926 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8927 {
8928 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8929 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8930 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8931 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8932 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8933 return VINF_SUCCESS;
8934 }
8935
8936 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8937 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8938 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8939 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8940 return VINF_SUCCESS;
8941 }
8942
8943 /*
8944 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8945 * the cache of an existing, current VMCS back to guest memory before loading a new,
8946 * different current VMCS.
8947 */
8948 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8949 {
8950 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8951 {
8952 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8953 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8954 }
8955
8956 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8957 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8958 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8959 if (RT_SUCCESS(rc))
8960 {
8961 /* Notify HM that a new, current VMCS is loaded. */
8962 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8963 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8964 }
8965 else
8966 {
8967 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8968 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8969 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8970 return rc;
8971 }
8972 }
8973
8974 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8975 iemVmxVmSucceed(pVCpu);
8976 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8977 return VINF_SUCCESS;
8978}
8979
8980
8981/**
8982 * Interface for HM and EM to emulate the VMPTRLD instruction.
8983 *
8984 * @returns Strict VBox status code.
8985 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8986 * @param pExitInfo Pointer to the VM-exit information.
8987 * @thread EMT(pVCpu)
8988 */
8989VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8990{
8991 Assert(pExitInfo);
8992 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8993 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8994
8995 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8996
8997 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8998 uint8_t const cbInstr = pExitInfo->cbInstr;
8999 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
9000 VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
9001 Assert(!pVCpu->iem.s.cActiveMappings);
9002 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9003}
9004
9005
9006/**
9007 * INVVPID instruction execution worker.
9008 *
9009 * @returns Strict VBox status code.
9010 * @param pVCpu The cross context virtual CPU structure.
9011 * @param cbInstr The instruction length in bytes.
9012 * @param iEffSeg The segment of the invvpid descriptor.
9013 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
9014 * @param u64InvvpidType The invalidation type.
9015 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9016 * NULL.
9017 *
9018 * @remarks Common VMX instruction checks are already expected to by the caller,
9019 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9020 */
9021VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
9022 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9023{
9024 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
9025 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
9026 return iemRaiseUndefinedOpcode(pVCpu);
9027
9028 /* Nested-guest intercept. */
9029 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9030 {
9031 if (pExitInfo)
9032 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9033 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
9034 }
9035
9036 /* CPL. */
9037 if (pVCpu->iem.s.uCpl != 0)
9038 {
9039 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
9040 return iemRaiseGeneralProtectionFault0(pVCpu);
9041 }
9042
9043 /*
9044 * Validate INVVPID invalidation type.
9045 *
9046 * The instruction specifies exactly ONE of the supported invalidation types.
9047 *
9048 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9049 * supported. In theory, it's possible for a CPU to not support flushing individual
9050 * addresses but all the other types or any other combination. We do not take any
9051 * shortcuts here by assuming the types we currently expose to the guest.
9052 */
9053 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9054 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9055 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9056 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9057 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9058 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9059
9060 bool afSupportedTypes[4];
9061 afSupportedTypes[0] = fTypeIndivAddr;
9062 afSupportedTypes[1] = fTypeSingleCtx;
9063 afSupportedTypes[2] = fTypeAllCtx;
9064 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9065
9066 if ( fInvvpidSupported
9067 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9068 && afSupportedTypes[u64InvvpidType & 3])
9069 { /* likely */ }
9070 else
9071 {
9072 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9073 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9074 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9075 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9076 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9077 return VINF_SUCCESS;
9078 }
9079
9080 /*
9081 * Fetch the invvpid descriptor from guest memory.
9082 */
9083 RTUINT128U uDesc;
9084 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9085 if (rcStrict == VINF_SUCCESS)
9086 {
9087 /*
9088 * Validate the descriptor.
9089 */
9090 if (uDesc.s.Lo <= 0xffff)
9091 { /* likely */ }
9092 else
9093 {
9094 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9095 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9096 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9097 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9098 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9099 return VINF_SUCCESS;
9100 }
9101
9102 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9103 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9104 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
9105 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9106 switch (u64InvvpidType)
9107 {
9108 case VMXTLBFLUSHVPID_INDIV_ADDR:
9109 {
9110 if (uVpid != 0)
9111 {
9112 if (IEM_IS_CANONICAL(GCPtrInvAddr))
9113 {
9114 /* Invalidate mappings for the linear address tagged with VPID. */
9115 /** @todo PGM support for VPID? Currently just flush everything. */
9116 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9117 iemVmxVmSucceed(pVCpu);
9118 }
9119 else
9120 {
9121 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9122 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9123 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9124 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9125 }
9126 }
9127 else
9128 {
9129 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9130 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9131 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9132 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9133 }
9134 break;
9135 }
9136
9137 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9138 {
9139 if (uVpid != 0)
9140 {
9141 /* Invalidate all mappings with VPID. */
9142 /** @todo PGM support for VPID? Currently just flush everything. */
9143 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9144 iemVmxVmSucceed(pVCpu);
9145 }
9146 else
9147 {
9148 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9149 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9150 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9151 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9152 }
9153 break;
9154 }
9155
9156 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9157 {
9158 /* Invalidate all mappings with non-zero VPIDs. */
9159 /** @todo PGM support for VPID? Currently just flush everything. */
9160 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9161 iemVmxVmSucceed(pVCpu);
9162 break;
9163 }
9164
9165 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9166 {
9167 if (uVpid != 0)
9168 {
9169 /* Invalidate all mappings with VPID except global translations. */
9170 /** @todo PGM support for VPID? Currently just flush everything. */
9171 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9172 iemVmxVmSucceed(pVCpu);
9173 }
9174 else
9175 {
9176 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9177 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9178 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9179 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9180 }
9181 break;
9182 }
9183 IEM_NOT_REACHED_DEFAULT_CASE_RET();
9184 }
9185 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9186 }
9187 return rcStrict;
9188}
9189
9190
9191/**
9192 * Interface for HM and EM to emulate the INVVPID instruction.
9193 *
9194 * @returns Strict VBox status code.
9195 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9196 * @param pExitInfo Pointer to the VM-exit information.
9197 * @thread EMT(pVCpu)
9198 */
9199VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9200{
9201 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9202 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9203 Assert(pExitInfo);
9204
9205 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9206
9207 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9208 uint8_t const cbInstr = pExitInfo->cbInstr;
9209 RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9210 uint64_t const u64InvvpidType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9211 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9212 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9213 VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9214 Assert(!pVCpu->iem.s.cActiveMappings);
9215 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9216}
9217
9218#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9219
9220/**
9221 * INVEPT instruction execution worker.
9222 *
9223 * @returns Strict VBox status code.
9224 * @param pVCpu The cross context virtual CPU structure.
9225 * @param cbInstr The instruction length in bytes.
9226 * @param iEffSeg The segment of the invept descriptor.
9227 * @param GCPtrInveptDesc The address of invept descriptor.
9228 * @param u64InveptType The invalidation type.
9229 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9230 * NULL.
9231 *
9232 * @remarks Common VMX instruction checks are already expected to by the caller,
9233 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9234 */
9235static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9236 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9237{
9238 /* Check if EPT is supported, otherwise raise #UD. */
9239 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9240 return iemRaiseUndefinedOpcode(pVCpu);
9241
9242 /* Nested-guest intercept. */
9243 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9244 {
9245 if (pExitInfo)
9246 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9247 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9248 }
9249
9250 /* CPL. */
9251 if (pVCpu->iem.s.uCpl != 0)
9252 {
9253 Log(("invept: CPL != 0 -> #GP(0)\n"));
9254 return iemRaiseGeneralProtectionFault0(pVCpu);
9255 }
9256
9257 /*
9258 * Validate INVEPT invalidation type.
9259 *
9260 * The instruction specifies exactly ONE of the supported invalidation types.
9261 *
9262 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9263 * supported. In theory, it's possible for a CPU to not support flushing individual
9264 * addresses but all the other types or any other combination. We do not take any
9265 * shortcuts here by assuming the types we currently expose to the guest.
9266 */
9267 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9268 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9269 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9270 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9271
9272 bool afSupportedTypes[4];
9273 afSupportedTypes[0] = false;
9274 afSupportedTypes[1] = fTypeSingleCtx;
9275 afSupportedTypes[2] = fTypeAllCtx;
9276 afSupportedTypes[3] = false;
9277
9278 if ( fInveptSupported
9279 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9280 && afSupportedTypes[u64InveptType & 3])
9281 { /* likely */ }
9282 else
9283 {
9284 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9285 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9286 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9287 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9288 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9289 return VINF_SUCCESS;
9290 }
9291
9292 /*
9293 * Fetch the invept descriptor from guest memory.
9294 */
9295 RTUINT128U uDesc;
9296 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9297 if (rcStrict == VINF_SUCCESS)
9298 {
9299 /*
9300 * Validate the descriptor.
9301 *
9302 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9303 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9304 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9305 * better to be strict in our emulation until proven otherwise.
9306 */
9307 if (uDesc.s.Hi)
9308 {
9309 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9310 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9311 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9312 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9313 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9314 return VINF_SUCCESS;
9315 }
9316
9317 /*
9318 * Flush TLB mappings based on the EPT type.
9319 */
9320 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9321 {
9322 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9323 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9324 if (RT_SUCCESS(rc))
9325 { /* likely */ }
9326 else
9327 {
9328 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9329 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9330 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9331 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9332 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9333 return VINF_SUCCESS;
9334 }
9335 }
9336
9337 /** @todo PGM support for EPT tags? Currently just flush everything. */
9338 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9339 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9340 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9341
9342 iemVmxVmSucceed(pVCpu);
9343 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9344 }
9345
9346 return rcStrict;
9347}
9348
9349
9350/**
9351 * Interface for HM and EM to emulate the INVEPT instruction.
9352 *
9353 * @returns Strict VBox status code.
9354 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9355 * @param pExitInfo Pointer to the VM-exit information.
9356 * @thread EMT(pVCpu)
9357 */
9358VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9359{
9360 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9361 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9362 Assert(pExitInfo);
9363
9364 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9365
9366 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9367 uint8_t const cbInstr = pExitInfo->cbInstr;
9368 RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9369 uint64_t const u64InveptType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9370 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9371 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9372 VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9373 Assert(!pVCpu->iem.s.cActiveMappings);
9374 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9375}
9376
9377#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9378
9379/**
9380 * VMXON instruction execution worker.
9381 *
9382 * @returns Strict VBox status code.
9383 * @param pVCpu The cross context virtual CPU structure.
9384 * @param cbInstr The instruction length in bytes.
9385 * @param iEffSeg The effective segment register to use with @a
9386 * GCPtrVmxon.
9387 * @param GCPtrVmxon The linear address of the VMXON pointer.
9388 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9389 *
9390 * @remarks Common VMX instruction checks are already expected to by the caller,
9391 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9392 */
9393static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9394 RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9395{
9396 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9397 {
9398 /* CPL. */
9399 if (pVCpu->iem.s.uCpl == 0)
9400 { /* likely */ }
9401 else
9402 {
9403 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9404 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9405 return iemRaiseGeneralProtectionFault0(pVCpu);
9406 }
9407
9408 /* A20M (A20 Masked) mode. */
9409 if (PGMPhysIsA20Enabled(pVCpu))
9410 { /* likely */ }
9411 else
9412 {
9413 Log(("vmxon: A20M mode -> #GP(0)\n"));
9414 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9415 return iemRaiseGeneralProtectionFault0(pVCpu);
9416 }
9417
9418 /* CR0. */
9419 {
9420 /*
9421 * CR0 MB1 bits.
9422 *
9423 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9424 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9425 * when the guest running in VMX non-root mode with unrestricted-guest control
9426 * enabled in the VMCS.
9427 */
9428 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9429 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9430 { /* likely */ }
9431 else
9432 {
9433 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9434 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9435 return iemRaiseGeneralProtectionFault0(pVCpu);
9436 }
9437
9438 /* CR0 MBZ bits. */
9439 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9440 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9441 { /* likely */ }
9442 else
9443 {
9444 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9445 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9446 return iemRaiseGeneralProtectionFault0(pVCpu);
9447 }
9448 }
9449
9450 /* CR4. */
9451 {
9452 /* CR4 MB1 bits. */
9453 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9454 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9455 { /* likely */ }
9456 else
9457 {
9458 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9459 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9460 return iemRaiseGeneralProtectionFault0(pVCpu);
9461 }
9462
9463 /* CR4 MBZ bits. */
9464 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9465 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9466 { /* likely */ }
9467 else
9468 {
9469 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9470 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9471 return iemRaiseGeneralProtectionFault0(pVCpu);
9472 }
9473 }
9474
9475 /* Feature control MSR's LOCK and VMXON bits. */
9476 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9477 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9478 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9479 { /* likely */ }
9480 else
9481 {
9482 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9483 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9484 return iemRaiseGeneralProtectionFault0(pVCpu);
9485 }
9486
9487 /* Get the VMXON pointer from the location specified by the source memory operand. */
9488 RTGCPHYS GCPhysVmxon;
9489 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9490 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9491 { /* likely */ }
9492 else
9493 {
9494 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9495 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9496 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9497 return rcStrict;
9498 }
9499
9500 /* VMXON region pointer alignment. */
9501 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9502 { /* likely */ }
9503 else
9504 {
9505 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9506 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9507 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9508 iemVmxVmFailInvalid(pVCpu);
9509 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9510 return VINF_SUCCESS;
9511 }
9512
9513 /* VMXON physical-address width limits. */
9514 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9515 { /* likely */ }
9516 else
9517 {
9518 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9519 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9520 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9521 iemVmxVmFailInvalid(pVCpu);
9522 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9523 return VINF_SUCCESS;
9524 }
9525
9526 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9527 restriction imposed by our implementation. */
9528 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9529 { /* likely */ }
9530 else
9531 {
9532 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9533 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9534 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9535 iemVmxVmFailInvalid(pVCpu);
9536 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9537 return VINF_SUCCESS;
9538 }
9539
9540 /* Read the VMCS revision ID from the VMXON region. */
9541 VMXVMCSREVID VmcsRevId;
9542 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9543 if (RT_SUCCESS(rc))
9544 { /* likely */ }
9545 else
9546 {
9547 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9548 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9549 return rc;
9550 }
9551
9552 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9553 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9554 { /* likely */ }
9555 else
9556 {
9557 /* Revision ID mismatch. */
9558 if (!VmcsRevId.n.fIsShadowVmcs)
9559 {
9560 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9561 VmcsRevId.n.u31RevisionId));
9562 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9563 iemVmxVmFailInvalid(pVCpu);
9564 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9565 return VINF_SUCCESS;
9566 }
9567
9568 /* Shadow VMCS disallowed. */
9569 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9570 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9571 iemVmxVmFailInvalid(pVCpu);
9572 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9573 return VINF_SUCCESS;
9574 }
9575
9576 /*
9577 * Record that we're in VMX operation, block INIT, block and disable A20M.
9578 */
9579 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9580 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9581 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9582
9583 /* Clear address-range monitoring. */
9584 EMMonitorWaitClear(pVCpu);
9585 /** @todo NSTVMX: Intel PT. */
9586
9587 iemVmxVmSucceed(pVCpu);
9588 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9589 return VINF_SUCCESS;
9590 }
9591 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9592 {
9593 /* Nested-guest intercept. */
9594 if (pExitInfo)
9595 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9596 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9597 }
9598
9599 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9600
9601 /* CPL. */
9602 if (pVCpu->iem.s.uCpl > 0)
9603 {
9604 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9605 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9606 return iemRaiseGeneralProtectionFault0(pVCpu);
9607 }
9608
9609 /* VMXON when already in VMX root mode. */
9610 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9611 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9612 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9613 return VINF_SUCCESS;
9614}
9615
9616
9617/**
9618 * Interface for HM and EM to emulate the VMXON instruction.
9619 *
9620 * @returns Strict VBox status code.
9621 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9622 * @param pExitInfo Pointer to the VM-exit information.
9623 * @thread EMT(pVCpu)
9624 */
9625VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9626{
9627 Assert(pExitInfo);
9628 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9629 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9630
9631 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9632
9633 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9634 uint8_t const cbInstr = pExitInfo->cbInstr;
9635 RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9636 VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9637 Assert(!pVCpu->iem.s.cActiveMappings);
9638 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9639}
9640
9641
9642/**
9643 * Implements 'VMXOFF'.
9644 *
9645 * @remarks Common VMX instruction checks are already expected to by the caller,
9646 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9647 */
9648IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9649{
9650 /* Nested-guest intercept. */
9651 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9652 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9653
9654 /* CPL. */
9655 if (pVCpu->iem.s.uCpl == 0)
9656 { /* likely */ }
9657 else
9658 {
9659 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9660 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9661 return iemRaiseGeneralProtectionFault0(pVCpu);
9662 }
9663
9664 /* Dual monitor treatment of SMIs and SMM. */
9665 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9666 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9667 { /* likely */ }
9668 else
9669 {
9670 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9671 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9672 return VINF_SUCCESS;
9673 }
9674
9675 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9676 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9677 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9678
9679 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9680 { /** @todo NSTVMX: Unblock SMI. */ }
9681
9682 EMMonitorWaitClear(pVCpu);
9683 /** @todo NSTVMX: Unblock and enable A20M. */
9684
9685 iemVmxVmSucceed(pVCpu);
9686 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9687 return VINF_SUCCESS;
9688}
9689
9690
9691/**
9692 * Interface for HM and EM to emulate the VMXOFF instruction.
9693 *
9694 * @returns Strict VBox status code.
9695 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9696 * @param cbInstr The instruction length in bytes.
9697 * @thread EMT(pVCpu)
9698 */
9699VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9700{
9701 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9702 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9703
9704 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9705 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9706 Assert(!pVCpu->iem.s.cActiveMappings);
9707 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9708}
9709
9710
9711/**
9712 * Implements 'VMXON'.
9713 */
9714IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9715{
9716 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9717}
9718
9719
9720/**
9721 * Implements 'VMLAUNCH'.
9722 */
9723IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9724{
9725 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9726}
9727
9728
9729/**
9730 * Implements 'VMRESUME'.
9731 */
9732IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9733{
9734 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9735}
9736
9737
9738/**
9739 * Implements 'VMPTRLD'.
9740 */
9741IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9742{
9743 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9744}
9745
9746
9747/**
9748 * Implements 'VMPTRST'.
9749 */
9750IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9751{
9752 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9753}
9754
9755
9756/**
9757 * Implements 'VMCLEAR'.
9758 */
9759IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9760{
9761 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9762}
9763
9764
9765/**
9766 * Implements 'VMWRITE' register.
9767 */
9768IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9769{
9770 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9771}
9772
9773
9774/**
9775 * Implements 'VMWRITE' memory.
9776 */
9777IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9778{
9779 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9780}
9781
9782
9783/**
9784 * Implements 'VMREAD' register (64-bit).
9785 */
9786IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9787{
9788 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9789}
9790
9791
9792/**
9793 * Implements 'VMREAD' register (32-bit).
9794 */
9795IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
9796{
9797 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
9798}
9799
9800
9801/**
9802 * Implements 'VMREAD' memory, 64-bit register.
9803 */
9804IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9805{
9806 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9807}
9808
9809
9810/**
9811 * Implements 'VMREAD' memory, 32-bit register.
9812 */
9813IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9814{
9815 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9816}
9817
9818
9819/**
9820 * Implements 'INVVPID'.
9821 */
9822IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9823{
9824 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9825}
9826
9827
9828#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9829/**
9830 * Implements 'INVEPT'.
9831 */
9832IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9833{
9834 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9835}
9836#endif
9837
9838
9839/**
9840 * Implements VMX's implementation of PAUSE.
9841 */
9842IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9843{
9844 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9845 {
9846 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9847 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9848 return rcStrict;
9849 }
9850
9851 /*
9852 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9853 * a VM-exit, the instruction operates normally.
9854 */
9855 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9856 return VINF_SUCCESS;
9857}
9858
9859#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9860
9861
9862/**
9863 * Implements 'VMCALL'.
9864 */
9865IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9866{
9867#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9868 /* Nested-guest intercept. */
9869 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9870 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9871#endif
9872
9873 /* Join forces with vmmcall. */
9874 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9875}
9876
9877
9878#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9879
9880/**
9881 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9882 *
9883 * @remarks The @a uUser argument is currently unused.
9884 */
9885DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9886 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9887 PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9888{
9889 RT_NOREF3(pvPhys, enmOrigin, uUser);
9890
9891 RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9892 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9893 {
9894 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9895 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9896
9897 uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9898 uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9899
9900 LogFlowFunc(("Fault at %#RGp (cbBuf=%u fAccess=%#x)\n", GCPhysFault, cbBuf, fAccess));
9901 VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9902 if (RT_FAILURE(rcStrict))
9903 return rcStrict;
9904
9905 /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9906 return VINF_SUCCESS;
9907 }
9908
9909 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9910 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9911 if (RT_FAILURE(rc))
9912 return rc;
9913
9914 /* Instruct the caller of this handler to perform the read/write as normal memory. */
9915 return VINF_PGM_HANDLER_DO_DEFAULT;
9916}
9917
9918
9919# ifndef IN_RING3
9920/**
9921 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9922 * \#PF access handler callback for guest VMX APIC-access page.}
9923 */
9924DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
9925 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9926
9927{
9928 RT_NOREF3(pVM, pRegFrame, uUser);
9929
9930 /*
9931 * Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9932 * Otherwise we must deregister the page and allow regular RAM access.
9933 * Failing to do so lands us with endless EPT VM-exits.
9934 */
9935 RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9936 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9937 {
9938 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9939 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9940
9941 /*
9942 * Check if the access causes an APIC-access VM-exit.
9943 */
9944 uint32_t fAccess;
9945 if (uErr & X86_TRAP_PF_ID)
9946 fAccess = IEM_ACCESS_INSTRUCTION;
9947 else if (uErr & X86_TRAP_PF_RW)
9948 fAccess = IEM_ACCESS_DATA_W;
9949 else
9950 fAccess = IEM_ACCESS_DATA_R;
9951
9952 RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
9953 uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
9954 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
9955 LogFlowFunc(("#PF at %#RGp (GCPhysNestedFault=%#RGp offAccess=%#x)\n", GCPhysFault, GCPhysNestedFault, offAccess));
9956 if (fIntercept)
9957 {
9958 /*
9959 * Query the source VM-exit (from the execution engine) that caused this access
9960 * within the APIC-access page. Currently only HM is supported.
9961 */
9962 AssertMsg(VM_IS_HM_ENABLED(pVM),
9963 ("VM-exit auxiliary info. fetching not supported for execution engine %d\n", pVM->bMainExecutionEngine));
9964
9965 HMEXITAUX HmExitAux;
9966 RT_ZERO(HmExitAux);
9967 int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
9968 | HMVMX_READ_EXIT_QUALIFICATION
9969 | HMVMX_READ_IDT_VECTORING_INFO
9970 | HMVMX_READ_IDT_VECTORING_ERROR_CODE);
9971 AssertRC(rc);
9972
9973 /*
9974 * Verify the VM-exit reason must be an EPT violation.
9975 * Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
9976 * Refer to @bugref{10092#c33s} for a more detailed explanation.
9977 */
9978 AssertMsgReturn(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
9979 ("Unexpected call to APIC-access page #PF handler for %#RGp offAcesss=%u uErr=%#RGx uReason=%u\n",
9980 GCPhysPage, offAccess, uErr, HmExitAux.Vmx.uReason), VERR_IEM_IPE_7);
9981
9982 /*
9983 * Construct the virtual APIC-access VM-exit.
9984 */
9985 VMXAPICACCESS enmAccess;
9986 if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
9987 {
9988 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9989 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
9990 else if (fAccess == IEM_ACCESS_INSTRUCTION)
9991 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
9992 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
9993 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
9994 else
9995 enmAccess = VMXAPICACCESS_LINEAR_READ;
9996
9997 /* For linear-address accesss the instruction length must be valid. */
9998 AssertMsg(HmExitAux.Vmx.cbInstr > 0,
9999 ("Invalid APIC-access VM-exit instruction length. cbInstr=%u\n", HmExitAux.Vmx.cbInstr));
10000 }
10001 else
10002 {
10003 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
10004 enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
10005 else
10006 {
10007 /** @todo How to distinguish between monitoring/trace vs other instructions
10008 * here? */
10009 enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
10010 }
10011
10012 /* For physical accesses the instruction length is undefined, we zero it for safety and consistency. */
10013 HmExitAux.Vmx.cbInstr = 0;
10014 }
10015
10016 VMXVEXITINFO ExitInfo;
10017 RT_ZERO(ExitInfo);
10018 ExitInfo.uReason = VMX_EXIT_APIC_ACCESS;
10019 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
10020 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
10021 ExitInfo.cbInstr = HmExitAux.Vmx.cbInstr;
10022
10023 VMXVEXITEVENTINFO ExitEventInfo;
10024 RT_ZERO(ExitEventInfo);
10025 ExitEventInfo.uIdtVectoringInfo = HmExitAux.Vmx.uIdtVectoringInfo;
10026 ExitEventInfo.uIdtVectoringErrCode = HmExitAux.Vmx.uIdtVectoringErrCode;
10027
10028 /*
10029 * Raise the APIC-access VM-exit.
10030 */
10031 LogFlowFunc(("Raising APIC-access VM-exit from #PF handler at offset %#x\n", offAccess));
10032 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
10033 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
10034 }
10035
10036 /*
10037 * The access isn't intercepted, which means it needs to be virtualized.
10038 *
10039 * This requires emulating the instruction because we need the bytes being
10040 * read/written by the instruction not just the offset being accessed within
10041 * the APIC-access page (which we derive from the faulting address).
10042 */
10043 LogFlowFunc(("Access at offset %#x not intercepted -> VINF_EM_RAW_EMULATE_INSTR\n", offAccess));
10044 return VINF_EM_RAW_EMULATE_INSTR;
10045 }
10046
10047 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
10048 int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
10049 if (RT_FAILURE(rc))
10050 return rc;
10051
10052 return VINF_SUCCESS;
10053}
10054# endif /* !IN_RING3 */
10055
10056#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10057
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use