VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp@ 96860

Last change on this file since 96860 was 96852, checked in by vboxsync, 20 months ago

IEM: Rotate the FPU stack when changing the FP TOS. Make sure stack adjustment is done before MMX instructions execute, not after.
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1/* $Id: IEMAllCImpl.cpp 96852 2022-09-26 06:06:05Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in C/C++ (code include).
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/cpum.h>
36#include <VBox/vmm/apic.h>
37#include <VBox/vmm/pdm.h>
38#include <VBox/vmm/pgm.h>
39#include <VBox/vmm/iom.h>
40#include <VBox/vmm/em.h>
41#include <VBox/vmm/hm.h>
42#include <VBox/vmm/nem.h>
43#include <VBox/vmm/gim.h>
44#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
45# include <VBox/vmm/em.h>
46# include <VBox/vmm/hm_svm.h>
47#endif
48#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
49# include <VBox/vmm/hmvmxinline.h>
50#endif
51#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
52# include <VBox/vmm/cpuidcall.h>
53#endif
54#include <VBox/vmm/tm.h>
55#include <VBox/vmm/dbgf.h>
56#include <VBox/vmm/dbgftrace.h>
57#include "IEMInternal.h"
58#include <VBox/vmm/vmcc.h>
59#include <VBox/log.h>
60#include <VBox/err.h>
61#include <VBox/param.h>
62#include <VBox/dis.h>
63#include <VBox/disopcode.h>
64#include <iprt/asm-math.h>
65#include <iprt/assert.h>
66#include <iprt/string.h>
67#include <iprt/x86.h>
68
69#include "IEMInline.h"
70
71
72/** @name Misc Helpers
73 * @{
74 */
75
76
77/**
78 * Worker function for iemHlpCheckPortIOPermission, don't call directly.
79 *
80 * @returns Strict VBox status code.
81 *
82 * @param pVCpu The cross context virtual CPU structure of the calling thread.
83 * @param u16Port The port number.
84 * @param cbOperand The operand size.
85 */
86static VBOXSTRICTRC iemHlpCheckPortIOPermissionBitmap(PVMCPUCC pVCpu, uint16_t u16Port, uint8_t cbOperand)
87{
88 /* The TSS bits we're interested in are the same on 386 and AMD64. */
89 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_BUSY == X86_SEL_TYPE_SYS_386_TSS_BUSY);
90 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_AVAIL == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
91 AssertCompileMembersAtSameOffset(X86TSS32, offIoBitmap, X86TSS64, offIoBitmap);
92 AssertCompile(sizeof(X86TSS32) == sizeof(X86TSS64));
93
94 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
95
96 /*
97 * Check the TSS type, 16-bit TSSes doesn't have any I/O permission bitmap.
98 */
99 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType);
100 if (RT_UNLIKELY( pVCpu->cpum.GstCtx.tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_BUSY
101 && pVCpu->cpum.GstCtx.tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_AVAIL))
102 {
103 Log(("iemHlpCheckPortIOPermissionBitmap: Port=%#x cb=%d - TSS type %#x (attr=%#x) has no I/O bitmap -> #GP(0)\n",
104 u16Port, cbOperand, pVCpu->cpum.GstCtx.tr.Attr.n.u4Type, pVCpu->cpum.GstCtx.tr.Attr.u));
105 return iemRaiseGeneralProtectionFault0(pVCpu);
106 }
107
108 /*
109 * Read the bitmap offset (may #PF).
110 */
111 uint16_t offBitmap;
112 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &offBitmap, UINT8_MAX,
113 pVCpu->cpum.GstCtx.tr.u64Base + RT_UOFFSETOF(X86TSS64, offIoBitmap));
114 if (rcStrict != VINF_SUCCESS)
115 {
116 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading offIoBitmap (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
117 return rcStrict;
118 }
119
120 /*
121 * The bit range from u16Port to (u16Port + cbOperand - 1), however intel
122 * describes the CPU actually reading two bytes regardless of whether the
123 * bit range crosses a byte boundrary. Thus the + 1 in the test below.
124 */
125 uint32_t offFirstBit = (uint32_t)u16Port / 8 + offBitmap;
126 /** @todo check if real CPUs ensures that offBitmap has a minimum value of
127 * for instance sizeof(X86TSS32). */
128 if (offFirstBit + 1 > pVCpu->cpum.GstCtx.tr.u32Limit) /* the limit is inclusive */
129 {
130 Log(("iemHlpCheckPortIOPermissionBitmap: offFirstBit=%#x + 1 is beyond u32Limit=%#x -> #GP(0)\n",
131 offFirstBit, pVCpu->cpum.GstCtx.tr.u32Limit));
132 return iemRaiseGeneralProtectionFault0(pVCpu);
133 }
134
135 /*
136 * Read the necessary bits.
137 */
138 /** @todo Test the assertion in the intel manual that the CPU reads two
139 * bytes. The question is how this works wrt to \#PF and \#GP on the
140 * 2nd byte when it's not required. */
141 uint16_t bmBytes = UINT16_MAX;
142 rcStrict = iemMemFetchSysU16(pVCpu, &bmBytes, UINT8_MAX, pVCpu->cpum.GstCtx.tr.u64Base + offFirstBit);
143 if (rcStrict != VINF_SUCCESS)
144 {
145 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading I/O bitmap @%#x (%Rrc)\n", offFirstBit, VBOXSTRICTRC_VAL(rcStrict)));
146 return rcStrict;
147 }
148
149 /*
150 * Perform the check.
151 */
152 uint16_t fPortMask = (1 << cbOperand) - 1;
153 bmBytes >>= (u16Port & 7);
154 if (bmBytes & fPortMask)
155 {
156 Log(("iemHlpCheckPortIOPermissionBitmap: u16Port=%#x LB %u - access denied (bm=%#x mask=%#x) -> #GP(0)\n",
157 u16Port, cbOperand, bmBytes, fPortMask));
158 return iemRaiseGeneralProtectionFault0(pVCpu);
159 }
160
161 return VINF_SUCCESS;
162}
163
164
165/**
166 * Checks if we are allowed to access the given I/O port, raising the
167 * appropriate exceptions if we aren't (or if the I/O bitmap is not
168 * accessible).
169 *
170 * @returns Strict VBox status code.
171 *
172 * @param pVCpu The cross context virtual CPU structure of the calling thread.
173 * @param u16Port The port number.
174 * @param cbOperand The operand size.
175 */
176DECLINLINE(VBOXSTRICTRC) iemHlpCheckPortIOPermission(PVMCPUCC pVCpu, uint16_t u16Port, uint8_t cbOperand)
177{
178 X86EFLAGS Efl;
179 Efl.u = IEMMISC_GET_EFL(pVCpu);
180 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
181 && ( pVCpu->iem.s.uCpl > Efl.Bits.u2IOPL
182 || Efl.Bits.u1VM) )
183 return iemHlpCheckPortIOPermissionBitmap(pVCpu, u16Port, cbOperand);
184 return VINF_SUCCESS;
185}
186
187
188#if 0
189/**
190 * Calculates the parity bit.
191 *
192 * @returns true if the bit is set, false if not.
193 * @param u8Result The least significant byte of the result.
194 */
195static bool iemHlpCalcParityFlag(uint8_t u8Result)
196{
197 /*
198 * Parity is set if the number of bits in the least significant byte of
199 * the result is even.
200 */
201 uint8_t cBits;
202 cBits = u8Result & 1; /* 0 */
203 u8Result >>= 1;
204 cBits += u8Result & 1;
205 u8Result >>= 1;
206 cBits += u8Result & 1;
207 u8Result >>= 1;
208 cBits += u8Result & 1;
209 u8Result >>= 1;
210 cBits += u8Result & 1; /* 4 */
211 u8Result >>= 1;
212 cBits += u8Result & 1;
213 u8Result >>= 1;
214 cBits += u8Result & 1;
215 u8Result >>= 1;
216 cBits += u8Result & 1;
217 return !(cBits & 1);
218}
219#endif /* not used */
220
221
222/**
223 * Updates the specified flags according to a 8-bit result.
224 *
225 * @param pVCpu The cross context virtual CPU structure of the calling thread.
226 * @param u8Result The result to set the flags according to.
227 * @param fToUpdate The flags to update.
228 * @param fUndefined The flags that are specified as undefined.
229 */
230static void iemHlpUpdateArithEFlagsU8(PVMCPUCC pVCpu, uint8_t u8Result, uint32_t fToUpdate, uint32_t fUndefined)
231{
232 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
233 iemAImpl_test_u8(&u8Result, u8Result, &fEFlags);
234 pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
235 pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
236}
237
238
239/**
240 * Updates the specified flags according to a 16-bit result.
241 *
242 * @param pVCpu The cross context virtual CPU structure of the calling thread.
243 * @param u16Result The result to set the flags according to.
244 * @param fToUpdate The flags to update.
245 * @param fUndefined The flags that are specified as undefined.
246 */
247static void iemHlpUpdateArithEFlagsU16(PVMCPUCC pVCpu, uint16_t u16Result, uint32_t fToUpdate, uint32_t fUndefined)
248{
249 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
250 iemAImpl_test_u16(&u16Result, u16Result, &fEFlags);
251 pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
252 pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
253}
254
255
256/**
257 * Helper used by iret.
258 *
259 * @param pVCpu The cross context virtual CPU structure of the calling thread.
260 * @param uCpl The new CPL.
261 * @param pSReg Pointer to the segment register.
262 */
263static void iemHlpAdjustSelectorForNewCpl(PVMCPUCC pVCpu, uint8_t uCpl, PCPUMSELREG pSReg)
264{
265 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
266 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_MASK);
267
268 if ( uCpl > pSReg->Attr.n.u2Dpl
269 && pSReg->Attr.n.u1DescType /* code or data, not system */
270 && (pSReg->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
271 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) /* not conforming code */
272 iemHlpLoadNullDataSelectorProt(pVCpu, pSReg, 0);
273}
274
275
276/**
277 * Indicates that we have modified the FPU state.
278 *
279 * @param pVCpu The cross context virtual CPU structure of the calling thread.
280 */
281DECLINLINE(void) iemHlpUsedFpu(PVMCPUCC pVCpu)
282{
283 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
284}
285
286/** @} */
287
288/** @name C Implementations
289 * @{
290 */
291
292/**
293 * Implements a 16-bit popa.
294 */
295IEM_CIMPL_DEF_0(iemCImpl_popa_16)
296{
297 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu);
298 RTGCPTR GCPtrLast = GCPtrStart + 15;
299 VBOXSTRICTRC rcStrict;
300
301 /*
302 * The docs are a bit hard to comprehend here, but it looks like we wrap
303 * around in real mode as long as none of the individual "popa" crosses the
304 * end of the stack segment. In protected mode we check the whole access
305 * in one go. For efficiency, only do the word-by-word thing if we're in
306 * danger of wrapping around.
307 */
308 /** @todo do popa boundary / wrap-around checks. */
309 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
310 && (pVCpu->cpum.GstCtx.cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
311 {
312 /* word-by-word */
313 RTUINT64U TmpRsp;
314 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
315 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.di, &TmpRsp);
316 if (rcStrict == VINF_SUCCESS)
317 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.si, &TmpRsp);
318 if (rcStrict == VINF_SUCCESS)
319 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.bp, &TmpRsp);
320 if (rcStrict == VINF_SUCCESS)
321 {
322 iemRegAddToRspEx(pVCpu, &TmpRsp, 2); /* sp */
323 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.bx, &TmpRsp);
324 }
325 if (rcStrict == VINF_SUCCESS)
326 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.dx, &TmpRsp);
327 if (rcStrict == VINF_SUCCESS)
328 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.cx, &TmpRsp);
329 if (rcStrict == VINF_SUCCESS)
330 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.ax, &TmpRsp);
331 if (rcStrict == VINF_SUCCESS)
332 {
333 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
334 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
335 }
336 }
337 else
338 {
339 uint16_t const *pa16Mem = NULL;
340 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R, sizeof(*pa16Mem) - 1);
341 if (rcStrict == VINF_SUCCESS)
342 {
343 pVCpu->cpum.GstCtx.di = pa16Mem[7 - X86_GREG_xDI];
344 pVCpu->cpum.GstCtx.si = pa16Mem[7 - X86_GREG_xSI];
345 pVCpu->cpum.GstCtx.bp = pa16Mem[7 - X86_GREG_xBP];
346 /* skip sp */
347 pVCpu->cpum.GstCtx.bx = pa16Mem[7 - X86_GREG_xBX];
348 pVCpu->cpum.GstCtx.dx = pa16Mem[7 - X86_GREG_xDX];
349 pVCpu->cpum.GstCtx.cx = pa16Mem[7 - X86_GREG_xCX];
350 pVCpu->cpum.GstCtx.ax = pa16Mem[7 - X86_GREG_xAX];
351 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_R);
352 if (rcStrict == VINF_SUCCESS)
353 {
354 iemRegAddToRsp(pVCpu, 16);
355 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
356 }
357 }
358 }
359 return rcStrict;
360}
361
362
363/**
364 * Implements a 32-bit popa.
365 */
366IEM_CIMPL_DEF_0(iemCImpl_popa_32)
367{
368 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu);
369 RTGCPTR GCPtrLast = GCPtrStart + 31;
370 VBOXSTRICTRC rcStrict;
371
372 /*
373 * The docs are a bit hard to comprehend here, but it looks like we wrap
374 * around in real mode as long as none of the individual "popa" crosses the
375 * end of the stack segment. In protected mode we check the whole access
376 * in one go. For efficiency, only do the word-by-word thing if we're in
377 * danger of wrapping around.
378 */
379 /** @todo do popa boundary / wrap-around checks. */
380 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
381 && (pVCpu->cpum.GstCtx.cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
382 {
383 /* word-by-word */
384 RTUINT64U TmpRsp;
385 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
386 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.edi, &TmpRsp);
387 if (rcStrict == VINF_SUCCESS)
388 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.esi, &TmpRsp);
389 if (rcStrict == VINF_SUCCESS)
390 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ebp, &TmpRsp);
391 if (rcStrict == VINF_SUCCESS)
392 {
393 iemRegAddToRspEx(pVCpu, &TmpRsp, 2); /* sp */
394 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ebx, &TmpRsp);
395 }
396 if (rcStrict == VINF_SUCCESS)
397 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.edx, &TmpRsp);
398 if (rcStrict == VINF_SUCCESS)
399 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ecx, &TmpRsp);
400 if (rcStrict == VINF_SUCCESS)
401 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.eax, &TmpRsp);
402 if (rcStrict == VINF_SUCCESS)
403 {
404#if 1 /** @todo what actually happens with the high bits when we're in 16-bit mode? */
405 pVCpu->cpum.GstCtx.rdi &= UINT32_MAX;
406 pVCpu->cpum.GstCtx.rsi &= UINT32_MAX;
407 pVCpu->cpum.GstCtx.rbp &= UINT32_MAX;
408 pVCpu->cpum.GstCtx.rbx &= UINT32_MAX;
409 pVCpu->cpum.GstCtx.rdx &= UINT32_MAX;
410 pVCpu->cpum.GstCtx.rcx &= UINT32_MAX;
411 pVCpu->cpum.GstCtx.rax &= UINT32_MAX;
412#endif
413 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
414 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
415 }
416 }
417 else
418 {
419 uint32_t const *pa32Mem;
420 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R, sizeof(*pa32Mem) - 1);
421 if (rcStrict == VINF_SUCCESS)
422 {
423 pVCpu->cpum.GstCtx.rdi = pa32Mem[7 - X86_GREG_xDI];
424 pVCpu->cpum.GstCtx.rsi = pa32Mem[7 - X86_GREG_xSI];
425 pVCpu->cpum.GstCtx.rbp = pa32Mem[7 - X86_GREG_xBP];
426 /* skip esp */
427 pVCpu->cpum.GstCtx.rbx = pa32Mem[7 - X86_GREG_xBX];
428 pVCpu->cpum.GstCtx.rdx = pa32Mem[7 - X86_GREG_xDX];
429 pVCpu->cpum.GstCtx.rcx = pa32Mem[7 - X86_GREG_xCX];
430 pVCpu->cpum.GstCtx.rax = pa32Mem[7 - X86_GREG_xAX];
431 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa32Mem, IEM_ACCESS_STACK_R);
432 if (rcStrict == VINF_SUCCESS)
433 {
434 iemRegAddToRsp(pVCpu, 32);
435 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
436 }
437 }
438 }
439 return rcStrict;
440}
441
442
443/**
444 * Implements a 16-bit pusha.
445 */
446IEM_CIMPL_DEF_0(iemCImpl_pusha_16)
447{
448 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu);
449 RTGCPTR GCPtrBottom = GCPtrTop - 15;
450 VBOXSTRICTRC rcStrict;
451
452 /*
453 * The docs are a bit hard to comprehend here, but it looks like we wrap
454 * around in real mode as long as none of the individual "pushd" crosses the
455 * end of the stack segment. In protected mode we check the whole access
456 * in one go. For efficiency, only do the word-by-word thing if we're in
457 * danger of wrapping around.
458 */
459 /** @todo do pusha boundary / wrap-around checks. */
460 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
461 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
462 {
463 /* word-by-word */
464 RTUINT64U TmpRsp;
465 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
466 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.ax, &TmpRsp);
467 if (rcStrict == VINF_SUCCESS)
468 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.cx, &TmpRsp);
469 if (rcStrict == VINF_SUCCESS)
470 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.dx, &TmpRsp);
471 if (rcStrict == VINF_SUCCESS)
472 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.bx, &TmpRsp);
473 if (rcStrict == VINF_SUCCESS)
474 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.sp, &TmpRsp);
475 if (rcStrict == VINF_SUCCESS)
476 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.bp, &TmpRsp);
477 if (rcStrict == VINF_SUCCESS)
478 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.si, &TmpRsp);
479 if (rcStrict == VINF_SUCCESS)
480 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.di, &TmpRsp);
481 if (rcStrict == VINF_SUCCESS)
482 {
483 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
484 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
485 }
486 }
487 else
488 {
489 GCPtrBottom--;
490 uint16_t *pa16Mem = NULL;
491 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W, sizeof(*pa16Mem) - 1);
492 if (rcStrict == VINF_SUCCESS)
493 {
494 pa16Mem[7 - X86_GREG_xDI] = pVCpu->cpum.GstCtx.di;
495 pa16Mem[7 - X86_GREG_xSI] = pVCpu->cpum.GstCtx.si;
496 pa16Mem[7 - X86_GREG_xBP] = pVCpu->cpum.GstCtx.bp;
497 pa16Mem[7 - X86_GREG_xSP] = pVCpu->cpum.GstCtx.sp;
498 pa16Mem[7 - X86_GREG_xBX] = pVCpu->cpum.GstCtx.bx;
499 pa16Mem[7 - X86_GREG_xDX] = pVCpu->cpum.GstCtx.dx;
500 pa16Mem[7 - X86_GREG_xCX] = pVCpu->cpum.GstCtx.cx;
501 pa16Mem[7 - X86_GREG_xAX] = pVCpu->cpum.GstCtx.ax;
502 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_W);
503 if (rcStrict == VINF_SUCCESS)
504 {
505 iemRegSubFromRsp(pVCpu, 16);
506 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
507 }
508 }
509 }
510 return rcStrict;
511}
512
513
514/**
515 * Implements a 32-bit pusha.
516 */
517IEM_CIMPL_DEF_0(iemCImpl_pusha_32)
518{
519 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu);
520 RTGCPTR GCPtrBottom = GCPtrTop - 31;
521 VBOXSTRICTRC rcStrict;
522
523 /*
524 * The docs are a bit hard to comprehend here, but it looks like we wrap
525 * around in real mode as long as none of the individual "pusha" crosses the
526 * end of the stack segment. In protected mode we check the whole access
527 * in one go. For efficiency, only do the word-by-word thing if we're in
528 * danger of wrapping around.
529 */
530 /** @todo do pusha boundary / wrap-around checks. */
531 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
532 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
533 {
534 /* word-by-word */
535 RTUINT64U TmpRsp;
536 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
537 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.eax, &TmpRsp);
538 if (rcStrict == VINF_SUCCESS)
539 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ecx, &TmpRsp);
540 if (rcStrict == VINF_SUCCESS)
541 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.edx, &TmpRsp);
542 if (rcStrict == VINF_SUCCESS)
543 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ebx, &TmpRsp);
544 if (rcStrict == VINF_SUCCESS)
545 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.esp, &TmpRsp);
546 if (rcStrict == VINF_SUCCESS)
547 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ebp, &TmpRsp);
548 if (rcStrict == VINF_SUCCESS)
549 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.esi, &TmpRsp);
550 if (rcStrict == VINF_SUCCESS)
551 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.edi, &TmpRsp);
552 if (rcStrict == VINF_SUCCESS)
553 {
554 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
555 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
556 }
557 }
558 else
559 {
560 GCPtrBottom--;
561 uint32_t *pa32Mem;
562 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W, sizeof(*pa32Mem) - 1);
563 if (rcStrict == VINF_SUCCESS)
564 {
565 pa32Mem[7 - X86_GREG_xDI] = pVCpu->cpum.GstCtx.edi;
566 pa32Mem[7 - X86_GREG_xSI] = pVCpu->cpum.GstCtx.esi;
567 pa32Mem[7 - X86_GREG_xBP] = pVCpu->cpum.GstCtx.ebp;
568 pa32Mem[7 - X86_GREG_xSP] = pVCpu->cpum.GstCtx.esp;
569 pa32Mem[7 - X86_GREG_xBX] = pVCpu->cpum.GstCtx.ebx;
570 pa32Mem[7 - X86_GREG_xDX] = pVCpu->cpum.GstCtx.edx;
571 pa32Mem[7 - X86_GREG_xCX] = pVCpu->cpum.GstCtx.ecx;
572 pa32Mem[7 - X86_GREG_xAX] = pVCpu->cpum.GstCtx.eax;
573 rcStrict = iemMemCommitAndUnmap(pVCpu, pa32Mem, IEM_ACCESS_STACK_W);
574 if (rcStrict == VINF_SUCCESS)
575 {
576 iemRegSubFromRsp(pVCpu, 32);
577 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
578 }
579 }
580 }
581 return rcStrict;
582}
583
584
585/**
586 * Implements pushf.
587 *
588 *
589 * @param enmEffOpSize The effective operand size.
590 */
591IEM_CIMPL_DEF_1(iemCImpl_pushf, IEMMODE, enmEffOpSize)
592{
593 VBOXSTRICTRC rcStrict;
594
595 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_PUSHF))
596 {
597 Log2(("pushf: Guest intercept -> #VMEXIT\n"));
598 IEM_SVM_UPDATE_NRIP(pVCpu);
599 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_PUSHF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
600 }
601
602 /*
603 * If we're in V8086 mode some care is required (which is why we're in
604 * doing this in a C implementation).
605 */
606 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
607 if ( (fEfl & X86_EFL_VM)
608 && X86_EFL_GET_IOPL(fEfl) != 3 )
609 {
610 Assert(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE);
611 if ( enmEffOpSize != IEMMODE_16BIT
612 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME))
613 return iemRaiseGeneralProtectionFault0(pVCpu);
614 fEfl &= ~X86_EFL_IF; /* (RF and VM are out of range) */
615 fEfl |= (fEfl & X86_EFL_VIF) >> (19 - 9);
616 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
617 }
618 else
619 {
620
621 /*
622 * Ok, clear RF and VM, adjust for ancient CPUs, and push the flags.
623 */
624 fEfl &= ~(X86_EFL_RF | X86_EFL_VM);
625
626 switch (enmEffOpSize)
627 {
628 case IEMMODE_16BIT:
629 AssertCompile(IEMTARGETCPU_8086 <= IEMTARGETCPU_186 && IEMTARGETCPU_V20 <= IEMTARGETCPU_186 && IEMTARGETCPU_286 > IEMTARGETCPU_186);
630 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_186)
631 fEfl |= UINT16_C(0xf000);
632 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
633 break;
634 case IEMMODE_32BIT:
635 rcStrict = iemMemStackPushU32(pVCpu, fEfl);
636 break;
637 case IEMMODE_64BIT:
638 rcStrict = iemMemStackPushU64(pVCpu, fEfl);
639 break;
640 IEM_NOT_REACHED_DEFAULT_CASE_RET();
641 }
642 }
643 if (rcStrict != VINF_SUCCESS)
644 return rcStrict;
645
646 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
647 return VINF_SUCCESS;
648}
649
650
651/**
652 * Implements popf.
653 *
654 * @param enmEffOpSize The effective operand size.
655 */
656IEM_CIMPL_DEF_1(iemCImpl_popf, IEMMODE, enmEffOpSize)
657{
658 uint32_t const fEflOld = IEMMISC_GET_EFL(pVCpu);
659 VBOXSTRICTRC rcStrict;
660 uint32_t fEflNew;
661
662 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_POPF))
663 {
664 Log2(("popf: Guest intercept -> #VMEXIT\n"));
665 IEM_SVM_UPDATE_NRIP(pVCpu);
666 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_POPF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
667 }
668
669 /*
670 * V8086 is special as usual.
671 */
672 if (fEflOld & X86_EFL_VM)
673 {
674 /*
675 * Almost anything goes if IOPL is 3.
676 */
677 if (X86_EFL_GET_IOPL(fEflOld) == 3)
678 {
679 switch (enmEffOpSize)
680 {
681 case IEMMODE_16BIT:
682 {
683 uint16_t u16Value;
684 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
685 if (rcStrict != VINF_SUCCESS)
686 return rcStrict;
687 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
688 break;
689 }
690 case IEMMODE_32BIT:
691 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
692 if (rcStrict != VINF_SUCCESS)
693 return rcStrict;
694 break;
695 IEM_NOT_REACHED_DEFAULT_CASE_RET();
696 }
697
698 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
699 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
700 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
701 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
702 }
703 /*
704 * Interrupt flag virtualization with CR4.VME=1.
705 */
706 else if ( enmEffOpSize == IEMMODE_16BIT
707 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME) )
708 {
709 uint16_t u16Value;
710 RTUINT64U TmpRsp;
711 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
712 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Value, &TmpRsp);
713 if (rcStrict != VINF_SUCCESS)
714 return rcStrict;
715
716 /** @todo Is the popf VME \#GP(0) delivered after updating RSP+RIP
717 * or before? */
718 if ( ( (u16Value & X86_EFL_IF)
719 && (fEflOld & X86_EFL_VIP))
720 || (u16Value & X86_EFL_TF) )
721 return iemRaiseGeneralProtectionFault0(pVCpu);
722
723 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000) & ~X86_EFL_VIF);
724 fEflNew |= (fEflNew & X86_EFL_IF) << (19 - 9);
725 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
726 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
727
728 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
729 }
730 else
731 return iemRaiseGeneralProtectionFault0(pVCpu);
732
733 }
734 /*
735 * Not in V8086 mode.
736 */
737 else
738 {
739 /* Pop the flags. */
740 switch (enmEffOpSize)
741 {
742 case IEMMODE_16BIT:
743 {
744 uint16_t u16Value;
745 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
746 if (rcStrict != VINF_SUCCESS)
747 return rcStrict;
748 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
749
750 /*
751 * Ancient CPU adjustments:
752 * - 8086, 80186, V20/30:
753 * Fixed bits 15:12 bits are not kept correctly internally, mostly for
754 * practical reasons (masking below). We add them when pushing flags.
755 * - 80286:
756 * The NT and IOPL flags cannot be popped from real mode and are
757 * therefore always zero (since a 286 can never exit from PM and
758 * their initial value is zero). This changed on a 386 and can
759 * therefore be used to detect 286 or 386 CPU in real mode.
760 */
761 if ( IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286
762 && !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE) )
763 fEflNew &= ~(X86_EFL_NT | X86_EFL_IOPL);
764 break;
765 }
766 case IEMMODE_32BIT:
767 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
768 if (rcStrict != VINF_SUCCESS)
769 return rcStrict;
770 break;
771 case IEMMODE_64BIT:
772 {
773 uint64_t u64Value;
774 rcStrict = iemMemStackPopU64(pVCpu, &u64Value);
775 if (rcStrict != VINF_SUCCESS)
776 return rcStrict;
777 fEflNew = u64Value; /** @todo testcase: Check exactly what happens if high bits are set. */
778 break;
779 }
780 IEM_NOT_REACHED_DEFAULT_CASE_RET();
781 }
782
783 /* Merge them with the current flags. */
784 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
785 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
786 if ( (fEflNew & (X86_EFL_IOPL | X86_EFL_IF)) == (fEflOld & (X86_EFL_IOPL | X86_EFL_IF))
787 || pVCpu->iem.s.uCpl == 0)
788 {
789 fEflNew &= fPopfBits;
790 fEflNew |= ~fPopfBits & fEflOld;
791 }
792 else if (pVCpu->iem.s.uCpl <= X86_EFL_GET_IOPL(fEflOld))
793 {
794 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
795 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
796 }
797 else
798 {
799 fEflNew &= fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF);
800 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
801 }
802 }
803
804 /*
805 * Commit the flags.
806 */
807 Assert(fEflNew & RT_BIT_32(1));
808 IEMMISC_SET_EFL(pVCpu, fEflNew);
809 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
810
811 return VINF_SUCCESS;
812}
813
814
815/**
816 * Implements an indirect call.
817 *
818 * @param uNewPC The new program counter (RIP) value (loaded from the
819 * operand).
820 */
821IEM_CIMPL_DEF_1(iemCImpl_call_16, uint16_t, uNewPC)
822{
823 uint16_t uOldPC = pVCpu->cpum.GstCtx.ip + cbInstr;
824 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
825 return iemRaiseGeneralProtectionFault0(pVCpu);
826
827 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
828 if (rcStrict != VINF_SUCCESS)
829 return rcStrict;
830
831 pVCpu->cpum.GstCtx.rip = uNewPC;
832 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
833
834#ifndef IEM_WITH_CODE_TLB
835 /* Flush the prefetch buffer. */
836 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
837#endif
838 return VINF_SUCCESS;
839}
840
841
842/**
843 * Implements a 16-bit relative call.
844 *
845 * @param offDisp The displacment offset.
846 */
847IEM_CIMPL_DEF_1(iemCImpl_call_rel_16, int16_t, offDisp)
848{
849 uint16_t uOldPC = pVCpu->cpum.GstCtx.ip + cbInstr;
850 uint16_t uNewPC = uOldPC + offDisp;
851 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
852 return iemRaiseGeneralProtectionFault0(pVCpu);
853
854 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
855 if (rcStrict != VINF_SUCCESS)
856 return rcStrict;
857
858 pVCpu->cpum.GstCtx.rip = uNewPC;
859 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
860
861#ifndef IEM_WITH_CODE_TLB
862 /* Flush the prefetch buffer. */
863 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
864#endif
865 return VINF_SUCCESS;
866}
867
868
869/**
870 * Implements a 32-bit indirect call.
871 *
872 * @param uNewPC The new program counter (RIP) value (loaded from the
873 * operand).
874 */
875IEM_CIMPL_DEF_1(iemCImpl_call_32, uint32_t, uNewPC)
876{
877 uint32_t uOldPC = pVCpu->cpum.GstCtx.eip + cbInstr;
878 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
879 return iemRaiseGeneralProtectionFault0(pVCpu);
880
881 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
882 if (rcStrict != VINF_SUCCESS)
883 return rcStrict;
884
885 pVCpu->cpum.GstCtx.rip = uNewPC;
886 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
887
888#ifndef IEM_WITH_CODE_TLB
889 /* Flush the prefetch buffer. */
890 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
891#endif
892 return VINF_SUCCESS;
893}
894
895
896/**
897 * Implements a 32-bit relative call.
898 *
899 * @param offDisp The displacment offset.
900 */
901IEM_CIMPL_DEF_1(iemCImpl_call_rel_32, int32_t, offDisp)
902{
903 uint32_t uOldPC = pVCpu->cpum.GstCtx.eip + cbInstr;
904 uint32_t uNewPC = uOldPC + offDisp;
905 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
906 return iemRaiseGeneralProtectionFault0(pVCpu);
907
908 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
909 if (rcStrict != VINF_SUCCESS)
910 return rcStrict;
911
912 pVCpu->cpum.GstCtx.rip = uNewPC;
913 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
914
915#ifndef IEM_WITH_CODE_TLB
916 /* Flush the prefetch buffer. */
917 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
918#endif
919 return VINF_SUCCESS;
920}
921
922
923/**
924 * Implements a 64-bit indirect call.
925 *
926 * @param uNewPC The new program counter (RIP) value (loaded from the
927 * operand).
928 */
929IEM_CIMPL_DEF_1(iemCImpl_call_64, uint64_t, uNewPC)
930{
931 uint64_t uOldPC = pVCpu->cpum.GstCtx.rip + cbInstr;
932 if (!IEM_IS_CANONICAL(uNewPC))
933 return iemRaiseGeneralProtectionFault0(pVCpu);
934
935 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
936 if (rcStrict != VINF_SUCCESS)
937 return rcStrict;
938
939 pVCpu->cpum.GstCtx.rip = uNewPC;
940 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
941
942#ifndef IEM_WITH_CODE_TLB
943 /* Flush the prefetch buffer. */
944 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
945#endif
946 return VINF_SUCCESS;
947}
948
949
950/**
951 * Implements a 64-bit relative call.
952 *
953 * @param offDisp The displacment offset.
954 */
955IEM_CIMPL_DEF_1(iemCImpl_call_rel_64, int64_t, offDisp)
956{
957 uint64_t uOldPC = pVCpu->cpum.GstCtx.rip + cbInstr;
958 uint64_t uNewPC = uOldPC + offDisp;
959 if (!IEM_IS_CANONICAL(uNewPC))
960 return iemRaiseNotCanonical(pVCpu);
961
962 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
963 if (rcStrict != VINF_SUCCESS)
964 return rcStrict;
965
966 pVCpu->cpum.GstCtx.rip = uNewPC;
967 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
968
969#ifndef IEM_WITH_CODE_TLB
970 /* Flush the prefetch buffer. */
971 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
972#endif
973
974 return VINF_SUCCESS;
975}
976
977
978/**
979 * Implements far jumps and calls thru task segments (TSS).
980 *
981 * @param uSel The selector.
982 * @param enmBranch The kind of branching we're performing.
983 * @param enmEffOpSize The effective operand size.
984 * @param pDesc The descriptor corresponding to @a uSel. The type is
985 * task gate.
986 */
987IEM_CIMPL_DEF_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
988{
989#ifndef IEM_IMPLEMENTS_TASKSWITCH
990 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
991#else
992 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
993 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL
994 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
995 RT_NOREF_PV(enmEffOpSize);
996 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
997
998 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
999 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1000 {
1001 Log(("BranchTaskSegment invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1002 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1003 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1004 }
1005
1006 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
1007 * far calls (see iemCImpl_callf). Most likely in both cases it should be
1008 * checked here, need testcases. */
1009 if (!pDesc->Legacy.Gen.u1Present)
1010 {
1011 Log(("BranchTaskSegment TSS not present uSel=%04x -> #NP\n", uSel));
1012 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1013 }
1014
1015 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
1016 return iemTaskSwitch(pVCpu, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
1017 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSel, pDesc);
1018#endif
1019}
1020
1021
1022/**
1023 * Implements far jumps and calls thru task gates.
1024 *
1025 * @param uSel The selector.
1026 * @param enmBranch The kind of branching we're performing.
1027 * @param enmEffOpSize The effective operand size.
1028 * @param pDesc The descriptor corresponding to @a uSel. The type is
1029 * task gate.
1030 */
1031IEM_CIMPL_DEF_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1032{
1033#ifndef IEM_IMPLEMENTS_TASKSWITCH
1034 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1035#else
1036 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1037 RT_NOREF_PV(enmEffOpSize);
1038 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1039
1040 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1041 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1042 {
1043 Log(("BranchTaskGate invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1044 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1045 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1046 }
1047
1048 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
1049 * far calls (see iemCImpl_callf). Most likely in both cases it should be
1050 * checked here, need testcases. */
1051 if (!pDesc->Legacy.Gen.u1Present)
1052 {
1053 Log(("BranchTaskSegment segment not present uSel=%04x -> #NP\n", uSel));
1054 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1055 }
1056
1057 /*
1058 * Fetch the new TSS descriptor from the GDT.
1059 */
1060 RTSEL uSelTss = pDesc->Legacy.Gate.u16Sel;
1061 if (uSelTss & X86_SEL_LDT)
1062 {
1063 Log(("BranchTaskGate TSS is in LDT. uSel=%04x uSelTss=%04x -> #GP\n", uSel, uSelTss));
1064 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1065 }
1066
1067 IEMSELDESC TssDesc;
1068 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelTss, X86_XCPT_GP);
1069 if (rcStrict != VINF_SUCCESS)
1070 return rcStrict;
1071
1072 if (TssDesc.Legacy.Gate.u4Type & X86_SEL_TYPE_SYS_TSS_BUSY_MASK)
1073 {
1074 Log(("BranchTaskGate TSS is busy. uSel=%04x uSelTss=%04x DescType=%#x -> #GP\n", uSel, uSelTss,
1075 TssDesc.Legacy.Gate.u4Type));
1076 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1077 }
1078
1079 if (!TssDesc.Legacy.Gate.u1Present)
1080 {
1081 Log(("BranchTaskGate TSS is not present. uSel=%04x uSelTss=%04x -> #NP\n", uSel, uSelTss));
1082 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelTss & X86_SEL_MASK_OFF_RPL);
1083 }
1084
1085 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
1086 return iemTaskSwitch(pVCpu, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
1087 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSelTss, &TssDesc);
1088#endif
1089}
1090
1091
1092/**
1093 * Implements far jumps and calls thru call gates.
1094 *
1095 * @param uSel The selector.
1096 * @param enmBranch The kind of branching we're performing.
1097 * @param enmEffOpSize The effective operand size.
1098 * @param pDesc The descriptor corresponding to @a uSel. The type is
1099 * call gate.
1100 */
1101IEM_CIMPL_DEF_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1102{
1103#define IEM_IMPLEMENTS_CALLGATE
1104#ifndef IEM_IMPLEMENTS_CALLGATE
1105 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1106#else
1107 RT_NOREF_PV(enmEffOpSize);
1108 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1109
1110 /* NB: Far jumps can only do intra-privilege transfers. Far calls support
1111 * inter-privilege calls and are much more complex.
1112 *
1113 * NB: 64-bit call gate has the same type as a 32-bit call gate! If
1114 * EFER.LMA=1, the gate must be 64-bit. Conversely if EFER.LMA=0, the gate
1115 * must be 16-bit or 32-bit.
1116 */
1117 /** @todo effective operand size is probably irrelevant here, only the
1118 * call gate bitness matters??
1119 */
1120 VBOXSTRICTRC rcStrict;
1121 RTPTRUNION uPtrRet;
1122 uint64_t uNewRsp;
1123 uint64_t uNewRip;
1124 uint64_t u64Base;
1125 uint32_t cbLimit;
1126 RTSEL uNewCS;
1127 IEMSELDESC DescCS;
1128
1129 AssertCompile(X86_SEL_TYPE_SYS_386_CALL_GATE == AMD64_SEL_TYPE_SYS_CALL_GATE);
1130 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1131 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE
1132 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE);
1133
1134 /* Determine the new instruction pointer from the gate descriptor. */
1135 uNewRip = pDesc->Legacy.Gate.u16OffsetLow
1136 | ((uint32_t)pDesc->Legacy.Gate.u16OffsetHigh << 16)
1137 | ((uint64_t)pDesc->Long.Gate.u32OffsetTop << 32);
1138
1139 /* Perform DPL checks on the gate descriptor. */
1140 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1141 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1142 {
1143 Log(("BranchCallGate invalid priv. uSel=%04x Gate DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1144 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1145 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1146 }
1147
1148 /** @todo does this catch NULL selectors, too? */
1149 if (!pDesc->Legacy.Gen.u1Present)
1150 {
1151 Log(("BranchCallGate Gate not present uSel=%04x -> #NP\n", uSel));
1152 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1153 }
1154
1155 /*
1156 * Fetch the target CS descriptor from the GDT or LDT.
1157 */
1158 uNewCS = pDesc->Legacy.Gate.u16Sel;
1159 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCS, X86_XCPT_GP);
1160 if (rcStrict != VINF_SUCCESS)
1161 return rcStrict;
1162
1163 /* Target CS must be a code selector. */
1164 if ( !DescCS.Legacy.Gen.u1DescType
1165 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
1166 {
1167 Log(("BranchCallGate %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
1168 uNewCS, uNewRip, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
1169 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1170 }
1171
1172 /* Privilege checks on target CS. */
1173 if (enmBranch == IEMBRANCH_JUMP)
1174 {
1175 if (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1176 {
1177 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1178 {
1179 Log(("BranchCallGate jump (conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1180 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1181 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1182 }
1183 }
1184 else
1185 {
1186 if (DescCS.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
1187 {
1188 Log(("BranchCallGate jump (non-conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1189 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1190 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1191 }
1192 }
1193 }
1194 else
1195 {
1196 Assert(enmBranch == IEMBRANCH_CALL);
1197 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1198 {
1199 Log(("BranchCallGate call invalid priv. uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1200 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1201 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
1202 }
1203 }
1204
1205 /* Additional long mode checks. */
1206 if (IEM_IS_LONG_MODE(pVCpu))
1207 {
1208 if (!DescCS.Legacy.Gen.u1Long)
1209 {
1210 Log(("BranchCallGate uNewCS %04x -> not a 64-bit code segment.\n", uNewCS));
1211 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1212 }
1213
1214 /* L vs D. */
1215 if ( DescCS.Legacy.Gen.u1Long
1216 && DescCS.Legacy.Gen.u1DefBig)
1217 {
1218 Log(("BranchCallGate uNewCS %04x -> both L and D are set.\n", uNewCS));
1219 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1220 }
1221 }
1222
1223 if (!DescCS.Legacy.Gate.u1Present)
1224 {
1225 Log(("BranchCallGate target CS is not present. uSel=%04x uNewCS=%04x -> #NP(CS)\n", uSel, uNewCS));
1226 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCS);
1227 }
1228
1229 if (enmBranch == IEMBRANCH_JUMP)
1230 {
1231 /** @todo This is very similar to regular far jumps; merge! */
1232 /* Jumps are fairly simple... */
1233
1234 /* Chop the high bits off if 16-bit gate (Intel says so). */
1235 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1236 uNewRip = (uint16_t)uNewRip;
1237
1238 /* Limit check for non-long segments. */
1239 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1240 if (DescCS.Legacy.Gen.u1Long)
1241 u64Base = 0;
1242 else
1243 {
1244 if (uNewRip > cbLimit)
1245 {
1246 Log(("BranchCallGate jump %04x:%08RX64 -> out of bounds (%#x) -> #GP(0)\n", uNewCS, uNewRip, cbLimit));
1247 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1248 }
1249 u64Base = X86DESC_BASE(&DescCS.Legacy);
1250 }
1251
1252 /* Canonical address check. */
1253 if (!IEM_IS_CANONICAL(uNewRip))
1254 {
1255 Log(("BranchCallGate jump %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1256 return iemRaiseNotCanonical(pVCpu);
1257 }
1258
1259 /*
1260 * Ok, everything checked out fine. Now set the accessed bit before
1261 * committing the result into CS, CSHID and RIP.
1262 */
1263 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1264 {
1265 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1266 if (rcStrict != VINF_SUCCESS)
1267 return rcStrict;
1268 /** @todo check what VT-x and AMD-V does. */
1269 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1270 }
1271
1272 /* commit */
1273 pVCpu->cpum.GstCtx.rip = uNewRip;
1274 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1275 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1276 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1277 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1278 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1279 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1280 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1281 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1282 }
1283 else
1284 {
1285 Assert(enmBranch == IEMBRANCH_CALL);
1286 /* Calls are much more complicated. */
1287
1288 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF) && (DescCS.Legacy.Gen.u2Dpl < pVCpu->iem.s.uCpl))
1289 {
1290 uint16_t offNewStack; /* Offset of new stack in TSS. */
1291 uint16_t cbNewStack; /* Number of bytes the stack information takes up in TSS. */
1292 uint8_t uNewCSDpl;
1293 uint8_t cbWords;
1294 RTSEL uNewSS;
1295 RTSEL uOldSS;
1296 uint64_t uOldRsp;
1297 IEMSELDESC DescSS;
1298 RTPTRUNION uPtrTSS;
1299 RTGCPTR GCPtrTSS;
1300 RTPTRUNION uPtrParmWds;
1301 RTGCPTR GCPtrParmWds;
1302
1303 /* More privilege. This is the fun part. */
1304 Assert(!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)); /* Filtered out above. */
1305
1306 /*
1307 * Determine new SS:rSP from the TSS.
1308 */
1309 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType);
1310
1311 /* Figure out where the new stack pointer is stored in the TSS. */
1312 uNewCSDpl = DescCS.Legacy.Gen.u2Dpl;
1313 if (!IEM_IS_LONG_MODE(pVCpu))
1314 {
1315 if (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1316 {
1317 offNewStack = RT_UOFFSETOF(X86TSS32, esp0) + uNewCSDpl * 8;
1318 cbNewStack = RT_SIZEOFMEMB(X86TSS32, esp0) + RT_SIZEOFMEMB(X86TSS32, ss0);
1319 }
1320 else
1321 {
1322 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1323 offNewStack = RT_UOFFSETOF(X86TSS16, sp0) + uNewCSDpl * 4;
1324 cbNewStack = RT_SIZEOFMEMB(X86TSS16, sp0) + RT_SIZEOFMEMB(X86TSS16, ss0);
1325 }
1326 }
1327 else
1328 {
1329 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1330 offNewStack = RT_UOFFSETOF(X86TSS64, rsp0) + uNewCSDpl * RT_SIZEOFMEMB(X86TSS64, rsp0);
1331 cbNewStack = RT_SIZEOFMEMB(X86TSS64, rsp0);
1332 }
1333
1334 /* Check against TSS limit. */
1335 if ((uint16_t)(offNewStack + cbNewStack - 1) > pVCpu->cpum.GstCtx.tr.u32Limit)
1336 {
1337 Log(("BranchCallGate inner stack past TSS limit - %u > %u -> #TS(TSS)\n", offNewStack + cbNewStack - 1, pVCpu->cpum.GstCtx.tr.u32Limit));
1338 return iemRaiseTaskSwitchFaultBySelector(pVCpu, pVCpu->cpum.GstCtx.tr.Sel);
1339 }
1340
1341 GCPtrTSS = pVCpu->cpum.GstCtx.tr.u64Base + offNewStack;
1342 rcStrict = iemMemMap(pVCpu, &uPtrTSS.pv, cbNewStack, UINT8_MAX, GCPtrTSS, IEM_ACCESS_SYS_R, 0);
1343 if (rcStrict != VINF_SUCCESS)
1344 {
1345 Log(("BranchCallGate: TSS mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1346 return rcStrict;
1347 }
1348
1349 if (!IEM_IS_LONG_MODE(pVCpu))
1350 {
1351 if (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1352 {
1353 uNewRsp = uPtrTSS.pu32[0];
1354 uNewSS = uPtrTSS.pu16[2];
1355 }
1356 else
1357 {
1358 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1359 uNewRsp = uPtrTSS.pu16[0];
1360 uNewSS = uPtrTSS.pu16[1];
1361 }
1362 }
1363 else
1364 {
1365 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1366 /* SS will be a NULL selector, but that's valid. */
1367 uNewRsp = uPtrTSS.pu64[0];
1368 uNewSS = uNewCSDpl;
1369 }
1370
1371 /* Done with the TSS now. */
1372 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrTSS.pv, IEM_ACCESS_SYS_R);
1373 if (rcStrict != VINF_SUCCESS)
1374 {
1375 Log(("BranchCallGate: TSS unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1376 return rcStrict;
1377 }
1378
1379 /* Only used outside of long mode. */
1380 cbWords = pDesc->Legacy.Gate.u5ParmCount;
1381
1382 /* If EFER.LMA is 0, there's extra work to do. */
1383 if (!IEM_IS_LONG_MODE(pVCpu))
1384 {
1385 if ((uNewSS & X86_SEL_MASK_OFF_RPL) == 0)
1386 {
1387 Log(("BranchCallGate new SS NULL -> #TS(NewSS)\n"));
1388 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1389 }
1390
1391 /* Grab the new SS descriptor. */
1392 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1393 if (rcStrict != VINF_SUCCESS)
1394 return rcStrict;
1395
1396 /* Ensure that CS.DPL == SS.RPL == SS.DPL. */
1397 if ( (DescCS.Legacy.Gen.u2Dpl != (uNewSS & X86_SEL_RPL))
1398 || (DescCS.Legacy.Gen.u2Dpl != DescSS.Legacy.Gen.u2Dpl))
1399 {
1400 Log(("BranchCallGate call bad RPL/DPL uNewSS=%04x SS DPL=%d CS DPL=%u -> #TS(NewSS)\n",
1401 uNewSS, DescCS.Legacy.Gen.u2Dpl, DescCS.Legacy.Gen.u2Dpl));
1402 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1403 }
1404
1405 /* Ensure new SS is a writable data segment. */
1406 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
1407 {
1408 Log(("BranchCallGate call new SS -> not a writable data selector (u4Type=%#x)\n", DescSS.Legacy.Gen.u4Type));
1409 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1410 }
1411
1412 if (!DescSS.Legacy.Gen.u1Present)
1413 {
1414 Log(("BranchCallGate New stack not present uSel=%04x -> #SS(NewSS)\n", uNewSS));
1415 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
1416 }
1417 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1418 cbNewStack = (uint16_t)sizeof(uint32_t) * (4 + cbWords);
1419 else
1420 cbNewStack = (uint16_t)sizeof(uint16_t) * (4 + cbWords);
1421 }
1422 else
1423 {
1424 /* Just grab the new (NULL) SS descriptor. */
1425 /** @todo testcase: Check whether the zero GDT entry is actually loaded here
1426 * like we do... */
1427 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1428 if (rcStrict != VINF_SUCCESS)
1429 return rcStrict;
1430
1431 cbNewStack = sizeof(uint64_t) * 4;
1432 }
1433
1434 /** @todo According to Intel, new stack is checked for enough space first,
1435 * then switched. According to AMD, the stack is switched first and
1436 * then pushes might fault!
1437 * NB: OS/2 Warp 3/4 actively relies on the fact that possible
1438 * incoming stack \#PF happens before actual stack switch. AMD is
1439 * either lying or implicitly assumes that new state is committed
1440 * only if and when an instruction doesn't fault.
1441 */
1442
1443 /** @todo According to AMD, CS is loaded first, then SS.
1444 * According to Intel, it's the other way around!?
1445 */
1446
1447 /** @todo Intel and AMD disagree on when exactly the CPL changes! */
1448
1449 /* Set the accessed bit before committing new SS. */
1450 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1451 {
1452 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
1453 if (rcStrict != VINF_SUCCESS)
1454 return rcStrict;
1455 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1456 }
1457
1458 /* Remember the old SS:rSP and their linear address. */
1459 uOldSS = pVCpu->cpum.GstCtx.ss.Sel;
1460 uOldRsp = pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig ? pVCpu->cpum.GstCtx.rsp : pVCpu->cpum.GstCtx.sp;
1461
1462 GCPtrParmWds = pVCpu->cpum.GstCtx.ss.u64Base + uOldRsp;
1463
1464 /* HACK ALERT! Probe if the write to the new stack will succeed. May #SS(NewSS)
1465 or #PF, the former is not implemented in this workaround. */
1466 /** @todo Proper fix callgate target stack exceptions. */
1467 /** @todo testcase: Cover callgates with partially or fully inaccessible
1468 * target stacks. */
1469 void *pvNewFrame;
1470 RTGCPTR GCPtrNewStack = X86DESC_BASE(&DescSS.Legacy) + uNewRsp - cbNewStack;
1471 rcStrict = iemMemMap(pVCpu, &pvNewFrame, cbNewStack, UINT8_MAX, GCPtrNewStack, IEM_ACCESS_SYS_RW, 0);
1472 if (rcStrict != VINF_SUCCESS)
1473 {
1474 Log(("BranchCallGate: Incoming stack (%04x:%08RX64) not accessible, rc=%Rrc\n", uNewSS, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
1475 return rcStrict;
1476 }
1477 rcStrict = iemMemCommitAndUnmap(pVCpu, pvNewFrame, IEM_ACCESS_SYS_RW);
1478 if (rcStrict != VINF_SUCCESS)
1479 {
1480 Log(("BranchCallGate: New stack probe unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1481 return rcStrict;
1482 }
1483
1484 /* Commit new SS:rSP. */
1485 pVCpu->cpum.GstCtx.ss.Sel = uNewSS;
1486 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSS;
1487 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
1488 pVCpu->cpum.GstCtx.ss.u32Limit = X86DESC_LIMIT_G(&DescSS.Legacy);
1489 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
1490 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
1491 pVCpu->cpum.GstCtx.rsp = uNewRsp;
1492 pVCpu->iem.s.uCpl = uNewCSDpl; /** @todo is the parameter words accessed using the new CPL or the old CPL? */
1493 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
1494 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
1495
1496 /* At this point the stack access must not fail because new state was already committed. */
1497 /** @todo this can still fail due to SS.LIMIT not check. */
1498 rcStrict = iemMemStackPushBeginSpecial(pVCpu, cbNewStack,
1499 IEM_IS_LONG_MODE(pVCpu) ? 7
1500 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 3 : 1,
1501 &uPtrRet.pv, &uNewRsp);
1502 AssertMsgReturn(rcStrict == VINF_SUCCESS, ("BranchCallGate: New stack mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)),
1503 VERR_INTERNAL_ERROR_5);
1504
1505 if (!IEM_IS_LONG_MODE(pVCpu))
1506 {
1507 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1508 {
1509 if (cbWords)
1510 {
1511 /* Map the relevant chunk of the old stack. */
1512 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 4, UINT8_MAX, GCPtrParmWds,
1513 IEM_ACCESS_DATA_R, 0 /** @todo Can uNewCSDpl == 3? Then we need alignment mask here! */);
1514 if (rcStrict != VINF_SUCCESS)
1515 {
1516 Log(("BranchCallGate: Old stack mapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1517 return rcStrict;
1518 }
1519
1520 /* Copy the parameter (d)words. */
1521 for (int i = 0; i < cbWords; ++i)
1522 uPtrRet.pu32[2 + i] = uPtrParmWds.pu32[i];
1523
1524 /* Unmap the old stack. */
1525 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1526 if (rcStrict != VINF_SUCCESS)
1527 {
1528 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1529 return rcStrict;
1530 }
1531 }
1532
1533 /* Push the old CS:rIP. */
1534 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
1535 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1536
1537 /* Push the old SS:rSP. */
1538 uPtrRet.pu32[2 + cbWords + 0] = uOldRsp;
1539 uPtrRet.pu32[2 + cbWords + 1] = uOldSS;
1540 }
1541 else
1542 {
1543 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1544
1545 if (cbWords)
1546 {
1547 /* Map the relevant chunk of the old stack. */
1548 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 2, UINT8_MAX, GCPtrParmWds,
1549 IEM_ACCESS_DATA_R, 0 /** @todo Can uNewCSDpl == 3? Then we need alignment mask here! */);
1550 if (rcStrict != VINF_SUCCESS)
1551 {
1552 Log(("BranchCallGate: Old stack mapping (16-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1553 return rcStrict;
1554 }
1555
1556 /* Copy the parameter words. */
1557 for (int i = 0; i < cbWords; ++i)
1558 uPtrRet.pu16[2 + i] = uPtrParmWds.pu16[i];
1559
1560 /* Unmap the old stack. */
1561 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1562 if (rcStrict != VINF_SUCCESS)
1563 {
1564 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1565 return rcStrict;
1566 }
1567 }
1568
1569 /* Push the old CS:rIP. */
1570 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
1571 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
1572
1573 /* Push the old SS:rSP. */
1574 uPtrRet.pu16[2 + cbWords + 0] = uOldRsp;
1575 uPtrRet.pu16[2 + cbWords + 1] = uOldSS;
1576 }
1577 }
1578 else
1579 {
1580 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1581
1582 /* For 64-bit gates, no parameters are copied. Just push old SS:rSP and CS:rIP. */
1583 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
1584 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1585 uPtrRet.pu64[2] = uOldRsp;
1586 uPtrRet.pu64[3] = uOldSS; /** @todo Testcase: What is written to the high words when pushing SS? */
1587 }
1588
1589 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1590 if (rcStrict != VINF_SUCCESS)
1591 {
1592 Log(("BranchCallGate: New stack unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1593 return rcStrict;
1594 }
1595
1596 /* Chop the high bits off if 16-bit gate (Intel says so). */
1597 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1598 uNewRip = (uint16_t)uNewRip;
1599
1600 /* Limit / canonical check. */
1601 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1602 if (!IEM_IS_LONG_MODE(pVCpu))
1603 {
1604 if (uNewRip > cbLimit)
1605 {
1606 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1607 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1608 }
1609 u64Base = X86DESC_BASE(&DescCS.Legacy);
1610 }
1611 else
1612 {
1613 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1614 if (!IEM_IS_CANONICAL(uNewRip))
1615 {
1616 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1617 return iemRaiseNotCanonical(pVCpu);
1618 }
1619 u64Base = 0;
1620 }
1621
1622 /*
1623 * Now set the accessed bit before
1624 * writing the return address to the stack and committing the result into
1625 * CS, CSHID and RIP.
1626 */
1627 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1628 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1629 {
1630 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1631 if (rcStrict != VINF_SUCCESS)
1632 return rcStrict;
1633 /** @todo check what VT-x and AMD-V does. */
1634 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1635 }
1636
1637 /* Commit new CS:rIP. */
1638 pVCpu->cpum.GstCtx.rip = uNewRip;
1639 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1640 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
1641 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1642 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1643 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1644 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1645 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1646 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1647 }
1648 else
1649 {
1650 /* Same privilege. */
1651 /** @todo This is very similar to regular far calls; merge! */
1652
1653 /* Check stack first - may #SS(0). */
1654 /** @todo check how gate size affects pushing of CS! Does callf 16:32 in
1655 * 16-bit code cause a two or four byte CS to be pushed? */
1656 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
1657 IEM_IS_LONG_MODE(pVCpu) ? 8+8
1658 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 4+4 : 2+2,
1659 IEM_IS_LONG_MODE(pVCpu) ? 7
1660 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 3 : 2,
1661 &uPtrRet.pv, &uNewRsp);
1662 if (rcStrict != VINF_SUCCESS)
1663 return rcStrict;
1664
1665 /* Chop the high bits off if 16-bit gate (Intel says so). */
1666 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1667 uNewRip = (uint16_t)uNewRip;
1668
1669 /* Limit / canonical check. */
1670 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1671 if (!IEM_IS_LONG_MODE(pVCpu))
1672 {
1673 if (uNewRip > cbLimit)
1674 {
1675 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1676 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1677 }
1678 u64Base = X86DESC_BASE(&DescCS.Legacy);
1679 }
1680 else
1681 {
1682 if (!IEM_IS_CANONICAL(uNewRip))
1683 {
1684 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1685 return iemRaiseNotCanonical(pVCpu);
1686 }
1687 u64Base = 0;
1688 }
1689
1690 /*
1691 * Now set the accessed bit before
1692 * writing the return address to the stack and committing the result into
1693 * CS, CSHID and RIP.
1694 */
1695 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1696 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1697 {
1698 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1699 if (rcStrict != VINF_SUCCESS)
1700 return rcStrict;
1701 /** @todo check what VT-x and AMD-V does. */
1702 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1703 }
1704
1705 /* stack */
1706 if (!IEM_IS_LONG_MODE(pVCpu))
1707 {
1708 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1709 {
1710 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
1711 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1712 }
1713 else
1714 {
1715 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1716 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
1717 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
1718 }
1719 }
1720 else
1721 {
1722 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1723 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
1724 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1725 }
1726
1727 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1728 if (rcStrict != VINF_SUCCESS)
1729 return rcStrict;
1730
1731 /* commit */
1732 pVCpu->cpum.GstCtx.rip = uNewRip;
1733 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1734 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
1735 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1736 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1737 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1738 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1739 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1740 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1741 }
1742 }
1743 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1744
1745 /* Flush the prefetch buffer. */
1746# ifdef IEM_WITH_CODE_TLB
1747 pVCpu->iem.s.pbInstrBuf = NULL;
1748# else
1749 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1750# endif
1751 return VINF_SUCCESS;
1752#endif
1753}
1754
1755
1756/**
1757 * Implements far jumps and calls thru system selectors.
1758 *
1759 * @param uSel The selector.
1760 * @param enmBranch The kind of branching we're performing.
1761 * @param enmEffOpSize The effective operand size.
1762 * @param pDesc The descriptor corresponding to @a uSel.
1763 */
1764IEM_CIMPL_DEF_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1765{
1766 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1767 Assert((uSel & X86_SEL_MASK_OFF_RPL));
1768 IEM_CTX_IMPORT_RET(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1769
1770 if (IEM_IS_LONG_MODE(pVCpu))
1771 switch (pDesc->Legacy.Gen.u4Type)
1772 {
1773 case AMD64_SEL_TYPE_SYS_CALL_GATE:
1774 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1775
1776 default:
1777 case AMD64_SEL_TYPE_SYS_LDT:
1778 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
1779 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
1780 case AMD64_SEL_TYPE_SYS_TRAP_GATE:
1781 case AMD64_SEL_TYPE_SYS_INT_GATE:
1782 Log(("branch %04x -> wrong sys selector (64-bit): %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1783 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1784 }
1785
1786 switch (pDesc->Legacy.Gen.u4Type)
1787 {
1788 case X86_SEL_TYPE_SYS_286_CALL_GATE:
1789 case X86_SEL_TYPE_SYS_386_CALL_GATE:
1790 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1791
1792 case X86_SEL_TYPE_SYS_TASK_GATE:
1793 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskGate, uSel, enmBranch, enmEffOpSize, pDesc);
1794
1795 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
1796 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
1797 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskSegment, uSel, enmBranch, enmEffOpSize, pDesc);
1798
1799 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
1800 Log(("branch %04x -> busy 286 TSS\n", uSel));
1801 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1802
1803 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
1804 Log(("branch %04x -> busy 386 TSS\n", uSel));
1805 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1806
1807 default:
1808 case X86_SEL_TYPE_SYS_LDT:
1809 case X86_SEL_TYPE_SYS_286_INT_GATE:
1810 case X86_SEL_TYPE_SYS_286_TRAP_GATE:
1811 case X86_SEL_TYPE_SYS_386_INT_GATE:
1812 case X86_SEL_TYPE_SYS_386_TRAP_GATE:
1813 Log(("branch %04x -> wrong sys selector: %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1814 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1815 }
1816}
1817
1818
1819/**
1820 * Implements far jumps.
1821 *
1822 * @param uSel The selector.
1823 * @param offSeg The segment offset.
1824 * @param enmEffOpSize The effective operand size.
1825 */
1826IEM_CIMPL_DEF_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1827{
1828 NOREF(cbInstr);
1829 Assert(offSeg <= UINT32_MAX);
1830
1831 /*
1832 * Real mode and V8086 mode are easy. The only snag seems to be that
1833 * CS.limit doesn't change and the limit check is done against the current
1834 * limit.
1835 */
1836 /** @todo Robert Collins claims (The Segment Descriptor Cache, DDJ August
1837 * 1998) that up to and including the Intel 486, far control
1838 * transfers in real mode set default CS attributes (0x93) and also
1839 * set a 64K segment limit. Starting with the Pentium, the
1840 * attributes and limit are left alone but the access rights are
1841 * ignored. We only implement the Pentium+ behavior.
1842 * */
1843 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
1844 {
1845 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
1846 if (offSeg > pVCpu->cpum.GstCtx.cs.u32Limit)
1847 {
1848 Log(("iemCImpl_FarJmp: 16-bit limit\n"));
1849 return iemRaiseGeneralProtectionFault0(pVCpu);
1850 }
1851
1852 if (enmEffOpSize == IEMMODE_16BIT) /** @todo WRONG, must pass this. */
1853 pVCpu->cpum.GstCtx.rip = offSeg;
1854 else
1855 pVCpu->cpum.GstCtx.rip = offSeg & UINT16_MAX;
1856 pVCpu->cpum.GstCtx.cs.Sel = uSel;
1857 pVCpu->cpum.GstCtx.cs.ValidSel = uSel;
1858 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1859 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uSel << 4;
1860 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1861 return VINF_SUCCESS;
1862 }
1863
1864 /*
1865 * Protected mode. Need to parse the specified descriptor...
1866 */
1867 if (!(uSel & X86_SEL_MASK_OFF_RPL))
1868 {
1869 Log(("jmpf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
1870 return iemRaiseGeneralProtectionFault0(pVCpu);
1871 }
1872
1873 /* Fetch the descriptor. */
1874 IEMSELDESC Desc;
1875 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
1876 if (rcStrict != VINF_SUCCESS)
1877 return rcStrict;
1878
1879 /* Is it there? */
1880 if (!Desc.Legacy.Gen.u1Present) /** @todo this is probably checked too early. Testcase! */
1881 {
1882 Log(("jmpf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
1883 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1884 }
1885
1886 /*
1887 * Deal with it according to its type. We do the standard code selectors
1888 * here and dispatch the system selectors to worker functions.
1889 */
1890 if (!Desc.Legacy.Gen.u1DescType)
1891 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_JUMP, enmEffOpSize, &Desc);
1892
1893 /* Only code segments. */
1894 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
1895 {
1896 Log(("jmpf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
1897 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1898 }
1899
1900 /* L vs D. */
1901 if ( Desc.Legacy.Gen.u1Long
1902 && Desc.Legacy.Gen.u1DefBig
1903 && IEM_IS_LONG_MODE(pVCpu))
1904 {
1905 Log(("jmpf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
1906 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1907 }
1908
1909 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
1910 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1911 {
1912 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
1913 {
1914 Log(("jmpf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
1915 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1916 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1917 }
1918 }
1919 else
1920 {
1921 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
1922 {
1923 Log(("jmpf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1924 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1925 }
1926 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
1927 {
1928 Log(("jmpf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
1929 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1930 }
1931 }
1932
1933 /* Chop the high bits if 16-bit (Intel says so). */
1934 if (enmEffOpSize == IEMMODE_16BIT)
1935 offSeg &= UINT16_MAX;
1936
1937 /* Limit check. (Should alternatively check for non-canonical addresses
1938 here, but that is ruled out by offSeg being 32-bit, right?) */
1939 uint64_t u64Base;
1940 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
1941 if (Desc.Legacy.Gen.u1Long)
1942 u64Base = 0;
1943 else
1944 {
1945 if (offSeg > cbLimit)
1946 {
1947 Log(("jmpf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
1948 /** @todo Intel says this is \#GP(0)! */
1949 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1950 }
1951 u64Base = X86DESC_BASE(&Desc.Legacy);
1952 }
1953
1954 /*
1955 * Ok, everything checked out fine. Now set the accessed bit before
1956 * committing the result into CS, CSHID and RIP.
1957 */
1958 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1959 {
1960 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
1961 if (rcStrict != VINF_SUCCESS)
1962 return rcStrict;
1963 /** @todo check what VT-x and AMD-V does. */
1964 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1965 }
1966
1967 /* commit */
1968 pVCpu->cpum.GstCtx.rip = offSeg;
1969 pVCpu->cpum.GstCtx.cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
1970 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1971 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1972 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1973 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
1974 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1975 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1976 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1977 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1978 /** @todo check if the hidden bits are loaded correctly for 64-bit
1979 * mode. */
1980
1981 /* Flush the prefetch buffer. */
1982#ifdef IEM_WITH_CODE_TLB
1983 pVCpu->iem.s.pbInstrBuf = NULL;
1984#else
1985 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1986#endif
1987
1988 return VINF_SUCCESS;
1989}
1990
1991
1992/**
1993 * Implements far calls.
1994 *
1995 * This very similar to iemCImpl_FarJmp.
1996 *
1997 * @param uSel The selector.
1998 * @param offSeg The segment offset.
1999 * @param enmEffOpSize The operand size (in case we need it).
2000 */
2001IEM_CIMPL_DEF_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
2002{
2003 VBOXSTRICTRC rcStrict;
2004 uint64_t uNewRsp;
2005 RTPTRUNION uPtrRet;
2006
2007 /*
2008 * Real mode and V8086 mode are easy. The only snag seems to be that
2009 * CS.limit doesn't change and the limit check is done against the current
2010 * limit.
2011 */
2012 /** @todo See comment for similar code in iemCImpl_FarJmp */
2013 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
2014 {
2015 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
2016
2017 /* Check stack first - may #SS(0). */
2018 rcStrict = iemMemStackPushBeginSpecial(pVCpu, enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
2019 enmEffOpSize == IEMMODE_32BIT ? 3 : 1,
2020 &uPtrRet.pv, &uNewRsp);
2021 if (rcStrict != VINF_SUCCESS)
2022 return rcStrict;
2023
2024 /* Check the target address range. */
2025 if (offSeg > UINT32_MAX)
2026 return iemRaiseGeneralProtectionFault0(pVCpu);
2027
2028 /* Everything is fine, push the return address. */
2029 if (enmEffOpSize == IEMMODE_16BIT)
2030 {
2031 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
2032 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
2033 }
2034 else
2035 {
2036 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
2037 uPtrRet.pu16[2] = pVCpu->cpum.GstCtx.cs.Sel;
2038 }
2039 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2040 if (rcStrict != VINF_SUCCESS)
2041 return rcStrict;
2042
2043 /* Branch. */
2044 pVCpu->cpum.GstCtx.rip = offSeg;
2045 pVCpu->cpum.GstCtx.cs.Sel = uSel;
2046 pVCpu->cpum.GstCtx.cs.ValidSel = uSel;
2047 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2048 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uSel << 4;
2049 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2050 return VINF_SUCCESS;
2051 }
2052
2053 /*
2054 * Protected mode. Need to parse the specified descriptor...
2055 */
2056 if (!(uSel & X86_SEL_MASK_OFF_RPL))
2057 {
2058 Log(("callf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
2059 return iemRaiseGeneralProtectionFault0(pVCpu);
2060 }
2061
2062 /* Fetch the descriptor. */
2063 IEMSELDESC Desc;
2064 rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
2065 if (rcStrict != VINF_SUCCESS)
2066 return rcStrict;
2067
2068 /*
2069 * Deal with it according to its type. We do the standard code selectors
2070 * here and dispatch the system selectors to worker functions.
2071 */
2072 if (!Desc.Legacy.Gen.u1DescType)
2073 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_CALL, enmEffOpSize, &Desc);
2074
2075 /* Only code segments. */
2076 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
2077 {
2078 Log(("callf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
2079 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2080 }
2081
2082 /* L vs D. */
2083 if ( Desc.Legacy.Gen.u1Long
2084 && Desc.Legacy.Gen.u1DefBig
2085 && IEM_IS_LONG_MODE(pVCpu))
2086 {
2087 Log(("callf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
2088 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2089 }
2090
2091 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
2092 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2093 {
2094 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
2095 {
2096 Log(("callf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
2097 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2098 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2099 }
2100 }
2101 else
2102 {
2103 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
2104 {
2105 Log(("callf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2106 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2107 }
2108 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
2109 {
2110 Log(("callf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
2111 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2112 }
2113 }
2114
2115 /* Is it there? */
2116 if (!Desc.Legacy.Gen.u1Present)
2117 {
2118 Log(("callf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
2119 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
2120 }
2121
2122 /* Check stack first - may #SS(0). */
2123 /** @todo check how operand prefix affects pushing of CS! Does callf 16:32 in
2124 * 16-bit code cause a two or four byte CS to be pushed? */
2125 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
2126 enmEffOpSize == IEMMODE_64BIT ? 8+8 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
2127 enmEffOpSize == IEMMODE_64BIT ? 7 : enmEffOpSize == IEMMODE_32BIT ? 3 : 1,
2128 &uPtrRet.pv, &uNewRsp);
2129 if (rcStrict != VINF_SUCCESS)
2130 return rcStrict;
2131
2132 /* Chop the high bits if 16-bit (Intel says so). */
2133 if (enmEffOpSize == IEMMODE_16BIT)
2134 offSeg &= UINT16_MAX;
2135
2136 /* Limit / canonical check. */
2137 uint64_t u64Base;
2138 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
2139 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2140 {
2141 if (!IEM_IS_CANONICAL(offSeg))
2142 {
2143 Log(("callf %04x:%016RX64 - not canonical -> #GP\n", uSel, offSeg));
2144 return iemRaiseNotCanonical(pVCpu);
2145 }
2146 u64Base = 0;
2147 }
2148 else
2149 {
2150 if (offSeg > cbLimit)
2151 {
2152 Log(("callf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
2153 /** @todo Intel says this is \#GP(0)! */
2154 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2155 }
2156 u64Base = X86DESC_BASE(&Desc.Legacy);
2157 }
2158
2159 /*
2160 * Now set the accessed bit before
2161 * writing the return address to the stack and committing the result into
2162 * CS, CSHID and RIP.
2163 */
2164 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2165 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2166 {
2167 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
2168 if (rcStrict != VINF_SUCCESS)
2169 return rcStrict;
2170 /** @todo check what VT-x and AMD-V does. */
2171 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2172 }
2173
2174 /* stack */
2175 if (enmEffOpSize == IEMMODE_16BIT)
2176 {
2177 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
2178 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
2179 }
2180 else if (enmEffOpSize == IEMMODE_32BIT)
2181 {
2182 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
2183 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when callf is pushing CS? */
2184 }
2185 else
2186 {
2187 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
2188 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when callf is pushing CS? */
2189 }
2190 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2191 if (rcStrict != VINF_SUCCESS)
2192 return rcStrict;
2193
2194 /* commit */
2195 pVCpu->cpum.GstCtx.rip = offSeg;
2196 pVCpu->cpum.GstCtx.cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
2197 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
2198 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
2199 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2200 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
2201 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
2202 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2203 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2204 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2205 /** @todo check if the hidden bits are loaded correctly for 64-bit
2206 * mode. */
2207
2208 /* Flush the prefetch buffer. */
2209#ifdef IEM_WITH_CODE_TLB
2210 pVCpu->iem.s.pbInstrBuf = NULL;
2211#else
2212 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2213#endif
2214 return VINF_SUCCESS;
2215}
2216
2217
2218/**
2219 * Implements retf.
2220 *
2221 * @param enmEffOpSize The effective operand size.
2222 * @param cbPop The amount of arguments to pop from the stack
2223 * (bytes).
2224 */
2225IEM_CIMPL_DEF_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2226{
2227 VBOXSTRICTRC rcStrict;
2228 RTCPTRUNION uPtrFrame;
2229 uint64_t uNewRsp;
2230 uint64_t uNewRip;
2231 uint16_t uNewCs;
2232 NOREF(cbInstr);
2233
2234 /*
2235 * Read the stack values first.
2236 */
2237 uint32_t cbRetPtr = enmEffOpSize == IEMMODE_16BIT ? 2+2
2238 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 8+8;
2239 rcStrict = iemMemStackPopBeginSpecial(pVCpu, cbRetPtr,
2240 enmEffOpSize == IEMMODE_16BIT ? 1 : enmEffOpSize == IEMMODE_32BIT ? 3 : 7,
2241 &uPtrFrame.pv, &uNewRsp);
2242 if (rcStrict != VINF_SUCCESS)
2243 return rcStrict;
2244 if (enmEffOpSize == IEMMODE_16BIT)
2245 {
2246 uNewRip = uPtrFrame.pu16[0];
2247 uNewCs = uPtrFrame.pu16[1];
2248 }
2249 else if (enmEffOpSize == IEMMODE_32BIT)
2250 {
2251 uNewRip = uPtrFrame.pu32[0];
2252 uNewCs = uPtrFrame.pu16[2];
2253 }
2254 else
2255 {
2256 uNewRip = uPtrFrame.pu64[0];
2257 uNewCs = uPtrFrame.pu16[4];
2258 }
2259 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2260 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2261 { /* extremely likely */ }
2262 else
2263 return rcStrict;
2264
2265 /*
2266 * Real mode and V8086 mode are easy.
2267 */
2268 /** @todo See comment for similar code in iemCImpl_FarJmp */
2269 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
2270 {
2271 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2272 /** @todo check how this is supposed to work if sp=0xfffe. */
2273
2274 /* Check the limit of the new EIP. */
2275 /** @todo Intel pseudo code only does the limit check for 16-bit
2276 * operands, AMD does not make any distinction. What is right? */
2277 if (uNewRip > pVCpu->cpum.GstCtx.cs.u32Limit)
2278 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2279
2280 /* commit the operation. */
2281 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2282 pVCpu->cpum.GstCtx.rip = uNewRip;
2283 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2284 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2285 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2286 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uNewCs << 4;
2287 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2288 if (cbPop)
2289 iemRegAddToRsp(pVCpu, cbPop);
2290 return VINF_SUCCESS;
2291 }
2292
2293 /*
2294 * Protected mode is complicated, of course.
2295 */
2296 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
2297 {
2298 Log(("retf %04x:%08RX64 -> invalid selector, #GP(0)\n", uNewCs, uNewRip));
2299 return iemRaiseGeneralProtectionFault0(pVCpu);
2300 }
2301
2302 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_LDTR);
2303
2304 /* Fetch the descriptor. */
2305 IEMSELDESC DescCs;
2306 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCs, uNewCs, X86_XCPT_GP);
2307 if (rcStrict != VINF_SUCCESS)
2308 return rcStrict;
2309
2310 /* Can only return to a code selector. */
2311 if ( !DescCs.Legacy.Gen.u1DescType
2312 || !(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
2313 {
2314 Log(("retf %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
2315 uNewCs, uNewRip, DescCs.Legacy.Gen.u1DescType, DescCs.Legacy.Gen.u4Type));
2316 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2317 }
2318
2319 /* L vs D. */
2320 if ( DescCs.Legacy.Gen.u1Long /** @todo Testcase: far return to a selector with both L and D set. */
2321 && DescCs.Legacy.Gen.u1DefBig
2322 && IEM_IS_LONG_MODE(pVCpu))
2323 {
2324 Log(("retf %04x:%08RX64 -> both L & D set.\n", uNewCs, uNewRip));
2325 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2326 }
2327
2328 /* DPL/RPL/CPL checks. */
2329 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
2330 {
2331 Log(("retf %04x:%08RX64 -> RPL < CPL(%d).\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
2332 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2333 }
2334
2335 if (DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2336 {
2337 if ((uNewCs & X86_SEL_RPL) < DescCs.Legacy.Gen.u2Dpl)
2338 {
2339 Log(("retf %04x:%08RX64 -> DPL violation (conforming); DPL=%u RPL=%u\n",
2340 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2341 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2342 }
2343 }
2344 else
2345 {
2346 if ((uNewCs & X86_SEL_RPL) != DescCs.Legacy.Gen.u2Dpl)
2347 {
2348 Log(("retf %04x:%08RX64 -> RPL != DPL; DPL=%u RPL=%u\n",
2349 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2350 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2351 }
2352 }
2353
2354 /* Is it there? */
2355 if (!DescCs.Legacy.Gen.u1Present)
2356 {
2357 Log(("retf %04x:%08RX64 -> segment not present\n", uNewCs, uNewRip));
2358 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2359 }
2360
2361 /*
2362 * Return to outer privilege? (We'll typically have entered via a call gate.)
2363 */
2364 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
2365 {
2366 /* Read the outer stack pointer stored *after* the parameters. */
2367 rcStrict = iemMemStackPopContinueSpecial(pVCpu, cbPop /*off*/, cbRetPtr, &uPtrFrame.pv, uNewRsp);
2368 if (rcStrict != VINF_SUCCESS)
2369 return rcStrict;
2370
2371 uint16_t uNewOuterSs;
2372 uint64_t uNewOuterRsp;
2373 if (enmEffOpSize == IEMMODE_16BIT)
2374 {
2375 uNewOuterRsp = uPtrFrame.pu16[0];
2376 uNewOuterSs = uPtrFrame.pu16[1];
2377 }
2378 else if (enmEffOpSize == IEMMODE_32BIT)
2379 {
2380 uNewOuterRsp = uPtrFrame.pu32[0];
2381 uNewOuterSs = uPtrFrame.pu16[2];
2382 }
2383 else
2384 {
2385 uNewOuterRsp = uPtrFrame.pu64[0];
2386 uNewOuterSs = uPtrFrame.pu16[4];
2387 }
2388 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2389 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2390 { /* extremely likely */ }
2391 else
2392 return rcStrict;
2393
2394 /* Check for NULL stack selector (invalid in ring-3 and non-long mode)
2395 and read the selector. */
2396 IEMSELDESC DescSs;
2397 if (!(uNewOuterSs & X86_SEL_MASK_OFF_RPL))
2398 {
2399 if ( !DescCs.Legacy.Gen.u1Long
2400 || (uNewOuterSs & X86_SEL_RPL) == 3)
2401 {
2402 Log(("retf %04x:%08RX64 %04x:%08RX64 -> invalid stack selector, #GP\n",
2403 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2404 return iemRaiseGeneralProtectionFault0(pVCpu);
2405 }
2406 /** @todo Testcase: Return far to ring-1 or ring-2 with SS=0. */
2407 iemMemFakeStackSelDesc(&DescSs, (uNewOuterSs & X86_SEL_RPL));
2408 }
2409 else
2410 {
2411 /* Fetch the descriptor for the new stack segment. */
2412 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSs, uNewOuterSs, X86_XCPT_GP);
2413 if (rcStrict != VINF_SUCCESS)
2414 return rcStrict;
2415 }
2416
2417 /* Check that RPL of stack and code selectors match. */
2418 if ((uNewCs & X86_SEL_RPL) != (uNewOuterSs & X86_SEL_RPL))
2419 {
2420 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.RPL != CS.RPL -> #GP(SS)\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2421 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2422 }
2423
2424 /* Must be a writable data segment. */
2425 if ( !DescSs.Legacy.Gen.u1DescType
2426 || (DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
2427 || !(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
2428 {
2429 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not a writable data segment (u1DescType=%u u4Type=%#x) -> #GP(SS).\n",
2430 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u1DescType, DescSs.Legacy.Gen.u4Type));
2431 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2432 }
2433
2434 /* L vs D. (Not mentioned by intel.) */
2435 if ( DescSs.Legacy.Gen.u1Long /** @todo Testcase: far return to a stack selector with both L and D set. */
2436 && DescSs.Legacy.Gen.u1DefBig
2437 && IEM_IS_LONG_MODE(pVCpu))
2438 {
2439 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS has both L & D set -> #GP(SS).\n",
2440 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2441 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2442 }
2443
2444 /* DPL/RPL/CPL checks. */
2445 if (DescSs.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
2446 {
2447 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.DPL(%u) != CS.RPL (%u) -> #GP(SS).\n",
2448 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u2Dpl, uNewCs & X86_SEL_RPL));
2449 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2450 }
2451
2452 /* Is it there? */
2453 if (!DescSs.Legacy.Gen.u1Present)
2454 {
2455 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not present -> #NP(SS).\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2456 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2457 }
2458
2459 /* Calc SS limit.*/
2460 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSs.Legacy);
2461
2462 /* Is RIP canonical or within CS.limit? */
2463 uint64_t u64Base;
2464 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2465
2466 /** @todo Testcase: Is this correct? */
2467 if ( DescCs.Legacy.Gen.u1Long
2468 && IEM_IS_LONG_MODE(pVCpu) )
2469 {
2470 if (!IEM_IS_CANONICAL(uNewRip))
2471 {
2472 Log(("retf %04x:%08RX64 %04x:%08RX64 - not canonical -> #GP.\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2473 return iemRaiseNotCanonical(pVCpu);
2474 }
2475 u64Base = 0;
2476 }
2477 else
2478 {
2479 if (uNewRip > cbLimitCs)
2480 {
2481 Log(("retf %04x:%08RX64 %04x:%08RX64 - out of bounds (%#x)-> #GP(CS).\n",
2482 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, cbLimitCs));
2483 /** @todo Intel says this is \#GP(0)! */
2484 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2485 }
2486 u64Base = X86DESC_BASE(&DescCs.Legacy);
2487 }
2488
2489 /*
2490 * Now set the accessed bit before
2491 * writing the return address to the stack and committing the result into
2492 * CS, CSHID and RIP.
2493 */
2494 /** @todo Testcase: Need to check WHEN exactly the CS accessed bit is set. */
2495 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2496 {
2497 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2498 if (rcStrict != VINF_SUCCESS)
2499 return rcStrict;
2500 /** @todo check what VT-x and AMD-V does. */
2501 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2502 }
2503 /** @todo Testcase: Need to check WHEN exactly the SS accessed bit is set. */
2504 if (!(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2505 {
2506 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewOuterSs);
2507 if (rcStrict != VINF_SUCCESS)
2508 return rcStrict;
2509 /** @todo check what VT-x and AMD-V does. */
2510 DescSs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2511 }
2512
2513 /* commit */
2514 if (enmEffOpSize == IEMMODE_16BIT)
2515 pVCpu->cpum.GstCtx.rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2516 else
2517 pVCpu->cpum.GstCtx.rip = uNewRip;
2518 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2519 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2520 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2521 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2522 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCs;
2523 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2524 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2525 pVCpu->cpum.GstCtx.ss.Sel = uNewOuterSs;
2526 pVCpu->cpum.GstCtx.ss.ValidSel = uNewOuterSs;
2527 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
2528 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSs.Legacy);
2529 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
2530 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2531 pVCpu->cpum.GstCtx.ss.u64Base = 0;
2532 else
2533 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSs.Legacy);
2534 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2535 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewOuterRsp;
2536 else
2537 pVCpu->cpum.GstCtx.rsp = uNewOuterRsp;
2538
2539 pVCpu->iem.s.uCpl = (uNewCs & X86_SEL_RPL);
2540 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.ds);
2541 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.es);
2542 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.fs);
2543 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.gs);
2544
2545 /** @todo check if the hidden bits are loaded correctly for 64-bit
2546 * mode. */
2547
2548 if (cbPop)
2549 iemRegAddToRsp(pVCpu, cbPop);
2550 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2551
2552 /* Done! */
2553 }
2554 /*
2555 * Return to the same privilege level
2556 */
2557 else
2558 {
2559 /* Limit / canonical check. */
2560 uint64_t u64Base;
2561 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2562
2563 /** @todo Testcase: Is this correct? */
2564 if ( DescCs.Legacy.Gen.u1Long
2565 && IEM_IS_LONG_MODE(pVCpu) )
2566 {
2567 if (!IEM_IS_CANONICAL(uNewRip))
2568 {
2569 Log(("retf %04x:%08RX64 - not canonical -> #GP\n", uNewCs, uNewRip));
2570 return iemRaiseNotCanonical(pVCpu);
2571 }
2572 u64Base = 0;
2573 }
2574 else
2575 {
2576 if (uNewRip > cbLimitCs)
2577 {
2578 Log(("retf %04x:%08RX64 -> out of bounds (%#x)\n", uNewCs, uNewRip, cbLimitCs));
2579 /** @todo Intel says this is \#GP(0)! */
2580 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2581 }
2582 u64Base = X86DESC_BASE(&DescCs.Legacy);
2583 }
2584
2585 /*
2586 * Now set the accessed bit before
2587 * writing the return address to the stack and committing the result into
2588 * CS, CSHID and RIP.
2589 */
2590 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2591 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2592 {
2593 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2594 if (rcStrict != VINF_SUCCESS)
2595 return rcStrict;
2596 /** @todo check what VT-x and AMD-V does. */
2597 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2598 }
2599
2600 /* commit */
2601 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2602 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
2603 else
2604 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2605 if (enmEffOpSize == IEMMODE_16BIT)
2606 pVCpu->cpum.GstCtx.rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2607 else
2608 pVCpu->cpum.GstCtx.rip = uNewRip;
2609 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2610 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2611 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2612 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2613 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCs;
2614 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2615 /** @todo check if the hidden bits are loaded correctly for 64-bit
2616 * mode. */
2617 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2618 if (cbPop)
2619 iemRegAddToRsp(pVCpu, cbPop);
2620 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2621 }
2622
2623 /* Flush the prefetch buffer. */
2624#ifdef IEM_WITH_CODE_TLB
2625 pVCpu->iem.s.pbInstrBuf = NULL;
2626#else
2627 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2628#endif
2629 return VINF_SUCCESS;
2630}
2631
2632
2633/**
2634 * Implements retn.
2635 *
2636 * We're doing this in C because of the \#GP that might be raised if the popped
2637 * program counter is out of bounds.
2638 *
2639 * @param enmEffOpSize The effective operand size.
2640 * @param cbPop The amount of arguments to pop from the stack
2641 * (bytes).
2642 */
2643IEM_CIMPL_DEF_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2644{
2645 NOREF(cbInstr);
2646
2647 /* Fetch the RSP from the stack. */
2648 VBOXSTRICTRC rcStrict;
2649 RTUINT64U NewRip;
2650 RTUINT64U NewRsp;
2651 NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2652
2653 switch (enmEffOpSize)
2654 {
2655 case IEMMODE_16BIT:
2656 NewRip.u = 0;
2657 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRip.Words.w0, &NewRsp);
2658 break;
2659 case IEMMODE_32BIT:
2660 NewRip.u = 0;
2661 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRip.DWords.dw0, &NewRsp);
2662 break;
2663 case IEMMODE_64BIT:
2664 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRip.u, &NewRsp);
2665 break;
2666 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2667 }
2668 if (rcStrict != VINF_SUCCESS)
2669 return rcStrict;
2670
2671 /* Check the new RSP before loading it. */
2672 /** @todo Should test this as the intel+amd pseudo code doesn't mention half
2673 * of it. The canonical test is performed here and for call. */
2674 if (enmEffOpSize != IEMMODE_64BIT)
2675 {
2676 if (NewRip.DWords.dw0 > pVCpu->cpum.GstCtx.cs.u32Limit)
2677 {
2678 Log(("retn newrip=%llx - out of bounds (%x) -> #GP\n", NewRip.u, pVCpu->cpum.GstCtx.cs.u32Limit));
2679 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2680 }
2681 }
2682 else
2683 {
2684 if (!IEM_IS_CANONICAL(NewRip.u))
2685 {
2686 Log(("retn newrip=%llx - not canonical -> #GP\n", NewRip.u));
2687 return iemRaiseNotCanonical(pVCpu);
2688 }
2689 }
2690
2691 /* Apply cbPop */
2692 if (cbPop)
2693 iemRegAddToRspEx(pVCpu, &NewRsp, cbPop);
2694
2695 /* Commit it. */
2696 pVCpu->cpum.GstCtx.rip = NewRip.u;
2697 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2698 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2699
2700 /* Flush the prefetch buffer. */
2701#ifndef IEM_WITH_CODE_TLB
2702 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2703#endif
2704
2705 return VINF_SUCCESS;
2706}
2707
2708
2709/**
2710 * Implements enter.
2711 *
2712 * We're doing this in C because the instruction is insane, even for the
2713 * u8NestingLevel=0 case dealing with the stack is tedious.
2714 *
2715 * @param enmEffOpSize The effective operand size.
2716 * @param cbFrame Frame size.
2717 * @param cParameters Frame parameter count.
2718 */
2719IEM_CIMPL_DEF_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters)
2720{
2721 /* Push RBP, saving the old value in TmpRbp. */
2722 RTUINT64U NewRsp; NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2723 RTUINT64U TmpRbp; TmpRbp.u = pVCpu->cpum.GstCtx.rbp;
2724 RTUINT64U NewRbp;
2725 VBOXSTRICTRC rcStrict;
2726 if (enmEffOpSize == IEMMODE_64BIT)
2727 {
2728 rcStrict = iemMemStackPushU64Ex(pVCpu, TmpRbp.u, &NewRsp);
2729 NewRbp = NewRsp;
2730 }
2731 else if (enmEffOpSize == IEMMODE_32BIT)
2732 {
2733 rcStrict = iemMemStackPushU32Ex(pVCpu, TmpRbp.DWords.dw0, &NewRsp);
2734 NewRbp = NewRsp;
2735 }
2736 else
2737 {
2738 rcStrict = iemMemStackPushU16Ex(pVCpu, TmpRbp.Words.w0, &NewRsp);
2739 NewRbp = TmpRbp;
2740 NewRbp.Words.w0 = NewRsp.Words.w0;
2741 }
2742 if (rcStrict != VINF_SUCCESS)
2743 return rcStrict;
2744
2745 /* Copy the parameters (aka nesting levels by Intel). */
2746 cParameters &= 0x1f;
2747 if (cParameters > 0)
2748 {
2749 switch (enmEffOpSize)
2750 {
2751 case IEMMODE_16BIT:
2752 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2753 TmpRbp.DWords.dw0 -= 2;
2754 else
2755 TmpRbp.Words.w0 -= 2;
2756 do
2757 {
2758 uint16_t u16Tmp;
2759 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Tmp, &TmpRbp);
2760 if (rcStrict != VINF_SUCCESS)
2761 break;
2762 rcStrict = iemMemStackPushU16Ex(pVCpu, u16Tmp, &NewRsp);
2763 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2764 break;
2765
2766 case IEMMODE_32BIT:
2767 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2768 TmpRbp.DWords.dw0 -= 4;
2769 else
2770 TmpRbp.Words.w0 -= 4;
2771 do
2772 {
2773 uint32_t u32Tmp;
2774 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Tmp, &TmpRbp);
2775 if (rcStrict != VINF_SUCCESS)
2776 break;
2777 rcStrict = iemMemStackPushU32Ex(pVCpu, u32Tmp, &NewRsp);
2778 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2779 break;
2780
2781 case IEMMODE_64BIT:
2782 TmpRbp.u -= 8;
2783 do
2784 {
2785 uint64_t u64Tmp;
2786 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Tmp, &TmpRbp);
2787 if (rcStrict != VINF_SUCCESS)
2788 break;
2789 rcStrict = iemMemStackPushU64Ex(pVCpu, u64Tmp, &NewRsp);
2790 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2791 break;
2792
2793 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2794 }
2795 if (rcStrict != VINF_SUCCESS)
2796 return VINF_SUCCESS;
2797
2798 /* Push the new RBP */
2799 if (enmEffOpSize == IEMMODE_64BIT)
2800 rcStrict = iemMemStackPushU64Ex(pVCpu, NewRbp.u, &NewRsp);
2801 else if (enmEffOpSize == IEMMODE_32BIT)
2802 rcStrict = iemMemStackPushU32Ex(pVCpu, NewRbp.DWords.dw0, &NewRsp);
2803 else
2804 rcStrict = iemMemStackPushU16Ex(pVCpu, NewRbp.Words.w0, &NewRsp);
2805 if (rcStrict != VINF_SUCCESS)
2806 return rcStrict;
2807
2808 }
2809
2810 /* Recalc RSP. */
2811 iemRegSubFromRspEx(pVCpu, &NewRsp, cbFrame);
2812
2813 /** @todo Should probe write access at the new RSP according to AMD. */
2814 /** @todo Should handle accesses to the VMX APIC-access page. */
2815
2816 /* Commit it. */
2817 pVCpu->cpum.GstCtx.rbp = NewRbp.u;
2818 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2819 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2820
2821 return VINF_SUCCESS;
2822}
2823
2824
2825
2826/**
2827 * Implements leave.
2828 *
2829 * We're doing this in C because messing with the stack registers is annoying
2830 * since they depends on SS attributes.
2831 *
2832 * @param enmEffOpSize The effective operand size.
2833 */
2834IEM_CIMPL_DEF_1(iemCImpl_leave, IEMMODE, enmEffOpSize)
2835{
2836 /* Calculate the intermediate RSP from RBP and the stack attributes. */
2837 RTUINT64U NewRsp;
2838 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2839 NewRsp.u = pVCpu->cpum.GstCtx.rbp;
2840 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2841 NewRsp.u = pVCpu->cpum.GstCtx.ebp;
2842 else
2843 {
2844 /** @todo Check that LEAVE actually preserve the high EBP bits. */
2845 NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2846 NewRsp.Words.w0 = pVCpu->cpum.GstCtx.bp;
2847 }
2848
2849 /* Pop RBP according to the operand size. */
2850 VBOXSTRICTRC rcStrict;
2851 RTUINT64U NewRbp;
2852 switch (enmEffOpSize)
2853 {
2854 case IEMMODE_16BIT:
2855 NewRbp.u = pVCpu->cpum.GstCtx.rbp;
2856 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRbp.Words.w0, &NewRsp);
2857 break;
2858 case IEMMODE_32BIT:
2859 NewRbp.u = 0;
2860 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRbp.DWords.dw0, &NewRsp);
2861 break;
2862 case IEMMODE_64BIT:
2863 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRbp.u, &NewRsp);
2864 break;
2865 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2866 }
2867 if (rcStrict != VINF_SUCCESS)
2868 return rcStrict;
2869
2870
2871 /* Commit it. */
2872 pVCpu->cpum.GstCtx.rbp = NewRbp.u;
2873 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2874 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2875
2876 return VINF_SUCCESS;
2877}
2878
2879
2880/**
2881 * Implements int3 and int XX.
2882 *
2883 * @param u8Int The interrupt vector number.
2884 * @param enmInt The int instruction type.
2885 */
2886IEM_CIMPL_DEF_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt)
2887{
2888 Assert(pVCpu->iem.s.cXcptRecursions == 0);
2889
2890 /*
2891 * We must check if this INT3 might belong to DBGF before raising a #BP.
2892 */
2893 if (u8Int == 3)
2894 {
2895 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2896 if (pVM->dbgf.ro.cEnabledInt3Breakpoints == 0)
2897 { /* likely: No vbox debugger breakpoints */ }
2898 else
2899 {
2900 VBOXSTRICTRC rcStrict = DBGFTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx));
2901 Log(("iemCImpl_int: DBGFTrap03Handler -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict) ));
2902 if (rcStrict != VINF_EM_RAW_GUEST_TRAP)
2903 return iemSetPassUpStatus(pVCpu, rcStrict);
2904 }
2905 }
2906 return iemRaiseXcptOrInt(pVCpu,
2907 cbInstr,
2908 u8Int,
2909 IEM_XCPT_FLAGS_T_SOFT_INT | enmInt,
2910 0,
2911 0);
2912}
2913
2914
2915/**
2916 * Implements iret for real mode and V8086 mode.
2917 *
2918 * @param enmEffOpSize The effective operand size.
2919 */
2920IEM_CIMPL_DEF_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize)
2921{
2922 X86EFLAGS Efl;
2923 Efl.u = IEMMISC_GET_EFL(pVCpu);
2924 NOREF(cbInstr);
2925
2926 /*
2927 * iret throws an exception if VME isn't enabled.
2928 */
2929 if ( Efl.Bits.u1VM
2930 && Efl.Bits.u2IOPL != 3
2931 && !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME))
2932 return iemRaiseGeneralProtectionFault0(pVCpu);
2933
2934 /*
2935 * Do the stack bits, but don't commit RSP before everything checks
2936 * out right.
2937 */
2938 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2939 VBOXSTRICTRC rcStrict;
2940 RTCPTRUNION uFrame;
2941 uint16_t uNewCs;
2942 uint32_t uNewEip;
2943 uint32_t uNewFlags;
2944 uint64_t uNewRsp;
2945 if (enmEffOpSize == IEMMODE_32BIT)
2946 {
2947 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, 1, &uFrame.pv, &uNewRsp);
2948 if (rcStrict != VINF_SUCCESS)
2949 return rcStrict;
2950 uNewEip = uFrame.pu32[0];
2951 if (uNewEip > UINT16_MAX)
2952 return iemRaiseGeneralProtectionFault0(pVCpu);
2953
2954 uNewCs = (uint16_t)uFrame.pu32[1];
2955 uNewFlags = uFrame.pu32[2];
2956 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2957 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT
2958 | X86_EFL_RF /*| X86_EFL_VM*/ | X86_EFL_AC /*|X86_EFL_VIF*/ /*|X86_EFL_VIP*/
2959 | X86_EFL_ID;
2960 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
2961 uNewFlags &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
2962 uNewFlags |= Efl.u & (X86_EFL_VM | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_1);
2963 }
2964 else
2965 {
2966 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, 1, &uFrame.pv, &uNewRsp);
2967 if (rcStrict != VINF_SUCCESS)
2968 return rcStrict;
2969 uNewEip = uFrame.pu16[0];
2970 uNewCs = uFrame.pu16[1];
2971 uNewFlags = uFrame.pu16[2];
2972 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2973 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT;
2974 uNewFlags |= Efl.u & ((UINT32_C(0xffff0000) | X86_EFL_1) & ~X86_EFL_RF);
2975 /** @todo The intel pseudo code does not indicate what happens to
2976 * reserved flags. We just ignore them. */
2977 /* Ancient CPU adjustments: See iemCImpl_popf. */
2978 if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286)
2979 uNewFlags &= ~(X86_EFL_NT | X86_EFL_IOPL);
2980 }
2981 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uFrame.pv);
2982 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2983 { /* extremely likely */ }
2984 else
2985 return rcStrict;
2986
2987 /** @todo Check how this is supposed to work if sp=0xfffe. */
2988 Log7(("iemCImpl_iret_real_v8086: uNewCs=%#06x uNewRip=%#010x uNewFlags=%#x uNewRsp=%#18llx\n",
2989 uNewCs, uNewEip, uNewFlags, uNewRsp));
2990
2991 /*
2992 * Check the limit of the new EIP.
2993 */
2994 /** @todo Only the AMD pseudo code check the limit here, what's
2995 * right? */
2996 if (uNewEip > pVCpu->cpum.GstCtx.cs.u32Limit)
2997 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2998
2999 /*
3000 * V8086 checks and flag adjustments
3001 */
3002 if (Efl.Bits.u1VM)
3003 {
3004 if (Efl.Bits.u2IOPL == 3)
3005 {
3006 /* Preserve IOPL and clear RF. */
3007 uNewFlags &= ~(X86_EFL_IOPL | X86_EFL_RF);
3008 uNewFlags |= Efl.u & (X86_EFL_IOPL);
3009 }
3010 else if ( enmEffOpSize == IEMMODE_16BIT
3011 && ( !(uNewFlags & X86_EFL_IF)
3012 || !Efl.Bits.u1VIP )
3013 && !(uNewFlags & X86_EFL_TF) )
3014 {
3015 /* Move IF to VIF, clear RF and preserve IF and IOPL.*/
3016 uNewFlags &= ~X86_EFL_VIF;
3017 uNewFlags |= (uNewFlags & X86_EFL_IF) << (19 - 9);
3018 uNewFlags &= ~(X86_EFL_IF | X86_EFL_IOPL | X86_EFL_RF);
3019 uNewFlags |= Efl.u & (X86_EFL_IF | X86_EFL_IOPL);
3020 }
3021 else
3022 return iemRaiseGeneralProtectionFault0(pVCpu);
3023 Log7(("iemCImpl_iret_real_v8086: u1VM=1: adjusted uNewFlags=%#x\n", uNewFlags));
3024 }
3025
3026 /*
3027 * Commit the operation.
3028 */
3029#ifdef DBGFTRACE_ENABLED
3030 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/rm %04x:%04x -> %04x:%04x %x %04llx",
3031 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewRsp);
3032#endif
3033 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3034 pVCpu->cpum.GstCtx.rip = uNewEip;
3035 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3036 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3037 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3038 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uNewCs << 4;
3039 /** @todo do we load attribs and limit as well? */
3040 Assert(uNewFlags & X86_EFL_1);
3041 IEMMISC_SET_EFL(pVCpu, uNewFlags);
3042
3043 /* Flush the prefetch buffer. */
3044#ifdef IEM_WITH_CODE_TLB
3045 pVCpu->iem.s.pbInstrBuf = NULL;
3046#else
3047 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3048#endif
3049
3050 return VINF_SUCCESS;
3051}
3052
3053
3054/**
3055 * Loads a segment register when entering V8086 mode.
3056 *
3057 * @param pSReg The segment register.
3058 * @param uSeg The segment to load.
3059 */
3060static void iemCImplCommonV8086LoadSeg(PCPUMSELREG pSReg, uint16_t uSeg)
3061{
3062 pSReg->Sel = uSeg;
3063 pSReg->ValidSel = uSeg;
3064 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
3065 pSReg->u64Base = (uint32_t)uSeg << 4;
3066 pSReg->u32Limit = 0xffff;
3067 pSReg->Attr.u = X86_SEL_TYPE_RW_ACC | RT_BIT(4) /*!sys*/ | RT_BIT(7) /*P*/ | (3 /*DPL*/ << 5); /* VT-x wants 0xf3 */
3068 /** @todo Testcase: Check if VT-x really needs this and what it does itself when
3069 * IRET'ing to V8086. */
3070}
3071
3072
3073/**
3074 * Implements iret for protected mode returning to V8086 mode.
3075 *
3076 * @param uNewEip The new EIP.
3077 * @param uNewCs The new CS.
3078 * @param uNewFlags The new EFLAGS.
3079 * @param uNewRsp The RSP after the initial IRET frame.
3080 *
3081 * @note This can only be a 32-bit iret du to the X86_EFL_VM position.
3082 */
3083IEM_CIMPL_DEF_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp)
3084{
3085 RT_NOREF_PV(cbInstr);
3086 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK);
3087
3088 /*
3089 * Pop the V8086 specific frame bits off the stack.
3090 */
3091 VBOXSTRICTRC rcStrict;
3092 RTCPTRUNION uFrame;
3093 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 0 /*off*/, 24 /*cbMem*/, &uFrame.pv, uNewRsp);
3094 if (rcStrict != VINF_SUCCESS)
3095 return rcStrict;
3096 uint32_t uNewEsp = uFrame.pu32[0];
3097 uint16_t uNewSs = uFrame.pu32[1];
3098 uint16_t uNewEs = uFrame.pu32[2];
3099 uint16_t uNewDs = uFrame.pu32[3];
3100 uint16_t uNewFs = uFrame.pu32[4];
3101 uint16_t uNewGs = uFrame.pu32[5];
3102 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R); /* don't use iemMemStackPopCommitSpecial here. */
3103 if (rcStrict != VINF_SUCCESS)
3104 return rcStrict;
3105
3106 /*
3107 * Commit the operation.
3108 */
3109 uNewFlags &= X86_EFL_LIVE_MASK;
3110 uNewFlags |= X86_EFL_RA1_MASK;
3111#ifdef DBGFTRACE_ENABLED
3112 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/p/v %04x:%08x -> %04x:%04x %x %04x:%04x",
3113 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp);
3114#endif
3115 Log7(("iemCImpl_iret_prot_v8086: %04x:%08x -> %04x:%04x %x %04x:%04x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp));
3116
3117 IEMMISC_SET_EFL(pVCpu, uNewFlags);
3118 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.cs, uNewCs);
3119 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.ss, uNewSs);
3120 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.es, uNewEs);
3121 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.ds, uNewDs);
3122 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.fs, uNewFs);
3123 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.gs, uNewGs);
3124 pVCpu->cpum.GstCtx.rip = (uint16_t)uNewEip;
3125 pVCpu->cpum.GstCtx.rsp = uNewEsp; /** @todo check this out! */
3126 pVCpu->iem.s.uCpl = 3;
3127
3128 /* Flush the prefetch buffer. */
3129#ifdef IEM_WITH_CODE_TLB
3130 pVCpu->iem.s.pbInstrBuf = NULL;
3131#else
3132 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3133#endif
3134
3135 return VINF_SUCCESS;
3136}
3137
3138
3139/**
3140 * Implements iret for protected mode returning via a nested task.
3141 *
3142 * @param enmEffOpSize The effective operand size.
3143 */
3144IEM_CIMPL_DEF_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize)
3145{
3146 Log7(("iemCImpl_iret_prot_NestedTask:\n"));
3147#ifndef IEM_IMPLEMENTS_TASKSWITCH
3148 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
3149#else
3150 RT_NOREF_PV(enmEffOpSize);
3151
3152 /*
3153 * Read the segment selector in the link-field of the current TSS.
3154 */
3155 RTSEL uSelRet;
3156 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &uSelRet, UINT8_MAX, pVCpu->cpum.GstCtx.tr.u64Base);
3157 if (rcStrict != VINF_SUCCESS)
3158 return rcStrict;
3159
3160 /*
3161 * Fetch the returning task's TSS descriptor from the GDT.
3162 */
3163 if (uSelRet & X86_SEL_LDT)
3164 {
3165 Log(("iret_prot_NestedTask TSS not in LDT. uSelRet=%04x -> #TS\n", uSelRet));
3166 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet);
3167 }
3168
3169 IEMSELDESC TssDesc;
3170 rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelRet, X86_XCPT_GP);
3171 if (rcStrict != VINF_SUCCESS)
3172 return rcStrict;
3173
3174 if (TssDesc.Legacy.Gate.u1DescType)
3175 {
3176 Log(("iret_prot_NestedTask Invalid TSS type. uSelRet=%04x -> #TS\n", uSelRet));
3177 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3178 }
3179
3180 if ( TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_286_TSS_BUSY
3181 && TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
3182 {
3183 Log(("iret_prot_NestedTask TSS is not busy. uSelRet=%04x DescType=%#x -> #TS\n", uSelRet, TssDesc.Legacy.Gate.u4Type));
3184 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3185 }
3186
3187 if (!TssDesc.Legacy.Gate.u1Present)
3188 {
3189 Log(("iret_prot_NestedTask TSS is not present. uSelRet=%04x -> #NP\n", uSelRet));
3190 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3191 }
3192
3193 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
3194 return iemTaskSwitch(pVCpu, IEMTASKSWITCH_IRET, uNextEip, 0 /* fFlags */, 0 /* uErr */,
3195 0 /* uCr2 */, uSelRet, &TssDesc);
3196#endif
3197}
3198
3199
3200/**
3201 * Implements iret for protected mode
3202 *
3203 * @param enmEffOpSize The effective operand size.
3204 */
3205IEM_CIMPL_DEF_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize)
3206{
3207 NOREF(cbInstr);
3208 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3209
3210 /*
3211 * Nested task return.
3212 */
3213 if (pVCpu->cpum.GstCtx.eflags.Bits.u1NT)
3214 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot_NestedTask, enmEffOpSize);
3215
3216 /*
3217 * Normal return.
3218 *
3219 * Do the stack bits, but don't commit RSP before everything checks
3220 * out right.
3221 */
3222 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3223 VBOXSTRICTRC rcStrict;
3224 RTCPTRUNION uFrame;
3225 uint16_t uNewCs;
3226 uint32_t uNewEip;
3227 uint32_t uNewFlags;
3228 uint64_t uNewRsp;
3229 if (enmEffOpSize == IEMMODE_32BIT)
3230 {
3231 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, 3, &uFrame.pv, &uNewRsp);
3232 if (rcStrict != VINF_SUCCESS)
3233 return rcStrict;
3234 uNewEip = uFrame.pu32[0];
3235 uNewCs = (uint16_t)uFrame.pu32[1];
3236 uNewFlags = uFrame.pu32[2];
3237 }
3238 else
3239 {
3240 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, 1, &uFrame.pv, &uNewRsp);
3241 if (rcStrict != VINF_SUCCESS)
3242 return rcStrict;
3243 uNewEip = uFrame.pu16[0];
3244 uNewCs = uFrame.pu16[1];
3245 uNewFlags = uFrame.pu16[2];
3246 }
3247 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3248 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3249 { /* extremely likely */ }
3250 else
3251 return rcStrict;
3252 Log7(("iemCImpl_iret_prot: uNewCs=%#06x uNewEip=%#010x uNewFlags=%#x uNewRsp=%#18llx uCpl=%u\n", uNewCs, uNewEip, uNewFlags, uNewRsp, pVCpu->iem.s.uCpl));
3253
3254 /*
3255 * We're hopefully not returning to V8086 mode...
3256 */
3257 if ( (uNewFlags & X86_EFL_VM)
3258 && pVCpu->iem.s.uCpl == 0)
3259 {
3260 Assert(enmEffOpSize == IEMMODE_32BIT);
3261 return IEM_CIMPL_CALL_4(iemCImpl_iret_prot_v8086, uNewEip, uNewCs, uNewFlags, uNewRsp);
3262 }
3263
3264 /*
3265 * Protected mode.
3266 */
3267 /* Read the CS descriptor. */
3268 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3269 {
3270 Log(("iret %04x:%08x -> invalid CS selector, #GP(0)\n", uNewCs, uNewEip));
3271 return iemRaiseGeneralProtectionFault0(pVCpu);
3272 }
3273
3274 IEMSELDESC DescCS;
3275 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3276 if (rcStrict != VINF_SUCCESS)
3277 {
3278 Log(("iret %04x:%08x - rcStrict=%Rrc when fetching CS\n", uNewCs, uNewEip, VBOXSTRICTRC_VAL(rcStrict)));
3279 return rcStrict;
3280 }
3281
3282 /* Must be a code descriptor. */
3283 if (!DescCS.Legacy.Gen.u1DescType)
3284 {
3285 Log(("iret %04x:%08x - CS is system segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3286 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3287 }
3288 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3289 {
3290 Log(("iret %04x:%08x - not code segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3291 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3292 }
3293
3294 /* Privilege checks. */
3295 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3296 {
3297 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3298 {
3299 Log(("iret %04x:%08x - RPL != DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3300 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3301 }
3302 }
3303 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3304 {
3305 Log(("iret %04x:%08x - RPL < DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3306 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3307 }
3308 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3309 {
3310 Log(("iret %04x:%08x - RPL < CPL (%d) -> #GP\n", uNewCs, uNewEip, pVCpu->iem.s.uCpl));
3311 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3312 }
3313
3314 /* Present? */
3315 if (!DescCS.Legacy.Gen.u1Present)
3316 {
3317 Log(("iret %04x:%08x - CS not present -> #NP\n", uNewCs, uNewEip));
3318 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3319 }
3320
3321 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3322
3323 /*
3324 * Return to outer level?
3325 */
3326 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
3327 {
3328 uint16_t uNewSS;
3329 uint32_t uNewESP;
3330 if (enmEffOpSize == IEMMODE_32BIT)
3331 {
3332 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 0/*off*/, 8 /*cbMem*/, &uFrame.pv, uNewRsp);
3333 if (rcStrict != VINF_SUCCESS)
3334 return rcStrict;
3335/** @todo We might be popping a 32-bit ESP from the IRET frame, but whether
3336 * 16-bit or 32-bit are being loaded into SP depends on the D/B
3337 * bit of the popped SS selector it turns out. */
3338 uNewESP = uFrame.pu32[0];
3339 uNewSS = (uint16_t)uFrame.pu32[1];
3340 }
3341 else
3342 {
3343 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 0 /*off*/, 4 /*cbMem*/, &uFrame.pv, uNewRsp);
3344 if (rcStrict != VINF_SUCCESS)
3345 return rcStrict;
3346 uNewESP = uFrame.pu16[0];
3347 uNewSS = uFrame.pu16[1];
3348 }
3349 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R);
3350 if (rcStrict != VINF_SUCCESS)
3351 return rcStrict;
3352 Log7(("iemCImpl_iret_prot: uNewSS=%#06x uNewESP=%#010x\n", uNewSS, uNewESP));
3353
3354 /* Read the SS descriptor. */
3355 if (!(uNewSS & X86_SEL_MASK_OFF_RPL))
3356 {
3357 Log(("iret %04x:%08x/%04x:%08x -> invalid SS selector, #GP(0)\n", uNewCs, uNewEip, uNewSS, uNewESP));
3358 return iemRaiseGeneralProtectionFault0(pVCpu);
3359 }
3360
3361 IEMSELDESC DescSS;
3362 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_GP); /** @todo Correct exception? */
3363 if (rcStrict != VINF_SUCCESS)
3364 {
3365 Log(("iret %04x:%08x/%04x:%08x - %Rrc when fetching SS\n",
3366 uNewCs, uNewEip, uNewSS, uNewESP, VBOXSTRICTRC_VAL(rcStrict)));
3367 return rcStrict;
3368 }
3369
3370 /* Privilege checks. */
3371 if ((uNewSS & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3372 {
3373 Log(("iret %04x:%08x/%04x:%08x -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewEip, uNewSS, uNewESP));
3374 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3375 }
3376 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3377 {
3378 Log(("iret %04x:%08x/%04x:%08x -> SS.DPL (%d) != CS.RPL -> #GP\n",
3379 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u2Dpl));
3380 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3381 }
3382
3383 /* Must be a writeable data segment descriptor. */
3384 if (!DescSS.Legacy.Gen.u1DescType)
3385 {
3386 Log(("iret %04x:%08x/%04x:%08x -> SS is system segment (%#x) -> #GP\n",
3387 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3388 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3389 }
3390 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3391 {
3392 Log(("iret %04x:%08x/%04x:%08x - not writable data segment (%#x) -> #GP\n",
3393 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3394 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3395 }
3396
3397 /* Present? */
3398 if (!DescSS.Legacy.Gen.u1Present)
3399 {
3400 Log(("iret %04x:%08x/%04x:%08x -> SS not present -> #SS\n", uNewCs, uNewEip, uNewSS, uNewESP));
3401 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
3402 }
3403
3404 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3405
3406 /* Check EIP. */
3407 if (uNewEip > cbLimitCS)
3408 {
3409 Log(("iret %04x:%08x/%04x:%08x -> EIP is out of bounds (%#x) -> #GP(0)\n",
3410 uNewCs, uNewEip, uNewSS, uNewESP, cbLimitCS));
3411 /** @todo Which is it, \#GP(0) or \#GP(sel)? */
3412 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3413 }
3414
3415 /*
3416 * Commit the changes, marking CS and SS accessed first since
3417 * that may fail.
3418 */
3419 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3420 {
3421 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3422 if (rcStrict != VINF_SUCCESS)
3423 return rcStrict;
3424 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3425 }
3426 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3427 {
3428 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
3429 if (rcStrict != VINF_SUCCESS)
3430 return rcStrict;
3431 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3432 }
3433
3434 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3435 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3436 if (enmEffOpSize != IEMMODE_16BIT)
3437 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3438 if (pVCpu->iem.s.uCpl == 0)
3439 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3440 else if (pVCpu->iem.s.uCpl <= pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL)
3441 fEFlagsMask |= X86_EFL_IF;
3442 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3443 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3444 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu);
3445 fEFlagsNew &= ~fEFlagsMask;
3446 fEFlagsNew |= uNewFlags & fEFlagsMask;
3447#ifdef DBGFTRACE_ENABLED
3448 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up%u %04x:%08x -> %04x:%04x %x %04x:%04x",
3449 pVCpu->iem.s.uCpl, uNewCs & X86_SEL_RPL, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip,
3450 uNewCs, uNewEip, uNewFlags, uNewSS, uNewESP);
3451#endif
3452
3453 IEMMISC_SET_EFL(pVCpu, fEFlagsNew);
3454 pVCpu->cpum.GstCtx.rip = uNewEip;
3455 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3456 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3457 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3458 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3459 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3460 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3461 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3462
3463 pVCpu->cpum.GstCtx.ss.Sel = uNewSS;
3464 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSS;
3465 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3466 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3467 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
3468 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3469 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
3470 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewESP;
3471 else
3472 pVCpu->cpum.GstCtx.rsp = uNewESP;
3473
3474 pVCpu->iem.s.uCpl = uNewCs & X86_SEL_RPL;
3475 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.ds);
3476 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.es);
3477 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.fs);
3478 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.gs);
3479
3480 /* Done! */
3481
3482 }
3483 /*
3484 * Return to the same level.
3485 */
3486 else
3487 {
3488 /* Check EIP. */
3489 if (uNewEip > cbLimitCS)
3490 {
3491 Log(("iret %04x:%08x - EIP is out of bounds (%#x) -> #GP(0)\n", uNewCs, uNewEip, cbLimitCS));
3492 /** @todo Which is it, \#GP(0) or \#GP(sel)? */
3493 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3494 }
3495
3496 /*
3497 * Commit the changes, marking CS first since it may fail.
3498 */
3499 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3500 {
3501 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3502 if (rcStrict != VINF_SUCCESS)
3503 return rcStrict;
3504 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3505 }
3506
3507 X86EFLAGS NewEfl;
3508 NewEfl.u = IEMMISC_GET_EFL(pVCpu);
3509 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3510 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3511 if (enmEffOpSize != IEMMODE_16BIT)
3512 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3513 if (pVCpu->iem.s.uCpl == 0)
3514 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3515 else if (pVCpu->iem.s.uCpl <= NewEfl.Bits.u2IOPL)
3516 fEFlagsMask |= X86_EFL_IF;
3517 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3518 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3519 NewEfl.u &= ~fEFlagsMask;
3520 NewEfl.u |= fEFlagsMask & uNewFlags;
3521#ifdef DBGFTRACE_ENABLED
3522 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up %04x:%08x -> %04x:%04x %x %04x:%04llx",
3523 pVCpu->iem.s.uCpl, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip,
3524 uNewCs, uNewEip, uNewFlags, pVCpu->cpum.GstCtx.ss.Sel, uNewRsp);
3525#endif
3526
3527 IEMMISC_SET_EFL(pVCpu, NewEfl.u);
3528 pVCpu->cpum.GstCtx.rip = uNewEip;
3529 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3530 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3531 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3532 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3533 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3534 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3535 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3536 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
3537 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
3538 else
3539 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3540 /* Done! */
3541 }
3542
3543 /* Flush the prefetch buffer. */
3544#ifdef IEM_WITH_CODE_TLB
3545 pVCpu->iem.s.pbInstrBuf = NULL;
3546#else
3547 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3548#endif
3549
3550 return VINF_SUCCESS;
3551}
3552
3553
3554/**
3555 * Implements iret for long mode
3556 *
3557 * @param enmEffOpSize The effective operand size.
3558 */
3559IEM_CIMPL_DEF_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize)
3560{
3561 NOREF(cbInstr);
3562
3563 /*
3564 * Nested task return is not supported in long mode.
3565 */
3566 if (pVCpu->cpum.GstCtx.eflags.Bits.u1NT)
3567 {
3568 Log(("iretq with NT=1 (eflags=%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.eflags.u));
3569 return iemRaiseGeneralProtectionFault0(pVCpu);
3570 }
3571
3572 /*
3573 * Normal return.
3574 *
3575 * Do the stack bits, but don't commit RSP before everything checks
3576 * out right.
3577 */
3578 VBOXSTRICTRC rcStrict;
3579 RTCPTRUNION uFrame;
3580 uint64_t uNewRip;
3581 uint16_t uNewCs;
3582 uint16_t uNewSs;
3583 uint32_t uNewFlags;
3584 uint64_t uNewRsp;
3585 if (enmEffOpSize == IEMMODE_64BIT)
3586 {
3587 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*8, 7, &uFrame.pv, &uNewRsp);
3588 if (rcStrict != VINF_SUCCESS)
3589 return rcStrict;
3590 uNewRip = uFrame.pu64[0];
3591 uNewCs = (uint16_t)uFrame.pu64[1];
3592 uNewFlags = (uint32_t)uFrame.pu64[2];
3593 uNewRsp = uFrame.pu64[3];
3594 uNewSs = (uint16_t)uFrame.pu64[4];
3595 }
3596 else if (enmEffOpSize == IEMMODE_32BIT)
3597 {
3598 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*4, 3, &uFrame.pv, &uNewRsp);
3599 if (rcStrict != VINF_SUCCESS)
3600 return rcStrict;
3601 uNewRip = uFrame.pu32[0];
3602 uNewCs = (uint16_t)uFrame.pu32[1];
3603 uNewFlags = uFrame.pu32[2];
3604 uNewRsp = uFrame.pu32[3];
3605 uNewSs = (uint16_t)uFrame.pu32[4];
3606 }
3607 else
3608 {
3609 Assert(enmEffOpSize == IEMMODE_16BIT);
3610 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*2, 1, &uFrame.pv, &uNewRsp);
3611 if (rcStrict != VINF_SUCCESS)
3612 return rcStrict;
3613 uNewRip = uFrame.pu16[0];
3614 uNewCs = uFrame.pu16[1];
3615 uNewFlags = uFrame.pu16[2];
3616 uNewRsp = uFrame.pu16[3];
3617 uNewSs = uFrame.pu16[4];
3618 }
3619 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3620 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3621 { /* extremely like */ }
3622 else
3623 return rcStrict;
3624 Log7(("iretq stack: cs:rip=%04x:%016RX64 rflags=%016RX64 ss:rsp=%04x:%016RX64\n", uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp));
3625
3626 /*
3627 * Check stuff.
3628 */
3629 /* Read the CS descriptor. */
3630 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3631 {
3632 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid CS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3633 return iemRaiseGeneralProtectionFault0(pVCpu);
3634 }
3635
3636 IEMSELDESC DescCS;
3637 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3638 if (rcStrict != VINF_SUCCESS)
3639 {
3640 Log(("iret %04x:%016RX64/%04x:%016RX64 - rcStrict=%Rrc when fetching CS\n",
3641 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3642 return rcStrict;
3643 }
3644
3645 /* Must be a code descriptor. */
3646 if ( !DescCS.Legacy.Gen.u1DescType
3647 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3648 {
3649 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS is not a code segment T=%u T=%#xu -> #GP\n",
3650 uNewCs, uNewRip, uNewSs, uNewRsp, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
3651 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3652 }
3653
3654 /* Privilege checks. */
3655 uint8_t const uNewCpl = uNewCs & X86_SEL_RPL;
3656 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3657 {
3658 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3659 {
3660 Log(("iret %04x:%016RX64 - RPL != DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3661 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3662 }
3663 }
3664 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3665 {
3666 Log(("iret %04x:%016RX64 - RPL < DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3667 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3668 }
3669 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3670 {
3671 Log(("iret %04x:%016RX64 - RPL < CPL (%d) -> #GP\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
3672 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3673 }
3674
3675 /* Present? */
3676 if (!DescCS.Legacy.Gen.u1Present)
3677 {
3678 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS not present -> #NP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3679 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3680 }
3681
3682 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3683
3684 /* Read the SS descriptor. */
3685 IEMSELDESC DescSS;
3686 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3687 {
3688 if ( !DescCS.Legacy.Gen.u1Long
3689 || DescCS.Legacy.Gen.u1DefBig /** @todo exactly how does iret (and others) behave with u1Long=1 and u1DefBig=1? \#GP(sel)? */
3690 || uNewCpl > 2) /** @todo verify SS=0 impossible for ring-3. */
3691 {
3692 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid SS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3693 return iemRaiseGeneralProtectionFault0(pVCpu);
3694 }
3695 DescSS.Legacy.u = 0;
3696 }
3697 else
3698 {
3699 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSs, X86_XCPT_GP); /** @todo Correct exception? */
3700 if (rcStrict != VINF_SUCCESS)
3701 {
3702 Log(("iret %04x:%016RX64/%04x:%016RX64 - %Rrc when fetching SS\n",
3703 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3704 return rcStrict;
3705 }
3706 }
3707
3708 /* Privilege checks. */
3709 if ((uNewSs & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3710 {
3711 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3712 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3713 }
3714
3715 uint32_t cbLimitSs;
3716 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3717 cbLimitSs = UINT32_MAX;
3718 else
3719 {
3720 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3721 {
3722 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.DPL (%d) != CS.RPL -> #GP\n",
3723 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u2Dpl));
3724 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3725 }
3726
3727 /* Must be a writeable data segment descriptor. */
3728 if (!DescSS.Legacy.Gen.u1DescType)
3729 {
3730 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS is system segment (%#x) -> #GP\n",
3731 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3732 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3733 }
3734 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3735 {
3736 Log(("iret %04x:%016RX64/%04x:%016RX64 - not writable data segment (%#x) -> #GP\n",
3737 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3738 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3739 }
3740
3741 /* Present? */
3742 if (!DescSS.Legacy.Gen.u1Present)
3743 {
3744 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS not present -> #SS\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3745 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSs);
3746 }
3747 cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3748 }
3749
3750 /* Check EIP. */
3751 if (DescCS.Legacy.Gen.u1Long)
3752 {
3753 if (!IEM_IS_CANONICAL(uNewRip))
3754 {
3755 Log(("iret %04x:%016RX64/%04x:%016RX64 -> RIP is not canonical -> #GP(0)\n",
3756 uNewCs, uNewRip, uNewSs, uNewRsp));
3757 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3758 }
3759 }
3760 else
3761 {
3762 if (uNewRip > cbLimitCS)
3763 {
3764 Log(("iret %04x:%016RX64/%04x:%016RX64 -> EIP is out of bounds (%#x) -> #GP(0)\n",
3765 uNewCs, uNewRip, uNewSs, uNewRsp, cbLimitCS));
3766 /** @todo Which is it, \#GP(0) or \#GP(sel)? */
3767 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3768 }
3769 }
3770
3771 /*
3772 * Commit the changes, marking CS and SS accessed first since
3773 * that may fail.
3774 */
3775 /** @todo where exactly are these actually marked accessed by a real CPU? */
3776 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3777 {
3778 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3779 if (rcStrict != VINF_SUCCESS)
3780 return rcStrict;
3781 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3782 }
3783 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3784 {
3785 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSs);
3786 if (rcStrict != VINF_SUCCESS)
3787 return rcStrict;
3788 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3789 }
3790
3791 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3792 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3793 if (enmEffOpSize != IEMMODE_16BIT)
3794 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3795 if (pVCpu->iem.s.uCpl == 0)
3796 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is ignored */
3797 else if (pVCpu->iem.s.uCpl <= pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL)
3798 fEFlagsMask |= X86_EFL_IF;
3799 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu);
3800 fEFlagsNew &= ~fEFlagsMask;
3801 fEFlagsNew |= uNewFlags & fEFlagsMask;
3802#ifdef DBGFTRACE_ENABLED
3803 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%ul%u %08llx -> %04x:%04llx %llx %04x:%04llx",
3804 pVCpu->iem.s.uCpl, uNewCpl, pVCpu->cpum.GstCtx.rip, uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp);
3805#endif
3806
3807 IEMMISC_SET_EFL(pVCpu, fEFlagsNew);
3808 pVCpu->cpum.GstCtx.rip = uNewRip;
3809 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3810 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3811 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3812 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3813 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3814 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3815 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3816 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1Long || pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig)
3817 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3818 else
3819 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
3820 pVCpu->cpum.GstCtx.ss.Sel = uNewSs;
3821 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs;
3822 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3823 {
3824 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3825 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_UNUSABLE | (uNewCpl << X86DESCATTR_DPL_SHIFT);
3826 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
3827 pVCpu->cpum.GstCtx.ss.u64Base = 0;
3828 Log2(("iretq new SS: NULL\n"));
3829 }
3830 else
3831 {
3832 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3833 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3834 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
3835 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3836 Log2(("iretq new SS: base=%#RX64 lim=%#x attr=%#x\n", pVCpu->cpum.GstCtx.ss.u64Base, pVCpu->cpum.GstCtx.ss.u32Limit, pVCpu->cpum.GstCtx.ss.Attr.u));
3837 }
3838
3839 if (pVCpu->iem.s.uCpl != uNewCpl)
3840 {
3841 pVCpu->iem.s.uCpl = uNewCpl;
3842 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.ds);
3843 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.es);
3844 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.fs);
3845 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.gs);
3846 }
3847
3848 /* Flush the prefetch buffer. */
3849#ifdef IEM_WITH_CODE_TLB
3850 pVCpu->iem.s.pbInstrBuf = NULL;
3851#else
3852 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3853#endif
3854
3855 return VINF_SUCCESS;
3856}
3857
3858
3859/**
3860 * Implements iret.
3861 *
3862 * @param enmEffOpSize The effective operand size.
3863 */
3864IEM_CIMPL_DEF_1(iemCImpl_iret, IEMMODE, enmEffOpSize)
3865{
3866 bool fBlockingNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3867
3868#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3869 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
3870 {
3871 /*
3872 * Record whether NMI (or virtual-NMI) blocking is in effect during the execution
3873 * of this IRET instruction. We need to provide this information as part of some
3874 * VM-exits.
3875 *
3876 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3877 */
3878 if (IEM_VMX_IS_PINCTLS_SET(pVCpu, VMX_PIN_CTLS_VIRT_NMI))
3879 pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret = pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking;
3880 else
3881 pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret = fBlockingNmi;
3882
3883 /*
3884 * If "NMI exiting" is set, IRET does not affect blocking of NMIs.
3885 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3886 */
3887 if (IEM_VMX_IS_PINCTLS_SET(pVCpu, VMX_PIN_CTLS_NMI_EXIT))
3888 fBlockingNmi = false;
3889
3890 /* Clear virtual-NMI blocking, if any, before causing any further exceptions. */
3891 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
3892 }
3893#endif
3894
3895 /*
3896 * The SVM nested-guest intercept for IRET takes priority over all exceptions,
3897 * The NMI is still held pending (which I assume means blocking of further NMIs
3898 * is in effect).
3899 *
3900 * See AMD spec. 15.9 "Instruction Intercepts".
3901 * See AMD spec. 15.21.9 "NMI Support".
3902 */
3903 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IRET))
3904 {
3905 Log(("iret: Guest intercept -> #VMEXIT\n"));
3906 IEM_SVM_UPDATE_NRIP(pVCpu);
3907 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IRET, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
3908 }
3909
3910 /*
3911 * Clear NMI blocking, if any, before causing any further exceptions.
3912 * See Intel spec. 6.7.1 "Handling Multiple NMIs".
3913 */
3914 if (fBlockingNmi)
3915 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
3916
3917 /*
3918 * Call a mode specific worker.
3919 */
3920 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
3921 return IEM_CIMPL_CALL_1(iemCImpl_iret_real_v8086, enmEffOpSize);
3922 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_LDTR);
3923 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
3924 return IEM_CIMPL_CALL_1(iemCImpl_iret_64bit, enmEffOpSize);
3925 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot, enmEffOpSize);
3926}
3927
3928
3929static void iemLoadallSetSelector(PVMCPUCC pVCpu, uint8_t iSegReg, uint16_t uSel)
3930{
3931 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
3932
3933 pHid->Sel = uSel;
3934 pHid->ValidSel = uSel;
3935 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
3936}
3937
3938
3939static void iemLoadall286SetDescCache(PVMCPUCC pVCpu, uint8_t iSegReg, uint8_t const *pbMem)
3940{
3941 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
3942
3943 /* The base is in the first three bytes. */
3944 pHid->u64Base = pbMem[0] + (pbMem[1] << 8) + (pbMem[2] << 16);
3945 /* The attributes are in the fourth byte. */
3946 pHid->Attr.u = pbMem[3];
3947 /* The limit is in the last two bytes. */
3948 pHid->u32Limit = pbMem[4] + (pbMem[5] << 8);
3949}
3950
3951
3952/**
3953 * Implements 286 LOADALL (286 CPUs only).
3954 */
3955IEM_CIMPL_DEF_0(iemCImpl_loadall286)
3956{
3957 NOREF(cbInstr);
3958
3959 /* Data is loaded from a buffer at 800h. No checks are done on the
3960 * validity of loaded state.
3961 *
3962 * LOADALL only loads the internal CPU state, it does not access any
3963 * GDT, LDT, or similar tables.
3964 */
3965
3966 if (pVCpu->iem.s.uCpl != 0)
3967 {
3968 Log(("loadall286: CPL must be 0 not %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
3969 return iemRaiseGeneralProtectionFault0(pVCpu);
3970 }
3971
3972 uint8_t const *pbMem = NULL;
3973 uint16_t const *pa16Mem;
3974 uint8_t const *pa8Mem;
3975 RTGCPHYS GCPtrStart = 0x800; /* Fixed table location. */
3976 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&pbMem, 0x66, UINT8_MAX, GCPtrStart, IEM_ACCESS_SYS_R, 0);
3977 if (rcStrict != VINF_SUCCESS)
3978 return rcStrict;
3979
3980 /* The MSW is at offset 0x06. */
3981 pa16Mem = (uint16_t const *)(pbMem + 0x06);
3982 /* Even LOADALL can't clear the MSW.PE bit, though it can set it. */
3983 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3984 uNewCr0 |= *pa16Mem & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3985 uint64_t const uOldCr0 = pVCpu->cpum.GstCtx.cr0;
3986
3987 CPUMSetGuestCR0(pVCpu, uNewCr0);
3988 Assert(pVCpu->cpum.GstCtx.cr0 == uNewCr0);
3989
3990 /* Inform PGM if mode changed. */
3991 if ((uNewCr0 & X86_CR0_PE) != (uOldCr0 & X86_CR0_PE))
3992 {
3993 int rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
3994 AssertRCReturn(rc, rc);
3995 /* ignore informational status codes */
3996 }
3997 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
3998 false /* fForce */);
3999
4000 /* TR selector is at offset 0x16. */
4001 pa16Mem = (uint16_t const *)(pbMem + 0x16);
4002 pVCpu->cpum.GstCtx.tr.Sel = pa16Mem[0];
4003 pVCpu->cpum.GstCtx.tr.ValidSel = pa16Mem[0];
4004 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
4005
4006 /* Followed by FLAGS... */
4007 pVCpu->cpum.GstCtx.eflags.u = pa16Mem[1] | X86_EFL_1;
4008 pVCpu->cpum.GstCtx.ip = pa16Mem[2]; /* ...and IP. */
4009
4010 /* LDT is at offset 0x1C. */
4011 pa16Mem = (uint16_t const *)(pbMem + 0x1C);
4012 pVCpu->cpum.GstCtx.ldtr.Sel = pa16Mem[0];
4013 pVCpu->cpum.GstCtx.ldtr.ValidSel = pa16Mem[0];
4014 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4015
4016 /* Segment registers are at offset 0x1E. */
4017 pa16Mem = (uint16_t const *)(pbMem + 0x1E);
4018 iemLoadallSetSelector(pVCpu, X86_SREG_DS, pa16Mem[0]);
4019 iemLoadallSetSelector(pVCpu, X86_SREG_SS, pa16Mem[1]);
4020 iemLoadallSetSelector(pVCpu, X86_SREG_CS, pa16Mem[2]);
4021 iemLoadallSetSelector(pVCpu, X86_SREG_ES, pa16Mem[3]);
4022
4023 /* GPRs are at offset 0x26. */
4024 pa16Mem = (uint16_t const *)(pbMem + 0x26);
4025 pVCpu->cpum.GstCtx.di = pa16Mem[0];
4026 pVCpu->cpum.GstCtx.si = pa16Mem[1];
4027 pVCpu->cpum.GstCtx.bp = pa16Mem[2];
4028 pVCpu->cpum.GstCtx.sp = pa16Mem[3];
4029 pVCpu->cpum.GstCtx.bx = pa16Mem[4];
4030 pVCpu->cpum.GstCtx.dx = pa16Mem[5];
4031 pVCpu->cpum.GstCtx.cx = pa16Mem[6];
4032 pVCpu->cpum.GstCtx.ax = pa16Mem[7];
4033
4034 /* Descriptor caches are at offset 0x36, 6 bytes per entry. */
4035 iemLoadall286SetDescCache(pVCpu, X86_SREG_ES, pbMem + 0x36);
4036 iemLoadall286SetDescCache(pVCpu, X86_SREG_CS, pbMem + 0x3C);
4037 iemLoadall286SetDescCache(pVCpu, X86_SREG_SS, pbMem + 0x42);
4038 iemLoadall286SetDescCache(pVCpu, X86_SREG_DS, pbMem + 0x48);
4039
4040 /* GDTR contents are at offset 0x4E, 6 bytes. */
4041 RTGCPHYS GCPtrBase;
4042 uint16_t cbLimit;
4043 pa8Mem = pbMem + 0x4E;
4044 /* NB: Fourth byte "should be zero"; we are ignoring it. */
4045 GCPtrBase = pa8Mem[0] + (pa8Mem[1] << 8) + (pa8Mem[2] << 16);
4046 cbLimit = pa8Mem[4] + (pa8Mem[5] << 8);
4047 CPUMSetGuestGDTR(pVCpu, GCPtrBase, cbLimit);
4048
4049 /* IDTR contents are at offset 0x5A, 6 bytes. */
4050 pa8Mem = pbMem + 0x5A;
4051 GCPtrBase = pa8Mem[0] + (pa8Mem[1] << 8) + (pa8Mem[2] << 16);
4052 cbLimit = pa8Mem[4] + (pa8Mem[5] << 8);
4053 CPUMSetGuestIDTR(pVCpu, GCPtrBase, cbLimit);
4054
4055 Log(("LOADALL: GDTR:%08RX64/%04X, IDTR:%08RX64/%04X\n", pVCpu->cpum.GstCtx.gdtr.pGdt, pVCpu->cpum.GstCtx.gdtr.cbGdt, pVCpu->cpum.GstCtx.idtr.pIdt, pVCpu->cpum.GstCtx.idtr.cbIdt));
4056 Log(("LOADALL: CS:%04X, CS base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.cs.u64Base, pVCpu->cpum.GstCtx.cs.u32Limit, pVCpu->cpum.GstCtx.cs.Attr.u));
4057 Log(("LOADALL: DS:%04X, DS base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.ds.Sel, pVCpu->cpum.GstCtx.ds.u64Base, pVCpu->cpum.GstCtx.ds.u32Limit, pVCpu->cpum.GstCtx.ds.Attr.u));
4058 Log(("LOADALL: ES:%04X, ES base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.es.Sel, pVCpu->cpum.GstCtx.es.u64Base, pVCpu->cpum.GstCtx.es.u32Limit, pVCpu->cpum.GstCtx.es.Attr.u));
4059 Log(("LOADALL: SS:%04X, SS base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.ss.u64Base, pVCpu->cpum.GstCtx.ss.u32Limit, pVCpu->cpum.GstCtx.ss.Attr.u));
4060 Log(("LOADALL: SI:%04X, DI:%04X, AX:%04X, BX:%04X, CX:%04X, DX:%04X\n", pVCpu->cpum.GstCtx.si, pVCpu->cpum.GstCtx.di, pVCpu->cpum.GstCtx.bx, pVCpu->cpum.GstCtx.bx, pVCpu->cpum.GstCtx.cx, pVCpu->cpum.GstCtx.dx));
4061
4062 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pbMem, IEM_ACCESS_SYS_R);
4063 if (rcStrict != VINF_SUCCESS)
4064 return rcStrict;
4065
4066 /* The CPL may change. It is taken from the "DPL fields of the SS and CS
4067 * descriptor caches" but there is no word as to what happens if those are
4068 * not identical (probably bad things).
4069 */
4070 pVCpu->iem.s.uCpl = pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl;
4071
4072 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS | CPUM_CHANGED_IDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_TR | CPUM_CHANGED_LDTR);
4073
4074 /* Flush the prefetch buffer. */
4075#ifdef IEM_WITH_CODE_TLB
4076 pVCpu->iem.s.pbInstrBuf = NULL;
4077#else
4078 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4079#endif
4080 return rcStrict;
4081}
4082
4083
4084/**
4085 * Implements SYSCALL (AMD and Intel64).
4086 */
4087IEM_CIMPL_DEF_0(iemCImpl_syscall)
4088{
4089 /** @todo hack, LOADALL should be decoded as such on a 286. */
4090 if (RT_UNLIKELY(pVCpu->iem.s.uTargetCpu == IEMTARGETCPU_286))
4091 return iemCImpl_loadall286(pVCpu, cbInstr);
4092
4093 /*
4094 * Check preconditions.
4095 *
4096 * Note that CPUs described in the documentation may load a few odd values
4097 * into CS and SS than we allow here. This has yet to be checked on real
4098 * hardware.
4099 */
4100 if (!(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SCE))
4101 {
4102 Log(("syscall: Not enabled in EFER -> #UD\n"));
4103 return iemRaiseUndefinedOpcode(pVCpu);
4104 }
4105 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4106 {
4107 Log(("syscall: Protected mode is required -> #GP(0)\n"));
4108 return iemRaiseGeneralProtectionFault0(pVCpu);
4109 }
4110 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4111 {
4112 Log(("syscall: Only available in long mode on intel -> #UD\n"));
4113 return iemRaiseUndefinedOpcode(pVCpu);
4114 }
4115
4116 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS);
4117
4118 /** @todo verify RPL ignoring and CS=0xfff8 (i.e. SS == 0). */
4119 /** @todo what about LDT selectors? Shouldn't matter, really. */
4120 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSCALL_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
4121 uint16_t uNewSs = uNewCs + 8;
4122 if (uNewCs == 0 || uNewSs == 0)
4123 {
4124 Log(("syscall: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
4125 return iemRaiseGeneralProtectionFault0(pVCpu);
4126 }
4127
4128 /* Long mode and legacy mode differs. */
4129 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4130 {
4131 uint64_t uNewRip = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.msrLSTAR : pVCpu->cpum.GstCtx. msrCSTAR;
4132
4133 /* This test isn't in the docs, but I'm not trusting the guys writing
4134 the MSRs to have validated the values as canonical like they should. */
4135 if (!IEM_IS_CANONICAL(uNewRip))
4136 {
4137 Log(("syscall: Only available in long mode on intel -> #UD\n"));
4138 return iemRaiseUndefinedOpcode(pVCpu);
4139 }
4140
4141 /*
4142 * Commit it.
4143 */
4144 Log(("syscall: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, uNewRip));
4145 pVCpu->cpum.GstCtx.rcx = pVCpu->cpum.GstCtx.rip + cbInstr;
4146 pVCpu->cpum.GstCtx.rip = uNewRip;
4147
4148 pVCpu->cpum.GstCtx.rflags.u &= ~X86_EFL_RF;
4149 pVCpu->cpum.GstCtx.r11 = pVCpu->cpum.GstCtx.rflags.u;
4150 pVCpu->cpum.GstCtx.rflags.u &= ~pVCpu->cpum.GstCtx.msrSFMASK;
4151 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_1;
4152
4153 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
4154 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
4155 }
4156 else
4157 {
4158 /*
4159 * Commit it.
4160 */
4161 Log(("syscall: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n",
4162 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, (uint32_t)(pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK)));
4163 pVCpu->cpum.GstCtx.rcx = pVCpu->cpum.GstCtx.eip + cbInstr;
4164 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK;
4165 pVCpu->cpum.GstCtx.rflags.u &= ~(X86_EFL_VM | X86_EFL_IF | X86_EFL_RF);
4166
4167 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
4168 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
4169 }
4170 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
4171 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
4172 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4173 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4174 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4175
4176 pVCpu->cpum.GstCtx.ss.Sel = uNewSs;
4177 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs;
4178 pVCpu->cpum.GstCtx.ss.u64Base = 0;
4179 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
4180 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4181
4182 /* Flush the prefetch buffer. */
4183#ifdef IEM_WITH_CODE_TLB
4184 pVCpu->iem.s.pbInstrBuf = NULL;
4185#else
4186 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4187#endif
4188
4189 return VINF_SUCCESS;
4190}
4191
4192
4193/**
4194 * Implements SYSRET (AMD and Intel64).
4195 */
4196IEM_CIMPL_DEF_0(iemCImpl_sysret)
4197
4198{
4199 RT_NOREF_PV(cbInstr);
4200
4201 /*
4202 * Check preconditions.
4203 *
4204 * Note that CPUs described in the documentation may load a few odd values
4205 * into CS and SS than we allow here. This has yet to be checked on real
4206 * hardware.
4207 */
4208 if (!(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SCE))
4209 {
4210 Log(("sysret: Not enabled in EFER -> #UD\n"));
4211 return iemRaiseUndefinedOpcode(pVCpu);
4212 }
4213 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4214 {
4215 Log(("sysret: Only available in long mode on intel -> #UD\n"));
4216 return iemRaiseUndefinedOpcode(pVCpu);
4217 }
4218 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4219 {
4220 Log(("sysret: Protected mode is required -> #GP(0)\n"));
4221 return iemRaiseGeneralProtectionFault0(pVCpu);
4222 }
4223 if (pVCpu->iem.s.uCpl != 0)
4224 {
4225 Log(("sysret: CPL must be 0 not %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
4226 return iemRaiseGeneralProtectionFault0(pVCpu);
4227 }
4228
4229 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS);
4230
4231 /** @todo Does SYSRET verify CS != 0 and SS != 0? Neither is valid in ring-3. */
4232 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSRET_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
4233 uint16_t uNewSs = uNewCs + 8;
4234 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4235 uNewCs += 16;
4236 if (uNewCs == 0 || uNewSs == 0)
4237 {
4238 Log(("sysret: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
4239 return iemRaiseGeneralProtectionFault0(pVCpu);
4240 }
4241
4242 /*
4243 * Commit it.
4244 */
4245 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4246 {
4247 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4248 {
4249 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64 [r11=%#llx]\n",
4250 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.r11));
4251 /* Note! We disregard intel manual regarding the RCX cananonical
4252 check, ask intel+xen why AMD doesn't do it. */
4253 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rcx;
4254 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4255 | (3 << X86DESCATTR_DPL_SHIFT);
4256 }
4257 else
4258 {
4259 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%08RX32 [r11=%#llx]\n",
4260 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.r11));
4261 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.ecx;
4262 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4263 | (3 << X86DESCATTR_DPL_SHIFT);
4264 }
4265 /** @todo testcase: See what kind of flags we can make SYSRET restore and
4266 * what it really ignores. RF and VM are hinted at being zero, by AMD. */
4267 pVCpu->cpum.GstCtx.rflags.u = pVCpu->cpum.GstCtx.r11 & (X86_EFL_POPF_BITS | X86_EFL_VIF | X86_EFL_VIP);
4268 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_1;
4269 }
4270 else
4271 {
4272 Log(("sysret: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx));
4273 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rcx;
4274 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_IF;
4275 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4276 | (3 << X86DESCATTR_DPL_SHIFT);
4277 }
4278 pVCpu->cpum.GstCtx.cs.Sel = uNewCs | 3;
4279 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs | 3;
4280 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4281 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4282 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4283
4284 pVCpu->cpum.GstCtx.ss.Sel = uNewSs | 3;
4285 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs | 3;
4286 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4287 /* The SS hidden bits remains unchanged says AMD. To that I say "Yeah, right!". */
4288 pVCpu->cpum.GstCtx.ss.Attr.u |= (3 << X86DESCATTR_DPL_SHIFT);
4289 /** @todo Testcase: verify that SS.u1Long and SS.u1DefBig are left unchanged
4290 * on sysret. */
4291
4292 /* Flush the prefetch buffer. */
4293#ifdef IEM_WITH_CODE_TLB
4294 pVCpu->iem.s.pbInstrBuf = NULL;
4295#else
4296 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4297#endif
4298
4299 return VINF_SUCCESS;
4300}
4301
4302
4303/**
4304 * Implements SYSENTER (Intel, 32-bit AMD).
4305 */
4306IEM_CIMPL_DEF_0(iemCImpl_sysenter)
4307{
4308 RT_NOREF(cbInstr);
4309
4310 /*
4311 * Check preconditions.
4312 *
4313 * Note that CPUs described in the documentation may load a few odd values
4314 * into CS and SS than we allow here. This has yet to be checked on real
4315 * hardware.
4316 */
4317 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSysEnter)
4318 {
4319 Log(("sysenter: not supported -=> #UD\n"));
4320 return iemRaiseUndefinedOpcode(pVCpu);
4321 }
4322 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4323 {
4324 Log(("sysenter: Protected or long mode is required -> #GP(0)\n"));
4325 return iemRaiseGeneralProtectionFault0(pVCpu);
4326 }
4327 bool fIsLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
4328 if (IEM_IS_GUEST_CPU_AMD(pVCpu) && fIsLongMode)
4329 {
4330 Log(("sysenter: Only available in protected mode on AMD -> #UD\n"));
4331 return iemRaiseUndefinedOpcode(pVCpu);
4332 }
4333 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSENTER_MSRS);
4334 uint16_t uNewCs = pVCpu->cpum.GstCtx.SysEnter.cs;
4335 if ((uNewCs & X86_SEL_MASK_OFF_RPL) == 0)
4336 {
4337 Log(("sysenter: SYSENTER_CS = %#x -> #GP(0)\n", uNewCs));
4338 return iemRaiseGeneralProtectionFault0(pVCpu);
4339 }
4340
4341 /* This test isn't in the docs, it's just a safeguard against missing
4342 canonical checks when writing the registers. */
4343 if (RT_LIKELY( !fIsLongMode
4344 || ( IEM_IS_CANONICAL(pVCpu->cpum.GstCtx.SysEnter.eip)
4345 && IEM_IS_CANONICAL(pVCpu->cpum.GstCtx.SysEnter.esp))))
4346 { /* likely */ }
4347 else
4348 {
4349 Log(("sysenter: SYSENTER_EIP = %#RX64 or/and SYSENTER_ESP = %#RX64 not canonical -> #GP(0)\n",
4350 pVCpu->cpum.GstCtx.SysEnter.eip, pVCpu->cpum.GstCtx.SysEnter.esp));
4351 return iemRaiseUndefinedOpcode(pVCpu);
4352 }
4353
4354/** @todo Test: Sysenter from ring-0, ring-1 and ring-2. */
4355
4356 /*
4357 * Update registers and commit.
4358 */
4359 if (fIsLongMode)
4360 {
4361 Log(("sysenter: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip,
4362 pVCpu->cpum.GstCtx.rflags.u, uNewCs & X86_SEL_MASK_OFF_RPL, pVCpu->cpum.GstCtx.SysEnter.eip));
4363 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.SysEnter.eip;
4364 pVCpu->cpum.GstCtx.rsp = pVCpu->cpum.GstCtx.SysEnter.esp;
4365 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_L | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4366 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC;
4367 }
4368 else
4369 {
4370 Log(("sysenter: %04x:%08RX32 [efl=%#llx] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs, (uint32_t)pVCpu->cpum.GstCtx.rip,
4371 pVCpu->cpum.GstCtx.rflags.u, uNewCs & X86_SEL_MASK_OFF_RPL, (uint32_t)pVCpu->cpum.GstCtx.SysEnter.eip));
4372 pVCpu->cpum.GstCtx.rip = (uint32_t)pVCpu->cpum.GstCtx.SysEnter.eip;
4373 pVCpu->cpum.GstCtx.rsp = (uint32_t)pVCpu->cpum.GstCtx.SysEnter.esp;
4374 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4375 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC;
4376 }
4377 pVCpu->cpum.GstCtx.cs.Sel = uNewCs & X86_SEL_MASK_OFF_RPL;
4378 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs & X86_SEL_MASK_OFF_RPL;
4379 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4380 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4381 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4382
4383 pVCpu->cpum.GstCtx.ss.Sel = (uNewCs & X86_SEL_MASK_OFF_RPL) + 8;
4384 pVCpu->cpum.GstCtx.ss.ValidSel = (uNewCs & X86_SEL_MASK_OFF_RPL) + 8;
4385 pVCpu->cpum.GstCtx.ss.u64Base = 0;
4386 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
4387 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4388 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_RW_ACC;
4389 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4390
4391 pVCpu->cpum.GstCtx.rflags.Bits.u1IF = 0;
4392 pVCpu->cpum.GstCtx.rflags.Bits.u1VM = 0;
4393 pVCpu->cpum.GstCtx.rflags.Bits.u1RF = 0;
4394
4395 pVCpu->iem.s.uCpl = 0;
4396
4397 /* Flush the prefetch buffer. */
4398#ifdef IEM_WITH_CODE_TLB
4399 pVCpu->iem.s.pbInstrBuf = NULL;
4400#else
4401 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4402#endif
4403
4404 return VINF_SUCCESS;
4405}
4406
4407
4408/**
4409 * Implements SYSEXIT (Intel, 32-bit AMD).
4410 *
4411 * @param enmEffOpSize The effective operand size.
4412 */
4413IEM_CIMPL_DEF_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize)
4414{
4415 RT_NOREF(cbInstr);
4416
4417 /*
4418 * Check preconditions.
4419 *
4420 * Note that CPUs described in the documentation may load a few odd values
4421 * into CS and SS than we allow here. This has yet to be checked on real
4422 * hardware.
4423 */
4424 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSysEnter)
4425 {
4426 Log(("sysexit: not supported -=> #UD\n"));
4427 return iemRaiseUndefinedOpcode(pVCpu);
4428 }
4429 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4430 {
4431 Log(("sysexit: Protected or long mode is required -> #GP(0)\n"));
4432 return iemRaiseGeneralProtectionFault0(pVCpu);
4433 }
4434 bool fIsLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
4435 if (IEM_IS_GUEST_CPU_AMD(pVCpu) && fIsLongMode)
4436 {
4437 Log(("sysexit: Only available in protected mode on AMD -> #UD\n"));
4438 return iemRaiseUndefinedOpcode(pVCpu);
4439 }
4440 if (pVCpu->iem.s.uCpl != 0)
4441 {
4442 Log(("sysexit: CPL(=%u) != 0 -> #GP(0)\n", pVCpu->iem.s.uCpl));
4443 return iemRaiseGeneralProtectionFault0(pVCpu);
4444 }
4445 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSENTER_MSRS);
4446 uint16_t uNewCs = pVCpu->cpum.GstCtx.SysEnter.cs;
4447 if ((uNewCs & X86_SEL_MASK_OFF_RPL) == 0)
4448 {
4449 Log(("sysexit: SYSENTER_CS = %#x -> #GP(0)\n", uNewCs));
4450 return iemRaiseGeneralProtectionFault0(pVCpu);
4451 }
4452
4453 /*
4454 * Update registers and commit.
4455 */
4456 if (enmEffOpSize == IEMMODE_64BIT)
4457 {
4458 Log(("sysexit: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip,
4459 pVCpu->cpum.GstCtx.rflags.u, (uNewCs | 3) + 32, pVCpu->cpum.GstCtx.rcx));
4460 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rdx;
4461 pVCpu->cpum.GstCtx.rsp = pVCpu->cpum.GstCtx.rcx;
4462 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_L | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4463 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC | (3 << X86DESCATTR_DPL_SHIFT);
4464 pVCpu->cpum.GstCtx.cs.Sel = (uNewCs | 3) + 32;
4465 pVCpu->cpum.GstCtx.cs.ValidSel = (uNewCs | 3) + 32;
4466 pVCpu->cpum.GstCtx.ss.Sel = (uNewCs | 3) + 40;
4467 pVCpu->cpum.GstCtx.ss.ValidSel = (uNewCs | 3) + 40;
4468 }
4469 else
4470 {
4471 Log(("sysexit: %04x:%08RX64 [efl=%#llx] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip,
4472 pVCpu->cpum.GstCtx.rflags.u, (uNewCs | 3) + 16, (uint32_t)pVCpu->cpum.GstCtx.edx));
4473 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.edx;
4474 pVCpu->cpum.GstCtx.rsp = pVCpu->cpum.GstCtx.ecx;
4475 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4476 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC | (3 << X86DESCATTR_DPL_SHIFT);
4477 pVCpu->cpum.GstCtx.cs.Sel = (uNewCs | 3) + 16;
4478 pVCpu->cpum.GstCtx.cs.ValidSel = (uNewCs | 3) + 16;
4479 pVCpu->cpum.GstCtx.ss.Sel = (uNewCs | 3) + 24;
4480 pVCpu->cpum.GstCtx.ss.ValidSel = (uNewCs | 3) + 24;
4481 }
4482 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4483 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4484 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4485
4486 pVCpu->cpum.GstCtx.ss.u64Base = 0;
4487 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
4488 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4489 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_RW_ACC | (3 << X86DESCATTR_DPL_SHIFT);
4490 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4491 pVCpu->cpum.GstCtx.rflags.Bits.u1RF = 0;
4492
4493 pVCpu->iem.s.uCpl = 3;
4494
4495 /* Flush the prefetch buffer. */
4496#ifdef IEM_WITH_CODE_TLB
4497 pVCpu->iem.s.pbInstrBuf = NULL;
4498#else
4499 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4500#endif
4501
4502 return VINF_SUCCESS;
4503}
4504
4505
4506/**
4507 * Common worker for 'pop SReg', 'mov SReg, GReg' and 'lXs GReg, reg/mem'.
4508 *
4509 * @param iSegReg The segment register number (valid).
4510 * @param uSel The new selector value.
4511 */
4512IEM_CIMPL_DEF_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel)
4513{
4514 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
4515 uint16_t *pSel = iemSRegRef(pVCpu, iSegReg);
4516 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
4517
4518 Assert(iSegReg <= X86_SREG_GS && iSegReg != X86_SREG_CS);
4519
4520 /*
4521 * Real mode and V8086 mode are easy.
4522 */
4523 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4524 {
4525 *pSel = uSel;
4526 pHid->u64Base = (uint32_t)uSel << 4;
4527 pHid->ValidSel = uSel;
4528 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4529#if 0 /* AMD Volume 2, chapter 4.1 - "real mode segmentation" - states that limit and attributes are untouched. */
4530 /** @todo Does the CPU actually load limits and attributes in the
4531 * real/V8086 mode segment load case? It doesn't for CS in far
4532 * jumps... Affects unreal mode. */
4533 pHid->u32Limit = 0xffff;
4534 pHid->Attr.u = 0;
4535 pHid->Attr.n.u1Present = 1;
4536 pHid->Attr.n.u1DescType = 1;
4537 pHid->Attr.n.u4Type = iSegReg != X86_SREG_CS
4538 ? X86_SEL_TYPE_RW
4539 : X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
4540#endif
4541 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4542 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4543 return VINF_SUCCESS;
4544 }
4545
4546 /*
4547 * Protected mode.
4548 *
4549 * Check if it's a null segment selector value first, that's OK for DS, ES,
4550 * FS and GS. If not null, then we have to load and parse the descriptor.
4551 */
4552 if (!(uSel & X86_SEL_MASK_OFF_RPL))
4553 {
4554 Assert(iSegReg != X86_SREG_CS); /** @todo testcase for \#UD on MOV CS, ax! */
4555 if (iSegReg == X86_SREG_SS)
4556 {
4557 /* In 64-bit kernel mode, the stack can be 0 because of the way
4558 interrupts are dispatched. AMD seems to have a slighly more
4559 relaxed relationship to SS.RPL than intel does. */
4560 /** @todo We cannot 'mov ss, 3' in 64-bit kernel mode, can we? There is a testcase (bs-cpu-xcpt-1), but double check this! */
4561 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4562 || pVCpu->iem.s.uCpl > 2
4563 || ( uSel != pVCpu->iem.s.uCpl
4564 && !IEM_IS_GUEST_CPU_AMD(pVCpu)) )
4565 {
4566 Log(("load sreg %#x -> invalid stack selector, #GP(0)\n", uSel));
4567 return iemRaiseGeneralProtectionFault0(pVCpu);
4568 }
4569 }
4570
4571 *pSel = uSel; /* Not RPL, remember :-) */
4572 iemHlpLoadNullDataSelectorProt(pVCpu, pHid, uSel);
4573 if (iSegReg == X86_SREG_SS)
4574 pHid->Attr.u |= pVCpu->iem.s.uCpl << X86DESCATTR_DPL_SHIFT;
4575
4576 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4577 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4578
4579 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4580 return VINF_SUCCESS;
4581 }
4582
4583 /* Fetch the descriptor. */
4584 IEMSELDESC Desc;
4585 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP); /** @todo Correct exception? */
4586 if (rcStrict != VINF_SUCCESS)
4587 return rcStrict;
4588
4589 /* Check GPs first. */
4590 if (!Desc.Legacy.Gen.u1DescType)
4591 {
4592 Log(("load sreg %d (=%#x) - system selector (%#x) -> #GP\n", iSegReg, uSel, Desc.Legacy.Gen.u4Type));
4593 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4594 }
4595 if (iSegReg == X86_SREG_SS) /* SS gets different treatment */
4596 {
4597 if ( (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
4598 || !(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
4599 {
4600 Log(("load sreg SS, %#x - code or read only (%#x) -> #GP\n", uSel, Desc.Legacy.Gen.u4Type));
4601 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4602 }
4603 if ((uSel & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
4604 {
4605 Log(("load sreg SS, %#x - RPL and CPL (%d) differs -> #GP\n", uSel, pVCpu->iem.s.uCpl));
4606 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4607 }
4608 if (Desc.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
4609 {
4610 Log(("load sreg SS, %#x - DPL (%d) and CPL (%d) differs -> #GP\n", uSel, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
4611 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4612 }
4613 }
4614 else
4615 {
4616 if ((Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4617 {
4618 Log(("load sreg%u, %#x - execute only segment -> #GP\n", iSegReg, uSel));
4619 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4620 }
4621 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4622 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4623 {
4624#if 0 /* this is what intel says. */
4625 if ( (uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl
4626 && pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4627 {
4628 Log(("load sreg%u, %#x - both RPL (%d) and CPL (%d) are greater than DPL (%d) -> #GP\n",
4629 iSegReg, uSel, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4630 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4631 }
4632#else /* this is what makes more sense. */
4633 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4634 {
4635 Log(("load sreg%u, %#x - RPL (%d) is greater than DPL (%d) -> #GP\n",
4636 iSegReg, uSel, (uSel & X86_SEL_RPL), Desc.Legacy.Gen.u2Dpl));
4637 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4638 }
4639 if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4640 {
4641 Log(("load sreg%u, %#x - CPL (%d) is greater than DPL (%d) -> #GP\n",
4642 iSegReg, uSel, pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4643 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4644 }
4645#endif
4646 }
4647 }
4648
4649 /* Is it there? */
4650 if (!Desc.Legacy.Gen.u1Present)
4651 {
4652 Log(("load sreg%d,%#x - segment not present -> #NP\n", iSegReg, uSel));
4653 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
4654 }
4655
4656 /* The base and limit. */
4657 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
4658 uint64_t u64Base = X86DESC_BASE(&Desc.Legacy);
4659
4660 /*
4661 * Ok, everything checked out fine. Now set the accessed bit before
4662 * committing the result into the registers.
4663 */
4664 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
4665 {
4666 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
4667 if (rcStrict != VINF_SUCCESS)
4668 return rcStrict;
4669 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
4670 }
4671
4672 /* commit */
4673 *pSel = uSel;
4674 pHid->Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4675 pHid->u32Limit = cbLimit;
4676 pHid->u64Base = u64Base;
4677 pHid->ValidSel = uSel;
4678 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4679
4680 /** @todo check if the hidden bits are loaded correctly for 64-bit
4681 * mode. */
4682 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4683
4684 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4685 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4686 return VINF_SUCCESS;
4687}
4688
4689
4690/**
4691 * Implements 'mov SReg, r/m'.
4692 *
4693 * @param iSegReg The segment register number (valid).
4694 * @param uSel The new selector value.
4695 */
4696IEM_CIMPL_DEF_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel)
4697{
4698 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4699 if (rcStrict == VINF_SUCCESS)
4700 {
4701 if (iSegReg == X86_SREG_SS)
4702 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
4703 }
4704 return rcStrict;
4705}
4706
4707
4708/**
4709 * Implements 'pop SReg'.
4710 *
4711 * @param iSegReg The segment register number (valid).
4712 * @param enmEffOpSize The efficient operand size (valid).
4713 */
4714IEM_CIMPL_DEF_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize)
4715{
4716 VBOXSTRICTRC rcStrict;
4717
4718 /*
4719 * Read the selector off the stack and join paths with mov ss, reg.
4720 */
4721 RTUINT64U TmpRsp;
4722 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
4723 switch (enmEffOpSize)
4724 {
4725 case IEMMODE_16BIT:
4726 {
4727 uint16_t uSel;
4728 rcStrict = iemMemStackPopU16Ex(pVCpu, &uSel, &TmpRsp);
4729 if (rcStrict == VINF_SUCCESS)
4730 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4731 break;
4732 }
4733
4734 case IEMMODE_32BIT:
4735 {
4736 uint32_t u32Value;
4737 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Value, &TmpRsp);
4738 if (rcStrict == VINF_SUCCESS)
4739 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u32Value);
4740 break;
4741 }
4742
4743 case IEMMODE_64BIT:
4744 {
4745 uint64_t u64Value;
4746 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Value, &TmpRsp);
4747 if (rcStrict == VINF_SUCCESS)
4748 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u64Value);
4749 break;
4750 }
4751 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4752 }
4753
4754 /*
4755 * Commit the stack on success.
4756 */
4757 if (rcStrict == VINF_SUCCESS)
4758 {
4759 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
4760 if (iSegReg == X86_SREG_SS)
4761 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
4762 }
4763 return rcStrict;
4764}
4765
4766
4767/**
4768 * Implements lgs, lfs, les, lds & lss.
4769 */
4770IEM_CIMPL_DEF_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize)
4771{
4772 /*
4773 * Use iemCImpl_LoadSReg to do the tricky segment register loading.
4774 */
4775 /** @todo verify and test that mov, pop and lXs works the segment
4776 * register loading in the exact same way. */
4777 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4778 if (rcStrict == VINF_SUCCESS)
4779 {
4780 switch (enmEffOpSize)
4781 {
4782 case IEMMODE_16BIT:
4783 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4784 break;
4785 case IEMMODE_32BIT:
4786 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4787 break;
4788 case IEMMODE_64BIT:
4789 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4790 break;
4791 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4792 }
4793 }
4794
4795 return rcStrict;
4796}
4797
4798
4799/**
4800 * Helper for VERR, VERW, LAR, and LSL and loads the descriptor into memory.
4801 *
4802 * @retval VINF_SUCCESS on success.
4803 * @retval VINF_IEM_SELECTOR_NOT_OK if the selector isn't ok.
4804 * @retval iemMemFetchSysU64 return value.
4805 *
4806 * @param pVCpu The cross context virtual CPU structure of the calling thread.
4807 * @param uSel The selector value.
4808 * @param fAllowSysDesc Whether system descriptors are OK or not.
4809 * @param pDesc Where to return the descriptor on success.
4810 */
4811static VBOXSTRICTRC iemCImpl_LoadDescHelper(PVMCPUCC pVCpu, uint16_t uSel, bool fAllowSysDesc, PIEMSELDESC pDesc)
4812{
4813 pDesc->Long.au64[0] = 0;
4814 pDesc->Long.au64[1] = 0;
4815
4816 if (!(uSel & X86_SEL_MASK_OFF_RPL)) /** @todo test this on 64-bit. */
4817 return VINF_IEM_SELECTOR_NOT_OK;
4818
4819 /* Within the table limits? */
4820 RTGCPTR GCPtrBase;
4821 if (uSel & X86_SEL_LDT)
4822 {
4823 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
4824 if ( !pVCpu->cpum.GstCtx.ldtr.Attr.n.u1Present
4825 || (uSel | X86_SEL_RPL_LDT) > pVCpu->cpum.GstCtx.ldtr.u32Limit )
4826 return VINF_IEM_SELECTOR_NOT_OK;
4827 GCPtrBase = pVCpu->cpum.GstCtx.ldtr.u64Base;
4828 }
4829 else
4830 {
4831 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_GDTR);
4832 if ((uSel | X86_SEL_RPL_LDT) > pVCpu->cpum.GstCtx.gdtr.cbGdt)
4833 return VINF_IEM_SELECTOR_NOT_OK;
4834 GCPtrBase = pVCpu->cpum.GstCtx.gdtr.pGdt;
4835 }
4836
4837 /* Fetch the descriptor. */
4838 VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Legacy.u, UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK));
4839 if (rcStrict != VINF_SUCCESS)
4840 return rcStrict;
4841 if (!pDesc->Legacy.Gen.u1DescType)
4842 {
4843 if (!fAllowSysDesc)
4844 return VINF_IEM_SELECTOR_NOT_OK;
4845 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4846 {
4847 rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Long.au64[1], UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK) + 8);
4848 if (rcStrict != VINF_SUCCESS)
4849 return rcStrict;
4850 }
4851
4852 }
4853
4854 return VINF_SUCCESS;
4855}
4856
4857
4858/**
4859 * Implements verr (fWrite = false) and verw (fWrite = true).
4860 */
4861IEM_CIMPL_DEF_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite)
4862{
4863 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4864
4865 /** @todo figure whether the accessed bit is set or not. */
4866
4867 bool fAccessible = true;
4868 IEMSELDESC Desc;
4869 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, false /*fAllowSysDesc*/, &Desc);
4870 if (rcStrict == VINF_SUCCESS)
4871 {
4872 /* Check the descriptor, order doesn't matter much here. */
4873 if ( !Desc.Legacy.Gen.u1DescType
4874 || !Desc.Legacy.Gen.u1Present)
4875 fAccessible = false;
4876 else
4877 {
4878 if ( fWrite
4879 ? (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE
4880 : (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4881 fAccessible = false;
4882
4883 /** @todo testcase for the conforming behavior. */
4884 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4885 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4886 {
4887 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4888 fAccessible = false;
4889 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4890 fAccessible = false;
4891 }
4892 }
4893
4894 }
4895 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4896 fAccessible = false;
4897 else
4898 return rcStrict;
4899
4900 /* commit */
4901 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fAccessible;
4902
4903 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4904 return VINF_SUCCESS;
4905}
4906
4907
4908/**
4909 * Implements LAR and LSL with 64-bit operand size.
4910 *
4911 * @returns VINF_SUCCESS.
4912 * @param pu64Dst Pointer to the destination register.
4913 * @param uSel The selector to load details for.
4914 * @param fIsLar true = LAR, false = LSL.
4915 */
4916IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar)
4917{
4918 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4919
4920 /** @todo figure whether the accessed bit is set or not. */
4921
4922 bool fDescOk = true;
4923 IEMSELDESC Desc;
4924 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, true /*fAllowSysDesc*/, &Desc);
4925 if (rcStrict == VINF_SUCCESS)
4926 {
4927 /*
4928 * Check the descriptor type.
4929 */
4930 if (!Desc.Legacy.Gen.u1DescType)
4931 {
4932 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4933 {
4934 if (Desc.Long.Gen.u5Zeros)
4935 fDescOk = false;
4936 else
4937 switch (Desc.Long.Gen.u4Type)
4938 {
4939 /** @todo Intel lists 0 as valid for LSL, verify whether that's correct */
4940 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
4941 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
4942 case AMD64_SEL_TYPE_SYS_LDT: /** @todo Intel lists this as invalid for LAR, AMD and 32-bit does otherwise. */
4943 break;
4944 case AMD64_SEL_TYPE_SYS_CALL_GATE:
4945 fDescOk = fIsLar;
4946 break;
4947 default:
4948 fDescOk = false;
4949 break;
4950 }
4951 }
4952 else
4953 {
4954 switch (Desc.Long.Gen.u4Type)
4955 {
4956 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
4957 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
4958 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
4959 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
4960 case X86_SEL_TYPE_SYS_LDT:
4961 break;
4962 case X86_SEL_TYPE_SYS_286_CALL_GATE:
4963 case X86_SEL_TYPE_SYS_TASK_GATE:
4964 case X86_SEL_TYPE_SYS_386_CALL_GATE:
4965 fDescOk = fIsLar;
4966 break;
4967 default:
4968 fDescOk = false;
4969 break;
4970 }
4971 }
4972 }
4973 if (fDescOk)
4974 {
4975 /*
4976 * Check the RPL/DPL/CPL interaction..
4977 */
4978 /** @todo testcase for the conforming behavior. */
4979 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)
4980 || !Desc.Legacy.Gen.u1DescType)
4981 {
4982 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4983 fDescOk = false;
4984 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4985 fDescOk = false;
4986 }
4987 }
4988
4989 if (fDescOk)
4990 {
4991 /*
4992 * All fine, start committing the result.
4993 */
4994 if (fIsLar)
4995 *pu64Dst = Desc.Legacy.au32[1] & UINT32_C(0x00ffff00);
4996 else
4997 *pu64Dst = X86DESC_LIMIT_G(&Desc.Legacy);
4998 }
4999
5000 }
5001 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
5002 fDescOk = false;
5003 else
5004 return rcStrict;
5005
5006 /* commit flags value and advance rip. */
5007 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fDescOk;
5008 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5009
5010 return VINF_SUCCESS;
5011}
5012
5013
5014/**
5015 * Implements LAR and LSL with 16-bit operand size.
5016 *
5017 * @returns VINF_SUCCESS.
5018 * @param pu16Dst Pointer to the destination register.
5019 * @param uSel The selector to load details for.
5020 * @param fIsLar true = LAR, false = LSL.
5021 */
5022IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar)
5023{
5024 uint64_t u64TmpDst = *pu16Dst;
5025 IEM_CIMPL_CALL_3(iemCImpl_LarLsl_u64, &u64TmpDst, uSel, fIsLar);
5026 *pu16Dst = u64TmpDst;
5027 return VINF_SUCCESS;
5028}
5029
5030
5031/**
5032 * Implements lgdt.
5033 *
5034 * @param iEffSeg The segment of the new gdtr contents
5035 * @param GCPtrEffSrc The address of the new gdtr contents.
5036 * @param enmEffOpSize The effective operand size.
5037 */
5038IEM_CIMPL_DEF_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
5039{
5040 if (pVCpu->iem.s.uCpl != 0)
5041 return iemRaiseGeneralProtectionFault0(pVCpu);
5042 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5043
5044 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5045 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5046 {
5047 Log(("lgdt: Guest intercept -> VM-exit\n"));
5048 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_GDTR_IDTR_ACCESS, VMXINSTRID_LGDT, cbInstr);
5049 }
5050
5051 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_WRITES))
5052 {
5053 Log(("lgdt: Guest intercept -> #VMEXIT\n"));
5054 IEM_SVM_UPDATE_NRIP(pVCpu);
5055 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5056 }
5057
5058 /*
5059 * Fetch the limit and base address.
5060 */
5061 uint16_t cbLimit;
5062 RTGCPTR GCPtrBase;
5063 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
5064 if (rcStrict == VINF_SUCCESS)
5065 {
5066 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
5067 || X86_IS_CANONICAL(GCPtrBase))
5068 {
5069 rcStrict = CPUMSetGuestGDTR(pVCpu, GCPtrBase, cbLimit);
5070 if (rcStrict == VINF_SUCCESS)
5071 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5072 }
5073 else
5074 {
5075 Log(("iemCImpl_lgdt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
5076 return iemRaiseGeneralProtectionFault0(pVCpu);
5077 }
5078 }
5079 return rcStrict;
5080}
5081
5082
5083/**
5084 * Implements sgdt.
5085 *
5086 * @param iEffSeg The segment where to store the gdtr content.
5087 * @param GCPtrEffDst The address where to store the gdtr content.
5088 */
5089IEM_CIMPL_DEF_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5090{
5091 /*
5092 * Join paths with sidt.
5093 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
5094 * you really must know.
5095 */
5096 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5097 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5098 {
5099 Log(("sgdt: Guest intercept -> VM-exit\n"));
5100 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_GDTR_IDTR_ACCESS, VMXINSTRID_SGDT, cbInstr);
5101 }
5102
5103 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_READS))
5104 {
5105 Log(("sgdt: Guest intercept -> #VMEXIT\n"));
5106 IEM_SVM_UPDATE_NRIP(pVCpu);
5107 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5108 }
5109
5110 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_GDTR);
5111 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.gdtr.cbGdt, pVCpu->cpum.GstCtx.gdtr.pGdt, iEffSeg, GCPtrEffDst);
5112 if (rcStrict == VINF_SUCCESS)
5113 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5114 return rcStrict;
5115}
5116
5117
5118/**
5119 * Implements lidt.
5120 *
5121 * @param iEffSeg The segment of the new idtr contents
5122 * @param GCPtrEffSrc The address of the new idtr contents.
5123 * @param enmEffOpSize The effective operand size.
5124 */
5125IEM_CIMPL_DEF_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
5126{
5127 if (pVCpu->iem.s.uCpl != 0)
5128 return iemRaiseGeneralProtectionFault0(pVCpu);
5129 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5130
5131 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_WRITES))
5132 {
5133 Log(("lidt: Guest intercept -> #VMEXIT\n"));
5134 IEM_SVM_UPDATE_NRIP(pVCpu);
5135 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5136 }
5137
5138 /*
5139 * Fetch the limit and base address.
5140 */
5141 uint16_t cbLimit;
5142 RTGCPTR GCPtrBase;
5143 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
5144 if (rcStrict == VINF_SUCCESS)
5145 {
5146 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
5147 || X86_IS_CANONICAL(GCPtrBase))
5148 {
5149 CPUMSetGuestIDTR(pVCpu, GCPtrBase, cbLimit);
5150 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5151 }
5152 else
5153 {
5154 Log(("iemCImpl_lidt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
5155 return iemRaiseGeneralProtectionFault0(pVCpu);
5156 }
5157 }
5158 return rcStrict;
5159}
5160
5161
5162/**
5163 * Implements sidt.
5164 *
5165 * @param iEffSeg The segment where to store the idtr content.
5166 * @param GCPtrEffDst The address where to store the idtr content.
5167 */
5168IEM_CIMPL_DEF_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5169{
5170 /*
5171 * Join paths with sgdt.
5172 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
5173 * you really must know.
5174 */
5175 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_READS))
5176 {
5177 Log(("sidt: Guest intercept -> #VMEXIT\n"));
5178 IEM_SVM_UPDATE_NRIP(pVCpu);
5179 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5180 }
5181
5182 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_IDTR);
5183 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.idtr.cbIdt, pVCpu->cpum.GstCtx.idtr.pIdt, iEffSeg, GCPtrEffDst);
5184 if (rcStrict == VINF_SUCCESS)
5185 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5186 return rcStrict;
5187}
5188
5189
5190/**
5191 * Implements lldt.
5192 *
5193 * @param uNewLdt The new LDT selector value.
5194 */
5195IEM_CIMPL_DEF_1(iemCImpl_lldt, uint16_t, uNewLdt)
5196{
5197 /*
5198 * Check preconditions.
5199 */
5200 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
5201 {
5202 Log(("lldt %04x - real or v8086 mode -> #GP(0)\n", uNewLdt));
5203 return iemRaiseUndefinedOpcode(pVCpu);
5204 }
5205 if (pVCpu->iem.s.uCpl != 0)
5206 {
5207 Log(("lldt %04x - CPL is %d -> #GP(0)\n", uNewLdt, pVCpu->iem.s.uCpl));
5208 return iemRaiseGeneralProtectionFault0(pVCpu);
5209 }
5210 /* Nested-guest VMX intercept. */
5211 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5212 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5213 {
5214 Log(("lldt: Guest intercept -> VM-exit\n"));
5215 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_LLDT, cbInstr);
5216 }
5217 if (uNewLdt & X86_SEL_LDT)
5218 {
5219 Log(("lldt %04x - LDT selector -> #GP\n", uNewLdt));
5220 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewLdt);
5221 }
5222
5223 /*
5224 * Now, loading a NULL selector is easy.
5225 */
5226 if (!(uNewLdt & X86_SEL_MASK_OFF_RPL))
5227 {
5228 /* Nested-guest SVM intercept. */
5229 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
5230 {
5231 Log(("lldt: Guest intercept -> #VMEXIT\n"));
5232 IEM_SVM_UPDATE_NRIP(pVCpu);
5233 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5234 }
5235
5236 Log(("lldt %04x: Loading NULL selector.\n", uNewLdt));
5237 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_LDTR;
5238 CPUMSetGuestLDTR(pVCpu, uNewLdt);
5239 pVCpu->cpum.GstCtx.ldtr.ValidSel = uNewLdt;
5240 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
5241 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
5242 {
5243 /* AMD-V seems to leave the base and limit alone. */
5244 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
5245 }
5246 else
5247 {
5248 /* VT-x (Intel 3960x) seems to be doing the following. */
5249 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D;
5250 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
5251 pVCpu->cpum.GstCtx.ldtr.u32Limit = UINT32_MAX;
5252 }
5253
5254 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5255 return VINF_SUCCESS;
5256 }
5257
5258 /*
5259 * Read the descriptor.
5260 */
5261 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR);
5262 IEMSELDESC Desc;
5263 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewLdt, X86_XCPT_GP); /** @todo Correct exception? */
5264 if (rcStrict != VINF_SUCCESS)
5265 return rcStrict;
5266
5267 /* Check GPs first. */
5268 if (Desc.Legacy.Gen.u1DescType)
5269 {
5270 Log(("lldt %#x - not system selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
5271 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5272 }
5273 if (Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
5274 {
5275 Log(("lldt %#x - not LDT selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
5276 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5277 }
5278 uint64_t u64Base;
5279 if (!IEM_IS_LONG_MODE(pVCpu))
5280 u64Base = X86DESC_BASE(&Desc.Legacy);
5281 else
5282 {
5283 if (Desc.Long.Gen.u5Zeros)
5284 {
5285 Log(("lldt %#x - u5Zeros=%#x -> #GP\n", uNewLdt, Desc.Long.Gen.u5Zeros));
5286 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5287 }
5288
5289 u64Base = X86DESC64_BASE(&Desc.Long);
5290 if (!IEM_IS_CANONICAL(u64Base))
5291 {
5292 Log(("lldt %#x - non-canonical base address %#llx -> #GP\n", uNewLdt, u64Base));
5293 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5294 }
5295 }
5296
5297 /* NP */
5298 if (!Desc.Legacy.Gen.u1Present)
5299 {
5300 Log(("lldt %#x - segment not present -> #NP\n", uNewLdt));
5301 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewLdt);
5302 }
5303
5304 /* Nested-guest SVM intercept. */
5305 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
5306 {
5307 Log(("lldt: Guest intercept -> #VMEXIT\n"));
5308 IEM_SVM_UPDATE_NRIP(pVCpu);
5309 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5310 }
5311
5312 /*
5313 * It checks out alright, update the registers.
5314 */
5315/** @todo check if the actual value is loaded or if the RPL is dropped */
5316 CPUMSetGuestLDTR(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5317 pVCpu->cpum.GstCtx.ldtr.ValidSel = uNewLdt & X86_SEL_MASK_OFF_RPL;
5318 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
5319 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
5320 pVCpu->cpum.GstCtx.ldtr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
5321 pVCpu->cpum.GstCtx.ldtr.u64Base = u64Base;
5322
5323 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5324 return VINF_SUCCESS;
5325}
5326
5327
5328/**
5329 * Implements sldt GReg
5330 *
5331 * @param iGReg The general register to store the CRx value in.
5332 * @param enmEffOpSize The operand size.
5333 */
5334IEM_CIMPL_DEF_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5335{
5336 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5337 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5338 {
5339 Log(("sldt: Guest intercept -> VM-exit\n"));
5340 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_SLDT, cbInstr);
5341 }
5342
5343 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
5344
5345 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
5346 switch (enmEffOpSize)
5347 {
5348 case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
5349 case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
5350 case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
5351 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5352 }
5353 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5354 return VINF_SUCCESS;
5355}
5356
5357
5358/**
5359 * Implements sldt mem.
5360 *
5361 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5362 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5363 */
5364IEM_CIMPL_DEF_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5365{
5366 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
5367
5368 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
5369 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.ldtr.Sel);
5370 if (rcStrict == VINF_SUCCESS)
5371 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5372 return rcStrict;
5373}
5374
5375
5376/**
5377 * Implements ltr.
5378 *
5379 * @param uNewTr The new TSS selector value.
5380 */
5381IEM_CIMPL_DEF_1(iemCImpl_ltr, uint16_t, uNewTr)
5382{
5383 /*
5384 * Check preconditions.
5385 */
5386 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
5387 {
5388 Log(("ltr %04x - real or v8086 mode -> #GP(0)\n", uNewTr));
5389 return iemRaiseUndefinedOpcode(pVCpu);
5390 }
5391 if (pVCpu->iem.s.uCpl != 0)
5392 {
5393 Log(("ltr %04x - CPL is %d -> #GP(0)\n", uNewTr, pVCpu->iem.s.uCpl));
5394 return iemRaiseGeneralProtectionFault0(pVCpu);
5395 }
5396 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5397 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5398 {
5399 Log(("ltr: Guest intercept -> VM-exit\n"));
5400 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_LTR, cbInstr);
5401 }
5402 if (uNewTr & X86_SEL_LDT)
5403 {
5404 Log(("ltr %04x - LDT selector -> #GP\n", uNewTr));
5405 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewTr);
5406 }
5407 if (!(uNewTr & X86_SEL_MASK_OFF_RPL))
5408 {
5409 Log(("ltr %04x - NULL selector -> #GP(0)\n", uNewTr));
5410 return iemRaiseGeneralProtectionFault0(pVCpu);
5411 }
5412 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_TR_WRITES))
5413 {
5414 Log(("ltr: Guest intercept -> #VMEXIT\n"));
5415 IEM_SVM_UPDATE_NRIP(pVCpu);
5416 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_TR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5417 }
5418
5419 /*
5420 * Read the descriptor.
5421 */
5422 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_TR);
5423 IEMSELDESC Desc;
5424 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewTr, X86_XCPT_GP); /** @todo Correct exception? */
5425 if (rcStrict != VINF_SUCCESS)
5426 return rcStrict;
5427
5428 /* Check GPs first. */
5429 if (Desc.Legacy.Gen.u1DescType)
5430 {
5431 Log(("ltr %#x - not system selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
5432 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5433 }
5434 if ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL /* same as AMD64_SEL_TYPE_SYS_TSS_AVAIL */
5435 && ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_286_TSS_AVAIL
5436 || IEM_IS_LONG_MODE(pVCpu)) )
5437 {
5438 Log(("ltr %#x - not an available TSS selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
5439 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5440 }
5441 uint64_t u64Base;
5442 if (!IEM_IS_LONG_MODE(pVCpu))
5443 u64Base = X86DESC_BASE(&Desc.Legacy);
5444 else
5445 {
5446 if (Desc.Long.Gen.u5Zeros)
5447 {
5448 Log(("ltr %#x - u5Zeros=%#x -> #GP\n", uNewTr, Desc.Long.Gen.u5Zeros));
5449 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5450 }
5451
5452 u64Base = X86DESC64_BASE(&Desc.Long);
5453 if (!IEM_IS_CANONICAL(u64Base))
5454 {
5455 Log(("ltr %#x - non-canonical base address %#llx -> #GP\n", uNewTr, u64Base));
5456 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5457 }
5458 }
5459
5460 /* NP */
5461 if (!Desc.Legacy.Gen.u1Present)
5462 {
5463 Log(("ltr %#x - segment not present -> #NP\n", uNewTr));
5464 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewTr);
5465 }
5466
5467 /*
5468 * Set it busy.
5469 * Note! Intel says this should lock down the whole descriptor, but we'll
5470 * restrict our selves to 32-bit for now due to lack of inline
5471 * assembly and such.
5472 */
5473 void *pvDesc;
5474 rcStrict = iemMemMap(pVCpu, &pvDesc, 8, UINT8_MAX, pVCpu->cpum.GstCtx.gdtr.pGdt + (uNewTr & X86_SEL_MASK_OFF_RPL),
5475 IEM_ACCESS_DATA_RW, 0);
5476 if (rcStrict != VINF_SUCCESS)
5477 return rcStrict;
5478 switch ((uintptr_t)pvDesc & 3)
5479 {
5480 case 0: ASMAtomicBitSet(pvDesc, 40 + 1); break;
5481 case 1: ASMAtomicBitSet((uint8_t *)pvDesc + 3, 40 + 1 - 24); break;
5482 case 2: ASMAtomicBitSet((uint8_t *)pvDesc + 2, 40 + 1 - 16); break;
5483 case 3: ASMAtomicBitSet((uint8_t *)pvDesc + 1, 40 + 1 - 8); break;
5484 }
5485 rcStrict = iemMemCommitAndUnmap(pVCpu, pvDesc, IEM_ACCESS_DATA_RW);
5486 if (rcStrict != VINF_SUCCESS)
5487 return rcStrict;
5488 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
5489
5490 /*
5491 * It checks out alright, update the registers.
5492 */
5493/** @todo check if the actual value is loaded or if the RPL is dropped */
5494 CPUMSetGuestTR(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5495 pVCpu->cpum.GstCtx.tr.ValidSel = uNewTr & X86_SEL_MASK_OFF_RPL;
5496 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
5497 pVCpu->cpum.GstCtx.tr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
5498 pVCpu->cpum.GstCtx.tr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
5499 pVCpu->cpum.GstCtx.tr.u64Base = u64Base;
5500
5501 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5502 return VINF_SUCCESS;
5503}
5504
5505
5506/**
5507 * Implements str GReg
5508 *
5509 * @param iGReg The general register to store the CRx value in.
5510 * @param enmEffOpSize The operand size.
5511 */
5512IEM_CIMPL_DEF_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5513{
5514 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5515 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5516 {
5517 Log(("str_reg: Guest intercept -> VM-exit\n"));
5518 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_STR, cbInstr);
5519 }
5520
5521 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
5522
5523 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
5524 switch (enmEffOpSize)
5525 {
5526 case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5527 case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5528 case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5529 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5530 }
5531 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5532 return VINF_SUCCESS;
5533}
5534
5535
5536/**
5537 * Implements str mem.
5538 *
5539 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5540 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5541 */
5542IEM_CIMPL_DEF_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5543{
5544 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5545 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5546 {
5547 Log(("str_mem: Guest intercept -> VM-exit\n"));
5548 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_STR, cbInstr);
5549 }
5550
5551 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
5552
5553 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
5554 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.tr.Sel);
5555 if (rcStrict == VINF_SUCCESS)
5556 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5557 return rcStrict;
5558}
5559
5560
5561/**
5562 * Implements mov GReg,CRx.
5563 *
5564 * @param iGReg The general register to store the CRx value in.
5565 * @param iCrReg The CRx register to read (valid).
5566 */
5567IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg)
5568{
5569 if (pVCpu->iem.s.uCpl != 0)
5570 return iemRaiseGeneralProtectionFault0(pVCpu);
5571 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5572
5573 if (IEM_SVM_IS_READ_CR_INTERCEPT_SET(pVCpu, iCrReg))
5574 {
5575 Log(("iemCImpl_mov_Rd_Cd: Guest intercept CR%u -> #VMEXIT\n", iCrReg));
5576 IEM_SVM_UPDATE_NRIP(pVCpu);
5577 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_READ_CR0 + iCrReg, IEMACCESSCRX_MOV_CRX, iGReg);
5578 }
5579
5580 /* Read it. */
5581 uint64_t crX;
5582 switch (iCrReg)
5583 {
5584 case 0:
5585 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5586 crX = pVCpu->cpum.GstCtx.cr0;
5587 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
5588 crX |= UINT32_C(0x7fffffe0); /* All reserved CR0 flags are set on a 386, just like MSW on 286. */
5589 break;
5590 case 2:
5591 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR2);
5592 crX = pVCpu->cpum.GstCtx.cr2;
5593 break;
5594 case 3:
5595 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5596 crX = pVCpu->cpum.GstCtx.cr3;
5597 break;
5598 case 4:
5599 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
5600 crX = pVCpu->cpum.GstCtx.cr4;
5601 break;
5602 case 8:
5603 {
5604 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
5605#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5606 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5607 {
5608 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovFromCr8(pVCpu, iGReg, cbInstr);
5609 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5610 return rcStrict;
5611
5612 /*
5613 * If the Mov-from-CR8 doesn't cause a VM-exit, bits 7:4 of the VTPR is copied
5614 * to bits 0:3 of the destination operand. Bits 63:4 of the destination operand
5615 * are cleared.
5616 *
5617 * See Intel Spec. 29.3 "Virtualizing CR8-based TPR Accesses"
5618 */
5619 if (IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_USE_TPR_SHADOW))
5620 {
5621 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5622 crX = (uTpr >> 4) & 0xf;
5623 break;
5624 }
5625 }
5626#endif
5627#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5628 if (CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
5629 {
5630 PCSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl;
5631 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, IEM_GET_CTX(pVCpu)))
5632 {
5633 crX = pVmcbCtrl->IntCtrl.n.u8VTPR & 0xf;
5634 break;
5635 }
5636 }
5637#endif
5638 uint8_t uTpr;
5639 int rc = APICGetTpr(pVCpu, &uTpr, NULL, NULL);
5640 if (RT_SUCCESS(rc))
5641 crX = uTpr >> 4;
5642 else
5643 crX = 0;
5644 break;
5645 }
5646 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5647 }
5648
5649#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5650 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5651 {
5652 switch (iCrReg)
5653 {
5654 /* CR0/CR4 reads are subject to masking when in VMX non-root mode. */
5655 case 0: crX = CPUMGetGuestVmxMaskedCr0(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u); break;
5656 case 4: crX = CPUMGetGuestVmxMaskedCr4(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u); break;
5657
5658 case 3:
5659 {
5660 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovFromCr3(pVCpu, iGReg, cbInstr);
5661 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5662 return rcStrict;
5663 break;
5664 }
5665 }
5666 }
5667#endif
5668
5669 /* Store it. */
5670 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5671 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = crX;
5672 else
5673 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)crX;
5674
5675 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5676 return VINF_SUCCESS;
5677}
5678
5679
5680/**
5681 * Implements smsw GReg.
5682 *
5683 * @param iGReg The general register to store the CRx value in.
5684 * @param enmEffOpSize The operand size.
5685 */
5686IEM_CIMPL_DEF_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5687{
5688 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5689
5690#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5691 uint64_t u64MaskedCr0;
5692 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5693 u64MaskedCr0 = pVCpu->cpum.GstCtx.cr0;
5694 else
5695 u64MaskedCr0 = CPUMGetGuestVmxMaskedCr0(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u);
5696 uint64_t const u64GuestCr0 = u64MaskedCr0;
5697#else
5698 uint64_t const u64GuestCr0 = pVCpu->cpum.GstCtx.cr0;
5699#endif
5700
5701 switch (enmEffOpSize)
5702 {
5703 case IEMMODE_16BIT:
5704 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
5705 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0;
5706 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
5707 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0 | 0xffe0;
5708 else
5709 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0 | 0xfff0;
5710 break;
5711
5712 case IEMMODE_32BIT:
5713 *(uint32_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)u64GuestCr0;
5714 break;
5715
5716 case IEMMODE_64BIT:
5717 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = u64GuestCr0;
5718 break;
5719
5720 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5721 }
5722
5723 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5724 return VINF_SUCCESS;
5725}
5726
5727
5728/**
5729 * Implements smsw mem.
5730 *
5731 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5732 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5733 */
5734IEM_CIMPL_DEF_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5735{
5736 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5737
5738#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5739 uint64_t u64MaskedCr0;
5740 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5741 u64MaskedCr0 = pVCpu->cpum.GstCtx.cr0;
5742 else
5743 u64MaskedCr0 = CPUMGetGuestVmxMaskedCr0(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u);
5744 uint64_t const u64GuestCr0 = u64MaskedCr0;
5745#else
5746 uint64_t const u64GuestCr0 = pVCpu->cpum.GstCtx.cr0;
5747#endif
5748
5749 uint16_t u16Value;
5750 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
5751 u16Value = (uint16_t)u64GuestCr0;
5752 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
5753 u16Value = (uint16_t)u64GuestCr0 | 0xffe0;
5754 else
5755 u16Value = (uint16_t)u64GuestCr0 | 0xfff0;
5756
5757 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, u16Value);
5758 if (rcStrict == VINF_SUCCESS)
5759 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5760 return rcStrict;
5761}
5762
5763
5764/**
5765 * Helper for mapping CR3 and PAE PDPEs for 'mov CRx,GReg'.
5766 */
5767#define IEM_MAP_PAE_PDPES_AT_CR3_RET(a_pVCpu, a_iCrReg, a_uCr3) \
5768 do \
5769 { \
5770 int const rcX = PGMGstMapPaePdpesAtCr3(a_pVCpu, a_uCr3); \
5771 if (RT_SUCCESS(rcX)) \
5772 { /* likely */ } \
5773 else \
5774 { \
5775 /* Either invalid PDPTEs or CR3 second-level translation failed. Raise #GP(0) either way. */ \
5776 Log(("iemCImpl_load_Cr%#x: Trying to load invalid PAE PDPEs\n", a_iCrReg)); \
5777 return iemRaiseGeneralProtectionFault0(a_pVCpu); \
5778 } \
5779 } while (0)
5780
5781
5782/**
5783 * Used to implemented 'mov CRx,GReg' and 'lmsw r/m16'.
5784 *
5785 * @param iCrReg The CRx register to write (valid).
5786 * @param uNewCrX The new value.
5787 * @param enmAccessCrX The instruction that caused the CrX load.
5788 * @param iGReg The general register in case of a 'mov CRx,GReg'
5789 * instruction.
5790 */
5791IEM_CIMPL_DEF_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg)
5792{
5793 VBOXSTRICTRC rcStrict;
5794 int rc;
5795#ifndef VBOX_WITH_NESTED_HWVIRT_SVM
5796 RT_NOREF2(iGReg, enmAccessCrX);
5797#endif
5798
5799 /*
5800 * Try store it.
5801 * Unfortunately, CPUM only does a tiny bit of the work.
5802 */
5803 switch (iCrReg)
5804 {
5805 case 0:
5806 {
5807 /*
5808 * Perform checks.
5809 */
5810 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5811
5812 uint64_t const uOldCrX = pVCpu->cpum.GstCtx.cr0;
5813 uint32_t const fValid = CPUMGetGuestCR0ValidMask();
5814
5815 /* ET is hardcoded on 486 and later. */
5816 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_486)
5817 uNewCrX |= X86_CR0_ET;
5818 /* The 386 and 486 didn't #GP(0) on attempting to set reserved CR0 bits. ET was settable on 386. */
5819 else if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_486)
5820 {
5821 uNewCrX &= fValid;
5822 uNewCrX |= X86_CR0_ET;
5823 }
5824 else
5825 uNewCrX &= X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG | X86_CR0_ET;
5826
5827 /* Check for reserved bits. */
5828 if (uNewCrX & ~(uint64_t)fValid)
5829 {
5830 Log(("Trying to set reserved CR0 bits: NewCR0=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
5831 return iemRaiseGeneralProtectionFault0(pVCpu);
5832 }
5833
5834 /* Check for invalid combinations. */
5835 if ( (uNewCrX & X86_CR0_PG)
5836 && !(uNewCrX & X86_CR0_PE) )
5837 {
5838 Log(("Trying to set CR0.PG without CR0.PE\n"));
5839 return iemRaiseGeneralProtectionFault0(pVCpu);
5840 }
5841
5842 if ( !(uNewCrX & X86_CR0_CD)
5843 && (uNewCrX & X86_CR0_NW) )
5844 {
5845 Log(("Trying to clear CR0.CD while leaving CR0.NW set\n"));
5846 return iemRaiseGeneralProtectionFault0(pVCpu);
5847 }
5848
5849 if ( !(uNewCrX & X86_CR0_PG)
5850 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE))
5851 {
5852 Log(("Trying to clear CR0.PG while leaving CR4.PCID set\n"));
5853 return iemRaiseGeneralProtectionFault0(pVCpu);
5854 }
5855
5856 /* Long mode consistency checks. */
5857 if ( (uNewCrX & X86_CR0_PG)
5858 && !(uOldCrX & X86_CR0_PG)
5859 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME) )
5860 {
5861 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE))
5862 {
5863 Log(("Trying to enabled long mode paging without CR4.PAE set\n"));
5864 return iemRaiseGeneralProtectionFault0(pVCpu);
5865 }
5866 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1Long)
5867 {
5868 Log(("Trying to enabled long mode paging with a long CS descriptor loaded.\n"));
5869 return iemRaiseGeneralProtectionFault0(pVCpu);
5870 }
5871 }
5872
5873 /* Check for bits that must remain set or cleared in VMX operation,
5874 see Intel spec. 23.8 "Restrictions on VMX operation". */
5875 if (IEM_VMX_IS_ROOT_MODE(pVCpu))
5876 {
5877#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5878 uint64_t const uCr0Fixed0 = IEM_VMX_IS_NON_ROOT_MODE(pVCpu) ? iemVmxGetCr0Fixed0(pVCpu) : VMX_V_CR0_FIXED0;
5879#else
5880 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
5881#endif
5882 if ((uNewCrX & uCr0Fixed0) != uCr0Fixed0)
5883 {
5884 Log(("Trying to clear reserved CR0 bits in VMX operation: NewCr0=%#llx MB1=%#llx\n", uNewCrX, uCr0Fixed0));
5885 return iemRaiseGeneralProtectionFault0(pVCpu);
5886 }
5887
5888 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5889 if (uNewCrX & ~uCr0Fixed1)
5890 {
5891 Log(("Trying to set reserved CR0 bits in VMX operation: NewCr0=%#llx MB0=%#llx\n", uNewCrX, uCr0Fixed1));
5892 return iemRaiseGeneralProtectionFault0(pVCpu);
5893 }
5894 }
5895
5896 /*
5897 * SVM nested-guest CR0 write intercepts.
5898 */
5899 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, iCrReg))
5900 {
5901 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5902 IEM_SVM_UPDATE_NRIP(pVCpu);
5903 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR0, enmAccessCrX, iGReg);
5904 }
5905 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5906 {
5907 /* 'lmsw' intercepts regardless of whether the TS/MP bits are actually toggled. */
5908 if ( enmAccessCrX == IEMACCESSCRX_LMSW
5909 || (uNewCrX & ~(X86_CR0_TS | X86_CR0_MP)) != (uOldCrX & ~(X86_CR0_TS | X86_CR0_MP)))
5910 {
5911 Assert(enmAccessCrX != IEMACCESSCRX_CLTS);
5912 Log(("iemCImpl_load_Cr%#x: lmsw or bits other than TS/MP changed: Guest intercept -> #VMEXIT\n", iCrReg));
5913 IEM_SVM_UPDATE_NRIP(pVCpu);
5914 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_CR0_SEL_WRITE, enmAccessCrX, iGReg);
5915 }
5916 }
5917
5918 /*
5919 * Change EFER.LMA if entering or leaving long mode.
5920 */
5921 uint64_t NewEFER = pVCpu->cpum.GstCtx.msrEFER;
5922 if ( (uNewCrX & X86_CR0_PG) != (uOldCrX & X86_CR0_PG)
5923 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME) )
5924 {
5925 if (uNewCrX & X86_CR0_PG)
5926 NewEFER |= MSR_K6_EFER_LMA;
5927 else
5928 NewEFER &= ~MSR_K6_EFER_LMA;
5929
5930 CPUMSetGuestEFER(pVCpu, NewEFER);
5931 Assert(pVCpu->cpum.GstCtx.msrEFER == NewEFER);
5932 }
5933
5934 /*
5935 * Inform PGM.
5936 */
5937 if ( (uNewCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE | X86_CR0_CD | X86_CR0_NW))
5938 != (uOldCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE | X86_CR0_CD | X86_CR0_NW)) )
5939 {
5940 if ( enmAccessCrX != IEMACCESSCRX_MOV_CRX
5941 || !CPUMIsPaePagingEnabled(uNewCrX, pVCpu->cpum.GstCtx.cr4, NewEFER)
5942 || CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
5943 { /* likely */ }
5944 else
5945 IEM_MAP_PAE_PDPES_AT_CR3_RET(pVCpu, iCrReg, pVCpu->cpum.GstCtx.cr3);
5946 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
5947 AssertRCReturn(rc, rc);
5948 /* ignore informational status codes */
5949 }
5950
5951 /*
5952 * Change CR0.
5953 */
5954 CPUMSetGuestCR0(pVCpu, uNewCrX);
5955 Assert(pVCpu->cpum.GstCtx.cr0 == uNewCrX);
5956
5957 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
5958 false /* fForce */);
5959 break;
5960 }
5961
5962 /*
5963 * CR2 can be changed without any restrictions.
5964 */
5965 case 2:
5966 {
5967 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 2))
5968 {
5969 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5970 IEM_SVM_UPDATE_NRIP(pVCpu);
5971 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR2, enmAccessCrX, iGReg);
5972 }
5973 pVCpu->cpum.GstCtx.cr2 = uNewCrX;
5974 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_CR2;
5975 rcStrict = VINF_SUCCESS;
5976 break;
5977 }
5978
5979 /*
5980 * CR3 is relatively simple, although AMD and Intel have different
5981 * accounts of how setting reserved bits are handled. We take intel's
5982 * word for the lower bits and AMD's for the high bits (63:52). The
5983 * lower reserved bits are ignored and left alone; OpenBSD 5.8 relies
5984 * on this.
5985 */
5986 /** @todo Testcase: Setting reserved bits in CR3, especially before
5987 * enabling paging. */
5988 case 3:
5989 {
5990 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5991
5992 /* Bit 63 being clear in the source operand with PCIDE indicates no invalidations are required. */
5993 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE)
5994 && (uNewCrX & RT_BIT_64(63)))
5995 {
5996 /** @todo r=ramshankar: avoiding a TLB flush altogether here causes Windows 10
5997 * SMP(w/o nested-paging) to hang during bootup on Skylake systems, see
5998 * Intel spec. 4.10.4.1 "Operations that Invalidate TLBs and
5999 * Paging-Structure Caches". */
6000 uNewCrX &= ~RT_BIT_64(63);
6001 }
6002
6003 /* Check / mask the value. */
6004#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6005 /* See Intel spec. 27.2.2 "EPT Translation Mechanism" footnote. */
6006 uint64_t const fInvPhysMask = !CPUMIsGuestVmxEptPagingEnabledEx(IEM_GET_CTX(pVCpu))
6007 ? (UINT64_MAX << IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth)
6008 : (~X86_CR3_EPT_PAGE_MASK & X86_PAGE_4K_BASE_MASK);
6009#else
6010 uint64_t const fInvPhysMask = UINT64_C(0xfff0000000000000);
6011#endif
6012 if (uNewCrX & fInvPhysMask)
6013 {
6014 /** @todo Should we raise this only for 64-bit mode like Intel claims? AMD is
6015 * very vague in this area. As mentioned above, need testcase on real
6016 * hardware... Sigh. */
6017 Log(("Trying to load CR3 with invalid high bits set: %#llx\n", uNewCrX));
6018 return iemRaiseGeneralProtectionFault0(pVCpu);
6019 }
6020
6021 uint64_t fValid;
6022 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
6023 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME))
6024 {
6025 /** @todo Redundant? This value has already been validated above. */
6026 fValid = UINT64_C(0x000fffffffffffff);
6027 }
6028 else
6029 fValid = UINT64_C(0xffffffff);
6030 if (uNewCrX & ~fValid)
6031 {
6032 Log(("Automatically clearing reserved MBZ bits in CR3 load: NewCR3=%#llx ClearedBits=%#llx\n",
6033 uNewCrX, uNewCrX & ~fValid));
6034 uNewCrX &= fValid;
6035 }
6036
6037 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 3))
6038 {
6039 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
6040 IEM_SVM_UPDATE_NRIP(pVCpu);
6041 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR3, enmAccessCrX, iGReg);
6042 }
6043
6044 /* Inform PGM. */
6045 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG)
6046 {
6047 if ( !CPUMIsGuestInPAEModeEx(IEM_GET_CTX(pVCpu))
6048 || CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
6049 { /* likely */ }
6050 else
6051 {
6052 Assert(enmAccessCrX == IEMACCESSCRX_MOV_CRX);
6053 IEM_MAP_PAE_PDPES_AT_CR3_RET(pVCpu, iCrReg, uNewCrX);
6054 }
6055 rc = PGMFlushTLB(pVCpu, uNewCrX, !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PGE));
6056 AssertRCReturn(rc, rc);
6057 /* ignore informational status codes */
6058 }
6059
6060 /* Make the change. */
6061 rc = CPUMSetGuestCR3(pVCpu, uNewCrX);
6062 AssertRCSuccessReturn(rc, rc);
6063
6064 rcStrict = VINF_SUCCESS;
6065 break;
6066 }
6067
6068 /*
6069 * CR4 is a bit more tedious as there are bits which cannot be cleared
6070 * under some circumstances and such.
6071 */
6072 case 4:
6073 {
6074 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6075 uint64_t const uOldCrX = pVCpu->cpum.GstCtx.cr4;
6076
6077 /* Reserved bits. */
6078 uint32_t const fValid = CPUMGetGuestCR4ValidMask(pVCpu->CTX_SUFF(pVM));
6079 if (uNewCrX & ~(uint64_t)fValid)
6080 {
6081 Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
6082 return iemRaiseGeneralProtectionFault0(pVCpu);
6083 }
6084
6085 bool const fPcide = !(uOldCrX & X86_CR4_PCIDE) && (uNewCrX & X86_CR4_PCIDE);
6086 bool const fLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
6087
6088 /* PCIDE check. */
6089 if ( fPcide
6090 && ( !fLongMode
6091 || (pVCpu->cpum.GstCtx.cr3 & UINT64_C(0xfff))))
6092 {
6093 Log(("Trying to set PCIDE with invalid PCID or outside long mode. Pcid=%#x\n", (pVCpu->cpum.GstCtx.cr3 & UINT64_C(0xfff))));
6094 return iemRaiseGeneralProtectionFault0(pVCpu);
6095 }
6096
6097 /* PAE check. */
6098 if ( fLongMode
6099 && (uOldCrX & X86_CR4_PAE)
6100 && !(uNewCrX & X86_CR4_PAE))
6101 {
6102 Log(("Trying to set clear CR4.PAE while long mode is active\n"));
6103 return iemRaiseGeneralProtectionFault0(pVCpu);
6104 }
6105
6106 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 4))
6107 {
6108 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
6109 IEM_SVM_UPDATE_NRIP(pVCpu);
6110 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR4, enmAccessCrX, iGReg);
6111 }
6112
6113 /* Check for bits that must remain set or cleared in VMX operation,
6114 see Intel spec. 23.8 "Restrictions on VMX operation". */
6115 if (IEM_VMX_IS_ROOT_MODE(pVCpu))
6116 {
6117 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6118 if ((uNewCrX & uCr4Fixed0) != uCr4Fixed0)
6119 {
6120 Log(("Trying to clear reserved CR4 bits in VMX operation: NewCr4=%#llx MB1=%#llx\n", uNewCrX, uCr4Fixed0));
6121 return iemRaiseGeneralProtectionFault0(pVCpu);
6122 }
6123
6124 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6125 if (uNewCrX & ~uCr4Fixed1)
6126 {
6127 Log(("Trying to set reserved CR4 bits in VMX operation: NewCr4=%#llx MB0=%#llx\n", uNewCrX, uCr4Fixed1));
6128 return iemRaiseGeneralProtectionFault0(pVCpu);
6129 }
6130 }
6131
6132 /*
6133 * Notify PGM.
6134 */
6135 if ((uNewCrX ^ uOldCrX) & (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_PCIDE /* | X86_CR4_SMEP */))
6136 {
6137 if ( !CPUMIsPaePagingEnabled(pVCpu->cpum.GstCtx.cr0, uNewCrX, pVCpu->cpum.GstCtx.msrEFER)
6138 || CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
6139 { /* likely */ }
6140 else
6141 {
6142 Assert(enmAccessCrX == IEMACCESSCRX_MOV_CRX);
6143 IEM_MAP_PAE_PDPES_AT_CR3_RET(pVCpu, iCrReg, pVCpu->cpum.GstCtx.cr3);
6144 }
6145 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
6146 AssertRCReturn(rc, rc);
6147 /* ignore informational status codes */
6148 }
6149
6150 /*
6151 * Change it.
6152 */
6153 rc = CPUMSetGuestCR4(pVCpu, uNewCrX);
6154 AssertRCSuccessReturn(rc, rc);
6155 Assert(pVCpu->cpum.GstCtx.cr4 == uNewCrX);
6156
6157 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
6158 false /* fForce */);
6159 break;
6160 }
6161
6162 /*
6163 * CR8 maps to the APIC TPR.
6164 */
6165 case 8:
6166 {
6167 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
6168 if (uNewCrX & ~(uint64_t)0xf)
6169 {
6170 Log(("Trying to set reserved CR8 bits (%#RX64)\n", uNewCrX));
6171 return iemRaiseGeneralProtectionFault0(pVCpu);
6172 }
6173
6174#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6175 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6176 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_USE_TPR_SHADOW))
6177 {
6178 /*
6179 * If the Mov-to-CR8 doesn't cause a VM-exit, bits 0:3 of the source operand
6180 * is copied to bits 7:4 of the VTPR. Bits 0:3 and bits 31:8 of the VTPR are
6181 * cleared. Following this the processor performs TPR virtualization.
6182 *
6183 * However, we should not perform TPR virtualization immediately here but
6184 * after this instruction has completed.
6185 *
6186 * See Intel spec. 29.3 "Virtualizing CR8-based TPR Accesses"
6187 * See Intel spec. 27.1 "Architectural State Before A VM-exit"
6188 */
6189 uint32_t const uTpr = (uNewCrX & 0xf) << 4;
6190 Log(("iemCImpl_load_Cr%#x: Virtualizing TPR (%#x) write\n", iCrReg, uTpr));
6191 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
6192 iemVmxVirtApicSetPendingWrite(pVCpu, XAPIC_OFF_TPR);
6193 rcStrict = VINF_SUCCESS;
6194 break;
6195 }
6196#endif
6197
6198#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6199 if (CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
6200 {
6201 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 8))
6202 {
6203 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
6204 IEM_SVM_UPDATE_NRIP(pVCpu);
6205 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR8, enmAccessCrX, iGReg);
6206 }
6207
6208 pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u8VTPR = uNewCrX;
6209 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, IEM_GET_CTX(pVCpu)))
6210 {
6211 rcStrict = VINF_SUCCESS;
6212 break;
6213 }
6214 }
6215#endif
6216 uint8_t const u8Tpr = (uint8_t)uNewCrX << 4;
6217 APICSetTpr(pVCpu, u8Tpr);
6218 rcStrict = VINF_SUCCESS;
6219 break;
6220 }
6221
6222 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
6223 }
6224
6225 /*
6226 * Advance the RIP on success.
6227 */
6228 if (RT_SUCCESS(rcStrict))
6229 {
6230 if (rcStrict != VINF_SUCCESS)
6231 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6232 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6233 }
6234
6235 return rcStrict;
6236}
6237
6238
6239/**
6240 * Implements mov CRx,GReg.
6241 *
6242 * @param iCrReg The CRx register to write (valid).
6243 * @param iGReg The general register to load the CRx value from.
6244 */
6245IEM_CIMPL_DEF_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg)
6246{
6247 if (pVCpu->iem.s.uCpl != 0)
6248 return iemRaiseGeneralProtectionFault0(pVCpu);
6249 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6250
6251 /*
6252 * Read the new value from the source register and call common worker.
6253 */
6254 uint64_t uNewCrX;
6255 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6256 uNewCrX = iemGRegFetchU64(pVCpu, iGReg);
6257 else
6258 uNewCrX = iemGRegFetchU32(pVCpu, iGReg);
6259
6260#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6261 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6262 {
6263 VBOXSTRICTRC rcStrict = VINF_VMX_INTERCEPT_NOT_ACTIVE;
6264 switch (iCrReg)
6265 {
6266 case 0:
6267 case 4: rcStrict = iemVmxVmexitInstrMovToCr0Cr4(pVCpu, iCrReg, &uNewCrX, iGReg, cbInstr); break;
6268 case 3: rcStrict = iemVmxVmexitInstrMovToCr3(pVCpu, uNewCrX, iGReg, cbInstr); break;
6269 case 8: rcStrict = iemVmxVmexitInstrMovToCr8(pVCpu, iGReg, cbInstr); break;
6270 }
6271 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6272 return rcStrict;
6273 }
6274#endif
6275
6276 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, iCrReg, uNewCrX, IEMACCESSCRX_MOV_CRX, iGReg);
6277}
6278
6279
6280/**
6281 * Implements 'LMSW r/m16'
6282 *
6283 * @param u16NewMsw The new value.
6284 * @param GCPtrEffDst The guest-linear address of the source operand in case
6285 * of a memory operand. For register operand, pass
6286 * NIL_RTGCPTR.
6287 */
6288IEM_CIMPL_DEF_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst)
6289{
6290 if (pVCpu->iem.s.uCpl != 0)
6291 return iemRaiseGeneralProtectionFault0(pVCpu);
6292 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6293 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6294
6295#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6296 /* Check nested-guest VMX intercept and get updated MSW if there's no VM-exit. */
6297 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6298 {
6299 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrLmsw(pVCpu, pVCpu->cpum.GstCtx.cr0, &u16NewMsw, GCPtrEffDst, cbInstr);
6300 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6301 return rcStrict;
6302 }
6303#else
6304 RT_NOREF_PV(GCPtrEffDst);
6305#endif
6306
6307 /*
6308 * Compose the new CR0 value and call common worker.
6309 */
6310 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
6311 uNewCr0 |= u16NewMsw & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
6312 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_LMSW, UINT8_MAX /* iGReg */);
6313}
6314
6315
6316/**
6317 * Implements 'CLTS'.
6318 */
6319IEM_CIMPL_DEF_0(iemCImpl_clts)
6320{
6321 if (pVCpu->iem.s.uCpl != 0)
6322 return iemRaiseGeneralProtectionFault0(pVCpu);
6323
6324 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6325 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0;
6326 uNewCr0 &= ~X86_CR0_TS;
6327
6328#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6329 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6330 {
6331 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrClts(pVCpu, cbInstr);
6332 if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
6333 uNewCr0 |= (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS);
6334 else if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6335 return rcStrict;
6336 }
6337#endif
6338
6339 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_CLTS, UINT8_MAX /* iGReg */);
6340}
6341
6342
6343/**
6344 * Implements mov GReg,DRx.
6345 *
6346 * @param iGReg The general register to store the DRx value in.
6347 * @param iDrReg The DRx register to read (0-7).
6348 */
6349IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg)
6350{
6351#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6352 /*
6353 * Check nested-guest VMX intercept.
6354 * Unlike most other intercepts, the Mov DRx intercept takes preceedence
6355 * over CPL and CR4.DE and even DR4/DR5 checks.
6356 *
6357 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
6358 */
6359 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6360 {
6361 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovDrX(pVCpu, VMXINSTRID_MOV_FROM_DRX, iDrReg, iGReg, cbInstr);
6362 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6363 return rcStrict;
6364 }
6365#endif
6366
6367 /*
6368 * Check preconditions.
6369 */
6370 /* Raise GPs. */
6371 if (pVCpu->iem.s.uCpl != 0)
6372 return iemRaiseGeneralProtectionFault0(pVCpu);
6373 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6374 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR0);
6375
6376 if ( (iDrReg == 4 || iDrReg == 5)
6377 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE) )
6378 {
6379 Log(("mov r%u,dr%u: CR4.DE=1 -> #GP(0)\n", iGReg, iDrReg));
6380 return iemRaiseGeneralProtectionFault0(pVCpu);
6381 }
6382
6383 /* Raise #DB if general access detect is enabled. */
6384 if (pVCpu->cpum.GstCtx.dr[7] & X86_DR7_GD)
6385 {
6386 Log(("mov r%u,dr%u: DR7.GD=1 -> #DB\n", iGReg, iDrReg));
6387 return iemRaiseDebugException(pVCpu);
6388 }
6389
6390 /*
6391 * Read the debug register and store it in the specified general register.
6392 */
6393 uint64_t drX;
6394 switch (iDrReg)
6395 {
6396 case 0:
6397 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6398 drX = pVCpu->cpum.GstCtx.dr[0];
6399 break;
6400 case 1:
6401 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6402 drX = pVCpu->cpum.GstCtx.dr[1];
6403 break;
6404 case 2:
6405 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6406 drX = pVCpu->cpum.GstCtx.dr[2];
6407 break;
6408 case 3:
6409 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6410 drX = pVCpu->cpum.GstCtx.dr[3];
6411 break;
6412 case 6:
6413 case 4:
6414 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
6415 drX = pVCpu->cpum.GstCtx.dr[6];
6416 drX |= X86_DR6_RA1_MASK;
6417 drX &= ~X86_DR6_RAZ_MASK;
6418 break;
6419 case 7:
6420 case 5:
6421 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7);
6422 drX = pVCpu->cpum.GstCtx.dr[7];
6423 drX |=X86_DR7_RA1_MASK;
6424 drX &= ~X86_DR7_RAZ_MASK;
6425 break;
6426 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
6427 }
6428
6429 /** @todo SVM nested-guest intercept for DR8-DR15? */
6430 /*
6431 * Check for any SVM nested-guest intercepts for the DRx read.
6432 */
6433 if (IEM_SVM_IS_READ_DR_INTERCEPT_SET(pVCpu, iDrReg))
6434 {
6435 Log(("mov r%u,dr%u: Guest intercept -> #VMEXIT\n", iGReg, iDrReg));
6436 IEM_SVM_UPDATE_NRIP(pVCpu);
6437 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_READ_DR0 + (iDrReg & 0xf),
6438 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
6439 }
6440
6441 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6442 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = drX;
6443 else
6444 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)drX;
6445
6446 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6447 return VINF_SUCCESS;
6448}
6449
6450
6451/**
6452 * Implements mov DRx,GReg.
6453 *
6454 * @param iDrReg The DRx register to write (valid).
6455 * @param iGReg The general register to load the DRx value from.
6456 */
6457IEM_CIMPL_DEF_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg)
6458{
6459#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6460 /*
6461 * Check nested-guest VMX intercept.
6462 * Unlike most other intercepts, the Mov DRx intercept takes preceedence
6463 * over CPL and CR4.DE and even DR4/DR5 checks.
6464 *
6465 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
6466 */
6467 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6468 {
6469 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovDrX(pVCpu, VMXINSTRID_MOV_TO_DRX, iDrReg, iGReg, cbInstr);
6470 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6471 return rcStrict;
6472 }
6473#endif
6474
6475 /*
6476 * Check preconditions.
6477 */
6478 if (pVCpu->iem.s.uCpl != 0)
6479 return iemRaiseGeneralProtectionFault0(pVCpu);
6480 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6481 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR4);
6482
6483 if (iDrReg == 4 || iDrReg == 5)
6484 {
6485 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)
6486 {
6487 Log(("mov dr%u,r%u: CR4.DE=1 -> #GP(0)\n", iDrReg, iGReg));
6488 return iemRaiseGeneralProtectionFault0(pVCpu);
6489 }
6490 iDrReg += 2;
6491 }
6492
6493 /* Raise #DB if general access detect is enabled. */
6494 /** @todo is \#DB/DR7.GD raised before any reserved high bits in DR7/DR6
6495 * \#GP? */
6496 if (pVCpu->cpum.GstCtx.dr[7] & X86_DR7_GD)
6497 {
6498 Log(("mov dr%u,r%u: DR7.GD=1 -> #DB\n", iDrReg, iGReg));
6499 return iemRaiseDebugException(pVCpu);
6500 }
6501
6502 /*
6503 * Read the new value from the source register.
6504 */
6505 uint64_t uNewDrX;
6506 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6507 uNewDrX = iemGRegFetchU64(pVCpu, iGReg);
6508 else
6509 uNewDrX = iemGRegFetchU32(pVCpu, iGReg);
6510
6511 /*
6512 * Adjust it.
6513 */
6514 switch (iDrReg)
6515 {
6516 case 0:
6517 case 1:
6518 case 2:
6519 case 3:
6520 /* nothing to adjust */
6521 break;
6522
6523 case 6:
6524 if (uNewDrX & X86_DR6_MBZ_MASK)
6525 {
6526 Log(("mov dr%u,%#llx: DR6 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
6527 return iemRaiseGeneralProtectionFault0(pVCpu);
6528 }
6529 uNewDrX |= X86_DR6_RA1_MASK;
6530 uNewDrX &= ~X86_DR6_RAZ_MASK;
6531 break;
6532
6533 case 7:
6534 if (uNewDrX & X86_DR7_MBZ_MASK)
6535 {
6536 Log(("mov dr%u,%#llx: DR7 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
6537 return iemRaiseGeneralProtectionFault0(pVCpu);
6538 }
6539 uNewDrX |= X86_DR7_RA1_MASK;
6540 uNewDrX &= ~X86_DR7_RAZ_MASK;
6541 break;
6542
6543 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6544 }
6545
6546 /** @todo SVM nested-guest intercept for DR8-DR15? */
6547 /*
6548 * Check for any SVM nested-guest intercepts for the DRx write.
6549 */
6550 if (IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(pVCpu, iDrReg))
6551 {
6552 Log2(("mov dr%u,r%u: Guest intercept -> #VMEXIT\n", iDrReg, iGReg));
6553 IEM_SVM_UPDATE_NRIP(pVCpu);
6554 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_DR0 + (iDrReg & 0xf),
6555 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
6556 }
6557
6558 /*
6559 * Do the actual setting.
6560 */
6561 if (iDrReg < 4)
6562 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6563 else if (iDrReg == 6)
6564 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
6565
6566 int rc = CPUMSetGuestDRx(pVCpu, iDrReg, uNewDrX);
6567 AssertRCSuccessReturn(rc, RT_SUCCESS_NP(rc) ? VERR_IEM_IPE_1 : rc);
6568
6569 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6570 return VINF_SUCCESS;
6571}
6572
6573
6574/**
6575 * Implements mov GReg,TRx.
6576 *
6577 * @param iGReg The general register to store the
6578 * TRx value in.
6579 * @param iTrReg The TRx register to read (6/7).
6580 */
6581IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg)
6582{
6583 /*
6584 * Check preconditions. NB: This instruction is 386/486 only.
6585 */
6586
6587 /* Raise GPs. */
6588 if (pVCpu->iem.s.uCpl != 0)
6589 return iemRaiseGeneralProtectionFault0(pVCpu);
6590 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6591
6592 if (iTrReg < 6 || iTrReg > 7)
6593 {
6594 /** @todo Do Intel CPUs reject this or are the TRs aliased? */
6595 Log(("mov r%u,tr%u: invalid register -> #GP(0)\n", iGReg, iTrReg));
6596 return iemRaiseGeneralProtectionFault0(pVCpu);
6597 }
6598
6599 /*
6600 * Read the test register and store it in the specified general register.
6601 * This is currently a dummy implementation that only exists to satisfy
6602 * old debuggers like WDEB386 or OS/2 KDB which unconditionally read the
6603 * TR6/TR7 registers. Software which actually depends on the TR values
6604 * (different on 386/486) is exceedingly rare.
6605 */
6606 uint64_t trX;
6607 switch (iTrReg)
6608 {
6609 case 6:
6610 trX = 0; /* Currently a dummy. */
6611 break;
6612 case 7:
6613 trX = 0; /* Currently a dummy. */
6614 break;
6615 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
6616 }
6617
6618 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)trX;
6619
6620 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6621 return VINF_SUCCESS;
6622}
6623
6624
6625/**
6626 * Implements mov TRx,GReg.
6627 *
6628 * @param iTrReg The TRx register to write (valid).
6629 * @param iGReg The general register to load the TRx
6630 * value from.
6631 */
6632IEM_CIMPL_DEF_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg)
6633{
6634 /*
6635 * Check preconditions. NB: This instruction is 386/486 only.
6636 */
6637
6638 /* Raise GPs. */
6639 if (pVCpu->iem.s.uCpl != 0)
6640 return iemRaiseGeneralProtectionFault0(pVCpu);
6641 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6642
6643 if (iTrReg < 6 || iTrReg > 7)
6644 {
6645 /** @todo Do Intel CPUs reject this or are the TRs aliased? */
6646 Log(("mov r%u,tr%u: invalid register -> #GP(0)\n", iGReg, iTrReg));
6647 return iemRaiseGeneralProtectionFault0(pVCpu);
6648 }
6649
6650 /*
6651 * Read the new value from the source register.
6652 */
6653 uint64_t uNewTrX;
6654 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6655 uNewTrX = iemGRegFetchU64(pVCpu, iGReg);
6656 else
6657 uNewTrX = iemGRegFetchU32(pVCpu, iGReg);
6658
6659 /*
6660 * Here we would do the actual setting if this weren't a dummy implementation.
6661 * This is currently a dummy implementation that only exists to prevent
6662 * old debuggers like WDEB386 or OS/2 KDB from crashing.
6663 */
6664 RT_NOREF(uNewTrX);
6665
6666 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6667 return VINF_SUCCESS;
6668}
6669
6670
6671/**
6672 * Implements 'INVLPG m'.
6673 *
6674 * @param GCPtrPage The effective address of the page to invalidate.
6675 * @remarks Updates the RIP.
6676 */
6677IEM_CIMPL_DEF_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage)
6678{
6679 /* ring-0 only. */
6680 if (pVCpu->iem.s.uCpl != 0)
6681 return iemRaiseGeneralProtectionFault0(pVCpu);
6682 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6683 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
6684
6685#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6686 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6687 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INVLPG_EXIT))
6688 {
6689 Log(("invlpg: Guest intercept (%RGp) -> VM-exit\n", GCPtrPage));
6690 return iemVmxVmexitInstrInvlpg(pVCpu, GCPtrPage, cbInstr);
6691 }
6692#endif
6693
6694 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPG))
6695 {
6696 Log(("invlpg: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
6697 IEM_SVM_UPDATE_NRIP(pVCpu);
6698 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_INVLPG,
6699 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? GCPtrPage : 0, 0 /* uExitInfo2 */);
6700 }
6701
6702 int rc = PGMInvalidatePage(pVCpu, GCPtrPage);
6703 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6704
6705 if (rc == VINF_SUCCESS)
6706 return VINF_SUCCESS;
6707 if (rc == VINF_PGM_SYNC_CR3)
6708 return iemSetPassUpStatus(pVCpu, rc);
6709
6710 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || RT_FAILURE_NP(rc), ("%Rrc\n", rc));
6711 Log(("PGMInvalidatePage(%RGv) -> %Rrc\n", GCPtrPage, rc));
6712 return rc;
6713}
6714
6715
6716/**
6717 * Implements INVPCID.
6718 *
6719 * @param iEffSeg The segment of the invpcid descriptor.
6720 * @param GCPtrInvpcidDesc The address of invpcid descriptor.
6721 * @param uInvpcidType The invalidation type.
6722 * @remarks Updates the RIP.
6723 */
6724IEM_CIMPL_DEF_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType)
6725{
6726 /*
6727 * Check preconditions.
6728 */
6729 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fInvpcid)
6730 return iemRaiseUndefinedOpcode(pVCpu);
6731
6732 /* When in VMX non-root mode and INVPCID is not enabled, it results in #UD. */
6733 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6734 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_INVPCID))
6735 {
6736 Log(("invpcid: Not enabled for nested-guest execution -> #UD\n"));
6737 return iemRaiseUndefinedOpcode(pVCpu);
6738 }
6739
6740 if (pVCpu->iem.s.uCpl != 0)
6741 {
6742 Log(("invpcid: CPL != 0 -> #GP(0)\n"));
6743 return iemRaiseGeneralProtectionFault0(pVCpu);
6744 }
6745
6746 if (IEM_IS_V86_MODE(pVCpu))
6747 {
6748 Log(("invpcid: v8086 mode -> #GP(0)\n"));
6749 return iemRaiseGeneralProtectionFault0(pVCpu);
6750 }
6751
6752 /*
6753 * Check nested-guest intercept.
6754 *
6755 * INVPCID causes a VM-exit if "enable INVPCID" and "INVLPG exiting" are
6756 * both set. We have already checked the former earlier in this function.
6757 *
6758 * CPL and virtual-8086 mode checks take priority over this VM-exit.
6759 * See Intel spec. "25.1.1 Relative Priority of Faults and VM Exits".
6760 */
6761 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6762 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INVLPG_EXIT))
6763 {
6764 Log(("invpcid: Guest intercept -> #VM-exit\n"));
6765 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_INVPCID, VMXINSTRID_NONE, cbInstr);
6766 }
6767
6768 if (uInvpcidType > X86_INVPCID_TYPE_MAX_VALID)
6769 {
6770 Log(("invpcid: invalid/unrecognized invpcid type %#RX64 -> #GP(0)\n", uInvpcidType));
6771 return iemRaiseGeneralProtectionFault0(pVCpu);
6772 }
6773 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
6774
6775 /*
6776 * Fetch the invpcid descriptor from guest memory.
6777 */
6778 RTUINT128U uDesc;
6779 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvpcidDesc);
6780 if (rcStrict == VINF_SUCCESS)
6781 {
6782 /*
6783 * Validate the descriptor.
6784 */
6785 if (uDesc.s.Lo > 0xfff)
6786 {
6787 Log(("invpcid: reserved bits set in invpcid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
6788 return iemRaiseGeneralProtectionFault0(pVCpu);
6789 }
6790
6791 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
6792 uint8_t const uPcid = uDesc.s.Lo & UINT64_C(0xfff);
6793 uint32_t const uCr4 = pVCpu->cpum.GstCtx.cr4;
6794 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
6795 switch (uInvpcidType)
6796 {
6797 case X86_INVPCID_TYPE_INDV_ADDR:
6798 {
6799 if (!IEM_IS_CANONICAL(GCPtrInvAddr))
6800 {
6801 Log(("invpcid: invalidation address %#RGP is not canonical -> #GP(0)\n", GCPtrInvAddr));
6802 return iemRaiseGeneralProtectionFault0(pVCpu);
6803 }
6804 if ( !(uCr4 & X86_CR4_PCIDE)
6805 && uPcid != 0)
6806 {
6807 Log(("invpcid: invalid pcid %#x\n", uPcid));
6808 return iemRaiseGeneralProtectionFault0(pVCpu);
6809 }
6810
6811 /* Invalidate mappings for the linear address tagged with PCID except global translations. */
6812 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6813 break;
6814 }
6815
6816 case X86_INVPCID_TYPE_SINGLE_CONTEXT:
6817 {
6818 if ( !(uCr4 & X86_CR4_PCIDE)
6819 && uPcid != 0)
6820 {
6821 Log(("invpcid: invalid pcid %#x\n", uPcid));
6822 return iemRaiseGeneralProtectionFault0(pVCpu);
6823 }
6824 /* Invalidate all mappings associated with PCID except global translations. */
6825 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6826 break;
6827 }
6828
6829 case X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL:
6830 {
6831 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
6832 break;
6833 }
6834
6835 case X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL:
6836 {
6837 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6838 break;
6839 }
6840 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6841 }
6842 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6843 }
6844 return rcStrict;
6845}
6846
6847
6848/**
6849 * Implements INVD.
6850 */
6851IEM_CIMPL_DEF_0(iemCImpl_invd)
6852{
6853 if (pVCpu->iem.s.uCpl != 0)
6854 {
6855 Log(("invd: CPL != 0 -> #GP(0)\n"));
6856 return iemRaiseGeneralProtectionFault0(pVCpu);
6857 }
6858
6859 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6860 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_INVD, cbInstr);
6861
6862 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_INVD, SVM_EXIT_INVD, 0, 0);
6863
6864 /* We currently take no action here. */
6865 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6866 return VINF_SUCCESS;
6867}
6868
6869
6870/**
6871 * Implements WBINVD.
6872 */
6873IEM_CIMPL_DEF_0(iemCImpl_wbinvd)
6874{
6875 if (pVCpu->iem.s.uCpl != 0)
6876 {
6877 Log(("wbinvd: CPL != 0 -> #GP(0)\n"));
6878 return iemRaiseGeneralProtectionFault0(pVCpu);
6879 }
6880
6881 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6882 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_WBINVD, cbInstr);
6883
6884 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_WBINVD, SVM_EXIT_WBINVD, 0, 0);
6885
6886 /* We currently take no action here. */
6887 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6888 return VINF_SUCCESS;
6889}
6890
6891
6892/** Opcode 0x0f 0xaa. */
6893IEM_CIMPL_DEF_0(iemCImpl_rsm)
6894{
6895 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_RSM, SVM_EXIT_RSM, 0, 0);
6896 NOREF(cbInstr);
6897 return iemRaiseUndefinedOpcode(pVCpu);
6898}
6899
6900
6901/**
6902 * Implements RDTSC.
6903 */
6904IEM_CIMPL_DEF_0(iemCImpl_rdtsc)
6905{
6906 /*
6907 * Check preconditions.
6908 */
6909 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTsc)
6910 return iemRaiseUndefinedOpcode(pVCpu);
6911
6912 if (pVCpu->iem.s.uCpl != 0)
6913 {
6914 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6915 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
6916 {
6917 Log(("rdtsc: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6918 return iemRaiseGeneralProtectionFault0(pVCpu);
6919 }
6920 }
6921
6922 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6923 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDTSC_EXIT))
6924 {
6925 Log(("rdtsc: Guest intercept -> VM-exit\n"));
6926 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDTSC, cbInstr);
6927 }
6928
6929 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSC))
6930 {
6931 Log(("rdtsc: Guest intercept -> #VMEXIT\n"));
6932 IEM_SVM_UPDATE_NRIP(pVCpu);
6933 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6934 }
6935
6936 /*
6937 * Do the job.
6938 */
6939 uint64_t uTicks = TMCpuTickGet(pVCpu);
6940#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
6941 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
6942#endif
6943 pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
6944 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
6945 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX); /* For IEMExecDecodedRdtsc. */
6946 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6947 return VINF_SUCCESS;
6948}
6949
6950
6951/**
6952 * Implements RDTSC.
6953 */
6954IEM_CIMPL_DEF_0(iemCImpl_rdtscp)
6955{
6956 /*
6957 * Check preconditions.
6958 */
6959 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdTscP)
6960 return iemRaiseUndefinedOpcode(pVCpu);
6961
6962 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6963 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_RDTSCP))
6964 {
6965 Log(("rdtscp: Not enabled for VMX non-root mode -> #UD\n"));
6966 return iemRaiseUndefinedOpcode(pVCpu);
6967 }
6968
6969 if (pVCpu->iem.s.uCpl != 0)
6970 {
6971 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6972 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
6973 {
6974 Log(("rdtscp: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6975 return iemRaiseGeneralProtectionFault0(pVCpu);
6976 }
6977 }
6978
6979 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6980 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDTSC_EXIT))
6981 {
6982 Log(("rdtscp: Guest intercept -> VM-exit\n"));
6983 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDTSCP, cbInstr);
6984 }
6985 else if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSCP))
6986 {
6987 Log(("rdtscp: Guest intercept -> #VMEXIT\n"));
6988 IEM_SVM_UPDATE_NRIP(pVCpu);
6989 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSCP, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6990 }
6991
6992 /*
6993 * Do the job.
6994 * Query the MSR first in case of trips to ring-3.
6995 */
6996 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TSC_AUX);
6997 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pVCpu->cpum.GstCtx.rcx);
6998 if (rcStrict == VINF_SUCCESS)
6999 {
7000 /* Low dword of the TSC_AUX msr only. */
7001 pVCpu->cpum.GstCtx.rcx &= UINT32_C(0xffffffff);
7002
7003 uint64_t uTicks = TMCpuTickGet(pVCpu);
7004#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
7005 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
7006#endif
7007 pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
7008 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
7009 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RCX); /* For IEMExecDecodedRdtscp. */
7010 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7011 }
7012 return rcStrict;
7013}
7014
7015
7016/**
7017 * Implements RDPMC.
7018 */
7019IEM_CIMPL_DEF_0(iemCImpl_rdpmc)
7020{
7021 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
7022
7023 if ( pVCpu->iem.s.uCpl != 0
7024 && !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCE))
7025 return iemRaiseGeneralProtectionFault0(pVCpu);
7026
7027 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7028 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDPMC_EXIT))
7029 {
7030 Log(("rdpmc: Guest intercept -> VM-exit\n"));
7031 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDPMC, cbInstr);
7032 }
7033
7034 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDPMC))
7035 {
7036 Log(("rdpmc: Guest intercept -> #VMEXIT\n"));
7037 IEM_SVM_UPDATE_NRIP(pVCpu);
7038 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDPMC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7039 }
7040
7041 /** @todo Emulate performance counters, for now just return 0. */
7042 pVCpu->cpum.GstCtx.rax = 0;
7043 pVCpu->cpum.GstCtx.rdx = 0;
7044 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
7045 /** @todo We should trigger a \#GP here if the CPU doesn't support the index in
7046 * ecx but see @bugref{3472}! */
7047
7048 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7049 return VINF_SUCCESS;
7050}
7051
7052
7053/**
7054 * Implements RDMSR.
7055 */
7056IEM_CIMPL_DEF_0(iemCImpl_rdmsr)
7057{
7058 /*
7059 * Check preconditions.
7060 */
7061 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
7062 return iemRaiseUndefinedOpcode(pVCpu);
7063 if (pVCpu->iem.s.uCpl != 0)
7064 return iemRaiseGeneralProtectionFault0(pVCpu);
7065
7066 /*
7067 * Check nested-guest intercepts.
7068 */
7069#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7070 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7071 {
7072 if (iemVmxIsRdmsrWrmsrInterceptSet(pVCpu, VMX_EXIT_RDMSR, pVCpu->cpum.GstCtx.ecx))
7073 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDMSR, cbInstr);
7074 }
7075#endif
7076
7077#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7078 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
7079 {
7080 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, pVCpu->cpum.GstCtx.ecx, false /* fWrite */);
7081 if (rcStrict == VINF_SVM_VMEXIT)
7082 return VINF_SUCCESS;
7083 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7084 {
7085 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", pVCpu->cpum.GstCtx.ecx, VBOXSTRICTRC_VAL(rcStrict)));
7086 return rcStrict;
7087 }
7088 }
7089#endif
7090
7091 /*
7092 * Do the job.
7093 */
7094 RTUINT64U uValue;
7095 /** @todo make CPUMAllMsrs.cpp import the necessary MSR state. */
7096 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
7097
7098 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pVCpu->cpum.GstCtx.ecx, &uValue.u);
7099 if (rcStrict == VINF_SUCCESS)
7100 {
7101 pVCpu->cpum.GstCtx.rax = uValue.s.Lo;
7102 pVCpu->cpum.GstCtx.rdx = uValue.s.Hi;
7103 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
7104
7105 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7106 return VINF_SUCCESS;
7107 }
7108
7109#ifndef IN_RING3
7110 /* Deferred to ring-3. */
7111 if (rcStrict == VINF_CPUM_R3_MSR_READ)
7112 {
7113 Log(("IEM: rdmsr(%#x) -> ring-3\n", pVCpu->cpum.GstCtx.ecx));
7114 return rcStrict;
7115 }
7116#endif
7117
7118 /* Often a unimplemented MSR or MSR bit, so worth logging. */
7119 if (pVCpu->iem.s.cLogRelRdMsr < 32)
7120 {
7121 pVCpu->iem.s.cLogRelRdMsr++;
7122 LogRel(("IEM: rdmsr(%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx));
7123 }
7124 else
7125 Log(( "IEM: rdmsr(%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx));
7126 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
7127 return iemRaiseGeneralProtectionFault0(pVCpu);
7128}
7129
7130
7131/**
7132 * Implements WRMSR.
7133 */
7134IEM_CIMPL_DEF_0(iemCImpl_wrmsr)
7135{
7136 /*
7137 * Check preconditions.
7138 */
7139 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
7140 return iemRaiseUndefinedOpcode(pVCpu);
7141 if (pVCpu->iem.s.uCpl != 0)
7142 return iemRaiseGeneralProtectionFault0(pVCpu);
7143
7144 RTUINT64U uValue;
7145 uValue.s.Lo = pVCpu->cpum.GstCtx.eax;
7146 uValue.s.Hi = pVCpu->cpum.GstCtx.edx;
7147
7148 uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
7149
7150 /** @todo make CPUMAllMsrs.cpp import the necessary MSR state. */
7151 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
7152
7153 /*
7154 * Check nested-guest intercepts.
7155 */
7156#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7157 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7158 {
7159 if (iemVmxIsRdmsrWrmsrInterceptSet(pVCpu, VMX_EXIT_WRMSR, idMsr))
7160 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_WRMSR, cbInstr);
7161 }
7162#endif
7163
7164#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7165 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
7166 {
7167 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, idMsr, true /* fWrite */);
7168 if (rcStrict == VINF_SVM_VMEXIT)
7169 return VINF_SUCCESS;
7170 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7171 {
7172 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", idMsr, VBOXSTRICTRC_VAL(rcStrict)));
7173 return rcStrict;
7174 }
7175 }
7176#endif
7177
7178 /*
7179 * Do the job.
7180 */
7181 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, idMsr, uValue.u);
7182 if (rcStrict == VINF_SUCCESS)
7183 {
7184 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7185 return VINF_SUCCESS;
7186 }
7187
7188#ifndef IN_RING3
7189 /* Deferred to ring-3. */
7190 if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
7191 {
7192 Log(("IEM: wrmsr(%#x) -> ring-3\n", idMsr));
7193 return rcStrict;
7194 }
7195#endif
7196
7197 /* Often a unimplemented MSR or MSR bit, so worth logging. */
7198 if (pVCpu->iem.s.cLogRelWrMsr < 32)
7199 {
7200 pVCpu->iem.s.cLogRelWrMsr++;
7201 LogRel(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", idMsr, uValue.s.Hi, uValue.s.Lo));
7202 }
7203 else
7204 Log(( "IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", idMsr, uValue.s.Hi, uValue.s.Lo));
7205 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
7206 return iemRaiseGeneralProtectionFault0(pVCpu);
7207}
7208
7209
7210/**
7211 * Implements 'IN eAX, port'.
7212 *
7213 * @param u16Port The source port.
7214 * @param fImm Whether the port was specified through an immediate operand
7215 * or the implicit DX register.
7216 * @param cbReg The register size.
7217 */
7218IEM_CIMPL_DEF_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg)
7219{
7220 /*
7221 * CPL check
7222 */
7223 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, u16Port, cbReg);
7224 if (rcStrict != VINF_SUCCESS)
7225 return rcStrict;
7226
7227 /*
7228 * Check VMX nested-guest IO intercept.
7229 */
7230#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7231 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7232 {
7233 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_IN, u16Port, fImm, cbReg, cbInstr);
7234 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
7235 return rcStrict;
7236 }
7237#else
7238 RT_NOREF(fImm);
7239#endif
7240
7241 /*
7242 * Check SVM nested-guest IO intercept.
7243 */
7244#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7245 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
7246 {
7247 uint8_t cAddrSizeBits;
7248 switch (pVCpu->iem.s.enmEffAddrMode)
7249 {
7250 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
7251 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
7252 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
7253 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7254 }
7255 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_IN, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
7256 false /* fRep */, false /* fStrIo */, cbInstr);
7257 if (rcStrict == VINF_SVM_VMEXIT)
7258 return VINF_SUCCESS;
7259 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7260 {
7261 Log(("iemCImpl_in: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
7262 VBOXSTRICTRC_VAL(rcStrict)));
7263 return rcStrict;
7264 }
7265 }
7266#endif
7267
7268 /*
7269 * Perform the I/O.
7270 */
7271 uint32_t u32Value = 0;
7272 rcStrict = IOMIOPortRead(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, &u32Value, cbReg);
7273 if (IOM_SUCCESS(rcStrict))
7274 {
7275 switch (cbReg)
7276 {
7277 case 1: pVCpu->cpum.GstCtx.al = (uint8_t)u32Value; break;
7278 case 2: pVCpu->cpum.GstCtx.ax = (uint16_t)u32Value; break;
7279 case 4: pVCpu->cpum.GstCtx.rax = u32Value; break;
7280 default: AssertFailedReturn(VERR_IEM_IPE_3);
7281 }
7282 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7283 pVCpu->iem.s.cPotentialExits++;
7284 if (rcStrict != VINF_SUCCESS)
7285 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7286 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
7287
7288 /*
7289 * Check for I/O breakpoints.
7290 */
7291 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
7292 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
7293 && X86_DR7_ANY_RW_IO(uDr7)
7294 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
7295 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
7296 {
7297 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
7298 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
7299 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
7300 rcStrict = iemRaiseDebugException(pVCpu);
7301 }
7302 }
7303
7304 return rcStrict;
7305}
7306
7307
7308/**
7309 * Implements 'IN eAX, DX'.
7310 *
7311 * @param cbReg The register size.
7312 */
7313IEM_CIMPL_DEF_1(iemCImpl_in_eAX_DX, uint8_t, cbReg)
7314{
7315 return IEM_CIMPL_CALL_3(iemCImpl_in, pVCpu->cpum.GstCtx.dx, false /* fImm */, cbReg);
7316}
7317
7318
7319/**
7320 * Implements 'OUT port, eAX'.
7321 *
7322 * @param u16Port The destination port.
7323 * @param fImm Whether the port was specified through an immediate operand
7324 * or the implicit DX register.
7325 * @param cbReg The register size.
7326 */
7327IEM_CIMPL_DEF_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg)
7328{
7329 /*
7330 * CPL check
7331 */
7332 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, u16Port, cbReg);
7333 if (rcStrict != VINF_SUCCESS)
7334 return rcStrict;
7335
7336 /*
7337 * Check VMX nested-guest I/O intercept.
7338 */
7339#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7340 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7341 {
7342 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_OUT, u16Port, fImm, cbReg, cbInstr);
7343 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
7344 return rcStrict;
7345 }
7346#else
7347 RT_NOREF(fImm);
7348#endif
7349
7350 /*
7351 * Check SVM nested-guest I/O intercept.
7352 */
7353#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7354 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
7355 {
7356 uint8_t cAddrSizeBits;
7357 switch (pVCpu->iem.s.enmEffAddrMode)
7358 {
7359 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
7360 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
7361 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
7362 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7363 }
7364 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_OUT, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
7365 false /* fRep */, false /* fStrIo */, cbInstr);
7366 if (rcStrict == VINF_SVM_VMEXIT)
7367 return VINF_SUCCESS;
7368 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7369 {
7370 Log(("iemCImpl_out: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
7371 VBOXSTRICTRC_VAL(rcStrict)));
7372 return rcStrict;
7373 }
7374 }
7375#endif
7376
7377 /*
7378 * Perform the I/O.
7379 */
7380 uint32_t u32Value;
7381 switch (cbReg)
7382 {
7383 case 1: u32Value = pVCpu->cpum.GstCtx.al; break;
7384 case 2: u32Value = pVCpu->cpum.GstCtx.ax; break;
7385 case 4: u32Value = pVCpu->cpum.GstCtx.eax; break;
7386 default: AssertFailedReturn(VERR_IEM_IPE_4);
7387 }
7388 rcStrict = IOMIOPortWrite(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, u32Value, cbReg);
7389 if (IOM_SUCCESS(rcStrict))
7390 {
7391 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7392 pVCpu->iem.s.cPotentialExits++;
7393 if (rcStrict != VINF_SUCCESS)
7394 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7395 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
7396
7397 /*
7398 * Check for I/O breakpoints.
7399 */
7400 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
7401 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
7402 && X86_DR7_ANY_RW_IO(uDr7)
7403 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
7404 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
7405 {
7406 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
7407 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
7408 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
7409 rcStrict = iemRaiseDebugException(pVCpu);
7410 }
7411 }
7412 return rcStrict;
7413}
7414
7415
7416/**
7417 * Implements 'OUT DX, eAX'.
7418 *
7419 * @param cbReg The register size.
7420 */
7421IEM_CIMPL_DEF_1(iemCImpl_out_DX_eAX, uint8_t, cbReg)
7422{
7423 return IEM_CIMPL_CALL_3(iemCImpl_out, pVCpu->cpum.GstCtx.dx, false /* fImm */, cbReg);
7424}
7425
7426
7427/**
7428 * Implements 'CLI'.
7429 */
7430IEM_CIMPL_DEF_0(iemCImpl_cli)
7431{
7432 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
7433 uint32_t const fEflOld = fEfl;
7434
7435 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4);
7436 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
7437 {
7438 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
7439 if (!(fEfl & X86_EFL_VM))
7440 {
7441 if (pVCpu->iem.s.uCpl <= uIopl)
7442 fEfl &= ~X86_EFL_IF;
7443 else if ( pVCpu->iem.s.uCpl == 3
7444 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PVI) )
7445 fEfl &= ~X86_EFL_VIF;
7446 else
7447 return iemRaiseGeneralProtectionFault0(pVCpu);
7448 }
7449 /* V8086 */
7450 else if (uIopl == 3)
7451 fEfl &= ~X86_EFL_IF;
7452 else if ( uIopl < 3
7453 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME) )
7454 fEfl &= ~X86_EFL_VIF;
7455 else
7456 return iemRaiseGeneralProtectionFault0(pVCpu);
7457 }
7458 /* real mode */
7459 else
7460 fEfl &= ~X86_EFL_IF;
7461
7462 /* Commit. */
7463 IEMMISC_SET_EFL(pVCpu, fEfl);
7464 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7465 Log2(("CLI: %#x -> %#x\n", fEflOld, fEfl)); NOREF(fEflOld);
7466 return VINF_SUCCESS;
7467}
7468
7469
7470/**
7471 * Implements 'STI'.
7472 */
7473IEM_CIMPL_DEF_0(iemCImpl_sti)
7474{
7475 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
7476 uint32_t const fEflOld = fEfl;
7477
7478 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4);
7479 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
7480 {
7481 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
7482 if (!(fEfl & X86_EFL_VM))
7483 {
7484 if (pVCpu->iem.s.uCpl <= uIopl)
7485 fEfl |= X86_EFL_IF;
7486 else if ( pVCpu->iem.s.uCpl == 3
7487 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PVI)
7488 && !(fEfl & X86_EFL_VIP) )
7489 fEfl |= X86_EFL_VIF;
7490 else
7491 return iemRaiseGeneralProtectionFault0(pVCpu);
7492 }
7493 /* V8086 */
7494 else if (uIopl == 3)
7495 fEfl |= X86_EFL_IF;
7496 else if ( uIopl < 3
7497 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME)
7498 && !(fEfl & X86_EFL_VIP) )
7499 fEfl |= X86_EFL_VIF;
7500 else
7501 return iemRaiseGeneralProtectionFault0(pVCpu);
7502 }
7503 /* real mode */
7504 else
7505 fEfl |= X86_EFL_IF;
7506
7507 /* Commit. */
7508 IEMMISC_SET_EFL(pVCpu, fEfl);
7509 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7510 if (!(fEflOld & X86_EFL_IF) && (fEfl & X86_EFL_IF))
7511 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
7512 Log2(("STI: %#x -> %#x\n", fEflOld, fEfl));
7513 return VINF_SUCCESS;
7514}
7515
7516
7517/**
7518 * Implements 'HLT'.
7519 */
7520IEM_CIMPL_DEF_0(iemCImpl_hlt)
7521{
7522 if (pVCpu->iem.s.uCpl != 0)
7523 return iemRaiseGeneralProtectionFault0(pVCpu);
7524
7525 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7526 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_HLT_EXIT))
7527 {
7528 Log2(("hlt: Guest intercept -> VM-exit\n"));
7529 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_HLT, cbInstr);
7530 }
7531
7532 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_HLT))
7533 {
7534 Log2(("hlt: Guest intercept -> #VMEXIT\n"));
7535 IEM_SVM_UPDATE_NRIP(pVCpu);
7536 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_HLT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7537 }
7538
7539 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7540 return VINF_EM_HALT;
7541}
7542
7543
7544/**
7545 * Implements 'MONITOR'.
7546 */
7547IEM_CIMPL_DEF_1(iemCImpl_monitor, uint8_t, iEffSeg)
7548{
7549 /*
7550 * Permission checks.
7551 */
7552 if (pVCpu->iem.s.uCpl != 0)
7553 {
7554 Log2(("monitor: CPL != 0\n"));
7555 return iemRaiseUndefinedOpcode(pVCpu); /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. */
7556 }
7557 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
7558 {
7559 Log2(("monitor: Not in CPUID\n"));
7560 return iemRaiseUndefinedOpcode(pVCpu);
7561 }
7562
7563 /*
7564 * Check VMX guest-intercept.
7565 * This should be considered a fault-like VM-exit.
7566 * See Intel spec. 25.1.1 "Relative Priority of Faults and VM Exits".
7567 */
7568 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7569 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_MONITOR_EXIT))
7570 {
7571 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
7572 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_MONITOR, cbInstr);
7573 }
7574
7575 /*
7576 * Gather the operands and validate them.
7577 */
7578 RTGCPTR GCPtrMem = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
7579 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
7580 uint32_t uEdx = pVCpu->cpum.GstCtx.edx;
7581/** @todo Test whether EAX or ECX is processed first, i.e. do we get \#PF or
7582 * \#GP first. */
7583 if (uEcx != 0)
7584 {
7585 Log2(("monitor rax=%RX64, ecx=%RX32, edx=%RX32; ECX != 0 -> #GP(0)\n", GCPtrMem, uEcx, uEdx)); NOREF(uEdx);
7586 return iemRaiseGeneralProtectionFault0(pVCpu);
7587 }
7588
7589 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrMem);
7590 if (rcStrict != VINF_SUCCESS)
7591 return rcStrict;
7592
7593 RTGCPHYS GCPhysMem;
7594 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrMem, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
7595 if (rcStrict != VINF_SUCCESS)
7596 return rcStrict;
7597
7598#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7599 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7600 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
7601 {
7602 /*
7603 * MONITOR does not access the memory, just monitors the address. However,
7604 * if the address falls in the APIC-access page, the address monitored must
7605 * instead be the corresponding address in the virtual-APIC page.
7606 *
7607 * See Intel spec. 29.4.4 "Instruction-Specific Considerations".
7608 */
7609 rcStrict = iemVmxVirtApicAccessUnused(pVCpu, &GCPhysMem, 1, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA);
7610 if ( rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE
7611 && rcStrict != VINF_VMX_MODIFIES_BEHAVIOR)
7612 return rcStrict;
7613 }
7614#endif
7615
7616 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MONITOR))
7617 {
7618 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
7619 IEM_SVM_UPDATE_NRIP(pVCpu);
7620 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MONITOR, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7621 }
7622
7623 /*
7624 * Call EM to prepare the monitor/wait.
7625 */
7626 rcStrict = EMMonitorWaitPrepare(pVCpu, pVCpu->cpum.GstCtx.rax, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.rdx, GCPhysMem);
7627 Assert(rcStrict == VINF_SUCCESS);
7628
7629 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7630 return rcStrict;
7631}
7632
7633
7634/**
7635 * Implements 'MWAIT'.
7636 */
7637IEM_CIMPL_DEF_0(iemCImpl_mwait)
7638{
7639 /*
7640 * Permission checks.
7641 */
7642 if (pVCpu->iem.s.uCpl != 0)
7643 {
7644 Log2(("mwait: CPL != 0\n"));
7645 /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. (Remember to check
7646 * EFLAGS.VM then.) */
7647 return iemRaiseUndefinedOpcode(pVCpu);
7648 }
7649 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
7650 {
7651 Log2(("mwait: Not in CPUID\n"));
7652 return iemRaiseUndefinedOpcode(pVCpu);
7653 }
7654
7655 /* Check VMX nested-guest intercept. */
7656 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7657 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_MWAIT_EXIT))
7658 IEM_VMX_VMEXIT_MWAIT_RET(pVCpu, EMMonitorIsArmed(pVCpu), cbInstr);
7659
7660 /*
7661 * Gather the operands and validate them.
7662 */
7663 uint32_t const uEax = pVCpu->cpum.GstCtx.eax;
7664 uint32_t const uEcx = pVCpu->cpum.GstCtx.ecx;
7665 if (uEcx != 0)
7666 {
7667 /* Only supported extension is break on IRQ when IF=0. */
7668 if (uEcx > 1)
7669 {
7670 Log2(("mwait eax=%RX32, ecx=%RX32; ECX > 1 -> #GP(0)\n", uEax, uEcx));
7671 return iemRaiseGeneralProtectionFault0(pVCpu);
7672 }
7673 uint32_t fMWaitFeatures = 0;
7674 uint32_t uIgnore = 0;
7675 CPUMGetGuestCpuId(pVCpu, 5, 0, -1 /*f64BitMode*/, &uIgnore, &uIgnore, &fMWaitFeatures, &uIgnore);
7676 if ( (fMWaitFeatures & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
7677 != (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
7678 {
7679 Log2(("mwait eax=%RX32, ecx=%RX32; break-on-IRQ-IF=0 extension not enabled -> #GP(0)\n", uEax, uEcx));
7680 return iemRaiseGeneralProtectionFault0(pVCpu);
7681 }
7682
7683#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7684 /*
7685 * If the interrupt-window exiting control is set or a virtual-interrupt is pending
7686 * for delivery; and interrupts are disabled the processor does not enter its
7687 * mwait state but rather passes control to the next instruction.
7688 *
7689 * See Intel spec. 25.3 "Changes to Instruction Behavior In VMX Non-root Operation".
7690 */
7691 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7692 && !pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
7693 {
7694 if ( IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INT_WINDOW_EXIT)
7695 || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
7696 {
7697 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7698 return VINF_SUCCESS;
7699 }
7700 }
7701#endif
7702 }
7703
7704 /*
7705 * Check SVM nested-guest mwait intercepts.
7706 */
7707 if ( IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT_ARMED)
7708 && EMMonitorIsArmed(pVCpu))
7709 {
7710 Log2(("mwait: Guest intercept (monitor hardware armed) -> #VMEXIT\n"));
7711 IEM_SVM_UPDATE_NRIP(pVCpu);
7712 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT_ARMED, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7713 }
7714 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT))
7715 {
7716 Log2(("mwait: Guest intercept -> #VMEXIT\n"));
7717 IEM_SVM_UPDATE_NRIP(pVCpu);
7718 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7719 }
7720
7721 /*
7722 * Call EM to prepare the monitor/wait.
7723 */
7724 VBOXSTRICTRC rcStrict = EMMonitorWaitPerform(pVCpu, uEax, uEcx);
7725
7726 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7727 return rcStrict;
7728}
7729
7730
7731/**
7732 * Implements 'SWAPGS'.
7733 */
7734IEM_CIMPL_DEF_0(iemCImpl_swapgs)
7735{
7736 Assert(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT); /* Caller checks this. */
7737
7738 /*
7739 * Permission checks.
7740 */
7741 if (pVCpu->iem.s.uCpl != 0)
7742 {
7743 Log2(("swapgs: CPL != 0\n"));
7744 return iemRaiseUndefinedOpcode(pVCpu);
7745 }
7746
7747 /*
7748 * Do the job.
7749 */
7750 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_GS);
7751 uint64_t uOtherGsBase = pVCpu->cpum.GstCtx.msrKERNELGSBASE;
7752 pVCpu->cpum.GstCtx.msrKERNELGSBASE = pVCpu->cpum.GstCtx.gs.u64Base;
7753 pVCpu->cpum.GstCtx.gs.u64Base = uOtherGsBase;
7754
7755 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7756 return VINF_SUCCESS;
7757}
7758
7759
7760#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
7761/**
7762 * Handles a CPUID call.
7763 */
7764static VBOXSTRICTRC iemCpuIdVBoxCall(PVMCPUCC pVCpu, uint32_t iFunction,
7765 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
7766{
7767 switch (iFunction)
7768 {
7769 case VBOX_CPUID_FN_ID:
7770 LogFlow(("iemCpuIdVBoxCall: VBOX_CPUID_FN_ID\n"));
7771 *pEax = VBOX_CPUID_RESP_ID_EAX;
7772 *pEbx = VBOX_CPUID_RESP_ID_EBX;
7773 *pEcx = VBOX_CPUID_RESP_ID_ECX;
7774 *pEdx = VBOX_CPUID_RESP_ID_EDX;
7775 break;
7776
7777 case VBOX_CPUID_FN_LOG:
7778 {
7779 CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX | CPUMCTX_EXTRN_RSI
7780 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
7781
7782 /* Validate input. */
7783 uint32_t cchToLog = *pEdx;
7784 if (cchToLog <= _2M)
7785 {
7786 uint32_t const uLogPicker = *pEbx;
7787 if (uLogPicker <= 1)
7788 {
7789 /* Resolve the logger. */
7790 PRTLOGGER const pLogger = !uLogPicker
7791 ? RTLogDefaultInstanceEx(UINT32_MAX) : RTLogRelGetDefaultInstanceEx(UINT32_MAX);
7792 if (pLogger)
7793 {
7794 /* Copy over the data: */
7795 RTGCPTR GCPtrSrc = pVCpu->cpum.GstCtx.rsi;
7796 while (cchToLog > 0)
7797 {
7798 uint32_t cbToMap = GUEST_PAGE_SIZE - (GCPtrSrc & GUEST_PAGE_OFFSET_MASK);
7799 if (cbToMap > cchToLog)
7800 cbToMap = cchToLog;
7801 /** @todo Extend iemMemMap to allowing page size accessing and avoid 7
7802 * unnecessary calls & iterations per pages. */
7803 if (cbToMap > 512)
7804 cbToMap = 512;
7805 void *pvSrc = NULL;
7806 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvSrc, cbToMap, UINT8_MAX, GCPtrSrc, IEM_ACCESS_DATA_R, 0);
7807 if (rcStrict == VINF_SUCCESS)
7808 {
7809 RTLogBulkNestedWrite(pLogger, (const char *)pvSrc, cbToMap, "Gst:");
7810 rcStrict = iemMemCommitAndUnmap(pVCpu, pvSrc, IEM_ACCESS_DATA_R);
7811 AssertRCSuccessReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
7812 }
7813 else
7814 {
7815 Log(("iemCpuIdVBoxCall: %Rrc at %RGp LB %#x\n", VBOXSTRICTRC_VAL(rcStrict), GCPtrSrc, cbToMap));
7816 return rcStrict;
7817 }
7818
7819 /* Advance. */
7820 pVCpu->cpum.GstCtx.rsi = GCPtrSrc += cbToMap;
7821 *pEdx = cchToLog -= cbToMap;
7822 }
7823 *pEax = VINF_SUCCESS;
7824 }
7825 else
7826 *pEax = (uint32_t)VERR_NOT_FOUND;
7827 }
7828 else
7829 *pEax = (uint32_t)VERR_NOT_FOUND;
7830 }
7831 else
7832 *pEax = (uint32_t)VERR_TOO_MUCH_DATA;
7833 *pEdx = VBOX_CPUID_RESP_GEN_EDX;
7834 *pEcx = VBOX_CPUID_RESP_GEN_ECX;
7835 *pEbx = VBOX_CPUID_RESP_GEN_EBX;
7836 break;
7837 }
7838
7839 default:
7840 LogFlow(("iemCpuIdVBoxCall: Invalid function %#x (%#x, %#x)\n", iFunction, *pEbx, *pEdx));
7841 *pEax = (uint32_t)VERR_INVALID_FUNCTION;
7842 *pEbx = (uint32_t)VERR_INVALID_FUNCTION;
7843 *pEcx = (uint32_t)VERR_INVALID_FUNCTION;
7844 *pEdx = (uint32_t)VERR_INVALID_FUNCTION;
7845 break;
7846 }
7847 return VINF_SUCCESS;
7848}
7849#endif /* VBOX_WITHOUT_CPUID_HOST_CALL */
7850
7851/**
7852 * Implements 'CPUID'.
7853 */
7854IEM_CIMPL_DEF_0(iemCImpl_cpuid)
7855{
7856 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7857 {
7858 Log2(("cpuid: Guest intercept -> VM-exit\n"));
7859 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_CPUID, cbInstr);
7860 }
7861
7862 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CPUID))
7863 {
7864 Log2(("cpuid: Guest intercept -> #VMEXIT\n"));
7865 IEM_SVM_UPDATE_NRIP(pVCpu);
7866 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_CPUID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7867 }
7868
7869
7870 uint32_t const uEax = pVCpu->cpum.GstCtx.eax;
7871 uint32_t const uEcx = pVCpu->cpum.GstCtx.ecx;
7872
7873#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
7874 /*
7875 * CPUID host call backdoor.
7876 */
7877 if ( uEax == VBOX_CPUID_REQ_EAX_FIXED
7878 && (uEcx & VBOX_CPUID_REQ_ECX_FIXED_MASK) == VBOX_CPUID_REQ_ECX_FIXED
7879 && pVCpu->CTX_SUFF(pVM)->iem.s.fCpuIdHostCall)
7880 {
7881 VBOXSTRICTRC rcStrict = iemCpuIdVBoxCall(pVCpu, uEcx & VBOX_CPUID_REQ_ECX_FN_MASK,
7882 &pVCpu->cpum.GstCtx.eax, &pVCpu->cpum.GstCtx.ebx,
7883 &pVCpu->cpum.GstCtx.ecx, &pVCpu->cpum.GstCtx.edx);
7884 if (rcStrict != VINF_SUCCESS)
7885 return rcStrict;
7886 }
7887 /*
7888 * Regular CPUID.
7889 */
7890 else
7891#endif
7892 CPUMGetGuestCpuId(pVCpu, uEax, uEcx, pVCpu->cpum.GstCtx.cs.Attr.n.u1Long,
7893 &pVCpu->cpum.GstCtx.eax, &pVCpu->cpum.GstCtx.ebx, &pVCpu->cpum.GstCtx.ecx, &pVCpu->cpum.GstCtx.edx);
7894
7895 pVCpu->cpum.GstCtx.rax &= UINT32_C(0xffffffff);
7896 pVCpu->cpum.GstCtx.rbx &= UINT32_C(0xffffffff);
7897 pVCpu->cpum.GstCtx.rcx &= UINT32_C(0xffffffff);
7898 pVCpu->cpum.GstCtx.rdx &= UINT32_C(0xffffffff);
7899 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX);
7900
7901 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7902 pVCpu->iem.s.cPotentialExits++;
7903 return VINF_SUCCESS;
7904}
7905
7906
7907/**
7908 * Implements 'AAD'.
7909 *
7910 * @param bImm The immediate operand.
7911 */
7912IEM_CIMPL_DEF_1(iemCImpl_aad, uint8_t, bImm)
7913{
7914 uint16_t const ax = pVCpu->cpum.GstCtx.ax;
7915 uint8_t const al = (uint8_t)ax + (uint8_t)(ax >> 8) * bImm;
7916 pVCpu->cpum.GstCtx.ax = al;
7917 iemHlpUpdateArithEFlagsU8(pVCpu, al,
7918 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
7919 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
7920
7921 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7922 return VINF_SUCCESS;
7923}
7924
7925
7926/**
7927 * Implements 'AAM'.
7928 *
7929 * @param bImm The immediate operand. Cannot be 0.
7930 */
7931IEM_CIMPL_DEF_1(iemCImpl_aam, uint8_t, bImm)
7932{
7933 Assert(bImm != 0); /* #DE on 0 is handled in the decoder. */
7934
7935 uint16_t const ax = pVCpu->cpum.GstCtx.ax;
7936 uint8_t const al = (uint8_t)ax % bImm;
7937 uint8_t const ah = (uint8_t)ax / bImm;
7938 pVCpu->cpum.GstCtx.ax = (ah << 8) + al;
7939 iemHlpUpdateArithEFlagsU8(pVCpu, al,
7940 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
7941 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
7942
7943 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7944 return VINF_SUCCESS;
7945}
7946
7947
7948/**
7949 * Implements 'DAA'.
7950 */
7951IEM_CIMPL_DEF_0(iemCImpl_daa)
7952{
7953 uint8_t const al = pVCpu->cpum.GstCtx.al;
7954 bool const fCarry = pVCpu->cpum.GstCtx.eflags.Bits.u1CF;
7955
7956 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7957 || (al & 0xf) >= 10)
7958 {
7959 pVCpu->cpum.GstCtx.al = al + 6;
7960 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7961 }
7962 else
7963 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7964
7965 if (al >= 0x9a || fCarry)
7966 {
7967 pVCpu->cpum.GstCtx.al += 0x60;
7968 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7969 }
7970 else
7971 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7972
7973 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7974 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7975 return VINF_SUCCESS;
7976}
7977
7978
7979/**
7980 * Implements 'DAS'.
7981 */
7982IEM_CIMPL_DEF_0(iemCImpl_das)
7983{
7984 uint8_t const uInputAL = pVCpu->cpum.GstCtx.al;
7985 bool const fCarry = pVCpu->cpum.GstCtx.eflags.Bits.u1CF;
7986
7987 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7988 || (uInputAL & 0xf) >= 10)
7989 {
7990 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7991 if (uInputAL < 6)
7992 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7993 pVCpu->cpum.GstCtx.al = uInputAL - 6;
7994 }
7995 else
7996 {
7997 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7998 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7999 }
8000
8001 if (uInputAL >= 0x9a || fCarry)
8002 {
8003 pVCpu->cpum.GstCtx.al -= 0x60;
8004 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8005 }
8006
8007 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8008 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8009 return VINF_SUCCESS;
8010}
8011
8012
8013/**
8014 * Implements 'AAA'.
8015 */
8016IEM_CIMPL_DEF_0(iemCImpl_aaa)
8017{
8018 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
8019 {
8020 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8021 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8022 {
8023 iemAImpl_add_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.u32);
8024 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8025 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8026 }
8027 else
8028 {
8029 iemHlpUpdateArithEFlagsU16(pVCpu, pVCpu->cpum.GstCtx.ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8030 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8031 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8032 }
8033 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8034 }
8035 else
8036 {
8037 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8038 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8039 {
8040 pVCpu->cpum.GstCtx.ax += UINT16_C(0x106);
8041 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8042 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8043 }
8044 else
8045 {
8046 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8047 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8048 }
8049 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8050 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8051 }
8052
8053 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8054 return VINF_SUCCESS;
8055}
8056
8057
8058/**
8059 * Implements 'AAS'.
8060 */
8061IEM_CIMPL_DEF_0(iemCImpl_aas)
8062{
8063 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
8064 {
8065 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8066 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8067 {
8068 iemAImpl_sub_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.u32);
8069 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8070 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8071 }
8072 else
8073 {
8074 iemHlpUpdateArithEFlagsU16(pVCpu, pVCpu->cpum.GstCtx.ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8075 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8076 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8077 }
8078 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8079 }
8080 else
8081 {
8082 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8083 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8084 {
8085 pVCpu->cpum.GstCtx.ax -= UINT16_C(0x106);
8086 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8087 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8088 }
8089 else
8090 {
8091 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8092 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8093 }
8094 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8095 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8096 }
8097
8098 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8099 return VINF_SUCCESS;
8100}
8101
8102
8103/**
8104 * Implements the 16-bit version of 'BOUND'.
8105 *
8106 * @note We have separate 16-bit and 32-bit variants of this function due to
8107 * the decoder using unsigned parameters, whereas we want signed one to
8108 * do the job. This is significant for a recompiler.
8109 */
8110IEM_CIMPL_DEF_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound)
8111{
8112 /*
8113 * Check if the index is inside the bounds, otherwise raise #BR.
8114 */
8115 if ( idxArray >= idxLowerBound
8116 && idxArray <= idxUpperBound)
8117 {
8118 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8119 return VINF_SUCCESS;
8120 }
8121
8122 return iemRaiseBoundRangeExceeded(pVCpu);
8123}
8124
8125
8126/**
8127 * Implements the 32-bit version of 'BOUND'.
8128 */
8129IEM_CIMPL_DEF_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound)
8130{
8131 /*
8132 * Check if the index is inside the bounds, otherwise raise #BR.
8133 */
8134 if ( idxArray >= idxLowerBound
8135 && idxArray <= idxUpperBound)
8136 {
8137 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8138 return VINF_SUCCESS;
8139 }
8140
8141 return iemRaiseBoundRangeExceeded(pVCpu);
8142}
8143
8144
8145
8146/*
8147 * Instantiate the various string operation combinations.
8148 */
8149#define OP_SIZE 8
8150#define ADDR_SIZE 16
8151#include "IEMAllCImplStrInstr.cpp.h"
8152#define OP_SIZE 8
8153#define ADDR_SIZE 32
8154#include "IEMAllCImplStrInstr.cpp.h"
8155#define OP_SIZE 8
8156#define ADDR_SIZE 64
8157#include "IEMAllCImplStrInstr.cpp.h"
8158
8159#define OP_SIZE 16
8160#define ADDR_SIZE 16
8161#include "IEMAllCImplStrInstr.cpp.h"
8162#define OP_SIZE 16
8163#define ADDR_SIZE 32
8164#include "IEMAllCImplStrInstr.cpp.h"
8165#define OP_SIZE 16
8166#define ADDR_SIZE 64
8167#include "IEMAllCImplStrInstr.cpp.h"
8168
8169#define OP_SIZE 32
8170#define ADDR_SIZE 16
8171#include "IEMAllCImplStrInstr.cpp.h"
8172#define OP_SIZE 32
8173#define ADDR_SIZE 32
8174#include "IEMAllCImplStrInstr.cpp.h"
8175#define OP_SIZE 32
8176#define ADDR_SIZE 64
8177#include "IEMAllCImplStrInstr.cpp.h"
8178
8179#define OP_SIZE 64
8180#define ADDR_SIZE 32
8181#include "IEMAllCImplStrInstr.cpp.h"
8182#define OP_SIZE 64
8183#define ADDR_SIZE 64
8184#include "IEMAllCImplStrInstr.cpp.h"
8185
8186
8187/**
8188 * Implements 'XGETBV'.
8189 */
8190IEM_CIMPL_DEF_0(iemCImpl_xgetbv)
8191{
8192 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
8193 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)
8194 {
8195 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
8196 switch (uEcx)
8197 {
8198 case 0:
8199 break;
8200
8201 case 1: /** @todo Implement XCR1 support. */
8202 default:
8203 Log(("xgetbv ecx=%RX32 -> #GP(0)\n", uEcx));
8204 return iemRaiseGeneralProtectionFault0(pVCpu);
8205
8206 }
8207 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_XCRx);
8208 pVCpu->cpum.GstCtx.rax = RT_LO_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]);
8209 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]);
8210
8211 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8212 return VINF_SUCCESS;
8213 }
8214 Log(("xgetbv CR4.OSXSAVE=0 -> UD\n"));
8215 return iemRaiseUndefinedOpcode(pVCpu);
8216}
8217
8218
8219/**
8220 * Implements 'XSETBV'.
8221 */
8222IEM_CIMPL_DEF_0(iemCImpl_xsetbv)
8223{
8224 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)
8225 {
8226 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_XSETBV))
8227 {
8228 Log2(("xsetbv: Guest intercept -> #VMEXIT\n"));
8229 IEM_SVM_UPDATE_NRIP(pVCpu);
8230 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_XSETBV, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
8231 }
8232
8233 if (pVCpu->iem.s.uCpl == 0)
8234 {
8235 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_XCRx);
8236
8237 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8238 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_XSETBV, cbInstr);
8239
8240 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
8241 uint64_t uNewValue = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx);
8242 switch (uEcx)
8243 {
8244 case 0:
8245 {
8246 int rc = CPUMSetGuestXcr0(pVCpu, uNewValue);
8247 if (rc == VINF_SUCCESS)
8248 break;
8249 Assert(rc == VERR_CPUM_RAISE_GP_0);
8250 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
8251 return iemRaiseGeneralProtectionFault0(pVCpu);
8252 }
8253
8254 case 1: /** @todo Implement XCR1 support. */
8255 default:
8256 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
8257 return iemRaiseGeneralProtectionFault0(pVCpu);
8258
8259 }
8260
8261 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8262 return VINF_SUCCESS;
8263 }
8264
8265 Log(("xsetbv cpl=%u -> GP(0)\n", pVCpu->iem.s.uCpl));
8266 return iemRaiseGeneralProtectionFault0(pVCpu);
8267 }
8268 Log(("xsetbv CR4.OSXSAVE=0 -> UD\n"));
8269 return iemRaiseUndefinedOpcode(pVCpu);
8270}
8271
8272#ifndef RT_ARCH_ARM64
8273# ifdef IN_RING3
8274
8275/** Argument package for iemCImpl_cmpxchg16b_fallback_rendezvous_callback. */
8276struct IEMCIMPLCX16ARGS
8277{
8278 PRTUINT128U pu128Dst;
8279 PRTUINT128U pu128RaxRdx;
8280 PRTUINT128U pu128RbxRcx;
8281 uint32_t *pEFlags;
8282# ifdef VBOX_STRICT
8283 uint32_t cCalls;
8284# endif
8285};
8286
8287/**
8288 * @callback_method_impl{FNVMMEMTRENDEZVOUS,
8289 * Worker for iemCImpl_cmpxchg16b_fallback_rendezvous}
8290 */
8291static DECLCALLBACK(VBOXSTRICTRC) iemCImpl_cmpxchg16b_fallback_rendezvous_callback(PVM pVM, PVMCPUCC pVCpu, void *pvUser)
8292{
8293 RT_NOREF(pVM, pVCpu);
8294 struct IEMCIMPLCX16ARGS *pArgs = (struct IEMCIMPLCX16ARGS *)pvUser;
8295# ifdef VBOX_STRICT
8296 Assert(pArgs->cCalls == 0);
8297 pArgs->cCalls++;
8298# endif
8299
8300 iemAImpl_cmpxchg16b_fallback(pArgs->pu128Dst, pArgs->pu128RaxRdx, pArgs->pu128RbxRcx, pArgs->pEFlags);
8301 return VINF_SUCCESS;
8302}
8303
8304# endif /* IN_RING3 */
8305
8306/**
8307 * Implements 'CMPXCHG16B' fallback using rendezvous.
8308 */
8309IEM_CIMPL_DEF_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
8310 PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags)
8311{
8312# ifdef IN_RING3
8313 struct IEMCIMPLCX16ARGS Args;
8314 Args.pu128Dst = pu128Dst;
8315 Args.pu128RaxRdx = pu128RaxRdx;
8316 Args.pu128RbxRcx = pu128RbxRcx;
8317 Args.pEFlags = pEFlags;
8318# ifdef VBOX_STRICT
8319 Args.cCalls = 0;
8320# endif
8321 VBOXSTRICTRC rcStrict = VMMR3EmtRendezvous(pVCpu->CTX_SUFF(pVM), VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE,
8322 iemCImpl_cmpxchg16b_fallback_rendezvous_callback, &Args);
8323 Assert(Args.cCalls == 1);
8324 if (rcStrict == VINF_SUCCESS)
8325 {
8326 /* Duplicated tail code. */
8327 rcStrict = iemMemCommitAndUnmap(pVCpu, pu128Dst, IEM_ACCESS_DATA_RW);
8328 if (rcStrict == VINF_SUCCESS)
8329 {
8330 pVCpu->cpum.GstCtx.eflags.u = *pEFlags; /* IEM_MC_COMMIT_EFLAGS */
8331 if (!(*pEFlags & X86_EFL_ZF))
8332 {
8333 pVCpu->cpum.GstCtx.rax = pu128RaxRdx->s.Lo;
8334 pVCpu->cpum.GstCtx.rdx = pu128RaxRdx->s.Hi;
8335 }
8336 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8337 }
8338 }
8339 return rcStrict;
8340# else
8341 RT_NOREF(pVCpu, cbInstr, pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
8342 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; /* This should get us to ring-3 for now. Should perhaps be replaced later. */
8343# endif
8344}
8345
8346#endif /* RT_ARCH_ARM64 */
8347
8348/**
8349 * Implements 'CLFLUSH' and 'CLFLUSHOPT'.
8350 *
8351 * This is implemented in C because it triggers a load like behaviour without
8352 * actually reading anything. Since that's not so common, it's implemented
8353 * here.
8354 *
8355 * @param iEffSeg The effective segment.
8356 * @param GCPtrEff The address of the image.
8357 */
8358IEM_CIMPL_DEF_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
8359{
8360 /*
8361 * Pretend to do a load w/o reading (see also iemCImpl_monitor and iemMemMap).
8362 */
8363 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrEff);
8364 if (rcStrict == VINF_SUCCESS)
8365 {
8366 RTGCPHYS GCPhysMem;
8367 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrEff, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
8368 if (rcStrict == VINF_SUCCESS)
8369 {
8370#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8371 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8372 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
8373 {
8374 /*
8375 * CLFLUSH/CLFLUSHOPT does not access the memory, but flushes the cache-line
8376 * that contains the address. However, if the address falls in the APIC-access
8377 * page, the address flushed must instead be the corresponding address in the
8378 * virtual-APIC page.
8379 *
8380 * See Intel spec. 29.4.4 "Instruction-Specific Considerations".
8381 */
8382 rcStrict = iemVmxVirtApicAccessUnused(pVCpu, &GCPhysMem, 1, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA);
8383 if ( rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE
8384 && rcStrict != VINF_VMX_MODIFIES_BEHAVIOR)
8385 return rcStrict;
8386 }
8387#endif
8388 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8389 return VINF_SUCCESS;
8390 }
8391 }
8392
8393 return rcStrict;
8394}
8395
8396
8397/**
8398 * Implements 'FINIT' and 'FNINIT'.
8399 *
8400 * @param fCheckXcpts Whether to check for umasked pending exceptions or
8401 * not.
8402 */
8403IEM_CIMPL_DEF_1(iemCImpl_finit, bool, fCheckXcpts)
8404{
8405 /*
8406 * Exceptions.
8407 */
8408 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
8409 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))
8410 return iemRaiseDeviceNotAvailable(pVCpu);
8411
8412 iemFpuActualizeStateForChange(pVCpu);
8413 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_X87);
8414
8415 /* FINIT: Raise #MF on pending exception(s): */
8416 if (fCheckXcpts && (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))
8417 return iemRaiseMathFault(pVCpu);
8418
8419 /*
8420 * Reset the state.
8421 */
8422 PX86XSAVEAREA pXState = &pVCpu->cpum.GstCtx.XState;
8423
8424 /* Rotate the stack to account for changed TOS. */
8425 iemFpuRotateStackSetTop(&pXState->x87, 0);
8426
8427 pXState->x87.FCW = 0x37f;
8428 pXState->x87.FSW = 0;
8429 pXState->x87.FTW = 0x00; /* 0 - empty. */
8430 /** @todo Intel says the instruction and data pointers are not cleared on
8431 * 387, presume that 8087 and 287 doesn't do so either. */
8432 /** @todo test this stuff. */
8433 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
8434 {
8435 pXState->x87.FPUDP = 0;
8436 pXState->x87.DS = 0; //??
8437 pXState->x87.Rsrvd2 = 0;
8438 pXState->x87.FPUIP = 0;
8439 pXState->x87.CS = 0; //??
8440 pXState->x87.Rsrvd1 = 0;
8441 }
8442 pXState->x87.FOP = 0;
8443
8444 iemHlpUsedFpu(pVCpu);
8445 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8446 return VINF_SUCCESS;
8447}
8448
8449
8450/**
8451 * Implements 'FXSAVE'.
8452 *
8453 * @param iEffSeg The effective segment.
8454 * @param GCPtrEff The address of the image.
8455 * @param enmEffOpSize The operand size (only REX.W really matters).
8456 */
8457IEM_CIMPL_DEF_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8458{
8459 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
8460
8461 /*
8462 * Raise exceptions.
8463 */
8464 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
8465 return iemRaiseUndefinedOpcode(pVCpu);
8466 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_TS | X86_CR0_EM))
8467 return iemRaiseDeviceNotAvailable(pVCpu);
8468
8469 /*
8470 * Access the memory.
8471 */
8472 void *pvMem512;
8473 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE,
8474 15 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8475 if (rcStrict != VINF_SUCCESS)
8476 return rcStrict;
8477 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
8478 PCX86FXSTATE pSrc = &pVCpu->cpum.GstCtx.XState.x87;
8479
8480 /*
8481 * Store the registers.
8482 */
8483 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
8484 * implementation specific whether MXCSR and XMM0-XMM7 are saved. */
8485
8486 /* common for all formats */
8487 pDst->FCW = pSrc->FCW;
8488 pDst->FSW = pSrc->FSW;
8489 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8490 pDst->FOP = pSrc->FOP;
8491 pDst->MXCSR = pSrc->MXCSR;
8492 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8493 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8494 {
8495 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
8496 * them for now... */
8497 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8498 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8499 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8500 pDst->aRegs[i].au32[3] = 0;
8501 }
8502
8503 /* FPU IP, CS, DP and DS. */
8504 pDst->FPUIP = pSrc->FPUIP;
8505 pDst->CS = pSrc->CS;
8506 pDst->FPUDP = pSrc->FPUDP;
8507 pDst->DS = pSrc->DS;
8508 if (enmEffOpSize == IEMMODE_64BIT)
8509 {
8510 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8511 pDst->Rsrvd1 = pSrc->Rsrvd1;
8512 pDst->Rsrvd2 = pSrc->Rsrvd2;
8513 }
8514 else
8515 {
8516 pDst->Rsrvd1 = 0;
8517 pDst->Rsrvd2 = 0;
8518 }
8519
8520 /* XMM registers. */
8521 if ( !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
8522 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
8523 || pVCpu->iem.s.uCpl != 0)
8524 {
8525 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8526 for (uint32_t i = 0; i < cXmmRegs; i++)
8527 pDst->aXMM[i] = pSrc->aXMM[i];
8528 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8529 * right? */
8530 }
8531
8532 /*
8533 * Commit the memory.
8534 */
8535 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8536 if (rcStrict != VINF_SUCCESS)
8537 return rcStrict;
8538
8539 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8540 return VINF_SUCCESS;
8541}
8542
8543
8544/**
8545 * Implements 'FXRSTOR'.
8546 *
8547 * @param iEffSeg The effective segment register for @a GCPtrEff.
8548 * @param GCPtrEff The address of the image.
8549 * @param enmEffOpSize The operand size (only REX.W really matters).
8550 */
8551IEM_CIMPL_DEF_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8552{
8553 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
8554
8555 /*
8556 * Raise exceptions.
8557 */
8558 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
8559 return iemRaiseUndefinedOpcode(pVCpu);
8560 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_TS | X86_CR0_EM))
8561 return iemRaiseDeviceNotAvailable(pVCpu);
8562
8563 /*
8564 * Access the memory.
8565 */
8566 void *pvMem512;
8567 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R,
8568 15 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8569 if (rcStrict != VINF_SUCCESS)
8570 return rcStrict;
8571 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
8572 PX86FXSTATE pDst = &pVCpu->cpum.GstCtx.XState.x87;
8573
8574 /*
8575 * Check the state for stuff which will #GP(0).
8576 */
8577 uint32_t const fMXCSR = pSrc->MXCSR;
8578 uint32_t const fMXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8579 if (fMXCSR & ~fMXCSR_MASK)
8580 {
8581 Log(("fxrstor: MXCSR=%#x (MXCSR_MASK=%#x) -> #GP(0)\n", fMXCSR, fMXCSR_MASK));
8582 return iemRaiseGeneralProtectionFault0(pVCpu);
8583 }
8584
8585 /*
8586 * Load the registers.
8587 */
8588 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
8589 * implementation specific whether MXCSR and XMM0-XMM7 are restored. */
8590
8591 /* common for all formats */
8592 pDst->FCW = pSrc->FCW;
8593 pDst->FSW = pSrc->FSW;
8594 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8595 pDst->FOP = pSrc->FOP;
8596 pDst->MXCSR = fMXCSR;
8597 /* (MXCSR_MASK is read-only) */
8598 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
8599 {
8600 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8601 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8602 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8603 pDst->aRegs[i].au32[3] = 0;
8604 }
8605
8606 /* FPU IP, CS, DP and DS. */
8607 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8608 {
8609 pDst->FPUIP = pSrc->FPUIP;
8610 pDst->CS = pSrc->CS;
8611 pDst->Rsrvd1 = pSrc->Rsrvd1;
8612 pDst->FPUDP = pSrc->FPUDP;
8613 pDst->DS = pSrc->DS;
8614 pDst->Rsrvd2 = pSrc->Rsrvd2;
8615 }
8616 else
8617 {
8618 pDst->FPUIP = pSrc->FPUIP;
8619 pDst->CS = pSrc->CS;
8620 pDst->Rsrvd1 = 0;
8621 pDst->FPUDP = pSrc->FPUDP;
8622 pDst->DS = pSrc->DS;
8623 pDst->Rsrvd2 = 0;
8624 }
8625
8626 /* XMM registers. */
8627 if ( !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
8628 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
8629 || pVCpu->iem.s.uCpl != 0)
8630 {
8631 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8632 for (uint32_t i = 0; i < cXmmRegs; i++)
8633 pDst->aXMM[i] = pSrc->aXMM[i];
8634 }
8635
8636 if (pDst->FSW & X86_FSW_ES)
8637 Log11(("fxrstor: %04x:%08RX64: loading state with pending FPU exception (FSW=%#x)\n",
8638 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pSrc->FSW));
8639
8640 /*
8641 * Commit the memory.
8642 */
8643 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
8644 if (rcStrict != VINF_SUCCESS)
8645 return rcStrict;
8646
8647 iemHlpUsedFpu(pVCpu);
8648 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8649 return VINF_SUCCESS;
8650}
8651
8652
8653/**
8654 * Implements 'XSAVE'.
8655 *
8656 * @param iEffSeg The effective segment.
8657 * @param GCPtrEff The address of the image.
8658 * @param enmEffOpSize The operand size (only REX.W really matters).
8659 */
8660IEM_CIMPL_DEF_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8661{
8662 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
8663
8664 /*
8665 * Raise exceptions.
8666 */
8667 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
8668 return iemRaiseUndefinedOpcode(pVCpu);
8669 /* When in VMX non-root mode and XSAVE/XRSTOR is not enabled, it results in #UD. */
8670 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8671 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_XSAVES_XRSTORS))
8672 {
8673 Log(("xrstor: Not enabled for nested-guest execution -> #UD\n"));
8674 return iemRaiseUndefinedOpcode(pVCpu);
8675 }
8676 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)
8677 return iemRaiseDeviceNotAvailable(pVCpu);
8678
8679 /*
8680 * Calc the requested mask.
8681 */
8682 uint64_t const fReqComponents = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx) & pVCpu->cpum.GstCtx.aXcr[0];
8683 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8684 uint64_t const fXInUse = pVCpu->cpum.GstCtx.aXcr[0];
8685
8686/** @todo figure out the exact protocol for the memory access. Currently we
8687 * just need this crap to work halfways to make it possible to test
8688 * AVX instructions. */
8689/** @todo figure out the XINUSE and XMODIFIED */
8690
8691 /*
8692 * Access the x87 memory state.
8693 */
8694 /* The x87+SSE state. */
8695 void *pvMem512;
8696 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE,
8697 63 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8698 if (rcStrict != VINF_SUCCESS)
8699 return rcStrict;
8700 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
8701 PCX86FXSTATE pSrc = &pVCpu->cpum.GstCtx.XState.x87;
8702
8703 /* The header. */
8704 PX86XSAVEHDR pHdr;
8705 rcStrict = iemMemMap(pVCpu, (void **)&pHdr, sizeof(&pHdr), iEffSeg, GCPtrEff + 512, IEM_ACCESS_DATA_RW, 0 /* checked above */);
8706 if (rcStrict != VINF_SUCCESS)
8707 return rcStrict;
8708
8709 /*
8710 * Store the X87 state.
8711 */
8712 if (fReqComponents & XSAVE_C_X87)
8713 {
8714 /* common for all formats */
8715 pDst->FCW = pSrc->FCW;
8716 pDst->FSW = pSrc->FSW;
8717 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8718 pDst->FOP = pSrc->FOP;
8719 pDst->FPUIP = pSrc->FPUIP;
8720 pDst->CS = pSrc->CS;
8721 pDst->FPUDP = pSrc->FPUDP;
8722 pDst->DS = pSrc->DS;
8723 if (enmEffOpSize == IEMMODE_64BIT)
8724 {
8725 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8726 pDst->Rsrvd1 = pSrc->Rsrvd1;
8727 pDst->Rsrvd2 = pSrc->Rsrvd2;
8728 }
8729 else
8730 {
8731 pDst->Rsrvd1 = 0;
8732 pDst->Rsrvd2 = 0;
8733 }
8734 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8735 {
8736 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
8737 * them for now... */
8738 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8739 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8740 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8741 pDst->aRegs[i].au32[3] = 0;
8742 }
8743
8744 }
8745
8746 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
8747 {
8748 pDst->MXCSR = pSrc->MXCSR;
8749 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8750 }
8751
8752 if (fReqComponents & XSAVE_C_SSE)
8753 {
8754 /* XMM registers. */
8755 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8756 for (uint32_t i = 0; i < cXmmRegs; i++)
8757 pDst->aXMM[i] = pSrc->aXMM[i];
8758 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8759 * right? */
8760 }
8761
8762 /* Commit the x87 state bits. (probably wrong) */
8763 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8764 if (rcStrict != VINF_SUCCESS)
8765 return rcStrict;
8766
8767 /*
8768 * Store AVX state.
8769 */
8770 if (fReqComponents & XSAVE_C_YMM)
8771 {
8772 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
8773 AssertLogRelReturn(pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
8774 PCX86XSAVEYMMHI pCompSrc = CPUMCTX_XSAVE_C_PTR(IEM_GET_CTX(pVCpu), XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
8775 PX86XSAVEYMMHI pCompDst;
8776 rcStrict = iemMemMap(pVCpu, (void **)&pCompDst, sizeof(*pCompDst), iEffSeg, GCPtrEff + pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT],
8777 IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE, 0 /* checked above */);
8778 if (rcStrict != VINF_SUCCESS)
8779 return rcStrict;
8780
8781 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8782 for (uint32_t i = 0; i < cXmmRegs; i++)
8783 pCompDst->aYmmHi[i] = pCompSrc->aYmmHi[i];
8784
8785 rcStrict = iemMemCommitAndUnmap(pVCpu, pCompDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8786 if (rcStrict != VINF_SUCCESS)
8787 return rcStrict;
8788 }
8789
8790 /*
8791 * Update the header.
8792 */
8793 pHdr->bmXState = (pHdr->bmXState & ~fReqComponents)
8794 | (fReqComponents & fXInUse);
8795
8796 rcStrict = iemMemCommitAndUnmap(pVCpu, pHdr, IEM_ACCESS_DATA_RW);
8797 if (rcStrict != VINF_SUCCESS)
8798 return rcStrict;
8799
8800 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8801 return VINF_SUCCESS;
8802}
8803
8804
8805/**
8806 * Implements 'XRSTOR'.
8807 *
8808 * @param iEffSeg The effective segment.
8809 * @param GCPtrEff The address of the image.
8810 * @param enmEffOpSize The operand size (only REX.W really matters).
8811 */
8812IEM_CIMPL_DEF_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8813{
8814 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
8815
8816 /*
8817 * Raise exceptions.
8818 */
8819 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
8820 return iemRaiseUndefinedOpcode(pVCpu);
8821 /* When in VMX non-root mode and XSAVE/XRSTOR is not enabled, it results in #UD. */
8822 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8823 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_XSAVES_XRSTORS))
8824 {
8825 Log(("xrstor: Not enabled for nested-guest execution -> #UD\n"));
8826 return iemRaiseUndefinedOpcode(pVCpu);
8827 }
8828 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)
8829 return iemRaiseDeviceNotAvailable(pVCpu);
8830 if (GCPtrEff & 63)
8831 {
8832 /** @todo CPU/VM detection possible! \#AC might not be signal for
8833 * all/any misalignment sizes, intel says its an implementation detail. */
8834 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
8835 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
8836 && pVCpu->iem.s.uCpl == 3)
8837 return iemRaiseAlignmentCheckException(pVCpu);
8838 return iemRaiseGeneralProtectionFault0(pVCpu);
8839 }
8840
8841/** @todo figure out the exact protocol for the memory access. Currently we
8842 * just need this crap to work halfways to make it possible to test
8843 * AVX instructions. */
8844/** @todo figure out the XINUSE and XMODIFIED */
8845
8846 /*
8847 * Access the x87 memory state.
8848 */
8849 /* The x87+SSE state. */
8850 void *pvMem512;
8851 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R,
8852 63 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8853 if (rcStrict != VINF_SUCCESS)
8854 return rcStrict;
8855 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
8856 PX86FXSTATE pDst = &pVCpu->cpum.GstCtx.XState.x87;
8857
8858 /*
8859 * Calc the requested mask
8860 */
8861 PX86XSAVEHDR pHdrDst = &pVCpu->cpum.GstCtx.XState.Hdr;
8862 PCX86XSAVEHDR pHdrSrc;
8863 rcStrict = iemMemMap(pVCpu, (void **)&pHdrSrc, sizeof(&pHdrSrc), iEffSeg, GCPtrEff + 512,
8864 IEM_ACCESS_DATA_R, 0 /* checked above */);
8865 if (rcStrict != VINF_SUCCESS)
8866 return rcStrict;
8867
8868 uint64_t const fReqComponents = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx) & pVCpu->cpum.GstCtx.aXcr[0];
8869 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8870 //uint64_t const fXInUse = pVCpu->cpum.GstCtx.aXcr[0];
8871 uint64_t const fRstorMask = pHdrSrc->bmXState;
8872 uint64_t const fCompMask = pHdrSrc->bmXComp;
8873
8874 AssertLogRelReturn(!(fCompMask & XSAVE_C_X), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8875
8876 uint32_t const cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8877
8878 /* We won't need this any longer. */
8879 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pHdrSrc, IEM_ACCESS_DATA_R);
8880 if (rcStrict != VINF_SUCCESS)
8881 return rcStrict;
8882
8883 /*
8884 * Store the X87 state.
8885 */
8886 if (fReqComponents & XSAVE_C_X87)
8887 {
8888 if (fRstorMask & XSAVE_C_X87)
8889 {
8890 pDst->FCW = pSrc->FCW;
8891 pDst->FSW = pSrc->FSW;
8892 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8893 pDst->FOP = pSrc->FOP;
8894 pDst->FPUIP = pSrc->FPUIP;
8895 pDst->CS = pSrc->CS;
8896 pDst->FPUDP = pSrc->FPUDP;
8897 pDst->DS = pSrc->DS;
8898 if (enmEffOpSize == IEMMODE_64BIT)
8899 {
8900 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8901 pDst->Rsrvd1 = pSrc->Rsrvd1;
8902 pDst->Rsrvd2 = pSrc->Rsrvd2;
8903 }
8904 else
8905 {
8906 pDst->Rsrvd1 = 0;
8907 pDst->Rsrvd2 = 0;
8908 }
8909 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8910 {
8911 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8912 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8913 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8914 pDst->aRegs[i].au32[3] = 0;
8915 }
8916 if (pDst->FSW & X86_FSW_ES)
8917 Log11(("xrstor: %04x:%08RX64: loading state with pending FPU exception (FSW=%#x)\n",
8918 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pSrc->FSW));
8919 }
8920 else
8921 {
8922 pDst->FCW = 0x37f;
8923 pDst->FSW = 0;
8924 pDst->FTW = 0x00; /* 0 - empty. */
8925 pDst->FPUDP = 0;
8926 pDst->DS = 0; //??
8927 pDst->Rsrvd2= 0;
8928 pDst->FPUIP = 0;
8929 pDst->CS = 0; //??
8930 pDst->Rsrvd1= 0;
8931 pDst->FOP = 0;
8932 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
8933 {
8934 pDst->aRegs[i].au32[0] = 0;
8935 pDst->aRegs[i].au32[1] = 0;
8936 pDst->aRegs[i].au32[2] = 0;
8937 pDst->aRegs[i].au32[3] = 0;
8938 }
8939 }
8940 pHdrDst->bmXState |= XSAVE_C_X87; /* playing safe for now */
8941 }
8942
8943 /* MXCSR */
8944 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
8945 {
8946 if (fRstorMask & (XSAVE_C_SSE | XSAVE_C_YMM))
8947 pDst->MXCSR = pSrc->MXCSR;
8948 else
8949 pDst->MXCSR = 0x1f80;
8950 }
8951
8952 /* XMM registers. */
8953 if (fReqComponents & XSAVE_C_SSE)
8954 {
8955 if (fRstorMask & XSAVE_C_SSE)
8956 {
8957 for (uint32_t i = 0; i < cXmmRegs; i++)
8958 pDst->aXMM[i] = pSrc->aXMM[i];
8959 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8960 * right? */
8961 }
8962 else
8963 {
8964 for (uint32_t i = 0; i < cXmmRegs; i++)
8965 {
8966 pDst->aXMM[i].au64[0] = 0;
8967 pDst->aXMM[i].au64[1] = 0;
8968 }
8969 }
8970 pHdrDst->bmXState |= XSAVE_C_SSE; /* playing safe for now */
8971 }
8972
8973 /* Unmap the x87 state bits (so we've don't run out of mapping). */
8974 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
8975 if (rcStrict != VINF_SUCCESS)
8976 return rcStrict;
8977
8978 /*
8979 * Restore AVX state.
8980 */
8981 if (fReqComponents & XSAVE_C_YMM)
8982 {
8983 AssertLogRelReturn(pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
8984 PX86XSAVEYMMHI pCompDst = CPUMCTX_XSAVE_C_PTR(IEM_GET_CTX(pVCpu), XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
8985
8986 if (fRstorMask & XSAVE_C_YMM)
8987 {
8988 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
8989 PCX86XSAVEYMMHI pCompSrc;
8990 rcStrict = iemMemMap(pVCpu, (void **)&pCompSrc, sizeof(*pCompDst),
8991 iEffSeg, GCPtrEff + pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT],
8992 IEM_ACCESS_DATA_R, 0 /* checked above */);
8993 if (rcStrict != VINF_SUCCESS)
8994 return rcStrict;
8995
8996 for (uint32_t i = 0; i < cXmmRegs; i++)
8997 {
8998 pCompDst->aYmmHi[i].au64[0] = pCompSrc->aYmmHi[i].au64[0];
8999 pCompDst->aYmmHi[i].au64[1] = pCompSrc->aYmmHi[i].au64[1];
9000 }
9001
9002 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pCompSrc, IEM_ACCESS_DATA_R);
9003 if (rcStrict != VINF_SUCCESS)
9004 return rcStrict;
9005 }
9006 else
9007 {
9008 for (uint32_t i = 0; i < cXmmRegs; i++)
9009 {
9010 pCompDst->aYmmHi[i].au64[0] = 0;
9011 pCompDst->aYmmHi[i].au64[1] = 0;
9012 }
9013 }
9014 pHdrDst->bmXState |= XSAVE_C_YMM; /* playing safe for now */
9015 }
9016
9017 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9018 return VINF_SUCCESS;
9019}
9020
9021
9022
9023
9024/**
9025 * Implements 'STMXCSR'.
9026 *
9027 * @param iEffSeg The effective segment register for @a GCPtrEff.
9028 * @param GCPtrEff The address of the image.
9029 */
9030IEM_CIMPL_DEF_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
9031{
9032 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
9033
9034 /*
9035 * Raise exceptions.
9036 */
9037 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
9038 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
9039 {
9040 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
9041 {
9042 /*
9043 * Do the job.
9044 */
9045 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.XState.x87.MXCSR);
9046 if (rcStrict == VINF_SUCCESS)
9047 {
9048 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9049 return VINF_SUCCESS;
9050 }
9051 return rcStrict;
9052 }
9053 return iemRaiseDeviceNotAvailable(pVCpu);
9054 }
9055 return iemRaiseUndefinedOpcode(pVCpu);
9056}
9057
9058
9059/**
9060 * Implements 'VSTMXCSR'.
9061 *
9062 * @param iEffSeg The effective segment register for @a GCPtrEff.
9063 * @param GCPtrEff The address of the image.
9064 */
9065IEM_CIMPL_DEF_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
9066{
9067 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_XCRx);
9068
9069 /*
9070 * Raise exceptions.
9071 */
9072 if ( ( !IEM_IS_GUEST_CPU_AMD(pVCpu)
9073 ? (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) == (XSAVE_C_SSE | XSAVE_C_YMM)
9074 : !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)) /* AMD Jaguar CPU (f0x16,m0,s1) behaviour */
9075 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
9076 {
9077 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
9078 {
9079 /*
9080 * Do the job.
9081 */
9082 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.XState.x87.MXCSR);
9083 if (rcStrict == VINF_SUCCESS)
9084 {
9085 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9086 return VINF_SUCCESS;
9087 }
9088 return rcStrict;
9089 }
9090 return iemRaiseDeviceNotAvailable(pVCpu);
9091 }
9092 return iemRaiseUndefinedOpcode(pVCpu);
9093}
9094
9095
9096/**
9097 * Implements 'LDMXCSR'.
9098 *
9099 * @param iEffSeg The effective segment register for @a GCPtrEff.
9100 * @param GCPtrEff The address of the image.
9101 */
9102IEM_CIMPL_DEF_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
9103{
9104 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
9105
9106 /*
9107 * Raise exceptions.
9108 */
9109 /** @todo testcase - order of LDMXCSR faults. Does \#PF, \#GP and \#SS
9110 * happen after or before \#UD and \#EM? */
9111 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
9112 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
9113 {
9114 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
9115 {
9116 /*
9117 * Do the job.
9118 */
9119 uint32_t fNewMxCsr;
9120 VBOXSTRICTRC rcStrict = iemMemFetchDataU32(pVCpu, &fNewMxCsr, iEffSeg, GCPtrEff);
9121 if (rcStrict == VINF_SUCCESS)
9122 {
9123 uint32_t const fMxCsrMask = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
9124 if (!(fNewMxCsr & ~fMxCsrMask))
9125 {
9126 pVCpu->cpum.GstCtx.XState.x87.MXCSR = fNewMxCsr;
9127 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9128 return VINF_SUCCESS;
9129 }
9130 Log(("lddmxcsr: New MXCSR=%#RX32 & ~MASK=%#RX32 = %#RX32 -> #GP(0)\n",
9131 fNewMxCsr, fMxCsrMask, fNewMxCsr & ~fMxCsrMask));
9132 return iemRaiseGeneralProtectionFault0(pVCpu);
9133 }
9134 return rcStrict;
9135 }
9136 return iemRaiseDeviceNotAvailable(pVCpu);
9137 }
9138 return iemRaiseUndefinedOpcode(pVCpu);
9139}
9140
9141
9142/**
9143 * Commmon routine for fnstenv and fnsave.
9144 *
9145 * @param pVCpu The cross context virtual CPU structure of the calling thread.
9146 * @param enmEffOpSize The effective operand size.
9147 * @param uPtr Where to store the state.
9148 */
9149static void iemCImplCommonFpuStoreEnv(PVMCPUCC pVCpu, IEMMODE enmEffOpSize, RTPTRUNION uPtr)
9150{
9151 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9152 PCX86FXSTATE pSrcX87 = &pVCpu->cpum.GstCtx.XState.x87;
9153 if (enmEffOpSize == IEMMODE_16BIT)
9154 {
9155 uPtr.pu16[0] = pSrcX87->FCW;
9156 uPtr.pu16[1] = pSrcX87->FSW;
9157 uPtr.pu16[2] = iemFpuCalcFullFtw(pSrcX87);
9158 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9159 {
9160 /** @todo Testcase: How does this work when the FPUIP/CS was saved in
9161 * protected mode or long mode and we save it in real mode? And vice
9162 * versa? And with 32-bit operand size? I think CPU is storing the
9163 * effective address ((CS << 4) + IP) in the offset register and not
9164 * doing any address calculations here. */
9165 uPtr.pu16[3] = (uint16_t)pSrcX87->FPUIP;
9166 uPtr.pu16[4] = ((pSrcX87->FPUIP >> 4) & UINT16_C(0xf000)) | pSrcX87->FOP;
9167 uPtr.pu16[5] = (uint16_t)pSrcX87->FPUDP;
9168 uPtr.pu16[6] = (pSrcX87->FPUDP >> 4) & UINT16_C(0xf000);
9169 }
9170 else
9171 {
9172 uPtr.pu16[3] = pSrcX87->FPUIP;
9173 uPtr.pu16[4] = pSrcX87->CS;
9174 uPtr.pu16[5] = pSrcX87->FPUDP;
9175 uPtr.pu16[6] = pSrcX87->DS;
9176 }
9177 }
9178 else
9179 {
9180 /** @todo Testcase: what is stored in the "gray" areas? (figure 8-9 and 8-10) */
9181 uPtr.pu16[0*2] = pSrcX87->FCW;
9182 uPtr.pu16[0*2+1] = 0xffff; /* (0xffff observed on intel skylake.) */
9183 uPtr.pu16[1*2] = pSrcX87->FSW;
9184 uPtr.pu16[1*2+1] = 0xffff;
9185 uPtr.pu16[2*2] = iemFpuCalcFullFtw(pSrcX87);
9186 uPtr.pu16[2*2+1] = 0xffff;
9187 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9188 {
9189 uPtr.pu16[3*2] = (uint16_t)pSrcX87->FPUIP;
9190 uPtr.pu32[4] = ((pSrcX87->FPUIP & UINT32_C(0xffff0000)) >> 4) | pSrcX87->FOP;
9191 uPtr.pu16[5*2] = (uint16_t)pSrcX87->FPUDP;
9192 uPtr.pu32[6] = (pSrcX87->FPUDP & UINT32_C(0xffff0000)) >> 4;
9193 }
9194 else
9195 {
9196 uPtr.pu32[3] = pSrcX87->FPUIP;
9197 uPtr.pu16[4*2] = pSrcX87->CS;
9198 uPtr.pu16[4*2+1] = pSrcX87->FOP;
9199 uPtr.pu32[5] = pSrcX87->FPUDP;
9200 uPtr.pu16[6*2] = pSrcX87->DS;
9201 uPtr.pu16[6*2+1] = 0xffff;
9202 }
9203 }
9204}
9205
9206
9207/**
9208 * Commmon routine for fldenv and frstor
9209 *
9210 * @param pVCpu The cross context virtual CPU structure of the calling thread.
9211 * @param enmEffOpSize The effective operand size.
9212 * @param uPtr Where to store the state.
9213 */
9214static void iemCImplCommonFpuRestoreEnv(PVMCPUCC pVCpu, IEMMODE enmEffOpSize, RTCPTRUNION uPtr)
9215{
9216 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9217 PX86FXSTATE pDstX87 = &pVCpu->cpum.GstCtx.XState.x87;
9218 if (enmEffOpSize == IEMMODE_16BIT)
9219 {
9220 pDstX87->FCW = uPtr.pu16[0];
9221 pDstX87->FSW = uPtr.pu16[1];
9222 pDstX87->FTW = uPtr.pu16[2];
9223 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9224 {
9225 pDstX87->FPUIP = uPtr.pu16[3] | ((uint32_t)(uPtr.pu16[4] & UINT16_C(0xf000)) << 4);
9226 pDstX87->FPUDP = uPtr.pu16[5] | ((uint32_t)(uPtr.pu16[6] & UINT16_C(0xf000)) << 4);
9227 pDstX87->FOP = uPtr.pu16[4] & UINT16_C(0x07ff);
9228 pDstX87->CS = 0;
9229 pDstX87->Rsrvd1= 0;
9230 pDstX87->DS = 0;
9231 pDstX87->Rsrvd2= 0;
9232 }
9233 else
9234 {
9235 pDstX87->FPUIP = uPtr.pu16[3];
9236 pDstX87->CS = uPtr.pu16[4];
9237 pDstX87->Rsrvd1= 0;
9238 pDstX87->FPUDP = uPtr.pu16[5];
9239 pDstX87->DS = uPtr.pu16[6];
9240 pDstX87->Rsrvd2= 0;
9241 /** @todo Testcase: Is FOP cleared when doing 16-bit protected mode fldenv? */
9242 }
9243 }
9244 else
9245 {
9246 pDstX87->FCW = uPtr.pu16[0*2];
9247 pDstX87->FSW = uPtr.pu16[1*2];
9248 pDstX87->FTW = uPtr.pu16[2*2];
9249 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9250 {
9251 pDstX87->FPUIP = uPtr.pu16[3*2] | ((uPtr.pu32[4] & UINT32_C(0x0ffff000)) << 4);
9252 pDstX87->FOP = uPtr.pu32[4] & UINT16_C(0x07ff);
9253 pDstX87->FPUDP = uPtr.pu16[5*2] | ((uPtr.pu32[6] & UINT32_C(0x0ffff000)) << 4);
9254 pDstX87->CS = 0;
9255 pDstX87->Rsrvd1= 0;
9256 pDstX87->DS = 0;
9257 pDstX87->Rsrvd2= 0;
9258 }
9259 else
9260 {
9261 pDstX87->FPUIP = uPtr.pu32[3];
9262 pDstX87->CS = uPtr.pu16[4*2];
9263 pDstX87->Rsrvd1= 0;
9264 pDstX87->FOP = uPtr.pu16[4*2+1];
9265 pDstX87->FPUDP = uPtr.pu32[5];
9266 pDstX87->DS = uPtr.pu16[6*2];
9267 pDstX87->Rsrvd2= 0;
9268 }
9269 }
9270
9271 /* Make adjustments. */
9272 pDstX87->FTW = iemFpuCompressFtw(pDstX87->FTW);
9273#ifdef LOG_ENABLED
9274 uint16_t const fOldFsw = pDstX87->FSW;
9275#endif
9276 pDstX87->FCW &= ~X86_FCW_ZERO_MASK;
9277 iemFpuRecalcExceptionStatus(pDstX87);
9278#ifdef LOG_ENABLED
9279 if ((pDstX87->FSW & X86_FSW_ES) ^ (fOldFsw & X86_FSW_ES))
9280 Log11(("iemCImplCommonFpuRestoreEnv: %04x:%08RX64: %s FPU exception (FCW=%#x FSW=%#x -> %#x)\n",
9281 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fOldFsw & X86_FSW_ES ? "Supressed" : "Raised",
9282 pDstX87->FCW, fOldFsw, pDstX87->FSW));
9283#endif
9284
9285 /** @todo Testcase: Check if ES and/or B are automatically cleared if no
9286 * exceptions are pending after loading the saved state? */
9287}
9288
9289
9290/**
9291 * Implements 'FNSTENV'.
9292 *
9293 * @param enmEffOpSize The operand size (only REX.W really matters).
9294 * @param iEffSeg The effective segment register for @a GCPtrEffDst.
9295 * @param GCPtrEffDst The address of the image.
9296 */
9297IEM_CIMPL_DEF_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
9298{
9299 RTPTRUNION uPtr;
9300 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
9301 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE,
9302 enmEffOpSize == IEMMODE_16BIT ? 1 : 3 /** @todo ? */);
9303 if (rcStrict != VINF_SUCCESS)
9304 return rcStrict;
9305
9306 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr);
9307
9308 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
9309 if (rcStrict != VINF_SUCCESS)
9310 return rcStrict;
9311
9312 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
9313 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9314 return VINF_SUCCESS;
9315}
9316
9317
9318/**
9319 * Implements 'FNSAVE'.
9320 *
9321 * @param enmEffOpSize The operand size.
9322 * @param iEffSeg The effective segment register for @a GCPtrEffDst.
9323 * @param GCPtrEffDst The address of the image.
9324 */
9325IEM_CIMPL_DEF_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
9326{
9327 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9328
9329 RTPTRUNION uPtr;
9330 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
9331 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE, 3 /** @todo ? */);
9332 if (rcStrict != VINF_SUCCESS)
9333 return rcStrict;
9334
9335 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9336 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr);
9337 PRTFLOAT80U paRegs = (PRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
9338 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
9339 {
9340 paRegs[i].au32[0] = pFpuCtx->aRegs[i].au32[0];
9341 paRegs[i].au32[1] = pFpuCtx->aRegs[i].au32[1];
9342 paRegs[i].au16[4] = pFpuCtx->aRegs[i].au16[4];
9343 }
9344
9345 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
9346 if (rcStrict != VINF_SUCCESS)
9347 return rcStrict;
9348
9349 /* Rotate the stack to account for changed TOS. */
9350 iemFpuRotateStackSetTop(pFpuCtx, 0);
9351
9352 /*
9353 * Re-initialize the FPU context.
9354 */
9355 pFpuCtx->FCW = 0x37f;
9356 pFpuCtx->FSW = 0;
9357 pFpuCtx->FTW = 0x00; /* 0 - empty */
9358 pFpuCtx->FPUDP = 0;
9359 pFpuCtx->DS = 0;
9360 pFpuCtx->Rsrvd2= 0;
9361 pFpuCtx->FPUIP = 0;
9362 pFpuCtx->CS = 0;
9363 pFpuCtx->Rsrvd1= 0;
9364 pFpuCtx->FOP = 0;
9365
9366 iemHlpUsedFpu(pVCpu);
9367 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9368 return VINF_SUCCESS;
9369}
9370
9371
9372
9373/**
9374 * Implements 'FLDENV'.
9375 *
9376 * @param enmEffOpSize The operand size (only REX.W really matters).
9377 * @param iEffSeg The effective segment register for @a GCPtrEffSrc.
9378 * @param GCPtrEffSrc The address of the image.
9379 */
9380IEM_CIMPL_DEF_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
9381{
9382 RTCPTRUNION uPtr;
9383 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
9384 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R,
9385 enmEffOpSize == IEMMODE_16BIT ? 1 : 3 /** @todo ?*/);
9386 if (rcStrict != VINF_SUCCESS)
9387 return rcStrict;
9388
9389 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr);
9390
9391 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
9392 if (rcStrict != VINF_SUCCESS)
9393 return rcStrict;
9394
9395 iemHlpUsedFpu(pVCpu);
9396 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9397 return VINF_SUCCESS;
9398}
9399
9400
9401/**
9402 * Implements 'FRSTOR'.
9403 *
9404 * @param enmEffOpSize The operand size.
9405 * @param iEffSeg The effective segment register for @a GCPtrEffSrc.
9406 * @param GCPtrEffSrc The address of the image.
9407 */
9408IEM_CIMPL_DEF_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
9409{
9410 RTCPTRUNION uPtr;
9411 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
9412 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R, 3 /** @todo ?*/ );
9413 if (rcStrict != VINF_SUCCESS)
9414 return rcStrict;
9415
9416 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9417 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr);
9418 PCRTFLOAT80U paRegs = (PCRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
9419 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
9420 {
9421 pFpuCtx->aRegs[i].au32[0] = paRegs[i].au32[0];
9422 pFpuCtx->aRegs[i].au32[1] = paRegs[i].au32[1];
9423 pFpuCtx->aRegs[i].au32[2] = paRegs[i].au16[4];
9424 pFpuCtx->aRegs[i].au32[3] = 0;
9425 }
9426
9427 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
9428 if (rcStrict != VINF_SUCCESS)
9429 return rcStrict;
9430
9431 iemHlpUsedFpu(pVCpu);
9432 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9433 return VINF_SUCCESS;
9434}
9435
9436
9437/**
9438 * Implements 'FLDCW'.
9439 *
9440 * @param u16Fcw The new FCW.
9441 */
9442IEM_CIMPL_DEF_1(iemCImpl_fldcw, uint16_t, u16Fcw)
9443{
9444 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9445
9446 /** @todo Testcase: Check what happens when trying to load X86_FCW_PC_RSVD. */
9447 /** @todo Testcase: Try see what happens when trying to set undefined bits
9448 * (other than 6 and 7). Currently ignoring them. */
9449 /** @todo Testcase: Test that it raises and loweres the FPU exception bits
9450 * according to FSW. (This is what is currently implemented.) */
9451 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9452 pFpuCtx->FCW = u16Fcw & ~X86_FCW_ZERO_MASK;
9453#ifdef LOG_ENABLED
9454 uint16_t fOldFsw = pFpuCtx->FSW;
9455#endif
9456 iemFpuRecalcExceptionStatus(pFpuCtx);
9457#ifdef LOG_ENABLED
9458 if ((pFpuCtx->FSW & X86_FSW_ES) ^ (fOldFsw & X86_FSW_ES))
9459 Log11(("fldcw: %04x:%08RX64: %s FPU exception (FCW=%#x, FSW %#x -> %#x)\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
9460 fOldFsw & X86_FSW_ES ? "Supressed" : "Raised", pFpuCtx->FCW, fOldFsw, pFpuCtx->FSW));
9461#endif
9462
9463 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
9464 iemHlpUsedFpu(pVCpu);
9465 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9466 return VINF_SUCCESS;
9467}
9468
9469
9470
9471/**
9472 * Implements the underflow case of fxch.
9473 *
9474 * @param iStReg The other stack register.
9475 */
9476IEM_CIMPL_DEF_1(iemCImpl_fxch_underflow, uint8_t, iStReg)
9477{
9478 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9479
9480 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9481 unsigned const iReg1 = X86_FSW_TOP_GET(pFpuCtx->FSW);
9482 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
9483 Assert(!(RT_BIT(iReg1) & pFpuCtx->FTW) || !(RT_BIT(iReg2) & pFpuCtx->FTW));
9484
9485 /** @todo Testcase: fxch underflow. Making assumptions that underflowed
9486 * registers are read as QNaN and then exchanged. This could be
9487 * wrong... */
9488 if (pFpuCtx->FCW & X86_FCW_IM)
9489 {
9490 if (RT_BIT(iReg1) & pFpuCtx->FTW)
9491 {
9492 if (RT_BIT(iReg2) & pFpuCtx->FTW)
9493 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
9494 else
9495 pFpuCtx->aRegs[0].r80 = pFpuCtx->aRegs[iStReg].r80;
9496 iemFpuStoreQNan(&pFpuCtx->aRegs[iStReg].r80);
9497 }
9498 else
9499 {
9500 pFpuCtx->aRegs[iStReg].r80 = pFpuCtx->aRegs[0].r80;
9501 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
9502 }
9503 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
9504 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
9505 }
9506 else
9507 {
9508 /* raise underflow exception, don't change anything. */
9509 pFpuCtx->FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_XCPT_MASK);
9510 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
9511 Log11(("fxch: %04x:%08RX64: Underflow exception (FSW=%#x)\n",
9512 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pFpuCtx->FSW));
9513 }
9514
9515 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx);
9516 iemHlpUsedFpu(pVCpu);
9517 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9518 return VINF_SUCCESS;
9519}
9520
9521
9522/**
9523 * Implements 'FCOMI', 'FCOMIP', 'FUCOMI', and 'FUCOMIP'.
9524 *
9525 * @param iStReg The other stack register.
9526 * @param pfnAImpl The assembly comparison implementation.
9527 * @param fPop Whether we should pop the stack when done or not.
9528 */
9529IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop)
9530{
9531 Assert(iStReg < 8);
9532 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9533
9534 /*
9535 * Raise exceptions.
9536 */
9537 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))
9538 return iemRaiseDeviceNotAvailable(pVCpu);
9539
9540 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9541 uint16_t u16Fsw = pFpuCtx->FSW;
9542 if (u16Fsw & X86_FSW_ES)
9543 return iemRaiseMathFault(pVCpu);
9544
9545 /*
9546 * Check if any of the register accesses causes #SF + #IA.
9547 */
9548 unsigned const iReg1 = X86_FSW_TOP_GET(u16Fsw);
9549 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
9550 if ((pFpuCtx->FTW & (RT_BIT(iReg1) | RT_BIT(iReg2))) == (RT_BIT(iReg1) | RT_BIT(iReg2)))
9551 {
9552 uint32_t u32Eflags = pfnAImpl(pFpuCtx, &u16Fsw, &pFpuCtx->aRegs[0].r80, &pFpuCtx->aRegs[iStReg].r80);
9553
9554 pFpuCtx->FSW &= ~X86_FSW_C1;
9555 pFpuCtx->FSW |= u16Fsw & ~X86_FSW_TOP_MASK;
9556 if ( !(u16Fsw & X86_FSW_IE)
9557 || (pFpuCtx->FCW & X86_FCW_IM) )
9558 {
9559 pVCpu->cpum.GstCtx.eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
9560 pVCpu->cpum.GstCtx.eflags.u |= u32Eflags & (X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
9561 }
9562 }
9563 else if (pFpuCtx->FCW & X86_FCW_IM)
9564 {
9565 /* Masked underflow. */
9566 pFpuCtx->FSW &= ~X86_FSW_C1;
9567 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF;
9568 pVCpu->cpum.GstCtx.eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
9569 pVCpu->cpum.GstCtx.eflags.u |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF;
9570 }
9571 else
9572 {
9573 /* Raise underflow - don't touch EFLAGS or TOP. */
9574 pFpuCtx->FSW &= ~X86_FSW_C1;
9575 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
9576 Log11(("fxch: %04x:%08RX64: Raising IE+SF exception (FSW=%#x)\n",
9577 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pFpuCtx->FSW));
9578 fPop = false;
9579 }
9580
9581 /*
9582 * Pop if necessary.
9583 */
9584 if (fPop)
9585 {
9586 pFpuCtx->FTW &= ~RT_BIT(iReg1);
9587 iemFpuStackIncTop(pVCpu);
9588 }
9589
9590 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx);
9591 iemHlpUsedFpu(pVCpu);
9592 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9593 return VINF_SUCCESS;
9594}
9595
9596/** @} */
9597
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