VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp@ 97705

Last change on this file since 97705 was 97705, checked in by vboxsync, 2 years ago

VMM/IEM,DBGF,CPUM: Do debugger I/O breakpoints via the internal EFLAGS bits too. Seems we might need two bits, so had to shift the internal bits down from 24 to 22. bugref:9898
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1/* $Id: DBGFAll.cpp 97705 2022-11-29 14:11:49Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, All Context Code.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DBGF
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/dbgf.h>
35#include "DBGFInternal.h"
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/vmcc.h>
38#include <VBox/err.h>
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/stdarg.h>
42
43
44/*
45 * Check the read-only VM members.
46 */
47AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSoftIntBreakpoints, VM, dbgf.ro.bmSoftIntBreakpoints);
48AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmHardIntBreakpoints, VM, dbgf.ro.bmHardIntBreakpoints);
49AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.bmSelectedEvents, VM, dbgf.ro.bmSelectedEvents);
50AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cHardIntBreakpoints, VM, dbgf.ro.cHardIntBreakpoints);
51AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSoftIntBreakpoints, VM, dbgf.ro.cSoftIntBreakpoints);
52AssertCompileMembersSameSizeAndOffset(VM, dbgf.s.cSelectedEvents, VM, dbgf.ro.cSelectedEvents);
53
54
55/**
56 * Gets the hardware breakpoint configuration as DR7.
57 *
58 * @returns DR7 from the DBGF point of view.
59 * @param pVM The cross context VM structure.
60 */
61VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
62{
63 RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
64 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); i++)
65 {
66 if ( pVM->dbgf.s.aHwBreakpoints[i].fEnabled
67 && pVM->dbgf.s.aHwBreakpoints[i].hBp != NIL_DBGFBP)
68 {
69 static const uint8_t s_au8Sizes[8] =
70 {
71 X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_WORD, X86_DR7_LEN_BYTE,
72 X86_DR7_LEN_DWORD,X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_QWORD
73 };
74 uDr7 |= X86_DR7_G(i)
75 | X86_DR7_RW(i, pVM->dbgf.s.aHwBreakpoints[i].fType)
76 | X86_DR7_LEN(i, s_au8Sizes[pVM->dbgf.s.aHwBreakpoints[i].cb]);
77 }
78 }
79 return uDr7;
80}
81
82
83/**
84 * Gets the address of the hardware breakpoint number 0.
85 *
86 * @returns DR0 from the DBGF point of view.
87 * @param pVM The cross context VM structure.
88 */
89VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM)
90{
91 return pVM->dbgf.s.aHwBreakpoints[0].GCPtr;
92}
93
94
95/**
96 * Gets the address of the hardware breakpoint number 1.
97 *
98 * @returns DR1 from the DBGF point of view.
99 * @param pVM The cross context VM structure.
100 */
101VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM)
102{
103 return pVM->dbgf.s.aHwBreakpoints[1].GCPtr;
104}
105
106
107/**
108 * Gets the address of the hardware breakpoint number 2.
109 *
110 * @returns DR2 from the DBGF point of view.
111 * @param pVM The cross context VM structure.
112 */
113VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM)
114{
115 return pVM->dbgf.s.aHwBreakpoints[2].GCPtr;
116}
117
118
119/**
120 * Gets the address of the hardware breakpoint number 3.
121 *
122 * @returns DR3 from the DBGF point of view.
123 * @param pVM The cross context VM structure.
124 */
125VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM)
126{
127 return pVM->dbgf.s.aHwBreakpoints[3].GCPtr;
128}
129
130
131/**
132 * Checks if any of the hardware breakpoints are armed.
133 *
134 * @returns true if armed, false if not.
135 * @param pVM The cross context VM structure.
136 * @remarks Don't call this from CPUMRecalcHyperDRx!
137 */
138VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM)
139{
140 return pVM->dbgf.s.cEnabledHwBreakpoints > 0;
141}
142
143
144/**
145 * Checks if any of the hardware I/O breakpoints are armed.
146 *
147 * @returns true if armed, false if not.
148 * @param pVM The cross context VM structure.
149 * @remarks Don't call this from CPUMRecalcHyperDRx!
150 */
151VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM)
152{
153 return pVM->dbgf.s.cEnabledHwIoBreakpoints > 0;
154}
155
156
157/**
158 * Checks if any INT3 breakpoints are armed.
159 *
160 * @returns true if armed, false if not.
161 * @param pVM The cross context VM structure.
162 * @remarks Don't call this from CPUMRecalcHyperDRx!
163 */
164VMM_INT_DECL(bool) DBGFBpIsInt3Armed(PVM pVM)
165{
166 /** @todo There was a todo here and returning false when I (bird) removed
167 * VBOX_WITH_LOTS_OF_DBGF_BPS, so this might not be correct. */
168 return pVM->dbgf.s.cEnabledInt3Breakpoints > 0;
169}
170
171
172/**
173 * Checks instruction boundrary for guest or hypervisor hardware breakpoints.
174 *
175 * @returns Strict VBox status code. May return DRx register import errors in
176 * addition to the ones detailed.
177 * @retval VINF_SUCCESS no breakpoint.
178 * @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
179 * @retval VINF_EM_RAW_GUEST_TRAP caller must trigger \#DB trap, DR6 and DR7
180 * have been updated appropriately.
181 *
182 * @param pVM The cross context VM structure.
183 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
184 * @param GCPtrPC The unsegmented PC address.
185 */
186VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckInstruction(PVMCC pVM, PVMCPUCC pVCpu, RTGCPTR GCPtrPC)
187{
188 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR7);
189
190 /*
191 * Check hyper breakpoints first as the VMM debugger has priority over
192 * the guest.
193 */
194 if (pVM->dbgf.s.cEnabledHwBreakpoints > 0)
195 for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
196 {
197 if ( pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr != GCPtrPC
198 || pVM->dbgf.s.aHwBreakpoints[iBp].fType != X86_DR7_RW_EO
199 || pVM->dbgf.s.aHwBreakpoints[iBp].cb != 1
200 || !pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
201 || pVM->dbgf.s.aHwBreakpoints[iBp].hBp == NIL_DBGFBP)
202 { /*likely*/ }
203 else
204 {
205 /* (See also DBGFRZTrap01Handler.) */
206 pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
207 pVCpu->dbgf.s.fSingleSteppingRaw = false;
208
209 LogFlow(("DBGFBpCheckInstruction: hit hw breakpoint %u at %04x:%RGv (%RGv)\n",
210 iBp, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPtrPC));
211 return VINF_EM_DBG_BREAKPOINT;
212 }
213 }
214
215 /*
216 * Check the guest.
217 */
218 uint32_t const fDr7 = (uint32_t)pVCpu->cpum.GstCtx.dr[7];
219 if (X86_DR7_ANY_EO_ENABLED(fDr7))
220 {
221 /*
222 * The CPU (10980XE & 6700K at least) will set the DR6.BPx bits for any
223 * DRx that matches the current PC and is configured as an execution
224 * breakpoint (RWx=EO, LENx=1byte). They don't have to be enabled,
225 * however one that is enabled must match for the #DB to be raised and
226 * DR6 to be modified, of course.
227 */
228 CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
229 uint32_t fMatched = 0;
230 uint32_t fEnabled = 0;
231 for (unsigned iBp = 0, uBpMask = 1; iBp < 4; iBp++, uBpMask <<= 1)
232 if (X86_DR7_IS_EO_CFG(fDr7, iBp))
233 {
234 if (fDr7 & X86_DR7_L_G(iBp))
235 fEnabled |= uBpMask;
236 if (pVCpu->cpum.GstCtx.dr[iBp] == GCPtrPC)
237 fMatched |= uBpMask;
238 }
239 if (!(fEnabled & fMatched))
240 { /*likely*/ }
241 else if (fEnabled & fMatched)
242 {
243 /*
244 * Update DR6 and DR7.
245 *
246 * See "AMD64 Architecture Programmer's Manual Volume 2", chapter
247 * 13.1.1.3 for details on DR6 bits. The basics is that the B0..B3
248 * bits are always cleared while the others must be cleared by software.
249 *
250 * The following sub chapters says the GD bit is always cleared when
251 * generating a #DB so the handler can safely access the debug registers.
252 */
253 CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_DR6);
254 pVCpu->cpum.GstCtx.dr[6] &= ~X86_DR6_B_MASK;
255 pVCpu->cpum.GstCtx.dr[6] |= fMatched; /* All matched */
256 pVCpu->cpum.GstCtx.dr[7] &= ~X86_DR7_GD;
257 LogFlow(("DBGFBpCheckInstruction: hit hw breakpoints %#x at %04x:%RGv (%RGv)\n",
258 fMatched, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPtrPC));
259 return VINF_EM_RAW_GUEST_TRAP;
260 }
261 }
262 return VINF_SUCCESS;
263}
264
265
266/**
267 * Checks I/O access for guest or hypervisor hardware breakpoints.
268 *
269 * @returns Strict VBox status code
270 * @retval VINF_SUCCESS no breakpoint.
271 * @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
272 * @retval VINF_EM_RAW_GUEST_TRAP guest breakpoint triggered, DR6 and DR7 have
273 * been updated appropriately.
274 *
275 * @param pVM The cross context VM structure.
276 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
277 * @param pCtx The CPU context for the calling EMT.
278 * @param uIoPort The I/O port being accessed.
279 * @param cbValue The size/width of the access, in bytes.
280 */
281VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue)
282{
283 uint32_t const uIoPortFirst = uIoPort;
284 uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
285
286 /*
287 * Check hyper breakpoints first as the VMM debugger has priority over
288 * the guest.
289 */
290 if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
291 {
292 for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
293 {
294 if ( pVM->dbgf.s.aHwBreakpoints[iBp].fType == X86_DR7_RW_IO
295 && pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
296 && pVM->dbgf.s.aHwBreakpoints[iBp].hBp != NIL_DBGFBP)
297 {
298 uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
299 uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr & ~(uint64_t)(cbReg - 1);
300 uint64_t uDrXLast = uDrXFirst + cbReg - 1;
301 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
302 {
303 /* (See also DBGFRZTrap01Handler.) */
304 pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
305 pVCpu->dbgf.s.fSingleSteppingRaw = false;
306
307 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
308 iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
309 return VINF_EM_DBG_BREAKPOINT;
310 }
311 }
312 }
313 }
314
315 /*
316 * Check the guest.
317 */
318 uint32_t const uDr7 = pCtx->dr[7];
319 if ( (uDr7 & X86_DR7_ENABLED_MASK)
320 && X86_DR7_ANY_RW_IO(uDr7)
321 && (pCtx->cr4 & X86_CR4_DE) )
322 {
323 for (unsigned iBp = 0; iBp < 4; iBp++)
324 {
325 if ( (uDr7 & X86_DR7_L_G(iBp))
326 && X86_DR7_GET_RW(uDr7, iBp) == X86_DR7_RW_IO)
327 {
328 /* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
329 static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
330 uint8_t cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(uDr7, iBp)];
331 uint64_t uDrXFirst = pCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
332 uint64_t uDrXLast = uDrXFirst + cbInvAlign;
333
334 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
335 {
336 /*
337 * Update DR6 and DR7.
338 *
339 * See "AMD64 Architecture Programmer's Manual Volume 2",
340 * chapter 13.1.1.3 for details on DR6 bits. The basics is
341 * that the B0..B3 bits are always cleared while the others
342 * must be cleared by software.
343 *
344 * The following sub chapters says the GD bit is always
345 * cleared when generating a #DB so the handler can safely
346 * access the debug registers.
347 */
348 pCtx->dr[6] &= ~X86_DR6_B_MASK;
349 pCtx->dr[6] |= X86_DR6_B(iBp);
350 pCtx->dr[7] &= ~X86_DR7_GD;
351 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
352 iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
353 return VINF_EM_RAW_GUEST_TRAP;
354 }
355 }
356 }
357 }
358 return VINF_SUCCESS;
359}
360
361
362/**
363 * Checks I/O access for guest or hypervisor hardware breakpoints.
364 *
365 * Caller must make sure DR0-3 and DR7 are present in the CPU context before
366 * calling this function.
367 *
368 * @returns CPUMCTX_DBG_DBGF_BP, CPUMCTX_DBG_HIT_DRX_MASK, or 0 (no match).
369 *
370 * @param pVM The cross context VM structure.
371 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
372 * @param uIoPort The I/O port being accessed.
373 * @param cbValue The size/width of the access, in bytes.
374 */
375VMM_INT_DECL(uint32_t) DBGFBpCheckIo2(PVMCC pVM, PVMCPUCC pVCpu, RTIOPORT uIoPort, uint8_t cbValue)
376{
377 uint32_t const uIoPortFirst = uIoPort;
378 uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
379
380 /*
381 * Check hyper breakpoints first as the VMM debugger has priority over
382 * the guest.
383 */
384 if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
385 for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
386 {
387 if ( pVM->dbgf.s.aHwBreakpoints[iBp].fType == X86_DR7_RW_IO
388 && pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
389 && pVM->dbgf.s.aHwBreakpoints[iBp].hBp != NIL_DBGFBP)
390 {
391 uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
392 uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr & ~(uint64_t)(cbReg - 1);
393 uint64_t uDrXLast = uDrXFirst + cbReg - 1;
394 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
395 {
396 /* (See also DBGFRZTrap01Handler.) */
397 pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
398 pVCpu->dbgf.s.fSingleSteppingRaw = false;
399
400 LogFlow(("DBGFBpCheckIo2: hit hw breakpoint %d at %04x:%RGv (iop %#x L %u)\n",
401 iBp, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uIoPort, cbValue));
402 return CPUMCTX_DBG_DBGF_BP;
403 }
404 }
405 }
406
407 /*
408 * Check the guest.
409 */
410 uint32_t const fDr7 = pVCpu->cpum.GstCtx.dr[7];
411 if ( (fDr7 & X86_DR7_ENABLED_MASK)
412 && X86_DR7_ANY_RW_IO(fDr7)
413 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE) )
414 {
415 uint32_t fEnabled = 0;
416 uint32_t fMatched = 0;
417 for (unsigned iBp = 0, uBpMask = 1; iBp < 4; iBp++, uBpMask <<= 1)
418 {
419 if (fDr7 & X86_DR7_L_G(iBp))
420 fEnabled |= uBpMask;
421 if (X86_DR7_GET_RW(fDr7, iBp) == X86_DR7_RW_IO)
422 {
423 /* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
424 static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
425 uint8_t const cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(fDr7, iBp)];
426 uint64_t const uDrXFirst = pVCpu->cpum.GstCtx.dr[iBp] & ~(uint64_t)cbInvAlign;
427 uint64_t const uDrXLast = uDrXFirst + cbInvAlign;
428 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
429 fMatched |= uBpMask;
430 }
431 }
432 if (fEnabled & fMatched)
433 {
434 LogFlow(("DBGFBpCheckIo2: hit hw breakpoint %#x at %04x:%RGv (iop %#x L %u)\n",
435 fMatched, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uIoPort, cbValue));
436 return fMatched << CPUMCTX_DBG_HIT_DRX_SHIFT;
437 }
438 }
439
440 return 0;
441}
442
443
444/**
445 * Returns the single stepping state for a virtual CPU.
446 *
447 * @returns stepping (true) or not (false).
448 *
449 * @param pVCpu The cross context virtual CPU structure.
450 */
451VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
452{
453 return pVCpu->dbgf.s.fSingleSteppingRaw;
454}
455
456
457/**
458 * Checks if the specified generic event is enabled or not.
459 *
460 * @returns true / false.
461 * @param pVM The cross context VM structure.
462 * @param enmEvent The generic event being raised.
463 * @param uEventArg The argument of that event.
464 */
465DECLINLINE(bool) dbgfEventIsGenericWithArgEnabled(PVM pVM, DBGFEVENTTYPE enmEvent, uint64_t uEventArg)
466{
467 if (DBGF_IS_EVENT_ENABLED(pVM, enmEvent))
468 {
469 switch (enmEvent)
470 {
471 case DBGFEVENT_INTERRUPT_HARDWARE:
472 AssertReturn(uEventArg < 256, false);
473 return ASMBitTest(pVM->dbgf.s.bmHardIntBreakpoints, (uint32_t)uEventArg);
474
475 case DBGFEVENT_INTERRUPT_SOFTWARE:
476 AssertReturn(uEventArg < 256, false);
477 return ASMBitTest(pVM->dbgf.s.bmSoftIntBreakpoints, (uint32_t)uEventArg);
478
479 default:
480 return true;
481
482 }
483 }
484 return false;
485}
486
487
488/**
489 * Raises a generic debug event if enabled and not being ignored.
490 *
491 * @returns Strict VBox status code.
492 * @retval VINF_EM_DBG_EVENT if the event was raised and the caller should
493 * return ASAP to the debugger (via EM). We set VMCPU_FF_DBGF so, it
494 * is okay not to pass this along in some situations.
495 * @retval VINF_SUCCESS if the event was disabled or ignored.
496 *
497 * @param pVM The cross context VM structure.
498 * @param pVCpu The cross context virtual CPU structure.
499 * @param enmEvent The generic event being raised.
500 * @param enmCtx The context in which this event is being raised.
501 * @param cArgs Number of arguments (0 - 6).
502 * @param ... Event arguments.
503 *
504 * @thread EMT(pVCpu)
505 */
506VMM_INT_DECL(VBOXSTRICTRC) DBGFEventGenericWithArgs(PVM pVM, PVMCPU pVCpu, DBGFEVENTTYPE enmEvent, DBGFEVENTCTX enmCtx,
507 unsigned cArgs, ...)
508{
509 Assert(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[0].Event.u.Generic.auArgs));
510
511 /*
512 * Is it enabled.
513 */
514 va_list va;
515 va_start(va, cArgs);
516 uint64_t uEventArg0 = cArgs ? va_arg(va, uint64_t) : 0;
517 if (dbgfEventIsGenericWithArgEnabled(pVM, enmEvent, uEventArg0))
518 {
519 /*
520 * Any events on the stack. Should the incoming event be ignored?
521 */
522 uint64_t const rip = CPUMGetGuestRIP(pVCpu);
523 uint32_t i = pVCpu->dbgf.s.cEvents;
524 if (i > 0)
525 {
526 while (i-- > 0)
527 {
528 if ( pVCpu->dbgf.s.aEvents[i].Event.enmType == enmEvent
529 && pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE
530 && pVCpu->dbgf.s.aEvents[i].rip == rip)
531 {
532 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_RESTORABLE;
533 va_end(va);
534 return VINF_SUCCESS;
535 }
536 Assert(pVCpu->dbgf.s.aEvents[i].enmState != DBGFEVENTSTATE_CURRENT);
537 }
538
539 /*
540 * Trim the event stack.
541 */
542 i = pVCpu->dbgf.s.cEvents;
543 while (i-- > 0)
544 {
545 if ( pVCpu->dbgf.s.aEvents[i].rip == rip
546 && ( pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_RESTORABLE
547 || pVCpu->dbgf.s.aEvents[i].enmState == DBGFEVENTSTATE_IGNORE) )
548 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_IGNORE;
549 else
550 {
551 if (i + 1 != pVCpu->dbgf.s.cEvents)
552 memmove(&pVCpu->dbgf.s.aEvents[i], &pVCpu->dbgf.s.aEvents[i + 1],
553 (pVCpu->dbgf.s.cEvents - i) * sizeof(pVCpu->dbgf.s.aEvents));
554 pVCpu->dbgf.s.cEvents--;
555 }
556 }
557
558 i = pVCpu->dbgf.s.cEvents;
559 AssertStmt(i < RT_ELEMENTS(pVCpu->dbgf.s.aEvents), i = RT_ELEMENTS(pVCpu->dbgf.s.aEvents) - 1);
560 }
561
562 /*
563 * Push the event.
564 */
565 pVCpu->dbgf.s.aEvents[i].enmState = DBGFEVENTSTATE_CURRENT;
566 pVCpu->dbgf.s.aEvents[i].rip = rip;
567 pVCpu->dbgf.s.aEvents[i].Event.enmType = enmEvent;
568 pVCpu->dbgf.s.aEvents[i].Event.enmCtx = enmCtx;
569 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.cArgs = cArgs;
570 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[0] = uEventArg0;
571 if (cArgs > 1)
572 {
573 AssertStmt(cArgs < RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs),
574 cArgs = RT_ELEMENTS(pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs));
575 for (unsigned iArg = 1; iArg < cArgs; iArg++)
576 pVCpu->dbgf.s.aEvents[i].Event.u.Generic.auArgs[iArg] = va_arg(va, uint64_t);
577 }
578 pVCpu->dbgf.s.cEvents = i + 1;
579
580 VMCPU_FF_SET(pVCpu, VMCPU_FF_DBGF);
581 va_end(va);
582 return VINF_EM_DBG_EVENT;
583 }
584
585 va_end(va);
586 return VINF_SUCCESS;
587}
588
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