VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp@ 47681

Last change on this file since 47681 was 47681, checked in by vboxsync, 12 years ago

VMM: I/O breakpoints.
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1/* $Id: DBGFAll.cpp 47681 2013-08-12 22:51:55Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, All Context Code.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_DBGF
23#include <VBox/vmm/dbgf.h>
24#include "DBGFInternal.h"
25#include <VBox/vmm/vm.h>
26#include <VBox/err.h>
27#include <iprt/assert.h>
28
29
30/**
31 * Gets the hardware breakpoint configuration as DR7.
32 *
33 * @returns DR7 from the DBGF point of view.
34 * @param pVM Pointer to the VM.
35 */
36VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR7(PVM pVM)
37{
38 RTGCUINTREG uDr7 = X86_DR7_GD | X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
39 PDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
40 unsigned cLeft = RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints);
41 while (cLeft-- > 0)
42 {
43 if ( pBp->enmType == DBGFBPTYPE_REG
44 && pBp->fEnabled)
45 {
46 static const uint8_t s_au8Sizes[8] =
47 {
48 X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_WORD, X86_DR7_LEN_BYTE,
49 X86_DR7_LEN_DWORD,X86_DR7_LEN_BYTE, X86_DR7_LEN_BYTE, X86_DR7_LEN_QWORD
50 };
51 uDr7 |= X86_DR7_G(pBp->u.Reg.iReg)
52 | X86_DR7_RW(pBp->u.Reg.iReg, pBp->u.Reg.fType)
53 | X86_DR7_LEN(pBp->u.Reg.iReg, s_au8Sizes[pBp->u.Reg.cb]);
54 }
55 pBp++;
56 }
57 return uDr7;
58}
59
60
61/**
62 * Gets the address of the hardware breakpoint number 0.
63 *
64 * @returns DR0 from the DBGF point of view.
65 * @param pVM Pointer to the VM.
66 */
67VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR0(PVM pVM)
68{
69 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[0];
70 Assert(pBp->u.Reg.iReg == 0);
71 return pBp->GCPtr;
72}
73
74
75/**
76 * Gets the address of the hardware breakpoint number 1.
77 *
78 * @returns DR1 from the DBGF point of view.
79 * @param pVM Pointer to the VM.
80 */
81VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR1(PVM pVM)
82{
83 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[1];
84 Assert(pBp->u.Reg.iReg == 1);
85 return pBp->GCPtr;
86}
87
88
89/**
90 * Gets the address of the hardware breakpoint number 2.
91 *
92 * @returns DR2 from the DBGF point of view.
93 * @param pVM Pointer to the VM.
94 */
95VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR2(PVM pVM)
96{
97 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[2];
98 Assert(pBp->u.Reg.iReg == 2);
99 return pBp->GCPtr;
100}
101
102
103/**
104 * Gets the address of the hardware breakpoint number 3.
105 *
106 * @returns DR3 from the DBGF point of view.
107 * @param pVM Pointer to the VM.
108 */
109VMM_INT_DECL(RTGCUINTREG) DBGFBpGetDR3(PVM pVM)
110{
111 PCDBGFBP pBp = &pVM->dbgf.s.aHwBreakpoints[3];
112 Assert(pBp->u.Reg.iReg == 3);
113 return pBp->GCPtr;
114}
115
116
117/**
118 * Checks if any of the hardware breakpoints are armed.
119 *
120 * @returns true if armed, false if not.
121 * @param pVM The cross context VM structure.
122 */
123VMM_INT_DECL(bool) DBGFBpIsHwArmed(PVM pVM)
124{
125 Assert(RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints) == 4);
126 return (pVM->dbgf.s.aHwBreakpoints[0].fEnabled && pVM->dbgf.s.aHwBreakpoints[0].enmType == DBGFBPTYPE_REG)
127 || (pVM->dbgf.s.aHwBreakpoints[1].fEnabled && pVM->dbgf.s.aHwBreakpoints[1].enmType == DBGFBPTYPE_REG)
128 || (pVM->dbgf.s.aHwBreakpoints[2].fEnabled && pVM->dbgf.s.aHwBreakpoints[2].enmType == DBGFBPTYPE_REG)
129 || (pVM->dbgf.s.aHwBreakpoints[3].fEnabled && pVM->dbgf.s.aHwBreakpoints[3].enmType == DBGFBPTYPE_REG);
130}
131
132
133/**
134 * Checks if any of the hardware I/O breakpoints are armed.
135 *
136 * @returns true if armed, false if not.
137 * @param pVM The cross context VM structure.
138 */
139VMM_INT_DECL(bool) DBGFBpIsHwIoArmed(PVM pVM)
140{
141 Assert(RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints) == 4);
142 /** @todo cache this! */
143 return ( pVM->dbgf.s.aHwBreakpoints[0].u.Reg.fType == X86_DR7_RW_IO
144 && pVM->dbgf.s.aHwBreakpoints[0].fEnabled
145 && pVM->dbgf.s.aHwBreakpoints[0].enmType == DBGFBPTYPE_REG
146 )
147 || ( pVM->dbgf.s.aHwBreakpoints[1].u.Reg.fType == X86_DR7_RW_IO
148 && pVM->dbgf.s.aHwBreakpoints[1].fEnabled
149 && pVM->dbgf.s.aHwBreakpoints[1].enmType == DBGFBPTYPE_REG
150 )
151 || ( pVM->dbgf.s.aHwBreakpoints[2].u.Reg.fType == X86_DR7_RW_IO
152 && pVM->dbgf.s.aHwBreakpoints[2].fEnabled
153 && pVM->dbgf.s.aHwBreakpoints[2].enmType == DBGFBPTYPE_REG
154 )
155 || ( pVM->dbgf.s.aHwBreakpoints[3].u.Reg.fType == X86_DR7_RW_IO
156 && pVM->dbgf.s.aHwBreakpoints[3].fEnabled
157 && pVM->dbgf.s.aHwBreakpoints[3].enmType == DBGFBPTYPE_REG
158 );
159}
160
161
162/**
163 * Checks I/O access for guest or hypervisor breakpoints.
164 *
165 * @returns Strict VBox status code
166 * @retval VINF_SUCCESS no breakpoint.
167 * @retval VINF_EM_DBG_BREAKPOINT hypervisor breakpoint triggered.
168 * @retval VINF_EM_RAW_GUEST_TRAP guest breakpoint triggered, DR6 and DR7 have
169 * been updated appropriately.
170 *
171 * @param pVM The cross context VM structure.
172 * @param pVCpu The cross context CPU structure for the calling EMT.
173 * @param pCtx The CPU context for the calling EMT.
174 * @param uIoPort The I/O port being accessed.
175 * @param cbValue The size/width of the access, in bytes.
176 */
177VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue)
178{
179 static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
180 uint32_t const uIoPortFirst = uIoPort;
181 uint32_t const uIoPortLast = uIoPortFirst + cbValue - 1;
182
183
184 /*
185 * Check hyper breakpoints first as the VMM debugger has priority over
186 * the guest.
187 */
188 for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
189 {
190 if ( pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.fType == X86_DR7_RW_IO
191 && pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
192 && pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG )
193 {
194 uint8_t cbReg = pVM->dbgf.s.aHwBreakpoints[iBp].u.Reg.cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
195 uint64_t uDrXFirst = pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr & ~(uint64_t)(cbReg - 1);
196 uint64_t uDrXLast = uDrXFirst + cbReg - 1;
197 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
198 {
199 /* (See also DBGFRZTrap01Handler.) */
200 pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
201 pVCpu->dbgf.s.fSingleSteppingRaw = false;
202
203 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
204 pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
205 return VINF_EM_DBG_BREAKPOINT;
206 }
207 }
208 }
209
210 /*
211 * Check the guest.
212 */
213 uint32_t const uDr7 = pCtx->dr[7];
214 if ( (uDr7 & X86_DR7_ENABLED_MASK)
215 && X86_DR7_ANY_RW_IO(uDr7)
216 && (pCtx->cr4 & X86_CR4_DE) )
217 {
218 for (unsigned iBp = 0; iBp < 4; iBp++)
219 {
220 if ( (uDr7 & X86_DR7_L_G(iBp))
221 && X86_DR7_GET_RW(uDr7, iBp) == X86_DR7_RW_IO)
222 {
223 /* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
224 static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
225 uint8_t cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(uDr7, iBp)];
226 uint64_t uDrXFirst = pCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
227 uint64_t uDrXLast = uDrXFirst + cbInvAlign;
228
229 if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
230 {
231 /*
232 * Update DR6 and DR7.
233 *
234 * See "AMD64 Architecture Programmer's Manual Volume 2",
235 * chapter 13.1.1.3 for details on DR6 bits. The basics is
236 * that the B0..B3 bits are always cleared while the others
237 * must be cleared by software.
238 *
239 * The following section says the GD bit is always cleared
240 * when generating a #DB so the handler can safely access
241 * the debug registers.
242 */
243 pCtx->dr[6] &= ~X86_DR6_B_MASK;
244 pCtx->dr[6] |= X86_DR6_B(iBp);
245 pCtx->dr[7] &= ~X86_DR7_GD;
246 LogFlow(("DBGFBpCheckIo: hit hw breakpoint %d at %04x:%RGv (iop %#x)\n",
247 pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pCtx->cs.Sel, pCtx->rip, uIoPort));
248 return VINF_EM_RAW_GUEST_TRAP;
249 }
250 }
251 }
252 }
253 return VINF_SUCCESS;
254}
255
256
257/**
258 * Returns the single stepping state for a virtual CPU.
259 *
260 * @returns stepping (true) or not (false).
261 *
262 * @param pVCpu Pointer to the VMCPU.
263 */
264VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu)
265{
266 return pVCpu->dbgf.s.fSingleSteppingRaw;
267}
268
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