[23] | 1 | /* $Id: CPUMAllRegs.cpp 100184 2023-06-16 06:51:39Z vboxsync $ */
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[1] | 2 | /** @file
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[12657] | 3 | * CPUM - CPU Monitor(/Manager) - Getters and Setters.
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[1] | 4 | */
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| 5 |
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| 6 | /*
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[98103] | 7 | * Copyright (C) 2006-2023 Oracle and/or its affiliates.
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[1] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[1] | 26 | */
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| 27 |
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| 28 |
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[57358] | 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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[1] | 32 | #define LOG_GROUP LOG_GROUP_CPUM
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[35346] | 33 | #include <VBox/vmm/cpum.h>
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| 34 | #include <VBox/vmm/dbgf.h>
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[64655] | 35 | #include <VBox/vmm/apic.h>
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[35346] | 36 | #include <VBox/vmm/pgm.h>
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| 37 | #include <VBox/vmm/mm.h>
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[45276] | 38 | #include <VBox/vmm/em.h>
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[80064] | 39 | #include <VBox/vmm/nem.h>
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| 40 | #include <VBox/vmm/hm.h>
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[1] | 41 | #include "CPUMInternal.h"
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[80253] | 42 | #include <VBox/vmm/vmcc.h>
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[1] | 43 | #include <VBox/err.h>
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| 44 | #include <VBox/dis.h>
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| 45 | #include <VBox/log.h>
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[43387] | 46 | #include <VBox/vmm/hm.h>
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[35346] | 47 | #include <VBox/vmm/tm.h>
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[1] | 48 | #include <iprt/assert.h>
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[772] | 49 | #include <iprt/asm.h>
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[93725] | 50 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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| 51 | # include <iprt/asm-amd64-x86.h>
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| 52 | #endif
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[13960] | 53 | #ifdef IN_RING3
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[72488] | 54 | # include <iprt/thread.h>
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[13960] | 55 | #endif
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[1] | 56 |
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| 57 | /** Disable stack frame pointer generation here. */
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[62440] | 58 | #if defined(_MSC_VER) && !defined(DEBUG) && defined(RT_ARCH_X86)
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[1] | 59 | # pragma optimize("y", off)
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| 60 | #endif
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| 61 |
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[55229] | 62 | AssertCompile2MemberOffsets(VM, cpum.s.GuestFeatures, cpum.ro.GuestFeatures);
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[1] | 63 |
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[55229] | 64 |
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[57358] | 65 | /*********************************************************************************************************************************
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| 66 | * Defined Constants And Macros *
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| 67 | *********************************************************************************************************************************/
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[1] | 68 | /**
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[42165] | 69 | * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
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| 70 | *
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| 71 | * @returns Pointer to the Virtual CPU.
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| 72 | * @param a_pGuestCtx Pointer to the guest context.
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| 73 | */
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| 74 | #define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
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| 75 |
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| 76 | /**
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| 77 | * Lazily loads the hidden parts of a selector register when using raw-mode.
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| 78 | */
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[80050] | 79 | #define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
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| 80 | Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg))
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[42165] | 81 |
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[72676] | 82 | /** @def CPUM_INT_ASSERT_NOT_EXTRN
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| 83 | * Macro for asserting that @a a_fNotExtrn are present.
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| 84 | *
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| 85 | * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
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| 86 | * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
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| 87 | */
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| 88 | #define CPUM_INT_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
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| 89 | AssertMsg(!((a_pVCpu)->cpum.s.Guest.fExtrn & (a_fNotExtrn)), \
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| 90 | ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.s.Guest.fExtrn, (a_fNotExtrn)))
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[42165] | 91 |
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| 92 |
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[18927] | 93 | VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
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[1] | 94 | {
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[18927] | 95 | pVCpu->cpum.s.Hyper.cr3 = cr3;
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[1] | 96 | }
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| 97 |
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[18927] | 98 | VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
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[16859] | 99 | {
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[18927] | 100 | return pVCpu->cpum.s.Hyper.cr3;
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[16859] | 101 | }
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[12657] | 102 |
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[16859] | 103 |
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[58116] | 104 | /** @def MAYBE_LOAD_DRx
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[47660] | 105 | * Macro for updating DRx values in raw-mode and ring-0 contexts.
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| 106 | */
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| 107 | #ifdef IN_RING0
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[80053] | 108 | # define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { a_fnLoad(a_uValue); } while (0)
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[47660] | 109 | #else
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| 110 | # define MAYBE_LOAD_DRx(a_pVCpu, a_fnLoad, a_uValue) do { } while (0)
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| 111 | #endif
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| 112 |
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[18927] | 113 | VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
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[1] | 114 | {
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[18927] | 115 | pVCpu->cpum.s.Hyper.dr[0] = uDr0;
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[47660] | 116 | MAYBE_LOAD_DRx(pVCpu, ASMSetDR0, uDr0);
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[1] | 117 | }
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| 118 |
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[12657] | 119 |
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[18927] | 120 | VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
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[1] | 121 | {
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[18927] | 122 | pVCpu->cpum.s.Hyper.dr[1] = uDr1;
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[47660] | 123 | MAYBE_LOAD_DRx(pVCpu, ASMSetDR1, uDr1);
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[1] | 124 | }
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| 125 |
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[12657] | 126 |
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[18927] | 127 | VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
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[1] | 128 | {
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[18927] | 129 | pVCpu->cpum.s.Hyper.dr[2] = uDr2;
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[47660] | 130 | MAYBE_LOAD_DRx(pVCpu, ASMSetDR2, uDr2);
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[1] | 131 | }
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| 132 |
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[12657] | 133 |
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[18927] | 134 | VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
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[1] | 135 | {
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[18927] | 136 | pVCpu->cpum.s.Hyper.dr[3] = uDr3;
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[47660] | 137 | MAYBE_LOAD_DRx(pVCpu, ASMSetDR3, uDr3);
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[1] | 138 | }
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| 139 |
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[12657] | 140 |
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[18927] | 141 | VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
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[1] | 142 | {
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[18927] | 143 | pVCpu->cpum.s.Hyper.dr[6] = uDr6;
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[1] | 144 | }
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| 145 |
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[12657] | 146 |
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[18927] | 147 | VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
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[1] | 148 | {
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[18927] | 149 | pVCpu->cpum.s.Hyper.dr[7] = uDr7;
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[1] | 150 | }
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| 151 |
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| 152 |
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[18927] | 153 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
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[1] | 154 | {
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[18927] | 155 | return pVCpu->cpum.s.Hyper.dr[0];
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[1] | 156 | }
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| 157 |
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[12657] | 158 |
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[18927] | 159 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
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[1] | 160 | {
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[18927] | 161 | return pVCpu->cpum.s.Hyper.dr[1];
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[1] | 162 | }
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| 163 |
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[12657] | 164 |
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[18927] | 165 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
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[1] | 166 | {
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[18927] | 167 | return pVCpu->cpum.s.Hyper.dr[2];
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[1] | 168 | }
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| 169 |
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[12657] | 170 |
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[18927] | 171 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
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[1] | 172 | {
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[18927] | 173 | return pVCpu->cpum.s.Hyper.dr[3];
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[1] | 174 | }
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| 175 |
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[12657] | 176 |
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[18927] | 177 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
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[1] | 178 | {
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[18927] | 179 | return pVCpu->cpum.s.Hyper.dr[6];
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[1] | 180 | }
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| 181 |
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[12657] | 182 |
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[18927] | 183 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
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[1] | 184 | {
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[18927] | 185 | return pVCpu->cpum.s.Hyper.dr[7];
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[1] | 186 | }
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| 187 |
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| 188 |
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| 189 | /**
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[97231] | 190 | * Checks that the special cookie stored in unused reserved RFLAGS bits
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| 191 | *
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| 192 | * @retval true if cookie is ok.
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| 193 | * @retval false if cookie is not ok.
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| 194 | * @param pVM The cross context VM structure.
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| 195 | * @param pVCpu The cross context virtual CPU structure.
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| 196 | */
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| 197 | VMM_INT_DECL(bool) CPUMAssertGuestRFlagsCookie(PVM pVM, PVMCPU pVCpu)
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| 198 | {
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[97286] | 199 | AssertLogRelMsgReturn( ( pVCpu->cpum.s.Guest.rflags.uBoth
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| 200 | & ~(uint64_t)(CPUMX86EFLAGS_HW_MASK_64 | CPUMX86EFLAGS_INT_MASK_64))
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[97231] | 201 | == pVM->cpum.s.fReservedRFlagsCookie
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[97286] | 202 | && (pVCpu->cpum.s.Guest.rflags.uBoth & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK
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| 203 | && (pVCpu->cpum.s.Guest.rflags.uBoth & X86_EFL_RAZ_MASK & CPUMX86EFLAGS_HW_MASK_64) == 0,
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[97231] | 204 | ("rflags=%#RX64 vs fReservedRFlagsCookie=%#RX64\n",
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| 205 | pVCpu->cpum.s.Guest.rflags.uBoth, pVM->cpum.s.fReservedRFlagsCookie),
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| 206 | false);
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| 207 | return true;
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| 208 | }
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| 209 |
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| 210 |
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| 211 | /**
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[42034] | 212 | * Queries the pointer to the internal CPUMCTX structure.
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[1] | 213 | *
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[13532] | 214 | * @returns The CPUMCTX pointer.
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[58123] | 215 | * @param pVCpu The cross context virtual CPU structure.
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[1] | 216 | */
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[18927] | 217 | VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
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[1] | 218 | {
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[13960] | 219 | return &pVCpu->cpum.s.Guest;
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| 220 | }
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| 221 |
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[72358] | 222 |
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| 223 | /**
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| 224 | * Queries the pointer to the internal CPUMCTXMSRS structure.
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| 225 | *
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| 226 | * This is for NEM only.
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| 227 | *
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| 228 | * @returns The CPUMCTX pointer.
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| 229 | * @param pVCpu The cross context virtual CPU structure.
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| 230 | */
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| 231 | VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu)
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| 232 | {
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| 233 | return &pVCpu->cpum.s.GuestMsrs;
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| 234 | }
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| 235 |
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| 236 |
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[36762] | 237 | VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
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[1] | 238 | {
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[36762] | 239 | pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
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| 240 | pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
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[72484] | 241 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_GDTR;
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[18927] | 242 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
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[42452] | 243 | return VINF_SUCCESS; /* formality, consider it void. */
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[1] | 244 | }
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| 245 |
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[72358] | 246 |
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[36762] | 247 | VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
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[1] | 248 | {
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[36762] | 249 | pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
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| 250 | pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
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[72484] | 251 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_IDTR;
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[18927] | 252 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
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[42452] | 253 | return VINF_SUCCESS; /* formality, consider it void. */
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[1] | 254 | }
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| 255 |
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[72358] | 256 |
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[18927] | 257 | VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
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[1] | 258 | {
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[41906] | 259 | pVCpu->cpum.s.Guest.tr.Sel = tr;
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[18927] | 260 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
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[42452] | 261 | return VINF_SUCCESS; /* formality, consider it void. */
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[1] | 262 | }
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| 263 |
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[72358] | 264 |
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[18927] | 265 | VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
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[1] | 266 | {
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[42407] | 267 | pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
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| 268 | /* The caller will set more hidden bits if it has them. */
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| 269 | pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
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| 270 | pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
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[18927] | 271 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
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[42452] | 272 | return VINF_SUCCESS; /* formality, consider it void. */
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[1] | 273 | }
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| 274 |
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| 275 |
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[5389] | 276 | /**
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[5695] | 277 | * Set the guest CR0.
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| 278 | *
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| 279 | * When called in GC, the hyper CR0 may be updated if that is
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| 280 | * required. The caller only has to take special action if AM,
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| 281 | * WP, PG or PE changes.
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| 282 | *
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[5389] | 283 | * @returns VINF_SUCCESS (consider it void).
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[58123] | 284 | * @param pVCpu The cross context virtual CPU structure.
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[5389] | 285 | * @param cr0 The new CR0 value.
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| 286 | */
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[80253] | 287 | VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0)
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[1] | 288 | {
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[5389] | 289 | /*
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[5695] | 290 | * Check for changes causing TLB flushes (for REM).
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| 291 | * The caller is responsible for calling PGM when appropriate.
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[5389] | 292 | */
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[31079] | 293 | if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
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[18927] | 294 | != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
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| 295 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
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| 296 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
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[5389] | 297 |
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[45798] | 298 | /*
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| 299 | * Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
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| 300 | */
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| 301 | if (((cr0 ^ pVCpu->cpum.s.Guest.cr0) & X86_CR0_WP) && (cr0 & X86_CR0_WP))
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| 302 | PGMCr0WpEnabled(pVCpu);
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| 303 |
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[60664] | 304 | /* The ET flag is settable on a 386 and hardwired on 486+. */
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| 305 | if ( !(cr0 & X86_CR0_ET)
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| 306 | && pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386)
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| 307 | cr0 |= X86_CR0_ET;
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| 308 |
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| 309 | pVCpu->cpum.s.Guest.cr0 = cr0;
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[72676] | 310 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR0;
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[1] | 311 | return VINF_SUCCESS;
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| 312 | }
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| 313 |
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[12657] | 314 |
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[18927] | 315 | VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
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[1] | 316 | {
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[18927] | 317 | pVCpu->cpum.s.Guest.cr2 = cr2;
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[72676] | 318 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR2;
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[1] | 319 | return VINF_SUCCESS;
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| 320 | }
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| 321 |
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[12657] | 322 |
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[18927] | 323 | VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
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[1] | 324 | {
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[18927] | 325 | pVCpu->cpum.s.Guest.cr3 = cr3;
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| 326 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
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[72676] | 327 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
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[1] | 328 | return VINF_SUCCESS;
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| 329 | }
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| 330 |
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[12657] | 331 |
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[18927] | 332 | VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
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[1] | 333 | {
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[61776] | 334 | /* Note! We don't bother with OSXSAVE and legacy CPUID patches. */
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[55229] | 335 |
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| 336 | if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
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| 337 | != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
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[18927] | 338 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
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[55229] | 339 |
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[18927] | 340 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
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| 341 | pVCpu->cpum.s.Guest.cr4 = cr4;
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[72676] | 342 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR4;
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[1] | 343 | return VINF_SUCCESS;
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| 344 | }
|
---|
| 345 |
|
---|
[12657] | 346 |
|
---|
[18927] | 347 | VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
|
---|
[1] | 348 | {
|
---|
[97220] | 349 | pVCpu->cpum.s.Guest.eflags.u = eflags;
|
---|
[72676] | 350 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_RFLAGS;
|
---|
[1] | 351 | return VINF_SUCCESS;
|
---|
| 352 | }
|
---|
| 353 |
|
---|
[12657] | 354 |
|
---|
[18927] | 355 | VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
|
---|
[1] | 356 | {
|
---|
[18927] | 357 | pVCpu->cpum.s.Guest.eip = eip;
|
---|
[1] | 358 | return VINF_SUCCESS;
|
---|
| 359 | }
|
---|
| 360 |
|
---|
[12657] | 361 |
|
---|
[18927] | 362 | VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
|
---|
[1] | 363 | {
|
---|
[18927] | 364 | pVCpu->cpum.s.Guest.eax = eax;
|
---|
[1] | 365 | return VINF_SUCCESS;
|
---|
| 366 | }
|
---|
| 367 |
|
---|
[12657] | 368 |
|
---|
[18927] | 369 | VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
|
---|
[1] | 370 | {
|
---|
[18927] | 371 | pVCpu->cpum.s.Guest.ebx = ebx;
|
---|
[1] | 372 | return VINF_SUCCESS;
|
---|
| 373 | }
|
---|
| 374 |
|
---|
[12657] | 375 |
|
---|
[18927] | 376 | VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
|
---|
[1] | 377 | {
|
---|
[18927] | 378 | pVCpu->cpum.s.Guest.ecx = ecx;
|
---|
[1] | 379 | return VINF_SUCCESS;
|
---|
| 380 | }
|
---|
| 381 |
|
---|
[12657] | 382 |
|
---|
[18927] | 383 | VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
|
---|
[1] | 384 | {
|
---|
[18927] | 385 | pVCpu->cpum.s.Guest.edx = edx;
|
---|
[1] | 386 | return VINF_SUCCESS;
|
---|
| 387 | }
|
---|
| 388 |
|
---|
[12657] | 389 |
|
---|
[18927] | 390 | VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
|
---|
[1] | 391 | {
|
---|
[18927] | 392 | pVCpu->cpum.s.Guest.esp = esp;
|
---|
[1] | 393 | return VINF_SUCCESS;
|
---|
| 394 | }
|
---|
| 395 |
|
---|
[12657] | 396 |
|
---|
[18927] | 397 | VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
|
---|
[1] | 398 | {
|
---|
[18927] | 399 | pVCpu->cpum.s.Guest.ebp = ebp;
|
---|
[1] | 400 | return VINF_SUCCESS;
|
---|
| 401 | }
|
---|
| 402 |
|
---|
[12657] | 403 |
|
---|
[18927] | 404 | VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
|
---|
[1] | 405 | {
|
---|
[18927] | 406 | pVCpu->cpum.s.Guest.esi = esi;
|
---|
[1] | 407 | return VINF_SUCCESS;
|
---|
| 408 | }
|
---|
| 409 |
|
---|
[12657] | 410 |
|
---|
[18927] | 411 | VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
|
---|
[1] | 412 | {
|
---|
[18927] | 413 | pVCpu->cpum.s.Guest.edi = edi;
|
---|
[1] | 414 | return VINF_SUCCESS;
|
---|
| 415 | }
|
---|
| 416 |
|
---|
[12657] | 417 |
|
---|
[18927] | 418 | VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
|
---|
[1] | 419 | {
|
---|
[41906] | 420 | pVCpu->cpum.s.Guest.ss.Sel = ss;
|
---|
[1] | 421 | return VINF_SUCCESS;
|
---|
| 422 | }
|
---|
| 423 |
|
---|
[12657] | 424 |
|
---|
[18927] | 425 | VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
|
---|
[1] | 426 | {
|
---|
[41906] | 427 | pVCpu->cpum.s.Guest.cs.Sel = cs;
|
---|
[1] | 428 | return VINF_SUCCESS;
|
---|
| 429 | }
|
---|
| 430 |
|
---|
[12657] | 431 |
|
---|
[18927] | 432 | VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
|
---|
[1] | 433 | {
|
---|
[41906] | 434 | pVCpu->cpum.s.Guest.ds.Sel = ds;
|
---|
[1] | 435 | return VINF_SUCCESS;
|
---|
| 436 | }
|
---|
| 437 |
|
---|
[12657] | 438 |
|
---|
[18927] | 439 | VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
|
---|
[1] | 440 | {
|
---|
[41906] | 441 | pVCpu->cpum.s.Guest.es.Sel = es;
|
---|
[1] | 442 | return VINF_SUCCESS;
|
---|
| 443 | }
|
---|
| 444 |
|
---|
[12657] | 445 |
|
---|
[18927] | 446 | VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
|
---|
[1] | 447 | {
|
---|
[41906] | 448 | pVCpu->cpum.s.Guest.fs.Sel = fs;
|
---|
[1] | 449 | return VINF_SUCCESS;
|
---|
| 450 | }
|
---|
| 451 |
|
---|
[12657] | 452 |
|
---|
[18927] | 453 | VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
|
---|
[1] | 454 | {
|
---|
[41906] | 455 | pVCpu->cpum.s.Guest.gs.Sel = gs;
|
---|
[1] | 456 | return VINF_SUCCESS;
|
---|
| 457 | }
|
---|
| 458 |
|
---|
[12657] | 459 |
|
---|
[18927] | 460 | VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
|
---|
[7730] | 461 | {
|
---|
[18927] | 462 | pVCpu->cpum.s.Guest.msrEFER = val;
|
---|
[72676] | 463 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_EFER;
|
---|
[7730] | 464 | }
|
---|
[1] | 465 |
|
---|
[12657] | 466 |
|
---|
[79164] | 467 | VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit)
|
---|
[1] | 468 | {
|
---|
[72676] | 469 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_IDTR);
|
---|
[1] | 470 | if (pcbLimit)
|
---|
[18927] | 471 | *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
|
---|
| 472 | return pVCpu->cpum.s.Guest.idtr.pIdt;
|
---|
[1] | 473 | }
|
---|
| 474 |
|
---|
[12657] | 475 |
|
---|
[79164] | 476 | VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden)
|
---|
[1] | 477 | {
|
---|
[72676] | 478 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_TR);
|
---|
[17035] | 479 | if (pHidden)
|
---|
[41906] | 480 | *pHidden = pVCpu->cpum.s.Guest.tr;
|
---|
| 481 | return pVCpu->cpum.s.Guest.tr.Sel;
|
---|
[1] | 482 | }
|
---|
| 483 |
|
---|
[12657] | 484 |
|
---|
[79164] | 485 | VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu)
|
---|
[1] | 486 | {
|
---|
[72676] | 487 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS);
|
---|
[41906] | 488 | return pVCpu->cpum.s.Guest.cs.Sel;
|
---|
[1] | 489 | }
|
---|
| 490 |
|
---|
[12657] | 491 |
|
---|
[79164] | 492 | VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu)
|
---|
[1] | 493 | {
|
---|
[72676] | 494 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DS);
|
---|
[41906] | 495 | return pVCpu->cpum.s.Guest.ds.Sel;
|
---|
[1] | 496 | }
|
---|
| 497 |
|
---|
[12657] | 498 |
|
---|
[79164] | 499 | VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu)
|
---|
[1] | 500 | {
|
---|
[72676] | 501 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ES);
|
---|
[41906] | 502 | return pVCpu->cpum.s.Guest.es.Sel;
|
---|
[1] | 503 | }
|
---|
| 504 |
|
---|
[12657] | 505 |
|
---|
[79164] | 506 | VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu)
|
---|
[1] | 507 | {
|
---|
[72676] | 508 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_FS);
|
---|
[41906] | 509 | return pVCpu->cpum.s.Guest.fs.Sel;
|
---|
[1] | 510 | }
|
---|
| 511 |
|
---|
[12657] | 512 |
|
---|
[79164] | 513 | VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu)
|
---|
[1] | 514 | {
|
---|
[72676] | 515 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GS);
|
---|
[41906] | 516 | return pVCpu->cpum.s.Guest.gs.Sel;
|
---|
[1] | 517 | }
|
---|
| 518 |
|
---|
[12657] | 519 |
|
---|
[79164] | 520 | VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu)
|
---|
[1] | 521 | {
|
---|
[72676] | 522 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SS);
|
---|
[41906] | 523 | return pVCpu->cpum.s.Guest.ss.Sel;
|
---|
[1] | 524 | }
|
---|
| 525 |
|
---|
[12657] | 526 |
|
---|
[64720] | 527 | VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu)
|
---|
| 528 | {
|
---|
[72676] | 529 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
|
---|
[64720] | 530 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
|
---|
| 531 | if ( !CPUMIsGuestInLongMode(pVCpu)
|
---|
[72676] | 532 | || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
|
---|
[64720] | 533 | return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.cs.u64Base;
|
---|
| 534 | return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.cs.u64Base;
|
---|
| 535 | }
|
---|
| 536 |
|
---|
| 537 |
|
---|
| 538 | VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu)
|
---|
| 539 | {
|
---|
[72676] | 540 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
|
---|
[64720] | 541 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
|
---|
| 542 | if ( !CPUMIsGuestInLongMode(pVCpu)
|
---|
[72676] | 543 | || !pVCpu->cpum.s.Guest.cs.Attr.n.u1Long)
|
---|
[64720] | 544 | return pVCpu->cpum.s.Guest.eip + (uint32_t)pVCpu->cpum.s.Guest.ss.u64Base;
|
---|
| 545 | return pVCpu->cpum.s.Guest.rip + pVCpu->cpum.s.Guest.ss.u64Base;
|
---|
| 546 | }
|
---|
| 547 |
|
---|
| 548 |
|
---|
[79164] | 549 | VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu)
|
---|
[1] | 550 | {
|
---|
[72676] | 551 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
|
---|
[41906] | 552 | return pVCpu->cpum.s.Guest.ldtr.Sel;
|
---|
[1] | 553 | }
|
---|
| 554 |
|
---|
[12657] | 555 |
|
---|
[79164] | 556 | VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
|
---|
[42427] | 557 | {
|
---|
[72676] | 558 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_LDTR);
|
---|
[42427] | 559 | *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
|
---|
| 560 | *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
|
---|
| 561 | return pVCpu->cpum.s.Guest.ldtr.Sel;
|
---|
| 562 | }
|
---|
| 563 |
|
---|
| 564 |
|
---|
[79164] | 565 | VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu)
|
---|
[1] | 566 | {
|
---|
[72676] | 567 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
|
---|
[18927] | 568 | return pVCpu->cpum.s.Guest.cr0;
|
---|
[1] | 569 | }
|
---|
| 570 |
|
---|
[12657] | 571 |
|
---|
[79164] | 572 | VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu)
|
---|
[1] | 573 | {
|
---|
[72676] | 574 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
|
---|
[18927] | 575 | return pVCpu->cpum.s.Guest.cr2;
|
---|
[1] | 576 | }
|
---|
| 577 |
|
---|
[12657] | 578 |
|
---|
[79164] | 579 | VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu)
|
---|
[1] | 580 | {
|
---|
[72676] | 581 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
|
---|
[18927] | 582 | return pVCpu->cpum.s.Guest.cr3;
|
---|
[1] | 583 | }
|
---|
| 584 |
|
---|
[12657] | 585 |
|
---|
[79164] | 586 | VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu)
|
---|
[1] | 587 | {
|
---|
[72676] | 588 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
|
---|
[18927] | 589 | return pVCpu->cpum.s.Guest.cr4;
|
---|
[1] | 590 | }
|
---|
| 591 |
|
---|
[12657] | 592 |
|
---|
[80253] | 593 | VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu)
|
---|
[31489] | 594 | {
|
---|
| 595 | uint64_t u64;
|
---|
[41728] | 596 | int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
|
---|
[31489] | 597 | if (RT_FAILURE(rc))
|
---|
| 598 | u64 = 0;
|
---|
| 599 | return u64;
|
---|
| 600 | }
|
---|
| 601 |
|
---|
| 602 |
|
---|
[79164] | 603 | VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR)
|
---|
[1] | 604 | {
|
---|
[72676] | 605 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_GDTR);
|
---|
[18927] | 606 | *pGDTR = pVCpu->cpum.s.Guest.gdtr;
|
---|
[1] | 607 | }
|
---|
| 608 |
|
---|
[12657] | 609 |
|
---|
[79164] | 610 | VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu)
|
---|
[1] | 611 | {
|
---|
[72676] | 612 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
|
---|
[18927] | 613 | return pVCpu->cpum.s.Guest.eip;
|
---|
[1] | 614 | }
|
---|
| 615 |
|
---|
[12657] | 616 |
|
---|
[79164] | 617 | VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu)
|
---|
[9841] | 618 | {
|
---|
[72676] | 619 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
|
---|
[18927] | 620 | return pVCpu->cpum.s.Guest.rip;
|
---|
[9841] | 621 | }
|
---|
| 622 |
|
---|
[12657] | 623 |
|
---|
[79164] | 624 | VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu)
|
---|
[1] | 625 | {
|
---|
[72676] | 626 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RAX);
|
---|
[18927] | 627 | return pVCpu->cpum.s.Guest.eax;
|
---|
[1] | 628 | }
|
---|
| 629 |
|
---|
[12657] | 630 |
|
---|
[79164] | 631 | VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu)
|
---|
[1] | 632 | {
|
---|
[72676] | 633 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBX);
|
---|
[18927] | 634 | return pVCpu->cpum.s.Guest.ebx;
|
---|
[1] | 635 | }
|
---|
| 636 |
|
---|
[12657] | 637 |
|
---|
[79164] | 638 | VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu)
|
---|
[1] | 639 | {
|
---|
[72676] | 640 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RCX);
|
---|
[18927] | 641 | return pVCpu->cpum.s.Guest.ecx;
|
---|
[1] | 642 | }
|
---|
| 643 |
|
---|
[12657] | 644 |
|
---|
[79164] | 645 | VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu)
|
---|
[1] | 646 | {
|
---|
[72676] | 647 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDX);
|
---|
[18927] | 648 | return pVCpu->cpum.s.Guest.edx;
|
---|
[1] | 649 | }
|
---|
| 650 |
|
---|
[12657] | 651 |
|
---|
[79164] | 652 | VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu)
|
---|
[1] | 653 | {
|
---|
[72676] | 654 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSI);
|
---|
[18927] | 655 | return pVCpu->cpum.s.Guest.esi;
|
---|
[1] | 656 | }
|
---|
| 657 |
|
---|
[12657] | 658 |
|
---|
[79164] | 659 | VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu)
|
---|
[1] | 660 | {
|
---|
[72676] | 661 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RDI);
|
---|
[18927] | 662 | return pVCpu->cpum.s.Guest.edi;
|
---|
[1] | 663 | }
|
---|
| 664 |
|
---|
[12657] | 665 |
|
---|
[79164] | 666 | VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu)
|
---|
[1] | 667 | {
|
---|
[72676] | 668 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RSP);
|
---|
[18927] | 669 | return pVCpu->cpum.s.Guest.esp;
|
---|
[1] | 670 | }
|
---|
| 671 |
|
---|
[12657] | 672 |
|
---|
[79164] | 673 | VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu)
|
---|
[1] | 674 | {
|
---|
[72676] | 675 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RBP);
|
---|
[18927] | 676 | return pVCpu->cpum.s.Guest.ebp;
|
---|
[1] | 677 | }
|
---|
| 678 |
|
---|
[12657] | 679 |
|
---|
[79164] | 680 | VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu)
|
---|
[1] | 681 | {
|
---|
[72676] | 682 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RFLAGS);
|
---|
[97220] | 683 | return pVCpu->cpum.s.Guest.eflags.u;
|
---|
[1] | 684 | }
|
---|
| 685 |
|
---|
[12657] | 686 |
|
---|
[80253] | 687 | VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue)
|
---|
[1] | 688 | {
|
---|
| 689 | switch (iReg)
|
---|
| 690 | {
|
---|
[41728] | 691 | case DISCREG_CR0:
|
---|
[72676] | 692 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
|
---|
[18927] | 693 | *pValue = pVCpu->cpum.s.Guest.cr0;
|
---|
[1] | 694 | break;
|
---|
[31489] | 695 |
|
---|
[41728] | 696 | case DISCREG_CR2:
|
---|
[72676] | 697 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR2);
|
---|
[18927] | 698 | *pValue = pVCpu->cpum.s.Guest.cr2;
|
---|
[1] | 699 | break;
|
---|
[31489] | 700 |
|
---|
[41728] | 701 | case DISCREG_CR3:
|
---|
[72676] | 702 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
|
---|
[18927] | 703 | *pValue = pVCpu->cpum.s.Guest.cr3;
|
---|
[1] | 704 | break;
|
---|
[31489] | 705 |
|
---|
[41728] | 706 | case DISCREG_CR4:
|
---|
[72676] | 707 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
|
---|
[18927] | 708 | *pValue = pVCpu->cpum.s.Guest.cr4;
|
---|
[1] | 709 | break;
|
---|
[31489] | 710 |
|
---|
[41728] | 711 | case DISCREG_CR8:
|
---|
[31489] | 712 | {
|
---|
[72676] | 713 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
|
---|
[31489] | 714 | uint8_t u8Tpr;
|
---|
[64655] | 715 | int rc = APICGetTpr(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
|
---|
[31489] | 716 | if (RT_FAILURE(rc))
|
---|
| 717 | {
|
---|
| 718 | AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
|
---|
| 719 | *pValue = 0;
|
---|
| 720 | return rc;
|
---|
| 721 | }
|
---|
[64655] | 722 | *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0 */
|
---|
[31489] | 723 | break;
|
---|
| 724 | }
|
---|
| 725 |
|
---|
[1] | 726 | default:
|
---|
| 727 | return VERR_INVALID_PARAMETER;
|
---|
| 728 | }
|
---|
| 729 | return VINF_SUCCESS;
|
---|
| 730 | }
|
---|
| 731 |
|
---|
[12657] | 732 |
|
---|
[79164] | 733 | VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu)
|
---|
[1] | 734 | {
|
---|
[72676] | 735 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
|
---|
[18927] | 736 | return pVCpu->cpum.s.Guest.dr[0];
|
---|
[1] | 737 | }
|
---|
| 738 |
|
---|
[12657] | 739 |
|
---|
[79164] | 740 | VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu)
|
---|
[1] | 741 | {
|
---|
[72676] | 742 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
|
---|
[18927] | 743 | return pVCpu->cpum.s.Guest.dr[1];
|
---|
[1] | 744 | }
|
---|
| 745 |
|
---|
[12657] | 746 |
|
---|
[79164] | 747 | VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu)
|
---|
[1] | 748 | {
|
---|
[72676] | 749 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
|
---|
[18927] | 750 | return pVCpu->cpum.s.Guest.dr[2];
|
---|
[1] | 751 | }
|
---|
| 752 |
|
---|
[12657] | 753 |
|
---|
[79164] | 754 | VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu)
|
---|
[1] | 755 | {
|
---|
[72676] | 756 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
|
---|
[18927] | 757 | return pVCpu->cpum.s.Guest.dr[3];
|
---|
[1] | 758 | }
|
---|
| 759 |
|
---|
[12657] | 760 |
|
---|
[79164] | 761 | VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu)
|
---|
[1] | 762 | {
|
---|
[72676] | 763 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR6);
|
---|
[18927] | 764 | return pVCpu->cpum.s.Guest.dr[6];
|
---|
[1] | 765 | }
|
---|
| 766 |
|
---|
[12657] | 767 |
|
---|
[79164] | 768 | VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu)
|
---|
[1] | 769 | {
|
---|
[72676] | 770 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR7);
|
---|
[18927] | 771 | return pVCpu->cpum.s.Guest.dr[7];
|
---|
[1] | 772 | }
|
---|
| 773 |
|
---|
[12657] | 774 |
|
---|
[79164] | 775 | VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
|
---|
[1] | 776 | {
|
---|
[72676] | 777 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_DR_MASK);
|
---|
[41728] | 778 | AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
|
---|
[12657] | 779 | /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
|
---|
| 780 | if (iReg == 4 || iReg == 5)
|
---|
| 781 | iReg += 2;
|
---|
[18927] | 782 | *pValue = pVCpu->cpum.s.Guest.dr[iReg];
|
---|
[1] | 783 | return VINF_SUCCESS;
|
---|
| 784 | }
|
---|
| 785 |
|
---|
[12657] | 786 |
|
---|
[79164] | 787 | VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu)
|
---|
[7730] | 788 | {
|
---|
[72676] | 789 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
|
---|
[18927] | 790 | return pVCpu->cpum.s.Guest.msrEFER;
|
---|
[7730] | 791 | }
|
---|
| 792 |
|
---|
[12657] | 793 |
|
---|
[1] | 794 | /**
|
---|
[54737] | 795 | * Looks up a CPUID leaf in the CPUID leaf array, no subleaf.
|
---|
| 796 | *
|
---|
| 797 | * @returns Pointer to the leaf if found, NULL if not.
|
---|
| 798 | *
|
---|
[58122] | 799 | * @param pVM The cross context VM structure.
|
---|
[54737] | 800 | * @param uLeaf The leaf to get.
|
---|
| 801 | */
|
---|
| 802 | PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf)
|
---|
| 803 | {
|
---|
[91266] | 804 | unsigned iEnd = RT_MIN(pVM->cpum.s.GuestInfo.cCpuIdLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves));
|
---|
[54737] | 805 | if (iEnd)
|
---|
| 806 | {
|
---|
| 807 | unsigned iStart = 0;
|
---|
[91266] | 808 | PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.aCpuIdLeaves;
|
---|
[54737] | 809 | for (;;)
|
---|
| 810 | {
|
---|
| 811 | unsigned i = iStart + (iEnd - iStart) / 2U;
|
---|
| 812 | if (uLeaf < paLeaves[i].uLeaf)
|
---|
| 813 | {
|
---|
| 814 | if (i <= iStart)
|
---|
| 815 | return NULL;
|
---|
| 816 | iEnd = i;
|
---|
| 817 | }
|
---|
| 818 | else if (uLeaf > paLeaves[i].uLeaf)
|
---|
| 819 | {
|
---|
| 820 | i += 1;
|
---|
| 821 | if (i >= iEnd)
|
---|
| 822 | return NULL;
|
---|
| 823 | iStart = i;
|
---|
| 824 | }
|
---|
| 825 | else
|
---|
| 826 | {
|
---|
| 827 | if (RT_LIKELY(paLeaves[i].fSubLeafMask == 0 && paLeaves[i].uSubLeaf == 0))
|
---|
| 828 | return &paLeaves[i];
|
---|
| 829 |
|
---|
| 830 | /* This shouldn't normally happen. But in case the it does due
|
---|
| 831 | to user configuration overrids or something, just return the
|
---|
| 832 | first sub-leaf. */
|
---|
| 833 | AssertMsgFailed(("uLeaf=%#x fSubLeafMask=%#x uSubLeaf=%#x\n",
|
---|
| 834 | uLeaf, paLeaves[i].fSubLeafMask, paLeaves[i].uSubLeaf));
|
---|
| 835 | while ( paLeaves[i].uSubLeaf != 0
|
---|
| 836 | && i > 0
|
---|
| 837 | && uLeaf == paLeaves[i - 1].uLeaf)
|
---|
| 838 | i--;
|
---|
| 839 | return &paLeaves[i];
|
---|
| 840 | }
|
---|
| 841 | }
|
---|
| 842 | }
|
---|
| 843 |
|
---|
| 844 | return NULL;
|
---|
| 845 | }
|
---|
| 846 |
|
---|
| 847 |
|
---|
| 848 | /**
|
---|
[49893] | 849 | * Looks up a CPUID leaf in the CPUID leaf array.
|
---|
| 850 | *
|
---|
| 851 | * @returns Pointer to the leaf if found, NULL if not.
|
---|
| 852 | *
|
---|
[58122] | 853 | * @param pVM The cross context VM structure.
|
---|
[49893] | 854 | * @param uLeaf The leaf to get.
|
---|
| 855 | * @param uSubLeaf The subleaf, if applicable. Just pass 0 if it
|
---|
| 856 | * isn't.
|
---|
[54737] | 857 | * @param pfExactSubLeafHit Whether we've got an exact subleaf hit or not.
|
---|
[49893] | 858 | */
|
---|
[54737] | 859 | PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit)
|
---|
[49893] | 860 | {
|
---|
[91266] | 861 | unsigned iEnd = RT_MIN(pVM->cpum.s.GuestInfo.cCpuIdLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves));
|
---|
[49893] | 862 | if (iEnd)
|
---|
| 863 | {
|
---|
| 864 | unsigned iStart = 0;
|
---|
[91266] | 865 | PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.aCpuIdLeaves;
|
---|
[49893] | 866 | for (;;)
|
---|
| 867 | {
|
---|
| 868 | unsigned i = iStart + (iEnd - iStart) / 2U;
|
---|
| 869 | if (uLeaf < paLeaves[i].uLeaf)
|
---|
| 870 | {
|
---|
| 871 | if (i <= iStart)
|
---|
| 872 | return NULL;
|
---|
| 873 | iEnd = i;
|
---|
| 874 | }
|
---|
| 875 | else if (uLeaf > paLeaves[i].uLeaf)
|
---|
| 876 | {
|
---|
| 877 | i += 1;
|
---|
| 878 | if (i >= iEnd)
|
---|
| 879 | return NULL;
|
---|
| 880 | iStart = i;
|
---|
| 881 | }
|
---|
| 882 | else
|
---|
| 883 | {
|
---|
| 884 | uSubLeaf &= paLeaves[i].fSubLeafMask;
|
---|
[54737] | 885 | if (uSubLeaf == paLeaves[i].uSubLeaf)
|
---|
| 886 | *pfExactSubLeafHit = true;
|
---|
| 887 | else
|
---|
[49893] | 888 | {
|
---|
| 889 | /* Find the right subleaf. We return the last one before
|
---|
| 890 | uSubLeaf if we don't find an exact match. */
|
---|
| 891 | if (uSubLeaf < paLeaves[i].uSubLeaf)
|
---|
| 892 | while ( i > 0
|
---|
[54714] | 893 | && uLeaf == paLeaves[i - 1].uLeaf
|
---|
| 894 | && uSubLeaf <= paLeaves[i - 1].uSubLeaf)
|
---|
[49893] | 895 | i--;
|
---|
| 896 | else
|
---|
| 897 | while ( i + 1 < pVM->cpum.s.GuestInfo.cCpuIdLeaves
|
---|
| 898 | && uLeaf == paLeaves[i + 1].uLeaf
|
---|
| 899 | && uSubLeaf >= paLeaves[i + 1].uSubLeaf)
|
---|
| 900 | i++;
|
---|
[54737] | 901 | *pfExactSubLeafHit = uSubLeaf == paLeaves[i].uSubLeaf;
|
---|
[49893] | 902 | }
|
---|
| 903 | return &paLeaves[i];
|
---|
| 904 | }
|
---|
| 905 | }
|
---|
| 906 | }
|
---|
| 907 |
|
---|
[54737] | 908 | *pfExactSubLeafHit = false;
|
---|
[49893] | 909 | return NULL;
|
---|
| 910 | }
|
---|
| 911 |
|
---|
| 912 |
|
---|
| 913 | /**
|
---|
[42034] | 914 | * Gets a CPUID leaf.
|
---|
[1] | 915 | *
|
---|
[58123] | 916 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[54737] | 917 | * @param uLeaf The CPUID leaf to get.
|
---|
| 918 | * @param uSubLeaf The CPUID sub-leaf to get, if applicable.
|
---|
[95248] | 919 | * @param f64BitMode A tristate indicate if the caller is in 64-bit mode or
|
---|
| 920 | * not: 1=true, 0=false, 1=whatever. This affect how the
|
---|
| 921 | * X86_CPUID_EXT_FEATURE_EDX_SYSCALL flag is returned on
|
---|
| 922 | * Intel CPUs, where it's only returned in 64-bit mode.
|
---|
[54737] | 923 | * @param pEax Where to store the EAX value.
|
---|
| 924 | * @param pEbx Where to store the EBX value.
|
---|
| 925 | * @param pEcx Where to store the ECX value.
|
---|
| 926 | * @param pEdx Where to store the EDX value.
|
---|
[1] | 927 | */
|
---|
[95248] | 928 | VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t uLeaf, uint32_t uSubLeaf, int f64BitMode,
|
---|
[54737] | 929 | uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
|
---|
[1] | 930 | {
|
---|
[54760] | 931 | bool fExactSubLeafHit;
|
---|
| 932 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
| 933 | PCCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, uSubLeaf, &fExactSubLeafHit);
|
---|
[54737] | 934 | if (pLeaf)
|
---|
[51301] | 935 | {
|
---|
[56985] | 936 | AssertMsg(pLeaf->uLeaf == uLeaf, ("%#x %#x\n", pLeaf->uLeaf, uLeaf));
|
---|
[54737] | 937 | if (fExactSubLeafHit)
|
---|
[51301] | 938 | {
|
---|
[54737] | 939 | *pEax = pLeaf->uEax;
|
---|
| 940 | *pEbx = pLeaf->uEbx;
|
---|
| 941 | *pEcx = pLeaf->uEcx;
|
---|
| 942 | *pEdx = pLeaf->uEdx;
|
---|
| 943 |
|
---|
| 944 | /*
|
---|
[61776] | 945 | * Deal with CPU specific information.
|
---|
[54737] | 946 | */
|
---|
[61776] | 947 | if (pLeaf->fFlags & ( CPUMCPUIDLEAF_F_CONTAINS_APIC_ID
|
---|
| 948 | | CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE
|
---|
| 949 | | CPUMCPUIDLEAF_F_CONTAINS_APIC ))
|
---|
[54737] | 950 | {
|
---|
| 951 | if (uLeaf == 1)
|
---|
| 952 | {
|
---|
[55229] | 953 | /* EBX: Bits 31-24: Initial APIC ID. */
|
---|
[54737] | 954 | Assert(pVCpu->idCpu <= 255);
|
---|
[54760] | 955 | AssertMsg((pLeaf->uEbx >> 24) == 0, ("%#x\n", pLeaf->uEbx)); /* raw-mode assumption */
|
---|
| 956 | *pEbx = (pLeaf->uEbx & UINT32_C(0x00ffffff)) | (pVCpu->idCpu << 24);
|
---|
[55229] | 957 |
|
---|
[61776] | 958 | /* EDX: Bit 9: AND with APICBASE.EN. */
|
---|
| 959 | if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
|
---|
| 960 | *pEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
|
---|
| 961 |
|
---|
[55229] | 962 | /* ECX: Bit 27: CR4.OSXSAVE mirror. */
|
---|
| 963 | *pEcx = (pLeaf->uEcx & ~X86_CPUID_FEATURE_ECX_OSXSAVE)
|
---|
| 964 | | (pVCpu->cpum.s.Guest.cr4 & X86_CR4_OSXSAVE ? X86_CPUID_FEATURE_ECX_OSXSAVE : 0);
|
---|
[54737] | 965 | }
|
---|
| 966 | else if (uLeaf == 0xb)
|
---|
| 967 | {
|
---|
| 968 | /* EDX: Initial extended APIC ID. */
|
---|
[54760] | 969 | AssertMsg(pLeaf->uEdx == 0, ("%#x\n", pLeaf->uEdx)); /* raw-mode assumption */
|
---|
[54737] | 970 | *pEdx = pVCpu->idCpu;
|
---|
[61776] | 971 | Assert(!(pLeaf->fFlags & ~(CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)));
|
---|
[54737] | 972 | }
|
---|
| 973 | else if (uLeaf == UINT32_C(0x8000001e))
|
---|
| 974 | {
|
---|
| 975 | /* EAX: Initial extended APIC ID. */
|
---|
[54760] | 976 | AssertMsg(pLeaf->uEax == 0, ("%#x\n", pLeaf->uEax)); /* raw-mode assumption */
|
---|
[54737] | 977 | *pEax = pVCpu->idCpu;
|
---|
[61776] | 978 | Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC_ID));
|
---|
[54737] | 979 | }
|
---|
[61776] | 980 | else if (uLeaf == UINT32_C(0x80000001))
|
---|
| 981 | {
|
---|
| 982 | /* EDX: Bit 9: AND with APICBASE.EN. */
|
---|
| 983 | if (!pVCpu->cpum.s.fCpuIdApicFeatureVisible)
|
---|
| 984 | *pEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
|
---|
| 985 | Assert(!(pLeaf->fFlags & ~CPUMCPUIDLEAF_F_CONTAINS_APIC));
|
---|
| 986 | }
|
---|
[54737] | 987 | else
|
---|
| 988 | AssertMsgFailed(("uLeaf=%#x\n", uLeaf));
|
---|
| 989 | }
|
---|
[95248] | 990 |
|
---|
| 991 | /* Intel CPUs supresses the SYSCALL bit when not executing in 64-bit mode: */
|
---|
| 992 | if ( uLeaf == UINT32_C(0x80000001)
|
---|
| 993 | && f64BitMode == false
|
---|
| 994 | && (*pEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
|
---|
| 995 | && ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
|
---|
| 996 | || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA /*?*/
|
---|
| 997 | || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_SHANGHAI /*?*/ ) )
|
---|
| 998 | *pEdx &= ~X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
|
---|
| 999 |
|
---|
[51301] | 1000 | }
|
---|
[54737] | 1001 | /*
|
---|
| 1002 | * Out of range sub-leaves aren't quite as easy and pretty as we emulate
|
---|
| 1003 | * them here, but we do the best we can here...
|
---|
| 1004 | */
|
---|
[51301] | 1005 | else
|
---|
| 1006 | {
|
---|
| 1007 | *pEax = *pEbx = *pEcx = *pEdx = 0;
|
---|
[54737] | 1008 | if (pLeaf->fFlags & CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)
|
---|
| 1009 | {
|
---|
| 1010 | *pEcx = uSubLeaf & 0xff;
|
---|
| 1011 | *pEdx = pVCpu->idCpu;
|
---|
| 1012 | }
|
---|
[51301] | 1013 | }
|
---|
| 1014 | }
|
---|
[1] | 1015 | else
|
---|
[19076] | 1016 | {
|
---|
[54737] | 1017 | /*
|
---|
| 1018 | * Different CPUs have different ways of dealing with unknown CPUID leaves.
|
---|
| 1019 | */
|
---|
| 1020 | switch (pVM->cpum.s.GuestInfo.enmUnknownCpuIdMethod)
|
---|
[25803] | 1021 | {
|
---|
[54737] | 1022 | default:
|
---|
| 1023 | AssertFailed();
|
---|
[69046] | 1024 | RT_FALL_THRU();
|
---|
[54737] | 1025 | case CPUMUNKNOWNCPUID_DEFAULTS:
|
---|
| 1026 | case CPUMUNKNOWNCPUID_LAST_STD_LEAF: /* ASSUME this is executed */
|
---|
| 1027 | case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: /** @todo Implement CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX */
|
---|
| 1028 | *pEax = pVM->cpum.s.GuestInfo.DefCpuId.uEax;
|
---|
| 1029 | *pEbx = pVM->cpum.s.GuestInfo.DefCpuId.uEbx;
|
---|
| 1030 | *pEcx = pVM->cpum.s.GuestInfo.DefCpuId.uEcx;
|
---|
| 1031 | *pEdx = pVM->cpum.s.GuestInfo.DefCpuId.uEdx;
|
---|
[25803] | 1032 | break;
|
---|
[54737] | 1033 | case CPUMUNKNOWNCPUID_PASSTHRU:
|
---|
| 1034 | *pEax = uLeaf;
|
---|
| 1035 | *pEbx = 0;
|
---|
| 1036 | *pEcx = uSubLeaf;
|
---|
| 1037 | *pEdx = 0;
|
---|
[25803] | 1038 | break;
|
---|
| 1039 | }
|
---|
[19076] | 1040 | }
|
---|
[54737] | 1041 | Log2(("CPUMGetGuestCpuId: uLeaf=%#010x/%#010x %RX32 %RX32 %RX32 %RX32\n", uLeaf, uSubLeaf, *pEax, *pEbx, *pEcx, *pEdx));
|
---|
[1] | 1042 | }
|
---|
| 1043 |
|
---|
| 1044 |
|
---|
| 1045 | /**
|
---|
[61776] | 1046 | * Sets the visibility of the X86_CPUID_FEATURE_EDX_APIC and
|
---|
| 1047 | * X86_CPUID_AMD_FEATURE_EDX_APIC CPUID bits.
|
---|
[1] | 1048 | *
|
---|
[61776] | 1049 | * @returns Previous value.
|
---|
| 1050 | * @param pVCpu The cross context virtual CPU structure to make the
|
---|
| 1051 | * change on. Usually the calling EMT.
|
---|
| 1052 | * @param fVisible Whether to make it visible (true) or hide it (false).
|
---|
[62277] | 1053 | *
|
---|
| 1054 | * @remarks This is "VMMDECL" so that it still links with
|
---|
| 1055 | * the old APIC code which is in VBoxDD2 and not in
|
---|
| 1056 | * the VMM module.
|
---|
[1] | 1057 | */
|
---|
[62277] | 1058 | VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible)
|
---|
[1] | 1059 | {
|
---|
[61776] | 1060 | bool fOld = pVCpu->cpum.s.fCpuIdApicFeatureVisible;
|
---|
| 1061 | pVCpu->cpum.s.fCpuIdApicFeatureVisible = fVisible;
|
---|
| 1062 | return fOld;
|
---|
[8111] | 1063 | }
|
---|
| 1064 |
|
---|
[12657] | 1065 |
|
---|
[8111] | 1066 | /**
|
---|
[42034] | 1067 | * Gets the host CPU vendor.
|
---|
[23794] | 1068 | *
|
---|
[42034] | 1069 | * @returns CPU vendor.
|
---|
[58122] | 1070 | * @param pVM The cross context VM structure.
|
---|
[23794] | 1071 | */
|
---|
| 1072 | VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
|
---|
| 1073 | {
|
---|
[49893] | 1074 | return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures.enmCpuVendor;
|
---|
[23794] | 1075 | }
|
---|
| 1076 |
|
---|
[42034] | 1077 |
|
---|
[23794] | 1078 | /**
|
---|
[80293] | 1079 | * Gets the host CPU microarchitecture.
|
---|
[9354] | 1080 | *
|
---|
[80293] | 1081 | * @returns CPU microarchitecture.
|
---|
| 1082 | * @param pVM The cross context VM structure.
|
---|
| 1083 | */
|
---|
| 1084 | VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM)
|
---|
| 1085 | {
|
---|
| 1086 | return pVM->cpum.s.HostFeatures.enmMicroarch;
|
---|
| 1087 | }
|
---|
| 1088 |
|
---|
| 1089 |
|
---|
| 1090 | /**
|
---|
| 1091 | * Gets the guest CPU vendor.
|
---|
| 1092 | *
|
---|
[42034] | 1093 | * @returns CPU vendor.
|
---|
[58122] | 1094 | * @param pVM The cross context VM structure.
|
---|
[9354] | 1095 | */
|
---|
[23794] | 1096 | VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
|
---|
[9354] | 1097 | {
|
---|
[49893] | 1098 | return (CPUMCPUVENDOR)pVM->cpum.s.GuestFeatures.enmCpuVendor;
|
---|
[9354] | 1099 | }
|
---|
[1] | 1100 |
|
---|
| 1101 |
|
---|
[80293] | 1102 | /**
|
---|
[100184] | 1103 | * Gets the guest CPU architecture.
|
---|
| 1104 | *
|
---|
| 1105 | * @returns CPU architecture.
|
---|
| 1106 | * @param pVM The cross context VM structure.
|
---|
| 1107 | */
|
---|
| 1108 | VMMDECL(CPUMARCH) CPUMGetGuestArch(PCVM pVM)
|
---|
| 1109 | {
|
---|
| 1110 | RT_NOREF(pVM);
|
---|
| 1111 | return kCpumArch_X86; /* Static as we are in the x86 VMM module here. */
|
---|
| 1112 | }
|
---|
| 1113 |
|
---|
| 1114 |
|
---|
| 1115 | /**
|
---|
[80293] | 1116 | * Gets the guest CPU microarchitecture.
|
---|
| 1117 | *
|
---|
| 1118 | * @returns CPU microarchitecture.
|
---|
| 1119 | * @param pVM The cross context VM structure.
|
---|
| 1120 | */
|
---|
| 1121 | VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM)
|
---|
| 1122 | {
|
---|
| 1123 | return pVM->cpum.s.GuestFeatures.enmMicroarch;
|
---|
| 1124 | }
|
---|
| 1125 |
|
---|
| 1126 |
|
---|
[88290] | 1127 | /**
|
---|
| 1128 | * Gets the maximum number of physical and linear address bits supported by the
|
---|
| 1129 | * guest.
|
---|
| 1130 | *
|
---|
| 1131 | * @param pVM The cross context VM structure.
|
---|
| 1132 | * @param pcPhysAddrWidth Where to store the physical address width.
|
---|
| 1133 | * @param pcLinearAddrWidth Where to store the linear address width.
|
---|
| 1134 | */
|
---|
| 1135 | VMMDECL(void) CPUMGetGuestAddrWidths(PCVM pVM, uint8_t *pcPhysAddrWidth, uint8_t *pcLinearAddrWidth)
|
---|
| 1136 | {
|
---|
| 1137 | AssertPtr(pVM);
|
---|
| 1138 | AssertReturnVoid(pcPhysAddrWidth);
|
---|
| 1139 | AssertReturnVoid(pcLinearAddrWidth);
|
---|
| 1140 | *pcPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
|
---|
| 1141 | *pcLinearAddrWidth = pVM->cpum.s.GuestFeatures.cMaxLinearAddrWidth;
|
---|
| 1142 | }
|
---|
| 1143 |
|
---|
| 1144 |
|
---|
[80253] | 1145 | VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0)
|
---|
[1] | 1146 | {
|
---|
[18927] | 1147 | pVCpu->cpum.s.Guest.dr[0] = uDr0;
|
---|
[87346] | 1148 | return CPUMRecalcHyperDRx(pVCpu, 0);
|
---|
[1] | 1149 | }
|
---|
| 1150 |
|
---|
[12657] | 1151 |
|
---|
[80253] | 1152 | VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1)
|
---|
[1] | 1153 | {
|
---|
[18927] | 1154 | pVCpu->cpum.s.Guest.dr[1] = uDr1;
|
---|
[87346] | 1155 | return CPUMRecalcHyperDRx(pVCpu, 1);
|
---|
[1] | 1156 | }
|
---|
| 1157 |
|
---|
[12657] | 1158 |
|
---|
[80253] | 1159 | VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2)
|
---|
[1] | 1160 | {
|
---|
[18927] | 1161 | pVCpu->cpum.s.Guest.dr[2] = uDr2;
|
---|
[87346] | 1162 | return CPUMRecalcHyperDRx(pVCpu, 2);
|
---|
[1] | 1163 | }
|
---|
| 1164 |
|
---|
[12657] | 1165 |
|
---|
[80253] | 1166 | VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3)
|
---|
[1] | 1167 | {
|
---|
[18927] | 1168 | pVCpu->cpum.s.Guest.dr[3] = uDr3;
|
---|
[87346] | 1169 | return CPUMRecalcHyperDRx(pVCpu, 3);
|
---|
[1] | 1170 | }
|
---|
| 1171 |
|
---|
[12657] | 1172 |
|
---|
[18927] | 1173 | VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
|
---|
[1] | 1174 | {
|
---|
[18927] | 1175 | pVCpu->cpum.s.Guest.dr[6] = uDr6;
|
---|
[72689] | 1176 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR6;
|
---|
[47660] | 1177 | return VINF_SUCCESS; /* No need to recalc. */
|
---|
[1] | 1178 | }
|
---|
| 1179 |
|
---|
[12657] | 1180 |
|
---|
[80253] | 1181 | VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7)
|
---|
[1] | 1182 | {
|
---|
[18927] | 1183 | pVCpu->cpum.s.Guest.dr[7] = uDr7;
|
---|
[72689] | 1184 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_DR7;
|
---|
[87346] | 1185 | return CPUMRecalcHyperDRx(pVCpu, 7);
|
---|
[1] | 1186 | }
|
---|
| 1187 |
|
---|
[12657] | 1188 |
|
---|
[80253] | 1189 | VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value)
|
---|
[1] | 1190 | {
|
---|
[41728] | 1191 | AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
|
---|
[12657] | 1192 | /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
|
---|
| 1193 | if (iReg == 4 || iReg == 5)
|
---|
| 1194 | iReg += 2;
|
---|
[18927] | 1195 | pVCpu->cpum.s.Guest.dr[iReg] = Value;
|
---|
[87346] | 1196 | return CPUMRecalcHyperDRx(pVCpu, iReg);
|
---|
[1] | 1197 | }
|
---|
| 1198 |
|
---|
| 1199 |
|
---|
| 1200 | /**
|
---|
[47660] | 1201 | * Recalculates the hypervisor DRx register values based on current guest
|
---|
| 1202 | * registers and DBGF breakpoints, updating changed registers depending on the
|
---|
| 1203 | * context.
|
---|
[1] | 1204 | *
|
---|
[47660] | 1205 | * This is called whenever a guest DRx register is modified (any context) and
|
---|
| 1206 | * when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
|
---|
[1] | 1207 | *
|
---|
[47660] | 1208 | * In raw-mode context this function will reload any (hyper) DRx registers which
|
---|
| 1209 | * comes out with a different value. It may also have to save the host debug
|
---|
| 1210 | * registers if that haven't been done already. In this context though, we'll
|
---|
| 1211 | * be intercepting and emulating all DRx accesses, so the hypervisor DRx values
|
---|
| 1212 | * are only important when breakpoints are actually enabled.
|
---|
| 1213 | *
|
---|
| 1214 | * In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
|
---|
| 1215 | * reloaded by the HM code if it changes. Further more, we will only use the
|
---|
| 1216 | * combined register set when the VBox debugger is actually using hardware BPs,
|
---|
| 1217 | * when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
|
---|
| 1218 | * concern us here).
|
---|
| 1219 | *
|
---|
| 1220 | * In ring-3 we won't be loading anything, so well calculate hypervisor values
|
---|
| 1221 | * all the time.
|
---|
| 1222 | *
|
---|
[1] | 1223 | * @returns VINF_SUCCESS.
|
---|
[58123] | 1224 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[47660] | 1225 | * @param iGstReg The guest debug register number that was modified.
|
---|
| 1226 | * UINT8_MAX if not guest register.
|
---|
[1] | 1227 | */
|
---|
[87346] | 1228 | VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg)
|
---|
[1] | 1229 | {
|
---|
[18927] | 1230 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
[62601] | 1231 | #ifndef IN_RING0
|
---|
| 1232 | RT_NOREF_PV(iGstReg);
|
---|
| 1233 | #endif
|
---|
[18927] | 1234 |
|
---|
[1] | 1235 | /*
|
---|
| 1236 | * Compare the DR7s first.
|
---|
| 1237 | *
|
---|
[47660] | 1238 | * We only care about the enabled flags. GD is virtualized when we
|
---|
| 1239 | * dispatch the #DB, we never enable it. The DBGF DR7 value is will
|
---|
| 1240 | * always have the LE and GE bits set, so no need to check and disable
|
---|
| 1241 | * stuff if they're cleared like we have to for the guest DR7.
|
---|
[1] | 1242 | */
|
---|
[47660] | 1243 | RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
|
---|
[72129] | 1244 | /** @todo This isn't correct. BPs work without setting LE and GE under AMD-V. They are also documented as unsupported by P6+. */
|
---|
[47660] | 1245 | if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE)))
|
---|
| 1246 | uGstDr7 = 0;
|
---|
| 1247 | else if (!(uGstDr7 & X86_DR7_LE))
|
---|
| 1248 | uGstDr7 &= ~X86_DR7_LE_ALL;
|
---|
| 1249 | else if (!(uGstDr7 & X86_DR7_GE))
|
---|
| 1250 | uGstDr7 &= ~X86_DR7_GE_ALL;
|
---|
| 1251 |
|
---|
[1] | 1252 | const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
|
---|
[87346] | 1253 | if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
|
---|
[1] | 1254 | {
|
---|
[47660] | 1255 | Assert(!CPUMIsGuestDebugStateActive(pVCpu));
|
---|
| 1256 |
|
---|
[1] | 1257 | /*
|
---|
[47660] | 1258 | * Ok, something is enabled. Recalc each of the breakpoints, taking
|
---|
| 1259 | * the VM debugger ones of the guest ones. In raw-mode context we will
|
---|
| 1260 | * not allow breakpoints with values inside the hypervisor area.
|
---|
[1] | 1261 | */
|
---|
[47328] | 1262 | RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_RA1_MASK;
|
---|
[1] | 1263 |
|
---|
| 1264 | /* bp 0 */
|
---|
| 1265 | RTGCUINTREG uNewDr0;
|
---|
| 1266 | if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
|
---|
| 1267 | {
|
---|
| 1268 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
|
---|
| 1269 | uNewDr0 = DBGFBpGetDR0(pVM);
|
---|
| 1270 | }
|
---|
| 1271 | else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
|
---|
| 1272 | {
|
---|
[18927] | 1273 | uNewDr0 = CPUMGetGuestDR0(pVCpu);
|
---|
[80050] | 1274 | uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
|
---|
[1] | 1275 | }
|
---|
| 1276 | else
|
---|
[47660] | 1277 | uNewDr0 = 0;
|
---|
[1] | 1278 |
|
---|
| 1279 | /* bp 1 */
|
---|
| 1280 | RTGCUINTREG uNewDr1;
|
---|
| 1281 | if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
|
---|
| 1282 | {
|
---|
| 1283 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
|
---|
| 1284 | uNewDr1 = DBGFBpGetDR1(pVM);
|
---|
| 1285 | }
|
---|
| 1286 | else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
|
---|
| 1287 | {
|
---|
[18927] | 1288 | uNewDr1 = CPUMGetGuestDR1(pVCpu);
|
---|
[80050] | 1289 | uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
|
---|
[1] | 1290 | }
|
---|
| 1291 | else
|
---|
[47660] | 1292 | uNewDr1 = 0;
|
---|
[1] | 1293 |
|
---|
| 1294 | /* bp 2 */
|
---|
| 1295 | RTGCUINTREG uNewDr2;
|
---|
| 1296 | if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
|
---|
| 1297 | {
|
---|
| 1298 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
|
---|
| 1299 | uNewDr2 = DBGFBpGetDR2(pVM);
|
---|
| 1300 | }
|
---|
| 1301 | else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
|
---|
| 1302 | {
|
---|
[18927] | 1303 | uNewDr2 = CPUMGetGuestDR2(pVCpu);
|
---|
[80050] | 1304 | uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
|
---|
[1] | 1305 | }
|
---|
| 1306 | else
|
---|
[47660] | 1307 | uNewDr2 = 0;
|
---|
[1] | 1308 |
|
---|
| 1309 | /* bp 3 */
|
---|
| 1310 | RTGCUINTREG uNewDr3;
|
---|
| 1311 | if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
|
---|
| 1312 | {
|
---|
| 1313 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
|
---|
| 1314 | uNewDr3 = DBGFBpGetDR3(pVM);
|
---|
| 1315 | }
|
---|
| 1316 | else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
|
---|
| 1317 | {
|
---|
[18927] | 1318 | uNewDr3 = CPUMGetGuestDR3(pVCpu);
|
---|
[80050] | 1319 | uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
|
---|
[1] | 1320 | }
|
---|
| 1321 | else
|
---|
[47660] | 1322 | uNewDr3 = 0;
|
---|
[1] | 1323 |
|
---|
| 1324 | /*
|
---|
| 1325 | * Apply the updates.
|
---|
| 1326 | */
|
---|
[80050] | 1327 | pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
|
---|
| 1328 | if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
|
---|
| 1329 | CPUMSetHyperDR3(pVCpu, uNewDr3);
|
---|
| 1330 | if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
|
---|
| 1331 | CPUMSetHyperDR2(pVCpu, uNewDr2);
|
---|
| 1332 | if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
|
---|
| 1333 | CPUMSetHyperDR1(pVCpu, uNewDr1);
|
---|
| 1334 | if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
|
---|
| 1335 | CPUMSetHyperDR0(pVCpu, uNewDr0);
|
---|
| 1336 | if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
|
---|
| 1337 | CPUMSetHyperDR7(pVCpu, uNewDr7);
|
---|
[1] | 1338 | }
|
---|
[47660] | 1339 | #ifdef IN_RING0
|
---|
| 1340 | else if (CPUMIsGuestDebugStateActive(pVCpu))
|
---|
| 1341 | {
|
---|
| 1342 | /*
|
---|
| 1343 | * Reload the register that was modified. Normally this won't happen
|
---|
| 1344 | * as we won't intercept DRx writes when not having the hyper debug
|
---|
| 1345 | * state loaded, but in case we do for some reason we'll simply deal
|
---|
| 1346 | * with it.
|
---|
| 1347 | */
|
---|
| 1348 | switch (iGstReg)
|
---|
| 1349 | {
|
---|
| 1350 | case 0: ASMSetDR0(CPUMGetGuestDR0(pVCpu)); break;
|
---|
| 1351 | case 1: ASMSetDR1(CPUMGetGuestDR1(pVCpu)); break;
|
---|
| 1352 | case 2: ASMSetDR2(CPUMGetGuestDR2(pVCpu)); break;
|
---|
| 1353 | case 3: ASMSetDR3(CPUMGetGuestDR3(pVCpu)); break;
|
---|
| 1354 | default:
|
---|
| 1355 | AssertReturn(iGstReg != UINT8_MAX, VERR_INTERNAL_ERROR_3);
|
---|
| 1356 | }
|
---|
| 1357 | }
|
---|
| 1358 | #endif
|
---|
[1] | 1359 | else
|
---|
| 1360 | {
|
---|
[47660] | 1361 | /*
|
---|
| 1362 | * No active debug state any more. In raw-mode this means we have to
|
---|
| 1363 | * make sure DR7 has everything disabled now, if we armed it already.
|
---|
[47714] | 1364 | * In ring-0 we might end up here when just single stepping.
|
---|
[47660] | 1365 | */
|
---|
[80064] | 1366 | #ifdef IN_RING0
|
---|
[47660] | 1367 | if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER)
|
---|
[1] | 1368 | {
|
---|
[47660] | 1369 | if (pVCpu->cpum.s.Hyper.dr[0])
|
---|
| 1370 | ASMSetDR0(0);
|
---|
| 1371 | if (pVCpu->cpum.s.Hyper.dr[1])
|
---|
| 1372 | ASMSetDR1(0);
|
---|
| 1373 | if (pVCpu->cpum.s.Hyper.dr[2])
|
---|
| 1374 | ASMSetDR2(0);
|
---|
| 1375 | if (pVCpu->cpum.s.Hyper.dr[3])
|
---|
| 1376 | ASMSetDR3(0);
|
---|
| 1377 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_DEBUG_REGS_HYPER;
|
---|
[1] | 1378 | }
|
---|
| 1379 | #endif
|
---|
[47660] | 1380 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
|
---|
| 1381 |
|
---|
| 1382 | /* Clear all the registers. */
|
---|
| 1383 | pVCpu->cpum.s.Hyper.dr[7] = X86_DR7_RA1_MASK;
|
---|
| 1384 | pVCpu->cpum.s.Hyper.dr[3] = 0;
|
---|
| 1385 | pVCpu->cpum.s.Hyper.dr[2] = 0;
|
---|
| 1386 | pVCpu->cpum.s.Hyper.dr[1] = 0;
|
---|
| 1387 | pVCpu->cpum.s.Hyper.dr[0] = 0;
|
---|
| 1388 |
|
---|
[1] | 1389 | }
|
---|
| 1390 | Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
|
---|
[18927] | 1391 | pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
|
---|
[47660] | 1392 | pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
|
---|
| 1393 | pVCpu->cpum.s.Hyper.dr[7]));
|
---|
[1] | 1394 |
|
---|
| 1395 | return VINF_SUCCESS;
|
---|
| 1396 | }
|
---|
| 1397 |
|
---|
[25835] | 1398 |
|
---|
| 1399 | /**
|
---|
[55289] | 1400 | * Set the guest XCR0 register.
|
---|
| 1401 | *
|
---|
[55312] | 1402 | * Will load additional state if the FPU state is already loaded (in ring-0 &
|
---|
| 1403 | * raw-mode context).
|
---|
| 1404 | *
|
---|
[55289] | 1405 | * @returns VINF_SUCCESS on success, VERR_CPUM_RAISE_GP_0 on invalid input
|
---|
| 1406 | * value.
|
---|
[58123] | 1407 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[55289] | 1408 | * @param uNewValue The new value.
|
---|
| 1409 | * @thread EMT(pVCpu)
|
---|
| 1410 | */
|
---|
[80253] | 1411 | VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue)
|
---|
[55289] | 1412 | {
|
---|
[72676] | 1413 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_XCRx);
|
---|
[55289] | 1414 | if ( (uNewValue & ~pVCpu->CTX_SUFF(pVM)->cpum.s.fXStateGuestMask) == 0
|
---|
| 1415 | /* The X87 bit cannot be cleared. */
|
---|
| 1416 | && (uNewValue & XSAVE_C_X87)
|
---|
| 1417 | /* AVX requires SSE. */
|
---|
| 1418 | && (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM
|
---|
| 1419 | /* AVX-512 requires YMM, SSE and all of its three components to be enabled. */
|
---|
| 1420 | && ( (uNewValue & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
|
---|
| 1421 | || (uNewValue & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
|
---|
| 1422 | == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI) )
|
---|
| 1423 | )
|
---|
| 1424 | {
|
---|
| 1425 | pVCpu->cpum.s.Guest.aXcr[0] = uNewValue;
|
---|
[55312] | 1426 |
|
---|
| 1427 | /* If more state components are enabled, we need to take care to load
|
---|
| 1428 | them if the FPU/SSE state is already loaded. May otherwise leak
|
---|
| 1429 | host state to the guest. */
|
---|
| 1430 | uint64_t fNewComponents = ~pVCpu->cpum.s.Guest.fXStateMask & uNewValue;
|
---|
| 1431 | if (fNewComponents)
|
---|
| 1432 | {
|
---|
[80064] | 1433 | #ifdef IN_RING0
|
---|
[61058] | 1434 | if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
|
---|
[55312] | 1435 | {
|
---|
| 1436 | if (pVCpu->cpum.s.Guest.fXStateMask != 0)
|
---|
| 1437 | /* Adding more components. */
|
---|
[91281] | 1438 | ASMXRstor(&pVCpu->cpum.s.Guest.XState, fNewComponents);
|
---|
[55312] | 1439 | else
|
---|
| 1440 | {
|
---|
| 1441 | /* We're switching from FXSAVE/FXRSTOR to XSAVE/XRSTOR. */
|
---|
| 1442 | pVCpu->cpum.s.Guest.fXStateMask |= XSAVE_C_X87 | XSAVE_C_SSE;
|
---|
| 1443 | if (uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE))
|
---|
[91281] | 1444 | ASMXRstor(&pVCpu->cpum.s.Guest.XState, uNewValue & ~(XSAVE_C_X87 | XSAVE_C_SSE));
|
---|
[55312] | 1445 | }
|
---|
| 1446 | }
|
---|
| 1447 | #endif
|
---|
| 1448 | pVCpu->cpum.s.Guest.fXStateMask |= uNewValue;
|
---|
| 1449 | }
|
---|
[55289] | 1450 | return VINF_SUCCESS;
|
---|
| 1451 | }
|
---|
| 1452 | return VERR_CPUM_RAISE_GP_0;
|
---|
| 1453 | }
|
---|
| 1454 |
|
---|
| 1455 |
|
---|
| 1456 | /**
|
---|
[25835] | 1457 | * Tests if the guest has No-Execute Page Protection Enabled (NXE).
|
---|
| 1458 | *
|
---|
| 1459 | * @returns true if in real mode, otherwise false.
|
---|
[58123] | 1460 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[25835] | 1461 | */
|
---|
[79146] | 1462 | VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu)
|
---|
[25835] | 1463 | {
|
---|
[72676] | 1464 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
|
---|
[25835] | 1465 | return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
|
---|
| 1466 | }
|
---|
| 1467 |
|
---|
| 1468 |
|
---|
| 1469 | /**
|
---|
[25866] | 1470 | * Tests if the guest has the Page Size Extension enabled (PSE).
|
---|
| 1471 | *
|
---|
| 1472 | * @returns true if in real mode, otherwise false.
|
---|
[58123] | 1473 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[25866] | 1474 | */
|
---|
[79146] | 1475 | VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu)
|
---|
[25866] | 1476 | {
|
---|
[72676] | 1477 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4);
|
---|
[26635] | 1478 | /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
|
---|
[26673] | 1479 | return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
|
---|
[25866] | 1480 | }
|
---|
| 1481 |
|
---|
| 1482 |
|
---|
| 1483 | /**
|
---|
| 1484 | * Tests if the guest has the paging enabled (PG).
|
---|
| 1485 | *
|
---|
| 1486 | * @returns true if in real mode, otherwise false.
|
---|
[58123] | 1487 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[25866] | 1488 | */
|
---|
[79146] | 1489 | VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu)
|
---|
[25866] | 1490 | {
|
---|
[72676] | 1491 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
|
---|
[25866] | 1492 | return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
|
---|
| 1493 | }
|
---|
| 1494 |
|
---|
| 1495 |
|
---|
| 1496 | /**
|
---|
| 1497 | * Tests if the guest has the paging enabled (PG).
|
---|
| 1498 | *
|
---|
| 1499 | * @returns true if in real mode, otherwise false.
|
---|
[58123] | 1500 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[25866] | 1501 | */
|
---|
[79146] | 1502 | VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu)
|
---|
[25866] | 1503 | {
|
---|
[72676] | 1504 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
|
---|
[25866] | 1505 | return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
|
---|
| 1506 | }
|
---|
| 1507 |
|
---|
| 1508 |
|
---|
| 1509 | /**
|
---|
[25835] | 1510 | * Tests if the guest is running in real mode or not.
|
---|
| 1511 | *
|
---|
| 1512 | * @returns true if in real mode, otherwise false.
|
---|
[58123] | 1513 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[25835] | 1514 | */
|
---|
[79146] | 1515 | VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu)
|
---|
[25835] | 1516 | {
|
---|
[72676] | 1517 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
|
---|
[25835] | 1518 | return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
|
---|
| 1519 | }
|
---|
| 1520 |
|
---|
| 1521 |
|
---|
| 1522 | /**
|
---|
[36639] | 1523 | * Tests if the guest is running in real or virtual 8086 mode.
|
---|
| 1524 | *
|
---|
| 1525 | * @returns @c true if it is, @c false if not.
|
---|
[58123] | 1526 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[36639] | 1527 | */
|
---|
[79146] | 1528 | VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu)
|
---|
[36639] | 1529 | {
|
---|
[72676] | 1530 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS);
|
---|
[36639] | 1531 | return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
|
---|
| 1532 | || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
|
---|
| 1533 | }
|
---|
| 1534 |
|
---|
| 1535 |
|
---|
| 1536 | /**
|
---|
[25835] | 1537 | * Tests if the guest is running in protected or not.
|
---|
| 1538 | *
|
---|
| 1539 | * @returns true if in protected mode, otherwise false.
|
---|
[58123] | 1540 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[25835] | 1541 | */
|
---|
[79146] | 1542 | VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu)
|
---|
[25835] | 1543 | {
|
---|
[72676] | 1544 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
|
---|
[25835] | 1545 | return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
|
---|
| 1546 | }
|
---|
| 1547 |
|
---|
| 1548 |
|
---|
| 1549 | /**
|
---|
| 1550 | * Tests if the guest is running in paged protected or not.
|
---|
| 1551 | *
|
---|
| 1552 | * @returns true if in paged protected mode, otherwise false.
|
---|
[58123] | 1553 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[25835] | 1554 | */
|
---|
[79146] | 1555 | VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu)
|
---|
[25835] | 1556 | {
|
---|
[72676] | 1557 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0);
|
---|
[25835] | 1558 | return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
|
---|
| 1559 | }
|
---|
| 1560 |
|
---|
| 1561 |
|
---|
| 1562 | /**
|
---|
| 1563 | * Tests if the guest is running in long mode or not.
|
---|
| 1564 | *
|
---|
| 1565 | * @returns true if in long mode, otherwise false.
|
---|
[58123] | 1566 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[25835] | 1567 | */
|
---|
[79146] | 1568 | VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu)
|
---|
[25835] | 1569 | {
|
---|
[72676] | 1570 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_EFER);
|
---|
[25835] | 1571 | return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
|
---|
| 1572 | }
|
---|
| 1573 |
|
---|
| 1574 |
|
---|
| 1575 | /**
|
---|
| 1576 | * Tests if the guest is running in PAE mode or not.
|
---|
| 1577 | *
|
---|
| 1578 | * @returns true if in PAE mode, otherwise false.
|
---|
[58123] | 1579 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[25835] | 1580 | */
|
---|
[79146] | 1581 | VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu)
|
---|
[25835] | 1582 | {
|
---|
[72676] | 1583 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
|
---|
[49849] | 1584 | /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
|
---|
| 1585 | than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
|
---|
[25835] | 1586 | return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
|
---|
[45291] | 1587 | && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG)
|
---|
[49849] | 1588 | && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
|
---|
[25835] | 1589 | }
|
---|
| 1590 |
|
---|
| 1591 |
|
---|
[42165] | 1592 | /**
|
---|
| 1593 | * Tests if the guest is running in 64 bits mode or not.
|
---|
| 1594 | *
|
---|
| 1595 | * @returns true if in 64 bits protected mode, otherwise false.
|
---|
[58123] | 1596 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[42165] | 1597 | */
|
---|
| 1598 | VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
|
---|
| 1599 | {
|
---|
[72676] | 1600 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
|
---|
[42165] | 1601 | if (!CPUMIsGuestInLongMode(pVCpu))
|
---|
| 1602 | return false;
|
---|
[42407] | 1603 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
|
---|
[42165] | 1604 | return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
|
---|
| 1605 | }
|
---|
| 1606 |
|
---|
| 1607 |
|
---|
| 1608 | /**
|
---|
| 1609 | * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
|
---|
| 1610 | * registers.
|
---|
| 1611 | *
|
---|
| 1612 | * @returns true if in 64 bits protected mode, otherwise false.
|
---|
| 1613 | * @param pCtx Pointer to the current guest CPU context.
|
---|
| 1614 | */
|
---|
| 1615 | VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
|
---|
| 1616 | {
|
---|
| 1617 | return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
|
---|
| 1618 | }
|
---|
| 1619 |
|
---|
[46165] | 1620 |
|
---|
[42407] | 1621 | /**
|
---|
[1] | 1622 | * Sets the specified changed flags (CPUM_CHANGED_*).
|
---|
| 1623 | *
|
---|
[58123] | 1624 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[58126] | 1625 | * @param fChangedAdd The changed flags to add.
|
---|
[1] | 1626 | */
|
---|
[58126] | 1627 | VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd)
|
---|
[1] | 1628 | {
|
---|
[58126] | 1629 | pVCpu->cpum.s.fChanged |= fChangedAdd;
|
---|
[1] | 1630 | }
|
---|
| 1631 |
|
---|
[12657] | 1632 |
|
---|
[1] | 1633 | /**
|
---|
[55062] | 1634 | * Checks if the CPU supports the XSAVE and XRSTOR instruction.
|
---|
| 1635 | *
|
---|
[1] | 1636 | * @returns true if supported.
|
---|
| 1637 | * @returns false if not supported.
|
---|
[58122] | 1638 | * @param pVM The cross context VM structure.
|
---|
[1] | 1639 | */
|
---|
[55062] | 1640 | VMMDECL(bool) CPUMSupportsXSave(PVM pVM)
|
---|
[1] | 1641 | {
|
---|
[55062] | 1642 | return pVM->cpum.s.HostFeatures.fXSaveRstor != 0;
|
---|
[1] | 1643 | }
|
---|
| 1644 |
|
---|
| 1645 |
|
---|
| 1646 | /**
|
---|
| 1647 | * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
|
---|
| 1648 | * @returns true if used.
|
---|
| 1649 | * @returns false if not used.
|
---|
[58122] | 1650 | * @param pVM The cross context VM structure.
|
---|
[1] | 1651 | */
|
---|
[12989] | 1652 | VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
|
---|
[1] | 1653 | {
|
---|
[47660] | 1654 | return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER);
|
---|
[1] | 1655 | }
|
---|
| 1656 |
|
---|
| 1657 |
|
---|
| 1658 | /**
|
---|
| 1659 | * Checks if the host OS uses the SYSCALL / SYSRET instructions.
|
---|
| 1660 | * @returns true if used.
|
---|
| 1661 | * @returns false if not used.
|
---|
[58122] | 1662 | * @param pVM The cross context VM structure.
|
---|
[1] | 1663 | */
|
---|
[12989] | 1664 | VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
|
---|
[1] | 1665 | {
|
---|
[47660] | 1666 | return RT_BOOL(pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL);
|
---|
[1] | 1667 | }
|
---|
| 1668 |
|
---|
[5695] | 1669 |
|
---|
[1] | 1670 | /**
|
---|
[42034] | 1671 | * Checks if we activated the FPU/XMM state of the guest OS.
|
---|
[61058] | 1672 | *
|
---|
[87345] | 1673 | * Obsolete: This differs from CPUMIsGuestFPUStateLoaded() in that it refers to
|
---|
| 1674 | * the next time we'll be executing guest code, so it may return true for
|
---|
| 1675 | * 64-on-32 when we still haven't actually loaded the FPU status, just scheduled
|
---|
| 1676 | * it to be loaded the next time we go thru the world switcher
|
---|
| 1677 | * (CPUM_SYNC_FPU_STATE).
|
---|
[61066] | 1678 | *
|
---|
| 1679 | * @returns true / false.
|
---|
[58123] | 1680 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[1] | 1681 | */
|
---|
[13960] | 1682 | VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
|
---|
[1] | 1683 | {
|
---|
[87361] | 1684 | bool fRet = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
|
---|
| 1685 | AssertMsg(fRet == pVCpu->cpum.s.Guest.fUsedFpuGuest, ("fRet=%d\n", fRet));
|
---|
| 1686 | return fRet;
|
---|
[61066] | 1687 | }
|
---|
| 1688 |
|
---|
| 1689 |
|
---|
| 1690 | /**
|
---|
| 1691 | * Checks if we've really loaded the FPU/XMM state of the guest OS.
|
---|
| 1692 | *
|
---|
| 1693 | * @returns true / false.
|
---|
| 1694 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 1695 | */
|
---|
| 1696 | VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu)
|
---|
| 1697 | {
|
---|
[87361] | 1698 | bool fRet = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
|
---|
| 1699 | AssertMsg(fRet == pVCpu->cpum.s.Guest.fUsedFpuGuest, ("fRet=%d\n", fRet));
|
---|
| 1700 | return fRet;
|
---|
[1] | 1701 | }
|
---|
| 1702 |
|
---|
[5695] | 1703 |
|
---|
[1] | 1704 | /**
|
---|
[61058] | 1705 | * Checks if we saved the FPU/XMM state of the host OS.
|
---|
| 1706 | *
|
---|
| 1707 | * @returns true / false.
|
---|
| 1708 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 1709 | */
|
---|
| 1710 | VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu)
|
---|
| 1711 | {
|
---|
| 1712 | return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST);
|
---|
| 1713 | }
|
---|
| 1714 |
|
---|
| 1715 |
|
---|
| 1716 | /**
|
---|
[42034] | 1717 | * Checks if the guest debug state is active.
|
---|
[12578] | 1718 | *
|
---|
| 1719 | * @returns boolean
|
---|
[58126] | 1720 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[12578] | 1721 | */
|
---|
[18927] | 1722 | VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
|
---|
[12578] | 1723 | {
|
---|
[47660] | 1724 | return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST);
|
---|
[12578] | 1725 | }
|
---|
| 1726 |
|
---|
[48544] | 1727 |
|
---|
[21252] | 1728 | /**
|
---|
[42034] | 1729 | * Checks if the hyper debug state is active.
|
---|
[21252] | 1730 | *
|
---|
| 1731 | * @returns boolean
|
---|
[58126] | 1732 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[21252] | 1733 | */
|
---|
| 1734 | VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
|
---|
| 1735 | {
|
---|
[47660] | 1736 | return RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HYPER);
|
---|
[21252] | 1737 | }
|
---|
[12657] | 1738 |
|
---|
[21252] | 1739 |
|
---|
[12578] | 1740 | /**
|
---|
[30263] | 1741 | * Mark the guest's debug state as inactive.
|
---|
[12578] | 1742 | *
|
---|
[58126] | 1743 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[47660] | 1744 | * @todo This API doesn't make sense any more.
|
---|
[12578] | 1745 | */
|
---|
[18927] | 1746 | VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
|
---|
[12578] | 1747 | {
|
---|
[47660] | 1748 | Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
|
---|
[57856] | 1749 | NOREF(pVCpu);
|
---|
[12578] | 1750 | }
|
---|
| 1751 |
|
---|
| 1752 |
|
---|
| 1753 | /**
|
---|
[1828] | 1754 | * Get the current privilege level of the guest.
|
---|
| 1755 | *
|
---|
[41939] | 1756 | * @returns CPL
|
---|
[58123] | 1757 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[1828] | 1758 | */
|
---|
[41939] | 1759 | VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
|
---|
[1828] | 1760 | {
|
---|
[42166] | 1761 | /*
|
---|
| 1762 | * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
|
---|
| 1763 | *
|
---|
| 1764 | * Note! We used to check CS.DPL here, assuming it was always equal to
|
---|
[66227] | 1765 | * CPL even if a conforming segment was loaded. But this turned out to
|
---|
[42166] | 1766 | * only apply to older AMD-V. With VT-x we had an ACP2 regression
|
---|
| 1767 | * during install after a far call to ring 2 with VT-x. Then on newer
|
---|
| 1768 | * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
|
---|
| 1769 | * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
|
---|
| 1770 | *
|
---|
| 1771 | * So, forget CS.DPL, always use SS.DPL.
|
---|
| 1772 | *
|
---|
| 1773 | * Note! The SS RPL is always equal to the CPL, while the CS RPL
|
---|
| 1774 | * isn't necessarily equal if the segment is conforming.
|
---|
| 1775 | * See section 4.11.1 in the AMD manual.
|
---|
[47225] | 1776 | *
|
---|
| 1777 | * Update: Where the heck does it say CS.RPL can differ from CPL other than
|
---|
| 1778 | * right after real->prot mode switch and when in V8086 mode? That
|
---|
| 1779 | * section says the RPL specified in a direct transfere (call, jmp,
|
---|
| 1780 | * ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
|
---|
| 1781 | * it would be impossible for an exception handle or the iret
|
---|
| 1782 | * instruction to figure out whether SS:ESP are part of the frame
|
---|
| 1783 | * or not. VBox or qemu bug must've lead to this misconception.
|
---|
[47242] | 1784 | *
|
---|
| 1785 | * Update2: On an AMD bulldozer system here, I've no trouble loading a null
|
---|
| 1786 | * selector into SS with an RPL other than the CPL when CPL != 3 and
|
---|
| 1787 | * we're in 64-bit mode. The intel dev box doesn't allow this, on
|
---|
| 1788 | * RPL = CPL. Weird.
|
---|
[42166] | 1789 | */
|
---|
[72676] | 1790 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
|
---|
[41939] | 1791 | uint32_t uCpl;
|
---|
[42166] | 1792 | if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
|
---|
[10523] | 1793 | {
|
---|
[42166] | 1794 | if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
|
---|
[31512] | 1795 | {
|
---|
[42407] | 1796 | if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
|
---|
[41939] | 1797 | uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
|
---|
[31512] | 1798 | else
|
---|
[42166] | 1799 | uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
|
---|
[1969] | 1800 | }
|
---|
| 1801 | else
|
---|
[42166] | 1802 | uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
|
---|
[1828] | 1803 | }
|
---|
| 1804 | else
|
---|
[42166] | 1805 | uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
|
---|
[41939] | 1806 | return uCpl;
|
---|
[1828] | 1807 | }
|
---|
[4207] | 1808 |
|
---|
| 1809 |
|
---|
| 1810 | /**
|
---|
| 1811 | * Gets the current guest CPU mode.
|
---|
| 1812 | *
|
---|
| 1813 | * If paging mode is what you need, check out PGMGetGuestMode().
|
---|
| 1814 | *
|
---|
| 1815 | * @returns The CPU mode.
|
---|
[58123] | 1816 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[4207] | 1817 | */
|
---|
[18927] | 1818 | VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
|
---|
[4207] | 1819 | {
|
---|
[72676] | 1820 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
|
---|
[4207] | 1821 | CPUMMODE enmMode;
|
---|
[18927] | 1822 | if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
|
---|
[4207] | 1823 | enmMode = CPUMMODE_REAL;
|
---|
[18927] | 1824 | else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
|
---|
[4207] | 1825 | enmMode = CPUMMODE_PROTECTED;
|
---|
[9543] | 1826 | else
|
---|
| 1827 | enmMode = CPUMMODE_LONG;
|
---|
[4207] | 1828 |
|
---|
| 1829 | return enmMode;
|
---|
| 1830 | }
|
---|
[42186] | 1831 |
|
---|
| 1832 |
|
---|
| 1833 | /**
|
---|
| 1834 | * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
|
---|
| 1835 | *
|
---|
| 1836 | * @returns 16, 32 or 64.
|
---|
[58123] | 1837 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[42186] | 1838 | */
|
---|
| 1839 | VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
|
---|
| 1840 | {
|
---|
[72676] | 1841 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
|
---|
| 1842 |
|
---|
[42186] | 1843 | if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
|
---|
| 1844 | return 16;
|
---|
| 1845 |
|
---|
| 1846 | if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
|
---|
| 1847 | {
|
---|
| 1848 | Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
|
---|
| 1849 | return 16;
|
---|
| 1850 | }
|
---|
| 1851 |
|
---|
[42407] | 1852 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
|
---|
[42186] | 1853 | if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
|
---|
| 1854 | && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
|
---|
| 1855 | return 64;
|
---|
| 1856 |
|
---|
| 1857 | if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
|
---|
| 1858 | return 32;
|
---|
| 1859 |
|
---|
| 1860 | return 16;
|
---|
| 1861 | }
|
---|
| 1862 |
|
---|
| 1863 |
|
---|
| 1864 | VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
|
---|
| 1865 | {
|
---|
[72676] | 1866 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS);
|
---|
| 1867 |
|
---|
[42186] | 1868 | if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
|
---|
| 1869 | return DISCPUMODE_16BIT;
|
---|
| 1870 |
|
---|
| 1871 | if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
|
---|
| 1872 | {
|
---|
| 1873 | Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
|
---|
| 1874 | return DISCPUMODE_16BIT;
|
---|
| 1875 | }
|
---|
| 1876 |
|
---|
[42407] | 1877 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
|
---|
[42186] | 1878 | if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
|
---|
| 1879 | && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
|
---|
| 1880 | return DISCPUMODE_64BIT;
|
---|
| 1881 |
|
---|
| 1882 | if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
|
---|
| 1883 | return DISCPUMODE_32BIT;
|
---|
| 1884 |
|
---|
| 1885 | return DISCPUMODE_16BIT;
|
---|
| 1886 | }
|
---|
| 1887 |
|
---|
[66403] | 1888 |
|
---|
| 1889 | /**
|
---|
| 1890 | * Gets the guest MXCSR_MASK value.
|
---|
| 1891 | *
|
---|
| 1892 | * This does not access the x87 state, but the value we determined at VM
|
---|
| 1893 | * initialization.
|
---|
| 1894 | *
|
---|
| 1895 | * @returns MXCSR mask.
|
---|
| 1896 | * @param pVM The cross context VM structure.
|
---|
| 1897 | */
|
---|
| 1898 | VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM)
|
---|
| 1899 | {
|
---|
| 1900 | return pVM->cpum.s.GuestInfo.fMxCsrMask;
|
---|
| 1901 | }
|
---|
| 1902 |
|
---|
[67258] | 1903 |
|
---|
| 1904 | /**
|
---|
[75830] | 1905 | * Returns whether the guest has physical interrupts enabled.
|
---|
[75729] | 1906 | *
|
---|
[75830] | 1907 | * @returns @c true if interrupts are enabled, @c false otherwise.
|
---|
| 1908 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[75729] | 1909 | *
|
---|
[75830] | 1910 | * @remarks Warning! This function does -not- take into account the global-interrupt
|
---|
| 1911 | * flag (GIF).
|
---|
| 1912 | */
|
---|
| 1913 | VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu)
|
---|
| 1914 | {
|
---|
[97096] | 1915 | switch (CPUMGetGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest))
|
---|
[75830] | 1916 | {
|
---|
[97096] | 1917 | case CPUMHWVIRT_NONE:
|
---|
| 1918 | default:
|
---|
| 1919 | return pVCpu->cpum.s.Guest.eflags.Bits.u1IF;
|
---|
| 1920 | case CPUMHWVIRT_VMX:
|
---|
| 1921 | return CPUMIsGuestVmxPhysIntrEnabled(&pVCpu->cpum.s.Guest);
|
---|
| 1922 | case CPUMHWVIRT_SVM:
|
---|
| 1923 | return CPUMIsGuestSvmPhysIntrEnabled(pVCpu, &pVCpu->cpum.s.Guest);
|
---|
[75830] | 1924 | }
|
---|
| 1925 | }
|
---|
| 1926 |
|
---|
| 1927 |
|
---|
| 1928 | /**
|
---|
| 1929 | * Returns whether the nested-guest has virtual interrupts enabled.
|
---|
| 1930 | *
|
---|
| 1931 | * @returns @c true if interrupts are enabled, @c false otherwise.
|
---|
[75729] | 1932 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[75830] | 1933 | *
|
---|
| 1934 | * @remarks Warning! This function does -not- take into account the global-interrupt
|
---|
| 1935 | * flag (GIF).
|
---|
[75729] | 1936 | */
|
---|
[75830] | 1937 | VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu)
|
---|
[75729] | 1938 | {
|
---|
[81665] | 1939 | PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
|
---|
| 1940 | Assert(CPUMIsGuestInNestedHwvirtMode(pCtx));
|
---|
[75729] | 1941 |
|
---|
[81665] | 1942 | if (CPUMIsGuestInVmxNonRootMode(pCtx))
|
---|
| 1943 | return CPUMIsGuestVmxVirtIntrEnabled(pCtx);
|
---|
[75729] | 1944 |
|
---|
[81665] | 1945 | Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
|
---|
| 1946 | return CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
|
---|
[75729] | 1947 | }
|
---|
| 1948 |
|
---|
| 1949 |
|
---|
| 1950 | /**
|
---|
[75646] | 1951 | * Calculates the interruptiblity of the guest.
|
---|
| 1952 | *
|
---|
| 1953 | * @returns Interruptibility level.
|
---|
| 1954 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 1955 | */
|
---|
| 1956 | VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu)
|
---|
| 1957 | {
|
---|
[75729] | 1958 | #if 1
|
---|
[75830] | 1959 | /* Global-interrupt flag blocks pretty much everything we care about here. */
|
---|
| 1960 | if (CPUMGetGuestGif(&pVCpu->cpum.s.Guest))
|
---|
[75729] | 1961 | {
|
---|
[75830] | 1962 | /*
|
---|
| 1963 | * Physical interrupts are primarily blocked using EFLAGS. However, we cannot access
|
---|
| 1964 | * it directly here. If and how EFLAGS are used depends on the context (nested-guest
|
---|
| 1965 | * or raw-mode). Hence we use the function below which handles the details.
|
---|
| 1966 | */
|
---|
[97286] | 1967 | if ( !(pVCpu->cpum.s.Guest.eflags.uBoth & CPUMCTX_INHIBIT_ALL_MASK)
|
---|
| 1968 | || ( !(pVCpu->cpum.s.Guest.eflags.uBoth & CPUMCTX_INHIBIT_NMI)
|
---|
[97178] | 1969 | && pVCpu->cpum.s.Guest.uRipInhibitInt != pVCpu->cpum.s.Guest.rip))
|
---|
[75729] | 1970 | {
|
---|
[97178] | 1971 | /** @todo OPT: this next call should be inlined! */
|
---|
| 1972 | if (CPUMIsGuestPhysIntrEnabled(pVCpu))
|
---|
| 1973 | {
|
---|
| 1974 | /** @todo OPT: type this out as it repeats tests. */
|
---|
| 1975 | if ( !CPUMIsGuestInNestedHwvirtMode(&pVCpu->cpum.s.Guest)
|
---|
| 1976 | || CPUMIsGuestVirtIntrEnabled(pVCpu))
|
---|
| 1977 | return CPUMINTERRUPTIBILITY_UNRESTRAINED;
|
---|
[75729] | 1978 |
|
---|
[97178] | 1979 | /* Physical interrupts are enabled, but nested-guest virtual interrupts are disabled. */
|
---|
| 1980 | return CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED;
|
---|
| 1981 | }
|
---|
| 1982 | return CPUMINTERRUPTIBILITY_INT_DISABLED;
|
---|
[75830] | 1983 | }
|
---|
| 1984 |
|
---|
| 1985 | /*
|
---|
| 1986 | * Blocking the delivery of NMIs during an interrupt shadow is CPU implementation
|
---|
| 1987 | * specific. Therefore, in practice, we can't deliver an NMI in an interrupt shadow.
|
---|
| 1988 | * However, there is some uncertainity regarding the converse, i.e. whether
|
---|
| 1989 | * NMI-blocking until IRET blocks delivery of physical interrupts.
|
---|
| 1990 | *
|
---|
| 1991 | * See Intel spec. 25.4.1 "Event Blocking".
|
---|
| 1992 | */
|
---|
[97178] | 1993 | /** @todo r=bird: The above comment mixes up VMX root-mode and non-root. Section
|
---|
| 1994 | * 25.4.1 is only applicable to VMX non-root mode. In root mode /
|
---|
| 1995 | * non-VMX mode, I have not see any evidence in the intel manuals that
|
---|
| 1996 | * NMIs are not blocked when in an interrupt shadow. Section "6.7
|
---|
| 1997 | * NONMASKABLE INTERRUPT (NMI)" in SDM 3A seems pretty clear to me.
|
---|
| 1998 | */
|
---|
[97286] | 1999 | if (!(pVCpu->cpum.s.Guest.eflags.uBoth & CPUMCTX_INHIBIT_NMI))
|
---|
[75830] | 2000 | return CPUMINTERRUPTIBILITY_INT_INHIBITED;
|
---|
[97178] | 2001 | return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
|
---|
[75729] | 2002 | }
|
---|
| 2003 | return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
|
---|
| 2004 | #else
|
---|
[75646] | 2005 | if (pVCpu->cpum.s.Guest.rflags.Bits.u1IF)
|
---|
| 2006 | {
|
---|
| 2007 | if (pVCpu->cpum.s.Guest.hwvirt.fGif)
|
---|
| 2008 | {
|
---|
| 2009 | if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS | VMCPU_FF_INHIBIT_INTERRUPTS))
|
---|
| 2010 | return CPUMINTERRUPTIBILITY_UNRESTRAINED;
|
---|
| 2011 |
|
---|
| 2012 | /** @todo does blocking NMIs mean interrupts are also inhibited? */
|
---|
| 2013 | if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
|
---|
| 2014 | {
|
---|
| 2015 | if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
|
---|
| 2016 | return CPUMINTERRUPTIBILITY_INT_INHIBITED;
|
---|
| 2017 | return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
|
---|
| 2018 | }
|
---|
| 2019 | AssertFailed();
|
---|
| 2020 | return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
|
---|
| 2021 | }
|
---|
| 2022 | return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
|
---|
| 2023 | }
|
---|
| 2024 | else
|
---|
| 2025 | {
|
---|
| 2026 | if (pVCpu->cpum.s.Guest.hwvirt.fGif)
|
---|
| 2027 | {
|
---|
| 2028 | if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
|
---|
| 2029 | return CPUMINTERRUPTIBILITY_NMI_INHIBIT;
|
---|
| 2030 | return CPUMINTERRUPTIBILITY_INT_DISABLED;
|
---|
| 2031 | }
|
---|
| 2032 | return CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT;
|
---|
| 2033 | }
|
---|
[75729] | 2034 | #endif
|
---|
[75646] | 2035 | }
|
---|
| 2036 |
|
---|
| 2037 |
|
---|
| 2038 | /**
|
---|
[75830] | 2039 | * Checks whether the SVM nested-guest has physical interrupts enabled.
|
---|
[75413] | 2040 | *
|
---|
[75830] | 2041 | * @returns true if interrupts are enabled, false otherwise.
|
---|
[75413] | 2042 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
| 2043 | * @param pCtx The guest-CPU context.
|
---|
[75830] | 2044 | *
|
---|
| 2045 | * @remarks This does -not- take into account the global-interrupt flag.
|
---|
[75413] | 2046 | */
|
---|
[78866] | 2047 | VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
|
---|
[67258] | 2048 | {
|
---|
[70234] | 2049 | /** @todo Optimization: Avoid this function call and use a pointer to the
|
---|
| 2050 | * relevant eflags instead (setup during VMRUN instruction emulation). */
|
---|
[67258] | 2051 | Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
|
---|
| 2052 |
|
---|
[72065] | 2053 | X86EFLAGS fEFlags;
|
---|
| 2054 | if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, pCtx))
|
---|
| 2055 | fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
|
---|
| 2056 | else
|
---|
| 2057 | fEFlags.u = pCtx->eflags.u;
|
---|
[67258] | 2058 |
|
---|
[72065] | 2059 | return fEFlags.Bits.u1IF;
|
---|
[67258] | 2060 | }
|
---|
| 2061 |
|
---|
| 2062 |
|
---|
| 2063 | /**
|
---|
[70781] | 2064 | * Checks whether the SVM nested-guest is in a state to receive virtual (setup
|
---|
| 2065 | * for injection by VMRUN instruction) interrupts.
|
---|
[67258] | 2066 | *
|
---|
| 2067 | * @returns VBox status code.
|
---|
| 2068 | * @retval true if it's ready, false otherwise.
|
---|
| 2069 | *
|
---|
[70781] | 2070 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
| 2071 | * @param pCtx The guest-CPU context.
|
---|
[67258] | 2072 | */
|
---|
[78866] | 2073 | VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
|
---|
[67258] | 2074 | {
|
---|
[77149] | 2075 | RT_NOREF(pVCpu);
|
---|
[67258] | 2076 | Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
|
---|
| 2077 |
|
---|
[91287] | 2078 | PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.Vmcb.ctrl;
|
---|
[72065] | 2079 | PCSVMINTCTRL pVmcbIntCtrl = &pVmcbCtrl->IntCtrl;
|
---|
[75759] | 2080 | Assert(!pVmcbIntCtrl->n.u1VGifEnable); /* We don't support passing virtual-GIF feature to the guest yet. */
|
---|
[72065] | 2081 | if ( !pVmcbIntCtrl->n.u1IgnoreTPR
|
---|
| 2082 | && pVmcbIntCtrl->n.u4VIntrPrio <= pVmcbIntCtrl->n.u8VTPR)
|
---|
| 2083 | return false;
|
---|
[67258] | 2084 |
|
---|
[77148] | 2085 | return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
|
---|
[67258] | 2086 | }
|
---|
| 2087 |
|
---|
| 2088 |
|
---|
| 2089 | /**
|
---|
[75830] | 2090 | * Gets the pending SVM nested-guest interruptvector.
|
---|
[67258] | 2091 | *
|
---|
| 2092 | * @returns The nested-guest interrupt to inject.
|
---|
| 2093 | * @param pCtx The guest-CPU context.
|
---|
| 2094 | */
|
---|
[75830] | 2095 | VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx)
|
---|
[67258] | 2096 | {
|
---|
[91287] | 2097 | return pCtx->hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u8VIntrVector;
|
---|
[67258] | 2098 | }
|
---|
| 2099 |
|
---|
[68226] | 2100 |
|
---|
| 2101 | /**
|
---|
| 2102 | * Restores the host-state from the host-state save area as part of a \#VMEXIT.
|
---|
| 2103 | *
|
---|
[69408] | 2104 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[68226] | 2105 | * @param pCtx The guest-CPU context.
|
---|
| 2106 | */
|
---|
[80253] | 2107 | VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx)
|
---|
[68226] | 2108 | {
|
---|
[68438] | 2109 | /*
|
---|
[68226] | 2110 | * Reload the guest's "host state".
|
---|
| 2111 | */
|
---|
| 2112 | PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
|
---|
| 2113 | pCtx->es = pHostState->es;
|
---|
| 2114 | pCtx->cs = pHostState->cs;
|
---|
| 2115 | pCtx->ss = pHostState->ss;
|
---|
| 2116 | pCtx->ds = pHostState->ds;
|
---|
| 2117 | pCtx->gdtr = pHostState->gdtr;
|
---|
| 2118 | pCtx->idtr = pHostState->idtr;
|
---|
[74101] | 2119 | CPUMSetGuestEferMsrNoChecks(pVCpu, pCtx->msrEFER, pHostState->uEferMsr);
|
---|
[69408] | 2120 | CPUMSetGuestCR0(pVCpu, pHostState->uCr0 | X86_CR0_PE);
|
---|
[68226] | 2121 | pCtx->cr3 = pHostState->uCr3;
|
---|
[69408] | 2122 | CPUMSetGuestCR4(pVCpu, pHostState->uCr4);
|
---|
[97220] | 2123 | pCtx->rflags.u = pHostState->rflags.u;
|
---|
[68226] | 2124 | pCtx->rflags.Bits.u1VM = 0;
|
---|
| 2125 | pCtx->rip = pHostState->uRip;
|
---|
| 2126 | pCtx->rsp = pHostState->uRsp;
|
---|
| 2127 | pCtx->rax = pHostState->uRax;
|
---|
| 2128 | pCtx->dr[7] &= ~(X86_DR7_ENABLED_MASK | X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
|
---|
| 2129 | pCtx->dr[7] |= X86_DR7_RA1_MASK;
|
---|
[69032] | 2130 | Assert(pCtx->ss.Attr.n.u2Dpl == 0);
|
---|
[68226] | 2131 |
|
---|
| 2132 | /** @todo if RIP is not canonical or outside the CS segment limit, we need to
|
---|
| 2133 | * raise \#GP(0) in the guest. */
|
---|
| 2134 |
|
---|
| 2135 | /** @todo check the loaded host-state for consistency. Figure out what
|
---|
| 2136 | * exactly this involves? */
|
---|
| 2137 | }
|
---|
| 2138 |
|
---|
| 2139 |
|
---|
| 2140 | /**
|
---|
| 2141 | * Saves the host-state to the host-state save area as part of a VMRUN.
|
---|
| 2142 | *
|
---|
| 2143 | * @param pCtx The guest-CPU context.
|
---|
| 2144 | * @param cbInstr The length of the VMRUN instruction in bytes.
|
---|
| 2145 | */
|
---|
| 2146 | VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr)
|
---|
| 2147 | {
|
---|
| 2148 | PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
|
---|
| 2149 | pHostState->es = pCtx->es;
|
---|
| 2150 | pHostState->cs = pCtx->cs;
|
---|
| 2151 | pHostState->ss = pCtx->ss;
|
---|
| 2152 | pHostState->ds = pCtx->ds;
|
---|
| 2153 | pHostState->gdtr = pCtx->gdtr;
|
---|
| 2154 | pHostState->idtr = pCtx->idtr;
|
---|
| 2155 | pHostState->uEferMsr = pCtx->msrEFER;
|
---|
| 2156 | pHostState->uCr0 = pCtx->cr0;
|
---|
| 2157 | pHostState->uCr3 = pCtx->cr3;
|
---|
| 2158 | pHostState->uCr4 = pCtx->cr4;
|
---|
[97220] | 2159 | pHostState->rflags.u = pCtx->rflags.u;
|
---|
[68226] | 2160 | pHostState->uRip = pCtx->rip + cbInstr;
|
---|
| 2161 | pHostState->uRsp = pCtx->rsp;
|
---|
| 2162 | pHostState->uRax = pCtx->rax;
|
---|
| 2163 | }
|
---|
| 2164 |
|
---|
[70056] | 2165 |
|
---|
| 2166 | /**
|
---|
[78220] | 2167 | * Applies the TSC offset of a nested-guest if any and returns the TSC value for the
|
---|
| 2168 | * nested-guest.
|
---|
[70056] | 2169 | *
|
---|
| 2170 | * @returns The TSC offset after applying any nested-guest TSC offset.
|
---|
| 2171 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[80064] | 2172 | * @param uTscValue The guest TSC.
|
---|
[70782] | 2173 | *
|
---|
[78220] | 2174 | * @sa CPUMRemoveNestedGuestTscOffset.
|
---|
[70056] | 2175 | */
|
---|
[80064] | 2176 | VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
|
---|
[70056] | 2177 | {
|
---|
[70782] | 2178 | PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
|
---|
[75109] | 2179 | if (CPUMIsGuestInVmxNonRootMode(pCtx))
|
---|
| 2180 | {
|
---|
[81665] | 2181 | if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
|
---|
[91297] | 2182 | return uTscValue + pCtx->hwvirt.vmx.Vmcs.u64TscOffset.u;
|
---|
[80064] | 2183 | return uTscValue;
|
---|
[75109] | 2184 | }
|
---|
| 2185 |
|
---|
[70056] | 2186 | if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
|
---|
| 2187 | {
|
---|
[80064] | 2188 | uint64_t offTsc;
|
---|
| 2189 | if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
|
---|
[91287] | 2190 | offTsc = pCtx->hwvirt.svm.Vmcb.ctrl.u64TSCOffset;
|
---|
[80064] | 2191 | return uTscValue + offTsc;
|
---|
[70056] | 2192 | }
|
---|
[80064] | 2193 | return uTscValue;
|
---|
[70056] | 2194 | }
|
---|
| 2195 |
|
---|
[72488] | 2196 |
|
---|
| 2197 | /**
|
---|
[78220] | 2198 | * Removes the TSC offset of a nested-guest if any and returns the TSC value for the
|
---|
| 2199 | * guest.
|
---|
| 2200 | *
|
---|
| 2201 | * @returns The TSC offset after removing any nested-guest TSC offset.
|
---|
| 2202 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[80064] | 2203 | * @param uTscValue The nested-guest TSC.
|
---|
[78220] | 2204 | *
|
---|
| 2205 | * @sa CPUMApplyNestedGuestTscOffset.
|
---|
| 2206 | */
|
---|
[80064] | 2207 | VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue)
|
---|
[78220] | 2208 | {
|
---|
| 2209 | PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
|
---|
| 2210 | if (CPUMIsGuestInVmxNonRootMode(pCtx))
|
---|
| 2211 | {
|
---|
[81665] | 2212 | if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_TSC_OFFSETTING))
|
---|
[91297] | 2213 | return uTscValue - pCtx->hwvirt.vmx.Vmcs.u64TscOffset.u;
|
---|
[80064] | 2214 | return uTscValue;
|
---|
[78220] | 2215 | }
|
---|
| 2216 |
|
---|
| 2217 | if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
|
---|
| 2218 | {
|
---|
[80064] | 2219 | uint64_t offTsc;
|
---|
| 2220 | if (!HMGetGuestSvmTscOffset(pVCpu, &offTsc))
|
---|
[91287] | 2221 | offTsc = pCtx->hwvirt.svm.Vmcb.ctrl.u64TSCOffset;
|
---|
[80064] | 2222 | return uTscValue - offTsc;
|
---|
[78220] | 2223 | }
|
---|
[80064] | 2224 | return uTscValue;
|
---|
[78220] | 2225 | }
|
---|
| 2226 |
|
---|
| 2227 |
|
---|
| 2228 | /**
|
---|
[72488] | 2229 | * Used to dynamically imports state residing in NEM or HM.
|
---|
| 2230 | *
|
---|
| 2231 | * This is a worker for the CPUM_IMPORT_EXTRN_RET() macro and various IEM ones.
|
---|
| 2232 | *
|
---|
| 2233 | * @returns VBox status code.
|
---|
| 2234 | * @param pVCpu The cross context virtual CPU structure of the calling thread.
|
---|
| 2235 | * @param fExtrnImport The fields to import.
|
---|
| 2236 | * @thread EMT(pVCpu)
|
---|
| 2237 | */
|
---|
[80253] | 2238 | VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPUCC pVCpu, uint64_t fExtrnImport)
|
---|
[72488] | 2239 | {
|
---|
| 2240 | VMCPU_ASSERT_EMT(pVCpu);
|
---|
| 2241 | if (pVCpu->cpum.s.Guest.fExtrn & fExtrnImport)
|
---|
| 2242 | {
|
---|
| 2243 | switch (pVCpu->cpum.s.Guest.fExtrn & CPUMCTX_EXTRN_KEEPER_MASK)
|
---|
| 2244 | {
|
---|
| 2245 | case CPUMCTX_EXTRN_KEEPER_NEM:
|
---|
| 2246 | {
|
---|
[72917] | 2247 | int rc = NEMImportStateOnDemand(pVCpu, fExtrnImport);
|
---|
[72488] | 2248 | Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
|
---|
| 2249 | return rc;
|
---|
| 2250 | }
|
---|
| 2251 |
|
---|
[72643] | 2252 | case CPUMCTX_EXTRN_KEEPER_HM:
|
---|
| 2253 | {
|
---|
| 2254 | #ifdef IN_RING0
|
---|
[72744] | 2255 | int rc = HMR0ImportStateOnDemand(pVCpu, fExtrnImport);
|
---|
[72643] | 2256 | Assert(rc == VINF_SUCCESS || RT_FAILURE_NP(rc));
|
---|
| 2257 | return rc;
|
---|
| 2258 | #else
|
---|
[72879] | 2259 | AssertLogRelMsgFailed(("TODO Fetch HM state: %#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport));
|
---|
[72643] | 2260 | return VINF_SUCCESS;
|
---|
| 2261 | #endif
|
---|
| 2262 | }
|
---|
[72488] | 2263 | default:
|
---|
| 2264 | AssertLogRelMsgFailedReturn(("%#RX64 vs %#RX64\n", pVCpu->cpum.s.Guest.fExtrn, fExtrnImport), VERR_CPUM_IPE_2);
|
---|
| 2265 | }
|
---|
| 2266 | }
|
---|
| 2267 | return VINF_SUCCESS;
|
---|
| 2268 | }
|
---|
| 2269 |
|
---|
[76548] | 2270 |
|
---|
| 2271 | /**
|
---|
| 2272 | * Gets valid CR4 bits for the guest.
|
---|
| 2273 | *
|
---|
| 2274 | * @returns Valid CR4 bits.
|
---|
| 2275 | * @param pVM The cross context VM structure.
|
---|
| 2276 | */
|
---|
| 2277 | VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM)
|
---|
| 2278 | {
|
---|
| 2279 | PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
|
---|
| 2280 | uint64_t fMask = X86_CR4_VME | X86_CR4_PVI
|
---|
| 2281 | | X86_CR4_TSD | X86_CR4_DE
|
---|
[91275] | 2282 | | X86_CR4_MCE | X86_CR4_PCE;
|
---|
| 2283 | if (pGuestFeatures->fPae)
|
---|
| 2284 | fMask |= X86_CR4_PAE;
|
---|
| 2285 | if (pGuestFeatures->fPge)
|
---|
| 2286 | fMask |= X86_CR4_PGE;
|
---|
| 2287 | if (pGuestFeatures->fPse)
|
---|
| 2288 | fMask |= X86_CR4_PSE;
|
---|
[76548] | 2289 | if (pGuestFeatures->fFxSaveRstor)
|
---|
| 2290 | fMask |= X86_CR4_OSFXSR;
|
---|
| 2291 | if (pGuestFeatures->fVmx)
|
---|
| 2292 | fMask |= X86_CR4_VMXE;
|
---|
| 2293 | if (pGuestFeatures->fXSaveRstor)
|
---|
| 2294 | fMask |= X86_CR4_OSXSAVE;
|
---|
| 2295 | if (pGuestFeatures->fPcid)
|
---|
| 2296 | fMask |= X86_CR4_PCIDE;
|
---|
| 2297 | if (pGuestFeatures->fFsGsBase)
|
---|
| 2298 | fMask |= X86_CR4_FSGSBASE;
|
---|
[91275] | 2299 | if (pGuestFeatures->fSse)
|
---|
| 2300 | fMask |= X86_CR4_OSXMMEEXCPT;
|
---|
[76548] | 2301 | return fMask;
|
---|
| 2302 | }
|
---|
| 2303 |
|
---|
[78371] | 2304 |
|
---|
| 2305 | /**
|
---|
[91580] | 2306 | * Sets the PAE PDPEs for the guest.
|
---|
[91271] | 2307 | *
|
---|
| 2308 | * @param pVCpu The cross context virtual CPU structure of the calling thread.
|
---|
[91580] | 2309 | * @param paPaePdpes The PAE PDPEs to set.
|
---|
[91271] | 2310 | */
|
---|
| 2311 | VMM_INT_DECL(void) CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes)
|
---|
| 2312 | {
|
---|
| 2313 | Assert(paPaePdpes);
|
---|
| 2314 | for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.s.Guest.aPaePdpes); i++)
|
---|
| 2315 | pVCpu->cpum.s.Guest.aPaePdpes[i].u = paPaePdpes[i].u;
|
---|
| 2316 | pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
|
---|
| 2317 | }
|
---|
| 2318 |
|
---|
| 2319 |
|
---|
| 2320 | /**
|
---|
[91580] | 2321 | * Gets the PAE PDPTEs for the guest.
|
---|
| 2322 | *
|
---|
| 2323 | * @param pVCpu The cross context virtual CPU structure of the calling thread.
|
---|
| 2324 | * @param paPaePdpes Where to store the PAE PDPEs.
|
---|
| 2325 | */
|
---|
| 2326 | VMM_INT_DECL(void) CPUMGetGuestPaePdpes(PVMCPU pVCpu, PX86PDPE paPaePdpes)
|
---|
| 2327 | {
|
---|
| 2328 | Assert(paPaePdpes);
|
---|
| 2329 | CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR3);
|
---|
| 2330 | for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.s.Guest.aPaePdpes); i++)
|
---|
| 2331 | paPaePdpes[i].u = pVCpu->cpum.s.Guest.aPaePdpes[i].u;
|
---|
| 2332 | }
|
---|
| 2333 |
|
---|
| 2334 |
|
---|
| 2335 | /**
|
---|
[81786] | 2336 | * Starts a VMX-preemption timer to expire as specified by the nested hypervisor.
|
---|
| 2337 | *
|
---|
| 2338 | * @returns VBox status code.
|
---|
| 2339 | * @param pVCpu The cross context virtual CPU structure of the calling thread.
|
---|
| 2340 | * @param uTimer The VMCS preemption timer value.
|
---|
| 2341 | * @param cShift The VMX-preemption timer shift (usually based on guest
|
---|
| 2342 | * VMX MSR rate).
|
---|
| 2343 | * @param pu64EntryTick Where to store the current tick when the timer is
|
---|
| 2344 | * programmed.
|
---|
| 2345 | * @thread EMT(pVCpu)
|
---|
| 2346 | */
|
---|
| 2347 | VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick)
|
---|
| 2348 | {
|
---|
| 2349 | Assert(uTimer);
|
---|
| 2350 | Assert(cShift <= 31);
|
---|
| 2351 | Assert(pu64EntryTick);
|
---|
| 2352 | VMCPU_ASSERT_EMT(pVCpu);
|
---|
| 2353 | uint64_t const cTicksToNext = uTimer << cShift;
|
---|
[87766] | 2354 | return TMTimerSetRelative(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.s.hNestedVmxPreemptTimer, cTicksToNext, pu64EntryTick);
|
---|
[81786] | 2355 | }
|
---|
| 2356 |
|
---|
| 2357 |
|
---|
| 2358 | /**
|
---|
| 2359 | * Stops the VMX-preemption timer from firing.
|
---|
| 2360 | *
|
---|
| 2361 | * @returns VBox status code.
|
---|
| 2362 | * @param pVCpu The cross context virtual CPU structure of the calling thread.
|
---|
| 2363 | * @thread EMT.
|
---|
| 2364 | *
|
---|
| 2365 | * @remarks This can be called during VM reset, so we cannot assume it will be on
|
---|
| 2366 | * the EMT corresponding to @c pVCpu.
|
---|
| 2367 | */
|
---|
| 2368 | VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu)
|
---|
| 2369 | {
|
---|
| 2370 | /*
|
---|
| 2371 | * CPUM gets initialized before TM, so we defer creation of timers till CPUMR3InitCompleted().
|
---|
[87766] | 2372 | * However, we still get called during CPUMR3Init() and hence we need to check if we have
|
---|
[81786] | 2373 | * a valid timer object before trying to stop it.
|
---|
| 2374 | */
|
---|
[87766] | 2375 | int rc;
|
---|
| 2376 | TMTIMERHANDLE hTimer = pVCpu->cpum.s.hNestedVmxPreemptTimer;
|
---|
| 2377 | if (hTimer != NIL_TMTIMERHANDLE)
|
---|
[81786] | 2378 | {
|
---|
[87766] | 2379 | PVMCC pVM = pVCpu->CTX_SUFF(pVM);
|
---|
| 2380 | rc = TMTimerLock(pVM, hTimer, VERR_IGNORED);
|
---|
| 2381 | if (rc == VINF_SUCCESS)
|
---|
| 2382 | {
|
---|
| 2383 | if (TMTimerIsActive(pVM, hTimer))
|
---|
| 2384 | TMTimerStop(pVM, hTimer);
|
---|
| 2385 | TMTimerUnlock(pVM, hTimer);
|
---|
| 2386 | }
|
---|
[81786] | 2387 | }
|
---|
[87766] | 2388 | else
|
---|
| 2389 | rc = VERR_NOT_FOUND;
|
---|
[81786] | 2390 | return rc;
|
---|
| 2391 | }
|
---|
| 2392 |
|
---|
| 2393 |
|
---|
| 2394 | /**
|
---|
[78371] | 2395 | * Gets the read and write permission bits for an MSR in an MSR bitmap.
|
---|
| 2396 | *
|
---|
| 2397 | * @returns VMXMSRPM_XXX - the MSR permission.
|
---|
| 2398 | * @param pvMsrBitmap Pointer to the MSR bitmap.
|
---|
| 2399 | * @param idMsr The MSR to get permissions for.
|
---|
| 2400 | *
|
---|
| 2401 | * @sa hmR0VmxSetMsrPermission.
|
---|
| 2402 | */
|
---|
| 2403 | VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr)
|
---|
| 2404 | {
|
---|
| 2405 | AssertPtrReturn(pvMsrBitmap, VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR);
|
---|
| 2406 |
|
---|
| 2407 | uint8_t const * const pbMsrBitmap = (uint8_t const * const)pvMsrBitmap;
|
---|
| 2408 |
|
---|
| 2409 | /*
|
---|
| 2410 | * MSR Layout:
|
---|
| 2411 | * Byte index MSR range Interpreted as
|
---|
| 2412 | * 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
|
---|
| 2413 | * 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
|
---|
| 2414 | * 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
|
---|
| 2415 | * 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
|
---|
| 2416 | *
|
---|
| 2417 | * A bit corresponding to an MSR within the above range causes a VM-exit
|
---|
| 2418 | * if the bit is 1 on executions of RDMSR/WRMSR. If an MSR falls out of
|
---|
| 2419 | * the MSR range, it always cause a VM-exit.
|
---|
| 2420 | *
|
---|
| 2421 | * See Intel spec. 24.6.9 "MSR-Bitmap Address".
|
---|
| 2422 | */
|
---|
| 2423 | uint32_t const offBitmapRead = 0;
|
---|
| 2424 | uint32_t const offBitmapWrite = 0x800;
|
---|
| 2425 | uint32_t offMsr;
|
---|
| 2426 | uint32_t iBit;
|
---|
| 2427 | if (idMsr <= UINT32_C(0x00001fff))
|
---|
| 2428 | {
|
---|
| 2429 | offMsr = 0;
|
---|
| 2430 | iBit = idMsr;
|
---|
| 2431 | }
|
---|
| 2432 | else if (idMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
|
---|
| 2433 | {
|
---|
| 2434 | offMsr = 0x400;
|
---|
| 2435 | iBit = idMsr - UINT32_C(0xc0000000);
|
---|
| 2436 | }
|
---|
| 2437 | else
|
---|
| 2438 | {
|
---|
| 2439 | LogFunc(("Warning! Out of range MSR %#RX32\n", idMsr));
|
---|
| 2440 | return VMXMSRPM_EXIT_RD | VMXMSRPM_EXIT_WR;
|
---|
| 2441 | }
|
---|
| 2442 |
|
---|
| 2443 | /*
|
---|
| 2444 | * Get the MSR read permissions.
|
---|
| 2445 | */
|
---|
| 2446 | uint32_t fRet;
|
---|
| 2447 | uint32_t const offMsrRead = offBitmapRead + offMsr;
|
---|
| 2448 | Assert(offMsrRead + (iBit >> 3) < offBitmapWrite);
|
---|
[96994] | 2449 | if (ASMBitTest(pbMsrBitmap, (offMsrRead << 3) + iBit))
|
---|
[78371] | 2450 | fRet = VMXMSRPM_EXIT_RD;
|
---|
| 2451 | else
|
---|
| 2452 | fRet = VMXMSRPM_ALLOW_RD;
|
---|
| 2453 |
|
---|
| 2454 | /*
|
---|
| 2455 | * Get the MSR write permissions.
|
---|
| 2456 | */
|
---|
| 2457 | uint32_t const offMsrWrite = offBitmapWrite + offMsr;
|
---|
| 2458 | Assert(offMsrWrite + (iBit >> 3) < X86_PAGE_4K_SIZE);
|
---|
[96994] | 2459 | if (ASMBitTest(pbMsrBitmap, (offMsrWrite << 3) + iBit))
|
---|
[78371] | 2460 | fRet |= VMXMSRPM_EXIT_WR;
|
---|
| 2461 | else
|
---|
| 2462 | fRet |= VMXMSRPM_ALLOW_WR;
|
---|
| 2463 |
|
---|
| 2464 | Assert(VMXMSRPM_IS_FLAG_VALID(fRet));
|
---|
| 2465 | return fRet;
|
---|
| 2466 | }
|
---|
| 2467 |
|
---|
| 2468 |
|
---|
| 2469 | /**
|
---|
[80806] | 2470 | * Checks the permission bits for the specified I/O port from the given I/O bitmap
|
---|
| 2471 | * to see if causes a VM-exit.
|
---|
[78371] | 2472 | *
|
---|
| 2473 | * @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
|
---|
[91305] | 2474 | * @param pbIoBitmap Pointer to I/O bitmap.
|
---|
[80806] | 2475 | * @param uPort The I/O port being accessed.
|
---|
| 2476 | * @param cbAccess e size of the I/O access in bytes (1, 2 or 4 bytes).
|
---|
[78371] | 2477 | */
|
---|
[91305] | 2478 | static bool cpumGetVmxIoBitmapPermission(uint8_t const *pbIoBitmap, uint16_t uPort, uint8_t cbAccess)
|
---|
[78371] | 2479 | {
|
---|
| 2480 | Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
|
---|
| 2481 |
|
---|
| 2482 | /*
|
---|
[80803] | 2483 | * If the I/O port access wraps around the 16-bit port I/O space, we must cause a
|
---|
| 2484 | * VM-exit.
|
---|
[78371] | 2485 | *
|
---|
[80804] | 2486 | * Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc are valid and do not
|
---|
| 2487 | * constitute a wrap around. However, reading 2 bytes at port 0xffff or 4 bytes
|
---|
| 2488 | * from port 0xffff/0xfffe/0xfffd constitute a wrap around. In other words, any
|
---|
| 2489 | * access to -both- ports 0xffff and port 0 is a wrap around.
|
---|
| 2490 | *
|
---|
[78371] | 2491 | * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
|
---|
| 2492 | */
|
---|
| 2493 | uint32_t const uPortLast = uPort + cbAccess;
|
---|
| 2494 | if (uPortLast > 0x10000)
|
---|
| 2495 | return true;
|
---|
| 2496 |
|
---|
[80803] | 2497 | /*
|
---|
| 2498 | * If any bit corresponding to the I/O access is set, we must cause a VM-exit.
|
---|
| 2499 | */
|
---|
[80814] | 2500 | uint16_t const offPerm = uPort >> 3; /* Byte offset of the port. */
|
---|
| 2501 | uint16_t const idxPermBit = uPort - (offPerm << 3); /* Bit offset within byte. */
|
---|
| 2502 | Assert(idxPermBit < 8);
|
---|
| 2503 | static const uint8_t s_afMask[] = { 0x0, 0x1, 0x3, 0x7, 0xf }; /* Bit-mask for all access sizes. */
|
---|
| 2504 | uint16_t const fMask = s_afMask[cbAccess] << idxPermBit; /* Bit-mask of the access. */
|
---|
[80803] | 2505 |
|
---|
[80814] | 2506 | /* Fetch 8 or 16-bits depending on whether the access spans 8-bit boundary. */
|
---|
| 2507 | RTUINT16U uPerm;
|
---|
[91305] | 2508 | uPerm.s.Lo = pbIoBitmap[offPerm];
|
---|
[80814] | 2509 | if (idxPermBit + cbAccess > 8)
|
---|
[91305] | 2510 | uPerm.s.Hi = pbIoBitmap[offPerm + 1];
|
---|
[80814] | 2511 | else
|
---|
| 2512 | uPerm.s.Hi = 0;
|
---|
[80803] | 2513 |
|
---|
[80814] | 2514 | /* If any bit for the access is 1, we must cause a VM-exit. */
|
---|
| 2515 | if (uPerm.u & fMask)
|
---|
| 2516 | return true;
|
---|
[80803] | 2517 |
|
---|
| 2518 | return false;
|
---|
[78371] | 2519 | }
|
---|
| 2520 |
|
---|
| 2521 |
|
---|
| 2522 | /**
|
---|
[79194] | 2523 | * Returns whether the given VMCS field is valid and supported for the guest.
|
---|
| 2524 | *
|
---|
| 2525 | * @param pVM The cross context VM structure.
|
---|
| 2526 | * @param u64VmcsField The VMCS field.
|
---|
| 2527 | *
|
---|
| 2528 | * @remarks This takes into account the CPU features exposed to the guest.
|
---|
| 2529 | */
|
---|
[80253] | 2530 | VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField)
|
---|
[79194] | 2531 | {
|
---|
| 2532 | uint32_t const uFieldEncHi = RT_HI_U32(u64VmcsField);
|
---|
| 2533 | uint32_t const uFieldEncLo = RT_LO_U32(u64VmcsField);
|
---|
| 2534 | if (!uFieldEncHi)
|
---|
| 2535 | { /* likely */ }
|
---|
| 2536 | else
|
---|
| 2537 | return false;
|
---|
| 2538 |
|
---|
| 2539 | PCCPUMFEATURES pFeat = &pVM->cpum.s.GuestFeatures;
|
---|
| 2540 | switch (uFieldEncLo)
|
---|
| 2541 | {
|
---|
| 2542 | /*
|
---|
| 2543 | * 16-bit fields.
|
---|
| 2544 | */
|
---|
| 2545 | /* Control fields. */
|
---|
| 2546 | case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
|
---|
| 2547 | case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
|
---|
| 2548 | case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
|
---|
| 2549 |
|
---|
| 2550 | /* Guest-state fields. */
|
---|
| 2551 | case VMX_VMCS16_GUEST_ES_SEL:
|
---|
| 2552 | case VMX_VMCS16_GUEST_CS_SEL:
|
---|
| 2553 | case VMX_VMCS16_GUEST_SS_SEL:
|
---|
| 2554 | case VMX_VMCS16_GUEST_DS_SEL:
|
---|
| 2555 | case VMX_VMCS16_GUEST_FS_SEL:
|
---|
| 2556 | case VMX_VMCS16_GUEST_GS_SEL:
|
---|
| 2557 | case VMX_VMCS16_GUEST_LDTR_SEL:
|
---|
| 2558 | case VMX_VMCS16_GUEST_TR_SEL: return true;
|
---|
| 2559 | case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
|
---|
| 2560 | case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
|
---|
| 2561 |
|
---|
| 2562 | /* Host-state fields. */
|
---|
| 2563 | case VMX_VMCS16_HOST_ES_SEL:
|
---|
| 2564 | case VMX_VMCS16_HOST_CS_SEL:
|
---|
| 2565 | case VMX_VMCS16_HOST_SS_SEL:
|
---|
| 2566 | case VMX_VMCS16_HOST_DS_SEL:
|
---|
| 2567 | case VMX_VMCS16_HOST_FS_SEL:
|
---|
| 2568 | case VMX_VMCS16_HOST_GS_SEL:
|
---|
| 2569 | case VMX_VMCS16_HOST_TR_SEL: return true;
|
---|
| 2570 |
|
---|
| 2571 | /*
|
---|
| 2572 | * 64-bit fields.
|
---|
| 2573 | */
|
---|
| 2574 | /* Control fields. */
|
---|
| 2575 | case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
|
---|
| 2576 | case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
|
---|
| 2577 | case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
|
---|
| 2578 | case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
|
---|
| 2579 | case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
|
---|
| 2580 | case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
|
---|
| 2581 | case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
|
---|
| 2582 | case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
|
---|
| 2583 | case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
|
---|
| 2584 | case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
|
---|
| 2585 | case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
|
---|
| 2586 | case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
|
---|
| 2587 | case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
|
---|
| 2588 | case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
|
---|
| 2589 | case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
|
---|
| 2590 | case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
|
---|
| 2591 | case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
|
---|
| 2592 | case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
|
---|
| 2593 | case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
|
---|
| 2594 | case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
|
---|
| 2595 | case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
|
---|
| 2596 | case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
|
---|
| 2597 | case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
|
---|
| 2598 | case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
|
---|
| 2599 | case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
|
---|
| 2600 | case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
|
---|
| 2601 | case VMX_VMCS64_CTRL_EPTP_FULL:
|
---|
| 2602 | case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
|
---|
| 2603 | case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
|
---|
| 2604 | case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
|
---|
| 2605 | case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
|
---|
| 2606 | case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
|
---|
| 2607 | case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
|
---|
| 2608 | case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
|
---|
| 2609 | case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
|
---|
| 2610 | case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
|
---|
| 2611 | case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
|
---|
| 2612 | case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
|
---|
| 2613 | {
|
---|
[80253] | 2614 | PCVMCPU pVCpu = pVM->CTX_SUFF(apCpus)[0];
|
---|
[79194] | 2615 | uint64_t const uVmFuncMsr = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc;
|
---|
| 2616 | return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
|
---|
| 2617 | }
|
---|
| 2618 | case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
|
---|
| 2619 | case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
|
---|
| 2620 | case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
|
---|
| 2621 | case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
|
---|
[90932] | 2622 | case VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_FULL:
|
---|
| 2623 | case VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
|
---|
[79194] | 2624 | case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
|
---|
| 2625 | case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
|
---|
| 2626 | case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
|
---|
| 2627 | case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
|
---|
[91037] | 2628 | case VMX_VMCS64_CTRL_PROC_EXEC3_FULL:
|
---|
| 2629 | case VMX_VMCS64_CTRL_PROC_EXEC3_HIGH: return pFeat->fVmxTertiaryExecCtls;
|
---|
[79194] | 2630 |
|
---|
| 2631 | /* Read-only data fields. */
|
---|
| 2632 | case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
|
---|
| 2633 | case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
|
---|
| 2634 |
|
---|
| 2635 | /* Guest-state fields. */
|
---|
| 2636 | case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
|
---|
| 2637 | case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
|
---|
| 2638 | case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
|
---|
| 2639 | case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
|
---|
| 2640 | case VMX_VMCS64_GUEST_PAT_FULL:
|
---|
| 2641 | case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
|
---|
| 2642 | case VMX_VMCS64_GUEST_EFER_FULL:
|
---|
| 2643 | case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
|
---|
| 2644 | case VMX_VMCS64_GUEST_PDPTE0_FULL:
|
---|
| 2645 | case VMX_VMCS64_GUEST_PDPTE0_HIGH:
|
---|
| 2646 | case VMX_VMCS64_GUEST_PDPTE1_FULL:
|
---|
| 2647 | case VMX_VMCS64_GUEST_PDPTE1_HIGH:
|
---|
| 2648 | case VMX_VMCS64_GUEST_PDPTE2_FULL:
|
---|
| 2649 | case VMX_VMCS64_GUEST_PDPTE2_HIGH:
|
---|
| 2650 | case VMX_VMCS64_GUEST_PDPTE3_FULL:
|
---|
| 2651 | case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
|
---|
| 2652 |
|
---|
| 2653 | /* Host-state fields. */
|
---|
| 2654 | case VMX_VMCS64_HOST_PAT_FULL:
|
---|
| 2655 | case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
|
---|
| 2656 | case VMX_VMCS64_HOST_EFER_FULL:
|
---|
| 2657 | case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
|
---|
| 2658 |
|
---|
| 2659 | /*
|
---|
| 2660 | * 32-bit fields.
|
---|
| 2661 | */
|
---|
| 2662 | /* Control fields. */
|
---|
| 2663 | case VMX_VMCS32_CTRL_PIN_EXEC:
|
---|
| 2664 | case VMX_VMCS32_CTRL_PROC_EXEC:
|
---|
| 2665 | case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
|
---|
| 2666 | case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
|
---|
| 2667 | case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
|
---|
| 2668 | case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
|
---|
| 2669 | case VMX_VMCS32_CTRL_EXIT:
|
---|
| 2670 | case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
|
---|
| 2671 | case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
|
---|
| 2672 | case VMX_VMCS32_CTRL_ENTRY:
|
---|
| 2673 | case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
|
---|
| 2674 | case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
|
---|
| 2675 | case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
|
---|
| 2676 | case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
|
---|
| 2677 | case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
|
---|
| 2678 | case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
|
---|
| 2679 | case VMX_VMCS32_CTRL_PLE_GAP:
|
---|
| 2680 | case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
|
---|
| 2681 |
|
---|
| 2682 | /* Read-only data fields. */
|
---|
| 2683 | case VMX_VMCS32_RO_VM_INSTR_ERROR:
|
---|
| 2684 | case VMX_VMCS32_RO_EXIT_REASON:
|
---|
| 2685 | case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
|
---|
| 2686 | case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
|
---|
| 2687 | case VMX_VMCS32_RO_IDT_VECTORING_INFO:
|
---|
| 2688 | case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
|
---|
| 2689 | case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
|
---|
| 2690 | case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
|
---|
| 2691 |
|
---|
| 2692 | /* Guest-state fields. */
|
---|
| 2693 | case VMX_VMCS32_GUEST_ES_LIMIT:
|
---|
| 2694 | case VMX_VMCS32_GUEST_CS_LIMIT:
|
---|
| 2695 | case VMX_VMCS32_GUEST_SS_LIMIT:
|
---|
| 2696 | case VMX_VMCS32_GUEST_DS_LIMIT:
|
---|
| 2697 | case VMX_VMCS32_GUEST_FS_LIMIT:
|
---|
| 2698 | case VMX_VMCS32_GUEST_GS_LIMIT:
|
---|
| 2699 | case VMX_VMCS32_GUEST_LDTR_LIMIT:
|
---|
| 2700 | case VMX_VMCS32_GUEST_TR_LIMIT:
|
---|
| 2701 | case VMX_VMCS32_GUEST_GDTR_LIMIT:
|
---|
| 2702 | case VMX_VMCS32_GUEST_IDTR_LIMIT:
|
---|
| 2703 | case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
|
---|
| 2704 | case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
|
---|
| 2705 | case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
|
---|
| 2706 | case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
|
---|
| 2707 | case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
|
---|
| 2708 | case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
|
---|
| 2709 | case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
|
---|
| 2710 | case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
|
---|
| 2711 | case VMX_VMCS32_GUEST_INT_STATE:
|
---|
| 2712 | case VMX_VMCS32_GUEST_ACTIVITY_STATE:
|
---|
| 2713 | case VMX_VMCS32_GUEST_SMBASE:
|
---|
| 2714 | case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
|
---|
| 2715 | case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
|
---|
| 2716 |
|
---|
| 2717 | /* Host-state fields. */
|
---|
| 2718 | case VMX_VMCS32_HOST_SYSENTER_CS: return true;
|
---|
| 2719 |
|
---|
| 2720 | /*
|
---|
| 2721 | * Natural-width fields.
|
---|
| 2722 | */
|
---|
| 2723 | /* Control fields. */
|
---|
| 2724 | case VMX_VMCS_CTRL_CR0_MASK:
|
---|
| 2725 | case VMX_VMCS_CTRL_CR4_MASK:
|
---|
| 2726 | case VMX_VMCS_CTRL_CR0_READ_SHADOW:
|
---|
| 2727 | case VMX_VMCS_CTRL_CR4_READ_SHADOW:
|
---|
| 2728 | case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
|
---|
| 2729 | case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
|
---|
| 2730 | case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
|
---|
| 2731 | case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
|
---|
| 2732 |
|
---|
| 2733 | /* Read-only data fields. */
|
---|
| 2734 | case VMX_VMCS_RO_EXIT_QUALIFICATION:
|
---|
| 2735 | case VMX_VMCS_RO_IO_RCX:
|
---|
| 2736 | case VMX_VMCS_RO_IO_RSI:
|
---|
| 2737 | case VMX_VMCS_RO_IO_RDI:
|
---|
| 2738 | case VMX_VMCS_RO_IO_RIP:
|
---|
| 2739 | case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
|
---|
| 2740 |
|
---|
| 2741 | /* Guest-state fields. */
|
---|
| 2742 | case VMX_VMCS_GUEST_CR0:
|
---|
| 2743 | case VMX_VMCS_GUEST_CR3:
|
---|
| 2744 | case VMX_VMCS_GUEST_CR4:
|
---|
| 2745 | case VMX_VMCS_GUEST_ES_BASE:
|
---|
| 2746 | case VMX_VMCS_GUEST_CS_BASE:
|
---|
| 2747 | case VMX_VMCS_GUEST_SS_BASE:
|
---|
| 2748 | case VMX_VMCS_GUEST_DS_BASE:
|
---|
| 2749 | case VMX_VMCS_GUEST_FS_BASE:
|
---|
| 2750 | case VMX_VMCS_GUEST_GS_BASE:
|
---|
| 2751 | case VMX_VMCS_GUEST_LDTR_BASE:
|
---|
| 2752 | case VMX_VMCS_GUEST_TR_BASE:
|
---|
| 2753 | case VMX_VMCS_GUEST_GDTR_BASE:
|
---|
| 2754 | case VMX_VMCS_GUEST_IDTR_BASE:
|
---|
| 2755 | case VMX_VMCS_GUEST_DR7:
|
---|
| 2756 | case VMX_VMCS_GUEST_RSP:
|
---|
| 2757 | case VMX_VMCS_GUEST_RIP:
|
---|
| 2758 | case VMX_VMCS_GUEST_RFLAGS:
|
---|
| 2759 | case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
|
---|
| 2760 | case VMX_VMCS_GUEST_SYSENTER_ESP:
|
---|
| 2761 | case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
|
---|
| 2762 |
|
---|
| 2763 | /* Host-state fields. */
|
---|
| 2764 | case VMX_VMCS_HOST_CR0:
|
---|
| 2765 | case VMX_VMCS_HOST_CR3:
|
---|
| 2766 | case VMX_VMCS_HOST_CR4:
|
---|
| 2767 | case VMX_VMCS_HOST_FS_BASE:
|
---|
| 2768 | case VMX_VMCS_HOST_GS_BASE:
|
---|
| 2769 | case VMX_VMCS_HOST_TR_BASE:
|
---|
| 2770 | case VMX_VMCS_HOST_GDTR_BASE:
|
---|
| 2771 | case VMX_VMCS_HOST_IDTR_BASE:
|
---|
| 2772 | case VMX_VMCS_HOST_SYSENTER_ESP:
|
---|
| 2773 | case VMX_VMCS_HOST_SYSENTER_EIP:
|
---|
| 2774 | case VMX_VMCS_HOST_RSP:
|
---|
| 2775 | case VMX_VMCS_HOST_RIP: return true;
|
---|
| 2776 | }
|
---|
| 2777 |
|
---|
| 2778 | return false;
|
---|
| 2779 | }
|
---|
| 2780 |
|
---|
| 2781 |
|
---|
| 2782 | /**
|
---|
[78454] | 2783 | * Checks whether the given I/O access should cause a nested-guest VM-exit.
|
---|
| 2784 | *
|
---|
[79376] | 2785 | * @returns @c true if it causes a VM-exit, @c false otherwise.
|
---|
[78454] | 2786 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
| 2787 | * @param u16Port The I/O port being accessed.
|
---|
| 2788 | * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
|
---|
| 2789 | */
|
---|
[78863] | 2790 | VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
|
---|
[78454] | 2791 | {
|
---|
| 2792 | PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
|
---|
[81665] | 2793 | if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_UNCOND_IO_EXIT))
|
---|
[78454] | 2794 | return true;
|
---|
| 2795 |
|
---|
[81665] | 2796 | if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_USE_IO_BITMAPS))
|
---|
[91305] | 2797 | return cpumGetVmxIoBitmapPermission(pCtx->hwvirt.vmx.abIoBitmap, u16Port, cbAccess);
|
---|
[78454] | 2798 |
|
---|
| 2799 | return false;
|
---|
| 2800 | }
|
---|
| 2801 |
|
---|
| 2802 |
|
---|
| 2803 | /**
|
---|
[79376] | 2804 | * Checks whether the Mov-to-CR3 instruction causes a nested-guest VM-exit.
|
---|
| 2805 | *
|
---|
| 2806 | * @returns @c true if it causes a VM-exit, @c false otherwise.
|
---|
| 2807 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
| 2808 | * @param uNewCr3 The CR3 value being written.
|
---|
| 2809 | */
|
---|
| 2810 | VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3)
|
---|
| 2811 | {
|
---|
| 2812 | /*
|
---|
| 2813 | * If the CR3-load exiting control is set and the new CR3 value does not
|
---|
| 2814 | * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
|
---|
| 2815 | *
|
---|
| 2816 | * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
|
---|
| 2817 | */
|
---|
[91297] | 2818 | PCCPUMCTX const pCtx = &pVCpu->cpum.s.Guest;
|
---|
[81665] | 2819 | if (CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_CR3_LOAD_EXIT))
|
---|
[79376] | 2820 | {
|
---|
[91297] | 2821 | uint32_t const uCr3TargetCount = pCtx->hwvirt.vmx.Vmcs.u32Cr3TargetCount;
|
---|
[79376] | 2822 | Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
|
---|
| 2823 |
|
---|
[79379] | 2824 | /* If the CR3-target count is 0, cause a VM-exit. */
|
---|
[79376] | 2825 | if (uCr3TargetCount == 0)
|
---|
| 2826 | return true;
|
---|
| 2827 |
|
---|
[79379] | 2828 | /* If the CR3 being written doesn't match any of the target values, cause a VM-exit. */
|
---|
[79376] | 2829 | AssertCompile(VMX_V_CR3_TARGET_COUNT == 4);
|
---|
[91297] | 2830 | if ( uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target0.u
|
---|
| 2831 | && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target1.u
|
---|
| 2832 | && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target2.u
|
---|
| 2833 | && uNewCr3 != pCtx->hwvirt.vmx.Vmcs.u64Cr3Target3.u)
|
---|
[79376] | 2834 | return true;
|
---|
| 2835 | }
|
---|
| 2836 | return false;
|
---|
| 2837 | }
|
---|
| 2838 |
|
---|
| 2839 |
|
---|
| 2840 | /**
|
---|
[78861] | 2841 | * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field causes a
|
---|
| 2842 | * VM-exit or not.
|
---|
| 2843 | *
|
---|
| 2844 | * @returns @c true if the VMREAD/VMWRITE is intercepted, @c false otherwise.
|
---|
| 2845 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 2846 | * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
|
---|
| 2847 | * VMX_EXIT_VMREAD).
|
---|
[79316] | 2848 | * @param u64VmcsField The VMCS field.
|
---|
[78861] | 2849 | */
|
---|
[79316] | 2850 | VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64VmcsField)
|
---|
[78861] | 2851 | {
|
---|
| 2852 | Assert(CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.s.Guest));
|
---|
| 2853 | Assert( uExitReason == VMX_EXIT_VMREAD
|
---|
| 2854 | || uExitReason == VMX_EXIT_VMWRITE);
|
---|
| 2855 |
|
---|
| 2856 | /*
|
---|
| 2857 | * Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted.
|
---|
| 2858 | */
|
---|
[81665] | 2859 | if (!CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VMCS_SHADOWING))
|
---|
[78861] | 2860 | return true;
|
---|
| 2861 |
|
---|
| 2862 | /*
|
---|
| 2863 | * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE
|
---|
| 2864 | * is intercepted. This excludes any reserved bits in the valid parts of the field
|
---|
| 2865 | * encoding (i.e. bit 12).
|
---|
| 2866 | */
|
---|
[79316] | 2867 | if (u64VmcsField & VMX_VMCSFIELD_RSVD_MASK)
|
---|
[78861] | 2868 | return true;
|
---|
| 2869 |
|
---|
| 2870 | /*
|
---|
| 2871 | * Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not.
|
---|
| 2872 | */
|
---|
[91301] | 2873 | uint32_t const u32VmcsField = RT_LO_U32(u64VmcsField);
|
---|
| 2874 | uint8_t const * const pbBitmap = uExitReason == VMX_EXIT_VMREAD
|
---|
| 2875 | ? &pVCpu->cpum.s.Guest.hwvirt.vmx.abVmreadBitmap[0]
|
---|
| 2876 | : &pVCpu->cpum.s.Guest.hwvirt.vmx.abVmwriteBitmap[0];
|
---|
[78861] | 2877 | Assert(pbBitmap);
|
---|
[79316] | 2878 | Assert(u32VmcsField >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
|
---|
[96994] | 2879 | return ASMBitTest(pbBitmap, (u32VmcsField << 3) + (u32VmcsField & 7));
|
---|
[78861] | 2880 | }
|
---|
| 2881 |
|
---|
| 2882 |
|
---|
| 2883 |
|
---|
| 2884 | /**
|
---|
[78483] | 2885 | * Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
|
---|
[78371] | 2886 | *
|
---|
| 2887 | * @param pvIoBitmap Pointer to the nested-guest IO bitmap.
|
---|
| 2888 | * @param u16Port The IO port being accessed.
|
---|
| 2889 | * @param enmIoType The type of IO access.
|
---|
| 2890 | * @param cbReg The IO operand size in bytes.
|
---|
| 2891 | * @param cAddrSizeBits The address size bits (for 16, 32 or 64).
|
---|
| 2892 | * @param iEffSeg The effective segment number.
|
---|
| 2893 | * @param fRep Whether this is a repeating IO instruction (REP prefix).
|
---|
| 2894 | * @param fStrIo Whether this is a string IO instruction.
|
---|
| 2895 | * @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
|
---|
| 2896 | * Optional, can be NULL.
|
---|
| 2897 | */
|
---|
[78483] | 2898 | VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
|
---|
| 2899 | uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
|
---|
| 2900 | PSVMIOIOEXITINFO pIoExitInfo)
|
---|
[78371] | 2901 | {
|
---|
| 2902 | Assert(cAddrSizeBits == 16 || cAddrSizeBits == 32 || cAddrSizeBits == 64);
|
---|
| 2903 | Assert(cbReg == 1 || cbReg == 2 || cbReg == 4 || cbReg == 8);
|
---|
| 2904 |
|
---|
| 2905 | /*
|
---|
| 2906 | * The IOPM layout:
|
---|
| 2907 | * Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
|
---|
| 2908 | * two 4K pages.
|
---|
| 2909 | *
|
---|
| 2910 | * For IO instructions that access more than a single byte, the permission bits
|
---|
| 2911 | * for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
|
---|
| 2912 | *
|
---|
| 2913 | * Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
|
---|
| 2914 | * we need 3 extra bits beyond the second 4K page.
|
---|
| 2915 | */
|
---|
| 2916 | static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
|
---|
| 2917 |
|
---|
| 2918 | uint16_t const offIopm = u16Port >> 3;
|
---|
| 2919 | uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
|
---|
| 2920 | uint8_t const cShift = u16Port - (offIopm << 3);
|
---|
| 2921 | uint16_t const fIopmMask = (1 << cShift) | (fSizeMask << cShift);
|
---|
| 2922 |
|
---|
| 2923 | uint8_t const *pbIopm = (uint8_t *)pvIoBitmap;
|
---|
| 2924 | Assert(pbIopm);
|
---|
| 2925 | pbIopm += offIopm;
|
---|
| 2926 | uint16_t const u16Iopm = *(uint16_t *)pbIopm;
|
---|
| 2927 | if (u16Iopm & fIopmMask)
|
---|
| 2928 | {
|
---|
| 2929 | if (pIoExitInfo)
|
---|
| 2930 | {
|
---|
| 2931 | static const uint32_t s_auIoOpSize[] =
|
---|
| 2932 | { SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
|
---|
| 2933 |
|
---|
| 2934 | static const uint32_t s_auIoAddrSize[] =
|
---|
| 2935 | { 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
|
---|
| 2936 |
|
---|
| 2937 | pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
|
---|
| 2938 | pIoExitInfo->u |= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
|
---|
| 2939 | pIoExitInfo->n.u1Str = fStrIo;
|
---|
| 2940 | pIoExitInfo->n.u1Rep = fRep;
|
---|
| 2941 | pIoExitInfo->n.u3Seg = iEffSeg & 7;
|
---|
| 2942 | pIoExitInfo->n.u1Type = enmIoType;
|
---|
| 2943 | pIoExitInfo->n.u16Port = u16Port;
|
---|
| 2944 | }
|
---|
| 2945 | return true;
|
---|
| 2946 | }
|
---|
| 2947 |
|
---|
| 2948 | /** @todo remove later (for debugging as VirtualBox always traps all IO
|
---|
| 2949 | * intercepts). */
|
---|
| 2950 | AssertMsgFailed(("CPUMSvmIsIOInterceptActive: We expect an IO intercept here!\n"));
|
---|
| 2951 | return false;
|
---|
| 2952 | }
|
---|
| 2953 |
|
---|
| 2954 |
|
---|
| 2955 | /**
|
---|
| 2956 | * Gets the MSR permission bitmap byte and bit offset for the specified MSR.
|
---|
| 2957 | *
|
---|
| 2958 | * @returns VBox status code.
|
---|
| 2959 | * @param idMsr The MSR being requested.
|
---|
| 2960 | * @param pbOffMsrpm Where to store the byte offset in the MSR permission
|
---|
| 2961 | * bitmap for @a idMsr.
|
---|
| 2962 | * @param puMsrpmBit Where to store the bit offset starting at the byte
|
---|
| 2963 | * returned in @a pbOffMsrpm.
|
---|
| 2964 | */
|
---|
| 2965 | VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit)
|
---|
| 2966 | {
|
---|
| 2967 | Assert(pbOffMsrpm);
|
---|
| 2968 | Assert(puMsrpmBit);
|
---|
| 2969 |
|
---|
| 2970 | /*
|
---|
| 2971 | * MSRPM Layout:
|
---|
| 2972 | * Byte offset MSR range
|
---|
| 2973 | * 0x000 - 0x7ff 0x00000000 - 0x00001fff
|
---|
| 2974 | * 0x800 - 0xfff 0xc0000000 - 0xc0001fff
|
---|
| 2975 | * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
|
---|
| 2976 | * 0x1800 - 0x1fff Reserved
|
---|
| 2977 | *
|
---|
| 2978 | * Each MSR is represented by 2 permission bits (read and write).
|
---|
| 2979 | */
|
---|
| 2980 | if (idMsr <= 0x00001fff)
|
---|
| 2981 | {
|
---|
| 2982 | /* Pentium-compatible MSRs. */
|
---|
| 2983 | uint32_t const bitoffMsr = idMsr << 1;
|
---|
| 2984 | *pbOffMsrpm = bitoffMsr >> 3;
|
---|
| 2985 | *puMsrpmBit = bitoffMsr & 7;
|
---|
| 2986 | return VINF_SUCCESS;
|
---|
| 2987 | }
|
---|
| 2988 |
|
---|
| 2989 | if ( idMsr >= 0xc0000000
|
---|
| 2990 | && idMsr <= 0xc0001fff)
|
---|
| 2991 | {
|
---|
| 2992 | /* AMD Sixth Generation x86 Processor MSRs. */
|
---|
| 2993 | uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
|
---|
| 2994 | *pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
|
---|
| 2995 | *puMsrpmBit = bitoffMsr & 7;
|
---|
| 2996 | return VINF_SUCCESS;
|
---|
| 2997 | }
|
---|
| 2998 |
|
---|
| 2999 | if ( idMsr >= 0xc0010000
|
---|
| 3000 | && idMsr <= 0xc0011fff)
|
---|
| 3001 | {
|
---|
| 3002 | /* AMD Seventh and Eighth Generation Processor MSRs. */
|
---|
| 3003 | uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
|
---|
| 3004 | *pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
|
---|
| 3005 | *puMsrpmBit = bitoffMsr & 7;
|
---|
| 3006 | return VINF_SUCCESS;
|
---|
| 3007 | }
|
---|
| 3008 |
|
---|
| 3009 | *pbOffMsrpm = 0;
|
---|
| 3010 | *puMsrpmBit = 0;
|
---|
| 3011 | return VERR_OUT_OF_RANGE;
|
---|
| 3012 | }
|
---|
| 3013 |
|
---|
[91710] | 3014 |
|
---|
| 3015 | /**
|
---|
| 3016 | * Checks whether the guest is in VMX non-root mode and using EPT paging.
|
---|
| 3017 | *
|
---|
| 3018 | * @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
|
---|
| 3019 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 3020 | */
|
---|
| 3021 | VMM_INT_DECL(bool) CPUMIsGuestVmxEptPagingEnabled(PCVMCPUCC pVCpu)
|
---|
| 3022 | {
|
---|
[91951] | 3023 | return CPUMIsGuestVmxEptPagingEnabledEx(&pVCpu->cpum.s.Guest);
|
---|
[91710] | 3024 | }
|
---|
| 3025 |
|
---|
[92541] | 3026 |
|
---|
| 3027 | /**
|
---|
| 3028 | * Checks whether the guest is in VMX non-root mode and using EPT paging and the
|
---|
| 3029 | * nested-guest is in PAE mode.
|
---|
| 3030 | *
|
---|
| 3031 | * @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
|
---|
| 3032 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 3033 | */
|
---|
| 3034 | VMM_INT_DECL(bool) CPUMIsGuestVmxEptPaePagingEnabled(PCVMCPUCC pVCpu)
|
---|
| 3035 | {
|
---|
| 3036 | return CPUMIsGuestVmxEptPagingEnabledEx(&pVCpu->cpum.s.Guest)
|
---|
| 3037 | && CPUMIsGuestInPAEModeEx(&pVCpu->cpum.s.Guest);
|
---|
| 3038 | }
|
---|
| 3039 |
|
---|
[93922] | 3040 |
|
---|
| 3041 | /**
|
---|
| 3042 | * Returns the guest-physical address of the APIC-access page when executing a
|
---|
| 3043 | * nested-guest.
|
---|
| 3044 | *
|
---|
| 3045 | * @returns The APIC-access page guest-physical address.
|
---|
| 3046 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 3047 | */
|
---|
| 3048 | VMM_INT_DECL(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCVMCPUCC pVCpu)
|
---|
| 3049 | {
|
---|
| 3050 | return CPUMGetGuestVmxApicAccessPageAddrEx(&pVCpu->cpum.s.Guest);
|
---|
| 3051 | }
|
---|
| 3052 |
|
---|