VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp@ 96860

Last change on this file since 96860 was 96652, checked in by vboxsync, 21 months ago

VMM/IEM: Implement [v]pclmulqdq instruction, ​bugref:9898
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1/* $Id: CPUMAllCpuId.cpp 96652 2022-09-08 08:49:40Z vboxsync $ */
2/** @file
3 * CPUM - CPU ID part, common bits.
4 */
5
6/*
7 * Copyright (C) 2013-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_CPUM
33#include <VBox/vmm/cpum.h>
34#include <VBox/vmm/hm.h>
35#include <VBox/vmm/ssm.h>
36#include "CPUMInternal.h"
37#include <VBox/vmm/vmcc.h>
38#include <VBox/sup.h>
39
40#include <VBox/err.h>
41#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
42# include <iprt/asm-amd64-x86.h>
43#endif
44#include <iprt/ctype.h>
45#include <iprt/mem.h>
46#include <iprt/string.h>
47#include <iprt/x86-helpers.h>
48
49
50/*********************************************************************************************************************************
51* Global Variables *
52*********************************************************************************************************************************/
53/**
54 * The intel pentium family.
55 */
56static const CPUMMICROARCH g_aenmIntelFamily06[] =
57{
58 /* [ 0(0x00)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro A-step (says sandpile.org). */
59 /* [ 1(0x01)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro */
60 /* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
61 /* [ 3(0x03)] = */ kCpumMicroarch_Intel_P6_II, /* PII Klamath */
62 /* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
63 /* [ 5(0x05)] = */ kCpumMicroarch_Intel_P6_II, /* PII Deschutes */
64 /* [ 6(0x06)] = */ kCpumMicroarch_Intel_P6_II, /* Celeron Mendocino. */
65 /* [ 7(0x07)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Katmai. */
66 /* [ 8(0x08)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Coppermine (includes Celeron). */
67 /* [ 9(0x09)] = */ kCpumMicroarch_Intel_P6_M_Banias, /* Pentium/Celeron M Banias. */
68 /* [10(0x0a)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Xeon */
69 /* [11(0x0b)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Tualatin (includes Celeron). */
70 /* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
71 /* [13(0x0d)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Pentium/Celeron M Dothan. */
72 /* [14(0x0e)] = */ kCpumMicroarch_Intel_Core_Yonah, /* Core Yonah (Enhanced Pentium M). */
73 /* [15(0x0f)] = */ kCpumMicroarch_Intel_Core2_Merom, /* Merom */
74 /* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
75 /* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
76 /* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
77 /* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
78 /* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
79 /* [21(0x15)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Tolapai - System-on-a-chip. */
80 /* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
81 /* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82 /* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
83 /* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
84 /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Nehalem-EP */
85 /* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
86 /* [28(0x1c)] = */ kCpumMicroarch_Intel_Atom_Bonnell, /* Diamonville, Pineview, */
87 /* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
88 /* [30(0x1e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Clarksfield, Lynnfield, Jasper Forest. */
89 /* [31(0x1f)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
90 /* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
91 /* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
92 /* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
93 /* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
94 /* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
95 /* [37(0x25)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Arrandale, Clarksdale. */
96 /* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
97 /* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
98 /* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
99 /* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
100 /* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
101 /* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
102 /* [44(0x2c)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Gulftown, Westmere-EP. */
103 /* [45(0x2d)] = */ kCpumMicroarch_Intel_Core7_SandyBridge, /* SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
104 /* [46(0x2e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Beckton (Xeon). */
105 /* [47(0x2f)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Westmere-EX. */
106 /* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
107 /* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
108 /* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
109 /* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
110 /* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
111 /* [53(0x35)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* ?? */
112 /* [54(0x36)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* Cedarview, ++ */
113 /* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
114 /* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
115 /* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
116 /* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
117 /* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
118 /* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
119 /* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
120 /* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121 /* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122 /* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
123 /* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
124 /* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
125 /* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
126 /* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
127 /* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128 /* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129 /* [71(0x47)] = */ kCpumMicroarch_Intel_Core7_Broadwell, /* i7-5775C */
130 /* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
131 /* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
132 /* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
133 /* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
134 /* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
135 /* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
136 /* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
137 /* [79(0x4f)] = */ kCpumMicroarch_Intel_Core7_Broadwell, /* Broadwell-E */
138 /* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
139 /* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
140 /* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
141 /* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
142 /* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
143 /* [85(0x55)] = */ kCpumMicroarch_Intel_Core7_Skylake, /* server cpu; skylake <= 4, cascade lake > 5 */
144 /* [86(0x56)] = */ kCpumMicroarch_Intel_Core7_Broadwell, /* Xeon D-1540, Broadwell-DE */
145 /* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
146 /* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
147 /* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
148 /* [90(0x5a)] = */ kCpumMicroarch_Intel_Atom_Silvermont, /* Moorefield */
149 /* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
150 /* [92(0x5c)] = */ kCpumMicroarch_Intel_Atom_Goldmont, /* Apollo Lake */
151 /* [93(0x5d)] = */ kCpumMicroarch_Intel_Atom_Silvermont, /* x3-C3230 */
152 /* [94(0x5e)] = */ kCpumMicroarch_Intel_Core7_Skylake, /* i7-6700K */
153 /* [95(0x5f)] = */ kCpumMicroarch_Intel_Atom_Goldmont, /* Denverton */
154 /* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
155 /* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
156 /* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
157 /* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
158 /*[100(0x64)] = */ kCpumMicroarch_Intel_Unknown,
159 /*[101(0x65)] = */ kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
160 /*[102(0x66)] = */ kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
161 /*[103(0x67)] = */ kCpumMicroarch_Intel_Unknown,
162 /*[104(0x68)] = */ kCpumMicroarch_Intel_Unknown,
163 /*[105(0x69)] = */ kCpumMicroarch_Intel_Unknown,
164 /*[106(0x6a)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
165 /*[107(0x6b)] = */ kCpumMicroarch_Intel_Unknown,
166 /*[108(0x6c)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
167 /*[109(0x6d)] = */ kCpumMicroarch_Intel_Unknown,
168 /*[110(0x6e)] = */ kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
169 /*[111(0x6f)] = */ kCpumMicroarch_Intel_Unknown,
170 /*[112(0x70)] = */ kCpumMicroarch_Intel_Unknown,
171 /*[113(0x71)] = */ kCpumMicroarch_Intel_Unknown,
172 /*[114(0x72)] = */ kCpumMicroarch_Intel_Unknown,
173 /*[115(0x73)] = */ kCpumMicroarch_Intel_Unknown,
174 /*[116(0x74)] = */ kCpumMicroarch_Intel_Unknown,
175 /*[117(0x75)] = */ kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
176 /*[118(0x76)] = */ kCpumMicroarch_Intel_Unknown,
177 /*[119(0x77)] = */ kCpumMicroarch_Intel_Unknown,
178 /*[120(0x78)] = */ kCpumMicroarch_Intel_Unknown,
179 /*[121(0x79)] = */ kCpumMicroarch_Intel_Unknown,
180 /*[122(0x7a)] = */ kCpumMicroarch_Intel_Atom_GoldmontPlus,
181 /*[123(0x7b)] = */ kCpumMicroarch_Intel_Unknown,
182 /*[124(0x7c)] = */ kCpumMicroarch_Intel_Unknown,
183 /*[125(0x7d)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
184 /*[126(0x7e)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
185 /*[127(0x7f)] = */ kCpumMicroarch_Intel_Unknown,
186 /*[128(0x80)] = */ kCpumMicroarch_Intel_Unknown,
187 /*[129(0x81)] = */ kCpumMicroarch_Intel_Unknown,
188 /*[130(0x82)] = */ kCpumMicroarch_Intel_Unknown,
189 /*[131(0x83)] = */ kCpumMicroarch_Intel_Unknown,
190 /*[132(0x84)] = */ kCpumMicroarch_Intel_Unknown,
191 /*[133(0x85)] = */ kCpumMicroarch_Intel_Phi_KnightsMill,
192 /*[134(0x86)] = */ kCpumMicroarch_Intel_Unknown,
193 /*[135(0x87)] = */ kCpumMicroarch_Intel_Unknown,
194 /*[136(0x88)] = */ kCpumMicroarch_Intel_Unknown,
195 /*[137(0x89)] = */ kCpumMicroarch_Intel_Unknown,
196 /*[138(0x8a)] = */ kCpumMicroarch_Intel_Unknown,
197 /*[139(0x8b)] = */ kCpumMicroarch_Intel_Unknown,
198 /*[140(0x8c)] = */ kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
199 /*[141(0x8d)] = */ kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
200 /*[142(0x8e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
201 /*[143(0x8f)] = */ kCpumMicroarch_Intel_Core7_SapphireRapids,
202 /*[144(0x90)] = */ kCpumMicroarch_Intel_Unknown,
203 /*[145(0x91)] = */ kCpumMicroarch_Intel_Unknown,
204 /*[146(0x92)] = */ kCpumMicroarch_Intel_Unknown,
205 /*[147(0x93)] = */ kCpumMicroarch_Intel_Unknown,
206 /*[148(0x94)] = */ kCpumMicroarch_Intel_Unknown,
207 /*[149(0x95)] = */ kCpumMicroarch_Intel_Unknown,
208 /*[150(0x96)] = */ kCpumMicroarch_Intel_Unknown,
209 /*[151(0x97)] = */ kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
210 /*[152(0x98)] = */ kCpumMicroarch_Intel_Unknown,
211 /*[153(0x99)] = */ kCpumMicroarch_Intel_Unknown,
212 /*[154(0x9a)] = */ kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
213 /*[155(0x9b)] = */ kCpumMicroarch_Intel_Unknown,
214 /*[156(0x9c)] = */ kCpumMicroarch_Intel_Unknown,
215 /*[157(0x9d)] = */ kCpumMicroarch_Intel_Unknown,
216 /*[158(0x9e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
217 /*[159(0x9f)] = */ kCpumMicroarch_Intel_Unknown,
218 /*[160(0xa0)] = */ kCpumMicroarch_Intel_Unknown,
219 /*[161(0xa1)] = */ kCpumMicroarch_Intel_Unknown,
220 /*[162(0xa2)] = */ kCpumMicroarch_Intel_Unknown,
221 /*[163(0xa3)] = */ kCpumMicroarch_Intel_Unknown,
222 /*[164(0xa4)] = */ kCpumMicroarch_Intel_Unknown,
223 /*[165(0xa5)] = */ kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
224 /*[166(0xa6)] = */ kCpumMicroarch_Intel_Unknown,
225 /*[167(0xa7)] = */ kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
226};
227AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
228
229
230/**
231 * Figures out the (sub-)micro architecture given a bit of CPUID info.
232 *
233 * @returns Micro architecture.
234 * @param enmVendor The CPU vendor.
235 * @param bFamily The CPU family.
236 * @param bModel The CPU model.
237 * @param bStepping The CPU stepping.
238 */
239VMMDECL(CPUMMICROARCH) CPUMCpuIdDetermineX86MicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
240 uint8_t bModel, uint8_t bStepping)
241{
242 if (enmVendor == CPUMCPUVENDOR_AMD)
243 {
244 switch (bFamily)
245 {
246 case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
247 case 0x03: return kCpumMicroarch_AMD_Am386;
248 case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
249 case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
250 case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
251 case 0x06:
252 switch (bModel)
253 {
254 case 0: return kCpumMicroarch_AMD_K7_Palomino;
255 case 1: return kCpumMicroarch_AMD_K7_Palomino;
256 case 2: return kCpumMicroarch_AMD_K7_Palomino;
257 case 3: return kCpumMicroarch_AMD_K7_Spitfire;
258 case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
259 case 6: return kCpumMicroarch_AMD_K7_Palomino;
260 case 7: return kCpumMicroarch_AMD_K7_Morgan;
261 case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
262 case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
263 }
264 return kCpumMicroarch_AMD_K7_Unknown;
265 case 0x0f:
266 /*
267 * This family is a friggin mess. Trying my best to make some
268 * sense out of it. Too much happened in the 0x0f family to
269 * lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
270 *
271 * Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
272 * cpu-world.com, and other places:
273 * - 130nm:
274 * - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
275 * - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
276 * - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
277 * - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
278 * - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
279 * - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
280 * - 90nm:
281 * - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
282 * - Oakville: 10FC0/DH-D0.
283 * - Georgetown: 10FC0/DH-D0.
284 * - Sonora: 10FC0/DH-D0.
285 * - Venus: 20F71/SH-E4
286 * - Troy: 20F51/SH-E4
287 * - Athens: 20F51/SH-E4
288 * - San Diego: 20F71/SH-E4.
289 * - Lancaster: 20F42/SH-E5
290 * - Newark: 20F42/SH-E5.
291 * - Albany: 20FC2/DH-E6.
292 * - Roma: 20FC2/DH-E6.
293 * - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
294 * - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
295 * - 90nm introducing Dual core:
296 * - Denmark: 20F30/JH-E1, 20F32/JH-E6
297 * - Italy: 20F10/JH-E1, 20F12/JH-E6
298 * - Egypt: 20F10/JH-E1, 20F12/JH-E6
299 * - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
300 * - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
301 * - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
302 * - Santa Ana: 40F32/JH-F2, /-F3
303 * - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
304 * - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
305 * - Manila: 50FF2/DH-F2, 40FF2/DH-F2
306 * - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
307 * - Keene: 40FC2/DH-F2.
308 * - Richmond: 40FC2/DH-F2
309 * - Taylor: 40F82/BH-F2
310 * - Trinidad: 40F82/BH-F2
311 *
312 * - 65nm:
313 * - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
314 * - Tyler: 60F81/BH-G1, 60F82/BH-G2.
315 * - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
316 * - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
317 * - Sherman: /-G1, 70FC2/DH-G2.
318 * - Huron: 70FF2/DH-G2.
319 */
320 if (bModel < 0x10)
321 return kCpumMicroarch_AMD_K8_130nm;
322 if (bModel >= 0x60 && bModel < 0x80)
323 return kCpumMicroarch_AMD_K8_65nm;
324 if (bModel >= 0x40)
325 return kCpumMicroarch_AMD_K8_90nm_AMDV;
326 switch (bModel)
327 {
328 case 0x21:
329 case 0x23:
330 case 0x2b:
331 case 0x2f:
332 case 0x37:
333 case 0x3f:
334 return kCpumMicroarch_AMD_K8_90nm_DualCore;
335 }
336 return kCpumMicroarch_AMD_K8_90nm;
337 case 0x10:
338 return kCpumMicroarch_AMD_K10;
339 case 0x11:
340 return kCpumMicroarch_AMD_K10_Lion;
341 case 0x12:
342 return kCpumMicroarch_AMD_K10_Llano;
343 case 0x14:
344 return kCpumMicroarch_AMD_Bobcat;
345 case 0x15:
346 switch (bModel)
347 {
348 case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
349 case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
350 case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
351 case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
352 case 0x11: /* ?? */
353 case 0x12: /* ?? */
354 case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
355 }
356 return kCpumMicroarch_AMD_15h_Unknown;
357 case 0x16:
358 return kCpumMicroarch_AMD_Jaguar;
359 case 0x17:
360 return kCpumMicroarch_AMD_Zen_Ryzen;
361 }
362 return kCpumMicroarch_AMD_Unknown;
363 }
364
365 if (enmVendor == CPUMCPUVENDOR_INTEL)
366 {
367 switch (bFamily)
368 {
369 case 3:
370 return kCpumMicroarch_Intel_80386;
371 case 4:
372 return kCpumMicroarch_Intel_80486;
373 case 5:
374 return kCpumMicroarch_Intel_P5;
375 case 6:
376 if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
377 {
378 CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
379 if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
380 {
381 if (bStepping >= 0xa && bStepping <= 0xc)
382 enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
383 else if (bStepping >= 0xc)
384 enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
385 }
386 else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
387 && bModel == 0x55
388 && bStepping >= 5)
389 enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
390 return enmMicroArch;
391 }
392 return kCpumMicroarch_Intel_Atom_Unknown;
393 case 15:
394 switch (bModel)
395 {
396 case 0: return kCpumMicroarch_Intel_NB_Willamette;
397 case 1: return kCpumMicroarch_Intel_NB_Willamette;
398 case 2: return kCpumMicroarch_Intel_NB_Northwood;
399 case 3: return kCpumMicroarch_Intel_NB_Prescott;
400 case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
401 case 5: return kCpumMicroarch_Intel_NB_Unknown; /*??*/
402 case 6: return kCpumMicroarch_Intel_NB_CedarMill;
403 case 7: return kCpumMicroarch_Intel_NB_Gallatin;
404 default: return kCpumMicroarch_Intel_NB_Unknown;
405 }
406 break;
407 /* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
408 case 0:
409 return kCpumMicroarch_Intel_8086;
410 case 1:
411 return kCpumMicroarch_Intel_80186;
412 case 2:
413 return kCpumMicroarch_Intel_80286;
414 }
415 return kCpumMicroarch_Intel_Unknown;
416 }
417
418 if (enmVendor == CPUMCPUVENDOR_VIA)
419 {
420 switch (bFamily)
421 {
422 case 5:
423 switch (bModel)
424 {
425 case 1: return kCpumMicroarch_Centaur_C6;
426 case 4: return kCpumMicroarch_Centaur_C6;
427 case 8: return kCpumMicroarch_Centaur_C2;
428 case 9: return kCpumMicroarch_Centaur_C3;
429 }
430 break;
431
432 case 6:
433 switch (bModel)
434 {
435 case 5: return kCpumMicroarch_VIA_C3_M2;
436 case 6: return kCpumMicroarch_VIA_C3_C5A;
437 case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
438 case 8: return kCpumMicroarch_VIA_C3_C5N;
439 case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
440 case 10: return kCpumMicroarch_VIA_C7_C5J;
441 case 15: return kCpumMicroarch_VIA_Isaiah;
442 }
443 break;
444 }
445 return kCpumMicroarch_VIA_Unknown;
446 }
447
448 if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
449 {
450 switch (bFamily)
451 {
452 case 6:
453 case 7:
454 return kCpumMicroarch_Shanghai_Wudaokou;
455 default:
456 break;
457 }
458 return kCpumMicroarch_Shanghai_Unknown;
459 }
460
461 if (enmVendor == CPUMCPUVENDOR_CYRIX)
462 {
463 switch (bFamily)
464 {
465 case 4:
466 switch (bModel)
467 {
468 case 9: return kCpumMicroarch_Cyrix_5x86;
469 }
470 break;
471
472 case 5:
473 switch (bModel)
474 {
475 case 2: return kCpumMicroarch_Cyrix_M1;
476 case 4: return kCpumMicroarch_Cyrix_MediaGX;
477 case 5: return kCpumMicroarch_Cyrix_MediaGXm;
478 }
479 break;
480
481 case 6:
482 switch (bModel)
483 {
484 case 0: return kCpumMicroarch_Cyrix_M2;
485 }
486 break;
487
488 }
489 return kCpumMicroarch_Cyrix_Unknown;
490 }
491
492 if (enmVendor == CPUMCPUVENDOR_HYGON)
493 {
494 switch (bFamily)
495 {
496 case 0x18:
497 return kCpumMicroarch_Hygon_Dhyana;
498 default:
499 break;
500 }
501 return kCpumMicroarch_Hygon_Unknown;
502 }
503
504 return kCpumMicroarch_Unknown;
505}
506
507
508/**
509 * Translates a microarchitecture enum value to the corresponding string
510 * constant.
511 *
512 * @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
513 * NULL if the value is invalid.
514 *
515 * @param enmMicroarch The enum value to convert.
516 */
517VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch)
518{
519 switch (enmMicroarch)
520 {
521#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
522 CASE_RET_STR(kCpumMicroarch_Intel_8086);
523 CASE_RET_STR(kCpumMicroarch_Intel_80186);
524 CASE_RET_STR(kCpumMicroarch_Intel_80286);
525 CASE_RET_STR(kCpumMicroarch_Intel_80386);
526 CASE_RET_STR(kCpumMicroarch_Intel_80486);
527 CASE_RET_STR(kCpumMicroarch_Intel_P5);
528
529 CASE_RET_STR(kCpumMicroarch_Intel_P6);
530 CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
531 CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
532
533 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
534 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
535 CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
536
537 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
538 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
539
540 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
541 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
542 CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
543 CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
544 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
545 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
546 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
547 CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
548 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
549 CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
550 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
551 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
552 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
553 CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
554 CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
555 CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
556 CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
557 CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
558
559 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
560 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
561 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
562 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
563 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
564 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
565 CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
566 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
567
568 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
569 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
570 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
571 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
572 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
573
574 CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
575 CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
576 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
577 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
578 CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
579 CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
580 CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
581
582 CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
583
584 CASE_RET_STR(kCpumMicroarch_AMD_Am286);
585 CASE_RET_STR(kCpumMicroarch_AMD_Am386);
586 CASE_RET_STR(kCpumMicroarch_AMD_Am486);
587 CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
588 CASE_RET_STR(kCpumMicroarch_AMD_K5);
589 CASE_RET_STR(kCpumMicroarch_AMD_K6);
590
591 CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
592 CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
593 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
594 CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
595 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
596 CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
597 CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
598
599 CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
600 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
601 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
602 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
603 CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
604
605 CASE_RET_STR(kCpumMicroarch_AMD_K10);
606 CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
607 CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
608 CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
609 CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
610
611 CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
612 CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
613 CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
614 CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
615 CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
616
617 CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
618
619 CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
620
621 CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
622
623 CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
624 CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
625
626 CASE_RET_STR(kCpumMicroarch_Centaur_C6);
627 CASE_RET_STR(kCpumMicroarch_Centaur_C2);
628 CASE_RET_STR(kCpumMicroarch_Centaur_C3);
629 CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
630 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
631 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
632 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
633 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
634 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
635 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
636 CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
637 CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
638 CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
639
640 CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
641 CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
642
643 CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
644 CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
645 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
646 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
647 CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
648 CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
649
650 CASE_RET_STR(kCpumMicroarch_NEC_V20);
651 CASE_RET_STR(kCpumMicroarch_NEC_V30);
652
653 CASE_RET_STR(kCpumMicroarch_Unknown);
654
655#undef CASE_RET_STR
656 case kCpumMicroarch_Invalid:
657 case kCpumMicroarch_Intel_End:
658 case kCpumMicroarch_Intel_Core2_End:
659 case kCpumMicroarch_Intel_Core7_End:
660 case kCpumMicroarch_Intel_Atom_End:
661 case kCpumMicroarch_Intel_P6_Core_Atom_End:
662 case kCpumMicroarch_Intel_Phi_End:
663 case kCpumMicroarch_Intel_NB_End:
664 case kCpumMicroarch_AMD_K7_End:
665 case kCpumMicroarch_AMD_K8_End:
666 case kCpumMicroarch_AMD_15h_End:
667 case kCpumMicroarch_AMD_16h_End:
668 case kCpumMicroarch_AMD_Zen_End:
669 case kCpumMicroarch_AMD_End:
670 case kCpumMicroarch_Hygon_End:
671 case kCpumMicroarch_VIA_End:
672 case kCpumMicroarch_Shanghai_End:
673 case kCpumMicroarch_Cyrix_End:
674 case kCpumMicroarch_NEC_End:
675 case kCpumMicroarch_32BitHack:
676 break;
677 /* no default! */
678 }
679
680 return NULL;
681}
682
683
684/**
685 * Gets a matching leaf in the CPUID leaf array.
686 *
687 * @returns Pointer to the matching leaf, or NULL if not found.
688 * @param paLeaves The CPUID leaves to search. This is sorted.
689 * @param cLeaves The number of leaves in the array.
690 * @param uLeaf The leaf to locate.
691 * @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
692 */
693PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
694{
695 /* Lazy bird does linear lookup here since this is only used for the
696 occational CPUID overrides. */
697 for (uint32_t i = 0; i < cLeaves; i++)
698 if ( paLeaves[i].uLeaf == uLeaf
699 && paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
700 return &paLeaves[i];
701 return NULL;
702}
703
704
705/**
706 * Ensures that the CPUID leaf array can hold one more leaf.
707 *
708 * @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
709 * failure.
710 * @param pVM The cross context VM structure. If NULL, use
711 * the process heap, otherwise the VM's hyper heap.
712 * @param ppaLeaves Pointer to the variable holding the array pointer
713 * (input/output).
714 * @param cLeaves The current array size.
715 *
716 * @remarks This function will automatically update the R0 and RC pointers when
717 * using the hyper heap, which means @a ppaLeaves and @a cLeaves must
718 * be the corresponding VM's CPUID arrays (which is asserted).
719 */
720PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
721{
722 /*
723 * If pVM is not specified, we're on the regular heap and can waste a
724 * little space to speed things up.
725 */
726 uint32_t cAllocated;
727 if (!pVM)
728 {
729 cAllocated = RT_ALIGN(cLeaves, 16);
730 if (cLeaves + 1 > cAllocated)
731 {
732 void *pvNew = RTMemRealloc(*ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
733 if (pvNew)
734 *ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
735 else
736 {
737 RTMemFree(*ppaLeaves);
738 *ppaLeaves = NULL;
739 }
740 }
741 }
742 /*
743 * Otherwise, we're on the hyper heap and are probably just inserting
744 * one or two leaves and should conserve space.
745 */
746 else
747 {
748#ifdef IN_VBOX_CPU_REPORT
749 AssertReleaseFailed();
750#else
751# ifdef IN_RING3
752 Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
753 Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves);
754 Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
755
756 if (cLeaves + 1 <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves))
757 { }
758 else
759# endif
760 {
761 *ppaLeaves = NULL;
762 LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n"));
763 }
764#endif
765 }
766 return *ppaLeaves;
767}
768
769
770#ifdef VBOX_STRICT
771/**
772 * Checks that we've updated the CPUID leaves array correctly.
773 *
774 * This is a no-op in non-strict builds.
775 *
776 * @param paLeaves The leaves array.
777 * @param cLeaves The number of leaves.
778 */
779void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
780{
781 for (uint32_t i = 1; i < cLeaves; i++)
782 if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
783 AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
784 else
785 {
786 AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
787 ("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
788 AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
789 ("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
790 AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
791 ("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
792 }
793}
794#endif
795
796#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
797
798/**
799 * Append a CPUID leaf or sub-leaf.
800 *
801 * ASSUMES linear insertion order, so we'll won't need to do any searching or
802 * replace anything. Use cpumR3CpuIdInsert() for those cases.
803 *
804 * @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
805 * the caller need do no more work.
806 * @param ppaLeaves Pointer to the pointer to the array of sorted
807 * CPUID leaves and sub-leaves.
808 * @param pcLeaves Where we keep the leaf count for *ppaLeaves.
809 * @param uLeaf The leaf we're adding.
810 * @param uSubLeaf The sub-leaf number.
811 * @param fSubLeafMask The sub-leaf mask.
812 * @param uEax The EAX value.
813 * @param uEbx The EBX value.
814 * @param uEcx The ECX value.
815 * @param uEdx The EDX value.
816 * @param fFlags The flags.
817 */
818static int cpumCollectCpuIdInfoAddOne(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves,
819 uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
820 uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
821{
822 if (!cpumCpuIdEnsureSpace(NULL /* pVM */, ppaLeaves, *pcLeaves))
823 return VERR_NO_MEMORY;
824
825 PCPUMCPUIDLEAF pNew = &(*ppaLeaves)[*pcLeaves];
826 Assert( *pcLeaves == 0
827 || pNew[-1].uLeaf < uLeaf
828 || (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
829
830 pNew->uLeaf = uLeaf;
831 pNew->uSubLeaf = uSubLeaf;
832 pNew->fSubLeafMask = fSubLeafMask;
833 pNew->uEax = uEax;
834 pNew->uEbx = uEbx;
835 pNew->uEcx = uEcx;
836 pNew->uEdx = uEdx;
837 pNew->fFlags = fFlags;
838
839 *pcLeaves += 1;
840 return VINF_SUCCESS;
841}
842
843
844/**
845 * Checks if ECX make a difference when reading a given CPUID leaf.
846 *
847 * @returns @c true if it does, @c false if it doesn't.
848 * @param uLeaf The leaf we're reading.
849 * @param pcSubLeaves Number of sub-leaves accessible via ECX.
850 * @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
851 * final sub-leaf (for leaf 0xb only).
852 */
853static bool cpumIsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t *pcSubLeaves, bool *pfFinalEcxUnchanged)
854{
855 *pfFinalEcxUnchanged = false;
856
857 uint32_t auCur[4];
858 uint32_t auPrev[4];
859 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
860
861 /* Look for sub-leaves. */
862 uint32_t uSubLeaf = 1;
863 for (;;)
864 {
865 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
866 if (memcmp(auCur, auPrev, sizeof(auCur)))
867 break;
868
869 /* Advance / give up. */
870 uSubLeaf++;
871 if (uSubLeaf >= 64)
872 {
873 *pcSubLeaves = 1;
874 return false;
875 }
876 }
877
878 /* Count sub-leaves. */
879 uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
880 uint32_t cRepeats = 0;
881 uSubLeaf = 0;
882 for (;;)
883 {
884 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
885
886 /* Figuring out when to stop isn't entirely straight forward as we need
887 to cover undocumented behavior up to a point and implementation shortcuts. */
888
889 /* 1. Look for more than 4 repeating value sets. */
890 if ( auCur[0] == auPrev[0]
891 && auCur[1] == auPrev[1]
892 && ( auCur[2] == auPrev[2]
893 || ( auCur[2] == uSubLeaf
894 && auPrev[2] == uSubLeaf - 1) )
895 && auCur[3] == auPrev[3])
896 {
897 if ( uLeaf != 0xd
898 || uSubLeaf >= 64
899 || ( auCur[0] == 0
900 && auCur[1] == 0
901 && auCur[2] == 0
902 && auCur[3] == 0
903 && auPrev[2] == 0) )
904 cRepeats++;
905 if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
906 break;
907 }
908 else
909 cRepeats = 0;
910
911 /* 2. Look for zero values. */
912 if ( auCur[0] == 0
913 && auCur[1] == 0
914 && (auCur[2] == 0 || auCur[2] == uSubLeaf)
915 && (auCur[3] == 0 || uLeaf == 0xb /* edx is fixed */)
916 && uSubLeaf >= cMinLeaves)
917 {
918 cRepeats = 0;
919 break;
920 }
921
922 /* 3. Leaf 0xb level type 0 check. */
923 if ( uLeaf == 0xb
924 && (auCur[2] & 0xff00) == 0
925 && (auPrev[2] & 0xff00) == 0)
926 {
927 cRepeats = 0;
928 break;
929 }
930
931 /* 99. Give up. */
932 if (uSubLeaf >= 128)
933 {
934# ifndef IN_VBOX_CPU_REPORT
935 /* Ok, limit it according to the documentation if possible just to
936 avoid annoying users with these detection issues. */
937 uint32_t cDocLimit = UINT32_MAX;
938 if (uLeaf == 0x4)
939 cDocLimit = 4;
940 else if (uLeaf == 0x7)
941 cDocLimit = 1;
942 else if (uLeaf == 0xd)
943 cDocLimit = 63;
944 else if (uLeaf == 0xf)
945 cDocLimit = 2;
946 if (cDocLimit != UINT32_MAX)
947 {
948 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
949 *pcSubLeaves = cDocLimit + 3;
950 return true;
951 }
952# endif
953 *pcSubLeaves = UINT32_MAX;
954 return true;
955 }
956
957 /* Advance. */
958 uSubLeaf++;
959 memcpy(auPrev, auCur, sizeof(auCur));
960 }
961
962 /* Standard exit. */
963 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
964 *pcSubLeaves = uSubLeaf + 1 - cRepeats;
965 if (*pcSubLeaves == 0)
966 *pcSubLeaves = 1;
967 return true;
968}
969
970
971/**
972 * Collects CPUID leaves and sub-leaves, returning a sorted array of them.
973 *
974 * @returns VBox status code.
975 * @param ppaLeaves Where to return the array pointer on success.
976 * Use RTMemFree to release.
977 * @param pcLeaves Where to return the size of the array on
978 * success.
979 */
980VMMDECL(int) CPUMCpuIdCollectLeavesX86(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
981{
982 *ppaLeaves = NULL;
983 *pcLeaves = 0;
984
985 /*
986 * Try out various candidates. This must be sorted!
987 */
988 static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
989 {
990 { UINT32_C(0x00000000), false },
991 { UINT32_C(0x10000000), false },
992 { UINT32_C(0x20000000), false },
993 { UINT32_C(0x30000000), false },
994 { UINT32_C(0x40000000), false },
995 { UINT32_C(0x50000000), false },
996 { UINT32_C(0x60000000), false },
997 { UINT32_C(0x70000000), false },
998 { UINT32_C(0x80000000), false },
999 { UINT32_C(0x80860000), false },
1000 { UINT32_C(0x8ffffffe), true },
1001 { UINT32_C(0x8fffffff), true },
1002 { UINT32_C(0x90000000), false },
1003 { UINT32_C(0xa0000000), false },
1004 { UINT32_C(0xb0000000), false },
1005 { UINT32_C(0xc0000000), false },
1006 { UINT32_C(0xd0000000), false },
1007 { UINT32_C(0xe0000000), false },
1008 { UINT32_C(0xf0000000), false },
1009 };
1010
1011 for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1012 {
1013 uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1014 uint32_t uEax, uEbx, uEcx, uEdx;
1015 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1016
1017 /*
1018 * Does EAX look like a typical leaf count value?
1019 */
1020 if ( uEax > uLeaf
1021 && uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1022 {
1023 /* Yes, dump them. */
1024 uint32_t cLeaves = uEax - uLeaf + 1;
1025 while (cLeaves-- > 0)
1026 {
1027 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1028
1029 uint32_t fFlags = 0;
1030
1031 /* There are currently three known leaves containing an APIC ID
1032 that needs EMT specific attention */
1033 if (uLeaf == 1)
1034 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1035 else if (uLeaf == 0xb && uEcx != 0)
1036 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1037 else if ( uLeaf == UINT32_C(0x8000001e)
1038 && ( uEax
1039 || uEbx
1040 || uEdx
1041 || RTX86IsAmdCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1042 || RTX86IsHygonCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1043 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1044
1045 /* The APIC bit is per-VCpu and needs flagging. */
1046 if (uLeaf == 1)
1047 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1048 else if ( uLeaf == UINT32_C(0x80000001)
1049 && ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1050 || RTX86IsAmdCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1051 || RTX86IsHygonCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1052 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1053
1054 /* Check three times here to reduce the chance of CPU migration
1055 resulting in false positives with things like the APIC ID. */
1056 uint32_t cSubLeaves;
1057 bool fFinalEcxUnchanged;
1058 if ( cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1059 && cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1060 && cpumIsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1061 {
1062 if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1063 {
1064 /* This shouldn't happen. But in case it does, file all
1065 relevant details in the release log. */
1066 LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1067 LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1068 for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1069 {
1070 uint32_t auTmp[4];
1071 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1072 LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1073 uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1074 }
1075 LogRel(("----------------- dump of what we've found so far -----------------\n"));
1076 for (uint32_t i = 0 ; i < *pcLeaves; i++)
1077 LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1078 (*ppaLeaves)[i].uLeaf, (*ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1079 (*ppaLeaves)[i].uEax, (*ppaLeaves)[i].uEbx, (*ppaLeaves)[i].uEcx, (*ppaLeaves)[i].uEdx));
1080 LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1081 return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1082 }
1083
1084 if (fFinalEcxUnchanged)
1085 fFlags |= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1086
1087 for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1088 {
1089 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1090 int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1091 uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1092 if (RT_FAILURE(rc))
1093 return rc;
1094 }
1095 }
1096 else
1097 {
1098 int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves, uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1099 if (RT_FAILURE(rc))
1100 return rc;
1101 }
1102
1103 /* next */
1104 uLeaf++;
1105 }
1106 }
1107 /*
1108 * Special CPUIDs needs special handling as they don't follow the
1109 * leaf count principle used above.
1110 */
1111 else if (s_aCandidates[iOuter].fSpecial)
1112 {
1113 bool fKeep = false;
1114 if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1115 fKeep = true;
1116 else if ( uLeaf == 0x8fffffff
1117 && RT_C_IS_PRINT(RT_BYTE1(uEax))
1118 && RT_C_IS_PRINT(RT_BYTE2(uEax))
1119 && RT_C_IS_PRINT(RT_BYTE3(uEax))
1120 && RT_C_IS_PRINT(RT_BYTE4(uEax))
1121 && RT_C_IS_PRINT(RT_BYTE1(uEbx))
1122 && RT_C_IS_PRINT(RT_BYTE2(uEbx))
1123 && RT_C_IS_PRINT(RT_BYTE3(uEbx))
1124 && RT_C_IS_PRINT(RT_BYTE4(uEbx))
1125 && RT_C_IS_PRINT(RT_BYTE1(uEcx))
1126 && RT_C_IS_PRINT(RT_BYTE2(uEcx))
1127 && RT_C_IS_PRINT(RT_BYTE3(uEcx))
1128 && RT_C_IS_PRINT(RT_BYTE4(uEcx))
1129 && RT_C_IS_PRINT(RT_BYTE1(uEdx))
1130 && RT_C_IS_PRINT(RT_BYTE2(uEdx))
1131 && RT_C_IS_PRINT(RT_BYTE3(uEdx))
1132 && RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1133 fKeep = true;
1134 if (fKeep)
1135 {
1136 int rc = cpumCollectCpuIdInfoAddOne(ppaLeaves, pcLeaves, uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1137 if (RT_FAILURE(rc))
1138 return rc;
1139 }
1140 }
1141 }
1142
1143# ifdef VBOX_STRICT
1144 cpumCpuIdAssertOrder(*ppaLeaves, *pcLeaves);
1145# endif
1146 return VINF_SUCCESS;
1147}
1148#endif /* RT_ARCH_X86 || RT_ARCH_AMD64 */
1149
1150
1151/**
1152 * Detect the CPU vendor give n the
1153 *
1154 * @returns The vendor.
1155 * @param uEAX EAX from CPUID(0).
1156 * @param uEBX EBX from CPUID(0).
1157 * @param uECX ECX from CPUID(0).
1158 * @param uEDX EDX from CPUID(0).
1159 */
1160VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1161{
1162 if (RTX86IsValidStdRange(uEAX))
1163 {
1164 if (RTX86IsAmdCpu(uEBX, uECX, uEDX))
1165 return CPUMCPUVENDOR_AMD;
1166
1167 if (RTX86IsIntelCpu(uEBX, uECX, uEDX))
1168 return CPUMCPUVENDOR_INTEL;
1169
1170 if (RTX86IsViaCentaurCpu(uEBX, uECX, uEDX))
1171 return CPUMCPUVENDOR_VIA;
1172
1173 if (RTX86IsShanghaiCpu(uEBX, uECX, uEDX))
1174 return CPUMCPUVENDOR_SHANGHAI;
1175
1176 if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1177 && uECX == UINT32_C(0x64616574)
1178 && uEDX == UINT32_C(0x736E4978))
1179 return CPUMCPUVENDOR_CYRIX;
1180
1181 if (RTX86IsHygonCpu(uEBX, uECX, uEDX))
1182 return CPUMCPUVENDOR_HYGON;
1183
1184 /* "Geode by NSC", example: family 5, model 9. */
1185
1186 /** @todo detect the other buggers... */
1187 }
1188
1189 return CPUMCPUVENDOR_UNKNOWN;
1190}
1191
1192
1193/**
1194 * Translates a CPU vendor enum value into the corresponding string constant.
1195 *
1196 * The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1197 * value name. This can be useful when generating code.
1198 *
1199 * @returns Read only name string.
1200 * @param enmVendor The CPU vendor value.
1201 */
1202VMMDECL(const char *) CPUMCpuVendorName(CPUMCPUVENDOR enmVendor)
1203{
1204 switch (enmVendor)
1205 {
1206 case CPUMCPUVENDOR_INTEL: return "INTEL";
1207 case CPUMCPUVENDOR_AMD: return "AMD";
1208 case CPUMCPUVENDOR_VIA: return "VIA";
1209 case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1210 case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1211 case CPUMCPUVENDOR_HYGON: return "HYGON";
1212 case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1213
1214 case CPUMCPUVENDOR_INVALID:
1215 case CPUMCPUVENDOR_32BIT_HACK:
1216 break;
1217 }
1218 return "Invalid-cpu-vendor";
1219}
1220
1221
1222static PCCPUMCPUIDLEAF cpumCpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1223{
1224 /* Could do binary search, doing linear now because I'm lazy. */
1225 PCCPUMCPUIDLEAF pLeaf = paLeaves;
1226 while (cLeaves-- > 0)
1227 {
1228 if (pLeaf->uLeaf == uLeaf)
1229 return pLeaf;
1230 pLeaf++;
1231 }
1232 return NULL;
1233}
1234
1235
1236static PCCPUMCPUIDLEAF cpumCpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1237{
1238 PCCPUMCPUIDLEAF pLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1239 if ( !pLeaf
1240 || pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1241 return pLeaf;
1242
1243 /* Linear sub-leaf search. Lazy as usual. */
1244 cLeaves -= pLeaf - paLeaves;
1245 while ( cLeaves-- > 0
1246 && pLeaf->uLeaf == uLeaf)
1247 {
1248 if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1249 return pLeaf;
1250 pLeaf++;
1251 }
1252
1253 return NULL;
1254}
1255
1256
1257static void cpumExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1258{
1259 Assert(pVmxMsrs);
1260 Assert(pFeatures);
1261 Assert(pFeatures->fVmx);
1262
1263 /* Basic information. */
1264 bool const fVmxTrueMsrs = RT_BOOL(pVmxMsrs->u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
1265 {
1266 uint64_t const u64Basic = pVmxMsrs->u64Basic;
1267 pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1268 }
1269
1270 /* Pin-based VM-execution controls. */
1271 {
1272 uint32_t const fPinCtls = fVmxTrueMsrs ? pVmxMsrs->TruePinCtls.n.allowed1 : pVmxMsrs->PinCtls.n.allowed1;
1273 pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1274 pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1275 pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1276 pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1277 pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1278 }
1279
1280 /* Processor-based VM-execution controls. */
1281 {
1282 uint32_t const fProcCtls = fVmxTrueMsrs ? pVmxMsrs->TrueProcCtls.n.allowed1 : pVmxMsrs->ProcCtls.n.allowed1;
1283 pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1284 pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1285 pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1286 pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1287 pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1288 pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1289 pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1290 pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1291 pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1292 pFeatures->fVmxTertiaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1293 pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1294 pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1295 pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1296 pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1297 pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1298 pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1299 pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1300 pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1301 pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1302 pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1303 pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1304 pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1305 }
1306
1307 /* Secondary processor-based VM-execution controls. */
1308 {
1309 uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1310 pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1311 pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1312 pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1313 pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1314 pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1315 pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1316 pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1317 pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1318 pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1319 pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1320 pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1321 pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1322 pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1323 pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1324 pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1325 pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1326 pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1327 pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE);
1328 pFeatures->fVmxConcealVmxFromPt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1329 pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1330 pFeatures->fVmxModeBasedExecuteEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1331 pFeatures->fVmxSppEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_SPP_EPT);
1332 pFeatures->fVmxPtEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PT_EPT);
1333 pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1334 pFeatures->fVmxUserWaitPause = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1335 pFeatures->fVmxEnclvExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_ENCLV_EXIT);
1336 }
1337
1338 /* Tertiary processor-based VM-execution controls. */
1339 {
1340 uint64_t const fProcCtls3 = pFeatures->fVmxTertiaryExecCtls ? pVmxMsrs->u64ProcCtls3 : 0;
1341 pFeatures->fVmxLoadIwKeyExit = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT);
1342 }
1343
1344 /* VM-exit controls. */
1345 {
1346 uint32_t const fExitCtls = fVmxTrueMsrs ? pVmxMsrs->TrueExitCtls.n.allowed1 : pVmxMsrs->ExitCtls.n.allowed1;
1347 pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1348 pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1349 pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1350 pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1351 pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1352 pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1353 pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1354 pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1355 }
1356
1357 /* VM-entry controls. */
1358 {
1359 uint32_t const fEntryCtls = fVmxTrueMsrs ? pVmxMsrs->TrueEntryCtls.n.allowed1 : pVmxMsrs->EntryCtls.n.allowed1;
1360 pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1361 pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1362 pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1363 pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1364 }
1365
1366 /* Miscellaneous data. */
1367 {
1368 uint32_t const fMiscData = pVmxMsrs->u64Misc;
1369 pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1370 pFeatures->fVmxPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1371 pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1372 pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1373 }
1374}
1375
1376
1377int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1378{
1379 Assert(pMsrs);
1380 RT_ZERO(*pFeatures);
1381 if (cLeaves >= 2)
1382 {
1383 AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1384 AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1385 PCCPUMCPUIDLEAF const pStd0Leaf = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1386 AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1387 PCCPUMCPUIDLEAF const pStd1Leaf = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1388 AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1389
1390 pFeatures->enmCpuVendor = CPUMCpuIdDetectX86VendorEx(pStd0Leaf->uEax,
1391 pStd0Leaf->uEbx,
1392 pStd0Leaf->uEcx,
1393 pStd0Leaf->uEdx);
1394 pFeatures->uFamily = RTX86GetCpuFamily(pStd1Leaf->uEax);
1395 pFeatures->uModel = RTX86GetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1396 pFeatures->uStepping = RTX86GetCpuStepping(pStd1Leaf->uEax);
1397 pFeatures->enmMicroarch = CPUMCpuIdDetermineX86MicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1398 pFeatures->uFamily,
1399 pFeatures->uModel,
1400 pFeatures->uStepping);
1401
1402 PCCPUMCPUIDLEAF const pExtLeaf8 = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1403 if (pExtLeaf8)
1404 {
1405 pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1406 pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1407 }
1408 else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1409 {
1410 pFeatures->cMaxPhysAddrWidth = 36;
1411 pFeatures->cMaxLinearAddrWidth = 36;
1412 }
1413 else
1414 {
1415 pFeatures->cMaxPhysAddrWidth = 32;
1416 pFeatures->cMaxLinearAddrWidth = 32;
1417 }
1418
1419 /* Standard features. */
1420 pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1421 pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1422 pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1423 pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1424 pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1425 pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1426 pFeatures->fPge = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PGE);
1427 pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1428 pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1429 pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1430 pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1431 pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1432 pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1433 pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1434 pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1435 pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1436 pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1437 pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1438 pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1439 pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1440 pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1441 pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1442 pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1443 pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1444 pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1445 pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1446 pFeatures->fPopCnt = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_POPCNT);
1447 pFeatures->fRdRand = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_RDRAND);
1448 pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1449 pFeatures->fPclMul = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCLMUL);
1450 if (pFeatures->fVmx)
1451 cpumExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1452
1453 /* Structured extended features. */
1454 PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1455 if (pSxfLeaf0)
1456 {
1457 pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1458 pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1459 pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1460 pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1461 pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1462 pFeatures->fBmi1 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI1);
1463 pFeatures->fBmi2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1464 pFeatures->fRdSeed = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_RDSEED);
1465
1466 pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1467 pFeatures->fIbrs = pFeatures->fIbpb;
1468 pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1469 pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1470 pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1471 pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1472 }
1473
1474 /* MWAIT/MONITOR leaf. */
1475 PCCPUMCPUIDLEAF const pMWaitLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 5);
1476 if (pMWaitLeaf)
1477 pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1478 == (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1479
1480 /* Extended features. */
1481 PCCPUMCPUIDLEAF const pExtLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1482 if (pExtLeaf)
1483 {
1484 pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1485 pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1486 pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1487 pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1488 pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1489 pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1490 pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1491 pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1492 || (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1493 | X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1494 pFeatures->fAbm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_ABM);
1495 }
1496
1497 /* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1498 pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1499
1500 if ( pExtLeaf
1501 && ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1502 || pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
1503 {
1504 /* AMD features. */
1505 pFeatures->fMsr |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1506 pFeatures->fApic |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1507 pFeatures->fPse |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1508 pFeatures->fPse36 |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1509 pFeatures->fPae |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1510 pFeatures->fPge |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PGE);
1511 pFeatures->fPat |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1512 pFeatures->fFxSaveRstor |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1513 pFeatures->fMmx |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1514 pFeatures->fTsc |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1515 pFeatures->fIbpb |= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1516 pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1517 pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1518 pFeatures->fTbm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_TBM);
1519 pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1520 if (pFeatures->fSvm)
1521 {
1522 PCCPUMCPUIDLEAF pSvmLeaf = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1523 AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1524 pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1525 pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1526 pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1527 pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1528 pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1529 pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1530 pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1531 pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1532 pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1533 pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1534 pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1535 pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1536 pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1537 pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
1538 pFeatures->fSvmSSSCheck = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SSSCHECK);
1539 pFeatures->fSvmSpecCtrl = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL);
1540 pFeatures->fSvmHostMceOverride = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE);
1541 pFeatures->fSvmTlbiCtl = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TLBICTL);
1542 pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1543 }
1544 }
1545
1546 /*
1547 * Quirks.
1548 */
1549 pFeatures->fLeakyFxSR = pExtLeaf
1550 && (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1551 && ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1552 && pFeatures->uFamily >= 6 /* K7 and up */)
1553 || pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
1554
1555 /*
1556 * Max extended (/FPU) state.
1557 */
1558 pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1559 if (pFeatures->fXSaveRstor)
1560 {
1561 PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1562 if (pXStateLeaf0)
1563 {
1564 if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1565 && pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1566 && RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1567 && pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1568 && pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1569 && RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1570 {
1571 pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1572
1573 /* (paranoia:) */
1574 PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1575 if ( pXStateLeaf1
1576 && pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1577 && pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1578 && (pXStateLeaf1->uEcx || pXStateLeaf1->uEdx) )
1579 pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1580 }
1581 else
1582 AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1583 pFeatures->fXSaveRstor = 0);
1584 }
1585 else
1586 AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1587 pFeatures->fXSaveRstor = 0);
1588 }
1589 }
1590 else
1591 AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1592 return VINF_SUCCESS;
1593}
1594
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